AD9223ARS-REEL_技术文档

Complete 12-Bit 1.5/3.0/10.0 MSPS

Monolithic A/D Converters

a

AD9221/AD9223/AD9220

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Monolithic 12-Bit A/D Converter Product Family

Family Members Are: AD9221, AD9223, and AD9220

Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS and

10.0 MSPS

Low Power Dissipation: 59 mW, 100 mW and 250 mW

Single +5 V Supply

AVDD

DVDD

CLK

SHA

VINA

VINB

MDAC1

GAIN = 16

MDAC2

GAIN = 8

MDAC3

GAIN = 4

5

4

3

A/D

Integral Nonlinearity Error: 0.5 LSB

Differential Nonlinearity Error: 0.3 LSB

Input Referred Noise: 0.09 LSB

Complete: On-Chip Sample-and-Hold Amplifier and

Voltage Reference

Signal-to-Noise and Distortion Ratio: 70 dB

Spurious-Free Dynamic Range: 86 dB

Out-of-Range Indicator

CAPT

CAPB

5

4

3

DIGITAL CORRECTION LOGIC

12

VREF

OUTPUT BUFFERS

OTR

SENSE

BIT 1

(MSB)

1V

MODE

SELECT

BIT 12

(LSB)

AD9221/AD9223/AD9220

REFCOM

CML

AVSS

DVSS

Straight Binary Output Data

28-Lead SOIC and 28-Lead SSOP

PRODUCT DESCRIPTION

suited for communication systems employing Direct-IF Down

Conversion since the SHA in the differential input mode can

achieve excellent dynamic performance far beyond its specified

Nyquist frequency.²

The AD9221, AD9223, and AD9220 are a generation of high

performance, single supply 12-bit analog-to-digital converters.

Each device exhibits true 12-bit linearity and temperature drift

performance¹as well as 11.5 bit or better ac performance.²The

AD9221/AD9223/AD9220 share the same interface options,

package, and pinout. Thus, the product family provides an

upward or downward component selection path based on per-

formance, sample rate and power. The devices differ with re-

spect to their specified sampling rate and power consumption

which is reflected in their dynamic performance over frequency.

A single clock input is used to control all internal conversion

cycles. The digital output data is presented in straight binary

output format. An out-of-range (OTR) signal indicates an

overflow condition which can be used with the most significant

bit to determine low or high overflow.

PRODUCT HIGHLIGHTS

The AD9221/AD9223/AD9220 family offers a complete single-

chip sampling 12-bit, analog-to-digital conversion function in

pin-compatible 28-lead SOIC and SSOP packages.

The AD9221/AD9223/AD9220 combine a low cost, high speed

CMOS process and a novel architecture to achieve the resolution

and speed of existing hybrid and monolithic implementations at

a fraction of the power consumption and cost. Each device is a

complete, monolithic ADC with an on-chip, high performance,

low noise sample-and-hold amplifier and programmable voltage

reference. An external reference can also be chosen to suit the dc

accuracy and temperature drift requirements of the application.

The devices use a multistage differential pipelined architecture with

digital output error correction logic to provide 12-bit accuracy at

the specified data rates and to guarantee no missing codes over the

full operating temperature range.

Flexible Sampling Rates—The AD9221, AD9223 and AD9220

offer sampling rates of 1.5 MSPS, 3.0 MSPS and 10.0 MSPS,

respectively.

Low Power and Single Supply—The AD9221, AD9223 and

AD9220 consume only 59 mW, 100 mW and 250 mW, respec-

tively, on a single +5 V power supply.

Excellent DC Performance Over Temperature—The AD9221/

AD9223/AD9220 provide 12-bit linearity and temperature drift

performance.¹

The input of the AD9221/AD9223/AD9220 is highly flexible,

allowing for easy interfacing to imaging, communications, medi-

cal, and data-acquisition systems. A truly differential input

structure allows for both single-ended and differential input

interfaces of varying input spans. The sample-and-hold (SHA)

amplifier is equally suited for both multiplexed systems that

switch full-scale voltage levels in successive channels as well as

sampling single-channel inputs at frequencies up to and beyond

the Nyquist rate. Also, the AD9221/AD9223/AD9220 is well

Excellent AC Performance and Low Noise—The AD9221/

AD9223/AD9220 provides better than 11.3 ENOB performance

and has an input referred noise of 0.09 LSB rms.²

Flexible Analog Input Range—The versatile onboard sample-

and-hold (SHA) can be configured for either single ended or differ-

ential inputs of varying input spans.

NOTES

¹Excluding internal voltage reference.

²Depends on the analog input configuration.

REV. D

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD9221/AD9223/AD9220–SPECIFICATIONS

(AVDD = +5 V, DVDD = +5 V, f_SAMPLE= Max Conversion Rate, V_REF= 2.5 V, VINB = 2.5 V, T_MINto T_MAXunless

DC SPECIFICATIONS otherwise noted)

Parameter

AD9221

12

AD9223

AD9220

12

Units

RESOLUTION

12

3

Bits min

MHz min

MAX CONVERSION RATE

INPUT REFERRED NOISE (TYP)

1.5

10

V

_REF= 1 V

0.23

0.09

0.23

0.09

0.23

0.09

LSB rms typ

V_REF= 2.5 V

ACCURACY

Integral Nonlinearity (INL)

±0.4

±1.25

±0.3

±0.75

±0.6

±0.3

12

±0.3

±1.5

±0.75

±0.5

±1.25

±0.3

±0.75

±0.6

±0.3

12

±0.3

±1.5

±0.75

±0.5

±1.25

±0.3

±0.75

±0.7

±0.35

12

±0.3

±1.5

±0.75

LSB typ

LSB max

LSB typ

LSB max

LSB typ

Bits Guaranteed

% FSR max

Differential Nonlinearity (DNL)

INL¹

DNL¹

No Missing Codes

Zero Error (@ +25°C)

Gain Error (@ +25°C)²

Gain Error (@ +25°C)³

TEMPERATURE DRIFT

Zero Error

±2

±26

±0.4

±2

±26

±0.4

±2

±26

±0.4

ppm/°C typ

Gain Error²

Gain Error³

POWER SUPPLY REJECTION

AVDD_,DVDD (+5 V ± 0.25 V)

±0.06

% FSR max

ANALOG INPUT

Input Span (with V_REF= 1.0 V)

Input Span (with V_REF= 2.5 V)

Input (VINA or VINB) Range

2

5

0

2

5

0

2

5

0

V p-p min

V p-p max

V min

AVDD

16

AVDD

16

AVDD

16

V max

pF typ

Input Capacitance

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode)

Output Voltage Tolerance (1 V Mode)

Output Voltage (2.5 V Mode)

Output Voltage Tolerance (2.5 V Mode)

Load Regulation⁴

1

Volts typ

mV max

Volts typ

mV max

±14

2.5

±35

2.0

±14

2.5

±35

2.0

±14

2.5

±35

2.0

REFERENCE INPUT RESISTANCE

5

kΩ typ

POWER SUPPLIES

Supply Voltages

AVDD

+5

+5 (±5%)

V (±5% AVDD Operating)

V

DVDD

+2.7 to +5.25 +2.7 to +5.25

Supply Current

IAVDD

14.0

11.8

0.5

26

20

0.5

0.02

58

48

12

10

mA max

mA typ

mA max

mA typ

IDVDD

0.02

POWER CONSUMPTION

59.0

70.0

100

130

250

310

mW typ

mW max

NOTES

¹V_REF=1 V.

²Including internal reference.

³Excluding internal reference.

⁴Load regulation with 1 mA load current (in addition to that required by the AD9220/AD9221/AD9223).

Specification subject to change without notice.

–2–

REV. D

AD9221/AD9223/AD9220

(AVDD = +5 V, DVDD= +5 V, f_SAMPLE= Max Conversion Rate, V_REF= 1.0 V, VINB = 2.5 V, DC Coupled/Single-

AC SPECIFICATIONS Ended Input T_MINto T_MAXunless otherwise noted)

Parameters

AD9221

AD9223

AD9220

Units

MAX CONVERSION RATE

1.5

3.0

10.0

MHz min

DYNAMIC PERFORMANCE

Input Test Frequency 1 (VINA = –0.5 dBFS)

Signal-to-Noise and Distortion (SINAD)

100

70.0

69.0

11.3

11.2

70.2

69.0

–83.4

–77.5

86.0

79.0

0.50

69.9

69.0

11.3

11.2

70.1

69.0

–83.4

–77.5

86.0

79.0

25

500

70.0

68.5

11.3

11.1

70.0

68.5

–83.4

–76.0

87.5

77.5

1.50

69.4

68.0

11.2

11.1

69.7

68.5

–82.9

–75.0

85.7

76.0

40

1000

70

kHz

dB typ

dB min

dB typ

dB min

dB typ

dB min

dB typ

dB max

dB typ

dB max

MHz

dB typ

dB min

dB typ

dB min

dB typ

dB min

dB typ

dB max

dB typ

dB max

MHz typ

ns typ

68.5

11.3

11.1

70.2

69.0

–83.7

–76.0

88.0

77.5

5.0

67.0

65.0

10.8

10.5

68.8

67.5

–72.0

–68.0

75.0

69.0

60

Effective Number of Bits (ENOBs)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Spurious Free Dynamic Range (SFDR)

Input Test Frequency 2 (VINA = –0.5 dBFS)

Signal-to-Noise and Distortion (SINAD)

Effective Number of Bits (ENOBs)

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Spurious Free Dynamic Range (SFDR)

Full Power Bandwidth

Small Signal Bandwidth

Aperture Delay

25

1

40

1

60

1

Aperture Jitter

Acquisition to Full-Scale Step

4

125

4

43

4

30

ps rms typ

ns typ

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS (AVDD = +5 V, DVDD= +5 V, T_MINto T_MAXunless otherwise noted)

Parameters

Symbol

Units

CLOCK INPUT

High Level Input Voltage

Low Level Input Voltage

High Level Input Current (V_IN= DVDD)

Low Level Input Current (V_IN= 0 V)

Input Capacitance

V_IH

V_IL

I_IH

I_IL

C_IN

+3.5

+1.0

±10

5

V min

V max

µA max

pF typ

LOGIC OUTPUTS

DVDD = 5 V

High Level Output Voltage (I_OH= 50 µA)

High Level Output Voltage (I_OH= 0.5 mA)

Low Level Output Voltage (I_OL= 1.6 mA)

Low Level Output Voltage (I_OL= 50 µA)

DVDD = 3 V

V_OH

V_OL

+4.5

+2.4

+0.4

+0.1

V min

V max

High Level Output Voltage (I_OH= 50 µA)

High Level Output Voltage (I_OH= 0.5 mA)

Low Level Output Voltage (I_OL= 1.6 mA)

Low Level Output Voltage (I_OL= 50 µA)

Output Capacitance

V_OH

V_OL

C_OUT

+2.95

+2.80

+0.4

+0.05

5

V min

V max

pF typ

Specifications subject to change without notice.

–3–

REV. D

AD9221/AD9223/AD9220

SWITCHING SPECIFICATIONS

(T_MINto T_MAXwith AVDD = +5 V, DVDD = +5 V, C_L= 20 pF)

Parameters

Symbol

AD9221

AD9223

AD9220

Units

Clock Period¹

CLOCK Pulsewidth High

CLOCK Pulsewidth Low

Output Delay

t_C

667

300

8

333

150

8

100

45

8

ns min

t_CH

t_CL

t_OD

13

19

3

13

19

3

13

19

3

ns typ

ns max

Clock Cycles

Pipeline Delay (Latency)

NOTES

¹The clock period may be extended to 1 ms without degradation in specified performance @ +25°C.

Specifications subject to change without notice.

S1

S2

ANALOG

INPUT

S4

t_C

S3

t_CH

t_CL

INPUT

CLOCK

t_OD

DATA

OUTPUT

DATA 1

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS*

THERMAL CHARACTERISTICS

Thermal Resistance

28-Lead SOIC

θ_JA= 71.4°C/W

θ_JC= 23°C/W

28-Lead SSOP

θ_JA= 63.3°C/W

θ_JC= 23°C/W

With

Respect

to

Parameter

Min Max

Units

AVDD

DVDD

AVSS

DVSS

–0.3 +6.5

–0.3 +0.3

V

AVDD

DVDD –6.5 +6.5

REFCOM

CLK

Digital Outputs

VINA, VINB

VREF

AVSS

DVSS

AVSS

–0.3 +0.3

V

°C

ORDERING GUIDE

–0.3 AVDD + 0.3

–0.3 DVDD + 0.3

–0.3 AVDD + 0.3

+150

Temperature

Range

Package

Description

Package

Options

Model

AD9221AR

AD9223AR

AD9220AR

AD9221ARS

AD9223ARS

AD9220ARS

–40°C to +85°C

28-Lead SOIC R-28

28-Lead SSOP RS-28

SENSE

CAPB, CAPT

Junction Temperature

Storage Temperature

Lead Temperature

(10 sec)

–65

+150

+300

°C

AD9220/AD9221/AD9223SOICEB Evaluation Board

AD9220/AD9221/AD9223SSOPEB Evaluation Board

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum

ratings for extended periods may effect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although these devices feature proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. D

AD9221/AD9223/AD9220

PIN CONNECTIONS

ZERO ERROR

The major carry transition should occur for an analog value

1/2 LSB below VINA = VINB. Zero error is defined as the

deviation of the actual transition from that point.

DVDD

DVSS

CLK

(LSB) BIT 12

BIT 11

1

2

28

27

GAIN ERROR

3

26 AVDD

The first code transition should occur at an analog value

1/2 LSB above negative full scale. The last transition should

occur at an analog value 1 1/2 LSB below the nominal full

scale. Gain error is the deviation of the actual difference

between first and last code transitions and the ideal differ-

ence between first and last code transitions.

BIT 10

AVSS

25

4

AD9221/

AD9223/

AD9220

BIT 9

VINB

24

5

BIT 8

6

23

VINA

BIT 7

7

CML

22

21

20

19

18

17

16

15

TOP VIEW

(Not to Scale)

8

BIT 6

BIT 5

BIT 4

CAPT

9

CAPB

10

11

12

13

14

REFCOM

VREF

TEMPERATURE DRIFT

The temperature drift for zero error and gain error specifies the

maximum change from the initial (+25°C) value to the value at

BIT 3

BIT 2

SENSE

(MSB) BIT 1

OTR

AVSS

AVDD

T_MINor T_MAX

.

POWER SUPPLY REJECTION

The specification shows the maximum change in full scale from

the value with the supply at the minimum limit to the value

with the supply at its maximum limit.

PIN FUNCTION DESCRIPTIONS

Number Name

APERTURE JITTER

Aperture jitter is the variation in aperture delay for successive

samples and is manifested as noise on the input to the A/D.

Description

1

CLK

Clock Input Pin

2

3–12

13

BIT 12

BIT N

BIT 1

OTR

AVDD

AVSS

SENSE

VREF

Least Significant Data Bit (LSB)

Data Output Bit

Most Significant Data Bit (MSB)

Out of Range

+5 V Analog Supply

Analog Ground

Reference Select

APERTURE DELAY

Aperture delay is a measure of the sample-and-hold amplifier

(SHA) performance and is measured from the rising edge of the

clock input to when the input signal is held for conversion.

14

15, 26

16, 25

17

18

19

20

21

22

23

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)

RATIO

S/N+D is the ratio of the rms value of the measured input sig-

nal to the rms sum of all other spectral components below the

Nyquist frequency, including harmonics but excluding dc.

The value for S/N+D is expressed in decibels.

Reference I/O

REFCOM Reference Common

CAPB

CAPT

CML

VINA

VINB

DVSS

DVDD

Noise Reduction Pin

Common-Mode Level (Midsupply)

Analog Input Pin (+)

Analog Input Pin (–)

EFFECTIVE NUMBER OF BITS (ENOB)

For a sine wave, SINAD can be expressed in terms of the num-

ber of bits. Using the following formula,

24

27

28

Digital Ground

+3 V to +5 V Digital Supply

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N,

the effective number of bits.

Thus, effective number of bits for a device for sine wave inputs

at a given input frequency can be calculated directly from its

measured SINAD.

DEFINITIONS OF SPECIFICATION

INTEGRAL NONLINEARITY (INL)

INL refers to the deviation of each individual code from a line

drawn from “negative full scale” through “positive full scale.”

The point used as “negative full scale” occurs 1/2 LSB before

the first code transition. “Positive full scale” is defined as a

level 1 1/2 LSB beyond the last code transition. The deviation

is measured from the middle of each particular code to the true

straight line.

TOTAL HARMONIC DISTORTION (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal and

is expressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)

SNR is the ratio of the rms value of the measured input signal

to the rms sum of all other spectral components below the

Nyquist frequency, excluding the first six harmonics and dc.

The value for SNR is expressed in decibels.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSING

CODES)

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Guaranteed

no missing codes to 12-bit resolution indicates that all 4096

codes, respectively, must be present over all operating ranges.

SPURIOUS FREE DYNAMIC RANGE (SFDR)

SFDR is the difference in dB between the rms amplitude of the

input signal and the peak spurious signal.

–5–

REV. D

AD9221/AD9223/AD9220

(AVDD = +5 V, DVDD = +5 V, f_SAMPLE= 1.5 MSPS, T_A= +25؇C)

AD9221–Typical Characterization Curves

1.0

8,180,388

0.8

0.6

0.4

0.6

0.4

0.2

0.0

0.2

0.0

–0.2

–0.4

–0.6

–0.2

–0.4

–0.6

–0.8

–1.0

121,764

85,895

N+1

–0.8

–1.0

N–1

N

0

4095

0

4095

CODE

Figure 2. Typical DNL

Figure 3. Typical INL

Figure 4. “Grounded-Input”

Histogram (Input Span = 2 V p-p)

80

75

70

65

60

55

50

–50

–55

–60

–65

–70

80

75

–0.5dB

–20.0dB

–0.5dB

–6.0dB

70

65

–6.0dB

–0.5dB

–75

–80

60

55

50

–20.0dB

–85

–90

45

40

–95

45

40

–100

0.1

1.0

0.1

1.0

0.1

1.0

FREQUENCY – MHz

Figure 5. SINAD vs. Input Frequency

(Input Span = 2.0 V p-p, V_CM= 2.5 V)

Figure 6. THD vs. Input Frequency

(Input Span = 2.0 V p-p, V_CM= 2.5 V)

Figure 7. SINAD vs. Input Frequency

(Input Span = 5.0 V p-p, V_CM= 2.5 V)

–60

–65

–70

–75

–50

–55

100

90

–20.0dB

80

70

–60

–65

SFDR

60

–0.5dB

–80

–70

5V p-p

50

–85

–75

SNR

2V p-p

40

–6.0dB

–90

–80

30

20

–95

–85

–90

–100

10

–60

0.1

1.0

0

0.2 0.3 0.4

0.6 0.8

1

2

3

–50

–40

–30

–20

–10

FREQUENCY – MHz

A

– dBFS

SAMPLE RATE – MSPS

IN

Figure 8. THD vs. Input Frequency

(Input Span = 5.0 V p-p, V_CM= 2.5 V)

Figure 9. THD vs. Sample Rate

(A_IN= –0.5 dB, f_IN= 500 kHz,

Figure 10. SNR/SFDR vs. A_IN(Input

Amplitude) (f_IN= 500 kHz, Input Span

= 2 V p-p, V_CM= 2.5 V)

V_CM= 2.5 V)

–6–

REV. D

AD9221/AD9223/AD9220

(AVDD = +5 V, DVDD = +5 V, f_SAMPLE= 3.0 MSPS, T_A= +25؇C)

AD9223–Typical Characterization Curves

1.0

0.8

8,123,672

0.8

0.6

0.4

0.6

0.4

0.2

0.0

0.2

0.0

–0.2

–0.4

–0.6

–0.2

–0.4

–0.6

–0.8

–1.0

130,323

96,830

–0.8

–1.0

N–1

N

N+1

0

4095

0

4095

CODE

Figure 11. Typical DNL

Figure 12. Typical INL

Figure 13. “Grounded-Input”

Histogram (Input Span = 2 V p-p)

80

75

70

65

60

55

50

–50

–55

80

75

–0.5dB

–6.0dB

–60

–65

–70

–20.0dB

–0.5dB

70

–6.0dB

65

60

55

50

–75

–80

–85

–90

–6.0dB

–20.0dB

45

40

45

40

–95

–100

0.1

1.0

10.0

0.1

1.0

FREQUENCY – MHz

10.0

0.1

1.0

10.0

FREQUENCY – MHz

Figure 14. SINAD vs. Input Frequency

(Input Span = 2.0 V p-p, V_CM= 2.5 V)

Figure 15. THD vs. Input Frequency

(Input Span = 2.0 V p-p, V_CM= 2.5 V)

Figure 16. SINAD vs. Input Frequency

(Input Span = 5.0 V p-p, V_CM= 2.5 V)

–50

–55

100

90

–60

–65

–60

80

–70

–75

–65

–20.0dB

70

SFDR

–70

60

5V p-p

–75

–80

–6.0dB

50

–80

SNR

–85

2V p-p

–0.5dB

40

–85

–90

–95

30

–90

–95

20

10

–100

0.1

–100

–60 –50

–40

–30

–20

–10

1.0

10.0

0.4

0.6 0.8

1

2

3

4

5 6

0

A

– dBFS

FREQUENCY – MHz

SAMPLE RATE – MSPS

IN

Figure 17. THD vs. Input Frequency

(Input Span = 5.0 V p-p, V_CM= 2.5 V)

Figure 19. SNR/SFDR vs. A_IN(Input

Amplitude) (f_IN= 1.5 MHz, Input

Span = 2 V p-p, V_CM= 2.5 V)

Figure 18. THD vs. Sample Rate (A_IN

= –0.5 dB, f_IN= 500 kHz, V_CM= 2.5 V)

–7–

REV. D

AD9221/AD9223/AD9220

(AVDD = +5 V, DVDD = +5 V, f_SAMPLE= 10 MSPS, T_A= +25؇C)

AD9220–Typical Characterization Curves

1.0

0.8

1.0

0.8

8,123,672

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

130,323

N+1

134,613

–0.8

–1.0

1

4095

1

4095

N–1

N

CODE

Figure 22. “Grounded-Input”

Histogram (Input Span = 2 V p-p)

Figure 20. Typical DNL

Figure 21. Typical INL

–50

–55

–60

–65

–70

–75

–80

–85

–90

80

75

70

65

60

55

50

80

75

–0.5dB

–6dB

–0.5dB

70

–6.0dB

–20dB

–6dB

65

60

–20.0dB

55

50

–20dB

–0.5dB

45

40

45

40

–95

–100

0.1

1.0

10.0

0.5

1.0

10.0

0.1

1.0

10.0

FREQUENCY – MHz

Figure 24. THD vs. Input Frequency

(Input Span = 2.0 V p-p, V_CM= 2.5 V)

Figure 25. SINAD vs. Input Fre-

quency (Input Span = 5.0 V p-p,

Figure 23. SINAD vs. Input Fre-

quency (Input Span = 2.0 V p-p,

V_CM= 2.5 V)

90

80

70

–50

–60

–65

–55

–60

–65

–70

–75

–80

SFDR

5V p-p

–70

–20.0dB

60

50

–75

2V p-p

SNR

–0.5dB

–80

–85

–90

–6.0dB

40

30

20

10

–85

–90

–95

–100

0

–60

–50

–40

–30

–20

–10

0.1

1.0

FREQUENCY – MHz

10.0

1

10

15

A

– dBFS

IN

SAMPLE RATE – MSPS

Figure 28. SNR/SFDR vs. A_IN(Input

Amplitude) (f_IN= 5.0 MHz, Input

Span = 2 V p-p, V_CM= 2.5 V)

Figure 26. THD vs. Input Frequency

(Input Span = 5.0 V p-p, V_CM= 2.5 V)

Figure 27. THD vs. Clock Frequency

(A_IN= –0.5 dB, f_IN= 1.0 MHz, V_CM

2.5 V)

=

–8–

REV. D

AD9221/AD9223/AD9220

INTRODUCTION

and interface options. As a result, many of the application issues

and tradeoffs associated with these resulting configurations are

also similar. The data sheet is structured such that the designer

can make an informed decision in selecting the proper A/D and

optimizing its performance to fit the specific application.

The AD9221/AD9223/AD9220 are members of a high perfor-

mance, complete single-supply 12-bit ADC product family based

on the same CMOS pipelined architecture. The product family

allows the system designer an upward or downward component

selection path based on dynamic performance, sample rate, and

power. The analog input range of the AD9221/AD9223/AD9220

is highly flexible allowing for both single-ended or differential

inputs of varying amplitudes which can be ac or dc coupled.

Each device shares the same interface options, pinout and pack-

age offering.

0

AD9220

AD9223

–3

–6

The AD9221/AD9223/AD9220 utilize a four-stage pipeline

architecture with a wideband input sample-and-hold amplifier

(SHA) implemented on a cost-effective CMOS process. Each

stage of the pipeline, excluding the last stage, consists of a low

resolution flash A/D connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

amplifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each of the stages to facilitate digital

correction of flash errors. The last stage simply consists of a

flash A/D.

AD9221

–9

–12

1

10

FREQUENCY – MHz

100

Figure 29. Full-Power Bandwidth

The pipeline architecture allows a greater throughput rate at the

expense of pipeline delay or latency. This means that while the

converter is capable of capturing a new input sample every clock

cycle, it actually takes three clock cycles for the conversion to be

fully processed and appear at the output. This latency is not a

concern in most applications. The digital output, together with

the out-of-range indicator (OTR), is latched into an output

buffer to drive the output pins. The output drivers of the

AD9220ARS, AD9221 and AD9223 can be configured to

interface with +5 V or +3.3 V logic families, while the AD9220AR

can only be configured for +5 V logic.

4000

3000

2000

AD9220

AD9221

AD9223

1000

0

The AD9221/AD9223/AD9220 use both edges of the clock in

their internal timing circuitry (see Figure 1 and specification

page for exact timing requirements). The A/D samples the ana-

log input on the rising edge of the clock input. During the clock

low time (between the falling edge and rising edge of the clock),

the input SHA is in the sample mode; during the clock high

time it is in hold. System disturbances just prior to the rising

edge of the clock and/or excessive clock jitter may cause the

input SHA to acquire the wrong value, and should be minimized.

0

10

20

30

40

50

60

SETTLING TIME – ns

Figure 30. Settling Time

ANALOG INPUT AND REFERENCE OVERVIEW

Figure 31, a simplified model of the AD9221/AD9223/AD9220,

highlights the relationship between the analog inputs, VINA,

VINB, and the reference voltage, VREF. Like the voltage

applied to the top of the resistor ladder in a flash A/D converter,

the value VREF defines the maximum input voltage to the A/D

core. The minimum input voltage to the A/D core is automatically

defined to be –VREF.

The internal circuitry of both the input SHA and individual

pipeline stages of each member of the product family are opti-

mized for both power dissipation and performance. An inherent

tradeoff exists between the input SHA’s dynamic performance

and its power dissipation. Figures 29 and 30 shows this tradeoff

by comparing the full-power bandwidth and settling time of the

AD9221/AD9223/AD9220. Both figures reveal that higher

full-power bandwidths and faster settling times are achieved at

the expense of an increase in power dissipation. Similarly, a

tradeoff exists between the sampling rate and the power dissipated

in each stage.

AD9221/AD9223/AD9220

+V

VINA

REF

12

V

CORE

A/D

CORE

As previously stated, the AD9220, AD9221 and AD9223 are

similar in most aspects except for the specified sampling rate,

power consumption, and dynamic performance. The product

family is highly flexible providing several different input ranges

–V

VINB

REF

Figure 31. AD9221/AD9223/AD9220 Equivalent Functional

Input Circuit

–9–

REV. D

AD9221/AD9223/AD9220

The addition of a differential input structure gives the user an

additional level of flexibility that is not possible with traditional

flash converters. The input stage allows the user to easily con-

figure the inputs for either single-ended operation or differential

operation. The A/D’s input structure allows the dc offset of the

input signal to be varied independently of the input span of the

converter. Specifically, the input to the A/D core is the differ-

ence of the voltages applied at the VINA and VINB input pins.

Therefore, the equation,

The SHA’s optimum distortion performance for a differential or

single-ended input is achieved under the following two condi-

tions: (1) the common-mode voltage is centered around mid

supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input

signal voltage span of the SHA is set at its lowest (i.e., 2 V input

span). This is due to the sampling switches, Q_S1, being CMOS

switches whose R_ONresistance is very low but has some signal

dependency which causes frequency dependent ac distortion

while the SHA is in the track mode. The R_ONresistance of a

CMOS switch is typically lowest at its midsupply but increases

symmetrically as the input signal approaches either AVDD or

AVSS. A lower input signal voltage span centered at midsupply

reduces the degree of R_ONmodulation.

V_CORE= VINA – VINB

(1)

defines the output of the differential input stage and provides

the input to the A/D core.

The voltage, V_CORE, must satisfy the condition,

Figure 32a compares the AD9221/AD9223/AD9220’s THD vs.

frequency performance for a 2 V input span with a common-

mode voltage of 1 V and 2.5 V. Note how each A/D with a

common-mode voltage of 1 V exhibits a similar degradation in

THD performance at higher frequencies (i.e., beyond 750 kHz).

Similarly, note how the THD performance at lower frequencies

becomes less sensitive to the common-mode voltage. As the

input frequency approaches dc, the distortion will be domi-

nated by static nonlinearities such as INL and DNL. It is

important to note that these dc static nonlinearities are inde-

pendent of any R_ONmodulation.

–VREF ≤ V_CORE≤ VREF

(2)

where VREF is the voltage at the VREF pin.

While an infinite combination of VINA and VINB inputs exist

that satisfy Equation 2, there is an additional limitation placed

on the inputs by the power supply voltages of the AD9221/

AD9223/AD9220. The power supplies bound the valid operat-

ing range for VINA and VINB. The condition,

AVSS – 0.3 V < VINA < AVDD + 0.3 V

AVSS – 0.3 V < VINB < AVDD + 0.3 V

(3)

where AVSS is nominally 0 V and AVDD is nominally +5 V,

defines this requirement. Thus, the range of valid inputs for

VINA and VINB is any combination that satisfies both Equa-

tions 2 and 3.

–50

AD9220

1V

CM

–60

For additional information showing the relationship between

VINA, VINB, VREF and the digital output of the AD9221/

AD9223/AD9220, see Table IV.

AD9223

1V

AD9221

CM

1V

–70

–80

–90

Refer to Table I and Table II at the end of this section for a

summary of both the various analog input and reference

configurations.

AD9223

2.5V

CM

AD9220

ANALOG INPUT OPERATION

AD9221

2.5V

CM

Figure 32 shows the equivalent analog input of the AD9221/

AD9223/AD9220 which consists of a differential sample-and-

hold amplifier (SHA). The differential input structure of the

SHA is highly flexible, allowing the devices to be easily config-

ured for either a differential or single-ended input. The dc

offset, or common-mode voltage, of the input(s) can be set to

accommodate either single-supply or dual supply systems. Also,

note that the analog inputs, VINA and VINB, are interchange-

able with the exception that reversing the inputs to the VINA

and VINB pins results in a polarity inversion.

0.1

1

10

FREQUENCY – MHz

Figure 32a. AD9221/AD9223/AD9220 THD vs. Frequency for

_CM= 2.5 V and 1.0 V (A_IN= –0.5 dB, Input Span = 2.0 V p-p)

V

Due to the high degree of symmetry within the SHA topology, a

significant improvement in distortion performance for differen-

tial input signals with frequencies up to and beyond Nyquist can

be realized. This inherent symmetry provides excellent cancella-

tion of both common-mode distortion and noise. Also, the

required input signal voltage span is reduced by a half which

further reduces the degree of R_ONmodulation and its effects on

distortion.

C

H

Q

S2

+

C

PAR

C

Q

S

S1

The optimum noise and dc linearity performance for either differ-

ential or single-ended inputs is achieved with the largest input

signal voltage span (i.e., 5 V input span) and matched input

impedance for VINA and VINB. Note that only a slight degra-

dation in dc linearity performance exists between the 2 V and

5 V input span as specified in the AD9221/AD9223/AD9220

DC SPECIFICATIONS.

VINA

VINB

Q

C

Q

H1

S

S1

–

C

PAR

Q

S2

C

H

Figure 32. AD9221/AD9223/AD9220 Simplified Input Circuit

–10–

REV. D

AD9221/AD9223/AD9220

Referring to Figure 32, the differential SHA is implemented

using a switched-capacitor topology. Hence, its input imped-

ance and its subsequent effects on the input drive source should

be understood to maximize the converter’s performance. The

combination of the pin capacitance, C_PIN, parasitic capacitance

C_PAR,and the sampling capacitance, C_S, is typically less than

16 pF. When the SHA goes into track mode, the input source

must charge or discharge the voltage stored on C_Sto the new

input voltage. This action of charging and discharging C_S,

averaged over a period of time and for a given sampling fre-

quency, F_S, makes the input impedance appear to have a benign

resistive component. However, if this action is analyzed within

a sampling period (i.e., T = 1/F_S), the input impedance is dy-

namic and hence certain precautions on the input drive source

should be observed.

applications may require a larger resistor value to reduce the

noise bandwidth or possibly limit the fault current in an over-

voltage condition. Other applications may require a larger

resistor value as part of an antialiasing filter. In any case, since

the THD performance is dependent on the series resistance

and the above mentioned factors, optimizing this resistor value

for a given application is encouraged.

A slight improvement in SNR performance and dc offset

performance is achieved by matching the input resistance of

VINA and VINB. The degree of improvement is dependent on

the resistor value and the sampling rate. For series resistor

values greater than 100 Ω, the use of a matching resistor is

encouraged.

Figure 34 shows a plot for THD performance vs. R_SERIESfor

the AD9221/AD9223/AD9220 at their respective sampling rate

and Nyquist frequency. The Nyquist frequency typically repre-

sents the worst case scenario for an ADC. In this case, a high

speed, high performance amplifier (AD8047) was used as the

buffer op amp. Although not shown, the AD9221/AD9223/

AD9220 exhibits a slight increase in SNR (i.e. 1 dB to 1.5 dB)

as the resistance is increased from 0 kΩ to 2.56 kΩ due to its

bandlimiting effect on wideband noise. Conversely, it exhibits

slight decrease in SNR (i.e., 0.5 dB to 2 dB) if VINA and

VINB do not have a matched input resistance.

The resistive component to the input impedance can be com-

puted by calculating the average charge that gets drawn by C_H

from the input drive source. It can be shown that if C_Sis al-

lowed to fully charge up to the input voltage before switches Q_S1

are opened, then the average current into the input is the same

as if there were a resistor of 1/(C_SF_S) ohms connected between

the inputs. This means that the input impedance is inversely

proportional to the converter’s sample rate. Since C_Sis only

4 pF, this resistive component is typically much larger than that

of the drive source (i.e., 25 kΩ at F_S= 10 MSPS).

–45

If one considers the SHA’s input impedance over a sampling

period, it appears as a dynamic input impedance to the input

drive source. When the SHA goes into the track mode, the

input source should ideally provide the charging current through

–55

AD9223

R

_ONof switch Q_S1in an exponential manner. The requirement

of exponential charging means that the most common input

source, an op amp, must exhibit a source impedance that is both

low and resistive up to and beyond the sampling frequency.

–65

AD9220

The output impedance of an op amp can be modeled with a

series inductor and resistor. When a capacitive load is switched

onto the output of the op amp, the output will momentarily

drop due to its effective output impedance. As the output re-

covers, ringing may occur. To remedy the situation, a series

resistor can be inserted between the op amp and the SHA input

as shown in Figure 33. The series resistance helps isolate the op

amp from the switched-capacitor load.

–75

AD9221

–85

1

10

100

1k

10k

R

– ⍀

SERIES

Figure 34. THD vs. R_SERIES(f_IN= F_S/2, A_IN= –0.5 dB, Input

Span = 2 V p-p, V_CM= 2.5 V)

V

Figure 34 shows that a small R_SERIESbetween 30 Ω and 50 Ω

provides the optimum THD performance for the AD9220.

Lower values of R_SERIESare acceptable for the AD9223 and

AD9221 as their lower sampling rates provide a longer transient

recovery period for the AD8047. Note that op amps with lower

bandwidths will typically have a longer transient recovery

period and hence require a slightly higher value of R_SERIES

and/or lower sampling rate to achieve the optimum THD

performance.

CC

AD9221/AD9223/

AD9220

VINA

R

S

R

S

VINB

V

EE

VREF

10␮F

0.1␮F

SENSE

REFCOM

As the value of R_SERIESincreases, a corresponding increase in

distortion is noted. This is due to its interaction with the SHA’s

parasitic capacitor, C_PAR,which has a signal dependency. Hence,

the resulting R-C time constant is signal dependent and conse-

quently a source of distortion.

Figure 33. Series Resistor Isolates Switched-Capacitor

SHA Input from Op Amp. Matching Resistors Improve

SNR Performance

The optimum size of this resistor is dependent on several factors

which include the AD9221/AD9223/AD9220 sampling rate,

the selected op amp, and the particular application. In most

applications, a 30 Ω to 50 Ω resistor is sufficient. However, some

The noise or small-signal bandwidth of the AD9221/AD9223/

AD9220 is the same as their full-power bandwidth as shown in

–11–

REV. D

AD9221/AD9223/AD9220

other comparator controls internal circuitry which will disable

the reference amplifier if the SENSE pin is tied AVDD. Dis-

abling the reference amplifier allows the VREF pin to be driven

by an external voltage reference.

Figure 29. For noise sensitive applications, the excessive band-

width may be detrimental and the addition of a series resistor

and/or shunt capacitor can help limit the wideband noise at the

A/D’s input by forming a low-pass filter. Note, however, that

the combination of this series resistance with the equivalent

input capacitance of the AD9221/AD9223/AD9220 should be

evaluated for those time-domain applications that are sensitive

to the input signal’s absolute settling time. In applications where

harmonic distortion is not a primary concern, the series resis-

tance may be selected in combination with the SHA’s nominal

16 pF of input capacitance to set the filter’s 3 dB cutoff frequency.

AD9221/AD9223/AD9220

TO

A/D

5k⍀

CAPT

5k⍀

A2

5k⍀

CAPB

5k⍀

LOGIC

A better method of reducing the noise bandwidth, while possi-

bly establishing a real pole for an antialiasing filter, is to add

some additional shunt capacitance between the input (i.e.,

VINA and/or VINB) and analog ground. Since this additional

shunt capacitance combines with the equivalent input capaci-

tance of the AD9221/AD9223/AD9220, a lower series resis-

tance can be selected to establish the filter’s cutoff frequency

while not degrading the distortion performance of the device.

The shunt capacitance also acts like a charge reservoir, sinking

or sourcing the additional charge required by the hold capacitor,

C_H, further reducing current transients seen at the op amp’s

output.

DISABLE

A2

VREF

A1

1V

7.5k⍀

5k⍀

SENSE

DISABLE

A1

LOGIC

REFCOM

Figure 35. Equivalent Reference Circuit

The actual reference voltages used by the internal circuitry of

the AD9221/AD9223/AD9220 appear on the CAPT and CAPB

pins. For proper operation when using the internal or an exter-

nal reference, it is necessary to add a capacitor network to de-

couple these pins. Figure 36 shows the recommended

decoupling network. This capacitive network performs the

following three functions: (1) along with the reference ampli-

fier, A2, it provides a low source impedance over a large fre-

quency range to drive the A/D internal circuitry, (2) it provides

the necessary compensation for A2, and (3) it bandlimits the

noise contribution from the reference. The turn-on time of the

reference voltage appearing between CAPT and CAPB is ap-

proximately 15 ms and should be evaluated in any power-

down mode of operation.

The effect of this increased capacitive load on the op amp driv-

ing the AD9221/AD9223/AD9220 should be evaluated. To

optimize performance when noise is the primary consideration,

increase the shunt capacitance as much as the transient response

of the input signal will allow. Increasing the capacitance too

much may adversely affect the op amp’s settling time, frequency

response, and distortion performance.

REFERENCE OPERATION

The AD9221/AD9223/AD9220 contain an onboard bandgap

reference that provides a pin-strappable option to generate either a

1 V or 2.5 V output. With the addition of two external resistors,

the user can generate reference voltages other than 1 V and

2.5 V. Another alternative is to use an external reference for

designs requiring enhanced accuracy and/or drift performance.

See Table II for a summary of the pin-strapping options for the

AD9221/AD9223/AD9220 reference configurations.

0.1␮F

CAPT

AD9221/

AD9223/

AD9220

10␮F

0.1␮F

Figure 35 shows a simplified model of the internal voltage refer-

ence of the AD9221/AD9223/AD9220. A pin-strappable refer-

ence amplifier buffers a 1 V fixed reference. The output from

the reference amplifier, A1, appears on the VREF pin. The

voltage on the VREF pin determines the full-scale input span of

the A/D. This input span equals,

CAPB

0.1␮F

Figure 36. Recommended CAPT/CAPB Decoupling Network

The A/D’s input span may be varied dynamically by changing

the differential reference voltage appearing across CAPT and

CAPB symmetrically around 2.5 V (i.e., midsupply). To change

the reference at speeds beyond the capabilities of A2, it will be

necessary to drive CAPT and CAPB with two high speed, low

noise amplifiers. In this case, both internal amplifiers (i.e., A1

and A2) must be disabled by connecting SENSE to AVDD and

VREF to REFCOM and the capacitive decoupling network

removed. The external voltages applied to CAPT and CAPB

must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4 respec-

tively in which the input span can be varied between 2 V and 5 V.

Note that those samples within the pipeline A/D during any

reference transition will be corrupted and should be discarded.

Full-Scale Input Span = 2 × VREF

The voltage appearing at the VREF pin as well as the state of

the internal reference amplifier, A1, are determined by the volt-

age appearing at the SENSE pin. The logic circuitry contains

two comparators which monitor the voltage at the SENSE pin.

The comparator with the lowest set point (approximately 0.3 V)

controls the position of the switch within the feedback path of

A1. If the SENSE pin is tied to REFCOM, the switch is con-

nected to the internal resistor network thus providing a VREF

of 2.5 V. If the SENSE pin is tied to the VREF pin via a short

or resistor, the switch is connected to the SENSE pin. A short

will provide a VREF of 1.0 V while an external resistor network

will provide an alternative VREF between 1.0 V and 2.5 V. The

–12–

REV. D

AD9221/AD9223/AD9220

Table I. Analog Input Configuration Summary

Input

Connection

Single-Ended

Input

Coupling Span (V)

Input Range (V)

Figure

#

VINA¹

VINB¹

Comments

DC

2

0 to 2

1

39, 40

Best for stepped input response applications, suboptimum

THD and noise performance, requires ±5 V op amp.

2 × VREF

0 to

2 × VREF

VREF

39, 40

Same as above but with improved noise performance due to

increase in dynamic range. Headroom/settling time require-

ments of ±5 V op amp should be evaluated.

5

0 to 5

2.5

39, 40

50

Optimum noise performance, excellent THD performance,

Requires op amp with VCC > +5 V due to headroom issue.

2 × VREF

2.5 – VREF

to

2.5 + VREF

Optimum THD performance with VREF = 1, noise

performance improves while THD performance degrades as

VREF increases to 2.5 V. Single supply operation (i.e., +5 V) for

many op amps.

Single-Ended

AC

2 or

2 × VREF

0 to 1 or

0 to 2 × VREF

1 or VREF

2.5

41

42

Suboptimum ac performance due to input common-mode

level not biased at optimum midsupply level (i.e., 2.5 V).

5

0 to 5

Optimum noise performance, excellent THD performance,

ability to use ±5 V op amp.

2 × VREF

2.5 – VREF

to

2.5 + VREF

2.5

Flexible input range, Optimum THD performance with

VREF = 1. Noise performance improves while THD perfor-

mance degrades as VREF increases to 2.5 V. Ability to use

+5 V or ±5 V op amp.

Differential

(via Transformer)

AC

2

2 to 3

3 to 2

45

Optimum full-scale THD and SFDR performance well be-

yond the A/Ds Nyquist frequency. Preferred mode for under-

sampling applications.

2 × VREF

2.5 – VREF/2 2.5 + VREF/2 45

to to

2.5 + VREF/2 2.5 – VREF/2

Same as 2 V to 3 V input range with the exception that full-scale

THD and SFDR performance can be traded off for better noise

performance. Refer to discussion in AC Coupling and Interface

Issue section and Simple AC Interface section.

5

1.75 to 3.25

3.25 to 1.75

45

Optimum Noise performance. Also, the optimum THD and

SFDR performance for “less than” full-scale signals (i.e.,

–6 dBFS). Refer to discussion in AC Coupling and Interface

Issue section and Simple AC Interface section.

NOTE

¹VINA and VINB can be interchanged if signal inversion is required.

Table II. Reference Configuration Summary

Input Span (VINA–VINB)

Reference

Operating Mode

(V p-p)

Required VREF (V)

Connect

To

INTERNAL

2

5

1

2.5

SENSE

R1

VREF

REFCOM

VREF AND SENSE

SENSE AND REFCOM

2 ≤ SPAN ≤ 5 AND

SPAN = 2 × VREF

1 ≤ VREF ≤ 2.5 AND

VREF = (1 + R1/R2)

R2

EXTERNAL

(NONDYNAMIC)

2 ≤ SPAN ≤ 5

1 ≤ VREF ≤ 2.5

SENSE

VREF

AVDD

EXT. REF.

EXTERNAL

(DYNAMIC)

2 ≤ SPAN ≤ 5

CAPT and CAPB

Externally Driven

SENSE

VREF

EXT. REF.

AVDD

REFCOM

CAPT

CAPB

–13–

REV. D

AD9221/AD9223/AD9220

DRIVING THE ANALOG INPUTS

INTRODUCTION

amps which may otherwise have been constrained by headroom

limitations, (3) Differential operation minimizes even-order

harmonic products, and (4) Differential operation offers noise

immunity based on the device’s common-mode rejection. Fig-

ure 37 depicts the common-mode rejection of the three devices.

The AD9221/AD9223/AD9220 has a highly flexible input struc-

ture allowing it to interface with single-ended or differential

input interface circuitry. The applications shown in sections

Driving the Analog Inputs and Reference Configurations, along

with the information presented in Input and Reference Over-

view of this data sheet, give examples of both single-ended and

differential operation. Refer to Tables I and II for a list of the

different possible input and reference configurations and their

associated figures in the data sheet.

As is typical of most CMOS devices, exceeding the supply

limits will turn on internal parasitic diodes resulting in transient

currents within the device. Figure 38 shows a simple means of

clamping an ac or dc coupled single-ended input with the addi-

tion of two series resistors and two diodes. An optional capaci-

tor is shown for ac coupled applications. Note that a larger

series resistor could be used to limit the fault current through

D1 and D2 but should be evaluated since it can cause a degra-

dation in overall performance. A similar clamping circuit could

also be used for each input if a differential input signal is being

applied.

The optimum mode of operation, analog input range, and asso-

ciated interface circuitry will be determined by the particular

applications performance requirements as well as power supply

options. For example, a dc coupled single-ended input would

be appropriate for most data acquisition and imaging applica-

tions. Also, many communication applications which require a

dc coupled input for proper demodulation can take advantage of

the excellent single-ended distortion performance of the AD9221/

AD9223/AD9220. The input span should be configured such

that the system’s performance objectives and the headroom

requirements of the driving op amp are simultaneously met.

OPTIONAL

AC COUPLING

CAPACITOR

AVDD

D2

V

CC

R

30⍀

R

S1

S2

1N4148

AD9221/

AD9223/

AD9220

20⍀

D1

1N4148

Alternatively, the differential mode of operation with a trans-

former coupled input provides the best THD and SFDR perfor-

mance over a wide frequency range. This mode of operation

should be considered for the most demanding spectral-based

applications which allow ac coupling (e.g., Direct IF to Digital

Conversion).

V

EE

Figure 38. Simple Clamping Circuit

SINGLE-ENDED MODE OF OPERATION

The AD9221/AD9223/AD9220 can be configured for single-

ended operation using dc or ac coupling. In either case, the

input of the A/D must be driven from an operational amplifier

that will not degrade the A/D’s performance. Because the A/D

operates from a single-supply, it will be necessary to level-shift

ground-based bipolar signals to comply with its input require-

ments. Both dc and ac coupling provide this necessary func-

tion, but each method results in different interface issues which

may influence the system design and performance.

Single-ended operation requires that VINA be ac or dc coupled

to the input signal source while VINB of the AD9221/AD9223/

AD9220 be biased to the appropriate voltage corresponding to a

midscale code transition. Note that signal inversion may be

easily accomplished by transposing VINA and VINB. The rated

specifications for the AD9221/AD9223/AD9220 are characterized

using single-ended circuitry with input spans of 5 V and 2 V as well

as VINB = 2.5 V.

DC COUPLING AND INTERFACE ISSUES

Differential operation requires that VINA and VINB be simulta-

neously driven with two equal signals that are in and out of

phase versions of the input signal. Differential operation of the

AD9221/AD9223/AD9220 offers the following benefits: (1)

Signal swings are smaller and therefore linearity requirements

placed on the input signal source may be easier to achieve, (2)

Signal swings are smaller and therefore may allow the use of op

Many applications require the analog input signal to be dc

coupled to the AD9221/AD9223/AD9220. An operational

amplifier can be configured to rescale and level shift the input

signal so that it is compatible with the selected input range of

the A/D. The input range to the A/D should be selected on the

basis of system performance objectives as well as the analog

power supply availability since this will place certain constraints

on the op amp selection.

20

Many of the new high performance op amps are specified for

only ± 5 V operation and have limited input/output swing

capabilities. Hence, the selected input range of the AD9221/

AD9223/AD9220 should be sensitive to the headroom require-

ments of the particular op amp to prevent clipping of the sig-

nal. Also, since the output of a dual supply amplifier can swing

below –0.3 V, clamping its output should be considered in

some applications.

30

40

AD9223

AD9221

50

60

AD9220

70

In some applications, it may be advantageous to use an op amp

specified for single supply +5 V operation since it will inher-

ently limit its output swing to within the power supply rails.

An amplifier like the AD8041, AD8011, and AD817 are useful

for this purpose. Rail-to-rail output amplifiers such as the

AD8041 allow the AD9221/AD9223/AD9220 to be configured

for larger input spans which improves the noise performance.

80

90

0.1

1

10

FREQUENCY– MHz

100

Figure 37. AD9221/AD9223/AD9220 Input CMR vs. Input

Frequency

–14–

REV. D

AD9221/AD9223/AD9220

If the application requires the largest input span (i.e., 0 V to

5 V) of the AD9221/AD9223/AD9220, the op amp will require

larger supplies to drive it. Various high speed amplifiers in the

Op Amp Selection Guide of this data sheet can be selected to

accommodate a wide range of supply options. Once again,

clamping the output of the amplifier should be considered for

these applications.

500⍀*

+V

CC

0.1␮F

NC

1

+VREF

–VREF

500⍀*

7

0V

2

3

DC

R

S

6

A1

VINA

R **

500⍀*

0.1␮F

P

5

AVDD

VREF

4

AD9221/

AD9223/

AD9220

Two dc coupled op amp circuits using a noninverting and invert-

ing topology are discussed below. Although not shown, the

noninverting and inverting topologies can be easily configured

as part of an antialiasing filter by using a Sallen-Key or Multiple-

Feedback topology, respectively. An additional R-C network

can be inserted between the op amp’s output and the AD9221/

AD9223/AD9220 input to provide a real pole.

500⍀*

NC

R

S

VINB

*OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D

**OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE

Figure 40. Single-Ended Input With DC-Coupled Level Shift

Simple Op Amp Buffer

AC COUPLING AND INTERFACE ISSUES

In the simplest case, the input signal to the AD9221/AD9223/

AD9220 will already be biased at levels in accordance with the

selected input range. It is simply necessary to provide an ad-

equately low source impedance for the VINA and VINB analog

input pins of the A/D. Figure 39 shows the recommended

configuration for a single-ended drive using an op amp. In this

case, the op amp is shown in a noninverting unity gain configu-

ration driving the VINA pin. The internal reference drives the

VINB pin. Note that the addition of a small series resistor of

30 Ω to 50 Ω connected to VINA and VINB will be beneficial

in nearly all cases. Refer to Analog Input Operation section for

a discussion on resistor selection. Figure 39 shows the proper

connection for a 0 V to 5 V input range. Alternative single-

ended input ranges of 0 V to 2 × VREF can also be realized

with the proper configuration of VREF (refer to the Using the

Internal Reference section).

For applications where ac coupling is appropriate, the op amp’s

output can be easily level shifted to the common-mode voltage,

V_CM, of the AD9221/AD9223/AD9220 via a coupling capaci-

tor. This has the advantage of allowing the op amps common-

mode level to be symmetrically biased to its midsupply level

(i.e. (V_CC+ V_EE)/2). Op amps which operate symmetrically

with respect to their power supplies typically provide the best ac

performance as well as greatest input/output span. Hence,

various high speed/performance amplifiers which are restricted

to +5 V/–5 V operation and/or specified for +5 V single-supply

operation can be easily configured for the 5 V or 2 V input span

of the AD9221/AD9223/AD9220. The best ac distortion per-

formance is achieved when the A/D is configured for a 2 V

input span and common-mode voltage of 2.5 V. Note that

differential transformer coupling, which is another form of ac

coupling, should be considered for optimum ac performance.

+V

Simple AC Interface

5V

AD9221/

AD9223/

AD9220

Figure 41 shows a typical example of an ac-coupled, single-

ended configuration. The bias voltage shifts the bipolar,

ground-referenced input signal to approximately VREF. The

value for C1 and C2 will depend on the size of the resistor, R.

The capacitors, C1 and C2, are typically a 0.1 µF ceramic and

10 µF tantalum capacitor in parallel to achieve a low cutoff

frequency while maintaining a low impedance over a wide fre-

quency range. The combination of the capacitor and the resistor

form a high-pass filter with a high-pass –3 dB frequency deter-

mined by the equation,

R

S

0V

VINA

VINB

VREF

U1

–V

R

S

2.5V

10␮F

0.1␮F

SENSE

Figure 39. Single-Ended AD9221/AD9223/AD9220

Op Amp Drive Circuit

Op Amp with DC Level Shifting

f

_{–3 dB}= 1/(2 × π × R × (C1 + C2))

Figure 40 shows a dc-coupled level shifting circuit employing

an op amp, A1, to sum the input signal with the desired dc

offset. Configuring the op amp in the inverting mode with the

given resistor values results in an ac signal gain of –1. If the

signal inversion is undesirable, interchange the VINA and

VINB connections to reestablish the original signal polarity.

The dc voltage at VREF sets the common-mode voltage of the

AD9221/AD9223/AD9220. For example, when VREF = 2.5 V,

the output level from the op amp will also be centered around

2.5 V. The use of ratio matched, thin-film resistor networks will

minimize gain and offset errors. Also, an optional pull-up

resistor, R_P, may be used to reduce the output load on VREF

to ±1 mA.

The low impedance VREF voltage source biases both the VINB

input and provides the bias voltage for the VINA input. Figure

41 shows the VREF configured for 2.5 V thus the input range

C1

+5V

AD9221/

AD9223/

AD9220

+VREF

0V

–VREF

C2

R

S

V

IN

VINA

R

S

–5V

VINB

VREF

C2

C1

SENSE

Figure 41. AC-Coupled Input

of the A/D is 0 V to 5 V. Other input ranges could be selected

by changing VREF but the A/D’s distortion performance will

–15–

REV. D

AD9221/AD9223/AD9220

degrade slightly as the input common-mode voltage deviates

from its optimum level of 2.5 V.

AD817:

AD826:

AD818:

AD828:

AD812:

50 MHz Unity GBW, 70 ns Settling to 0.01%, +5 V

to ±15 V Supplies

Best Applications: Sample Rates < 7 MSPS, Low-

Noise, 5 V p-p Input Range

Alternative AC Interface

Figure 42 shows a flexible ac coupled circuit which can be con-

figured for different input spans. Since the common-mode

voltage of VINA and VINB are biased to midsupply indepen-

dent of VREF, VREF can be pin-strapped or reconfigured to

achieve input spans between 2 V and 5 V p-p. The AD9221/

AD9223/AD9220’s CMRR along with the symmetrical coupling

R-C networks will reject both power supply variations and noise.

The resistors, R, establish the common-mode voltage. They may

have a high value (e.g., 5 kΩ) to minimize power consumption

and establish a low cutoff frequency. The capacitors, C1and

C2, are typically a 0.1 µF ceramic and 10 µF tantalum capacitor

in parallel to achieve a low cutoff frequency while maintaining a

low impedance over a wide frequency range. R_Sisolates the

buffer amplifier from the A/D input. The optimum performance

is achieved when VINA and VINB are driven via «Immetrical

networks. The f_{–3 dB}point can be approximated by the equation,

Limits: THD above 100 kHz

Dual Version of AD817

Best Applications: Differential and/or Low Imped-

ance Input

Drivers, Low Noise

Limits: THD above 100 kHz

130 MHz @ G = +2 BW, 80 ns Settling to 0.01%,

+5 V to ±15 V Supplies

Best Applications: Sample Rates < 7 MSPS, Low

Noise, 5 V p-p Input Range, Gains ≥ +2

Limits: THD above 100 kHz

Dual Version of AD818

Best Applications: Differential and/or Low Impedance

Input

Drivers, Low Noise, Gains ≥ +2

Limits: THD above 100 kHz

f

_{–3 dB}= 1/(2 × π × R/2 × (C1 + C2))

+5V

Dual, 145 MHz Unity GBW, Single-Supply Cur-

rent Feedback, +5 V to ±15 V Supplies

Best Applications: Differential and/or Low Imped-

ance Input Drivers, Sample Rates < 7 MSPS

Limits: THD above 1 MHz

+5V

R

C1

V

R

S

IN

VINA

C2

R

AD9221/

AD9223/

AD9220

–5V

AD8011: f_{–3 dB}= 300 MHz, +5 V or ±5 V Supplies, Current

Feedback

R

S

VINB

+5V

C1

C2

R

Best Applications: Single-Supply, AC/DC-Coupled,

Good AC Specs, Low Noise, Low Power (5 mW)

Limits: THD above 5 MHz, Usable Input/Output

Range

Figure 42. AC-Coupled Input-Flexible Input Span, V_CM= 2 V

AD8013: Triple, f_{–3 dB}= 230 MHz, +5 V or ±5 V Supplies,

Current Feedback, Disable Function

OP AMP SELECTION GUIDE

Op amp selection for the AD9221/AD9223/AD9220 is highly

dependent on a particular application. In general, the perfor-

mance requirements of any given application can be character-

ized by either time domain or frequency domain parameters. In

either case, one should carefully select an op amp which pre-

serves the performance of the A/D. This task becomes challeng-

ing when one considers the AD9221/AD9223/AD9220’s high

performance capabilities coupled with other extraneous system

level requirements such as power consumption and cost.

Best Applications: 3:1 Multiplexer, Good AC Specs

Limits: THD above 5 MHz, Input Range

AD9631: 220 MHz Unity GBW, 16 ns Settling to 0.01%, ±5 V

Supplies

Best Applications: Best AC Specs, Low Noise, AC-

Coupled

Limits: Usable Input/Output Range, Power

Consumption

The ability to select the optimal op amp may be further compli-

cated by either limited power supply availability and/or limited

acceptable supplies for a desired op amp. Newer, high performance

op amps typically have input and output range limitations in

accordance with their lower supply voltages. As a result, some

op amps will be more appropriate in systems where ac-coupling

is allowable. When dc-coupling is required, op amps without

headroom constraints such as rail-to-rail op amps or ones where

larger supplies can be used should be considered. The following

section describes some op amps currently available from Analog

Devices. The system designer is always encouraged to contact

the factory or local sales office to be updated on Analog Devices

latest amplifier product offerings. Highlights of the areas where

the op amps excel and where they may limit the performance of

the AD9221/AD9223/AD9220 is also included.

AD8047: 130 MHz Unity GBW, 30 ns Settling to 0.01%,

±5 V Supplies

Best Applications: Good AC Specs, Low Noise,

AC-Coupled

Limits: THD > 5 MHz, Usable Input Range

AD8041: Rail-to-Rail, 160 MHz Unity GBW, 55 ns Settling

to 0.01%, +5 V Supply, 26 mW

Best Applications: Low Power, Single-Supply Sys-

tems, DC-Coupled, Large Input Range

Limits: Noise with 2 V Input Range

AD8042: Dual AD8041

Best Applications: Differential and/or Low Imped-

ance Input Drivers

Limits: Noise with 2 V Input Range

–16–

REV. D

AD9221/AD9223/AD9220

–55

–65

–75

–85

–95

DIFFERENTIAL MODE OF OPERATION

Since not all applications have a signal preconditioned for differ-

ential operation, there is often a need to perform a single-ended-

to-differential conversion. In systems which do not need to be

dc coupled, an RF transformer with a center tap is the best

method to generate differential inputs for the AD9221/AD9223/

AD9220. It provides all the benefits of operating the A/D in the

differential mode without contributing additional noise or dis-

tortion. An RF transformer also has the added benefit of provid-

ing electrical isolation between the signal source and the A/D.

AD9221

AD9223

AD9220

Note that although a single-ended-to-differential op amp topol-

ogy would allow dc coupling of the input signal, no significant

improvement in THD performance was realized when compared

to the dc single-ended mode of operation up to the AD9221/

AD9223/AD9220’s Nyquist frequency (i.e., f_IN< F_S/2). Also,

the additional op amp required in the topology tends to in-

creases the total system noise, power consumption, and cost.

Hence, a single-ended mode of operation is recommended for

most applications requiring dc coupling.

1

10

100

FREQUENCY – MHz

Figure 44. AD9221/AD9223/AD9220 SFDR vs. Input Fre-

quency (V_CM= 2.5 V, 2 V p-p Input Span, A_IN= –0.5 dB)

Figure 45 shows the schematic of the suggested transformer

circuit. The circuit uses a minicircuits RF transformer, model

#T4-6T, which has an impedance ratio of four (turns ratio of

2). The schematic assumes that the signal source has a 50 Ω

source impedance. The 1:4 impedance ratio requires the 200 Ω

secondary termination for optimum power transfer and VSWR.

The center tap of the transformer provides a convenient means

of level shifting the input signal to a desired common-mode

voltage. Optimum performance can be realized when the center

tap is tied to CML of the AD9221/AD9223/AD9220 which is

the common-mode bias level of the internal SHA.

A dramatic improvement in THD and SFDR performance can

be realized by operating the AD9221/AD9223/AD9220 in the

differential mode using a transformer. Figure 43 shows a plot of

THD vs. Input Frequency for the differential transformer

coupled circuit for each A/D while Figure 44 shows a plot of

SFDR vs. Input Frequency. Both figures demonstrate the enhance-

ment in spectral performance for the differential-mode of opera-

tion. The performance enhancement between the differential

and single-ended mode is most noteworthy as the input frequency

approaches and goes beyond the Nyquist frequency (i.e., f_IN

F_S/2) corresponding to the particular A/D.

>

C

R

S

The figures are also helpful in determining the appropriate A/D

for Direct IF-Down Conversion or undersampling applications.

Refer to Analog Devices application notes AN-301 and AN-302

for an informative discussion on undersampling. One should

select the A/D that meets or exceeds the distortion performance

requirements measured over the required frequency passband.

For example, the AD9220 achieves the best distortion perfor-

mance over an extended frequency range as a result of its greater

full-power bandwidth and thus would represent the best selec-

tion for an IF undersampling application at 21.4 MHz. Refer to

the Applications section of this data sheet for more detailed

information and characterization of this particular application.

15pF

33⍀

VINA

CML

49.9⍀

0.1␮F

AD9221/

200⍀

AD9223/

AD9220

VINB

R

C

S

15pF

S

MINI CIRCUITS

T4-1

33⍀

Figure 45. Transformer Coupled Input

Transformers with other turns ratios may also be selected to

optimize the performance of a given application. For example,

a given input signal source or amplifier may realize an improve-

ment in distortion performance at reduced output power levels

and signal swings. Hence, selecting a transformer with a higher

impedance ratio (e.g., Minicircuits T16-6T with a 1:16 imped-

ance ratio) effectively “steps up” the signal level thus further

reducing the driving requirements of the signal source.

–50

–60

Referring to Figure 45, a series resistors, R_S, and shunt capaci-

tor, C_S, were inserted between the AD9221/AD9223/AD9220

and the secondary of the transformer. The values of 33 Ω and

15 pF were selected to specifically optimize both the THD and

SNR performance of the A/D. R_Sand C_Shelp provide some

isolation from transients at the A/D inputs reflected back

through the primary of the transformer.

–70

AD9223

AD9221

–80

AD9220

The AD9221/AD9223/AD9220 can be easily configured for

either a 2 V p-p input span or 5.0 V p-p input span by setting

the internal reference (see Table II). Other input spans can be

realized with two external gain setting resistors as shown in

Figure 49 of this data sheet. Figure 46 demonstrates how both

spans of the AD9220 achieve the high degree of linearity and

–90

1

10

100

FREQUENCY – MHz

Figure 43. AD9221/AD9223/AD9220 THD vs. Input Fre-

quency (V_CM= 2.5 V, 2 V p-p Input Span, A_IN= –0.5 dB)

–17–

REV. D

AD9221/AD9223/AD9220

SFDR over a wide range of amplitudes required by the most

demanding communication applications. Similar performance is

achievable with the AD9221 and AD9223 at their correspond-

ing Nyquist frequency.

pin configures the internal reference amplifier for a gain of 2.5

and the resultant VREF output is 2.5 V. Thus, the valid input

range becomes 0 V to 5 V. The VREF pin should be bypassed

to the REFCOM pin with a 10 µF tantalum capacitor in parallel

with a low-inductance 0.1 µF ceramic capacitor.

90

2

؋

VREF

AD9221/

VINA

SFDR – 5.0V p-p

80

AD9223/

AD9220

0V

SFDR – 2.0V p-p

70

VINB

10␮F

0.1␮F

VREF

60

50

SHORT FOR 0V TO 2V

INPUT SPAN

SENSE

SNR – 2.0V p-p

SHORT FOR 0V TO 5V

INPUT SPAN

40

SNR – 5.0V p-p

REFCOM

30

20

Figure 47. Internal Reference—2 V p-p Input Span, V_CM

1 V, or 5 V p-p Input Span, V_CM= 2.5 V

=

–50

–40

–30

–20

–10

0

INPUT AMPLITUDE – dBFS

Single-Ended or Differential Input, V_CM= 2.5 V

Figure 46. AD9220 SFDR, SNR vs. Input Amplitude

(f_IN= 5 MHz, f_CLK= 10 MSPS, V_CM= 2.5 V, Differential)

Figure 48 shows the single-ended configuration that gives the

best dynamic performance (SINAD, SFDR). To optimize

dynamic specifications, center the common-mode voltage of the

analog input at approximately by 2.5 V by connecting VINB to

a low-impedance 2.5 V source. As described above, shorting

the VREF pin directly to the SENSE pin results in a 1 V refer-

ence voltage and a 2 V p-p input span. The valid range for

input signals is 1.5 V to 3.5 V. The VREF pin should be by-

passed to the REFCOM pin with a 10 µF tantalum capacitor in

parallel with a low-inductance 0.1 µF ceramic capacitor.

Figure 46 also reveals a noteworthy difference in the SFDR and

SNR performance of the AD9220 between the 2 V p-p and 5 V

p-p input span options. First, the SNR performance improves

by 2 dB with a 5.0 V p-p input span due to the increase in dy-

namic range. Second, the SFDR performance of the AD9220

will improve for input signals below approximately –6.0 dBFS.

A 3 dB to 5 dB improvement was typically realized for input

signal levels between –6.0 dBFS and –36 dBFS. This improve-

ment in SNR and SFDR for a 5.0 V p-p span may be advanta-

geous for communication systems that have additional margin

or headroom to minimize clipping of the ADC.

This reference configuration could also be used for a differential

input in which VINA and VINB are driven via a transformer as

shown in Figure 45. In this case, the common-mode voltage,

V_CM, is set at midsupply by connecting the transformers center

tap to CML of the AD9221/AD9223/AD9220. VREF can be

configured for 1 V or 2.5 V by connecting SENSE to either

VREF or REFCOM respectively. Note that the valid input

range for each of the differential input is one half of the single-

ended input and thus becomes V_CM– VREF/2 to V_CM+ VREF/2.

REFERENCE CONFIGURATIONS

The figures associated with this section on internal and external

reference operation do not show recommended matching series resistors

for VINA and VINB for the purpose of simplicity. Please refer to

section Driving the Analog Inputs, Introduction for a discussion of

this topic. Also, the figures do not show the decoupling network asso-

ciated with the CAPT and CAPB pins. Please refer to the section “Ref-

erence Operation” for a discussion of the internal reference circuitry

and the recommended decoupling network shown in Figure 36.

3.5V

VINA

VINB

AD9221/

AD9223/

AD9220

1.5V

2.5V

USING THE INTERNAL REFERENCE

1V

VREF

Single-Ended Input with 0 to 2

؋

VREF Range

SENSE

0.1␮F

10␮F

Figure 47 shows how to connect the AD9221/AD9223/AD9220

for a 0 V to 2 V or 0 V to 5 V input range via pin strapping the

SENSE pin. An intermediate input range of 0 to 2 × VREF can

be established using the resistor programmable configuration in

Figure 49 and connecting VREF to VINB.

REFCOM

Figure 48. Internal Reference—2 V p-p Input Span,

_CM= 2.5 V

V

In either case, both the common-mode voltage and input span

are directly dependent on the value of VREF. More specifically,

the common-mode voltage is equal to VREF while the input

span is equal to 2 × VREF. Thus, the valid input range extends

from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output

will be 000 Hex; when VINA is ≥ 2 × VREF, the digital output

will be FFF Hex.

Resistor Programmable Reference

Figure 49 shows an example of how to generate a reference

voltage other than 1 V or 2.5 V with the addition of two exter-

nal resistors and a bypass capacitor. Use the equation,

VREF = 1 V × (1 + R1/R2),

to determine appropriate values for R1 and R2. These resistors

should be in the 2 kΩ to 100 kΩ range. For the example shown,

R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation

above, the resultant reference voltage on the VREF pin is

Shorting the VREF pin directly to the SENSE pin places the

internal reference amplifier in unity-gain mode and the resultant

VREF output is 1 V. Therefore, the valid input range is 0 V to

2 V. However, shorting the SENSE pin directly to the REFCOM

–18–

REV. D

AD9221/AD9223/AD9220

Variable Input Span with V_CM= 2.5 V

1.5 V. This sets the input span to be 3 V p-p. To assure stabil-

ity, place a 0.1 µF ceramic capacitor in parallel with R1.

Figure 50 shows an example of the AD9221/AD9223/AD9220

configured for an input span of 2 × VREF centered at 2.5 V. An

external 2.5 V reference drives the VINB pin thus setting the

common-mode voltage at 2.5 V. The input span can be inde-

pendently set by a voltage divider consisting of R1 and R2

which generates the VREF signal. A1 buffers this resistor net-

work and drives VREF. Choose this op amp based on accuracy

requirements. It is essential that a minimum of a 10 µF capaci-

tor in parallel with a 0.1 µF low inductance ceramic capacitor

decouple the reference output to ground.

The common-mode voltage can be set to VREF by connecting

VINB to VREF to provide an input span of 0 to 2 × VREF.

Alternatively, the common-mode voltage can be set to VREF

by connecting VINB to a low impedance 2.5 V source. For

the example shown, the valid input single range for VINA is 1 V

to 4 V since VINB is set to an external, low impedance 2.5 V

source. The VREF pin should be bypassed to the REFCOM pin

with a 10 µF tantalum capacitor in parallel with a low induc-

tance 0.1 µF ceramic capacitor.

2.5V+VREF

2.5V

2.5V–VREF

4V

AD9221/

AD9223/

AD9220

VINA

VINB

VINA

1V

2.5V

REF

2.5V

VINB

+5V

0.1␮F

AD9220

1.5V

C1

22␮F

0.1␮F

R1

R2

VREF

R1

2.5k⍀

0.1␮F

10␮F

0.1␮F

A1

VREF

SENSE

R2

5k⍀

0.1␮F

SENSE

+5V

REFCOM

Figure 50. External Reference—V_CM= 2.5 V (2.5 V on

VINB, Resistor Divider to Make VREF)

Figure 49. Resistor Programmable Reference—3 V p-p

Input Span, V_CM= 2.5 V

Single-Ended Input with 0 to 2

؋

VREF Range

Figure 51 shows an example of an external reference driving

both VINB and VREF. In this case, both the common mode

voltage and input span are directly dependent on the value of

VREF. More specifically, the common mode voltage is equal to

VREF while the input span is equal to 2 × VREF. Thus, the

valid input range extends from 0 to 2 × VREF. For example, if

the REF-191, a 2.048 external reference was selected, the valid

input range extends from 0 to 4.096 V. In this case, 1 LSB of

the AD9221/AD9223/AD9220 corresponds to 1 mV. It is es-

sential that a minimum of a 10 µF capacitor in parallel with a

0.1 µF low inductance ceramic capacitor decouple the reference

output to ground.

USING AN EXTERNAL REFERENCE

Using an external reference may enhance the dc performance of

the AD9221/AD9223/AD9220 by improving drift and accuracy.

Figures 50 through 52 show examples of how to use an external

reference with the A/D. Table III is a list of suitable voltage

references from Analog Devices. To use an external reference,

the user must disable the internal reference amplifier and drive

the VREF pin. Connecting the SENSE pin to AVDD disables

the internal reference amplifier.

Table III. Suitable Voltage References

Initial

Accuracy

% (max)

Operating

Current

(␮A)

2

؋

REF

VINA

VINB

AD9221/

AD9223/

AD9220

Output

Voltage

Drift

(ppm/؇C)

0V

+5V

VREF

Internal

AD589

1.00

1.235

AD1580 1.225

REF191 2.048

2.50

REF192 2.50

26

1.4

N/A

50

45

N/A

45

0.1␮F

10␮F

0.1␮F

10–100

50–100

5–25

26

5–25

10–25

3–7

1.2–2.8

0.08–0.8

0.1–0.5

1.4

0.08–0.4

0.06–0.1

0.04–0.2

VREF

0.1␮F

Internal

+5V

SENSE

REF43

AD780

2.50

600

1000

Figure 51. Input Range = 0 V to 2 × VREF

Low Cost/Power Reference

The AD9221/AD9223/AD9220 contains an internal reference

buffer, A2 (see Figure 35), that simplifies the drive requirements

of an external reference. The external reference must be able to

drive a ≈5 kΩ (±20%) load. Note that the bandwidth of the ref-

erence buffer is deliberately left small to minimize the reference

noise contribution. As a result, it is not possible to change the

reference voltage rapidly in this mode without the removal of

the CAPT/CAPB Decoupling Network.

The external reference circuit shown in Figure 52 uses a low

cost 1.225 V external reference (e.g., AD580 or AD1580) along

with an op amp and transistor. The 2N2222 transistor acts in

conjunction with 1/2 of an OP282 to provide a very low imped-

ance drive for VINB. The selected op amp need not be a high

speed op amp and may be selected based on cost, power and

accuracy.

–19–

REV. D

AD9221/AD9223/AD9220

Table V. Out-of-Range Truth Table

3.75V

VINA

AD9221/

AD9223/

AD9220

1.25V

OTR

MSB

Analog Input Is

820⍀

+5V

1k⍀

0

1

0

1

0

1

In Range

Underrange

Overrange

0.1␮F

1k⍀

VINB

10␮F

0.1␮F

2N2222

1k⍀

316⍀

10␮F

1/2

OP282

7.5k⍀

MSB

OTR

MSB

1.225V

OVER = “1”

+5V

VREF

0.1␮F

AD1580

+5V

SENSE

UNDER = “1”

Figure 52. External Reference Using the AD1580 and Low

Impedance Buffer

Figure 54. Overrange or Underrange Logic

DIGITAL INPUTS AND OUTPUTS

Digital Output Driver Considerations (DVDD)

Digital Outputs

The AD9221, AD9223 and AD9220ARS output drivers can be

configured to interface with +5 V or 3.3 V logic families by setting

DVDD to +5 V or 3.3 V respectively. However, the AD9220AR

can only be configured to interface with +5 V logic families. The

AD9221/AD9223/AD9220 output drivers are sized to provide

sufficient output current to drive a wide variety of logic families.

However, large drive currents tend to cause glitches on the

supplies and may affect SINAD performance. Applications

requiring the AD9221/AD9223/AD9220 to drive large capaci-

tive loads or large fanout may require additional decoupling

capacitors on DVDD. In extreme cases, external buffers or

latches may be required.

The AD9221/AD9223/AD9220 output data is presented in

positive true straight binary for all input ranges. Table IV indi-

cates the output data formats for various input ranges regardless

of the selected input range. A twos complement output data

format can be created by inverting the MSB.

Table IV. Output Data Format

I

nput (V)

Condition (V)

Digital Output

OTR

VINA –VINB < – VREF

VINA –VINB = – VREF

VINA –VINB = 0

VINA –VINB = + VREF – 1 LSB 1111 1111 1111

VINA –VINB ≥ + VREF

0000 0000 0000

1000 0000 0000

1

0

1

Clock Input and Considerations

The AD9221/AD9223/AD9220 internal timing uses the two

edges of the clock input to generate a variety of internal timing

signals. The clock input must meet or exceed the minimum

specified pulsewidth high and low (t_CHand t_CL) specifications

for the given A/D as defined in the Switching Specifications at

the beginning of the data sheet to meet the rated performance

specifications. For example, the clock input to the AD9220

operating at 10 MSPS may have a duty cycle between 45% to

55% to meet this timing requirement since the minimum specified

t_CHand t_CLis 45 ns. For clock rates below 10 MSPS, the duty

cycle may deviate from this range to the extent that both t_CH

and t_CLare satisfied.

1111 1111 1111

+FS –1 1/2 LSB

OTR DATA OUTPUTS

1111 1111 1111

1111 1111 1110

OTR

1

0

–FS+1/2 LSB

0000 0000 0001

0000 0000 0000

0

1

–FS

–FS –1/2 LSB

+FS

+FS –1/2 LSB

All high speed high resolution A/Ds are sensitive to the quality

of the clock input. The degradation in SNR at a given full-scale

input frequency (f_IN) due to only aperture jitter (t_A) can be

calculated with the following equation:

Figure 53. Output Data Format

Out Of Range (OTR)

An out-of-range condition exists when the analog input voltage

is beyond the input range of the converter. OTR is a digital

output that is updated along with the data output corresponding

to the particular sampled analog input voltage. Hence, OTR has

the same pipeline delay (latency) as the digital data. It is LOW

when the analog input voltage is within the analog input range.

It is HIGH when the analog input voltage exceeds the input

range as shown in Figure 53. OTR will remain HIGH until the

analog input returns within the input range and another conver-

sion is completed. By logical ANDing OTR with the MSB

and its complement, overrange high or underrange low condi-

tions can be detected. Table V is a truth table for the over/

underrange circuit in Figure 54 which uses NAND gates. Sys-

tems requiring programmable gain conditioning of the AD9221/

AD9223/AD9220 input signal can immediately detect an out-

of-range condition, thus eliminating gain selection iterations.

Also, OTR can be used for digital offset and gain calibration.

SNR = 20 log₁₀[1/2 π f_INt_A]

In the equation, the rms aperture jitter, t_A, represents the root-

sum square of all the jitter sources which include the clock in-

put, analog input signal, and A/D aperture jitter specification.

For example, if a 5 MHz full-scale sine wave is sampled by an

A/D with a total rms jitter of 15 ps, the SNR performance of the

A/D will be limited to 66.5 dB. Undersampling applications are

particularly sensitive to jitter.

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9221/AD9223/AD9220. As such, supplies for clock drivers

should be separated from the A/D output driver supplies to

avoid modulating the clock signal with digital noise. Low jitter

crystal controlled oscillators make the best clock sources. If the

–20–

REV. D

AD9221/AD9223/AD9220

clock is generated from another type of source (by gating, divid-

ing, or other method), it should be retimed by the original clock

at the last step.

GROUNDING AND DECOUPLING

Analog and Digital Grounding

Proper grounding is essential in any high speed, high resolution

system. Multilayer printed circuit boards (PCBs) are recom-

mended to provide optimal grounding and power schemes. The

use of ground and power planes offers distinct advantages:

Most of the power dissipated by the AD9221/AD9223/AD9220

is from the analog power supplies. However, lower clock speeds

will reduce digital current slightly. Figure 55 shows the relation-

ship between power and clock rate for each A/D.

1. The minimization of the loop area encompassed by a signal

and its return path.

66

2. The minimization of the impedance associated with ground

and power paths.

64

62

3. The inherent distributed capacitor formed by the power

plane, PCB insulation, and ground plane.

60

5V p-p

These characteristics result in both a reduction of electro-

magnetic interference (EMI) and an overall improvement in

performance.

58

2V p-p

56

54

52

50

It is important to design a layout that prevents noise from coupling

onto the input signal. Digital signals should not be run in paral-

lel with input signal traces and should be routed away from the

input circuitry. While the AD9221/AD9223/AD9220 features

separate analog and digital ground pins, it should be treated as

an analog component. The AVSS and DVSS pins must be joined

together directly under the AD9221/AD9223/AD9220. A solid

ground plane under the A/D is acceptable if the power and

ground return currents are managed carefully. Alternatively, the

ground plane under the A/D may contain serrations to steer

currents in predictable directions where cross-coupling between

analog and digital would otherwise be unavoidable. The

AD9221/AD9223/AD9220/EB ground layout, shown in Figure

65, depicts the serrated type of arrangement. The analog and

digital grounds are connected by a jumper below the A/D.

48

0.5

1.0

1.5

2.0

2.5

3.0

CLOCK FREQUENCY – MHz

Figure 55a. AD9221 Power Consumption vs. Clock

Frequency

125

120

115

110

Analog and Digital Supply Decoupling

5V p-p

105

The AD9221/AD9223/AD9220 features separate analog and

digital supply and ground pins, helping to minimize digital

corruption of sensitive analog signals. In general, AVDD, the

analog supply, should be decoupled to AVSS, the analog com-

mon, as close to the chip as physically possible. Figure 56

shows the recommended decoupling for the analog supplies;

0.1 µF ceramic chip capacitors should provide adequately low

impedance over a wide frequency range. Note that the AVDD

and AVSS pins are co-located on the AD9221/AD9223/AD9220

to simplify the layout of the decoupling capacitors and provide

the shortest possible PCB trace lengths. The AD9221/AD9223/

AD9220/EB power plane layout, shown in Figure 66 depicts a

typical arrangement using a multilayer PCB.

2V p-p

100

95

90

0

1

2

3

4

5

6

CLOCK FREQUENCY – MHz

Figure 55b. AD9223 Power Consumption vs. Clock

Frequency

300

280

26

INPUT = 5V p-p

AVDD

AD9221/

AD9223/

AD9220

0.1␮F

260

25

AVSS

INPUT = 2V p-p

240

15 AVDD

16 AVSS

0.1␮F

220

200

Figure 56. Analog Supply Decoupling

0

2

4

6

8

10

12

14

The CML is an internal analog bias point used internally by the

AD9221/AD9223/AD9220. This pin must be decoupled with

at least a 0.1 µF capacitor as shown in Figure 57. The dc level of

CLOCK FREQUENCY – MHz

Figure 55c. AD9220 Power Consumption vs. Clock

Frequency

–21–

REV. D

AD9221/AD9223/AD9220

CML is approximately AVDD/2. This voltage should be buff-

ered if it is to be used for any external biasing.

to perform such functions as filtering, channel selection, quadra-

ture demodulation, data reduction, and detection.

One common example is the digitization of a 21.4 MHz IF using a

low jitter 10 MHz sample clock. Using the equation above for

the fifth Nyquist zone, the resultant frequency after sampling is

1.4 MHz. Figure 59 shows the typical performance of the

AD9220 operating under these conditions. Figure 60 demon-

strates how the AD9220 is still able to maintain a high degree of

linearity and SFDR over a wide amplitude.

AD9221/

AD9223/

AD9220

22

CML

0.1␮F

Figure 57. CML Decoupling

The digital activity on the AD9221/AD9223/AD9220 chip falls

into two general categories: correction logic, and output drivers.

The internal correction logic draws relatively small surges of

current, mainly during the clock transitions. The output drivers

draw large current impulses while the output bits are changing.

The size and duration of these currents are a function of the

load on the output bits: large capacitive loads are to be avoided.

Note, the internal correction logic of the AD9221, AD9223 and

AD9220 is referenced to AVDD while the output drivers are

referenced to DVDD.

1

0

ENCODE = 10MSPS

A = 21.4MHz

–20

–40

IN

–60

The decoupling shown in Figure 58, a 0.1 µF ceramic chip

capacitor, is appropriate for a reasonable capacitive load on the

digital outputs (typically 20 pF on each pin). Applications involv-

ing greater digital loads should consider increasing the digital

decoupling proportionally, and/or using external buffers/latches.

–80

8

2

4

7

5

3

6

9

–100

–120

1

5

FREQUENCY – MHz

DVDD

DVSS

28

27

AD9221/

AD9223/

AD9220

Figure 59. IF Sampling a 21.4 MHz Input Using the

AD9220 (V_CM= 2.5 V, Input Span = 2 V p-p)

0.1␮F

90

80

70

Figure 58. Digital Supply Decoupling

A complete decoupling scheme will also include large tantalum

or electrolytic capacitors on the PCB to reduce low-frequency

ripple to negligible levels. Refer to the AD9221/AD9223/

AD9220/EB schematic and layouts in Figures 62–68 for more

information regarding the placement of decoupling capacitors.

SFDR

60

50

SNR

40

30

20

10

0

APPLICATIONS

Direct IF Down Conversion Using the AD9220

As previously noted, the AD9220’s performance in the differen-

tial mode of operation extends well beyond its baseband region

and into several Nyquist zone regions. Hence, the AD9220 may

be well suited as a mix down converter in both narrow and

wideband applications. Various IF frequencies exist over the

frequency range in which the AD9220 maintains excellent dy-

namic performance (e.g., refer to Figure 43 and 44). The IF

signal will be aliased to the ADC’s baseband region due to the

sampling process in a similar manner that a mixer will down

convert an IF signal. For signals in various Nyquist zones, the

following equation may be used to determine the final frequency

after aliasing.

–50

–40

–30

–20

– dB

–10

0

A

IN

Figure 60. AD9220 Differential Input SNR/SFDR vs.

Input Amplitude (A_IN) @ 21.4 MHz

Multichannel Data Acquisition with Autocalibration

The AD9221/AD9223/AD9220 is well suited for high perfor-

mance, low power data acquisition systems. Aside from its ex-

ceptional ac performance, it exhibits true 12-bit linearity and

temperature drift performance (i.e., excluding internal refer-

ence). Furthermore, the A/D product family provides the system

designer with an upward or downward component selection

path based on power consumption and sampling rate.

f_{1 NYQUIST}= f_SIGNAL

f_{2 NYQUIST}= f_SAMPLE– f_SIGNAL

f_{3 NYQUIST}= abs (f_SAMPLE– f_SIGNAL

f_{4 NYQUIST}= 2 × f_SAMPLE– f_SIGNAL

)

A typical multichannel data acquisition system is shown in Fig-

ure 61. Also shown is some additional inexpensive gain and

offset autocalibration circuitry which is often required in high

accuracy data acquisition systems. These additional peripheral

components were selected based on their performance, power

consumption, and cost.

f_{5 NYQUIST}= abs (2 × f_SAMPLE– f_SIGNAL

)

There are several potential benefits in using the ADC to alias

(i.e., or mix) down a narrowband or wideband IF signal. First

and foremost is the elimination of a complete mixer stage with

its associated amplifiers and filters, reducing cost and power

dissipation. Second is the ability to apply various DSP techniques

–22–

REV. D

AD9221/AD9223/AD9220

The calibration procedure consists of a two step process. First,

the bipolar offset is calibrated by selecting CH2, the 2.5 V sys-

tem reference, of the analog multiplexer and preloading the

DAC, U5, with a midscale code of 1000 0000. If possible, sev-

eral readings of the A/D should be taken and averaged to deter-

mine the required digital offset adjustment code, U5. This

averaged offset code requires an extra bit of resolution since 1

LSB of U5 equates to 1/2 LSB of the AD9221/AD9223/AD9220.

The required offset correction code to U5 can then be deter-

mined. Second, the system gain is calibrated by selecting CH2,

a 1.25 V input which corresponds to –F_Sof the A/D. Before the

value is read, U4 should be preloaded with a code of 00 (Hex).

Several readings can also be taken and averaged to determine

the digital gain adjustment code to U2A. In this case, 1 LSB of

the A/D corresponds to 1 LSB of U4.

Referring to Figure 61, the AD9221/AD9223/AD9220 is config-

ured for single-ended operation with a 2.5 V p-p input span and

a 2.5 V common-mode voltage using an external, precision 2.5

voltage reference, U1. This configuration and input span allows

the buffer amplifier, U4, to be single supply. Also, it simplifies

the design of the low temperature drift autocalibration circuitry

which uses thin-film resistors for temperature stability and ratio-

metric accuracy. The input of the AD9221/AD9223/AD9220

can be easily configured for a wider span but it should remain

within the input/output swing capabilities of a high speed, rail-

to-rail, single-supply amplifier, U4 (e.g., AD8041).

The gain and offset calibration circuitry is based on two 8-bit,

current-output DAC08s, U3 and U5. The gain calibration

circuitry consisting of U3, and an op amp, U2A, is configured

to provide a low drift nominal 1.25 V reference to the AD9221/

AD9223/AD9220. The resistor values which set the gain cali-

bration range were selected to provide a nominal adjustment

span of ±128 LSBs with 1 LSB resolution with respect to the

A/D. Note that the bandwidth of the reference is low and, as a

result, it is not possible to change the reference voltage rapidly

in this mode.

Due to the AD9221/AD9223/AD9220’s excellent INL perfor-

mance, a two-point calibration procedure (i.e., –F_Sto midscale)

instead of an endpoint calibration procedure was chosen. Also,

since the bipolar offset is insensitive to any gain adjustment (due

to the differential SHA of the A/D), an iterative calibration

process is not required. The temperature stability of the circuit

is enhanced by selecting a dual precision op amp for U2 (e.g.,

OP293) and low temperature drift, thin film resistors. Note

that this application circuit was not built at the release of this

data sheet. Please consult Analog Devices for application assis-

tance or comments.

The offset calibration circuitry consists of a DAC, U5 and the

buffer amplifier, U4. The DAC is configured for a bipolar ad-

justment span of ±64 LSB with a 1/2 LSB resolution span with

respect to the AD9221/AD9223/AD9220. Note that both cur-

rent outputs of U5 were configured to provide a bipolar adjust-

ment span. Also, R_Cis used to decouple the output of both

DACs, U3 and U5, from their respective op amps.

0.1␮F

1.25k⍀

1.25V

162⍀

2.5k⍀

U2B

2.5k⍀

0.1␮F

1.25V

؎39mV

U2A

2.5k⍀

0.1␮F

2.5k⍀

1.1k⍀

U1

2

؋

39⍀

REF43

0.1␮F

10␮F

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

+5V

SENSE

VREF

R

100⍀

2.5k⍀

C

IOUT

VREF(+)

VREF(–)

OUT

U6

ADG608

U3

DAC08

AD9221/

AD9223/

AD9220

IOUT

BIT 1 – BIT 12

OTR

2.5k⍀

39⍀

VINA

U4

39⍀

2.50V

VINB

R

100⍀

R

C

100⍀

C

2.5k⍀

VREF(+)

VREF(–)

IOUT

U5

DAC08

IOUT

2.5k⍀

Figure 61. Typical Multichannel Data Acquisition System

–23–

REV. D

AD9221/AD9223/AD9220

+5A

TPA

D2

JP19

JP20

R15

TP16

1N5711

U8

22⍀

MSB

2

AD9221/

AD9223/

AD9220

1

C18

VINA

C19

74HC541N

G1

J8

1

3

5

0.1␮F

D3

C13

1

19

9

R16

22⍀

74HC04N

TP15

TP14

TP13

TP12

TP11

TP10

TP9

1N5711

15pF

Y0A

Y1A

Y2A

Y3A

Y4A

Y5A

13

14

15

16

17

18

11

12

Y5

Y5A

G2

15

26

23

20

21

22

24

18

17

19

27

28

25

16

MSB

OTR

13

14

12

11

10

9

8

7

6

5

A

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

MSB

A

AVDD

BIT 1

OTR

Y4

Y3

Y2

Y1

Y0

Y7

Y6

A7

A6

A5

A4

A3

A2

A1

A0

GND

8

7

6

5

4

3

2

10

AVDD

VINA

CAPB

CAPT

CML

VINB

VREF

SENSE

NOT

INSTALLED

R17

22⍀

C26

0.1␮F

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

LSB

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

Y4A

Y3A

Y2A

Y1A

Y0A

Y7B

Y6B

Y5B

Y4B

U6

C24

R18

22⍀

C23

0.1␮F

10␮F

TP1

C28

U5

16V

A

7

9

J8

R19

22⍀

C25

0.1␮F

+5D2

20

+5A

+5VD

A

TPB

AGND

DGND

REFCOM BIT 9

C21

0.1␮F

D4

1N5711

R20

22⍀

4

3

2

1

DVSS

DVDD

AVSS

BIT 10

BIT 11

BIT 12

CLK

11 J8

13 J8

15 J8

17 J8

19 J8

21 J8

23 J8

VINB

+5D

C15

15pF

C14

0.1␮F

R21

22⍀

D5

1N5711

74HC541N

G1

JP10

A

1

19

9

R22

22⍀

C20

0.1␮F

11

12

13

14

15

16

17

18

NOT

INSTALLED

CLK

JP16

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

G2

A7

A6

A5

A4

A3

A2

A1

A0

GND

REMOVE

FOR DIFF.

MODE

U8

4

U8

Y2B

Y3B

Y4B

Y5B

Y6B

Y7B

5

3

6

8

7

6

TP8

R23

22⍀

TPD

TPC

OTR

LSB

74HC04N 74HC04N

U7

CLK

JP15

JP21

BIT 11

BIT 10

BIT 9

5

4

3

2

REFOUT

R24

22⍀

TP7

TP6

TP5

TPE

JP11

JP12

J7

+5A

BIT 8

R25

22⍀

+5D2

20

10

C33

CLK IN

R12

10k⍀

+5VD

0.1␮F

C22

0.1␮F

R26

22⍀

C17

0.1␮F

JP13

JP14

R14

50⍀

Y3B

Y2B

C16

10␮F

16V

R13

10k⍀

R27 TP4

22⍀

J8

39

33

JP18

JP17

+5REFBUF

A

R28

22⍀

TP3

R10

820⍀

REFOUT

C10

+5REFBUF

U3

C11

C9

0.1␮F

10␮F

0.1␮F

C12

16V

REF43

V

0.1␮F

U4

2

6

OUT

V

+5REFBUF

IN

2

4

6

8

J8

F.S./GAIN ADJ

A

C7

0.1␮F

A

Q1

2N2222

GND

4

R11

1k⍀

7

A

3

R7

JP9

R9

50⍀

EXTERNAL REFERENCE

AND REFERENCE BUFFER

15k⍀

6

AD817

A

U8

2

A

C34

0.1␮F

4

9

8

C8

10␮F

16V

R29

U8

10 J8

12 J8

R8

10k⍀

316⍀

DECOUPLING

74HC04N

U8

+5D2

A

–SUPPLY

A

14 J8

16 J8

A

11

10

+SUPPLY

C27

0.1␮F

L1

L6

74HC04N

U8

18 J8

20 J8

+5A

+5REFBUF

L5

JP6

3

VINB

13

12

22 J8

24 J8

25 J8

26 J8

27 J8

28 J8

29 J8

30 J8

U2

C32

0.1␮F

TPF

TPG

TPH

74HC04N

J2

J3

78L05P

IN OUT

A

R6

10k⍀

SPARE GATES

1

+V

–V

R5

10k⍀

CC

C29

GND

2

22␮F

A

25V

C3

0.1␮F

A

L2

+SUPPLY

–SUPPLY

EE

C30

22␮F

25V

C4

C2

0.1␮F

A

0.1␮F

A

JP5

JP1

U1

JP7

A

J1

31 J8

32 J8

J4

J5

J6

A

L3

L4

R4

33⍀

7

A

3

AIN

+5 DIG

+5D

C5

0.1␮F

C31

6

AD8047

34 J8

TPI

22␮F

R1

50⍀

A

2

4

C1

0.1␮F

25V

NC 35 J8

JP4

+5D2

DGND

AGND

36 J8

NC 37 J8

38 J8

C6

A

0.1␮F

JP2

TPJ

TPK TPL

POWER

SUPPLY

VINA

GJ1

–SUPPLY

JP3

40 J8

R2

261⍀

R3

261⍀

(GJ1-WIRE

JUMPER CKT SIDE)

A

Figure 62. Evaluation Board Schematic

–24–

REV. D

AD9221/AD9223/AD9220

Figure 63. Evaluation Board Component Side Layout (Not to Scale)

Figure 64. Evaluation Board Solder Side Layout (Not to Scale)

–25–

REV. D

AD9221/AD9223/AD9220

Figure 65. Evaluation Board Ground Plane Layout (Not to Scale)

Figure 66. Evaluation Board Power Plane Layout

–26–

REV. D

AD9221/AD9223/AD9220

Figure 67. Evaluation Board Component Side Silkscreen (Not to Scale)

Figure 68. Evaluation Board Component Side Silkscreen (Not to Scale)

–27–

REV. D

AD9221/AD9223/AD9220

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead SOIC (R-28)

0.7125 (18.10)

0.6969 (17.70)

28

1

15

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

14

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

0.0098 (0.25)

؋

45؇

8؇

0؇

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0118 (0.30)

0.0040 (0.10)

0.0500 (1.27)

0.0157 (0.40)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

28-Lead Shrink Small Outline Package (SSOP)

(RS-28)

0.407 (10.34)

0.397 (10.08)

28

15

14

1

0.07 (1.79)

0.078 (1.98)

PIN 1

0.066 (1.67)

0.068 (1.73)

0.03 (0.762)

8°

0°

0.0256

(0.65)

BSC

0.015 (0.38)

0.010 (0.25)

0.022 (0.558)

0.008 (0.203)

0.002 (0.050)

SEATING

PLANE

0.009 (0.229)

0.005 (0.127)

–28–

REV. D


型号：	AD9223ARS-REEL
厂家：	ADI
描述：	IC 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28, SSOP-28, Analog to Digital Converter 转换器
文件：	总28页 (文件大小：353K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9223ARS-REEL [ADI]

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AD9223ARSZ

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AD9223ARZ

AD9223ARZ

AD9223ARZ-REEL

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AD9223_15

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