AD9230BCPZRL7-170 [ADI]
12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter;
| 型号： | AD9230BCPZRL7-170 |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter 转换器 |
| 文件： | 总32页 (文件大小：1949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Analog-to-Digital Converter
AD9230
FUNCTIONAL BLOCK DIAGRAM
FEATURES
RBIAS
PWDN
AGND
AVDD (1.8V)
SNR = 64.9 dBFS @ fIN up to 70 MHz @ 250 MSPS
ENOB of 10.4 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
SFDR = −79 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
Excellent linearity
REFERENCE
AD9230
CML
DRVDD
DRGND
VIN+
VIN–
DNL = 0.3 LSB typical
TRACK-AND-HOLD
INL = 0.5 LSB typical
12
12
ADC
12-BIT
CORE
OUTPUT
STAGING
LVDS
D11 TO D0
LVDS at 250 MSPS (ANSI-644 levels)
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
CLK+
CLK–
CLOCK
MANAGEMENT
OR+
OR–
SERIAL PORT
DCO+
DCO–
434 mW @ 250 MSPS—LVDS SDR mode
400 mW @ 250 MSPS—LVDS DDR mode
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
RESET SCLK SDIO CSB
Figure 1. Functional Block Diagram
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9230 is a 12-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 250 MSPS conversion
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including a track-and-hold (T/H) and voltage
reference, are included on the chip to provide a complete signal
conversion solution.
1. High Performance—Maintains 64.9 dBFS SNR @ 250 MSPS
with a 70 MHz input.
2. Low Power—Consumes only 434 mW @ 250 MSPS.
3. Ease of Use—LVDS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample and hold provide flexibility in system
design. Use of a single 1.8 V supply simplifies system
power supply design.
The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support either
twos complement, offset binary format, or Gray code. A data
clock output is available for proper output data timing.
4. Serial Port Control—Standard serial port interface supports
various product functions, such as data formatting, disabling
the clock duty cycle stabilizer, power-down, gain adjust,
and output test pattern generation.
5. Pin-Compatible Family—10-bit pin-compatible family
offered as AD9211.
Fabricated on an advanced CMOS process, the AD9230 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD9230
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 21
Analog Input and Voltage Reference ....................................... 21
Clock Input Considerations...................................................... 22
Power Dissipation and Power-Down Mode ........................... 23
Digital Outputs ........................................................................... 23
Timing ......................................................................................... 24
RBIAS........................................................................................... 24
AD9230 Configuration Using the SPI..................................... 24
Hardware Interface..................................................................... 25
Configuration Without the SPI ................................................ 25
Memory Map .................................................................................. 27
Reading the Memory Map Table.............................................. 27
Reserved Locations .................................................................... 27
Default Values............................................................................. 27
Logic Levels................................................................................. 27
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Equivalent Circuits......................................................................... 13
Typical Performance Characteristics ........................................... 14
REVISION HISTORY
2/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD9230
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 1.
AD9230-170
AD9230-210
AD9230-250
Parameter1
RESOLUTION
ACCURACY
Temp Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
12
12
12
Bits
No Missing Codes
Offset Error
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
Guaranteed
4.2
Guaranteed
4.3
Guaranteed
4.5
mV
mV
mV
% FS
LSB
LSB
LSB
LSB
−12
12
−12
12
−12
−1.5
−0.6
−1.0
12
Gain Error
0.89
0.3
1.0
0.3
0.4
1.1
0.3
0.5
−1.5
−0.5
−0.75
3.5
0.5
0.75
−1.5
−0.5
−0.75
3.5
0.5
0.75
3.5
0.6
+1.0
Differential Nonlinearity
(DNL)
Integral Nonlinearity (INL)
0.5
TEMPERATURE DRIFT
Offset Error
Full
Full
μV/°C
%/°C
±9
0.019
±8
0.021
±7
0.018
Gain Error
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
POWER SUPPLY
Full
Full
Full
25°C
0.98
1.25
1.4
4.3
2
1.5
0.98
1.25
1.4
4.3
2
1.5
0.98
1.25
1.4
4.3
2
1.5
V p-p
V
kΩ
pF
AVDD
DRVDD
Full
Full
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
V
V
Supply Currents
3
IAVDD
Full
Full
Full
Full
Full
Full
136
58
39
145
61
154
59
40
164
62
181
60
41
194
63
mA
mA
mA
mW
mW
mW
IDRVDD3/SDR Mode4
IDRVDD3/DDR Mode5
Power Dissipation3
SDR Mode4
349
315
371
383
349
407
434
400
463
DDR Mode5
1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
3 IAVDD and IDRVDD are measured with a −1 dBFS, 10.3 MHz sine input at rated sample rate.
4 Single data rate mode; this is the default mode of the AD9230.
5 Double data rate mode; user-programmable feature. See the Memory Map section.
Rev. 0 | Page 3 of 32
AD9230
AC SPECIFICATIONS1
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 2.
AD9230-170
AD9230-210
AD9230-250
Parameter2
SNR
Temp
Min
Typ
64.6
64.3
Max
Min
Typ
64.5
64.2
Max
Min
Typ
64.1
63.9
Max
Unit
fIN = 10 MHz
25°C
Full
25°C
Full
63.8
63.5
63.5
63.3
63.7
63.4
63.3
63.1
63.3
62.5
63.0
62.3
dB
dB
dB
dB
dB
dB
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
SINAD
25°C
25°C
63.5
63.0
63.4
61.5
63.3
63.3
fIN = 10 MHz
25°C
Full
25°C
Full
25°C
25°C
63.7
63.4
63.3
63.1
64.5
64.1
63.6
63.4
63.2
63.0
64.4
64.0
63.3
62.4
62.9
62.2
64.0
63.7
dB
dB
dB
dB
dB
dB
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
63.3
61.8
63.1
61.1
63.0
62.8
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 70 MHz
fIN = 170 MHz3
25°C
25°C
25°C
25°C
10.6
10.5
10.4
10.1
10.6
10.5
10.4
10.0
10.5
10.4
10.3
10.3
Bits
Bits
Bits
Bits
fIN = 225 MHz
WORST HARMONIC (Second or Third)
fIN = 10 MHz
25°C
Full
25°C
Full
25°C
25°C
−82
−78
−78
−78
−76
−75
−86
−80
−80
−78
−77
−75
−84
−79
−79
−76
−76
−75
dBc
dBc
dBc
dBc
dBc
dBc
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
−78
−68
−79
−70
−78
−75
WORST OTHER
(SFDR Excluding Second and Third)
fIN = 10 MHz
25°C
Full
25°C
Full
25°C
25°C
−89
−89
−84
−83
−83
−83
−89
−86
−84
−83
−81
−81
−84
−83
−79
−76
−79
−75
dBc
dBc
dBc
dBc
dBc
dBc
fIN = 70 MHz
fIN = 170 MHz3
fIN = 225 MHz
−89
−80
−79
−79
−83
−80
TWO-TONE IMD
140.2 MHz/141.3 MHz @ −7 dBFS
170.2 MHz/171.3 MHz @ −7 dBFS
ANALOG INPUT BANDWIDTH
25°C
25°C
25°C
73
75
67
78
73
dBc
dBc
MHz
700
700
700
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
3 140 MHz for the AD9230-170 speed grade, 170 MHz for the AD9230-210 and AD9230-250 speed grades.
Rev. 0 | Page 4 of 32
AD9230
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 3.
AD9230-170
Typ Max
AD9230-210
Typ Max
AD9230-250
Typ Max
Parameter1
Temp Min
Min
Min
Unit
CLOCK INPUTS
Logic Compliance
Full
Full
Full
Full
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
1.2
6
1.2
1.2
V
V p-p
V
0.2
0.2
6
0.2
6
AVDD −
0.3
AVDD + AVDD −
1.6
AVDD + AVDD −
1.6
AVDD
3.6
0.8
AVDD +
1.6
AVDD
3.6
0.3
1.1
1.2
0
0.3
1.1
1.2
0
Input Common-Mode Range
High Level Input Voltage (VIH) Full
Full
1.1
1.2
0
AVDD
3.6
0.8
V
V
V
μA
μA
kΩ
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
(Differential)
Input Capacitance
LOGIC INPUTS
Full
Full
Full
Full
0.8
−10
−10
16
+10
+10
24
−10
−10
16
+10
+10
24
−10
−10
16
+10
+10
24
20
4
20
4
20
4
Full
pF
Logic 1 Voltage
Full
Full
0.8 ×
VDD
0.8 ×
VDD
0.8 ×
VDD
V
V
Logic 0 Voltage
0.2 ×
0.2 ×
0.2 ×
AVDD
AVDD
AVDD
Logic 1 Input Current (SDIO)
Logic 0 Input Current (SDIO)
Logic 1 Input Current
Full
Full
Full
0
−60
55
0
−60
55
0
−60
50
μA
μA
μA
(SCLK, PDWN, CSB, RESET)
Logic 0 Input Current
(SCLK, PDWN, CSB, RESET)
Input Capacitance
LOGIC OUTPUTS2
Full
0
4
0
4
0
4
μA
pF
25°C
VOD Differential Output Voltage Full
247
1.125
454
1.375
247
1.125
454
1.375
247
1.125
454
1.375
mV
V
VOS Output Offset Voltage
Output Coding
Full
Twos complement, Gray code, or offset binary (default)
1 See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
2 LVDS RTERMINATION = 100 Ω.
Rev. 0 | Page 5 of 32
AD9230
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.
Table 4.
AD9230-170
AD9230-210
AD9230-250
Parameter (Conditions)
Maximum Conversion Rate
Minimum Conversion Rate
CLK+ Pulse Width High (tCH)
CLK+ Pulse Width Low (tCL)
Output (LVDS − SDR Mode)1
Data Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD
Temp Min
Typ
Max
Min
Typ
Max
Unit
MSPS
MSPS
ns
Full
Full
Full
Full
170
210
250
40
40
40
2.65
2.65
2.9
2.9
2.15
2.15
2.4
2.4
1.8
1.8
2.0
2.0
ns
Full
3.0
0.2
0.2
3.9
0.1
7
3.0
0.2
0.2
3.9
0.1
7
3.0
0.2
0.2
3.9
0.1
7
ns
ns
ns
ns
ns
Cycles
25°C
25°C
Full
)
Data to DCO Skew (tSKEW
)
Full
Full
−0.3
−0.5
0.5
0.3
−0.3
−0.5
0.5
0.3
−0.3
−0.5
0.5
0.3
Latency
Output (LVDS − DDR Mode)2
Data Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD
Full
3.8
0.2
0.2
3.9
0.1
7
3.8
0.2
0.2
3.9
0.1
7
3.8
0.2
0.2
3.9
0.1
7
ns
ns
ns
ns
ns
Cycles
ps rms
25°C
25°C
Full
)
Data to DCO Skew (tSKEW
Latency
)
Full
Full
25°C
Aperture Uncertainty (Jitter, tJ)
0.2
0.2
1 See Figure 2.
2 See Figure 3.
Rev. 0 | Page 6 of 32
AD9230
TIMING DIAGRAMS
N – 1
tA
N + 4
N + 5
N
N + 3
VIN
N + 1
N + 2
tCH
tCL
1/fS
CLK+
CLK–
tCPD
DCO+
DCO–
tSKEW
tPD
DX+
DX–
N – 7
N – 6
N – 5
N – 4
N – 3
Figure 2. Single Data Rate Mode
N – 1
tA
N + 4
N + 5
N
N + 3
VIN
N + 1
N + 2
tCH
tCL
1/fS
CLK+
CLK–
tCPD
DCO+
DCO–
tSKEW
tPD
D0/D6+
D0/D6–
D6
N – 8
D0
N – 7
D6
N – 7
D0
N – 6
D6
N – 6
D0
N – 5
D6
N – 5
D0
N – 4
D6
N – 4
D0
N – 3
D5/D11+
D5/D11–
D11
D5
N – 7
D11
N – 7
D5
N – 6
D11
N – 6
D5
N – 5
D11
N – 5
D5
N – 4
D11
N – 4
D5
N – 3
N – 8
6 MSBs
6 LSBs
Figure 3. Double Data Rate Mode
Rev. 0 | Page 7 of 32
AD9230
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
ELECTRICAL
AVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
D0+/D0− through D13+/D13−
to DRGND
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−2.0 V to +2.0 V
−0.3 V to DRVDD + 0.3 V
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
DCO to DRGND
OR to DGND
CLK+ to AGND
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to +3.9 V
CLK− to AGND
−0.3 V to +3.9 V
VIN+ to AGND
VIN− to AGND
SDIO/DCS to DGND
PDWN to AGND
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to +3.9 V
Table 6.
Package Type
56-Lead LFCSP (CP-48-3)
θJA
θJC
Unit
30.4
2.9
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, and through holes, ground, and power planes
reduces the θJA.
CSB to AGND
−0.3 V to +3.9 V
−0.3 V to +3.9 V
SCLK/DFS to AGND
ENVIRONMENTAL
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 10 sec)
−65°C to +125°C
−40°C to +85°C
300°C
ESD CAUTION
Junction Temperature
150°C
Rev. 0 | Page 8 of 32
AD9230
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D3–
D3+
D4–
D4+
D5–
1
2
3
4
5
6
7
8
9
PIN 1
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
INDICATOR
D5+
AD9230
TOP VIEW
(Not to Scale)
DRVDD
DRGND
D6–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
D6+ 10
D7– 11
D7+ 12
D8– 13
D8+ 14
PIN 0 (EXPOSED PADDLE) = AGND
Figure 4. Single Data Rate Mode
Table 7. Single Data Rate Mode Pin Function Descriptions
Pin No.
Mnemonic
Description
30, 32 to 34, 37 to 39, AVDD
41 to 43, 46
1.8 V Analog Supply.
7, 24, 47
0
8, 23, 48
35
DRVDD
AGND1
DRGND1
VIN+
1.8 V Digital Output Supply.
Analog Ground.
Digital Output Ground.
Analog Input—True.
36
VIN−
Analog Input—Complement.
40
CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44
45
31
28
25
CLK+
CLK−
RBIAS
RESET
SDIO/DCS
Clock Input—True.
Clock Input—Complement.
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V.
CMOS-Compatible Chip Reset (Active Low).
Serial Port Interface (SPI®) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode).
26
27
29
49
50
51
52
53
54
55
56
1
SCLK/DFS
CSB
PWDN
DCO−
DCO+
D0−
D0+
D1−
D1+
D2−
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
D0 Complement Output Bit (LSB).
D0 True Output Bit (LSB).
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D2+
D3−
D3+
2
3
4
D4−
D4+
D4 Complement Output Bit.
D4 True Output Bit.
Rev. 0 | Page 9 of 32
AD9230
Pin No.
5
6
Mnemonic
D5−
D5+
Description
D5 Complement Output Bit.
D5 True Output Bit.
9
D6−
D6+
D7−
D7+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
OR−
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit (MSB).
D11 True Output Bit (MSB).
Overrange Complement Output Bit.
Overrange True Output Bit.
10
11
12
13
14
15
16
17
18
19
20
21
22
OR+
1 AGND and DRGND should be tied to a common quiet ground plane.
Rev. 0 | Page 10 of 32
AD9230
D3/D9–
D3/D9+
D4/D10–
1
2
3
4
5
6
7
8
9
PIN 1
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
INDICATOR
D4/D10+
(MSB) D5/D11–
(MSB) D5/D11+
DRVDD
AD9230
TOP VIEW
(Not to Scale)
DRGND
OR–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 RBIAS
30 AVDD
29 PWDN
OR+ 10
DNC 11
DNC 12
DNC 13
DNC 14
PIN 0 (EXPOSED PADDLE) = AGND
DNC = DO NOT CONNECT
Figure 5. Double Data Rate
Table 8. Double Data Rate Mode Pin Function Descriptions
Pin No.
Mnemonic
Description
30, 32 to 34, 37 to 39,
41 to 43, 46
AVDD
1.8 V Analog Supply.
7, 24, 47
0
8, 23, 48
35
DRVDD
AGND1
DRGND1
VIN+
1.8 V Digital Output Supply.
Analog Ground.
Digital Output Ground.
Analog Input—True.
36
VIN−
Analog Input—Complement.
40
CML
Common-Mode Output Pin. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
44
45
31
28
25
CLK+
CLK−
RBIAS
RESET
SDIO/DCS
Clock Input—True.
Clock Input—Complement.
Set Pin for Chip Bias Current. (Place 1% 10 kΩ resistor terminated to ground.) Nominally 0.5 V.
CMOS-Compatible Chip Reset (Active Low).
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode).
26
27
29
49
50
51
52
53
54
55
56
1
SCLK/DFS
CSB
PWDN
DCO−
DCO+
D0/D6−
D0/D6+
D1/D7−
D1/D7+
D2/D8−
D2/D8+
D3/D9−
D3/D9+
D4/D10−
D4/D10+
D5/D11−
D5/D11+
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
D0/D6 Complement Output Bit (LSB).
D0/D6 True Output Bit (LSB).
D1/D7 Complement Output Bit.
D1/D7 True Output Bit.
D2/D8 Complement Output Bit.
D2/D8 True Output Bit.
D3/D9 Complement Output Bit.
D3/D9 True Output Bit.
D4/D10 Complement Output Bit.
D4/D10 True Output Bit.
D5/D11 Complement Output Bit (MSB).
D5/D11 True Output Bit (MSB).
2
3
4
5
6
Rev. 0 | Page 11 of 32
AD9230
Pin No.
Mnemonic
OR−
Description
9
D6 Complement Output Bit. (This pin is disabled if Pin 21 is reconfigured through the SPI to be OR−.)
D6 True Output Bit. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.)
Do Not Connect.
Do Not Connect. (This pin can be reconfigured as the Overrange Complement Output Bit through
the serial port register.)
10
11 to 20
21
OR+
DNC
DNC/(OR−)
22
DNC/(OR+)
Do Not Connect. (This pin can be reconfigured as the Overrange True Output Bit through the serial
port register.)
1 AGND and DRGND should be tied to a common quiet ground plane.
Rev. 0 | Page 12 of 32
AD9230
EQUIVALENT CIRCUITS
AVDD
AVDD
26kΩ
1kΩ
CSB
1.2V
10kΩ
10kΩ
CLK+
CLK–
Figure 6. Clock Inputs
Figure 9. Equivalent CSB Input Circuit
AVDD
DRVDD
AVDD
V
VIN+
VIN–
BUF
2kΩ
V+
DATAOUT–
V–
V–
CML
BUF
DATAOUT+
V+
~1.4V
AVDD
2kΩ
BUF
Figure 7. Analog Inputs (VCML = ~1.4 V)
Figure 10. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−)
1kΩ
DRVDD
SCLK/DFS
RESET
PDWN
30kΩ
1kΩ
SDIO/DCS
Figure 8. Equivalent SCLK/DFS, RESET, PDWN Input Circuit
Figure 11. Equivalent SDIO/DCS Input Circuit
Rev. 0 | Page 13 of 32
AD9230
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, TA = 25°C, 1.25 V p-p differential input, AIN = −1 dBFS, unless
otherwise noted.
0
–20
40000
35000
30000
25000
20000
15000
10000
5000
170MSPS
10.3MHz @ –1.0dBFS
SNR: 64.6dB
ENOB: 10.6 BITS
SFDR: 82dBc
INPUT REFERRED NOISE: 0.72 LSBs
–40
–60
–80
–100
–120
–140
0
0
10
20
30
40
50
60
70
80
N – 3 N – 2 N – 1
N
N + 1 N + 2 N + 3 MORE
BIN
FREQUENCY (MHz)
Figure 12. AD9230-170 64k Point Single-Tone FFT; 170 MSPS, 10.3 MHz
Figure 15. AD9230-170 Grounded Input Histogram; 170 MSPS
0
85
170MSPS
70.3MHz @ –1.0dBFS
SNR: 64.3dB
ENOB: 10.5 BITS
SFDR: 78dBc
–20
–40
80
SFDR (dBc) +25°C
75
SFDR (dBc) –40°C
–60
70
SFDR (dBc) +85°C
–80
65
–100
–120
–140
60
SNR (dB) +85°C
SNR (dB) +25°C
SNR (dB) –40°C
55
50
0
10
20
30
40
50
60
70
80
0
50
100
150
200
250
300
350
400
450
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 13. AD9230-170 64k Point Single-Tone FFT; 170 MSPS, 70.3 MHz
Figure 16. AD9230-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.25 V p-p Full Scale; 170 MSPS
0
100
170MSPS
140.3MHz @ –1.0dBFS
SNR: 63.5dB
ENOB: 10.2 BITS
SFDR: 78dBc
SFDR (dBFS)
90
80
–20
SNR (dBFS)
70
–40
–60
60
50
SFDR (dBc)
–80
40
30
–100
–120
–140
20
SNR (dB)
10
0
90
0
10
20
30
40
50
60
70
80
80
70
60
50
40
30
20
10
0
FREQUENCY (MHz)
AMPLITUDE (–dBFS)
Figure 14. AD9230-170 64k Point Single-Tone FFT; 170 MSPS, 140.3 MHz
Figure 17. AD9230-170 SNR/SFDR vs. Input Amplitude; 140.3 MHz
Rev. 0 | Page 14 of 32
AD9230
1.0
0.8
0.5
0.4
0.6
0.3
0.4
0.2
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
1023
2047
3071
4095
–1
1023
2047
3071
4095
OUTPUT CODE
OUTPUT CODE
Figure 18. AD9230-170 INL; 170 MSPS
Figure 21. AD9230-170 DNL; 170 MSPS
0
–20
120
100
80
60
40
20
0
IMD3 (dBFS)
–40
SFDR (dBFS)
–60
–80
–100
–120
–140
SFDR (dBc)
0
10
20
30
40
50
60
70
80
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
Figure 19. AD9230-170 64k Point, Two-Tone FFT; 170 MSPS,
140.1 MHz, 141.1 MHz
Figure 22. AD9230-170 Two-Tone SFDR vs. Input Amplitude; 170 MSPS,
140.1 MHz, 141.1 MHz
140
130
120
110
100
90
380
IAVDD
370
360
350
340
330
320
310
300
TOTAL POWER
80
70
60
IDVDD
50
40
60
80
100
120
140
160
180
SAMPLE RATE (MHz)
Figure 20. AD9230-170 Power Supply Current vs. Sample Rate
Rev. 0 | Page 15 of 32
AD9230
0
40000
35000
30000
25000
20000
15000
10000
5000
210MSPS
10.3MHz @ –1.0dBFS
SNR: 64.5dB
ENOB: 10.5 BITS
SFDR: 79dBc
INPUT REFERRED NOISE: 0.70 LSBs
–20
–40
–60
–80
–100
–120
–140
0
0
20
40
60
80
100
N – 3 N – 2 N – 1
N
N + 1 N + 2 N + 3 MORE
BIN
FREQUENCY (MHz)
Figure 23. AD9230-210 64k Point Single-Tone FFT; 210 MSPS, 10.3 MHz
Figure 26. AD9230-210 Grounded Input Histogram; 210 MSPS
0
90
85
210MSPS
70.3MHz @ –1.0dBFS
SNR: 63.9dB
ENOB: 10.4 BITS
SFDR: 80dBc
–20
SFDR (dBc) +25°C
80
–40
–60
SFDR (dBc) –40°C
75
SFDR (dBc) +85°C
70
65
–80
–100
–120
–140
60
SNR (dB) +25°C
55
SNR (dB) +85°C
SNR (dB) –40°C
50
0
20
40
60
80
100
0
50
100
150
200
250
300
350
400
450
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 24. AD9230-210 64k Point Single-Tone FFT; 210 MSPS, 70.3 MHz
Figure 27. AD9230-210 Single-Tone SNR/SFDR vs. Input Frequency (fIN
)
and Temperature with 1.25 V p-p Full Scale; 210 MSPS
0
100
210MSPS
SFDR (dBFS)
90
170.3MHz @ –1.0dBFS
SNR: 631.7dB
ENOB: 9.9 BITS
SFDR: 67dBc
–20
80
–40
–60
SNR (dBFS)
70
60
50
40
30
20
10
0
SFDR (dBc)
–80
–100
–120
–140
SNR (dB)
0
20
40
60
80
100
90
80
70
60
50
40
30
20
10
0
FREQUENCY (MHz)
AMPLITUDE (–dBFS)
Figure 25. AD9230-210 64k Point Single-Tone FFT; 210 MSPS, 170.3 MHz
Figure 28. AD9230-210 SNR/SFDR vs. Input Amplitude; 210 MSPS, 170.3 MHz
Rev. 0 | Page 16 of 32
AD9230
1.0
0.8
0.5
0.4
0.6
0.3
0.4
0.2
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
1023
2047
3071
4095
–1
1023
2047
3071
4095
OUTPUT CODE
OUTPUT CODE
Figure 29. AD9230-210 INL; 210 MSPS
Figure 32. AD9230-210 DNL; 210 MSPS
0
–20
120
100
80
60
40
20
0
IMD3 (dBFS)
–40
SFDR (dBFS)
–60
–80
–100
–120
–140
SFDR (dBc)
0
20
40
60
80
100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
Figure 30. AD9230-210 64 Point, Two-Tone FFT; 210 MSPS,
170.1 MHz, 171.1 MHz
Figure 33. AD9230-210 Two-Tone SFDR vs. Input Amplitude; 210 MSPS,
170.1 MHz, 171.1 MHz
170
150
130
110
90
400
390
380
370
360
350
340
330
320
IAVDD
TOTAL POWER
70
IDRVDD
50
40
90
140
190
240
SAMPLE RATE (MSPS)
Figure 31. AD9230-210 Power Supply Current vs. Sample Rate
Rev. 0 | Page 17 of 32
AD9230
0
40000
35000
30000
25000
20000
15000
10000
5000
250MSPS
10.3MHz @ –1.0dBFS
SNR: 64.1dB
ENOB: 10.5 BITS
SFDR: 84dBc
INPUT REFERRED NOISE: 0.71 LSBs
–20
–40
–60
–80
–100
–120
–140
0
0
20
40
60
80
100
120
N – 3 N – 2 N – 1
N
N + 1 N + 2 N + 3 MORE
BIN
FREQUENCY (MHz)
Figure 34. AD9230-250 64k Point Single-Tone FFT; 250 MSPS, 10.3 MHz
Figure 37. AD9230-250 Grounded Input Histogram; 250 MSPS
0
90
85
250MSPS
70.3MHz @ –1.0dBFS
SNR: 63.9dB
ENOB: 10.5 BITS
SFDR: 79dBc
–20
–40
SFDR (dBc) +25°C
80
SFDR (dBc) –40°C
75
SFDR (dBc) +85°C
–60
70
65
–80
–100
–120
–140
60
SNR (dB) +25°C
55
SNR (dB) +85°C
SNR (dB) –40°C
50
0
20
40
60
80
100
120
0
50
100
150
200
250
300
350
400
450
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 35. AD9230-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz
Figure 38. AD9230-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.25 V p-p Full Scale; 250 MSPS
0
100
250MSPS
SFDR (dBFS)
170.3MHz @ –1.0dBFS
SNR: 63.3dB
ENOB: 10.5 BITS
SFDR: 78dBc
90
80
–20
–40
SNR (dBFS)
70
60
50
40
30
20
10
0
–60
SFDR (dBc)
–80
–100
–120
–140
SNR (dBc)
0
20
40
60
80
100
120
100
90
80
70
60
50
40
30
20
10
0
FREQUENCY (MHz)
AMPLITUDE (–dBFS)
Figure 36. AD9230-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz
Figure 39. AD9230-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz
Rev. 0 | Page 18 of 32
AD9230
1.0
0.8
0.5
0.4
0.6
0.3
0.4
0.2
0.2
0.1
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
–0.5
–1
1023
2047
3071
4095
–1
1023
2047
3071
4095
OUTPUT CODE
OUTPUT CODE
Figure 40. AD9230-250 INL; 250 MSPS
Figure 43. AD9230-250 DNL; 250 MSPS
0
–20
120
100
80
60
40
20
0
IMD3 (dBFS)
SFDR (dBFS)
–40
–60
–80
SFDR (dBc)
–100
–120
–140
0
10
20
30
40
50
60
70
80
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (MHz)
AMPLITUDE (–dBFS)
Figure 41. AD9230-250 64k Point, Two-Tone FFT; 250 MSPS,
170.1 MHz, 171.1 MHz
Figure 44. AD9230-250 Two-Tone SFDR vs. Input Amplitude; 250 MSPS,
170.1 MHz, 171.1 MHz
210
190
170
150
130
110
90
480
0
–20
460
440
420
400
380
360
340
320
300
IAVDD
–40
TOTAL POWER
–60
–80
–100
–120
70
IDRVDD
50
50
100
150
200
250
300
0
30.72
61.44
92.16
122.88
SAMPLE RATE (MSPS)
FREQUENCY (MHz)
Figure 42. AD9230 Power Supply Current vs. Sample Rate
Figure 45. AD9230-250 64k Point FFT; Four W-CDMA Carriers, IF = 184 MHz,
245.6 MSPS
Rev. 0 | Page 19 of 32
AD9230
85
80
75
70
65
60
55
90
80
70
60
50
40
30
20
SFDR (dBFS) w/ DCS ON
SFDR (dBFS) w/ DCS OFF
SFDR (dBc)
SNR (dBFS) w/ DCS ON
SNR (dB)
SNR (dBFS) w/ DCS OFF
50
1.0
0
10
20
30
40
50
60
70
80
90
100
1.1
1.2
1.3
1.4
(V)
1.5
1.6
1.7
1.8
INPUT CLOCK DUTY CYCLE (% CLK+ HIGH)
V
CM
Figure 49. SNR/SFDR vs. Sample Clock Duty Cycle;
250 MSPS, 170.3 MHz @ −1 dBFS
Figure 46. SNR/SFDR vs. Common-Mode Voltage;
250 MSPS, 70.3 MHz @ −1 dBFS
2.5
2.0
1.5
1.0
0.5
0
80
75
70
65
60
55
50
45
SFDR (dBc)
AD9230-250
AD9230-210
SNR (dB)
AD9230-170
–0.5
–60
40
50
–40
–20
0
20
40
60
80
100
120
100
150
200
250
300
TEMPERATURE (°C)
SAMPLE RATE (MSPS)
Figure 50. Gain vs. Temperature
Figure 47. SNR/SFDR vs. Sample Rate;
250 MSPS, 170.3 MHz @ −1 dBFS
6.0
85
80
75
70
65
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
SFDR (dBFS)
AD9230-250
AD9230-210
AD9230-170
SNR (dBFS)
60
0.9
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
ANALOG INPUT RANGE (MHz)
Figure 51. Offset vs. Temperature
Figure 48. SNR/SFDR vs. Analog Input Range;
250 MSPS, 170.3 MHz @ −1 dBFS
Rev. 0 | Page 20 of 32
AD9230
THEORY OF OPERATION
The AD9230 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
1V p-p
49.9Ω
499Ω
AVDD
VIN+
33Ω
499Ω
523Ω
20pF
AD8138
AD9230
0.1µF
VIN–
CML
33Ω
499Ω
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
Figure 52. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9230. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few MHz, and excessive signal power can
also cause core saturation, which leads to distortion.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output-
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
ANALOG INPUT AND VOLTAGE REFERENCE
15Ω
The analog input to the AD9230 is a differential buffer. For best
dynamic performance, the source impedances driving VIN+
and VIN− should be matched such that common-mode settling
errors are symmetrical. The analog input is optimized to
provide superior wideband performance and requires that the
analog inputs be driven differentially. SNR and SINAD
performance degrades significantly if the analog input is driven
with a single-ended signal.
VIN+
1.25V p-p
50Ω
2pF
AD9230
VIN–
15Ω
0.1µF
Figure 53. Differential Transformer—Coupled Configuration
As an alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone, the AD8352 differential
driver can be used (see Figure 54).
A wideband transformer, such as Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 1.3 V.
V
CC
0.1µF
0.1µF
0Ω
16
8, 13
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.25 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of SPI control. See the AD9230 Configuration Using
the SPI section for more details.
1
2
0.1µF
0.1µF
ANALOG INPUT
11
R
R
VIN+
200Ω
200Ω
C
D
R
R
AD8352
10
C
AD9230
D
G
3
4
5
CML
VIN–
ANALOG INPUT
14
0.1µF
0Ω
0.1µF
0.1µF
Differential Input Configurations
Optimum performance is achieved while driving the AD9230
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
Figure 54. Differential Input Configuration Using the AD8352
Rev. 0 | Page 21 of 32
AD9230
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 58). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9230 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and CLK−
pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 55 shows one preferred method for clocking the AD9230.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9230 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9230 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
CLOCK
CLK
INPUT
OPTIONAL
100Ω
0.1µF
1
50Ω
CLK+
ADC
AD9230
CMOS DRIVER
CLK
0.1µF
CLK–
0.1µF
39kΩ
1
MINI-CIRCUITS
ADT1–1WT, 1:1Z
50Ω RESISTOR IS OPTIONAL.
0.1µF
0.1µF
Figure 58. Single-Ended 1.8 V CMOS Sample Clock
XFMR
CLOCK
INPUT
CLK+
100Ω
ADC
AD9230
CLK–
50Ω
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
SCHOTTKY
0.1µF
DIODES:
HSM2812
CLOCK
INPUT
CLK
OPTIONAL
100Ω
0.1µF
0.1µF
1
50Ω
Figure 55. Transformer-Coupled Differential Clock
CLK+
ADC
CMOS DRIVER
CLK
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 56. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
AD9230
0.1µF
CLK–
1
50Ω RESISTOR IS OPTIONAL.
Figure 59. Single-Ended 3.3 V CMOS Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Clock Duty Cycle Considerations
0.1µF
0.1µF
CLOCK
INPUT
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9230 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9230. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the AD9230 Configuration
Using the SPI section for more details on using this feature.
CLK
PECL DRIVER
CLK
CLK+
ADC
100Ω
AD9230
0.1µF
0.1µF
CLOCK
INPUT
CLK–
1
1
240Ω
240Ω
50Ω
50Ω
1
50Ω RESISTORS ARE OPTIONAL.
Figure 56. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
0.1µF
0.1µF
CLOCK
INPUT
CLK+
CLK
ADC
AD9230
100Ω
LVDS DRIVER
CLK
0.1µF
CLOCK
INPUT
CLK–
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
1
1
50Ω
50Ω
1
50Ω RESISTORS ARE OPTIONAL.
Figure 57. Differential LVDS Sample Clock
Rev. 0 | Page 22 of 32
AD9230
Clock Jitter Considerations
DIGITAL OUTPUTS
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
Digital Outputs and Timing
The AD9230 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SPI. This LVDS standard can further reduce
the overall power dissipation of the device, which reduces the
power by ~39 mW. See the Memory Map section for more
information. The LVDS driver current is derived on-chip and
sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal 350 mV swing at the
receiver.
SNR Degradation = 20 × log10[1/2 × π × fA × tJ]
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 60).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9230.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
The AD9230 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length is no longer than 24 inches and that the
differential output traces are kept close together and at equal
lengths.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
130
RMS CLOCK JITTER REQUIREMENT
120
110
An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 61. Figure 62 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
14
16 BITS
100
90
14 BITS
80
12 BITS
70
10 BITS
60
0.125ps
8 BITS
0.25ps
0.5ps
1.0ps
2.0ps
50
40
30
1
10
100
1000
500
ANALOG INPUT FREQUENCY (MHz)
12
400
Figure 60. Ideal SNR vs. Input Frequency and Jitter
300
10
200
POWER DISSIPATION AND POWER-DOWN MODE
100
0
8
6
4
2
0
As shown in Figure 42, the power dissipated by the AD9230 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
–100
–200
–300
–400
–500
By asserting PDWN (Pin 29) high, the AD9230 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9230 into its normal operational mode.
–3 –2 –1
0
1
2
3
–40
–20
0
20
40
TIME (ns)
TIME (ps)
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 20 MHz, the
AD9230 assumes a standby state. In this case, the biasing network
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9230 resumes normal
operation after allowing for the pipeline latency.
Figure 61. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
than 24 Inches on Standard FR-4, AD9230-250
Rev. 0 | Page 23 of 32
AD9230
+FS – 1 LSB
600
400
200
0
12
10
8
OR DATA OUTPUTS
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
OR
–FS + 1/2 LSB
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
6
–FS
–FS – 1/2 LSB
+FS
+FS – 1/2 LSB
–200
–400
–600
4
Figure 63. OR Relation to Input Voltage and Output Data
TIMING
2
The AD9230 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one
0
–100
–3 –2 –1
0
1
2
3
0
100
propagation delay (tPD) after the rising edge of the clock signal.
TIME (ns)
TIME (ps)
Figure 62. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9230-250
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9230.
These transients can degrade the converter’s dynamic performance.
The AD9230 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO.
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 12.
If it is desired to change the output data format to twos comple-
ment, see the AD9230 Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9230. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data rate
mode (SDR), data is clocked out of the AD9230 and must be
captured on the rising edge of the DCO. In double data rate
mode (DDR), data is clocked out of the AD9230 and must be
captured on the rising and falling edges of the DCO See the
timing diagrams shown in Figure 2 and Figure 3 for more
information.
The lowest typical conversion rate of the AD9230 is 40 MSPS.
At clock rates below 1 MSPS, the AD9230 assumes the standby
mode.
RBIAS
The AD9230 requires the user to place a 10 kꢀ resistor between
the RBIAS pin and ground. This resister should have a 1%
tolerance and is used to set the master current reference of the
ADC core.
AD9230 CONFIGURATION USING THE SPI
Output Data Rate and Pinout Configuration
The AD9230 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
one-byte words. Each byte may be further divided down into
fields, which are documented in the Memory Map section.
The output data of the AD9230 can be configured to drive 12
pairs of LVDS outputs at the same rate as the input clock signal
(single data rate, or SDR, mode), or six pairs of LVDS outputs at
2× the rate of the input clock signal (double data rate, or DDR,
mode). SDR is the default mode; the device may be reconfigured
for DDR by setting Bit 3 in Register 14 (see Table 13).
Out-of-Range (OR)
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK/DFS, SPI
SDIO/DCS, and CSB pins. The SCLK/DFS (serial clock) is used
to synchronize the read and write data presented the ADC. The
SDIO/DCS (serial data input/output) is a dual-purpose pin that
allows data to be sent and read from the internal ADC memory
map registers. The CSB is an active low control that enables or
disables the read and write cycles (see Table 9).
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data. OR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range, as shown in
Figure 63. OR remains high until the analog input returns to
within the input range and another conversion is completed. By
logically AND-ing OR with the MSB and its complement, over-
range high or underrange low conditions can be detected.
Rev. 0 | Page 24 of 32
AD9230
HARDWARE INTERFACE
Table 9. Serial Port Pins
The pins described in Table 9 comprise the physical interface
between the user’s programming device and the serial port of
the AD9230. All serial pins are inputs, which is an open-drain
output and should be tied to an external pull-up or pull-down
resistor (suggested value of 10 kΩ).
Mnemonic
SCLK
Function
SCLK (Serial Clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (Serial Data Input/Output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (Chip Select Bar) is active low controls that
gates the read and write cycles.
SDIO
This interface is flexible enough to be controlled by either
PROMS or PIC mirocontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
CSB
RESET
Master Device Reset. When asserted, device
assumes default settings. Active low.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power
on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9230.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 64
and Table 11.
CONFIGURATION WITHOUT THE SPI
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is 1 or more bytes of data. All data is
composed of 8-bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
In applications that do not interface to the SPI control registers,
the SPI SDIO/DCS and SPI SCLK/DFS pins can alternately
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use
the pins as static control lines for the duty cycle stabilizer. In
this mode, the SPI CSB chip select should be connected to
ground, which disables the serial port interface.
Data may be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see Interfacing to High Speed ADCs via SPI at
www.analog.com.
Table 10. Mode Selection
External
Voltage
Mnemonic
Configuration
SPI SDIO/DCS
AVDD
AGND
AVDD
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
SPI SCLK/DFS
AGND
tDS
tHI
tCLK
tH
tS
tDH
tLO
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 64. Serial Port Interface Timing Diagram
Rev. 0 | Page 25 of 32
AD9230
Table 11. Serial Timing Definitions
Parameter
Timing (minimum, ns)
Description
tDS
5
2
40
5
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
tDH
tCLK
tS
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHI
tLO
tEN_SDIO
16
16
1
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 64)
tDIS_SDIO
5
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 64)
Table 12. Output Data Format
Gray Code Mode
(SPI Accessible)
D11 to D0
Offset Binary
Output Mode
D11 to D0
Twos Complement Mode
D11 to D0
Input (V)
Condition (V)
< 0.62
= 0.62
= 0
= 0.62
OR
1
0
0
0
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
0000 0000 0000
> 0.62 + 0.5 LSB
1
Rev. 0 | Page 26 of 32
AD9230
MEMORY MAP
READING THE MEMORY MAP TABLE
RESERVED LOCATIONS
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02),
transfer register map (Address 0xFF), and program register map
(Address 0x08 to Address 0x2A).
Undefined memory locations should not be written to other
than their default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
The Addr. (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x09, clock, has a hexadecimal default value of 0x01.
This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0,
Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. The
default value enables the duty cycle stabilizer. Overwriting this
default so that Bit 0 = 0 disables the duty cycle stabilizer. For more
information on this and other functions, consult the Interfacing
to High-Speed ADCs via SPI® user manual at www.analog.com.
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 13. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Table 13. Memory Map Register
Default
Addr.
Bit 7
(MSB)
Bit 0
(LSB)
Value
(Hex)
Default Notes/
Comments
(Hex) Parameter Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Chip Configuration Registers
00
chip_port_config
0
LSB
first
Soft
reset
1
1
Soft
reset
LSB first
0
0x18
The nibbles
should be
mirrored by the
user so that LSB
or MSB first
mode registers
correctly,
regardless of
shift mode.
01
02
chip_id
8-bit chip ID, Bits[7:0]
AD9230 = 0x0C
Read-
only
Default is unique
chip ID, different
for each device.
This is a read-
only register.
chip_grade
0
0
0
0
0
0
Speed grade:
00 = 250 MSPS
01 = 210 MSPS
10 = 170 MSPS
X
0
X
0
X
Read-
only
Child ID used to
differentiate
graded devices.
Transfer Register
FF device_update
0
0
SW
transfer
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
Rev. 0 | Page 27 of 32
AD9230
Def.
Addr.
Bit 7
(MSB)
Bit 0
(LSB)
Value
(Hex)
Default Notes/
Comments
(Hex) Parameter Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ADC Functions
08
modes
0
0
PDWN:
0 = full
(default)
1 =
0
0
Internal power-down mode:
000 = normal (power-up,
default)
001 = full power-down
010 = standby
0x00
Determines
various generic
modes of chip
operation.
standby
011 = normal (power-up)
Note: External PDWN pin
overrides this setting.
09
clock
0
0
0
0
0
0
0
Duty
cycle
stabilizer:
0 =
disabled
1 =
0x01
0x00
enabled
(default)
OD
test_io
Reset
Reset
Output test mode:
When set, the
test data is
placed on the
output pins in
place of normal
data.
PN23
gen:
1 = on
0 = off
(default)
PN9 gen:
1 = on
0 = off
0000 = off (default)
0001 = midscale short
0010 = +FS short
(default)
0011 = −FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = unused
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by output_mode)
OF
14
ain_config
0
0
0
0
0
0
0
Analog
input
disable:
1 = on
0 = off
(default)
CML
0
0x00
0x00
enable:
1 = on
0 = off
(default)
output_mode
Output
enable:
0 =
enable
(default)
1 =
DDR:
1 =
enabled
0 =
disabled (default)
(default)
Output
invert:
1 = on
0 = off
Data format select:
00 = offset binary
(default)
0
0
01 = twos
complement
10 = Gray code
disable
15
16
output_adjust
output_phase
0
0
0
LVDS
LVDS fine adjust:
0x00
0x03
course
adjust:
0 =
3.5 mA
(default)
1 =
001 = 3.50 mA
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA
2.0 mA
Output
clock
0
0
polarity
1 =
inverted
0 =
normal
(default)
Rev. 0 | Page 28 of 32
AD9230
Def.
Addr.
Bit 7
(MSB)
Bit 0
(LSB)
Value
(Hex)
Default Notes/
Comments
(Hex) Parameter Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
17
flex_output_delay Output
Output clock delay:
00000 = 0.1 ns
00001 = 0.2 ns
00010 = 0.3 ns
…
11101 = 3.0 ns
11110 = 3.1 ns
11111 = 3.2 ns
0
delay
enable:
0 =
enable
1 =
disable
18
flex_vref
Input voltage range setting:
10000 = 0.98 V
10001 =1.00 V
10010 = 1.02 V
10011 =1.04 V
…
0
11111 = 1.23 V
00000 = 1.25 V
00001 = 1.27 V
…
01110 = 1.48 V
01111 = 1.50 V
2A
ovr_config
OR
position
(DDR
OR
enable:
1 = on
00000001
mode
only):
(default)
0 = off
0 = Pin 9,
Pin 10
1 =
Pin 21,
Pin 22
Rev. 0 | Page 29 of 32
AD9230
OUTLINE DIMENSIONS
0.30
0.23
0.18
8.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
56
43
42
1
PIN 1
INDICATOR
4.45
4.30 SQ
4.15
TOP
VIEW
EXPOSED
7.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
14
15
29
28
0.30 MIN
6.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.50 BSC
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 65. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm Body, Very Thin Quad
(CP-56-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
CP-56-2
CP-56-2
AD9230BCPZ-1701
AD9230BCPZ-2101
AD9230BCPZ-2501
AD9230-170EBZ1
AD9230-210EBZ1
AD9230-250EBZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
LVDS Evaluation Board with AD9230BCPZ-170
LVDS Evaluation Board with AD9230BCPZ-210
LVDS Evaluation Board with AD9230BCPZ-250
CP-56-2
1 Z = Pb-free part.
Rev. 0 | Page 30 of 32
AD9230
NOTES
Rev. 0 | Page 31 of 32
AD9230
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06002-0-2/07(0)
Rev. 0 | Page 32 of 32
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