AD9233_技术文档

12-Bit, 80 MSPS/105 MSPS/125 MSPS,

1.8 V Analog-to-Digital Converter

AD9233

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AVDD

DRVDD

1.8 V analog supply operation

1.8 V to 3.3 V output supply

AD9233

SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input

SFDR = 85 dBc to 70 MHz input

Low power: 395 mW @ 125 MSPS

Differential input with 650 MHz bandwidth

On-chip voltage reference and sample-and-hold amplifier

DNL = 0.15 LSB

Flexible analog input: 1 V p-p to 2 V p-p range

Offset binary, Gray code, or twos complement data format

Clock duty cycle stabilizer

VIN+

VIN–

8-STAGE

MDAC1

A/D

3

SHA

1 1/2-BIT PIPELINE

4

8

A/D

REFT

REFB

CORRECTION LOGIC

OR

13

OUTPUT BUFFERS

DCO

D11 (MSB)

D0 (LSB)

VREF

Data output clock

Serial port control

Built-in selectable digital test pattern generation

Programmable clock and data alignment

SENSE

SCLK/DFS

SDIO/DCS

CSB

CLOCK

DUTY CYCLE

STABILIZER

0.5V

MODE

SELECT

REF

SELECT

AGND

CLK+ CLK–

PDWN DRGND

APPLICATIONS

Ultrasound equipment

Figure 1.

IF sampling in communications receivers

IS-95, CDMA-One, IMT-2000

Battery-powered instruments

Hand-held scopemeters

The digital output data is presented in offset binary, Gray code, or

twos complement formats. A data output clock (DCO) is provided

to ensure proper latch timing with receiving logic.

The AD9233 is available in a 48-lead LFCSP and is specified

over the industrial temperature range (−40°C to +85°C).

Low cost digital oscilloscopes

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD9233 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/

105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring

a high performance sample-and-hold amplifier (SHA) and on-

chip voltage reference. The product uses a multistage differential

pipeline architecture with output error correction logic to

provide 12-bit accuracy at 125 MSPS data rates and guarantees

no missing codes over the full operating temperature range.

1. The AD9233 operates from a single 1.8 V power supply

and features a separate digital output driver supply to

accommodate 1.8 V to 3.3 V logic families.

2. The patented SHA input maintains excellent performance

for input frequencies up to 225 MHz.

The wide bandwidth, truly differential SHA allows a variety of

user-selectable input ranges and offsets, including single-ended

applications. It is suitable for multiplexed systems that switch

full-scale voltage levels in successive channels and for sampling

single-channel inputs at frequencies well beyond the Nyquist rate.

Combined with power and cost savings over previously available

ADCs, the AD9233 is suitable for applications in communications,

imaging, and medical ultrasound.

3. The clock DCS maintains overall ADC performance over a

wide range of clock pulse widths.

4. A standard serial port interface supports various product

features and functions, such as data formatting (offset

binary, twos complement, or Gray coding), enabling the

clock DCS, power-down, and voltage reference mode.

5. The AD9233 is pin compatible with the AD9246, allowing

a simple migration from 12 bits to 14 bits.

A differential clock input controls all internal conversion cycles. A

duty cycle stabilizer (DCS) compensates for wide variations in the

clock duty cycle while maintaining excellent overall ADC

performance.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9233

TABLE OF CONTENTS

Features .............................................................................................. 1

Timing ......................................................................................... 22

Serial Port Interface (SPI).............................................................. 23

Configuration Using the SPI..................................................... 23

Hardware Interface..................................................................... 23

Configuration Without the SPI ................................................ 23

Memory Map .................................................................................. 24

Reading the Memory Map Table.............................................. 24

Layout Considerations................................................................... 27

Power and Ground Recommendations................................... 27

CML ............................................................................................. 27

RBIAS........................................................................................... 27

Reference Decoupling................................................................ 27

Evaluation Board ............................................................................ 28

Power Supplies............................................................................ 28

Input Signals................................................................................ 28

Output Signals ............................................................................ 28

Default Operation and Jumper Selection Settings................. 29

Alternative Clock Configurations............................................ 29

Alternative Analog Input Drive Configuration...................... 30

Schematics....................................................................................... 31

Evaluation Board Layouts ......................................................... 36

Bill of Materials (BOM)............................................................. 39

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Diagram ........................................................................... 7

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Equivalent Circuits......................................................................... 10

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 15

Analog Input Considerations.................................................... 15

Voltage Reference ....................................................................... 17

Clock Input Considerations...................................................... 18

Jitter Considerations .................................................................. 19

Power Dissipation and Standby Mode..................................... 20

Digital Outputs ........................................................................... 21

Rev. A | Page 2 of 44

AD9233

REVISION HISTORY

8/06—Rev. 0 to Rev. A

4/06—Revision 0: Initial Version

Updated Format.................................................................. Universal

Added 80 MSPS.................................................................. Universal

Deleted Figure 19, Figure 20, Figure 22, and Figure 23;

Renumbered Sequentially ..............................................................11

Deleted Figure 24, Figure 25, and Figure 27 to Figure 29;

Renumbered Sequentially ..............................................................12

Deleted Figure 31 and Figure 34; Renumbered Sequentially....13

Deleted Figure 37, Figure 38, Figure 40, and Figure 41;

Renumbered Sequentially ..............................................................14

Deleted Figure 46; Renumbered Sequentially .............................15

Deleted Figure 52; Renumbered Sequentially .............................16

Changes to Figure 40 ......................................................................16

Changes to Figure 46 ......................................................................18

Inserted Figure 54; Renumbered Sequentially ............................20

Changes to Digital Outputs Section .............................................21

Changes to Timing Section............................................................22

Added Data Clock Output (DCO) Section..................................22

Changes to Configuration Using the SPI Section and

Configuration Without the SPI Section.......................................23

Changes to Table 15 ........................................................................25

Changes to Table 16 ........................................................................39

Changes to Ordering Guide...........................................................42

Rev. A | Page 3 of 44

AD9233

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS enabled, unless otherwise noted.

Table 1.

AD9233BCPZ-80

AD9233BCPZ-105

AD9233BCPZ-125

Parameter

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

Full

12

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Full

2ꢀ°C

Full

2ꢀ°C

Guaranteed

±±.3

±±.2

±±.ꢀ

±4.ꢂ

±±.3

±±.2

±±.ꢁ

±4.ꢃ

±±.ꢀ

±±.3

±±.2

±±.ꢁ

±3.ꢃ

±±.ꢀ

% FSR

LSB

Differential Nonlinearity (DNL)¹

±±.2

±±.ꢀ

±±.2

±±.ꢀ

±±.2

±±.ꢀ

Integral Nonlinearity (INL)¹

±1.2

±2±

±1.2

±3ꢀ

±1.2

±3ꢀ

LSB

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

±1ꢀ

±ꢃꢀ

±1ꢀ

±ꢃꢀ

±1ꢀ

±ꢃꢀ

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Load Regulation @ 1.± mA

INPUT REFERRED NOISE

VREF = 1.± V

Full

±ꢀ

ꢂ

±ꢀ

ꢂ

±ꢀ

ꢂ

mV

2ꢀ°C

±.34

LSB rms

ANALOG INPUT

Input Span, VREF = 1.± V

Input Capacitance²

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Full

2

ꢁ

6

2

ꢁ

6

2

ꢁ

6

V p-p

pF

kΩ

Supply Voltage

AVDD

DRVDD

Full

1.ꢂ

1.ꢁ

3.3

1.ꢃ

3.6

1.ꢂ

1.ꢁ

3.3

1.ꢃ

3.6

1.ꢂ

1.ꢁ

3.3

1.ꢃ

3.6

V

Supply Current

IAVDD¹

Full

13ꢁ

ꢂ

12

1ꢀꢀ

1ꢂꢁ

ꢁ

14

1ꢃ4

22±

1±

1ꢂ

236

mA

IDRVDD¹(DRVDD = 1.ꢁ V)

IDRVDD¹(DRVDD = 3.3 V)

POWER CONSUMPTION

DC Input

Full

24ꢁ

261

2ꢁꢁ

4±

2ꢂꢃ

32±

33ꢀ

36ꢀ

4±

3ꢀ±

3ꢃꢀ

41ꢀ

4ꢀ2

4±

42ꢀ

mW

Sine Wave Input¹(DRVDD = 1.ꢁ V)

Sine Wave Input¹(DRVDD = 3.3 V)

Standby³

Power-Down

1.ꢁ

¹Measured with a low input frequency, full-scale sine wave, with approximately ꢀ pF loading on each output bit.

²Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.

³Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

Rev. A | Page 4 of 44

AD9233

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS enabled, unless otherwise noted.

Table 2.

AD9233BCPZ-80

AD9233BCPZ-105

AD9233BCPZ-125

Parameter¹

Temp Min Typ

Max

Min Typ

Max

Min Typ

Max

Unit

SIGNAL-TO-NOISE-RATIO (SNR)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

6ꢃ.ꢀ

dBc

6ꢁ.ꢃ

6ꢁ.ꢀ

6ꢁ.3

f_IN= 1±± MHz

f_IN= 1ꢂ± MHz

6ꢃ.4

6ꢁ.ꢃ

6ꢃ.4

6ꢁ.ꢃ

6ꢃ.4

6ꢁ.ꢃ

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

6ꢃ.2

dBc

6ꢂ.3

f_IN= 1±± MHz

f_IN= 1ꢂ± MHz

6ꢃ.1

6ꢁ.6

6ꢃ.1

6ꢁ.6

6ꢃ.1

6ꢁ.6

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

f_IN= 1±± MHz

f_IN= 1ꢂ± MHz

2ꢀ°C

11.4

11.3

11.4

11.3

11.4

11.3

Bits

WORST SECOND OR THIRD HARMONIC

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

−ꢃ±.±

−ꢁꢀ.±

−ꢃ±.±

−ꢁꢀ.±

−ꢃ±.±

−ꢁꢀ.±

dBc

−ꢂ3.± dBc

dBc

−ꢂ6.±

−ꢂ3.±

f_IN= 1±± MHz

f_IN= 1ꢂ± MHz

−ꢁꢀ.±

−ꢁ3.ꢀ

−ꢁꢀ.±

−ꢁ3.ꢀ

−ꢁꢀ.±

−ꢁ3.ꢀ

dBc

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

ꢃ±.±

ꢁꢀ.±

ꢃ±.±

ꢁꢀ.±

ꢃ±.±

ꢁꢀ.±

dBc

ꢂ6.±

ꢂ3.±

f_IN= 1±± MHz

f_IN= 1ꢂ± MHz

ꢁꢀ.±

ꢁ3.ꢀ

ꢁꢀ.±

ꢁ3.ꢀ

ꢁꢀ.±

ꢁ3.ꢀ

WORST OTHER (HARMONIC OR SPUR)

f_IN= 2.4 MHz

f_IN= ꢂ± MHz

2ꢀ°C

Full

2ꢀ°C

−ꢃ±.±

dBc

−ꢁ1.± dBc

dBc

−ꢁꢀ.±

−ꢁ1.±

f_IN= 1±± MHz

f_IN= 1ꢂ± MHz

−ꢃ±.±

dBc

TWO-TONE SFDR

f_IN= 3± MHz (−ꢂ dBFS), 31 MHz (−ꢂ dBFS)

f_IN= 1ꢂ± MHz (−ꢂ dBFS), 1ꢂ1 MHz (−ꢂ dBFS)

2ꢀ°C

ꢁꢂ

ꢁ3

ꢁꢂ

ꢁ3

ꢁꢀ

ꢁ4

dBFS

MHz

ANALOG INPUT BANDWIDTH

6ꢀ±

¹See AN-ꢁ3ꢀ, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

Rev. A | Page ꢀ of 44

AD9233

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,

DCS enabled, unless otherwise noted.

Table 3.

AD9233BCPZ-80/105/125

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

High Level Input Voltage (V_IH)

Low Level Input Voltage (V_IL)

High Level Input Current (I_IH)

Low Level Input Current (I_IL)

Input Resistance

Full

1.2

V

V p-p

V

±.2

AVDD − ±.3

6

AVDD + 1.6

AVDD

3.6

1.1

1.2

±

−1±

ꢁ

±.ꢁ

V

+1±

12

μA

kΩ

pF

1±

4

Input Capacitance

LOGIC INPUTS (SCLK/DFS, OE, PWDN)

High Level Input Voltage (V_IH)

Low Level Input Voltage (V_IL)

High Level Input Current (I_IH)

Low Level Input Current (I_IL)

Input Resistance

Full

1.2

±

−ꢀ±

−1±

3.6

±.ꢁ

−ꢂꢀ

+1±

V

μA

kΩ

pF

3±

2

Input Capacitance

LOGIC INPUTS (CSB)

High Level Input Voltage (V_IH)

Low Level Input Voltage (V_IL)

High Level Input Current (I_IH)

Low Level Input Current (I_IL)

Input Resistance

Full

1.2

±

−1±

+4±

3.6

±.ꢁ

+1±

+13ꢀ

V

μA

kΩ

pF

26

2

Input Capacitance

LOGIC INPUTS (SDIO/DCS)

High Level Input Voltage (V_IH)

Low Level Input Voltage (V_IL)

High Level Input Current (I_IH)

Low Level Input Current (I_IL)

Input Resistance

Full

1.2

±

−1±

+4±

DRVDD + ±.3

±.ꢁ

+1±

V

μA

kΩ

pF

+13±

26

ꢀ

Input Capacitance

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage (V_OH, I_OH= ꢀ± μA)

High Level Output Voltage (V_OH, I_OH= ±.ꢀ mA)

Low Level Output Voltage (V_OL, I_OL= 1.6 mA)

Low Level Output Voltage (V_OL, I_OL= ꢀ± μA)

DRVDD = 1.ꢁ V

Full

3.2ꢃ

3.2ꢀ

V

±.2

±.±ꢀ

High Level Output Voltage (V_OH, I_OH= ꢀ± μA)

High Level Output Voltage (V_OH, I_OH= ±.ꢀ mA)

Low Level Output Voltage (V_OL, I_OL= 1.6 mA)

Low Level Output Voltage (V_OL, I_OL= ꢀ± μA)

Full

1.ꢂꢃ

1.ꢂꢀ

V

±.2

±.±ꢀ

Rev. A | Page 6 of 44

AD9233

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

AD9233BCPZ-80

AD9233BCPZ-105

AD9233BCPZ-125

Parameter¹

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Conversion Rate, DCS Enabled

Conversion Rate, DCS Disabled

CLK Period

CLK Pulse Width High, DCS Enabled

CLK Pulse Width High, DCS Disabled

DATA OUTPUT PARAMETERS

Data Propagation Delay (t_PD)²

Full

2±

1±

12.ꢀ

3.ꢂꢀ

ꢀ.63

ꢁ±

2±

1±

ꢃ.ꢀ

2.ꢁꢀ

4.2ꢁ

1±ꢀ

2±

1±

ꢁ

2.4

3.6

12ꢀ

MSPS

ns

6.2ꢀ

ꢁ.ꢂꢀ

6.ꢁꢁ

4.ꢂꢀ

6.6ꢀ

ꢀ.23

4

ꢀ.6

4.4

Full

3.1

3.ꢃ

4.4

ꢀ.ꢂ

6.ꢁ

12

±.ꢁ

±.1

3ꢀ±

2

4.ꢁ

3.1

3.ꢃ

4.4

4.3

ꢀ.3

12

±.ꢁ

±.1

3ꢀ±

2

4.ꢁ

3.1

3.ꢃ

4.4

3.ꢀ

4.ꢀ

12

±.ꢁ

±.1

3ꢀ±

3

4.ꢁ

ns

cycles

ns

ps rms

ms

DCO Propagation Delay (t_DCO

)

Setup Time (t_S)

Hold Time (t_H)

Pipeline Delay (Latency)

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

Wake-Up Time³

4.ꢃ

ꢀ.ꢃ

3.4

4.4

2.6

3.ꢂ

OUT-OF-RANGE RECOVERY TIME

SERIAL PORT INTERFACE⁴

cycles

SCLK Period (t_CLK

)

Full

4±

16

ꢀ

2

ꢀ

4±

16

ꢀ

2

ꢀ

4±

16

ꢀ

2

ꢀ

ns

SCLK Pulse Width High Time (t_HI)

SCLK Pulse Width Low Time (t_LO)

SDIO to SCLK Setup Time (t_DS)

SDIO to SCLK Hold Time (t_DH)

CSB to SCLK Setup Time (t_S)

CSB to SCLK Hold Time (t_H)

2

¹See AN-ꢁ3ꢀ, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

²Output propagation delay is measured from CLK ꢀ±% transition to DATA ꢀ±% transition, with ꢀ pF load.

³Wake-up time is dependant on the value of the decoupling capacitors, values shown with ±.1 μF capacitor across REFT and REFB.

⁴See Figure ꢀꢂ and the Serial Port Interface (SPI) section.

TIMING DIAGRAM

N + 2

N + 1

N + 3

N

N + 4

N + 8

t_A

N + 5

N + 7

N + 6

t_CLK

CLK+

CLK–

t_PD

N – 12

DATA

DCO

N – 13

t_S

N – 11

t_H

N – 10

N – 9

t_DCO

N – 8

N – 7

t_CLK

N – 6

N – 5

N – 4

Figure 2. Timing Diagram

Rev. A | Page ꢂ of 44

AD9233

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

ELECTRICAL

AVDD to AGND

−±.3 V to +2.± V

−±.3 V to +3.ꢃ V

−±.3 V to +±.3 V

−3.ꢃ V to +2.± V

−±.3V to DRVDD + ±.3V

−±.3 V to DRVDD + ±.3 V

−±.3V to DRVDD + ±.3V

−±.3 V to +3.ꢃ V

DRVDD to DRGND

AGND to DRGND

AVDD to DRVDD

D± through D11 to DRGND

DCO to DRGND

OR to DRGND

CLK+ to AGND

CLK− to AGND

VIN+ to AGND

VIN− to AGND

THERMAL RESISTANCE

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the

customer board increases the reliability of the solder joints,

maximizing the thermal capability of the package.

−±.3 V to +3.ꢃ V

−±.3 V to AVDD + 1.3 V

−±.3 V to AVDD + ±.2 V

−±.3 V to DRVDD + ±.3 V

−±.3 V to +3.ꢃ V

VREF to AGND

SENSE to AGND

REFT to AGND

Table 6.

Package Type

θ_JA

θ_JC

Unit

4ꢁ-lead LFCSP (CP-4ꢁ-3)

26.4

2.4

°C/W

REFB to AGND

SDIO/DCS to DRGND

PDWN to AGND

CSB to AGND

SCLK/DFS to AGND

OEB to AGND

Typical θ_JAand θ_JCare specified for a 4-layer board in still air.

Airflow increases heat dissipation, effectively reducing θ_JA. In

addition, metal in direct contact with the package leads from

metal traces, and through holes, ground, and power planes,

reduces the θ_JA.

−±.3 V to +3.ꢃ V

ENVIRONMENTAL

Storage Temperature Range

Operating Temperature Range

Lead Temperature

(Soldering 1± Sec)

–6ꢀ°C to +12ꢀ°C

–4±°C to +ꢁꢀ°C

3±±°C

Junction Temperature

1ꢀ±°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page ꢁ of 44

AD9233

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

(LSB) D0

D1

1

2

3

4

5

6

7

8

9

36 PDWN

35 RBIAS

34 CML

PIN 1

INDICATOR

D2

33 AVDD

32 AGND

31 VIN–

D3

D4

AD9233

D5

DRGND

DRVDD

D6

30 VIN+

TOP VIEW

(Not to Scale)

29 AGND

28 REFT

27 REFB

26 VREF

25 SENSE

D7 10

D8 11

D9 12

PIN 0 (EXPOSED PADDLE): AGND

NC = NO CONNECT

Figure 3. Pin Configuration

Table 7. Pin Function Description

Pin No.

Mnemonic

Description

±, 21, 23, 2ꢃ,

32, 3ꢂ, 41

AGND

Analog Ground. (Pin ± is the exposed thermal pad on the bottom of the package.)

1 to 6, ꢃ to 14

ꢂ, 16, 4ꢂ

ꢁ, 1ꢂ, 4ꢁ

1ꢀ

D± (LSB) to D11 (MSB)

DRGND

DRVDD

Data Output Bits.

Digital Output Ground.

Digital Output Driver Supply (1.ꢁ V to 3.3 V).

Out-of-Range Indicator.

OR

1ꢁ

SDIO/DCS

Serial Port Interface (SPI)® Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select

(External Pin Mode). See Table 1±.

1ꢃ

2±

SCLK/DFS

CSB

SPI Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode). See Table 1±.

SPI Chip Select (Active Low).

22, 24, 33, 4±, 42 AVDD

Analog Power Supply.

2ꢀ

26

2ꢂ

2ꢁ

3±

31

34

3ꢀ

SENSE

VREF

REFB

REFT

VIN+

VIN–

CML

Reference Mode Selection. See Table ꢃ.

Voltage Reference Input/Output.

Differential Reference (−).

Differential Reference (+).

Analog Input Pin (+).

Analog Input Pin (−).

Common-Mode Level Bias Output.

External Bias Resister Connection. A 1± kΩ resister must be connected between this pin and

analog ground (AGND).

RBIAS

36

3ꢁ

3ꢃ

43

44

4ꢀ, 46

PDWN

CLK+

CLK–

OEB

DCO

NC

Power-Down Function Select.

Clock Input (+).

Clock Input (−).

Output Enable (Active Low).

Data Clock Output.

No Connection.

Rev. A | Page ꢃ of 44

AD9233

EQUIVALENT CIRCUITS

1kΩ

30kΩ

SCLK/DFS

OEB

VIN

PDWN

Figure 4. Equivalent Analog Input Circuit

Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit

AVDD

26kΩ

1kΩ

1.2V

CSB

10kΩ

CLK+

CLK–

Figure 9. Equivalent CSB Input Circuit

Figure 5. Equivalent Clock Input Circuit

1kΩ

DRVDD

SENSE

1kΩ

SDIO/DCS

Figure 6. Equivalent SDIO/DCS Input Circuit

Figure 10. Equivalent SENSE Circuit

DRVDD

AVDD

VREF

6kΩ

DRGND

Figure 11. Equivalent VREF Circuit

Figure 7. Equivalent Digital Output Circuit

Rev. A | Page 1± of 44

AD9233

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN =

−1.0 dBFS; 64k sample; T_A= 25°C, unless otherwise noted. All figures show typical performance for all speed grades.

0

125MSPS

100.3MHz @ –1dBFS

SNR = 69.4dBc (70.4dBFS)

ENOB = 11.2 BITS

SFDR = 85.0dBc

2.3MHz @ –1dBFS

SNR = 69.5dBc (70.5dBFS)

ENOB = 11.2 BITS

SFDR = 90.0dBc

–20

–40

–60

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

15.625

31.250

46.875

62.500

0

15.625

31.250

46.875

62.500

FREQUENCY (MHz)

Figure 15. AD9233-125 Single-Tone FFT with F_IN= 100.3 MHz

Figure 12. AD9233-125 Single-Tone FFT with F_IN= 2.3 MHz

0

125MSPS

140.3MHz @ –1dBFS

SNR = 69.0dBc (70.0dBFS)

ENOB = 11.1 BITS

SFDR = 85.0dBc

125MSPS

30.3MHz @ –1dBFS

–20

SNR = 69.5dBc (70.5dBFS)

ENOB = 11.2 BITS

SFDR = 88.8dBc

–40

–60

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

15.625

31.250

46.875

62.500

0

15.625

31.250

46.875

62.500

FREQUENCY (MHz)

Figure 16. AD9233-125 Single-Tone FFT with F_IN= 140.3 MHz

Figure 13. AD9233-125 Single-Tone FFT with F_IN= 30.3 MHz

0

125MSPS

70.3MHz @ –1dBFS

125MSPS

170.3MHz @ –1dBFS

SNR = 69.5dBc (70.5dBFS)

ENOB = 11.2 BITS

SFDR = 85.0dBc

–20

SNR = 68.9dBc (69.9dBFS)

ENOB = 11.1 BITS

SFDR = 83.5dBc

–40

–60

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

15.625

31.250

FREQUENCY (MHz)

46.875

62.500

0

15.625

31.250

FREQUENCY (MHz)

46.875

62.500

Figure 14. AD9233-125 Single-Tone FFT with F_IN= 70.3 MHz

Figure 17. AD9233-125 Single-Tone FFT with F_IN= 170.3 MHz

Rev. A | Page 11 of 44

AD9233

100

95

90

85

80

75

70

65

60

0

125MSPS

225.3MHz @ –1dBFS

SNR = 68.5dBc (69.5dBFS)

ENOB = 11.0 BITS

SFDR = 80.4dBc

–20

SFDR = –40°C

–40

–60

SFDR = +25°C

SFDR = +85°C

–80

SNR = +25°C

SNR = –40°C

–100

–120

SNR = +85°C

50

–140

0

100

150

200

250

15.625

31.250

46.875

62.500

INPUT FREQUENCY (MHz)

FREQUENCY (MHz)

Figure 18. AD9233-125 Single-Tone FFT with F_IN= 225.3 MHz

Figure 21. AD9233 Single-Tone SNR/SFDR vs.

Input Frequency (F_IN) and Temperature with 2 V p-p Full Scale

100

0

125MSPS

300.3MHz @ –1dBFS

95

–20

SNR = 67.8dBc (68.8dBFS)

ENOB = 10.8 BITS

SFDR = +85°C

SFDR = 77.4dBc

90

85

80

75

70

65

60

SFDR = +25°C

–40

–60

SFDR = –40°C

SNR = –40°C

–80

–100

–120

–140

SNR = +25°C

SNR = +85°C

50

0

100

150

200

250

0

15.625

31.250

FREQUENCY (MHz)

46.875

62.500

INPUT FREQUENCY (MHz)

Figure 22. AD9233 Single-Tone SNR/SFDR vs.

Figure 19. AD9233-125 Single-Tone FFT with F_IN= 300.3 MHz

Input Frequency (F_IN) and Temperature with 1 V p-p Full Scale

1.0

120

SFDR (dBFS)

100

0.8

OFFSET ERROR

0.5

80

60

40

20

0

SNR (dBFS)

0.3

0

GAIN ERROR

–0.3

–0.5

–0.8

–1.0

SFDR (dBc)

85dB REFERENCE LINE

SNR (dBc)

–20

0

20

40

60

–40

80

–90

0

–80

–70

–60

–50

–40

–30

–20

–10

TEMPERATURE (°C)

INPUT AMPLITUDE (dBFS)

Figure 23. AD9233 Gain and Offset vs. Temperature

Figure 20. AD9233 Single-Tone SNR/SFDR vs.

Input Amplitude (AIN) with F_IN= 2.4 MHz

Rev. A | Page 12 of 44

AD9233

0

–20

–40

125MSPS

29.1MHz @ –7dBFS

32.1MHz @ –7dBFS

SFDR = 85dBc (92dBFS)

–20

SFDR (dBc)

–40

–60

IMD3 (dBc)

–60

–80

–100

–120

–140

SFDR (dBFS)

–100

–120

IMD3 (dBFS)

–30

0

15.625

31.250

46.875

62.500

–90

–78

–66

–54

–42

–18

–6

FREQUENCY (MHz)

ANALOG INPUT LEVEL (dBFS)

Figure 24. AD9233-125 Two-Tone FFT with F_IN1= 29.1 MHz, F_IN2= 32.1 MHz

Figure 27. AD9233 Two-Tone SFDR/IMD vs.

Input Amplitude (AIN) with F_IN1= 29.1 MHz, F_IN2= 32.1 MHz

0

125MSPS

169.1MHz @ –7dBFS

172.1MHz @ –7dBFS

–20

SFDR = 84dBc (91dBFS)

SFDR (dBc)

–40

–60

–40

IMD3 (dBFS)

–60

–80

SFDR (dBFS)

–100

–120

–140

–100

IMD3 (dBFS)

–66 –54

INPUT AMPLITUDE (dBFS)

–120

–90

0

15.625

31.250

FREQUENCY (MHz)

46.875

62.500

–78

–42

–30

–18

–6

Figure 28. AD9233 Two-Tone SFDR/IMD vs.

Input Amplitude (AIN) with F_IN1= 169.1 MHz, F_IN2= 172.1 MHz

Figure 25. AD9233-125 Two-Tone FFT with F_IN1= 169.1 MHz, F_IN2= 172.1 MHz

0

–20

NPR = 61.9dBc

NOTCH @ 18.5MHz

NOTCH WIDTH = 3MHz

–20

–40

–60

–80

–100

–120

–100

–120

0

15.625

31.250

FREQUENCY (MHz)

46.875

62.500

0

15.36

30.72

46.08

61.44

FREQUENCY (MHz)

Figure 29. AD9233-125 Noise Power Ratio

Figure 26. AD9233-125 Two 64k WCDMA Carriers

with F_IN= 215.04 MHz, F_S= 122.88 MSPS

Rev. A | Page 13 of 44

AD9233

100

95

90

85

80

75

70

10

8

0.34 LSB rms

SFDR

6

4

SNR

2

65

5

0

25

45

65

85

105

125

N–1

N

N+1

CLOCK FREQUENCY (MSPS)

OUTPUT CODE

Figure 33. AD9233 Grounded Input Histogram

Figure 30. AD9233 Single-Tone SNR/SFDR vs.

Clock Frequency (F_S) with F_IN= 2.4 MHz

0.35

0.25

100

SFDR DCS = ON

90

80

70

60

50

40

0.15

SFDR DCS = OFF

0.05

SNR DCS = ON

–0.05

–0.15

–0.25

–0.35

SNR DCS = OFF

60

0

1024

2048

3072

4096

20

40

DUTY CYCLE (%)

80

OUTPUT CODE

Figure 31. AD9233 SNR/SFDR vs. Duty Cycle with F_IN= 10.3 MHz

Figure 34. AD9233 INL with F_IN= 10.3 MHz

90

0.15

0.10

0.05

0

SFDR

85

80

75

–0.05

–0.10

–0.15

70

SNR

65

0.5

0.7

0.9

1.1

1.3

0

1024

2048

3072

4096

INPUT COMMON-MODE VOLTAGE (V)

OUTPUT CODE

Figure 32. AD9233 SNR/SFDR vs.

Input Common Mode (V_CM) with F_IN= 30 MHz

Figure 35. AD9233 DNL with F_IN= 10.3 MHz

Rev. A | Page 14 of 44

AD9233

THEORY OF OPERATION

S

The AD9233 architecture consists of a front-end SHA followed

by a pipelined switched capacitor ADC. The quantized outputs

from each stage are combined into a final 12-bit result in the

digital correction logic. The pipelined architecture permits the

first stage to operate on a new input sample, while the

remaining stages operate on preceding samples. Sampling

occurs on the rising edge of the clock.

C

H

S

C

S

VIN+

C

PIN, PAR

H

VIN–

C

H

PIN, PAR

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

S

Figure 36. Switched-Capacitor SHA Input

For best dynamic performance, the source impedances driving

VIN+ and VIN− should match such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

The input stage contains a differential SHA that can be ac- or

dc-coupled in differential or single-ended modes. The output-

staging block aligns the data, carries out the error correction,

and passes the data to the output buffers. The output buffers are

powered from a separate supply, allowing adjustment of the

output voltage swing. During power-down, the output buffers

proceed into a high impedance state.

An internal differential reference buffer creates two reference

voltages used to define the input span of the ADC core. The

span of the ADC core is set by the buffer to be 2 × VREF. The

reference voltages are not available to the user. Two bypass

points, REFT and REFB, are brought out for decoupling to

reduce the noise contributed by the internal reference buffer. It

is recommended that REFT be decoupled to REFB by a 0.1 μF

capacitor, as described in the Layout Considerations section.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9233 is a differential switched

capacitor SHA that has been designed for optimum

performance while processing a differential input signal.

Input Common Mode

The analog inputs of the AD9233 are not internally dc-biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device such that V_CM= 0.55 × AVDD is

recommended for optimum performance; however, the device

functions over a wider range with reasonable performance (see

Figure 32). An on-board common-mode voltage reference is

included in the design and is available from the CML pin.

Optimum performance is achieved when the common-mode

voltage of the analog input is set by the CML pin voltage

(typically 0.55 × AVDD). The CML pin must be decoupled to

ground by a 0.1 μF capacitor, as described in the Layout

Considerations section.

The clock signal alternately switches the SHA between sample

mode and hold mode (see Figure 36). When the SHA is

switched into sample mode, the signal source must be capable

of charging the sample capacitors and settling within one-half

of a clock cycle. A small resistor in series with each input can

help reduce the peak transient current required from the output

stage of the driving source.

A shunt capacitor can be placed across the inputs to provide

dynamic charging currents. This passive network creates a low-

pass filter at the ADC input; therefore, the precise values are

dependant upon the application.

Differential Input Configurations

In IF undersampling applications, any shunt capacitors should

be reduced. In combination with the driving source impedance,

these capacitors limit the input bandwidth. See Application

Notes AN-742, Frequency Domain Response of Switched-

Capacitor ADCs, and AN-827, A Resonant Approach To

Interfacing Amplifiers to Switched-Capacitor ADCs, and the

Analog Dialogue article, “Transformer-Coupled Front-End for

Wideband A/D Converters”, for more information.

Optimum performance is achieved by driving the AD9233 in a

differential input configuration. For baseband applications, the

AD8138 differential driver provides excellent performance and

a flexible interface to the ADC. The output common-mode

voltage of the AD8138 is easily set with the CML pin of the

AD9233 (see Figure 37), and the driver can be configured

in a Sallen-Key filter topology to provide band limiting of the

input signal.

Rev. A | Page 1ꢀ of 44

AD9233

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9233. For applications

where SNR is a key parameter, transformer coupling is the

recommended input. For applications where SFDR is a key

parameter, differential double balun coupling is the recom-

mended input configuration. An example is shown in Figure 39.

1V p-p

49.9Ω

499Ω

R

VIN+

VIN–

AVDD

499Ω

523Ω

C

AD9233

AD8138

0.1µF

CML

499Ω

Figure 37. Differential Input Configuration Using the AD8138

As an alternative to using a transformer-coupled input at

frequencies in the second Nyquist zone, the AD8352 differential

driver can be used. An example is shown in Figure 40.

For baseband applications where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 38. The CML

voltage can be connected to the center tap of the secondary

winding of the transformer to bias the analog input.

In any configuration, the value of the shunt capacitor, C, is

dependent on the input frequency and source impedance

and may need to be reduced or removed. Table 8 displays

recommended values to set the RC network. However, these

values are dependant on the input signal and should only be

used as a starting guide.

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can cause core

saturation, which leads to distortion.

Table 8. RC Network Recommended Values

Frequency Range (MHz)

R Series (Ω) C Differential (pF)

R

VIN+

± to ꢂ±

ꢂ± to 2±±

2±± to 3±±

>3±±

33

1ꢀ

ꢀ

49.9Ω

C

AD9233

2V p-p

R

CML

Open

VIN–

0.1µF

Figure 38. Differential Transformer-Coupled Configuration

0.1µF

R

VIN+

2V p-p

25Ω

P

S

P

C

AD9233

A

0.1µF

R

CML

VIN–

Figure 39. Differential Double Balun Input Configuration

V

CC

0.1µF

11

0.1µF

0Ω

16

1

8, 13

ANALOG INPUT

0.1µF

R

2

VIN+

200Ω

AD8352

R

C

AD9233

D

G

C

D

3

4

5

10

CML

VIN–

14

0.1µF

ANALOG INPUT

0Ω

0.1µF

Figure 40. Differential Input Configuration Using the AD8352

Rev. A | Page 16 of 44

AD9233

Single-Ended Input Configuration

This puts the reference amplifier in a noninverting mode with

the VREF output defined as

Although not recommended, it is possible to operate the

AD9233 in a single-ended input configuration, as long as the

input voltage swing is within the AVDD supply. Single-ended

operation can provide adequate performance in cost-sensitive

applications. In this configuration, SFDR and distortion

performance degrade due to the large input common-mode

swing. If the source impedances on each input are matched,

there should be little effect on SNR performance. Figure 41

details a typical single-ended input configuration.

R2

R1

⎛

⎝

⎞

⎟

⎠

VREF = 0.5× 1+

⎜

If the SENSE pin is connected to the AVDD pin, the reference

amplifier is disabled, and an external reference voltage can be

applied to the VREF pin (see the External Reference Operation

section).

The input range of the ADC always equals twice the voltage at

the reference pin for either an internal or an external reference.

AVDD

10µF

1kΩ

R

VIN+

ADC

VIN+

CORE

VIN–

0.1µF

49.9Ω

1kΩ

AVDD

1V p-p

REFT

0.1µF

ADC

C

AD9233

1kΩ

R

VIN–

10µF

1kΩ

0.1µF

REFB

VREF

0.1µF

Figure 41. Single-Ended Input Configuration

0.1µF

SELECT

LOGIC

VOLTAGE REFERENCE

SENSE

A stable and accurate voltage reference is built into the AD9233.

The input range is adjustable by varying the reference voltage

applied to the AD9233, using either the internal reference or an

externally applied reference voltage. The input span of the ADC

tracks reference voltage changes linearly. The various reference

modes are summarized in the following sections. The Reference

Decoupling section describes the best practices and requirements

for PCB layout of the reference.

0.5V

AD9233

Figure 42. Internal Reference Configuration

VIN+

ADC

CORE

VIN–

REFT

Internal Reference Connection

A comparator within the AD9233 detects the potential at the

SENSE pin and configures the reference into four possible

states, which are summarized in Table 9. If SENSE is grounded,

the reference amplifier switch is connected to the internal

resistor divider (see Figure 42), setting VREF to 1 V.

0.1µF

REFB

VREF

0.1µF

R2

SELECT

LOGIC

SENSE

Connecting the SENSE pin to VREF switches the reference

amplifier output to the SENSE pin, completing the loop and

providing a 0.5 V reference output. If a resistor divider is

connected external to the chip, as shown in Figure 43, the

switch again sets to the SENSE pin.

0.5V

R1

AD9233

Figure 43. Programmable Reference Configuration

If the internal reference of the AD9233 is used to drive multiple

converters to improve gain matching, the loading of the

reference by the other converters must be considered. Figure 44

depicts how the internal reference voltage is affected by loading.

Rev. A | Page 1ꢂ of 44

AD9233

Table 9. Reference Configuration Summary

Selected Mode

SENSE Voltage

Resulting VREF (V)

Resulting Differential Span (V p-p)

External Reference

AVDD

N/A

2 × External Reference

Internal Fixed Reference

Programmable Reference

Internal Fixed Reference

VREF

±.2 V to VREF

AGND to ±.2 V

±.ꢀ

1.±

2 × VREF

2.±

±.ꢀ × (1 + R2/R1) (See Figure 43)

1.±

0

–0.25

–0.50

–0.75

–1.00

–1.25

CLOCK INPUT CONSIDERATIONS

VREF = 0.5V

For optimum performance, the AD9233 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

The signal is typically ac-coupled into the CLK+ pin and the

CLK− pin via a transformer or capacitors. These pins are biased

internally (see Figure 5) and require no external bias.

VREF = 1V

Clock Input Options

The AD9233 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal used, the jitter of the clock

source is of the most concern, as described in the Jitter

Considerations section.

0

0.5

1.0

1.5

2.0

LOAD CURRENT (mA)

Figure 46 shows one preferred method for clocking the

AD9233. A low jitter clock source is converted from single-

ended to a differential signal using an RF transformer. The

back-to-back Schottky diodes across the transformer secondary

limit clock excursions into the AD9233 to approximately

0.8 V p-p differential. This helps prevent the large voltage

swings of the clock from feeding through to other portions of

the AD9233 while preserving the fast rise and fall times of the

signal, which are critical to a low jitter performance.

Figure 44. VREF Accuracy vs. Load

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift

characteristics. Figure 45 shows the typical drift characteristics

of the internal reference in both 1 V and 0.5 V modes.

10

VREF = 0.5V

8

MIN-CIRCUITS

ADT1–1WT, 1:1Z

0.1µF

XFMR

6

4

2

0

VREF = 1V

CLOCK

INPUT

CLK+

100Ω

ADC

AD9233

CLK–

50Ω

0.1µF

SCHOTTKY

DIODES:

0.1µF

HSMS2812

Figure 46. Transformer Coupled Differential Clock

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins, as shown in Figure 47. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515 family of clock drivers offers

excellent jitter performance.

–20

0

20

40

60

–40

80

TEMPERATURE (°C)

Figure 45. Typical VREF Drift

When the SENSE pin is tied to the AVDD pin, the internal

reference is disabled, allowing the use of an external reference.

An internal resistor divider loads the external reference with an

equivalent 6 kΩ load (see Figure 11). In addition, an internal

buffer generates the positive and negative full-scale references

for the ADC core. Therefore, the external reference must be

limited to a maximum of 1 V.

0.1µF

CLOCK

INPUT

CLK

CLK+

ADC

AD9233

AD951x

100Ω

PECL DRIVER

0.1µF

CLOCK

INPUT

CLK–

CLK

240Ω

50Ω*

*50Ω RESISTORS ARE OPTIONAL

Figure 47. Differential PECL Sample Clock

Rev. A | Page 1ꢁ of 44

AD9233

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 48. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515 family of clock

drivers offers excellent jitter performance.

and distortion performance are nearly flat for a wide range of

duty cycles when the DCS is on, as shown in Figure 31.

Jitter in the rising edge of the input is still of paramount

concern and is not reduced by the internal stabilization circuit.

The duty cycle control loop does not function for clock rates

less than 20 MHz nominally. The loop has a time constant

associated with it that needs to be considered in applications

where the clock rate can change dynamically, which requires a

wait time of 1.5 ꢀs to 5 ꢀs after a dynamic clock frequency

increase (or decrease) before the DCS loop is relocked to the

input signal. During the time the loop is not locked, the DCS

loop is bypassed, and the internal device timing is dependant

on the duty cycle of the input clock signal. In such an application,

it can be appropriate to disable the duty cycle stabilizer. In all

other applications, enabling the DCS circuit is recommended to

maximize ac performance.

0.1µF

CLOCK

INPUT

CLK+

CLK

ADC

AD9233

AD951x

LVDS DRIVER

100Ω

0.1µF

CLOCK

INPUT

CLK–

CLK

50Ω*

*50Ω RESISTORS ARE OPTIONAL

Figure 48. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

directly drive CLK+ from a CMOS gate, while bypassing the

CLK− pin to ground with a 0.1 μF capacitor. Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages up to 3.6 V, making the

selection of the drive logic voltage very flexible. When driving

CLK+ with a 1.8 V CMOS signal, it is required to bias the

CLK− pin with a 0.1 ꢀF capacitor in parallel with a 39 kΩ

resistor (see Figure 49). The 39 kΩ resistor is not required when

driving CLK+ with a 3.3 V CMOS signal (see Figure 50).

The DCS can be enabled or disabled by setting the SDIO/DCS

pin when operating in the external pin mode (see Table 10), or

via the SPI, as described in the Table 15.

Table 10. Mode Selection (External Pin Mode)

Voltage at Pin

SCLK/DFS

SDIO/DCS

AGND

AVDD

Binary (default)

Twos complement

DCS disabled

DCS enabled (default)

VCC

JITTER CONSIDERATIONS

OPTIONAL

0.1µF

1kΩ

AD951x

100Ω

CLOCK

INPUT

CLK+

CMOS DRIVER

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (F_IN) due to jitter (t_J) is calculated as

50Ω*

ADC

AD9233

CLK–

0.1µF

39kΩ

SNR = −20 log (2π × F_IN× t_J)

*50Ω RESISTOR IS OPTIONAL

In the equation, the rms aperture jitter (t_J) represents the root-

mean-square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification. IF

undersampling applications are particularly sensitive to jitter, as

shown in Figure 51.

Figure 49. Single-Ended 1.8 V CMOS Sample Clock

VCC

OPTIONAL

100Ω

0.1µF

50Ω*

1kΩ

CLOCK

INPUT

AD951x

CMOS DRIVER

CLK+

ADC

AD9233

70

0.05ps

CLK–

MEASURED

65

PERFORMANCE

*50Ω RESISTOR IS OPTIONAL

0.20ps

0.5ps

Figure 50. Single-Ended 3.3 V CMOS Sample Clock

60

55

50

45

40

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic perform-

ance characteristics.

1.0ps

1.50ps

2.00ps

2.50ps

3.00ps

The AD9233 contains a DCS that retimes the nonsampling, or

falling edge, providing an internal clock signal with a nominal

50% duty cycle. This allows a wide range of clock input duty

cycles without affecting the performance of the AD9233. Noise

1

10

100

1000

INPUT FREQUENCY (MHz)

Figure 51. SNR vs. Input Frequency and Jitter

Rev. A | Page 1ꢃ of 44

AD9233

475

450

425

400

375

350

250

200

150

100

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9233. Power

supplies for clock drivers should be separated from the ADC

output driver supplies to avoid modulating the clock signal with

digital noise. The power supplies should also not be shared with

analog input circuits such as buffers to avoid the clock

modulating onto the input signal or vice versa. Low jitter,

crystal-controlled oscillators make the best clock sources.

If the clock is generated from another type of source (by

gating, dividing, or other methods), it should be retimed by the

original clock at the last step.

IAVDD

TOTAL POWER

50

0

IDRVDD

75

325

Refer to Application Notes AN-501, Aperture Uncertainty and

ADC System Performance, and AN-756, Sampled Systems and

the Effects of Clock Phase Noise and Jitter for more in-depth

information about jitter performance as it relates to ADCs.

25

50

100

0

125

CLOCK FREQUENCY (MSPS)

Figure 52. AD9233-125 Power and Current vs. Clock Frequency, F_IN= 30 MHz

410

390

370

350

330

310

290

270

200

180

160

140

120

POWER DISSIPATION AND STANDBY MODE

IAVDD

As shown in Figure 52 and Figure 53, the power dissipated by

the AD9233 is proportional to its sample rate. The digital power

dissipation is determined primarily by the strength of the digital

drivers and the load on each output bit. The maximum DRVDD

current (I_DRVDD) can be calculated as

100

80

TOTAL POWER

f_CLK

2

I_DRVDD= V_DRVDD×C_LOAD

×

×N

60

40

20

where N is the number of output bits (12 in the case of the

IDRVDD

AD9233).

250

0

105

30

55

80

5

This maximum current occurs when every output bit switches

on every clock cycle, that is, a full-scale square wave at the

Nyquist frequency, f_CLK/2. In practice, the DRVDD current is

established by the average number of output bits switching,

which is determined by the sample rate and the characteristics

of the analog input signal. Reducing the capacitive load

presented to the output drivers can minimize digital power

consumption.

CLOCK FREQUENCY (MSPS)

Figure 53. AD9233-105 Power and Current vs. Clock Frequency, F_IN= 30 MHz

290

275

260

245

230

150

120

90

IAVDD

TOTAL POWER

The data used for Figure 52 and Figure 53 is based on the

same operating conditions as used in the plots in the Typical

Performance Characteristics section with a 5 pF load on each

output driver.

60

30

0

IDRVDD

215

20

40

CLOCK FREQUENCY (MSPS)

60

80

0

Figure 54. AD9233-80 Power and Current vs. Clock Frequency, F_IN= 30 MHz

Rev. A | Page 2± of 44

AD9233

Power-Down Mode

Out-of-Range (OR) Condition

By asserting the PDWN pin high, the AD9233 is placed in

power-down mode. In this state, the ADC typically dissipates

1.8 mW. During power-down, the output drivers are placed in a

high impedance state. Reasserting the PDWN pin low returns

the AD9233 to its normal operational mode. This pin is both

1.8 V and 3.3 V tolerant.

An out-of-range condition exists when the analog input voltage

is beyond the input range of the ADC. OR is a digital output

that is updated along with the data output corresponding to the

particular sampled input voltage. Thus, OR has the same pipeline

latency as the digital data.

+FS – 1 LSB

OR DATA OUTPUTS

1

0

1111 1111 1111

1111 1111 1110

OR

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and then must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in power-down mode;

shorter power-down cycles result in proportionally shorter

wake-up times. With the recommended 0.1 ꢀF decoupling

capacitor on REFT and REFB, it takes approximately 0.25 ms

to fully discharge the reference buffer decoupling capacitor and

0.35 ms to restore full operation.

–FS + 1/2 LSB

0

1

0000 0000 0001

0000 0000 0000

–FS

–FS – 1/2 LSB

+FS

+FS – 1/2 LSB

Figure 55. OR Relation to Input Voltage and Output Data

OR is low when the analog input voltage is within the analog

input range and high when the analog input voltage exceeds the

input range, as shown in Figure 55. OR remains high until the

analog input returns to within the input range and another

conversion is completed. By logically AND’ing the OR bit with

the MSB and its complement, overrange high or underrange

low conditions can be detected. Table 11 is a truth table for the

overrange/underrange circuit in Figure 56, which uses NAND

gates.

Standby Mode

When using the SPI port interface, the user can place the ADC

in power-down or standby modes. Standby mode allows the

user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map

section for more details.

MSB

DIGITAL OUTPUTS

OVER = 1

OR

The AD9233 output drivers can be configured to interface with

1.8 V to 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that can affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fanouts can require external buffers or latches.

UNDER = 1

MSB

Figure 56. Overrange/Underrange Logic

Table 11. Overrange/Underrange Truth Table

OR

MSB

Analog Input Is:

Within Range

Underrange

±

1

±

1

±

1

The output data format can be selected for either offset binary

or twos complement by setting the SCLK/DFS pin when

operating in the external pin mode (see Table 10). As detailed in

the Interfacing to High Speed ADCs via SPI User Manual, the

data format can be selected for either offset binary, twos

complement, or Gray code when using the SPI control.

Overrange

Digital Output Enable Function (OEB)

The AD9233 has three-state ability. If the OEB pin is low, the

output data drivers are enabled. If the OEB pin is high, the output

data drivers are placed in a high impedance state. This is not

intended for rapid access to the data bus. Note that OEB is

referenced to the digital supplies (DRVDD) and should not

exceed that supply voltage.

Table 12. Output Data Format

Condition (V)

Binary Output Mode

±±±± ±±±± ±±±±

1±±± ±±±± ±±±±

1111 1111 1111

Twos Complement Mode

Gray Code Mode (SPI Accessible)

11±± ±±±± ±±±±

±±±± ±±±± ±±±±

1±±± ±±±± ±±±±

OR

VIN+ − VIN− < –VREF – ±.ꢀ LSB

VIN+ − VIN− = –VREF

VIN+ − VIN− = ±

VIN+ − VIN− = +VREF – 1.± LSB

VIN+ − VIN− > +VREF – ±.ꢀ LSB

1±±± ±±±± ±±±±

±±±± ±±±± ±±±±

±111 1111 1111

1

±

1

1±±± ±±±± ±±±±

Rev. A | Page 21 of 44

AD9233

Data Clock Output (DCO)

TIMING

The AD9233 provides a data clock output (DCO) intended for

capturing the data in an external register. The data outputs are

valid on the rising edge of DCO, unless the DCO clock polarity

has been changed via the SPI. See Figure 2 for a graphical

timing description.

The lowest typical conversion rate of the AD9233 is 10 MSPS.

At clock rates below 10 MSPS, dynamic performance can

degrade.

The AD9233 provides latched data outputs with a pipeline delay

of 12 clock cycles. Data outputs are available one propagation

delay (t_PD) after the rising edge of the clock signal.

The length of the output data lines and the loads placed on

them should be minimized to reduce transients within the

AD9233. These transients can degrade the dynamic performance

of the converter.

Rev. A | Page 22 of 44

AD9233

SERIAL PORT INTERFACE (SPI)

The AD9233 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. This provides the user added

flexibility and customization depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that

are further divided into fields, as documented in the Memory

Map section. For detailed operational information, see the

Interfacing to High Speed ADCs via SPI User Manual.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip as well as read the

contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an

output at the appropriate point in the serial frame.

Data can be sent in MSB first or in LSB first mode. MSB first is

the default on power up and can be changed via the

configuration register. For more information, see the Interfacing

to High Speed ADCs via SPI User Manual.

CONFIGURATION USING THE SPI

As summarized in Table 13, three pins define the SPI of this

ADC. The SCLK/DFS pin synchronizes the read and write data

presented to the ADC. The SDIO/DCS dual-purpose pin allows

data to be sent and read from the internal ADC memory map

registers. The CSB pin is an active low control that enables or

disables the read and write cycles.

Table 14. SPI Timing Diagram Specifications

Name Description

t_DS

t_DH

t_CLK

t_S

Setup time between data and rising edge of SCLK

Hold time between data and rising edge of SCLK

Period of the clock

Setup time between CSB and SCLK

Table 13. Serial Port Interface Pins

Mnemonic Description

t_H

Hold time between CSB and SCLK

t_HI

t_LO

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

SCLK/DFS

SCLK (Serial Clock) is the serial shift clock in. SCLK

synchronizes serial interface reads and writes.

SDIO/DCS

SDIO (Serial Data Input/Output) is a dual-purpose

pin. The typical role for this pin is an input and

output depending on the instruction being sent

and the relative position in the timing frame.

HARDWARE INTERFACE

The pins described in Table 13 comprise the physical interface

between the user’s programming device and the serial port of

the AD9233. The SCLK and CSB pins function as inputs when

using the SPI interface. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during readback.

CSB

CSB (Chip Select Bar) is an active low control that

gates the read and write cycles.

The falling edge of the CSB in conjunction with the rising edge

of the SCLK determines the start of the framing. Figure 57 and

Table 14 provide an example of the serial timing and its

definitions.

The SPI interface is flexible enough to be controlled by either

PROM or PIC microcontrollers. This provides the user with the

ability to use an alternate method to program the ADC. One

method is described in detail in the Application Note AN-812.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, permanently enabling the device (this is

called streaming). The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high

during power up, SPI functions are placed in a high impedance

mode. This mode turns on any SPI pin secondary functions. If

CSB is high at power up and then brought low to activate the

SPI, the SPI pin secondary functions are no longer available,

unless the device power is cycled.

When the SPI interface is not used, some pins serve a dual

function. When strapped to AVDD or ground during device

power on, the pins are associated with a specific function.

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DCS and SCLK/DFS pins serve as standalone CMOS-

compatible control pins. When the device is powered up with

the CSB chip select connected to AVDD, the serial port interface is

disabled. In this mode, it is assumed that the user intends to use

the pins as static control lines for the output data format and

duty cycle stabilizer (see Table 10). For more information, see

the Interfacing to High Speed ADCs via SPI User Manual.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase and the length is determined

by the W0 bit and the W1 bit. All data is composed of 8-bit

words. The first bit of each individual byte of serial data indicates

whether a read or write command is issued. This allows the

serial data input/output (SDIO) pin to change direction from

an input to an output.

Rev. A | Page 23 of 44

AD9233

MEMORY MAP

READING THE MEMORY MAP TABLE

Logic Levels

An explanation of two registers follows:

Each row in the memory map table has eight address locations.

The memory map is roughly divided into three sections: chip

configuration registers map (Address 0x00 to Address 0x02),

device index and transfer registers map (Address 0xFF), and

ADC functions map (Address 0x08 to Address 0x18).

•

Bit is set is synonymous with bit is set to Logic 1 or writing

Logic 1 for the bit.

•

Clear a bit is synonymous with bit is set to Logic 0 or

writing Logic 0 for the bit.

The memory map register in Table 15 displays the register

address number in hexadecimal in the first column. The last

column displays the default value for each hexadecimal address.

The Bit 7 (MSB) column is the start of the default hexadecimal

value given. For example, Hexadecimal Address 0x14,

output_phase has a hexadecimal default value of 0x00. This

means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or 0011 in

binary. This setting is the default output clock or DCO phase

adjust option. The default value adjusts the DCO phase 90°

relative to the nominal DCO edge and 180° relative to the data

edge. For more information on this function, consult the

Interfacing to High Speed ADCs via SPI User Manual.

SPI-Accessible Features

A list of features accessible via the SPI and a brief description of

what the user can do with these features follows. These features

are described in detail in the Interfacing to High Speed ADCs via

SPI User Manual.

•

Modes: Set either power-down or standby mode.

Clock: Access the DCS via the SPI.

Offset: Digitally adjust the converter offset.

Test I/O: Set test modes to have known data on output bits.

Open Locations

Locations marked as open are currently not supported for this

device. When required, these locations should be written with

0s. Writing to these locations is required only when part of an

address location is open (for example, Address 0x14). If the

entire address location is open (Address 0x13), then the address

location does not need to be written.

Output Mode: Setup outputs, vary the strength of the

output drivers.

•

Output Phase: Set the output clock polarity.

VREF: Set the reference voltage.

Default Values

Coming out of reset, critical registers are loaded with default

values. The default values for the registers are provided in Table 15.

t_DS

t_HI

t_CLK

t_H

t_S

t_DH

t_LO

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 57. Serial Port Interface Timing Diagram

Rev. A | Page 24 of 44

AD9233

Table 15. Memory Map Register

Default Default

Addr Parameter

(Hex) Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

±±

chip_port_config

±

LSB

First

Soft

Reset

1

Soft

Reset

LSB

First

±

±x1ꢁ

The nibbles

should be

mirrored. See

Interfacing to

High Speed

ADCs via SPI

User Manual.

± = Off

(Default) (Default)

1 = On

± = Off

(Default) (Default)

1 = On

± = Off

1 = On

±1

±2

chip_id

ꢁ-Bit Chip ID Bits ꢂ:±

(ADꢃ233 = ±x±±), (Default)

Read-

Only

Default is

unique chip ID,

different for

each device.

chip_grade

Open

Child ID

± =

Open

Read-

Only

Child ID used

to differentiate

speed grades.

12ꢀ

MSPS,

1 =

1±ꢀ

MSPS

Device Index and Transfer Registers

FF

device_update

Open

SW Transfer ±x±±

Synchronously

transfers data

from the

master

shift register to

the slave.

Global ADC Functions

±ꢁ modes

Open

PDWN

±—Full

1—

Internal Power-Down Mode

±±±—Normal (Power-Up)

±±1—Full Power-Down

±1±—Standby

±11—Normal (Power-Up)

Note: External PDWN pin

overrides this setting.

±x±±

Determines

various generic

modes of chip

operation. See

Power

Dissipation

and Standby

Mode and

Standby

SPI-Accessible

Features

sections.

±ꢃ

clock

Open

Duty Cycle

Stabilizer

±—

Disabled

1—Enabled

±x±1

±x±±

See Clock Duty

Cycle and

SPI-Accessible

Features

sections.

Flexible ADC Functions

1± offset

Digital Offset Adjust <5:0>

Offset in LSBs

+ꢂ 3/4

+ꢂ 1/2

Adjustable for

offset inherent

in the

converter.

See SPI-

±11111

±1111±

±111±1

…

+ꢂ 1/4

Accessible

Features

section.

±±±±1±

±±±±±1

±±±±±±

111111

11111±

1111±1

...

+1/2

+1/4

±

−1/4

−1/2

−3/4

1±±±±1

1±±±±±

−ꢂ 3/4

−ꢁ

Rev. A | Page 2ꢀ of 44

AD9233

Default Default

Addr Parameter

(Hex) Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

±D

test_io

PN23

± =

Normal

1 =

PNꢃ

± =

Normal

1 =

Reset

Global Output Test Options

±±±—Off

±±1—Midscale Short

±1±— +FS Short

±x±±

See the

Interfacing to

High Speed

ADCs via SPI

User Manual.

Reset

±11— −FS Short

1±±—Checker Board Output

1±1—PN 23 Sequence

11±—PN ꢃ

111—One/Zero Word Toggle

14

output_mode

Output Driver

Configuration

±± for DRVDD = 3.3 V

1± for DRVDD = 1.ꢁ V

Open

Output

Disable

1—

Open

Output

Data

Invert

1 =

Data Format Select

±±—Offset Binary

(Default)

±1—Twos

Complement

1±—Gray Code

±x±±

Configures the

outputs and

the format of

the data and

the output

driver

Disabled

±—

Invert

Enabled¹

strength.

16

1ꢁ

output_phase

VREF

DCO

Polarity

1 = Inverted

± = Normal

Open

±x±±

±xC±

See SPI-

Accessible

Features

section.

Internal Reference

Resistor Divider

±±—VREF = 1.2ꢀ V

±1—VREF = 1.ꢀ V

1±—VREF = 1.ꢂꢀ V

11—VREF = 2.±± V

Open

See SPI-

Accessible

Features

section.

¹External Output Enable (OEB) pin must be high.

Rev. A | Page 26 of 44

AD9233

LAYOUT CONSIDERATIONS

POWER AND GROUND RECOMMENDATIONS

When connecting power to the AD9233, it is recommended

that two separate supplies be used: one for analog (AVDD, 1.8 V

nominal) and one for digital (DRVDD, 1.8 V to 3.3 V nominal).

If only a single 1.8 V supply is available, then it should be routed

to AVDD first, then tapped off and isolated with a ferrite bead

or filter choke with decoupling capacitors preceding its con-

nection to DRVDD. The user can employ several different

decoupling capacitors to cover both high and low frequencies.

These should be located close to the point of entry at the PC

board level and close to the parts with minimal trace length.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 58. Typical PCB Layout

CML

The CML pin should be decoupled to ground with a 0.1 μF

capacitor, as shown in Figure 38.

A single PC board ground plane should be sufficient when

using the AD9233. With proper decoupling and smart parti-

tioning of the analog, digital, and clock sections of the board,

optimum performance is easily achieved.

RBIAS

The AD9233 requires the user to place a 10 kΩ resistor between

the RBIAS pin and ground. This resister sets the master current

reference of the ADC core and should have at least a 1% tolerance.

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the

ADC is connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9233. An

exposed, continuous copper plane on the PCB should mate to

the AD9233 exposed paddle, Pin 0. The copper plane should

have several vias to achieve the lowest possible resistive thermal

path for heat dissipation to flow through the bottom of the PCB.

These vias should be solder filled or plugged.

REFERENCE DECOUPLING

The VREF pin should be externally decoupled to ground with a

low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low

ESR capacitor. In all reference configurations, REFT and REFB

are bypass points provided for reducing the noise contributed

by the internal reference buffer. It is recommended to place an

external 0.1 ꢀF ceramic capacitor across REFT/REFB. While it is

not required to place this 0.1 ꢀF capacitor, the SNR performance

will degrade by approximately 0.1 dB without it. All reference

decoupling capacitors should be placed as close to the ADC as

possible with minimal trace lengths.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous plane by overlaying a silkscreen

on the PCB into several uniform sections. This provides several

tie points between the two during the reflow process. Using one

continuous plane with no partitions only guarantees one tie

point between the ADC and PCB. See Figure 58 for a PCB

layout example. For detailed information on packaging and the

PCB layout of chip scale packages, see Application Note AN-772,

A Design and Manufacturing Guide for the Lead Frame Chip

Scale Package (LFCSP).

Rev. A | Page 2ꢂ of 44

AD9233

EVALUATION BOARD

The AD9233 evaluation board provides all of the support

circuitry required to operate the ADC in its various modes and

configurations. The converter can be driven differentially

through a double balun configuration (default) or through the

AD8352 differential driver. The ADC can also be driven in a

single-ended fashion. Separate power pins are provided to

isolate the DUT from the AD8352 drive circuitry. Each input

configuration can be selected by proper connection of various

components. Figure 59 shows the typical bench characterization

setup used to evaluate the ac performance of the AD9233.

Although at least one 1.8 V supply is needed with a 1 A current

capability for AVDD_DUT and DRVDD_DUT, it is recom-

mended that separate supplies be used for analog and digital.

To operate the evaluation board using the AD8352 option, a

separate 5.0 V analog supply is needed. The 5.0 V supply, or

AMP_VDD, should have a 1 A current capability. To operate

the evaluation board using the alternate SPI options, a separate

3.3 V analog supply is needed in addition to the other supplies.

The 3.3 V supply (AVDD_3.3V) should have a 1 A current

capability as well. Solder Jumpers J501, J502, and J505 allow the

user to combine these supplies. See Figure 64 for more details.

It is critical that the signal sources used for the analog input and

clock have very low phase noise (<1 ps rms jitter) to realize the

optimum performance of the converter. Proper filtering of the

analog input signal to remove harmonics and lower the inte-

grated or broadband noise at the input is also necessary to achieve

the specified noise performance.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal

generators with low phase noise, such as Rohde & Schwarz SMHU

or Agilent HP8644 signal generators or the equivalent. Use one

meter long, shielded, RG-58, 50 Ω coaxial cables for making

connections to the evaluation board. Enter the desired frequency

and amplitude for the ADC. Typically, most ADI evaluation

boards can accept a ~2.8 V p-p or 13 dBm sine wave input for

the clock. When connecting the analog input source, it is

recommended to use a multipole, narrow-band, band-pass

filter with 50 Ω terminations. Analog Devices uses TTE®, Allen

Avionics, and K&L® types of band-pass filters. Connect the filter

directly to the evaluation board, if possible.

See Figure 60 to Figure 70 for the complete schematics and

layout diagrams that demonstrate the routing and grounding

techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching

power supply that provides a 6 V, 2 A maximum output. Simply

connect the supply to the rated 100 V ac to 240 V ac wall outlet

at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter

jack that connects to the PCB at P500. Once on the PC board,

the 6 V supply is fused and conditioned before connecting to

five low dropout linear regulators that supply the proper bias to

each of the various sections on the board. When operating the

evaluation board in a nondefault condition, L501, L503, L504,

L508, and L509 can be removed to disconnect the switching

power supply. This enables the user to bias each section of the

board independently. Use P501 to connect a different supply for

each section.

OUTPUT SIGNALS

The parallel CMOS outputs interface directly with Analog

Devices’ standard single-channel FIFO data capture board

(HSC-ADC-EVALB-SC). For more information on the FIFO

boards and their optional settings, visit www.analog.com/FIFO.

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz

6V DC

2A MAX

5.0V

1.8V

2.5V

3.3V

–

+

–

+

–

+

–

+

–

+

–

+

SWITCHING

POWER

SUPPLY

PC

RUNNING

ADC

ANALYZER

AND SPI

USER

ROHDE & SCHWARZ,

HSC-ADC-EVALB-SC

FIFO DATA

SMHU,

2V p-p SIGNAL

SYNTHESIZER

BAND-PASS

FILTER

AIN

CAPTURE

BOARD

AD9233

12-BIT

EVALUATION BOARD

SOFTWARE

PARALLEL

CMOS

USB

CONNECTION

ROHDE & SCHWARZ,

SMHU,

CLK

2V p-p SIGNAL

SYNTHESIZER

SPI

Figure 59. Evaluation Board Connection

Rev. A | Page 2ꢁ of 44

AD9233

SCLK/DFS

DEFAULT OPERATION AND JUMPER SELECTION

SETTINGS

If the SPI port is in external pin mode, the SCLK/DFS pin sets the

data format of the outputs. If the pin is left floating, the pin is

internally pulled down, setting the default condition to binary.

Connecting JP2 Pin 2 and Pin 3 sets the format to twos

complement. If the SPI port is in serial pin mode, connecting

JP2 Pin 1 and Pin 2 connects the SCLK pin to the on board

SPI circuitry. See the Serial Port Interface (SPI) section for

more details.

The following is a list of the default and optional settings or

modes allowed on the AD9233 Rev. A evaluation board.

POWER

Connect the switching power supply that is supplied in the

evaluation kit between a rated 100 V ac to 240 V ac wall outlet

at 47 Hz to 63 Hz and P500.

VIN

SDIO/DCS

The evaluation board is set up for a double balun configuration

analog input with optimum 50 Ω impedance matching out to

70 MHz. For more bandwidth response, the differential capacitor

across the analog inputs can be changed or removed (see Table 8).

The common mode of the analog inputs is developed from the

center tap of the transformer via the CML pin of the ADC. See

the Analog Input Considerations section for more information.

If the SPI port is in external pin mode, the SDIO/DCS pin acts

to set the duty cycle stabilizer. If the pin is left floating, the pin is

internally pulled up, setting the default condition to DCS enabled.

To disable the DCS, connect JP3 Pin 2 and Pin 3. If the SPI port

is in serial pin mode, connecting JP3 Pin 1 and Pin 2 connects the

SDIO pin to the on-board SPI circuitry. See the Serial Port

Interface (SPI) section for more details.

VREF

ALTERNATIVE CLOCK CONFIGURATIONS

VREF is set to 1.0 V by tying the SENSE pin to ground via

JP507 (Pin 1 and Pin 2). This causes the ADC to operate in

2.0 V p-p full-scale range. A separate external reference option

is also included on the evaluation board. Simply connect JP507

between Pin 2 and Pin 3, connect JP501, and provide an external

reference at E500. Proper use of the VREF options is detailed in

the Voltage Reference section.

A differential LVPECL clock can also be used to clock the ADC

input using the AD9515 (U500). When using this drive option,

the components listed in Table 16 need to be populated.

Consult the AD9515 data sheet for further information.

To configure the analog input to drive the AD9515 instead of

the default transformer option, the following components need

to be added, removed, and/or changed.

RBIAS

•

Remove R507, R508, C532, and C533 in the default

clock path.

RBIAS requires a 10 kΩ (R503) to ground and is used to set the

ADC core bias current.

Populate R505 with a 0 Ω resistor and C531 in the default

clock path.

CLOCK

The default clock input circuitry is derived from a simple

transformer-coupled circuit using a high bandwidth 1:1

impedance ratio transformer (T503) that adds a very low

amount of jitter to the clock path. The clock input is 50 Ω

terminated and ac-coupled to handle single-ended sine wave

inputs. The transformer converts the single-ended input to a

differential signal that is clipped before entering the ADC

clock inputs.

Populate R511, R512, R513, R515 to R524, U500, R580,

R582, R583, R584, C536, C537, and R586.

If using an oscillator, two oscillator footprint options are also

available (OSC500) to check the performance of the ADC.

JP508 provides the user flexibility in using the enable pin, which

is common on most oscillators. Populate OSC500, R575, R587,

and R588 to use this option.

PDWN

To enable the power-down feature, connect JP506, shorting the

PDWN pin to AVDD.

CSB

The CSB pin is internally pulled-up, setting the chip into

external pin mode, to ignore the SDIO and SCLK information.

To connect the control of the CSB pin to the SPI circuitry on the

evaluation board, connect JP1 Pin 1 and Pin 2. To set the chip

into serial pin mode and to enable the SPI information on the

SDIO and SCLK pins, tie JP1 low (connect Pin 2 and Pin 3) in

the always enabled mode.

Rev. A | Page 2ꢃ of 44

AD9233

To configure the analog input to drive the AD8352 instead of

the default transformer option, the following components need

to be added, removed and/or changed:

ALTERNATIVE ANALOG INPUT DRIVE

CONFIGURATION

This section provides a brief description of the alternative

analog input drive configuration using the AD8352 . When

using this particular drive option, some components need to be

populated as listed in Table 16. For more details on the AD8352

differential driver, including how it works and its optional pin

settings, consult the AD8352 data sheet.

•

Remove C1 and C2 in the default analog input path.

Populate R3 and R4 with 200 Ω resistors in the analog

input path.

•

Populate the optional amplifier input path with all

components, except R594, R595, and C502. Note that to

terminate the input path, only one of these components,

(R9, R592, or R590 and R591) should be populated.

•

Populate C529 with a 5 pF capacitor in the analog

input path.

Currently, R561 and R562 are populated with 0 Ω resistors to

allow signal connection. This area allows the user to design a

filter if additional requirements are necessary.

Rev. A | Page 3± of 44

AD9233

SCHEMATICS

8 5 0 2 - 4 9 0 5

2 1 8 2 S M H S

0 4 0 R 2 C

2 1 8 2 S M H S

0 4 0 R 2 C

RC040

2

RC0402

0 4 0 R 2 C

4 0 2 C R

0 4 0 C 2 C

4 0 2 C C 0

0 2 0 4 C C

0 4 0 C 2 C

RC0603

RC060

3

RC060

3

RC0603

Figure 60. Evaluation Board Schematic, DUT Analog Inputs

Rev. A | Page 31 of 44

AD9233

9

0 - 5 2 4 5 9 0

RC060 3

Figure 61. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface

Rev. A | Page 32 of 44

AD9233

0 5 7 5 4 0 9 2 -

0 4 C 0 C 2

4 0 2 C C

0 2 0 4 C C

0 4 C 0 C 2

2

0 4 C 0 R

4 0 2 C R

0 4 C 0 R 2

0 4 C 0 C 2

2

0 4 C 0 C

0 4 C 0 R 2

S 1 0

S 9

2 5

1 6

1 5

1 4

1 3

1 2

1 1

1 0

9

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

S 8

S 7

33

31

GND_PAD

GN D

S 6

S 5

S 4

S 3

S 2

S 1

8

S 0

7

S10

F E V R

6

32

RSET

0 4 C 0 R 2

2

0 4 C 0 R

0 4 C 0 R 2

4 0 2 C R

0 4 C 0 R 2

4 0 2 C R

RC0603

0 4 C 0 C 2

2

0 4 C 0 C

RC060 3

Figure 62. Evaluation Board Schematic, DUT Clock Inputs

Rev. A | Page 33 of 44

AD9233

0 5 6 9 2 - 5 4

3 0 6

R C 0

RC0603

3 0 6

R C 0

3

0 6 C 0 R

0 3 0 6 C R

3

0 6 C 0 R

SDO_CHA

3

0 6 C 0 R

CSB1_CHA

SDI_CHA

SCLK_CHA

_PICVCC1

2

PICVCC

3

4

GP1

5

6

GP0

_MCLR-GP37

9

8

MCLR-GP3

10

3

0 6 C 0 R

Figure 63. Evaluation Board Schematic, SPI Circuitry

Rev. A | Page 34 of 44

AD9233

5 0 5 9 2 - 0 5 4

9 0 5 T P

2 1 5 T P

1 1 5 T P

0 1 5 T P

D

G N

D G N

1

D

G N

D

G N

D G N

1

CR500

1

2

Figure 64. Evaluation Board Schematic, Power Supply Inputs

Rev. A | Page 3ꢀ of 44

AD9233

EVALUATION BOARD LAYOUTS

Figure 65. Evaluation Board Layout, Primary Side

Figure 66. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. A | Page 36 of 44

AD9233

Figure 67. Evaluation Board Layout, Ground Plane

Figure 68. Evaluation Board Layout, Power Plane

Rev. A | Page 3ꢂ of 44

AD9233

Figure 69. Evaluation Board Layout, Silkscreen Primary Side

Figure 70. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image)

Rev. A | Page 3ꢁ of 44

AD9233

BILL OF MATERIALS (BOM)

Table 16. Evaluation Board BOM

Omit

Item Qty. (DNI) Reference Designator

Device

PCB

Package

Description

PCB

Supplier/Part No.

1

2

1

ADꢃ246CE_REVA

Analog Devices, Inc.

24

C1, C2, Cꢀ±ꢃ, Cꢀ1±, Cꢀ11, Cꢀ12,

Capacitors

±4±2

±.1 ꢄF

Cꢀ14, Cꢀ1ꢀ, Cꢀ16, Cꢀ1ꢂ, Cꢀ2ꢁ, Cꢀ3±,

Cꢀ32, Cꢀ33, Cꢀ3ꢁ, Cꢀ3ꢃ, Cꢀ4±, Cꢀ42,

Cꢀ43, Cꢀ44, Cꢀ4ꢀ, Cꢀ46, Cꢀꢀ4, Cꢀꢀꢀ

12

C3, Cꢀ±±, Cꢀ±2, Cꢀ±3, Cꢀ±4, Cꢀ±ꢀ,

Cꢀ31, Cꢀ34, Cꢀ3ꢀ, Cꢀ36, Cꢀ3ꢂ, Cꢀꢀꢂ

3

4

ꢀ

1

2

Cꢀ±1

Capacitor

Resistors

Capacitors

±4±2

±.3 pF

± Ω

C4, Cꢀ

1±

Cꢀ13, Cꢀ1ꢁ, Cꢀ1ꢃ, Cꢀ2±, Cꢀ21,

Cꢀ22, Cꢀ23, Cꢀ24, Cꢀ2ꢀ, Cꢀ26

1.± ꢄF

6

1

Cꢀ2ꢂ

Capacitor

Capacitors

Capacitor

Capacitors

12±6

±4±2

ACASE

±ꢁ±ꢀ

±6±3

1± ꢄF

2± pF

1± ꢄF

1.± ꢄF

±.1 ꢄF

ꢂ

1

Cꢀ2ꢃ

ꢁ

ꢀ

Cꢀ4ꢁ, Cꢀ4ꢃ, Cꢀꢀ±, Cꢀꢀ1, Cꢀꢀ2

Cꢀꢀ3

ꢃ

1

1±

1ꢀ

Cꢀꢀ6, Cꢀꢀꢁ, Cꢀꢀꢃ, Cꢀ64, Cꢀ6ꢀ,

Cꢀ66, Cꢀ6ꢂ, Cꢀ6ꢁ, Cꢀ6ꢃ, Cꢀꢂ±,

Cꢀꢂ2, Cꢀꢂ3, Cꢀꢂ4, Cꢀꢂꢀ, Cꢀꢃꢃ

11

12

1

CRꢀ±±

LED

±6±3

Green

Panasonic

LNJ314GꢁTRA

Dꢀ±2

Diode

SOT-23

3± V, 2± mA,

HSMS2ꢁ12

dual Schottky

2

1

Dꢀ±±, Dꢀ±1

Dꢀ±3

Diodes

Diode

13

14

1

DO-214AB

3 A, 3± V, SMC

Micro Commercial Group

SK33-TPMSCT-ND

Dꢀ±4

Diode

DO-214AA 2 A, ꢀ± V, SMC

Micro Commercial Group

S2A-TPMSTR-ND

1ꢀ

16

Dꢀ±ꢀ

Fꢀ±±

LED

LN1461C

121±

AMB

Amber LED

1

Fuse

6.± V, 2.2 A trip

current resettable

fuse

Tyco, Raychem

NANO SMDC11±F-2

1ꢂ

FERꢀ±±

Choke

2±2±

Murata

DLWꢀBSN1ꢃ1SQ2

1ꢁ

1ꢃ

2±

1

3

Jꢀ±±

Jumper

Solder jumper

Male header

Jꢀ±1, Jꢀ±2, Jꢀ±ꢀ

Jꢀ±3

Jumpers

Connector

1

12± Pin

Samtec

TSW-14±-±ꢁ-G-T-RA

21

22

1

Jꢀ±4

Connector

Jumpers

1± Pin

3 Pin

Male, 2 × ꢀ

Samtec

3

4

1

JP1, JP2, JP3

Male, straight

Samtec

TSW-1±3-±ꢂ-G-S

23

24

JPꢀ±±, JPꢀ±1, JPꢀ±2, JPꢀ±6

JPꢀ±ꢂ

Jumpers

2 Pin

3 Pin

Male, straight

Samtec

TSW-1±2-±ꢂ-G-S

Samtec

TSW-1±3-±ꢂ-G-S

2

JPꢀ±ꢁ, JPꢀ±ꢃ

2ꢀ

26

1±

1

Lꢀ±±, Lꢀ±1, Lꢀ±2, Lꢀ±3, Lꢀ±4,

Lꢀ±ꢀ, Lꢀ±6, Lꢀ±ꢂ, Lꢀ±ꢁ, Lꢀ±ꢃ

Ferrite Beads 3.2 mm ×

2.ꢀ mm ×

Digi-Key Pꢃꢁ11CT-ND

CTS Reeves CB3LV-3C

1.6 mm

1

OSCꢀ±±

Oscillator

SMT

12ꢀ MHz or

1±ꢀ MHz

2ꢂ

2ꢁ

Pꢀ±±

Pꢀ±1

Connector

PJ-1±2A

1± Pin

DC power jack

Male, straight

Digi-Key CP-1±2A-ND

PTMICRO1±

Rev. A | Page 3ꢃ of 44

AD9233

Omit

Item Qty. (DNI) Reference Designator

Device

Package

±4±2

Description

DNI

Supplier/Part No.

2ꢃ

3±

6

R1, R6, Rꢀ63, Rꢀ6ꢀ, Rꢀꢂ4, Rꢀꢂꢂ

R2, Rꢀ, Rꢀ61, Rꢀ62, Rꢀꢂ1

R1±, R11, R12, Rꢀ3ꢀ, Rꢀ36, Rꢀꢂꢀ

R3, R4

Resistors

Resistor

Resistors

ꢀ

2

±4±2

± Ω

6

31

32

33

34

3ꢀ

±4±2

±6±3

±4±2

±6±3

2ꢀ Ω

DNI

6

Rꢂ, Rꢁ, Rꢃ, Rꢀ±2, Rꢀ1±, Rꢀ11

Rꢀ±±, Rꢀ±1, Rꢀꢂ6, Rꢀꢂꢁ, Rꢀꢂꢃ, Rꢀꢁ1

Rꢀ±3, Rꢀ4ꢁ, Rꢀ4ꢃ, Rꢀꢀ±

Rꢀ±4

DNI

4

1

1± kΩ

4ꢃ.ꢃ Ω

1

Rꢀ±ꢀ

36

ꢃ

Rꢀ±6, Rꢀ±ꢁ, Rꢀ±ꢃ, Rꢀ12, Rꢀꢀ4,

Rꢀꢀꢀ, Rꢀꢀ6, Rꢀꢀꢂ, Rꢀ6±

±6±3

± Ω

23

Rꢀ±ꢂ, Rꢀ14, Rꢀ13, Rꢀ1ꢀ, Rꢀ16, Rꢀ1ꢂ,

Rꢀ1ꢁ, Rꢀ1ꢃ, Rꢀ2±, Rꢀ21, Rꢀ22, Rꢀ23,

Rꢀ24, Rꢀ2ꢀ, Rꢀ26, Rꢀ2ꢂ, Rꢀ2ꢁ, Rꢀ2ꢃ,

Rꢀ3±, Rꢀ31, Rꢀ32, Rꢀ33, Rꢀ34

3ꢂ

3ꢁ

3ꢃ

4

1

Rꢀ4ꢀ, Rꢀ46, Rꢀ4ꢂ, Rꢀꢀꢁ

Rꢀꢀ1, Rꢀꢀ2, Rꢀꢀ3

Rꢀꢁꢃ

Resistors

±6±3

4.ꢂ kΩ

1 kΩ

3

1

261 Ω

Rꢀꢀꢃ

4±

41

42

43

44

4ꢀ

46

4ꢂ

4ꢁ

4ꢃ

ꢀ±

ꢀ1

ꢀ2

2

Rꢀ66, Rꢀ6ꢂ

Rꢀꢁ2, Rꢀꢁꢀ, Rꢀꢃꢁ

Rꢀꢁ3, Rꢀꢁ4

Rꢀꢁ6

Resistors

Resistor

Resistors

Resistor

Resistors

Resistor

Resistors

Switch

±4±2

33 Ω

3

2

1

3

2

1

2

1

±4±2

1±± Ω

24± Ω

4.12 kΩ

1± kΩ

2ꢀ Ω

±4±2

Rꢀꢁ±, Rꢀꢁꢂ, Rꢀꢁꢁ

Rꢀꢃ±, Rꢀꢃ1

Rꢀꢃ2

±4±2

DNI

Rꢀꢃ3, Rꢀꢃ6

Rꢀꢃ4, Rꢀꢃꢀ

Rꢀꢃꢂ

±4±2

± Ω

±4±2

1± kΩ

4.3 kΩ

22 Ω

±4±2

1

2

RPꢀ±±

RCAꢂ42±4

RCAꢂ42±ꢁ

RPꢀ±1, RPꢀ±2

S1

22 Ω

1

Momentary

Panasonic

(normally open)

EVQ-PLDA1ꢀ

ꢀ3

2

Sꢀ±±, Sꢀ±1

Connectors

SMAEDGE

SMA edge

right angle

2

Sꢀ±2, Sꢀ±3

Sꢀ±4, Sꢀ±ꢀ

ꢀ4

ꢀꢀ

SMA2±±UP SMA RF

ꢀ-pin upright

2

1

Tꢀ±±, Tꢀ±1

T1

Transformers SM-22

M/A-Com ETC1-1-13

1

ꢀ6

ꢀꢂ

Tꢀ±3

Transformer

IC

CDꢀ42

Mini-Circuits

ADT1-1WT

1

Tꢀ±2

Uꢀ±±

32-Lead

LFCSP

Clock distribution Analog Devices, Inc.

ADꢃꢀ1ꢀBCPZ

ꢀꢁ

ꢀꢃ

6±

61

1

2

Uꢀ±1

IC

SOT-223

Voltage regulator Analog Devices, Inc.

ADP333ꢃAKCZ-ꢀ

Uꢀ±2

IC

Voltage regulator Analog Devices, Inc.

ADP333ꢃAKCZ-1.ꢁ

Uꢀ±3

IC

Voltage regulator Analog Devices, Inc.

ADP333ꢃAKCZ-2.ꢀ

Uꢀ±4, Uꢀ±ꢀ

ICs

Voltage regulator Analog Devices, Inc.

ADP333ꢃAKCZ-3.3

Rev. A | Page 4± of 44

AD9233

Omit

Item Qty. (DNI) Reference Designator

Device

Package

Description

Supplier/Part No.

62

1

Uꢀ±6

IC

ꢁ-pin SOIC

ꢁ-bit

Microchip PIC12F62ꢃ

microcontroller

63

64

6ꢀ

1

Uꢀ±ꢂ

Uꢀ±ꢁ

Uꢀ±ꢃ

IC

SCꢂ±

Dual buffer

Fairchild NCꢂWZ16

Fairchild NCꢂWZ±ꢂ

Fairchild ꢂ4VCX162244

Dual buffer

4ꢁ-Lead

TSSOP

Buffer/line driver

66

6ꢂ

1

Uꢀ1±

DUT

(ADꢃ233)

4ꢁ-Lead

LFCSP

ADC

Analog Devices, Inc.

ADꢃ233BCPZ

1

Uꢀ11 (or Zꢀ±±)

IC

16-Lead

LFCSP

Differential

amplifier

Analog Devices, Inc.

ADꢁ3ꢀ2ACPZ

Total 128 107

Rev. A | Page 41 of 44

AD9233

OUTLINE DIMENSIONS

0.30

0.23

0.18

7.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

37

36

48

1

PIN 1

INDICATOR

EXPOSED

PAD

(BOTTOM VIEW)

4.25

4.10 SQ

3.95

TOP

VIEW

6.75

BSC SQ

0.50

0.40

0.30

25

24

12

13

0.25 MIN

5.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.50 BSC

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 71. 48-Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

–4±°C to +ꢁꢀ°C

Package Description

Package Option¹

CP-4ꢁ-3

ADꢃ233BCPZ-12ꢀ²

ADꢃ233BCPZRLꢂ–12ꢀ²

ADꢃ233BCPZ-1±ꢀ²

ADꢃ233BCPZRLꢂ–1±ꢀ²

ADꢃ233BCPZ-ꢁ±²

ADꢃ233BCPZRLꢂ–ꢁ±²

ADꢃ233-12ꢀEB

4ꢁ-Lead Lead Frame Chip Scale Package [LFSCP_VQ]

Evaluation Board

ADꢃ233-1±ꢀEB

Evaluation Board

ADꢃ233-ꢁ±EB

Evaluation Board

¹It is required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance .

²Z = Pb-free part.

Rev. A | Page 42 of 44

AD9233

NOTES

Rev. A | Page 43 of 44

AD9233

NOTES

registered trademarks are the property of their respective owners.

D05492-0-8/06(A)

Rev. A | Page 44 of 44


型号：	AD9233
厂家：	ADI
描述：	12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter 12位， 80 MSPS / 105 MSPS / 125 MSPS ， 1.8 V模拟数字转换器转换器
文件：	总44页 (文件大小：1243K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9233 [ADI]

相关型号：

AD9233-105EB

AD9233-125EB

AD9233-80EB

AD9233BCPZ-105

AD9233BCPZ-125

AD9233BCPZ-80

AD9233BCPZRL7-105

AD9233BCPZRL7-125

AD9233BCPZRL7-80

AD9234

AD9234-1000EBZ

AD9234-500EBZ