AD9238 [ADI]
12-Bit, 20/40/65 MSPS Dual A/D Converter; 12位20/40/65 MSPS双通道A / D转换器
| 型号： | AD9238 |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 20/40/65 MSPS Dual A/D Converter |
| 文件： | 总24页 (文件大小：1704K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 20/40/65 MSPS
Dual A/D Converter
AD9238
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Integrated Dual 12-Bit Analog-to-Digital Converters
Single 3V Supply Operation (2.7V to 3.6V)
SNR = 70 dBc (to Nyquist, AD9238-65)
SFDR = 85 dBc (to Nyquist, AD9238-65)
Low Power: 600 mW at 65 MSPS
Differential Input with 500 MHz 3 dB Bandwidth
On-Chip Reference and SHA
Flexible Analog Input: 1V p-p to 2V p-p Range
Offset Binary orTwos Complement Data Format
Clock Duty Cycle Stabilizer
AVDD
DRVDD
OEB_A
OTR_A
VIN+_A
VIN–_A
A/D
SHA
D11_A
D0_A
REFT_A
REFB_A
MUX_SELECT
CLK_A
CLOCK
DUTY CYCLE
STABILIZER
VREF
CLK_B
DCS
SENSE
DFS
0.5V
PDWN_A
PDWN_B
SHARED_REF
MODE
SELECT
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
IS-95, CDMA One, IMT-2000
Battery-Powered Instruments
Hand-Held Scopemeters
AGND
REFB_B
REFT_B
OEB_B
OTR_B
D11_B
D0_B
VIN–_B
VIN+_B
A/D
SHA
Low Cost Digital Oscilloscopes
AGND
DRGND
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. Integrated, dual version of the AD9235—a 12-bit,
20 MSPS/40 MSPS/65 MSPS ADC.
The AD9238 is a dual, 3V, 12-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter. It features dual high performance
sample-and-hold amplifiers and an integrated voltage reference.
The AD9238 uses a multistage differential pipelined architecture
with output error correction logic to provide 12-bit accuracy and
guarantee no missing codes over the full operating temperature
range at data rates up to 65 MSPS.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to suit
an application.
3. The AD9238 operates from a single 3V power supply and
features a separate digital output driver supply to accommo-
date 2.5V and 3.3V logic families.
The wide bandwidth, differential SHA allows for a variety of
user selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including multi-
plexed systems that switch full-scale voltage levels in successive
channels and for sampling inputs at frequencies well beyond the
Nyquist rate.The AD9238 is suitable for applications in commu-
nications, imaging, and medical ultrasound.
4. Low power consumption:
AD9238-20 operating at 20 MSPS consumes a low 180 mW.
AD9238-40 operating at 40 MSPS consumes a low 330 mW.
AD9238-65 operating at 65 MSPS consumes a low 600 mW.
5. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
Dual single-ended clock inputs are used to control all internal con-
version cycles. A duty cycle stabilizer is available on the AD9238-65
and can compensate for wide variations in the clock duty cycle,
allowing the converters to maintain excellent performance.The
digital output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to deter-
mine low or high overflow.
6. Typical channel isolation of 80 dB @ fIN = 10 MHz.
7. The clock duty cycle stabilizer (AD9238-65 only) maintains
performance over a wide range of clock duty cycles.
8. The OTR output bits indicate when either input signal is
beyond the selected input range.
9. Multiplexed data output option enables single-port operation
from either data port A or data port B.
Fabricated on an advanced CMOS process, the AD9238 is avail-
able in a space saving 64-lead LQFP and is specified over the
industrial temperature range (–40°C to +85°C).
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9238–SPECIFICATIONS
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input,
1.0 V Internal Reference, TMIN to TMAX, unless otherwise noted.)
DC SPECIFICATIONS
Test
AD9238BST-20
AD9238BST-40
AD9238BST-65
Parameter
Temp Level Min Typ
Max Min Typ
Max Min Typ
Max
Unit
RESOLUTION
Full
VI
12
12
12
12
12
12
Bits
ACCURACY
No Missing Codes Guaranteed
Offset Error
Full
Full
Full
Full
2ꢀЊC
Full
2ꢀЊC
VI
VI
IV
V
I
V
I
Bits
±±0.± ±102
±±0.± ±202
±±0.ꢀ
±±0.ꢀ ±±0ꢂ
±±0ꢁꢀ
±±0ꢀ± ±101
±±0ꢀ± ±20ꢁ
±±0.ꢀ
±±0.ꢀ ±±0ꢃ
±±0ꢄ±
±±0ꢀ± ±101
±±0ꢀ± ±20ꢀ
±±0.ꢀ
±±0.ꢀ ±10±
±±0ꢅ±
% FSR
% FSR
LSB
LSB
LSB
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
±±0ꢁ± ±10ꢁ
±±0ꢀ± ±10ꢁ
±±0ꢀꢀ ±10ꢅꢀ LSB
TEMPERATURE DRIFT
Offset Error
Full
Full
V
V
±2
±12
±2
±12
±.
±12
ppm/°C
ppm/°C
Gain Error1
INTERNALVOLTAGE REFERENCE
OutputVoltage Error (1V Mode)
Load Regulation @ 10± mA
OutputVoltage Error (±0ꢀV Mode)
Load Regulation @ ±0ꢀ mA
Full
Full
Full
Full
VI
V
V
±ꢀ
±.ꢀ
±ꢀ
±.ꢀ
±ꢀ
±.ꢀ
mV
mV
mV
mV
±0ꢃ
±20ꢀ
±01
±0ꢃ
±20ꢀ
±01
±0ꢃ
±20ꢀ
±01
V
INPUT REFERRED NOISE
Input Span = 1V
Input Span = 20±V
2ꢀЊC
2ꢀЊC
V
V
±0ꢀꢁ
±02ꢅ
±0ꢀꢁ
±02ꢅ
±0ꢀꢁ
±02ꢅ
LSB rms
LSB rms
ANALOG INPUT
Input Span = 10±V
Input Span = 20±V
Input Capacitance.
Full
Full
Full
IV
IV
V
1
2
ꢅ
1
2
ꢅ
1
2
ꢅ
V p-p
V p-p
pF
REFERENCE INPUT RESISTANCE Full
V
ꢅ
ꢅ
ꢅ
k⍀
POWER SUPPLIES
SupplyVoltages
AVDD
DRVDD
Full
Full
IV
IV
20ꢅ .0±
202ꢀ .0±
.0ꢄ
.0ꢄ
20ꢅ
202ꢀ .0±
.0±
.0ꢄ
.0ꢄ
20ꢅ .0±
202ꢀ .0±
.0ꢄ
.0ꢄ
V
V
Supply Current
IAVDD2
Full
Full
Full
V
V
V
ꢄ±
ꢁ
±±0±1
11±
1±
±±0±1
2±±
1ꢁ
±±0±1
mA
mA
% FSR
IDRVDD2
PSRR
POWER CONSUMPTION
DC Inputꢁ
Full
Full
Full
V
VI
V
1ꢃ±
1ꢂ±
20±
..±
.ꢄ±
20±
ꢄ±±
ꢄꢁ±
20±
mW
mW
mW
SineWave Input2
Standby Powerꢀ
212
.ꢂꢅ
ꢄꢂꢃ
MATCHING CHARACTERISTICS
Offset Error
Gain Error
Full
Full
V
V
±±01
±±0±ꢀ
±±01
±±0±ꢀ
±±01
±±0±ꢀ
% FSR
% FSR
NOTES
1Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 10±V external reference)0
2Measured at maximum clock rate with a low frequency sine wave input and approximately ꢀ pF loading on each output bit0
.Input capacitance refers to the effective capacitance between one differential input pin and AVSS0 Refer to Figure 2 for the equivalent analog input structure0
ꢁMeasured with dc input at maximum clock rate0
ꢀStandby power is measured with the CLK_A and CLK_B pins inactive (i0e0, set to AVDD or AGND)0
Specifications subject to change without notice0
–2–
REV. A
(continued)
Te
Typ
Typ
Typ
High Level InputVoltage
Low Level InputVoltage
High Level Input Current
Low Level Input Current
Input Capacitance
µA
µA
pF
High Level OutputVoltage
(IOH = 50 mA)
High Level OutputVoltage
(IOH = 0.5 mA)
Low Level OutputVoltage
(IOL = 50 mA)
Low Level OutputVoltage
(IOL = 1.6 mA)
High Level OutputVoltage
(IOH = 50 mA)
High Level OutputVoltage
(IOH = 0.5 mA)
Low Level OutputVoltage
(IOL = 50 mA)
Low Level OutputVoltage
(IOL = 1.6 mA)
OutputVoltage Levels measured with 5 pF load on each output.
Specifications subject to change without notice.
Te
Typ
Typ
Typ
CLK Pulsewidth High1
1
Output Delay2 (tPD
)
Cycles
ps rms
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (t)
Wake-UpTime3
Cycles
1The AD9238-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (seeTPC 20).
2Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.
3Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = –0.5 dBFS Differential Input,
1.0 V Internal Reference, TMIN MAX, unless otherwise noted.)
Temp
Typ
Typ
Typ
INPUT
Full
Full
V
V
dBc
dBc
INPUT
INPUT = 19.6 MHz
INPUT = 32.5 MHz
INPUT
70.1
69.3
INPUT
25°C
25°C
IV
IV
70.2
dBc
dBc
INPUT
69.3
INPUT
INPUT
INPUT
69.4 70.1
INPUT
INPUT
Full
Full
V
V
–81.0
dBc
dBc
INPUT = 19.6 MHz
INPUT = 32.5 MHz
INPUT
–78.0
(2nd or 3rd)
INPUT
INPUT
fINPUT = 32.5 MHz
Full
V
dBc
–80.0
DYNAMIC RANGE
INPUT
INPUT
INPUT
INPUT
INPUT
CROSSTALK
–80
–80
Full
V
–80
dB
Specifications subject to change without notice.
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Figure 1. Timing Diagram
REV. A
1
100% production tested.
Respect
II 100% production tested at 25°C and sample tested at specified
temperatures.
Digital Outputs
CLK, DCS,
MUX_SELECT,
SHARED_REF,
OEB, DFS
VINA,VINB
REFB, REFT
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
2
OperatingTemperature
JunctionTemperature
LeadTemperature (10 sec)
StorageTemperature
1 Absolute maximum ratings are limiting values to be applied individually,and beyond
which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2 Typical thermal impedances (64-lead LQFP); JA
were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
ORDERING GUIDE
Temperature Range
Package Description
Package Option
64-Lead Low Profile Quad Flat Pack (LQFP)
64-Lead Low Profile Quad Flat Pack (LQFP)
64-Lead Low Profile Quad Flat Pack (LQFP)
64-Lead Low Profile Quad Flat Pack (LQFP)
64-Lead Low Profile Quad Flat Pack (LQFP)
64-Lead Low Profile Quad Flat Pack (LQFP)
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9238 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. A
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
2
48
47
46
45
44
AGND
VIN+_A
VIN–_A
D4_A
PIN 1
IDENTIFIER
D3_A
D2_A
3
4
AGND
AVDD
D1_A
D0_A
5
6
REFT_A
REFB_A
VREF
43 DNC
7
42
DNC
AD9238
8
41
DRVDD
40 DRGND
64-LEAD LQFP
TOP VIEW
9
SENSE
REFB_B
REFT_B
AVDD
10
11
12
13
(Not to Scale)
39
38
37
36
35
34
33
OTR_B
D11_B (MSB)
D10_B
AGND
D9_B
VIN–_B 14
D8_B
D7_B
D6_B
15
VIN+_B
16
AGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DNC = DO NOT CONNECT
Description
6
VIN+_A
VIN–_A
VIN+_B
VIN–_B
REFT_A
REFB_A
REFT_B
REFB_B
Analog Input Pin (+) for Channel A
Analog Input Pin (–) for Channel A
Analog Input Pin (+) for Channel B
Analog Input Pin (–) for Channel B
Differential Reference (+) for Channel A
Differential Reference (–) for Channel A
Differential Reference (+) for Channel B
Differential Reference (–) for Channel B
Voltage Reference Input/Output
CLK_B
CLK_A
Clock Input Pin for Channel B
Clock Input Pin for Channel A
Enable Duty Cycle Stabilizer (DCS) Mode
Data Output Format Select Bit (Low for Offset Binary, High forTwos Complement)
Power-Down Function Selection for Channel B (Active High)
Power-Down Function Selection for Channel A (Active High)
Output Enable Bit for Channel B
63
59
PDWN_B
PDWN_A
OEB_B
OEB_A
Output Enable Bit for Channel A (Low Setting Enables Channel A Output Data Bus)
44–51, 54–57 D0_A (LSB)–D11_A (MSB) Channel A Data Output Bits
25–27, 30–38 D0_B (LSB)–D11_B (MSB) Channel B Data Output Bits
OTR_B
OTR_A
SHARED_REF
Out-of-Range Indicator for Channel B
Out-of-Range Indicator for Channel A
Shared Reference Control Bit (Low for Independent Reference Mode,
High for Shared Reference Mode)
61
MUX_SELECT
Data Multiplexed Mode. (See description for how to enable; high setting disables
output data Multiplexed mode).
5, 12, 17, 64
1, 4, 13, 16
28, 40, 53
29, 41, 52
Analog Power Supply
Analog Ground
Digital Output Ground
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum
0.1 µF capacitor. Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.
Do Not Connect Pins. Should be left floating.
23, 24, 42, 43 DNC
REV. A
AD9238
TERMINOLOGY
Effective Number of Bits (ENOB)
Aperture Delay
Using the following formula:
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
ENOB = SINAD –1.76 /6.02
(
)
effective number of bits for a device for sine wave inputs at a
given input frequency can be calculated directly from its
measured SINAD.
Aperture Jitter
The variation in aperture delay for successive samples, which is
manifested as noise on the input to the A/D converter.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the rms
sum of all other spectral components below the Nyquist frequency,
excluding the first six harmonics and dc.The value for SNR is
expressed in decibels relative to the peak carrier signal (dBc).
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale.The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition.The deviation is measured from
the middle of each particular code to the true straight line.
Spurious Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Nyquist Sampling
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to 12-bit resolution indicates that all 4096 codes
must be present over all operating ranges.
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies will be aliased
down into the first Nyquist zone (DC – fCLOCK/2) on the output
of the ADC. Care must be taken that the bandwidth of the sam-
pled signal does not overlap Nyquist zones and alias onto itself.
Nyquist sampling performance is limited by the bandwidth of the
input SHA and clock jitter (jitter adds more noise at higher input
frequencies).
Offset Error
The major carry transition should occur for an analog value
1/2 LSB belowVIN+ =VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above negative full scale.The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component.The peak spurious component
may or may not be an IMD product.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
Out-of-Range RecoveryTime
Out-of-range recovery time is the time it takes for the A/D con-
verter to reacquire the analog input after a transient from 10%
above positive full scale to 10% above negative full scale, or from
10% below negative full scale to 10% below positive full scale.
TMIN orTMAX
.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
Crosstalk
Coupling onto one channel being driven by a (–0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-scale
signal. Measurement includes all spurs resulting from both direct
coupling and mixing components.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal (dBc).
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
The ratio of the rms value of the measured input signal to the rms
sum of all other spectral components below the Nyquist frequency,
including harmonics but excluding dc.The value for S/N+D is
expressed in decibels relative to the peak carrier signal (dBc).
REV. A
–7–
AD9238–Typical Performance Characteristics
0
100
95
90
85
80
75
70
65
–20
SFDR
–40
–60
THIRD
HARMONIC
SECOND
HARMONIC
SNR
–80
–100
–120
CROSSTALK
60
55
50
0
5
10
15
20
25
30
40
45
50
55
60
65
FREQUENCY – MHz
ADC SAMPLE RATE – MSPS
TPC 1. Single-Tone FFT of Channel A Digitizing
fIN = 12.5 MHz while Channel B is Digitizing fIN = 10 MHz
TPC 4. AD9238-65 Single-Tone SNR/SFDR vs. FS with
fIN = 32.5 MHz
100
95
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90
SFDR
85
80
75
70
65
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60
55
50
20
25
30
ADC SAMPLE RATE – MSPS
35
40
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TPC 2. Single-Tone FFT of Channel A Digitizing
fIN = 70 MHz while Channel B is Digitizing fIN = 76 MHz
TPC 5. AD9238-40 Single-Tone SNR/SFDR vs. FS with
fIN = 20 MHz
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TPC 3. Single-Tone FFT of Channel A Digitizing
fIN = 120 MHz while Channel B is Digitizing fIN = 126 MHz
TPC 6. AD9238-20 Single-Tone SNR/SFDR vs. FS with
fIN = 10 MHz
–8–
REV. A
100
90
95
90
SFDR
80
70
60
85
80
75
SFDR
SNR
50
40
70
65
SNR
–35
–30
–25
–20
–15
–10
–5
0
0
20
40
60
80
100
120
140
INPUT AMPLITUDE – dBFS
INPUT FREQUENCY – MHz
TPC 7. AD9238-65 Single-Tone SNR/SFDR vs. AIN
with fIN = 32.5 MHz
TPC 10. AD9238-65 Single-Tone SNR/SFDR vs. fIN
95
90
100
90
SFDR
85
80
75
80
70
60
SFDR
SNR
SNR
60
70
65
50
40
0
20
40
80
100
120
140
–35
–30
–25
–20
–15
–10
–5
0
INPUT FREQUENCY – MHz
INPUT AMPLITUDE – dBFS
TPC 11. AD9238-40 Single-Tone SNR/SFDR vs. fIN
with fIN = 20 MHz
95
90
100
90
SFDR
SFDR
85
80
70
60
80
75
SNR
SNR
70
50
40
65
0
20
40
60
80
100
120
140
–35
–30
–25
–20
–15
–10
–5
0
INPUT FREQUENCY – MHz
INPUT AMPLITUDE – dBFS
TPC 12. AD9238-20 Single-Tone SNR/SFDR vs. fIN
IN
REV. A
AD9238
100
95
90
85
80
75
70
0
SFDR
–20
–40
–60
–80
SNR
–18
–100
65
60
–120
0
5
10
15
20
25
30
–24
–21
–15
–12
–9
–6
INPUT AMPLITUDE – dBFS
FREQUENCY – MHz
TPC 13. Dual-Tone FFT with fIN1 = 45 MHz and
fIN2 = 46 MHz
TPC 16. Dual-Tone SNR/SFDR vs. AIN with
fIN1 = 45 MHz and fIN2 = 46 MHz
0
100
95
90
85
80
75
70
SFDR
–20
–40
–60
–80
SNR
–18
–100
–120
65
60
0
5
10
15
20
25
30
–24
–21
–15
–12
–9
–6
INPUT AMPLITUDE – dBFS
FREQUENCY – MHz
TPC 14. Dual-Tone FFT with fIN1 = 70 MHz and
fIN2 = 71 MHz
TPC 17. Dual-Tone SNR/SFDR vs. AIN with
fIN1 = 70 MHz and fIN2 = 71 MHz
0
100
95
90
85
80
75
70
–20
SFDR
–40
–60
–80
SNR
–18
–100
–120
65
60
0
5
10
15
20
25
30
–24
–21
–15
–12
–9
–6
FREQUENCY – MHz
INPUT AMPLITUDE – dBFS
TPC 18. Dual-Tone SNR/SFDR vs. AIN with
fIN1 = 200 MHz and fIN2 = 201 MHz
TPC 15. Dual-Tone FFT with fIN1 = 200 MHz and
fIN2 = 201 MHz
–10–
REV. A
AD9238
74
72
12.0
11.5
11.0
–65
600
500
400
–40
SINAD –20
300
70
68
200
100
–20
SINAD –40
SINAD –65
60
0
20
40
CLOCK FREQUENCY
0
10
20
30
40
50
60
SAMPLE RATE – MSPS
TPC 19. SINAD vs. FS with Nyquist Input
TPC 22. Analog Power Consumption vs. FS
95
90
1.0
0.8
0.6
0.4
0.2
0
DCS ON – SFDR
85
80
75
70
65
60
55
50
DCS OFF – SFDR
DCS ON – SINAD
–0.2
–0.4
DCS OFF – SINAD
–0.6
–0.8
–1.0
30
35
40
45
50
55
60
65
0
500
1000 1500
2000
2500
3000 3500 4000
DUTY CYCLE – %
CODE
TPC 20. SINAD/SFDR vs. Clock Duty Cycle
TPC 23. AD9238-65Typical INL
84
1.0
0.8
0.6
0.4
0.2
0
SFDR
82
80
78
76
74
72
–0.2
–0.4
70
–0.6
–0.8
–1.0
SINAD
68
66
–50
0
50
100
0
500
1000 1500
2000
2500
3000 3500 4000
TEMPERATURE – C
CODE
TPC 21. SINAD/SFDR vs.Temperature with fIN = 32.5 MHz
TPC 24. AD9238-65Typical DNL
REV. A
–11–
Equivalent Circuits
AVDD
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VIN+_A, VIN–_A,
VIN+_B, VIN–_B,
Figure 3. Equivalent Digital Output Circuit
Figure 2. Equivalent Analog Input Circuit
AVDD
CLK_A, CLK_B
DCS, DFS,
MUX_SELECT
SHARED_REF
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers.The output
buffers are powered from a separate supply, allowing adjustment
of the output voltage swing.
The AD9238 consists of two high performance analog-to-digital
converters (ADCs) that are based on the AD9235 converter core.
The dual ADC paths are independent, except for a shared internal
band gap reference source,VREF. Each of the ADC’s paths consists
of a proprietary front end sample-and-hold amplifier (SHA)
followed by a pipelined switched capacitor ADC.The pipelined
ADC is divided into three sections, consisting of a 4-bit first stage
followed by eight 1.5-bit stages and a final 3-bit flash. Each stage
provides sufficient overlap to correct for flash errors in the preced-
ing stages.The quantized outputs from each stage are combined
through the digital correction logic block into a final 12-bit result.
The pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the respective clock.
The analog input to the AD9238 is a differential switched capacitor,
SHA, that has been designed for optimum performance while
processing a differential input signal.The SHA input accepts inputs
over a wide common-mode range. An input common-mode voltage
of midsupply is recommended to maintain optimal performance.
The SHA input is a differential switched capacitor circuit. In
Figure 5, the clock signal alternatively switches the SHA between
sample mode and hold mode.When the SHA is switched into
sample mode, the signal source must be capable of charging the
sample capacitors and settling within one-half of a clock cycle. A
small resistor in series with each input can help reduce the peak
transient current required from the output stage of the driving
source. Also, a small shunt capacitor can be placed across the inputs
to provide dynamic charging currents.This passive network will
create a low-pass filter at the ADC’s input; therefore, the precise
values are dependant on the application. In IF undersampling
applications, any shunt capacitors should be removed. In combi-
nation with the driving source impedance, they would limit the
input bandwidth. For best dynamic performance, the source
impedances drivingVIN+ andVIN– should be matched such that
common-mode settling errors are symmetrical.These errors will
be reduced by the common-mode rejection of the ADC.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline.The residual multiplier uses the flash ADC
output to control a switched capacitor digital-to-analog converter
(DAC) of the same resolution.The DAC output is subtracted from
the stage’s input signal and the residual is amplified (multiplied)
to drive the next pipeline stage.The residual multiplier stage is
also called a multiplying DAC (MDAC). One bit of redundancy
is used in each one of the stages to facilitate digital correction of
flash errors.The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be config-
ured as ac- or dc-coupled in differential or single-ended modes.
REV. A
H
The output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
T
T
5pF
5pF
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers will not be adequate to achieve
the true performance of the AD9238.This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input con-
figuration, as shown in Figure 6.
VIN+
VIN–
C
PAR
T
C
PAR
T
AVDD
50
VINA
H
10pF
2V p-p
49.9
AD9238
50
Figure 5. Switched Capacitor Input
VINB
AGND
An internal differential reference buffer creates positive and nega-
tive reference voltages, REFT and REFB, respectively, that define
the span of the ADC core.The output common-mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as follows:
10pF
1k
1k
0.1F
Figure 6. DifferentialTransformer Coupling
REFT = 1/2 AVDD +V
(
)
)
REF
The signal characteristics must be considered when selecting a
transformer. Most RF transformers will saturate at frequencies
below a few MHz, and excessive signal power can also cause core
saturation, which leads to distortion.
REFB = 1/2 AVDD −V
(
REF
Span = 2 × REFT − REFB = 2 ×V
REF
It can be seen from the equations above that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of theVREF voltage.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there will be a
degradation in SFDR and in distortion performance due to the
large input common-mode swing. However, if the source imped-
ances on each input are matched, there should be little effect on
SNR performance.
The internal voltage reference can be pin-strapped to fixed values
of 0.5V or 1.0V, or adjusted within the same range as discussed
performance will be achieved with the AD9238 set to the largest
input span of 2V p-p.The relative SNR degradation will be 3 dB
when changing from 2V p-p mode to 1V p-p mode.
CLOCK INPUT AND CONSIDERATIONS
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference volt-
age.The minimum and maximum common-mode input levels
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensitive
to clock duty cycle. Commonly, a 5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
VCMMIN =VREF
VCMMAX =(AVDD +VREF ) 2
2
The AD9238 provides separate clock inputs for each channel.The
optimum performance is achieved with the clocks operated at the
same frequency and phase. Clocking the channels asynchronously
may degrade performance significantly. In some applications, it is
desirable to skew the clock timing of adjacent channels.The AD9238’s
separate clock inputs allow for clock timing skew (typically ±1 ns)
between the channels without significant performance degradation.
The minimum common-mode input level allows the AD9238
to accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-ended
source may be driven intoVIN+ orVIN–. In this configuration,
one input will accept the signal, while the opposite input should
be set to midscale by connecting it to an appropriate reference.
For example, a 2V p-p signal may be applied toVIN+ while a
1V reference is applied toVIN–.The AD9238 will then accept
an input signal varying between 2V and 0V. In the single-ended
configuration, distortion performance may degrade significantly
as compared to the differential case. However, the effect will be
less noticeable at lower input frequencies and in the lower speed
grade models (AD9238-40 and AD9238-20).
The AD9238-65 contains two clock duty cycle stabilizers, one for
each converter, that retime the nonsampling edge, providing an
internal clock with a nominal 50% duty cycle (DCS is not avail-
able on the –40 MSPS or –20 MSPS versions). Input clock rates
of over 40 MHz can use the DCS so that a wide range of input
clock duty cycles can be accommodated. Maintaining a 50% duty
cycle clock is particularly important in high speed applications,
when proper track-and-hold times for the converter are required
to maintain high performance.The DCS can be enabled by tying
the DCS pin high.
Differential Input Configurations
As previously detailed, optimum performance will be achieved
while driving the AD9238 in a differential input configuration.
For baseband applications, the AD8138 differential driver pro-
vides excellent performance and a flexible interface to the ADC.
The duty cycle stabilizer utilizes a delay locked loop to create the
nonsampling edge. As a result, any changes to the sampling fre-
quency will require approximately 2 µs to 3 µs to allow the DLL
to acquire and settle to the new rate.
REV. A
High speed, high resolution ADCs are sensitive to the quality of
the clock input.The degradation in SNR at a given full-scale input
frequency (fINPUT) due only to aperture jitter (tJ) can be calculated
with the following equation:
will result in a typical power consumption of 1 mW for the ADC.
Note that if DCS is enabled, it is mandatory to disable the clock
of an independently powered-down channel. Otherwise, sig-
inputs remain active while in total standby mode, typical power
dissipation of 12 mW will result.
SNR degradation = 20 × log10 1/2 × p × f
× tJ
INPUT
In the equation, the rms aperture jitter, J, represents the root-sum-
square of all jitter sources, which includes the clock input, analog
input signal, and ADC aperture jitter specification. Undersampling
applications are particularly sensitive to jitter.
The minimum standby power is achieved when both channels are
placed into full power-down mode (PDWN_A = PDWN_B =
HI). Under this condition, the internal references are powered
down.When either or both of the channel paths are enabled after a
power-down, the wake-up time will be directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down.Typically, it takes approximately
5 ms to restore full operation with fully discharged 0.1 µF and
10 µF decoupling capacitors on REFT and REFB.
For optimal performance, especially in cases where aperture jitter
may affect the dynamic range of the AD9238, it is important to
minimize input clock jitter.The clock input circuitry should use
stable references, for example using analog power and ground
planes to generate the valid high and low digital levels for the
AD9238 clock input. Power supplies for clock drivers should be sep-
arated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.
A single channel can be powered down for moderate power savings.
The powered-down channel shuts down internal circuits, but both
the reference buffers and shared reference remain powered. Because
the buffer and voltage reference remain powered, the wake-up
time is reduced to several clock cycles.
DIGITAL OUTPUTS
POWER DISSIPATION AND STANDBY MODE
The AD9238 output drivers can be configured to interface with
2.5V or 3.3V logic families by matching DRVDD to the digital
supply of the interfaced logic.The output drivers are sized to pro-
vide sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance. Applications
requiring the ADC to drive large capacitive loads or large fan-outs
may require external buffers or latches.
The power dissipated by the AD9238 is proportional to its
sampling rates.The digital (DRVDD) power dissipation is deter-
mined primarily by the strength of the digital drivers and the load
on each output bit.The digital drive current can be calculated by
IDRVDD =VDRVDD × CLOAD × fCLOCK × N
is the number of bits changing and LOAD is the average
load on the digital pins that changed.
The data format can be selected for either offset binary or twos
complement.This is discussed later in the Data Format section.
The analog circuitry is optimally biased so that each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at low
sample rates that increases with clock frequency.
TIMING
The AD9238 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (tPD) after the rising edge of the clock signal. Refer to
Figure 1 for a detailed timing diagram.
Either channel of the AD9238 can be placed into standby mode
independently by asserting the PWDN_A or PDWN_B pins.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
A
A
ANALOG INPUT
ADC A
A
1
0
8
A
2
A
–1
A
A
7
3
A
A
6
4
A
5
B
B
B
1
0
8
B
ANALOG INPUT
ADC B
2
B
–1
B
B
7
3
B
B
6
4
B
5
CLK_A = CLK_B =
MUX_SELECT
D0_A
–D11_A
B
A
B
–7
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
1
–8
–7
–6
–6
–5
–5
–4
–4
–3
–3
–2
–2
–1
–1
0
0
tODF
tODR
Figure 7. Example of Multiplexed Data Format Using the Channel A Output and the Same ClockTied to CLK_A,
CLK_B, and MUX_SELECT
REV. A
The internal duty cycle stabilizer can be enabled on the AD9238-65
using the DCS pin.This provides a stable 50% duty cycle to
ences from the dual ADCs together externally for superior gain
and offset matching performance. If the ADCs are to function
independently, the reference decoupling can be treated inde-
pendently and can provide superior isolation between the dual
channels.To enable Shared Reference mode, the SHARED_REF
pin must be tied high and external differential references must
be externally shorted. (REFT_A must be externally shorted to
REFT_B and REFB_A must be shorted to REFB_B.)
The length of the output data lines and loads placed on them should
transients can detract from the converter’s dynamic performance.
The lowest typical conversion rate of the AD9238 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
Internal Reference Connection
A comparator within the AD9238 detects the potential at the
SENSE pin and configures the reference into four possible states,
which are summarized inTable I. If SENSE is grounded, the refer-
ence amplifier switch is connected to the internal resistor divider
(see Figure 8), settingVREF to 1V. Connecting the SENSE pin to
REF switches the reference amplifier output to the SENSE pin,
completing the loop and providing a 0.5V reference output. If a
resistor divider is connected as shown in Figure 9, the switch will
again be set to the SENSE pin.This will put the reference ampli-
fier in a noninverting mode with theVREF output defined as follows:
DATA FORMAT
The AD9238 data output format can be configured for either
twos complement or offset binary.This is controlled by the Data
Format Select pin (DFS). Connecting DFS to AGND will pro-
duce offset binary output data. Conversely, connecting DFS to
AVDD will format the output data as twos complement.
The output data from the dual A/D converters can be multiplexed
onto a single 12-bit output bus.The multiplexing is accomplished
by toggling the MUX_SELECT bit, which directs channel data
to the same or opposite channel data port.When MUX_SELECT
is logic high, the Channel A data is directed to Channel A output
bus, and Channel B data is directed to the Channel B output bus.
When MUX_SELECT is logic low, the channel data is reversed, i.e.,
Channel A data is directed to the Channel B output bus and
Channel B data is directed to the Channel A output bus. By
toggling the MUX_SELECT bit, multiplexed data is available
on either of the output data ports.
VREF = 0.5×(1+ R2 R1)
In all reference configurations, REFT and REFB drive the ADC
core and establish its input span.The input range of the ADC
always equals twice the voltage at the reference pin for either an
VIN+
If the ADCs are run with synchronized timing, this same clock can
be applied to the MUX_SELECT bit. After the MUX_SELECT
rising edge, either data port will have the data for its respective
channel; after the falling edge, the alternate channel’s data will be
placed on the bus.Typically, the other unused bus would be
disabled by setting the appropriate OEB high to reduce power
consumption and noise. Figure 7 shows an example of multiplex
mode.When multiplexing data, the data rate is two times the
sample rate. Note that both channels must remain active in this
mode and that each channel's power-down pin must remain low.
VIN–
REFT
0.1�F
ADC
CORE
0.1�F
10�F
REFB
0.1�F
V
REF
VOLTAGE REFERENCE
A stable and accurate 0.5V voltage reference is built into the
AD9238.The input range can be adjusted by varying the reference
voltage applied to the AD9238, using either the internal reference
with different external resistor configurations or an externally
applied reference voltage.The input span of the ADC tracks refer-
ence voltage changes linearly.
10�F
SELECT
LOGIC
0.1�F
0.5V
SENSE
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap (common-
mode voltage).
AD9238
Figure 8. Internal Reference Configuration
Table I. Reference Configuration Summary
Resulting Differential
Span (V p-p)
SENSEVoltage
ResultingVREF (V)
REF
REF
REF (See Figure 9)
Programmable Reference
(1 + R2/R1)
REV. A
1.2
1.0
External Reference Operation
The use of an external reference may be necessary to enhance the
gain accuracy of the ADC or to improve thermal drift character-
istics.When multiple ADCs track one another, a single reference
(internal or external) may be necessary to reduce gain matching
errors to an acceptable level. A high precision external reference
may also be selected to provide lower gain and offset temperature
drift. Figure 10 shows the typical drift characteristics of the inter-
V
= 1V
REF
0.8
0.6
0.4
V
= 0.5V
REF
When the SENSE pin is tied to AVDD, the internal reference will
be disabled, allowing the use of an external reference. An internal
reference buffer will load the external reference with an equiva-
load.The internal buffer will still generate the positive
and negative full-scale references, REFT and REFB, for the ADC
core.The input span will always be twice the value of the refer-
ence voltage; therefore, the external reference must be limited to
0.2
0
0
–40 –30 –20 –10
10 20 30 40 50 60 70 80
TEMPERATURE – C
Figure 10. Typical VREF Drift
If the internal reference of the AD9238 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 11 depicts
how the internal reference voltage is affected by loading.
0.05
0
–0.05
–0.10
–0.15
0.5V ERROR
VIN+
VIN–
1V ERROR
REFT
0.1�F
ADC
CORE
–0.20
–0.25
0.1�F
10�F
REFB
0.1�F
0.5
1.0
1.5
2.0
2.5
3.0
0
LOAD – mA
Figure 11. VREF Accuracy vs. Load
V
REF
10�F
10�F
SENSE
R2
SELECT
LOGIC
0.5V
R1
AD9238
Figure 9. Programmable Reference Configuration
REV. A
Figure 12. Evaluation Board Schematic
REV. A
Figure 13. Evaluation Board Schematic (continued)
REV. A
Figure 14. Evaluation Board Schematic (continued)
REV. A
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Figure 15. Evaluation Board Schematic (continued)
REV. A
AD9238
Figure 16. PCBTop Layer
Figure 17. PCB Bottom Layer
REV. A
–21–
AD9238
Figure 18. PCB Ground Plane
Figure 19. PCB Split Power Plane
–22–
REV. A
AD9238
Figure 20. PCBTop Silkscreen
Figure 21. PCB Bottom Silkscreen
REV. A
–23–
AD9238
OUTLINE DIMENSIONS
64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-1)
Dimensions shown in millimeters
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
64
49
1
48
SEATING
PLANE
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
10
6
2
1.45
1.40
1.35
0.20
0.09
7
3.5
0
VIEW A
0.15
0.05
16
33
SEATING
PLANE
0.10 MAX
COPLANARITY
17
32
0.23
0.18
0.13
0.40
BSC
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBD
Revision History
Location
Page
9/03—Data Sheet changed from REV. 0 to REV. A.
Changes to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to SWITCHING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to AC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes toTPCs 2, 3, and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Changes to CLOCK INPUT AND CONSIDERATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Added text to DATA FORMAT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Added EVALUATION BOARD DIAGRAMS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
–24–
REV. A
相关型号：
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