AD9245BCP-40EB [ADI]
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter; 14位， 20 MSPS / 40 MSPS / 65 MSPS / 80 MSPS ， 3 VA / D转换器
| 型号： | AD9245BCP-40EB |
| 厂家： | 
ADI |
| 描述： | 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 3 V A/D Converter |
| 文件： | 总32页 (文件大小：883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
3 V A/D Converter
AD9245
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
DRVDD
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 72.7 dBc to Nyquist
AD9245
SFDR = 83.0 dBc to Nyquist
Low power
366 mW at 80 MSPS
VIN+
VIN–
8-STAGE
1 1/2-BIT PIPELINE
MDAC1
A/D
3
SHA
4
16
300 mW at 65 MSPS
165 mW at 40 MSPS
A/D
REFT
REFB
CORRECTION LOGIC
OTR
90 mW at 20 MSPS
14
Differential input with 500 MHz bandwidth
On-chip reference and sample-and-hold
DNL = 0.5 LSB
OUTPUT BUFFERS
D13 (MSB)
D0 (LSB)
VREF
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty-cycle stabilizer
SENSE
CLOCK
DUTY CYCLE
STABILIZER
0.5V
MODE
SELECT
REF
SELECT
APPLICATIONS
AGND
CLK
PDWN MODE DGND
Medical imaging equipment
Figure 1.
IF sampling in communications receivers
WCDMA, CDMA-One, CDMA-2000, and TDS-CDMA
Battery-powered instruments
Hand-held scopemeters
Spectrum analyzers
A single-ended clock input is used to control all internal con-
version cycles. A duty cycle stabilizer (DCS) compensates for
wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow. Fabricated on an advanced CMOS process, the
AD9245 is available in a 32-lead LFCSP and is specified over
the industrial temperature range (–40°C to +85°C).
Power-sensitive military applications
GENERAL DESCRIPTION
The AD9245 is a monolithic, single 3 V supply, 14-bit,
20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC) featuring a high performance sample-and-
hold amplifier (SHA) and voltage reference. The AD9245 uses a
multistage differential pipelined architecture with output error
correction logic to provide 14-bit accuracy and guarantee no
missing codes over the full operating temperature range.
PRODUCT HIGHLIGHTS
1. The AD9245 operates from a single 3 V power supply and
features a separate digital output driver supply to
accommodate 2.5 V and 3.3 V logic families.
2. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
3. The AD9245 is pin-compatible with the AD9215, AD9235,
and AD9236. This allows a simplified migration from 10 bits
to 14 bits and 20 MSPS to 80 MSPS.
4. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
5. The OTR output bit indicates when the signal is beyond the
selected input range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and common modes, including
single-ended applications. It is suitable for multiplexed systems
that switch full-scale voltage levels in successive channels and
for sampling single-channel inputs at frequencies well beyond
the Nyquist rate. Combined with power and cost savings over
previously available analog-to-digital converters, the AD9245 is
suitable for applications in communications, imaging, and
medical ultrasound.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
AD9245
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ........................................... 13
Theory of Operation ...................................................................... 18
Analog Input and Reference Overview................................... 18
Clock Input Considerations...................................................... 19
Jitter Considerations .................................................................. 20
Power Dissipation and Standby Mode .................................... 20
Digital Outputs ........................................................................... 20
Timing ......................................................................................... 21
Voltage Reference ....................................................................... 21
Internal Reference Connection ................................................ 21
External Reference Operation .................................................. 22
Operational Mode Selection..................................................... 22
Evaluation Board........................................................................ 22
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Terminology .................................................................................... 10
Pin Configuration and Function Descriptions........................... 11
Equivalent Circuits......................................................................... 12
REVISION HISTORY
1/06—Rev. C to Rev. D
Added Figure 32 to Figure 37; Renumbered Sequentially ........ 17
Changes to Figure 39...................................................................... 18
Changes to Clock Input Consideration Section......................... 19
Changes to Figure 44...................................................................... 20
Changes to Table 10 ....................................................................... 21
Changes to Figure 51...................................................................... 25
Changes to Table 12 ....................................................................... 28
Changes to Ordering Guide.......................................................... 29
Updated Outline Dimensions....................................................... 29
Changes to Differential Input Configurations Section and
Figure 40 .......................................................................................... 19
Changes to Internal Reference Connection Section.................. 21
Changes to Figure 49...................................................................... 23
Changes to Figure 50...................................................................... 24
Changes to Table 12........................................................................ 28
Updated Outline Dimensions....................................................... 29
Changes to Ordering Guide .......................................................... 29
8/05—Rev. B to Rev. C
10/03—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features, Applications, General Description, and
Product Highlights ........................................................................... 1
Added Table 1; Renumbered Sequentially .................................... 3
Changes to Table 2............................................................................ 4
Added Table 3; Renumbered Sequentially .................................... 5
Changes to Table 4............................................................................ 6
Changes to Table 5............................................................................ 7
Changes to Table 6............................................................................ 8
Deleted Explanation of Test Levels Table ...................................... 8
Added Figure 26 to Figure 31; Renumbered Sequentially ........ 16
Changes to Figure 33...................................................................... 17
5/03—Rev. 0 to Rev. A
Changes to Figure 30...................................................................... 15
Changes to Figure 37...................................................................... 19
Changes to Figure 38...................................................................... 20
Changes to Figure 39...................................................................... 21
Changes to Table 10 ....................................................................... 24
Changes to the Ordering Guide ................................................... 25
Rev. D | Page 2 of 32
AD9245
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise noted.
Table 1.
AD9245BCP-20
AD9245BCP-40
AD9245BCP-65
Parameter
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
RESOLUTION
14
14
14
Bits
ACCURACY
No Missing Codes Guaranteed
Offset Error
14
14
14
Bits
±±.3±
±±.3±
±±.ꢁ±
±1.2±
±1.ꢀ±
±3.2ꢁ
±1.±±
±3.1±
±±.ꢁ±
±±.ꢁ±
±±.ꢁ±
±1.4±
±1.ꢂꢁ
±3.2ꢁ
±1.±±
±3.4±
±±.ꢁ±
±±.ꢁ±
±±.ꢁ±
±1.ꢀ±
±1.ꢂꢁ
±ꢀ.ꢃ±
±1.±±
±ꢁ.ꢁꢁ
% FSR
% FSR
LSB
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT1
Offset Error
LSB
±2
±12
±2
±12
±3
±12
ppm/°C
ppm/°C
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.± mA
Output Voltage Error (±.ꢁ V Mode)
Load Regulation @ ±.ꢁ mA
INPUT REFERRED NOISE
VREF = ±.ꢁ V
±ꢁ
±3ꢁ
±ꢁ
±3ꢁ
±ꢁ
±3ꢁ
mV
mV
mV
mV
±.8
±2.ꢁ
±.1
±.8
±2.ꢁ
±.1
±.8
±2.ꢁ
±.1
2.28
1.±8
2.28
1.±8
2.28
1.±8
LSB rms
LSB rms
VREF = 1.± V
ANALOG INPUT
Input Span, VREF = ±.ꢁ V
Input Span, VREF = 1.± V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
1
2
ꢂ
ꢂ
1
2
ꢂ
ꢂ
1
2
ꢂ
ꢂ
V p-p
V p-p
pF
kΩ
AVDD
DRVDD
2.ꢂ
2.2ꢁ
3.±
3.±
3.ꢀ
3.ꢀ
2.ꢂ
2.2ꢁ
3.±
3.±
3.ꢀ
3.ꢀ
2.ꢂ
2.2ꢁ
3.±
3.±
3.ꢀ
3.ꢀ
V
V
Supply Current
IAVDD2
IDRVDD2
3±
2
ꢁꢁ
ꢁ
1±±
ꢂ
mA
mA
PSRR
±±.±1
±±.±1
±±.±1
% FSR
POWER CONSUMPTION
DC Input4
Sine Wave Input2
Standby Powerꢁ
ꢃ±
ꢃꢁ
1.±
1ꢀꢁ
18±
1.±
3±±
32±
1.±
mW
mW
mW
12±
22±
3ꢂꢁ
1 Gain errors and gain temperature coefficients are based on the ADC only (with a fixed 1.± V external reference).
2 Measured at maximum clock rate, low input frequency, full-scale sine wave, with approximately ꢁ pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4 Measured with dc input at maximum clock rate.
ꢁ Standby power is measured with a dc input, the CLK pin inactive (that is, set to AVDD or AGND).
Rev. D | Page 3 of 32
AD9245
AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, unless otherwise noted.
Table 2.
AD9245BCP-80
Parameter
Min
Typ
Max
Unit
RESOLUTION
14
Bits
ACCURACY
No Missing Codes
Offset Error1
Gain Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error1
Gain Error
Gain Error1
Guaranteed
±±.3±
±±.28
±±.ꢂ±
±±.ꢁ
±1.2
% FSR
% FSR
% FSR
LSB
±4.1ꢀ
±1.±
±ꢁ.1ꢁ
±1.4
LSB
±1±
±12
±1ꢂ
ppm/°C
ppm/°C
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.± mA
Output Voltage Error (±.ꢁ V Mode)
Load Regulation @ ±.ꢁ mA
INPUT REFERRED NOISE
VREF = ±.ꢁ V
±3
±2
±ꢀ
±1
±34
mV
mV
mV
mV
1.8ꢀ
1.1ꢂ
LSB rms
LSB rms
VREF = 1.± V
ANALOG INPUT
Input Span, VREF = ±.ꢁ V
Input Span, VREF = 1.± V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
1
2
ꢂ
ꢂ
V p-p
V p-p
pF
kΩ
AVDD
DRVDD
2.ꢂ
2.2ꢁ
3.±
2.ꢁ
3.ꢀ
3.ꢀ
V
V
Supply Current
IAVDD2
IDRVDD2
122
ꢃ
138
mA
mA
PSRR
±±.±1
% FSR
POWER CONSUMPTION
Low Frequency Input4
Standby Powerꢁ
3ꢀꢀ
1.±
mW
mW
1 With a 1.± V internal reference.
2 Measured at the maximum clock rate, low input frequency, full-scale sine wave, with approximately ꢁ pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure.
4 Measured at ac specification conditions without output drivers.
ꢁ Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND).
Rev. D | Page 4 of 32
AD9245
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.
Table 3.
AD9245BCP-20
AD9245BCP-40
AD9245BCP-65
Parameter
Min
Typ
Max
Min
Typ
ꢂ3.ꢁ
ꢂ3.4
ꢂ1.3
ꢂ3.4
ꢂ3.2
ꢀꢃ.1
Max
Min
Typ
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz
fINPUT = ꢃ.ꢂ MHz
fINPUT = 1ꢃ.ꢀ MHz
fINPUT = 32.ꢁ MHz
ꢂ3.ꢁ
ꢂ3.3
ꢂ3.1
dBc
dBc
dBc
dBc
dBc
ꢂ±.ꢀ
ꢀꢃ.4
ꢂ±.ꢁ
ꢂ±.±
ꢂ±.3
ꢀ8.4
ꢂ2.ꢂ
ꢂ±.2
fINPUT = 1±± MHz
ꢂ±.8
SIGNAL-TO-NOISE RATIO AND DISTORTION (SINAD)
fINPUT = 2.4 MHz
fINPUT = ꢃ.ꢂ MHz
fINPUT = 1ꢃ.ꢀ MHz
fINPUT = 32.ꢁ MHz
ꢂ3.4
ꢂ3.2
ꢂ3.±
dBc
dBc
dBc
dBc
dBc
ꢂ2.ꢀ
ꢀꢂ.ꢃ
fINPUT = 1±± MHz
ꢀꢃ.ꢁ
11.ꢃ
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = ꢃ.ꢂ MHz
fINPUT = 1ꢃ.ꢀ MHz
Bits
Bits
Bits
11.8
–8ꢃ
fINPUT = 32.ꢁ MHz
11.ꢂ
WORST HARMONIC (SECOND OR THIRD)
fINPUT = ꢃ.ꢂ MHz
fINPUT = 1ꢃ.ꢀ MHz
–8ꢃ
–8±
dBc
dBc
dBc
–8±
fINPUT = 32.ꢁ MHz
–83
–ꢂ4
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fINPUT = 2.4 MHz
fINPUT = ꢃ.ꢂ MHz
fINPUT = 1ꢃ.ꢀ MHz
fINPUT = 32.ꢁ MHz
ꢃ2.±
8ꢃ.±
ꢃ2.±
8ꢃ.±
8ꢁ.±
ꢃ2.±
dBc
dBc
dBc
dBc
dBc
8±.±
8±.±
ꢂ4.±
83.±
8±.ꢁ
fINPUT = 1±± MHz
84.±
Rev. D | Page ꢁ of 32
AD9245
AVDD = 3 V, DRVDD = 2.5 V, sample rate = 80 MSPS, 2 V p-p differential input, 1.0 V external reference, AIN = –0.5 dBFS, DCS off,
unless otherwise noted.
Table 4.
AD9245BCP-80
Parameter
Min
ꢂ1.1
ꢂ±.ꢁ
Typ
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 4± MHz
fIN = ꢂ± MHz
fIN = 1±± MHz
ꢂ3.3
ꢂ2.ꢂ
ꢂ1.ꢂ
ꢂ±.2
dB
dB
dB
dB
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = 4± MHz
fIN = ꢂ± MHz
fIN = 1±± MHz
ꢂ±.ꢂ
ꢀꢃ.ꢃ
ꢂ3.2
ꢂ2.ꢁ
ꢂ1.2
ꢀꢃ.ꢀ
dB
dB
dB
dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 4± MHz
fIN = ꢂ± MHz
fIN = 1±± MHz
11.ꢁ
11.3
11.ꢃ
11.8
11.ꢁ
11.3
Bits
Bits
Bits
Bits
WORST HARMONIC (SECOND OR THIRD)
fIN = 2.4 MHz
fIN = 4± MHz
fIN = ꢂ± MHz
fIN = 1±± MHz
−ꢃ2.8
–8ꢂ.ꢀ
−81.ꢀ
–ꢂꢃ.±
–ꢂꢀ.ꢁ
–ꢂꢁ.ꢂ
dBc
dBc
dBc
dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 4± MHz
fIN = ꢂ± MHz
fIN = 1±± MHz
ꢂꢀ.ꢁ
ꢂꢁ.ꢂ
ꢃ2.8
8ꢂ.ꢀ
81.ꢀ
ꢂꢃ.±
dBc
dBc
dBc
dBc
Rev. D | Page ꢀ of 32
AD9245
DIGITAL SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, 1.0 V internal reference, unless otherwise noted.
Table 5.
AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-801
Parameter
Min
Typ
Max
Unit
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
2.±
V
Low Level Input Voltage
±.8
V
High Level Input Current
Low Level Input Current
Input Capacitance
–1±
–1±
+1±
+1±
μA
μA
pF
2
DIGITAL OUTPUT BITS (D± to D13, OTR)2
DRVDD = 3.3 V
High Level Output Voltage (IOH = ꢁ± μA)
High Level Output Voltage (IOH = ±.ꢁ mA)
Low Level Output Voltage (IOH = 1.ꢀ mA)
Low Level Output Voltage (IOH = ꢁ± μA)
DRVDD = 2.ꢁ V
3.2ꢃ
3.2ꢁ
V
V
V
V
±.2
±.±ꢁ
High Level Output Voltage (IOH = ꢁ± μA)
High Level Output Voltage (IOH = ±.ꢁ mA)
Low Level Output Voltage (IOH = 1.ꢀ mA)
Low Level Output Voltage (IOH = ꢁ± μA)
2.4ꢃ
2.4ꢁ
V
V
V
V
±.2
±.±ꢁ
1 ADꢃ24ꢁBCP-8± performance measured with 1.± V external reference.
2 Output voltage levels measured with ꢁ pF load on each output.
Rev. D | Page ꢂ of 32
AD9245
SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, unless otherwise noted.
Table 6.
AD9245BCP-20
AD9245BCP-40
AD9245BCP-65
AD9245BCP-80
Unit
Parameter
Min
Typ Max
Min Typ Max Min
Typ Max Min
Typ Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High1
CLK Pulse Width Low1
DATA OUTPUT PARAMETERS
Output Delay2 (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty Jitter (tJ)
Wake-Up Time3
2±
4±
ꢀꢁ
8±
MSPS
MSPS
ns
ns
ns
1
1
1
1
ꢁ±.±
1ꢁ.±
1ꢁ.±
2ꢁ.±
8.8
8.8
1ꢁ.4
ꢀ.2
ꢀ.2
12.ꢁ
4.ꢀ
4.ꢀ
3.ꢁ
ꢂ
1.±
±.ꢁ
3.±
1
3.ꢁ
ꢂ
1.±
±.ꢁ
3.±
1
3.ꢁ
ꢂ
1.±
±.ꢁ
3.±
2
4.2
ꢂ
1.±
±.3
ꢂ.±
2
ns
Cycles
ns
ps rms
ms
OUT-OF-RANGE RECOVERY TIME
Cycles
1 For the ADꢃ24ꢁBCP-ꢀꢁ and ADꢃ24ꢁBCP-8± models only, with duty cycle stabilizer enabled. DCS function not applicable for ADꢃ24ꢁBCP-2± and ADꢃ24ꢁBCP-4±
models.
2 Output delay is measured from CLK ꢁ±% transition to DATA ꢁ±% transition, with ꢁ pF load on each output.
3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with ±.1 μF and 1± μF capacitors on REFT and REFB.
N+1
N
N+2
N+8
N–1
N+3
tA
ANALOG
INPUT
N+7
N+4
N+6
N+5
CLK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
tPD = 6.0ns MAX
2.0ns MIN
Figure 2. Timing Diagram
Rev. D | Page 8 of 32
AD9245
ABSOLUTE MAXIMUM RATINGS
Table 7.
THERMAL RESISTANCE
Parameter
ELECTRICAL
AVDD
DRVDD
AGND
AVDD
D± to D13
CLK, MODE AGND
VIN+, VIN–
VREF
With Respect to Min Max
Unit
θJA is specified for the worst-case conditions on a 4-layer board
in still air, in accordance with EIA/JESD51-1.
AGND
DGND
DGND
DRVDD
DGND
–±.3 +3.ꢃ
–±.3 +3.ꢃ
–±.3 +±.3
–3.ꢃ +3.ꢃ
–±.3 DRVDD + ±.3
–±.3 AVDD + ±.3
–±.3 AVDD + ±.3
–±.3 AVDD + ±.3
–±.3 AVDD + ±.3
–±.3 AVDD + ±.3
–±.3 AVDD + ±.3
V
V
V
V
V
V
V
V
V
V
V
Table 8. Thermal Resistance
Package Type
Unit
θJA
32.ꢁ
θJC
32.ꢂ1
32-Lead LFCSP
°C/W
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads from metal traces, through holes, ground, and power
planes reduces the θJA. It is recommended that the exposed
paddle be soldered to the ground plane for the LFCSP package.
There is an increased reliability of the solder joints, and
maximum thermal capability of the package is achieved with
the exposed paddle soldered to the customer board.
AGND
AGND
AGND
AGND
AGND
SENSE
REFT, REFB
PDWN
ENVIRONMENTAL
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 1± sec)
–ꢀꢁ +12ꢁ
–4± +8ꢁ
3±±
°C
°C
°C
Junction Temperature
1ꢁ±
°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page ꢃ of 32
AD9245
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Signal-to-Noise and Distortion (SINAD)1
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Aperture Delay (tA)
Effective Number of Bits (ENOB)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
Aperture Uncertainty (Jitter, tJ)
(
SINAD −1.76
)
The sample-to-sample variation in aperture delay.
ENOB =
6.02
Integral Nonlinearity (INL)
Signal-to-Noise Ratio (SNR)1
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Spurious-Free Dynamic Range (SFDR)1
The difference in dB between the rms input signal amplitude
and the peak spurious signal. The peak spurious component
may or may not be a harmonic.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Two-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the Logic 0 state. At a given clock rate,
these specifications define an acceptable clock duty cycle.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
at TMIN or TMAX
.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum limit.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Total Harmonic Distortion (THD)1
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
1 AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. D | Page 1± of 32
AD9245
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DNC 1
CLK 2
24 VREF
23 SENSE
22 MODE
21 OTR
DNC 3
PDWN 4
(LSB) D0 5
D1 6
AD9245
CSP
TOP VIEW
20 D13 (MSB)
19 D12
(Not to Scale)
D2 7
18 D11
D3 8
17 D10
Figure 3. LFCSP Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 3
DNC
Do Not Connect
2
CLK
Clock Input Pin
4
PDWN
Power-Down Function Select
Data Output Bits
ꢁ to 14, 1ꢂ to 2±
1ꢁ
1ꢀ
21
22
23
24
2ꢁ
D± (LSB) to D13 (MSB)
DGND
DRVDD
OTR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
Digital Output Ground
Digital Output Driver Supply
Out-of-Range Indicator
Data Format Select and DCS Mode Selection (See Table 11)
Reference Mode Selection (See Table 1±)
Voltage Reference Input/Output
Differential Reference (–)
Differential Reference (+)
Analog Power Supply
2ꢀ
2ꢂ, 32
28, 31
2ꢃ
Analog Ground
Analog Input Pin (+)
VIN+
3±
VIN–
Analog Input Pin (–)
Rev. D | Page 11 of 32
AD9245
EQUIVALENT CIRCUITS
AVDD
DRVDD
D13-D0,
OTR
VIN+, VIN–
Figure 4. Equivalent Analog Input Circuit
Figure 6. Equivalent Digital Output Circuit
AVDD
AVDD
CLK,
PDWN
MODE
20kΩ
Figure 5. Equivalent MODE Input Circuit
Figure 7. Equivalent Digital Input Circuit
Rev. D | Page 12 of 32
AD9245
TYPICAL PERFORMANCE CHARACTERISTICS
DUT = AD9245-80, AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, DCS disabled, TA = 25°C, 2 V p-p differential input,
AIN = −0.5 dBFS, VREF = 1.0 V external, unless otherwise noted.
0
–10
100
90
80
70
60
50
40
SFDR (dBFS)
AIN = –0.5dBFS
SNR = 73.2dBc
ENOB = 11.8 BITS
SFDR = 92.8dBc
–20
SFDR (dBc)
–30
–40
SNR (dBFS)
–50
–60
SFDR = 90dBc
REFERENCE LINE
–70
–80
–90
SNR (dBc)
–100
–110
–120
0
5
10
15
20
25
30
35
40
–30
–25
–20
–15
–10
–5
0
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 11. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 2.5 MHz
Figure 8. Single Tone 8K FFT @ 2.5 MHz
0
–10
100
SFDR (dBFS)
AIN = –0.5dBFS
SNR = 72.7dBc
ENOB = 11.8 BITS
SFDR = 87.6dBc
–20
90
SFDR (dBc)
–30
–40
SNR (dBFS)
80
70
60
50
40
–50
–60
SFDR = 90dBc
–70
REFERENCE LINE
–80
–90
SNR (dBc)
–100
–110
–120
0
5
10
15
20
25
30
35
40
–30
–25
–20
–15
–10
–5
0
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 9. Single Tone 8K FFT @ 39 MHz
Figure 12. Single Tone SNR/SFDR vs. Input Amplitude (AIN) @ 39 MHz
0
–10
100
AIN = –0.5dBFS
SNR = 71.7dBc
ENOB = 11.5 BITS
SFDR = 81.6dBc
SFDR (DIFF)
–20
90
–30
SNR (DIFF)
SFDR (SE)
–40
80
70
–50
–60
–70
–80
SNR (SE)
–90
60
–100
–110
–120
50
0
20
40
60
80
100
0
5
10
15
20
25
30
35
40
SAMPLE RATE (MSPS)
FREQUENCY (MHz)
Figure 13. SNR/SFDR vs. Sample Rate @ 40 MHz
Figure 10. Single Tone 8K FFT @ 70 MHz
Rev. D | Page 13 of 32
AD9245
100
90
80
70
60
50
40
0
SFDR (dBFS)
AIN = –6.5dBFS
SNR = 73.4dBFS
SFDR = 86.0dBFS
–10
–20
SFDR (dBc)
–30
–40
–50
–60
SNR (dBFS)
–70
SFDR = 90dBc
REFERENCE LINE
–80
–90
SNR (dBc)
–100
–110
–120
–30
–27
–24
–21
–18
–15
–12
–9
–6
0
0
0
5
10
15
20
25
30
35
40
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 17. Two-Tone SNR/SFDR vs. Input Amplitude @ 30 MHz and 31 MHz
Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 MHz
100
0
–10
SFDR (dBFS)
AIN = –6.5dBFS
SNR = 72.7dBFS
SFDR = 78.8dBFS
90
–20
SFDR (dBc)
–30
80
–40
–50
70
–60
SNR (dBFS)
–70
SFDR = 90dBc
REFERENCE LINE
60
50
40
–80
–90
SNR (dBc)
–100
–110
–120
–30
–27
–24
–21
–18
–15
–12
–9
–6
5
10
15
20
25
30
35
40
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 15. Two-Tone 8K FFT @ 69 MHz and 70 MHz
Figure 18. Two-Tone SNR/SFDR vs. Input Amplitude @ 69 MHz and 70 MHz
1.5
1.0
1.0
0.8
0.6
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
2048
4096
6144
8192 10240 12288 14336 16384
CODE
Figure 16. Typical INL
Figure 19. Typical DNL
Rev. D | Page 14 of 32
AD9245
75
74
73
72
71
70
69
68
67
66
65
100
95
90
85
80
75
70
–40°C
+85°C
+25°C
–40°C
+25°C
+85°C
0
25
50
75
100
125
0
25
50
75
100
125
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 20. SNR vs. Input Frequency
Figure 23. SFDR vs. Input Frequency
0
90
88
86
84
82
80
78
76
74
72
70
SFDR (DCS ON)
–10
–20
–30
–40
SFDR (DCS OFF)
–50
–60
–70
–80
–90
–100
–110
–120
SNR (DCS OFF)
SNR (DCS ON)
50 55
DUTY CYCLE (%)
0
9.6
19.2
28.8
38.4
30
35
40
45
60
65
70
FREQUENCY (MHz)
Figure 21. SNR/SFDR vs. Clock Duty Cycle
Figure 24. Two 32K FFT CDMA-2000 Carriers @
FIN = 46.08 MHz; Sample Rate = 61.44 MSPS
0
–10
0
–10
–20
–30
–20
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
0
9.6
19.2
28.8
38.4
0
9.6
19.2
28.8
38.4
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 22. 32K FFT WCDMA Carrier @ FIN = 96 MHz; Sample Rate = 76.8 MSPS
Figure 25. Two 32K FFT WCDMA Carriers @
FIN = 76.8 MHz; Sample Rate = 61.44 MSPS
Rev. D | Page 1ꢁ of 32
AD9245
0
0
AIN = –0.5dBFS
SNR = 73.4dBc
ENOB = 11.9 BITS
SFDR = 88.3dBc
AIN = –0.5dBFS
SNR = 72.7dBc
ENOB = 11.7 BITS
SFDR = 81.3dBc
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
5
10
15
20
25
30
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 29. AD9245-40 Single Tone 16K FFT @ 19.7 MHz
Figure 26. AD9245-65 Single Tone 16K FFT @ 35 MHz
1.0
2.0
1.5
1.0
0.8
0.6
0.4
0.2
0.5
0
0
–0.2
–0.5
–0.4
–0.6
–0.8
–1.0
–1.0
–1.5
–2.0
0
2048 4096
6144 8192 10240 12288 14336 16384
CODE
0
2048
4096 6144
8192 10240 12288 14336 16384
CODE
Figure 27. AD9245-65 Typical INL
Figure 30. AD9245-65 Typical DNL
2.0
1.5
1.0
1.0
0.8
0.6
0.4
0.2
0.5
0
0
–0.2
–0.5
–0.4
–0.6
–0.8
–1.0
–1.0
–1.5
–2.0
0
2048
4096
6144
8192 10240 12288 14336 16384
CODE
0
2048
4096 6144 8192 10240 12288 14336 16384
CODE
Figure 28. AD9245-40 Typical INL
Figure 31. AD9245-40 Typical DNL
Rev. D | Page 1ꢀ of 32
AD9245
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.5
–0.4
–0.6
–0.8
–1.0
–1.0
–1.5
–2.0
0
2048
4096 6144 8192 10240 12288 14336 16384
CODE
0
2048 4096
6144 8192 10240 12288 14336 16384
CODE
Figure 32. AD9245-20 Typical INL
Figure 35. AD9245-20 Typical DNL
0
0
AIN = –0.5dBFS
AIN = –0.5dBFS
SNR = 73.3dBc
ENOB = 11.9 BITS
SFDR = 92.6dBc
SNR = 73.4dBc
ENOB = 11.9 BITS
SFDR = 95.0dBc
–20
–20
–40
–60
–40
–60
–80
–80
–100
–120
–100
–120
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 33. AD9245-20 Single Tone 16K FFT @ 5 MHz
Figure 36. AD9245-20 Single Tone 16K FFT @ 9.7 MHz
75
70
65
10004707
–0.5dBFS
–6dBFS
7996189
7281624
60
55
50
3167101
1755666
547498
N+3
–20dBFS
253625
N–3
N–2
N–1
N
N+1
N+2
1
10
100
CODE
INPUT FREQUENCY (MHz)
Figure 37. AD9245-20 Grounded-Input Histogram
Figure 34. AD9245-20 SINAD vs. Input Frequency
Rev. D | Page 1ꢂ of 32
AD9245
THEORY OF OPERATION
The AD9245 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections
consisting of a 4-bit first stage followed by eight 1.5-bit stages,
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 14-bit result
in the digital correction logic. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
Referring to Figure 39, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. In addition, a small shunt capacitor
can be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependent upon
the application. In IF undersampling applications, any shunt
capacitors should be reduced or removed. In combination with
the driving source impedance, they would limit the input
bandwidth.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
H
T
T
5pF
5pF
VIN+
VIN–
C
PAR
The input stage contains a differential SHA that can be
ac-coupled or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment of
the output voltage swing. During power-down, the output
buffers go into a high impedance state.
T
C
PAR
T
H
Figure 39. Switched-Capacitor SHA Input
ANALOG INPUT AND REFERENCE OVERVIEW
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
The analog input to the AD9245 is a differential switched-
capacitor SHA that has been designed for optimum performance
while processing a differential input signal. The SHA input can
support a wide common-mode range (VCM) and maintain
excellent performance, as shown in Figure 38. An input
common-mode voltage of midsupply minimizes signal-
dependent errors and provides optimum performance.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as:
100
95
SFDR (2.5MHz)
90
REFT = ½ (AVDD + VREF)
REFB = ½ (AVDD − VREF)
85
SFDR (39MHz)
80
Span = 2 × (REFT − REFB) = 2 × VREF
SNR (2.5MHz)
SNR (39MHz)
75
70
65
60
55
50
The previous equations show that the REFT and REFB voltages
are symmetrical about the midsupply voltage, and, by definition,
the input span is twice the value of the VREF voltage.
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9245 set
to the largest input span of 2 V p-p. The relative SNR degradation
is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.
0.5
1.0
1.5
2.0
2.5
3.0
COMMON-MODE LEVEL (V)
Figure 38. AD9245-80 SNR/SFDR vs. Common-Mode Level
Rev. D | Page 18 of 32
AD9245
The SHA can be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as
AVDD
33Ω
VIN+
2V p-p
49.9Ω
20pF
33Ω
AD9245
VREF
2
VCMMIN
VCMMAX
=
VIN–
AGND
(
AVDD +VREF
)
=
1kΩ
1kΩ
2
0.1μF
The minimum common-mode input level allows the AD9245 to
accommodate ground referenced inputs.
Figure 41. Differential Transformer-Coupled Configuration
Although optimum performance is achieved with a differential
input, a single-ended source can be applied to VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input is set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal can be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9245 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
can degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing (see Figure 13). However, if
the source impedances on each input are matched, there should
be little effect on SNR performance. Figure 42 details a typical
single-ended input configuration.
Differential Input Configurations
As previously detailed, optimum performance is achieved while
driving the AD9245 in a differential input configuration. For
baseband applications, the AD8351 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8351 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
1k
Ω
AVDD
VIN+
33
Ω
0.33μF
1k
2V p-p
49.9
Ω
Ω
20pF
33
AD9245
1k
1k
Ω
Ω
Ω
+
VIN–
AGND
1kΩ
0.1μF
1.2kΩ
10
μF
0.1μ
F
AVDD
VIN+
33Ω
0.1μF
25Ω
2V p-p
50Ω
20pF
25Ω
AD8351
AD9245
Figure 42. Single-Ended Input Configuration
0.1μF
33Ω
VIN–
AGND
0.1μF
CLOCK INPUT CONSIDERATIONS
1kΩ
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result can be sensitive
to clock duty cycle. Commonly a 5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9245-80 and AD9245-65 contain a clock duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows a
wide range of clock input duty cycles without affecting the
performance of the AD9245. As shown in Figure 21, noise and
distortion performance is nearly flat for a 30% to 70% duty cycle
with the DCS on.
Figure 40. Differential Input Configuration Using the AD8351
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9245. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The value of the shunt capacitor is dependent on
the input frequency and source impedance and should be
reduced or removed. An example is shown in Figure 41.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
Rev. D | Page 1ꢃ of 32
AD9245
which is determined by the sample rate and the characteristics
of the analog input signal.
JITTER CONSIDERATIONS
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated with the following equation:
450
400
AD9245-80
SNR = −20log10[2π fINPUT × tj]
350
In the equation, the rms aperture jitter represents the root-
mean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter
(see Figure 43).
300
AD9245-65
250
200
AD9245-40
150
The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the
AD9245. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last step.
AD9245-20
100
50
0
10
20
30
40
50
60
70
80
SAMPLE RATE (MSPS)
Figure 44. AD9245 Power vs. Sample Rate @ 2.5 MHz
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 44 was
taken with the same operating conditions as those reported in
the Typical Performance Characteristics section, and with a
5 pF load on each output driver.
75
0.2ps
70
MEASURED SNR
65
By asserting the PDWN pin high, the AD9245 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During standby,
the output drivers are placed in a high impedance state.
Reasserting the PDWN pin low returns the AD9245 to its
normal operational mode.
0.5ps
60
1.0ps
1.5ps
55
2.0ps
2.5ps
3.0ps
50
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
45
40
1
10
100
1000
INPUT FREQUENCY (MHz)
Figure 43. SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 44, the power dissipated by the AD9245 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current
(IDRVDD) can be calculated as
DIGITAL OUTPUTS
The AD9245 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies, which can affect converter performance.
Applications requiring the ADC to drive large capacitive loads or
large fanouts can require external buffers or latches.
IDRVDD = VDRVDD ×CLOAD × fCLK ×N
where N is the number of output bits, 14 in the case of the
AD9245. This maximum current occurs when every output bit
switches on every clock cycle, that is, a full-scale square wave at
the Nyquist frequency, fCLK/2. In practice, the DRVDD current
is established by the average number of output bits switching,
Rev. D | Page 2± of 32
AD9245
As detailed in Table 11, the data format can be selected for either
offset binary or twos complement.
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
TIMING
The AD9245 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
VIN+
VIN–
REFT
0.1μF
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9245. These transients can degrade the converter’s dynamic
performance.
+
ADC
CORE
0.1μF
10μF
REFB
0.1μF
VREF
0.1μF
+
10μF
The lowest typical conversion rate of the AD9245 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance can degrade.
SELECT
LOGIC
SENSE
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD9245. The input range can be adjusted by varying the
reference voltage applied to the AD9245 using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly. The various reference modes are summarized in Table 10
and described in the following sections.
0.5V
AD9245
Figure 45. Internal Reference Configuration
If the internal reference of the AD9245 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 46 depicts
how the internal reference voltage is affected by loading. A
2 mA load is the maximum recommended load.
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).
0.05
INTERNAL REFERENCE CONNECTION
A comparator within the AD9245 detects the potential at the
SENSE pin and configures the reference into one of four
possible states, which are summarized in Table 10. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 45), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in Figure 47, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
0
–0.05
0.5V ERROR (%)
–0.10
1.0V ERROR (%)
–0.15
–0.20
–0.25
R2
⎛
⎞
⎟
⎠
VREF = 0.5× 1+
0
0.5
1.0
1.5
LOAD (mA)
2.0
2.5
3.0
⎜
R1
⎝
Figure 46. VREF Accuracy vs. Load
Table 10. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
Internal Fixed Reference
Programmable Reference
AVDD
VREF
±.2 V to VREF
N/A
±.ꢁ
R2
2 × External Reference
1.±
2 × VREF
⎛
⎞
⎟
⎠
(See Figure 4ꢂ)
0.5 × 1 +
⎜
R1
⎝
Internal Fixed Reference
AGND to ±.2 V
1.±
2.±
Rev. D | Page 21 of 32
AD9245
OPERATIONAL MODE SELECTION
VIN+
VIN–
As discussed earlier, the AD9245 can output data in either
offset binary or twos complement format. There is also a
provision for enabling or disabling the clock DCS. The
MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined in Table 11.
REFT
0.1μF
0.1μF
REFB
+
ADC
CORE
10μF
0.1μF
VREF
+
Table 11. Mode Selection
10μF
0.1μF
SELECT
LOGIC
R2
MODE Voltage
Data Format
Duty Cycle Stabilizer
Disabled
Enabled
SENSE
AVDD
2/3 AVDD
1/3 AVDD
Twos Complement
Twos Complement
Offset Binary
R1
0.5V
Enabled
AGND (Default)
Offset Binary
Disabled
AD9245
Figure 47. Programmable Reference Configuration
EVALUATION BOARD
The AD9245 evaluation board provides the support circuitry
required to operate the ADC in its various modes and
configurations. Complete schematics and layout plots follow
and demonstrate the proper routing and grounding techniques
that should be applied at the system level.
EXTERNAL REFERENCE OPERATION
The use of an external reference can be necessary to enhance
the gain accuracy of the ADC or improve thermal drift char-
acteristics. When multiple ADCs track one another, a single
reference (internal or external) can be necessary to reduce
gain matching errors to an acceptable level. Figure 48 shows
the typical drift characteristics of the internal reference in both
1.0 V and 0.5 V modes.
It is critical that signal sources with very low phase noise
(<1 ps rms jitter) be used to realize the ultimate performance of
the converter. Proper filtering of the input signal, to remove
harmonics and lower the integrated noise at the input, is also
necessary to achieve the specified noise performance.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.0 V.
The AD9245 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input
configuration can be selected by proper connection of
various jumpers (refer to the schematics).
An alternative differential analog input path using an
AD8351 op amp is included in the layout but is not populated
in production. Designers interested in evaluating the op amp
with the ADC should remove C15, R12, and R3 and populate
the op amp circuit. The passive network between the AD8351
outputs and the AD9245 allows the user to optimize the
frequency response of the op amp for the application.
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
VREF = 1.0V
0.2
0.1
VREF = 0.5V
0
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 48. Typical VREF Drift
Rev. D | Page 22 of 32
AD9245
P 2
5 . 0 V
2 . 5 V
V A M P
V D L
G N D
2 . 5 V
3 . 0 V
V D D R
G N D
D D A V
D 1 0
D 1 1
D 1 2
D 1 3
O T
D 3
1 7
1 8
8
D 2 7
D 1
1 9
2 0
2 1
2 2
2 3
6
D 0
5
R
P D W N
4
D N C
M O D E
S E N S E
V R E F
3
C L K
2
D N C
1
2 4
Figure 49. LFCSP Evaluation Board Schematic—Analog Inputs and DUT
Rev. D | Page 23 of 32
AD9245
Figure 50. LFCSP Evaluation Board Schematic—Digital Path
Rev. D | Page 24 of 32
AD9245
Figure 51. LFCSP Evaluation Board Schematic—Clock Input
Rev. D | Page 2ꢁ of 32
AD9245
Figure 52. LFCSP Evaluation Board Layout, Primary Side
Figure 54. LFCSP Evaluation Board Layout, Ground Plane
Figure 53. LFCSP Evaluation Board Layout, Secondary Side
Figure 55. LFCSP Evaluation Board Layout, Power Plane
Rev. D | Page 2ꢀ of 32
AD9245
Figure 56. LFCSP Evaluation Board Layout, Primary Silkscreen
Figure 57. LFCSP Evaluation Board Layout, Secondary Silkscreen
Rev. D | Page 2ꢂ of 32
AD9245
Table 12. LFCSP Evaluation Board Bill of Materials
Recommended
Package Value Vendor/Part No.
Supplied
by ADI
Item Qty. Omit1 Reference Designator
Device
1
18
C1, Cꢁ, Cꢂ, C8, Cꢃ, C11, C12,
C13, C1ꢁ, C1ꢀ, C31, C33, C34,
C3ꢀ, C3ꢂ, C41, C43, C4ꢂ
Chip Capacitors
±ꢀ±3
±.1 μF
8
2
Cꢀ, C1ꢂ, C18, C2ꢂ,
C28, C3ꢁ, C4ꢁ, C44
2
3
8
8
C2, C3, C4, C1±, C2±,
C22, C2ꢁ, C2ꢃ
Tantalum Capacitors
Chip Capacitors
TAJC
±ꢀ±3
1± μF
C24, C4ꢀ
C14, C3±, C32, C38,
C3ꢃ, C4±, C48, C4ꢃ
±.±±1 μF
4
ꢁ
1
1
C1ꢃ
Chip Capacitors
Chip Capacitors
±ꢀ±3
±ꢀ±3
2± pF
1± pF
C2ꢀ
2
2
C21, C23
ꢀ
ꢃ
E31, E3ꢁ, E43, E44,
Eꢁ±, Eꢁ1, Eꢁ2, Eꢁ3
Headers
EHOLE
Jumper Blocks
E1, E4ꢁ
J1, J2
L1
ꢂ
8
2
1
SMA Connectors/ꢁ± Ω
Inductor
SMA
±ꢀ±3
1± nH
± Ω
Coilcraft/
±ꢀ±3CS-1±NXGBU
ꢃ
1
P2
Terminal Block
TBꢀ
Wieland/2ꢁ.ꢀ±2.2ꢀꢁ3.±,
zꢁ-ꢁ3±-±ꢀ2ꢁ-±
1±
11
1
ꢁ
P12
Header Dual 2±-Pin RT Angle HEADER4±
Digi-Key S2131-2±-ND
R3, R12, R23, R28, Rx
R1ꢀ, R1ꢂ, R22, R2ꢂ, R42, R3ꢂ
R4, R1ꢁ
Chip Resistors
±ꢀ±3
ꢀ
1
12
13
2
Chip Resistors
Chip Resistors
±ꢀ±3
±ꢀ±3
33 Ω
1 kΩ
14
Rꢁ, Rꢀ, Rꢂ, R8, R13, R2±, R21,
R24, R2ꢁ, R2ꢀ, R3±, R31, R32, R3ꢀ
14
1ꢁ
2
1
R1±, R11
R2ꢃ
Chip Resistors
Chip Resistors
±ꢀ±3
±ꢀ±3
3ꢀ Ω
ꢁ± Ω
R1ꢃ
1ꢀ
2
RP1, RP2
Resistor Packs
ADT1-1WT
R_ꢂ42
22± Ω Digi-Key
CTS/ꢂ42C1ꢀ3221JTR
1ꢂ
18
1ꢃ
2±
21
22
23
24
2ꢁ
2ꢀ
2ꢂ
28
Total
1
1
1
1
1
T1
AWT1-1T
Mini-Circuits
U1
ꢂ4LVTH1ꢀ23ꢂ4 CMOS Register TSSOP-48
U4
ADꢃ24ꢁBCP ADC (DUT)
ꢂ4VCX8ꢀM
LFCSP-32
SOIC-14
PCB
Analog Devices, Inc.
Fairchild
X
Uꢁ
PCB
ADꢃ2XXBCP/PCB
AD83ꢁ1 Op Amp
M/A-COM Transformer
Chip Resistors
Analog Devices, Inc.
Analog Devices, Inc.
X
X
1
1
ꢁ
3
2
1
1
U3
MSOP-8
T2
ETC1-1-13 1-1 TX M/A-COM/ETC1-1-13
R1, R2, Rꢃ, R38, R3ꢃ
R14, R18, R3ꢁ
R4±, R41
±ꢀ±3
±ꢀ±3
±ꢀ±3
SELECT
2ꢁ Ω
Chip Resistors
Chip Resistors
1± kΩ
1.2 kΩ
2ꢁ Ω
R34
Chip Resistor
R33
Chip Resistor
81 3ꢁ
1 These items are included in the PCB design, but are omitted at assembly.
Rev. D | Page 28 of 32
AD9245
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 58. 32-Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADꢃ24ꢁBCP-8±
Temperature Range
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
–4±°C to +8ꢁ°C
Package Description1
Package Option
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
CP-32-2
ADꢃ24ꢁBCPRLꢂ–8±
ADꢃ24ꢁBCPZ-8±2
ADꢃ24ꢁBCPZRLꢂ-8±2
ADꢃ24ꢁBCPZ-ꢀꢁ2
ADꢃ24ꢁBCPZRLꢂ-ꢀꢁ2
ADꢃ24ꢁBCPZ-4±2
ADꢃ24ꢁBCPZRLꢂ-4±2
ADꢃ24ꢁBCPZ-2±2
ADꢃ24ꢁBCPZRLꢂ-2±2
ADꢃ24ꢁBCP-8±EB
ADꢃ24ꢁBCP-ꢀꢁEB
ADꢃ24ꢁBCP-4±EB
ADꢃ24ꢁBCP-2±EB
Evaluation Board
Evaluation Board
Evaluation Board
1 It is recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the
maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board.
2 Z = Pb-free part.
Rev. D | Page 2ꢃ of 32
AD9245
NOTES
Rev. D | Page 3± of 32
AD9245
NOTES
Rev. D | Page 31 of 32
AD9245
NOTES
©
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03583–0–1/06(D)
Rev. D | Page 32 of 32
相关型号：
AD9245BCPZ-40
1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32, ROHS COMPLIANT, EXPOSED PAD, MO-220-VHHD-2, LFCSP-32
ROCHESTER
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