AD9249BBCZRL7-65 [ADI]
16 Channel, 14-Bit, 65 MSPS, Serial LVDS, 1.8 V ADC; 16通道， 14位， 65 MSPS ，串行LVDS ， 1.8 V ADC
| 型号： | AD9249BBCZRL7-65 |
| 厂家： | 
ADI |
| 描述： | 16 Channel, 14-Bit, 65 MSPS, Serial LVDS, 1.8 V ADC |
| 文件： | 总36页 (文件大小：1132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Channel, 14-Bit,
65 MSPS, Serial LVDS, 1.8 V ADC
Data Sheet
AD9249
FEATURES
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN DRVDD
Low power
AD9249
D+A1
D–A1
16 ADC channels integrated into 1 package
58 mW per channel at 65 MSPS with scalable power options
35 mW per channel at 20 MSPS
SNR: 75 dBFS (to Nyquist); SFDR: 90 dBc (to Nyquist)
DNL: 0.6 LSB (typical); INL: 0.9 LSB (typical)
Crosstalk, worst adjacent channel, 10 MHz, −1 dBFS: −90 dB
typical
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
14
VIN+A1
VIN–A1
SERIAL
LVDS
ADC
ADC
REF
D+A2
D–A2
14
VIN+A2
VIN–A2
SERIAL
LVDS
ADC
D+H1
D–H1
14
VIN+H1
VIN–H1
SERIAL
LVDS
D+H2
D–H2
14
VIN+H2
VIN–H2
SERIAL
LVDS
ADC
VREF
FCO+1, FCO+2
FCO–1, FCO–2
SENSE
1.0V
DATA
RATE
MULTIPLIER
VCM1, VCM2
SYNC
650 MHz full power analog bandwidth
2 V p-p input voltage range
DCO+1, DCO+2
DCO–1, DCO–2
SERIAL PORT
INTERFACE
SELECT
1.8 V supply operation
RBIAS1,
RBIAS2
GND CSB1, SDIO/ SCLK/
CSB2 DFS DTP
CLK+ CLK–
Serial port control
Flexible bit orientation
Figure 1.
Built in and custom digital test pattern generation
Programmable clock and data alignment
Power-down and standby modes
APPLICATIONS
Medical imaging
Communications receivers
Multichannel data acquisition
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation.
GENERAL DESCRIPTION
The available digital test patterns include built-in deterministic
and pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9249 is a 16-channel, 14-bit, 65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The device operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low power
in applications where a small package size is critical.
The AD9249 is available in an RoHS-compliant, 144-ball CSP-
BGA. It is specified over the industrial temperature range of −40°C
to +85°C. This product is protected by a U.S. patent.
The ADC requires a single 1.8 V power supply and an LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
PRODUCT HIGHLIGHTS
1. Small Footprint. Sixteen ADCs are contained in a small,
10 mm × 10 mm package.
2. Low Power. 35 mW/channel at 20 MSPS with scalable power
options.
3. Ease of Use. Data clock outputs (DCO 1, DCO 2) operate
at frequencies of up to 455 MHz and support double data
rate (DDR) operation.
The AD9249 automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. Data clock outputs (DCO 1,
DCO 2) for capturing data on the output and frame clock outputs
(FCO 1, FCO 2) for signaling a new output byte are provided.
Individual channel power-down is supported, and the device
typically consumes less than 2 mW when all channels are disabled.
4. User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9249
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Outputs and Timing ..................................................... 21
Built-In Output Test Modes .......................................................... 25
Output Test Modes..................................................................... 25
Serial Port Interface (SPI).............................................................. 26
Configuration Using the SPI..................................................... 26
Hardware Interface..................................................................... 27
Configuration Without the SPI ................................................ 27
SPI Accessible Features.............................................................. 27
Memory Map .................................................................................. 28
Reading the Memory Map Register Table............................... 28
Memory Map Register Table..................................................... 29
Memory Map Register Descriptions........................................ 32
Applications Information .............................................................. 34
Design Guidelines ...................................................................... 34
Power and Ground Recommendations................................... 34
Board Layout Considerations ................................................... 34
Clock Stability Considerations ................................................. 35
VCM............................................................................................. 35
Reference Decoupling................................................................ 35
SPI Port ........................................................................................ 35
Outline Dimensions....................................................................... 36
Ordering Guide .......................................................................... 36
Applications....................................................................................... 1
General Description ......................................................................... 1
Simplified Functional Block Diagram ........................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Analog Input Considerations.................................................... 17
Voltage Reference ....................................................................... 18
Clock Input Considerations ...................................................... 19
Power Dissipation and Power-Down Mode ........................... 21
REVISION HISTORY
10/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
Data Sheet
AD9249
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN DRVDD
AD9249
D+A1
D–A1
14
14
14
14
14
14
14
14
VIN+A1
SERIAL
LVDS
ADC
VIN–A1
D+A2
D–A2
14
VIN+A2
VIN–A2
SERIAL
LVDS
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
D+B1
D–B1
VIN+B1
VIN–B1
SERIAL
LVDS
ADC
ADC
ADC
ADC
ADC
ADC
ADC
D+B2
D–B2
14
14
14
14
14
14
14
VIN+B2
VIN–B2
SERIAL
LVDS
D+C1
D–C1
VIN+C1
VIN–C1
SERIAL
LVDS
D+C2
D–C2
VIN+C2
VIN–C2
SERIAL
LVDS
D+D1
D–D1
VIN+D1
VIN–D1
SERIAL
LVDS
D+D2
D–D2
VIN+D2
VIN–D2
SERIAL
LVDS
D+E1
D–E1
VIN+E1
VIN–E1
SERIAL
LVDS
D+E2
D–E2
VIN+E2
VIN–E2
SERIAL
LVDS
D+F1
D–F1
VIN+F1
VIN–F1
SERIAL
LVDS
D+F2
D–F2
VIN+F2
VIN–F2
SERIAL
LVDS
D+G1
D–G1
VIN+G1
VIN–G1
SERIAL
LVDS
D+G2
D–G2
VIN+G2
VIN–G2
SERIAL
LVDS
D+H1
D–H1
VIN+H1
VIN–H1
SERIAL
LVDS
D+H2
D–H2
VIN+H2
VIN–H2
SERIAL
LVDS
VREF
FCO+1, FCO+2
FCO–1, FCO–2
SENSE
1.0V
DATA
RATE
MULTIPLIER
VCM1, VCM2
SYNC
REF
SELECT
DCO+1, DCO+2
DCO–1, DCO–2
SERIAL PORT
INTERFACE
RBIAS1,
RBIAS2
GND CSB1, SDIO/ SCLK/
CSB2 DFS DTP
CLK+ CLK–
Figure 2.
Rev. 0 | Page 3 of 36
AD9249
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1.
Parameter1
Temp
Min
Typ
Max
Unit
RESOLUTION
14
Bits
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Full
Full
Full
Full
Full
Full
Full
Guaranteed
0.24
0.24
−3.5
1.8
0.6
0
0
−7.2
0
−0.9
−3.0
0.8
0.7
+0.2
6.0
+1.6
+3.0
% FSR
% FSR
% FSR
% FSR
LSB
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
0.9
LSB
Full
Full
−1.8
3.6
ppm/°C
ppm/°C
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
Full
25°C
Full
0.98
1.0
3
7.5
1.01
V
mV
kΩ
INPUT REFERRED NOISE
VREF = 1.0 V
25°C
0.98
LSB rms
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Common-Mode Range
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
Full
Full
Full
Full
Full
2
0.9
V p-p
V
V
kΩ
pF
0.5
1.3
5.2
3.5
AVDD
DRVDD
IAVDD
Full
Full
Full
Full
25°C
1.7
1.7
1.8
1.8
395
118
88
1.9
1.9
429
124
V
V
mA
mA
mA
IDRVDD (ANSI-644 Mode)
IDRVDD (Reduced Range Mode)
TOTAL POWER CONSUMPTION
Total Power Dissipation (16 Channels, ANSI-644 Mode)
Total Power Dissipation (16 Channels, Reduced Range Mode) 25°C
Power-Down Dissipation
Standby Dissipation2
Full
924
869
2
995
mW
mW
mW
mW
25°C
25°C
199
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for information about how these tests were completed.
2 Controlled via the SPI.
Rev. 0 | Page 4 of 36
Data Sheet
AD9249
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2.
Parameter1
Temp
Min
Typ
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 48 MHz
fIN = 69.5 MHz
fIN = 118 MHz
fIN = 139.5 MHz
25°C
Full
25°C
25°C
25°C
25°C
75.4
75.3
74.7
74.4
72.8
72.2
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
74.4
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 48 MHz
fIN = 69.5 MHz
fIN = 118 MHz
fIN = 139.5 MHz
25°C
Full
25°C
25°C
25°C
25°C
75.4
75.3
74.7
74.4
72.6
71.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
74.0
12.0
85
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 48 MHz
fIN = 69.5 MHz
fIN = 118 MHz
fIN = 139.5 MHz
25°C
Full
25°C
25°C
25°C
25°C
12.2
12.2
12.1
12.1
11.8
11.6
Bits
Bits
Bits
Bits
Bits
Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 48 MHz
fIN = 69.5 MHz
fIN = 118 MHz
fIN = 139.5 MHz
25°C
Full
25°C
25°C
25°C
25°C
95
93
94
92
83
82
dBc
dBc
dBc
dBc
dBc
dBc
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 48 MHz
fIN = 69.5 MHz
fIN = 118 MHz
fIN = 139.5 MHz
25°C
Full
25°C
25°C
25°C
25°C
−98
−93
−94
−92
−83
−82
dBc
dBc
dBc
dBc
dBc
dBc
−85
−86
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 19.7 MHz
fIN = 48 MHz
fIN = 69.5 MHz
fIN = 118 MHz
fIN = 139.5 MHz
25°C
Full
25°C
25°C
25°C
25°C
−95
−96
−94
−92
−90
−90
dBc
dBc
dBc
dBc
dBc
dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 30.1 MHz, fIN2 = 32.1 MHz
CROSSTALK, WORST ADJACENT CHANNEL2
Crosstalk, Worst Adjacent Channel Overrange Condition3
ANALOG INPUT BANDWIDTH, FULL POWER
25°C
25°C
25°C
25°C
92
dBc
dB
dB
−90
−85
650
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Crosstalk is measured at 10 MHz, with −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3 Overrange condition is defined as 3 dB above input full scale.
Rev. 0 | Page 5 of 36
AD9249
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
Temp Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Full
Full
Full
25°C
25°C
0.2
GND − 0.2
3.6
AVDD + 0.2
V p-p
V
V
kΩ
pF
0.9
15
4
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
1.2
0
AVDD + 0.2
0.8
V
V
Input Resistance
Input Capacitance
25°C
25°C
30
2
kΩ
pF
LOGIC INPUTS (CSB1, CSB2)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
1.2
0
AVDD + 0.2
0.8
V
V
Input Resistance
Input Capacitance
25°C
25°C
26
2
kΩ
pF
LOGIC INPUT (SDIO)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
1.2
0
AVDD + 0.2
0.8
V
V
Input Resistance
Input Capacitance
25°C
25°C
26
5
kΩ
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D x1, D x2), ANSI-644
Logic Compliance
Full
Full
1.79
V
V
0.05
LVDS
Differential Output Voltage (VOD
)
Full
Full
281
1.12
350
1.22
422
1.38
mV
V
Output Offset Voltage (VOS
Output Coding (Default)
)
Twos complement
DIGITAL OUTPUTS (D x1, D x2), LOW POWER,
REDUCED SIGNAL OPTION
Logic Compliance
LVDS
Differential Output Voltage (VOD
)
Full
Full
150
1.12
201
1.22
250
1.38
mV
V
Output Offset Voltage (VOS
Output Coding (Default)
)
Twos complement
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO/DFS pins sharing the same connection.
Rev. 0 | Page 6 of 36
Data Sheet
AD9249
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
Symbol
Temp
Min
Typ
Max
Unit
CLOCK3
Input Clock Rate
Conversion Rate
Full
Full
Full
Full
10
10
520
65
MHz
MSPS
ns
Clock Pulse Width High
Clock Pulse Width Low
OUTPUT PARAMETERS3
Propagation Delay
Rise Time (20% to 80%)
Fall Time (20% to 80%)
FCO 1, FCO 2 Propagation Delay
DCO 1, DCO 2 Propagation Delay4
DCO 1, DCO 2 to Data Delay4
DCO 1, DCO 2 to FCO 1, FCO 2 Delay4
Data to Data Skew
tEH
tEL
7.69
7.69
ns
tPD
tR
tF
tFCO
tCPD
tDATA
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
1.5
1.5
2.3
300
300
2.3
3.1
3.1
ns
ps
ps
ns
ns
tFCO + (tSAMPLE/28)
(tSAMPLE/28)
(tSAMPLE/28)
50
35
(tSAMPLE/28) − 300
(tSAMPLE/28) − 300
(tSAMPLE/28) + 300 ps
(tSAMPLE/28) + 300 ps
200
tFRAME
tDATA-MAX − tDATA-MIN
ps
μs
μs
Clock
cycles
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)5
Pipeline Latency
375
16
APERTURE
Aperture Delay
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
tA
tJ
25°C
25°C
25°C
1
135
1
ns
fs rms
Clock
cycles
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
3 Adjustable using the SPI.
4 tSAMPLE/28 is based on the number of bits, divided by 2, because the delays are based on half duty cycles. tSAMPLE = 1/fSAMPLE
5 Wake-up time is defined as the time required to return to normal operation from power-down mode.
.
Rev. 0 | Page 7 of 36
AD9249
Data Sheet
Timing Diagrams
Refer to the Memory Map Register Descriptions section for SPI register setting of output mode.
N – 1
VIN±x1,
VIN±x2
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–1,
DCO–2
DCO+1,
DCO+2
tFCO
tFRAME
FCO–1,
FCO–2
FCO+1,
FCO+2
tPD
tDATA
D–x1,
D–x2
MSB D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB
D12
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16
D+x1,
D+x2
Figure 3. Wordwise DDR, 1× Frame, 14-Bit Output Mode (Default)
N – 1
VIN±x1,
VIN±x2
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–1,
DCO–2
DCO+1,
DCO+2
tFRAME
tFCO
FCO–1,
FCO–2
FCO+1,
FCO+2
tPD
tDATA
D–x1,
D–x2
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB
D10
N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16
D+x1,
D+x2
Figure 4. Wordwise DDR, 1× Frame, 12-Bit Output Mode
Rev. 0 | Page 8 of 36
Data Sheet
AD9249
TIMING SPECIFICATIONS
Table 5.
Parameter
Description
Limit
Unit
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
See Figure 50
0.24
0.40
ns typ
ns typ
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB1/CSB2 and SCLK
Hold time between CSB1/CSB2 and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 50)
2
2
40
2
2
10
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 50)
10
ns min
SYNC Timing Diagram
CLK+
tSSYNC
tHSYNC
SYNC
Figure 5. SYNC Input Timing Requirements
Rev. 0 | Page 9 of 36
AD9249
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
THERMAL CHARACTERISTICS
Rating
Typical θJA is specified for a 4-layer PCB with a solid ground plane.
Airflow improves heat dissipation, which reduces θJA. In addition,
metal in direct contact with the package leads from metal traces,
Electrical
AVDD to GND
DRVDD to GND
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
through holes, ground, and power planes reduces θJA
.
Digital Outputs
(D x1, D x2, DCO 1, DCO 2,
FCO 1, FCO 2) to GND
CLK+, CLK− to GND
VIN x1, VIN x2 to GND
SCLK/DTP, SDIO/DFS, CSB1, CSB2 to GND
SYNC, PDWN to GND
RBIAS1, RBIAS2 to GND
VREF, VCM1, VCM2, SENSE to GND
Environmental
Table 7. Thermal Resistance (Simulated)
Airflow Velocity
(m/sec)
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
1, 2
1, 2
Package Type
θJA
30.2
ΨJT
0.13
Unit
144-Ball,
0
°C/W
10 mm × 10 mm
CSP-BGA
1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
−40°C to +85°C
150°C
300°C
ESD CAUTION
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 10 of 36
Data Sheet
AD9249
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9249
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
D
E
F
VIN–G2
VIN+G2
VIN–G1
VIN–F2
VIN–F1
VIN–E2
VIN–E1
VIN–D2
VIN–D1
VIN–C2
VIN+C1
VIN–C1
VIN–H1
VIN–H2
GND
VIN+H1
VIN+H2
GND
VIN+G1
SYNC
GND
VIN+F2
VCM1
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
DRVDD
D+E1
VIN+F1
VCM2
AVDD
GND
VIN+E2
VREF
AVDD
GND
VIN+E1
SENSE
AVDD
GND
VIN+D2
RBIAS1
AVDD
GND
VIN+D1
RBIAS2
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
DRVDD
D+D2
VIN+C2
GND
VIN+B2
VIN+B1
VIN+A2
VIN+A1
VIN–B2
VIN–B1
VIN–A2
VIN–A1
GND
CLK–
GND
CLK+
GND
GND
CSB1
CSB2
PDWN
GND
GND
GND
GND
GND
GND
SDIO/DFS SCLK/DTP
G
H
J
D–H2
D–H1
D–G2
D–G1
D–F2
D–F1
D+H2
D+H1
D+G2
D+G1
D+F2
D+F1
GND
GND
GND
GND
GND
D+A1
D+A2
D+B1
D+B2
D+C1
D+C2
D–A1
D–A2
D–B1
D–B2
D–C1
D–C2
GND
GND
GND
GND
GND
GND
AVDD
GND
AVDD
GND
AVDD
GND
AVDD
GND
GND
K
L
DRVDD
D+E2
D–E2
DRVDD
D+D1
D–D1
FCO+1
FCO–1
DCO+1
DCO–1
DCO+2
DCO–2
FCO+2
FCO–2
M
D–E1
D–D2
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
C10, D1 to D3, D10,
E3, E5 to E8, F1 to F3,
F5 to F8, G3, G5 to G8,
H3, H5 to H8, H10, J3,
J10, K5 to K8
GND
Ground.
D4 to D9, E4, E9, F4,
F9, G4, G9, H4, H9,
J4 to J9
AVDD
1.8 V Analog Supply.
K3, K4, K9, K10
E1, E2
G12, G11
H12, H11
J12, J11
DRVDD
1.8 V Digital Output Driver Supply.
Input Clock Complement, Input Clock True.
CLK−, CLK+
D−A1, D+A1
D−A2, D+A2
D−B1, D+B1
D−B2, D+B2
D−C1, D+C1
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
K12, K11
L12, L11
Rev. 0 | Page 11 of 36
AD9249
Data Sheet
Pin No.
M12, M11
M10, L10
M9, L9
M4, L4
M3, L3
M1, M2
L1, L2
K1, K2
J1, J2
H1, H2
G1, G2
Mnemonic
D−C2, D+C2
D−D1, D+D1
D−D2, D+D2
D−E1, D+E1
D−E2, D+E2
D−F1, D+F1
D−F2, D+F2
D−G1, D+G1
D−G2, D+G2
D−H1, D+H1
D−H2, D+H2
Description
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
Bank 1 Digital Output Complement, Bank 1 Digital Output True.
Bank 2 Digital Output Complement, Bank 2 Digital Output True.
M6, L6,
M7, L7
DCO−1, DCO+1, Data Clock Digital Output Complement, Data Clock Digital Output True. DCO 1 is used to
DCO−2, DCO+2
capture D x1 digital output data; DCO 2 is used to capture D x2 digital output data.
M5, L5,
M8, L8
FCO−1, FCO+1,
FCO−2, FCO+2
Frame Clock Digital Output Complement, Frame Clock Digital Output True. FCO 1 frames D x1
digital output data; FCO 2 frames D x2 digital output data.
F12
F11
E10, F10
SCLK/DTP
SDIO/DFS
CSB1, CSB2
Serial Clock (SCLK)/Digital Test Pattern (DTP).
Serial Data Input/Output (SDIO)/Data Format Select (DFS).
Chip Select Bar. CSB1 enables/disables SPI for eight channels in Bank 1; CSB2 enables/disables
SPI for eight channels in Bank 2.
G10
PDWN
Power-Down.
E12, E11
D12, D11
C12, C11
B12, B11
A12, A11
A10, B10
A9, B9
VIN−A1, VIN+A1 Analog Input Complement, Analog Input True.
VIN−A2, VIN+A2 Analog Input Complement, Analog Input True.
VIN−B1, VIN+B1 Analog Input Complement, Analog Input True.
VIN−B2, VIN+B2 Analog Input Complement, Analog Input True.
VIN−C1, VIN+C1 Analog Input Complement, Analog Input True.
VIN−C2, VIN+C2 Analog Input Complement, Analog Input True.
VIN−D1,
VIN+D1
Analog Input Complement, Analog Input True.
A8, B8
VIN−D2,
VIN+D2
Analog Input Complement, Analog Input True.
A7, B7
A6, B6
A5, B5
A4, B4
A3, B3
VIN−E1, VIN+E1 Analog Input Complement, Analog Input True.
VIN−E2, VIN+E2 Analog Input Complement, Analog Input True.
VIN−F1, VIN+F1 Analog Input Complement, Analog Input True.
VIN−F2, VIN+F2 Analog Input Complement, Analog Input True.
VIN−G1,
VIN+G1
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
Analog Input Complement, Analog Input True.
A1, A2
B1, B2
C1, C2
VIN−G2,
VIN+G2
VIN−H1,
VIN+H1
VIN−H2,
VIN+H2
C8, C9
C7
RBIAS1, RBIAS2
SENSE
Sets analog current bias. Connect each RBIASx pin to a 10 kΩ (1% tolerance) resistor to ground.
Reference Mode Selection.
C6
VREF
Voltage Reference Input/Output.
C4, C5
VCM1, VCM2
Analog Output Voltage at Midsupply. Sets the common mode of the analog inputs, external to
the ADC, as shown in Figure 35 and Figure 36.
C3
SYNC
Digital Input; Synchronizing Input to Clock Divider. This pin is internally pulled to ground by a
30 kΩ resistor.
Rev. 0 | Page 12 of 36
Data Sheet
AD9249
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–20
A
f
= –1dBFS
A
= –1dBFS
IN
= 69.5MHz
IN
= 9.7MHz
f
IN
IN
SNR = 75.47dBFS
SINAD = 74.45dBc
SFDR = 96.6dBc
SNR = 74.41dBFS
SINAD = 73.37dBc
SFDR = 92.3dBc
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Single-Tone 32k FFT with fIN = 9.7 MHz, fSAMPLE = 65 MSPS
Figure 10. Single-Tone 32k FFT with fIN = 69.5 MHz, fSAMPLE = 65 MSPS
0
0
A
f
= –1dBFS
= 118MHz
A
f
= –1dBFS
= 19.7MHz
IN
IN
IN
IN
SNR = 72.86dBFS
SINAD = 71.55dBc
SFDR = 83.3dBc
SNR = 75.39dBFS
SINAD = 74.35dBc
SFDR = 95.8dBc
–20
–40
–20
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. Single-Tone 32k FFT with fIN = 118 MHz, fSAMPLE = 65 MSPS
Figure 8. Single-Tone 32k FFT with fIN = 19.7 MHz, fSAMPLE = 65 MSPS
0
0
A
f
= –1dBFS
= 139.5MHz
A
f
= –1dBFS
= 48MHz
IN
IN
IN
IN
SNR = 72.22dBFS
SINAD = 70.84dBc
SFDR = 82.7dBc
SNR = 74.78dBFS
SINAD = 73.75dBc
SFDR = 96.6dBc
–20
–40
–20
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Single-Tone 32k FFT with fIN = 139.5 MHz, fSAMPLE = 65 MSPS
Figure 9. Single-Tone 32k FFT with fIN = 48 MHz, fSAMPLE = 65 MSPS
Rev. 0 | Page 13 of 36
AD9249
Data Sheet
0
0
–20
A
f
= –1dBFS
= 139.5MHz
IN
IN
SNR = 72.74dBFS
SINAD = 71.45dBc
SFDR = 84dBc
–20
–SFDR (dBc)
–40
–40
IMD3 (dBc)
–60
–60
–80
–80
–100
–120
–SFDR (dBFS)
IMD3 (dBFS)
–100
–120
–140
0
5
10
15
20
25
30
–90
–80
–70
–60
–50
–40
–30
–20
–10
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 13. Single-Tone 32k FFT with fIN = 139.5 MHz, fSAMPLE = 65 MSPS,
Clock Divider = 4
Figure 16. Two-Tone SFDR/IMD3 vs. Input Amplitude; fIN1 = 30.1 MHz,
f
IN2 = 32.1 MHz, fSAMPLE = 65 MSPS
120
110
100
90
80
70
60
50
40
30
20
10
0
SFDR (dBFS)
100
SFDR (dBc)
SNRFS (dBFS)
80
SNRFS (dBFS)
60
SFDR (dBc)
40
SNR (dB)
20
0
–20
0
50
100 150 200 250 300 350 400 450 500
INPUT FREQUENCY (MHz)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
Figure 17. SNR/SFDR vs. fIN; fSAMPLE = 65 MSPS
Figure 14. SNR/SFDR vs. Input Amplitude; fIN = 9.7 MHz, fSAMPLE = 65 MSPS
0
105
A
f
= –7dBFS
= 30.1MHz, 32.1MHz
IN
IN
100
95
90
85
80
75
70
65
IMD2 = –95.4dBc
IMD3 = –95.4dBc
SFDR = 93.0dBc
–20
–40
SFDR (dBc)
–60
2F2 – F1
F1 + 2F2
–80
2F1 – F2
2F1 + F2
F2 – F1
F1 + F2
SNRFS (dBFS)
–100
–120
–140
–40
–15
10
35
60
85
0
5
10
15
20
25
30
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 15. Two Tone FFT, fIN = 30.1 MHz and 32.1 MHz, fSAMPLE = 65 MSPS
Figure 18. SNR/SFDR vs. Temperature; fIN = 9.7 MHz, fSAMPLE = 65 MSPS
Rev. 0 | Page 14 of 36
Data Sheet
AD9249
0.8
110
105
100
95
0.6
SFDR (dBc)
0.4
0.2
90
0
85
80
–0.2
–0.4
–0.6
–0.8
SNRFS (dBFS)
75
70
65
60
0
2000 4000 6000 8000 10000 12000 14000 16000
20
30
40
50
60
70
80
OUTPUT CODE
SAMPLE RATE (MSPS)
Figure 22. SNR/SFDR vs. Sample Rate; fIN = 9.7 MHz, fSAMPLE = 65 MSPS
Figure 19. INL; fIN = 9.7 MHz, fSAMPLE = 65 MSPS
110
105
0.8
0.6
SFDR (dBc)
100
0.4
95
90
85
80
0.2
0
–0.2
–0.4
–0.6
–0.8
SNRFS (dBFS)
75
70
65
60
0
2000 4000 6000 8000 10000 12000 14000 16000
OUTPUT CODE
20
30
40
50
60
70
80
SAMPLE RATE (MSPS)
Figure 20. DNL; fIN = 9.7 MHz, fSAMPLE = 65 MSPS
Figure 23. SNR/SFDR vs. Sample Rate; fIN =19.7 MHz, fSAMPLE = 65 MSPS
900000
800000
700000
600000
500000
400000
300000
200000
100000
0
0.98 LSB RMS
OUTPUT CODE
Figure 21. Input Referred Noise Histogram; fSAMPLE = 65 MSPS
Rev. 0 | Page 15 of 36
AD9249
Data Sheet
EQUIVALENT CIRCUITS
AVDD
AVDD
VIN±x1,
VIN±x2
350Ω
SCLK/DTP, SYNC,
AND PDWN
30kΩ
Figure 24. Equivalent Analog Input Circuit
Figure 28. Equivalent SCLK/DTP, SYNC, and PDWN Input Circuit
AVDD
10Ω
CLK+
AVDD
15kΩ
15kΩ
0.9V
AVDD
375Ω
RBIAS1, RBIAS2
AND VCM1, VCM2
10Ω
CLK–
Figure 25. Equivalent Clock Input Circuit
Figure 29. Equivalent RBIASx and VCMx Circuit
AVDD
AVDD
30kΩ
350Ω
SDIO/DFS
30kΩ
350Ω
30kΩ
CSB1, CSB2
Figure 26. Equivalent SDIO/DFS Input Circuit
Figure 30. Equivalent CSBx Input Circuit
DRVDD
AVDD
V
V
D–x1, D–x2
D+x1, D+x2
V
V
375Ω
VREF
7.5kΩ
DRGND
Figure 27. Equivalent Digital Output Circuit
Figure 31. Equivalent VREF Circuit
Rev. 0 | Page 16 of 36
Data Sheet
AD9249
THEORY OF OPERATION
the output stage of the driving source. In addition, low Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and, therefore,
achieve the maximum bandwidth of the ADC. Such use of low
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Place either a differential capacitor
or two single-ended capacitors on the inputs to provide a matching
passive network. This configuration ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-
Capacitor ADCs; and the Analog Dialogue article “Transformer-
Coupled Front-End for Wideband A/D Converters” (Volume 39,
April 2005) for more information. In general, the precise values
vary, depending on the application.
The AD9249 is a multistage, pipelined ADC. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stage. The quantized outputs from each stage are
combined into a final 14-bit result in the digital correction
logic. The serializer transmits this converted data in a 14-bit
output. The pipelined architecture permits the first stage to
operate with a new input sample while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
Input Common Mode
The analog inputs of the AD9249 are not internally dc biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. For optimum performance, set the device
so that VCM = AVDD/2. However, the device can function over
a wider range with reasonable performance, as shown in
Figure 33.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9249 is a differential switched
capacitor circuit designed for processing differential input signals.
This circuit can support a wide common-mode range while
maintaining excellent performance. By using an input common-
mode voltage of midsupply, users can minimize signal dependent
errors and achieve optimum performance.
An on-chip, common-mode voltage reference is included in the
design and is available at the VCMx pin. Decouple the VCMx pin
to ground using a 0.1 µF capacitor, as described in the Applications
Information section.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9249, the largest available input span is 2 V p-p.
110
H
CPAR
H
100
VIN+ x
CSAMPLE
SFDR (dBc)
90
S
S
S
S
80
CSAMPLE
VIN– x
SNRFS (dBFS)
70
60
50
40
30
20
H
CPAR
H
Figure 32. Switched Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 32). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor, in series with each
input, can help reduce the peak transient current injected from
0.5
0.6
0.7
0.8
0.9
(V)
1.0
1.1
1.2
1.3
V
CM
Figure 33. SNR/SFDR vs. Common-Mode Voltage,
IN = 9.7 MHz, fSAMPLE = 65 MSPS
f
Rev. 0 | Page 17 of 36
AD9249
Data Sheet
Differential Input Configurations
Internal Reference Connection
There are several ways to drive the AD9249, either actively or
passively. However, optimum performance is achieved by driving
the analog inputs differentially. Using a differential double balun
configuration to drive the AD9249 provides excellent performance
and a flexible interface to the ADC (see Figure 35) for baseband
applications. Similarly, differential transformer coupling also
provides excellent performance (see Figure 36).
A comparator within the AD9249 detects the potential at the
SENSE pin and configures the reference into two possible
modes, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 34), setting VREF to 1.0 V.
Table 9. Reference Configuration Summary
Resulting
Differential
Span (V p-p)
Because the noise performance of most amplifiers is not adequate
to achieve the true performance of the AD9249, use of these
passive configurations is recommended wherever possible.
SENSE
Resulting
VREF (V)
Selected Mode Voltage (V)
Fixed Internal
Reference
GND to 0.2
1.0 internal
2.0
Regardless of the configuration, the value of the shunt capacitor, C,
is dependent on the input frequency and may need to be reduced
or removed.
Fixed External
Reference
AVDD
1.0 applied
to external
VREF pin
2.0
It is recommended that the AD9249 inputs not be driven single-
ended.
VIN+x1, VIN+x2
VIN–x1, VIN–x2
VOLTAGE REFERENCE
ADC
CORE
A stable and accurate 1.0 V voltage reference is built into the
AD9249. Configure VREF using either the internal 1.0 V
reference or an externally applied 1.0 V reference voltage. The
various reference modes are summarized in the Internal Reference
Connection section and the External Reference Operation section.
Bypass the VREF pin to ground externally, using a low ESR,
1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic
capacitor.
VREF
0.1µF
1.0µF
SELECT
LOGIC
SENSE
0.5V
ADC
Figure 34. Internal Reference Configuration
0.1µF
R
*C1
5pF
0.1µF
VIN+x1,
VIN+x2
33Ω
33Ω
33Ω
C
2V p-p
C
ADC
VCM1,
VCM2
0.1µF
C
VIN–x1,
VIN–x2
R
33Ω
ET1-1-I3
*C1
R
200Ω
*C1 IS OPTIONAL
0.1µF
C
0.1µF
Figure 35. Differential Double Balun Input Configuration for Baseband Applications
ADT1-1WT
1:1 Z RATIO
*C1
R
VIN+x1,
VIN+x2
33Ω
2Vp-p
49.9Ω
ADC
C
5pF
*C1
VIN–x1, VCM1,
VIN–x2 VCM2
R
33Ω
200Ω
0.1µF
0.1μF
*C1 IS OPTIONAL
Figure 36. Differential Transformer Coupled Configuration for Baseband Applications
Rev. 0 | Page 18 of 36
Data Sheet
AD9249
If the internal reference of the AD9249 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 37 shows
how the internal reference voltage is affected by loading.
0
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9249 sample clock inputs,
CLK+ and CLK−, with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK− pins via a transformer or
capacitors. These pins are biased internally (see Figure 25) and
require no external bias.
–0.5
–1.0
Clock Input Options
INTERNAL V
= 1V
REF
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
The AD9249 has a flexible clock input structure. The clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, clock source jitter is of the
utmost concern, as described in the Jitter Considerations section.
Figure 39 and Figure 40 show two preferred methods for clocking
the AD9249 (at clock rates of up to 520 MHz prior to the internal
clock divider). A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF transformer
or an RF balun.
0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD CURRENT (mA)
The RF balun configuration is recommended for clock frequencies
from 65 MHz to 520 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
antiparallel Schottky diodes across the transformer/balun
secondary winding limit clock excursions into the AD9249 to
approximately 0.8 V p-p differential.
Figure 37. VREF Error vs. Load Current
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 38 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9249 while
preserving the fast rise and fall times of the signal that are critical
to achieving a low jitter performance. However, the diode capaci-
tance comes into play at frequencies above 500 MHz. Take care
when choosing the appropriate signal limiting diode.
4
2
0
®
Mini-Circuits
–2
–4
–6
–8
ADT1-1WT, 1:1 Z
0.1µF
0.1µF
XFMR
CLOCK
INPUT
CLK+
100Ω
50Ω
ADC
0.1µF
CLK–
SCHOTTKY
DIODES:
HSMS2822
0.1µF
–40
–15
10
35
60
85
Figure 39. Transformer-Coupled Differential Clock (Up to 200 MHz)
TEMPERATURE (°C)
Figure 38. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 31). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, limit the external reference to a maximum of 1.0 V.
0.1µF
0.1µF
0.1µF
CLOCK
INPUT
CLK+
50Ω
ADC
0.1µF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 40. Balun-Coupled Differential Clock (65 MHz to 520 MHz)
Do not leave the SENSE pin floating.
Rev. 0 | Page 19 of 36
AD9249
Data Sheet
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 41. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515-x/AD9516-x/AD9517-x clock
drivers offer excellent jitter performance.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals and, as a result, may be sensitive to clock
duty cycle. Commonly, a 5% tolerance is required on the clock
duty cycle to maintain dynamic performance characteristics.
The AD9249 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the per-
formance of the AD9249. Noise and distortion performance are
nearly flat for a wide range of duty cycles with the DCS turned on.
0.1µF
0.1µF
CLOCK
CLK+
INPUT
AD951x
PECL DRIVER
100Ω
ADC
0.1µF
0.1µF
CLOCK
INPUT
CLK–
240Ω
240Ω
50kΩ
50kΩ
Jitter on the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates of less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 µs to 5 µs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
Figure 41. Differential PECL Sample Clock (Up to 520 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 42. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515-x/AD9516-x/
AD9517-x clock drivers offer excellent jitter performance.
0.1µF
0.1µF
CLOCK
INPUT
CLK+
Jitter Considerations
AD951x
LVDS DRIVER
100Ω
ADC
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) that is due only to aperture jitter (tJ) is expressed by
0.1µF
0.1µF
CLOCK
INPUT
CLK–
50kΩ
50kΩ
Figure 42. Differential LVDS Sample Clock (Up to 520 MHz)
1
SNR Degradation = 20 log
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 43).
10
2π × fA ×tJ
In this equation, the rms aperture jitter represents the root-sum-
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 44).
V
CC
130
RMS CLOCK JITTER REQUIREMENT
OPTIONAL
100Ω
0.1µF
1
0.1µF
1kΩ
1kΩ
AD951x
CMOS DRIVER
120
110
CLOCK
INPUT
CLK+
50Ω
ADC
16 BITS
100
90
80
70
60
50
40
30
CLK–
0.1µF
14 BITS
12 BITS
1
50Ω RESISTOR IS OPTIONAL.
Figure 43. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
10 BITS
8 BITS
Input Clock Divider
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
The AD9249 contains an input clock divider with the ability
to divide the input clock by integer values from 1 to 8.
The AD9249 clock divider can be synchronized using the
external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows the clock dividers of multiple
devices to be aligned to guarantee simultaneous input sampling.
1
10
100
1000
ANALOG INPUT FREQUENCY (MHz)
Figure 44. Ideal SNR vs. Input Frequency and Jitter
Rev. 0 | Page 20 of 36
Data Sheet
AD9249
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9249. Separate the
clock driver power supplies from the ADC output driver supplies
to avoid modulating the clock signal with digital noise. Low jitter,
crystal controlled oscillators are excellent clock sources. If
another type of source generates the clock (by gating, dividing, or
another method), ensure that it is retimed by the original clock
at the last step.
DIGITAL OUTPUTS AND TIMING
The AD9249 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via
the SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
See the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance, and the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter,
for more in depth information about jitter performance as it
relates to ADCs.
When operating in reduced range mode, the output current
reduces to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.
The AD9249 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as near to the receiver as possible. If there is no far end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is recom-
mended that the trace length be less than 24 inches, with all traces
the same length. Place the differential output traces as near to each
other as possible. An example of the FCO and data stream with
proper trace length and position is shown in Figure 46. Figure 47
shows an LVDS output timing example in reduced range mode.
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 45, the power dissipated by the AD9249 is
proportional to its sample rate and can be set to one of several
power saving modes using Register 0x100, Bits[2:0].
1.0
0.9
0.8
65MSPS
SETTING
50MSPS
SETTING
0.7
0.6
0.5
0.4
40MSPS
SETTING
20MSPS
SETTING
10
20
30
40
50
60
SAMPLE RATE (MSPS)
Figure 45. Total Power vs. fSAMPLE for fIN = 9.7 MHz
The AD9249 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 2 mW. During power-down, the output drivers
are placed in a high impedance state. Asserting the PDWN pin
low returns the AD9249 to its normal operating mode. Note
that PDWN is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
FCO 500mV/DIV
DCO 500mV/DIV
DATA 500mV/DIV
5ns/DIV
Figure 46. LVDS Output Timing Example in ANSI-644 Mode (Default)
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The internal capacitors are discharged when the device
enters power-down mode and then must be recharged when
returning to normal operation. As a result, wake-up time is
related to the time spent in power-down mode, and shorter
power-down cycles result in proportionally shorter wake-up
times. When using the SPI port interface, the user can place the
ADC in power-down mode or standby mode. Standby mode
allows the user to keep the internal reference circuitry powered
when faster wake-up times are required. See the Memory Map
section for more details on using these features.
FCO 500mV/DIV
DCO 500mV/DIV
DATA 500mV/DIV
5ns/DIV
Figure 47. LVDS Output Timing Example in Reduced Range Mode
Rev. 0 | Page 21 of 36
AD9249
Data Sheet
programming Register 0x15. Although this option produces
sharper rise and fall times on the data edges and is less prone to
bit errors, it also increases the power dissipation of the DRVDD
supply.
Figure 48 shows an example of the LVDS output using the
ANSI-644 standard (default) data eye and a time interval error
(TIE) jitter histogram with trace lengths of less than 24 inches
on standard FR-4 material.
400
300
EYE: ALL BITS
ULS: 7000:18200
EYE: ALL BITS
ULS: 7000:400354
300
200
200
100
100
0
0
–100
–200
–300
–400
–100
–200
–300
2.5k
2.0k
1.5k
1.0k
0.5k
0
2.5k
2.0k
1.5k
1.0k
0.5k
0
Figure 49. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of
Greater Than 24 Inches on Standard FR-4 Material, External 100 Ω Far End
Termination Only
Figure 48. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches on Standard FR-4 Material, External 100 Ω Far End
Termination Only
The default format of the output data is twos complement. Table 10
shows an example of the output coding format. To change the
output data format to offset binary, see the Memory Map section.
Figure 49 shows an example of trace lengths exceeding 24 inches
on standard FR-4 material. Note that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position.
Data from each ADC is serialized and provided on a separate
channel in DDR mode. The data rate for each serial stream is equal
to 14 bits times the sample clock rate, quantity divided by 2,
with a maximum of 455 Mbps (14 bits × 65 MSPS)/2 = 455 Mbps.
The lowest typical conversion rate is 10 MSPS. See the Memory
Map section for details on enabling this feature.
It is the responsibility of the user to determine if the waveforms
meet the timing budget of the design when the trace lengths
exceed 24 inches. Additional SPI options allow the user to further
increase the internal termination (increasing the current) of all 16
outputs to drive longer trace lengths, which can be achieved by
Table 10. Digital Output Coding
Input (V)
Condition (V)
< −VREF − 0.5 LSB
= −VREF
Offset Binary Output Mode
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
= 0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Rev. 0 | Page 22 of 36
Data Sheet
AD9249
Two output clock types are provided to assist in capturing data
from the AD9249. DCO 1 and DCO 2 clock the output data,
and their frequency is equal to 7× the sample clock (CLK ) rate
for the default mode of operation. Data is clocked out of the
AD9249 and must be captured on the rising and falling edges of
the DCO that supports double data rate (DDR) capturing. DCO 1
is used to capture the D x1 (Bank 1) data; DCO 2 is used to
capture the D x2 (Bank 2) data. FCO 1 and FCO 2 signal the
start of a new output byte, and the frequency is equal to the sample
clock rate. FCO 1 frames the D x1 (Bank 1) data; FCO 2
frames the D x2 (Bank 2) data (see Figure 3 and Figure 4).
A 12-bit serial stream can also be initiated from the SPI. This
allows the user to implement and test compatibility to lower
resolution systems. When changing the resolution to a 12-bit
serial stream, the data stream is shortened. See Figure 4 for the
12-bit example.
In default mode, as shown in Figure 3, the MSB is first in the
data output serial stream. This can be inverted so that the LSB is
first in the data output serial stream by using the SPI.
There are 12 digital output test pattern options available that can
be initiated through the SPI. This is a useful feature when validating
receiver capture and timing (see Table 11 for the output bit
sequencing options that are available). Some test patterns have
two serial sequential words and can alternate in various ways,
depending on the test pattern chosen. Note that some patterns
do not adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in Register 0x19,
Register 0x1A, Register 0x1B, and Register 0x1C.
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to one data cycle (30° relative to one DCO
cycle). This enables the user to refine system timing margins, if
required. The default DCO 1 and DCO 2 to output data edge
timing, as shown in Figure 3, is 180° relative to one data cycle
(90° relative to one DCO cycle).
Table 11. Flexible Output Test Modes
Output Test
Mode Bit
Sequence
Subject
to Data
Format
(Reg. 0x0D)
Pattern Name
Off (default)
Midscale short
Digital Output Word 11
N/A
Digital Output Word 21
Select1
N/A
Notes
0000
0001
N/A
N/A
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
Yes
Offset binary code shown
Offset binary code shown
Offset binary code shown
0010
0011
0100
0101
+Full-scale short
−Full-scale short
Checkerboard
N/A
N/A
Yes
Yes
No
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)
N/A
PN sequence long2 N/A
Yes
PN23
ITU 0.150
X23 + X18 + 1
PN9
ITU 0.150
X9 + X5 + 1
0110
0111
PN sequence short2 N/A
N/A
Yes
No
One-/zero-word
toggle
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
1000
1001
User input
1-/0-bit toggle
Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C
No
No
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
1000 0000 0000 (12-bit)
N/A
N/A
N/A
1010
1011
1× sync
No
No
One bit high
Pattern associated with
the external pin
10 0000 0000 0000 (14-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
1100
Mixed frequency
N/A
No
1 N/A means not applicable.
2 All test mode options except PN sequence short and PN sequence long can support 12-bit to 14-bit word lengths to verify data capture to the receiver.
Rev. 0 | Page 23 of 36
AD9249
Data Sheet
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 or 511 bits. Refer to
Section 5.1 of the ITU-T 0.150 (05/96) standard for a description
of the PN sequence and how it is generated. The seed value is all
1s (see Table 12 for the initial values). The output is a parallel
representation of the serial PN9 sequence in MSB-first format.
The first output word is the first 14 bits of the PN9 sequence in
MSB aligned form.
SCLK/DTP Pin
The SCLK/DTP pin can enable a single digital test pattern if it
and the CSB1 and CSB2 pins are held high during device power-
up. When SCLK/DTP is tied to AVDD, the ADC channel outputs
shift out the following pattern: 10 0000 0000 0000. The FCO 1,
FCO 2, DCO 1, and DCO 2 pins function normally while all
channels shift out the repeatable test pattern. This pattern allows
the user to perform timing alignment adjustments among the
FCO 1, FCO 2, DCO 1, DCO 2, and output data. The SCLK/
DTP pin has an internal 30 kΩ resistor to GND. It can be left
unconnected for normal operation.
Table 12. PN Sequence
Initial
Value
Next Three Output Samples
(MSB First) Twos Complement
Sequence
PN Sequence Short 0x1FE0
PN Sequence Long 0x1FFF
0x1DF1, 0x3CC8, 0x294E
0x1FE0, 0x2001, 0x1C00
Table 14. Digital Test Pattern Pin Settings
Selected DTP
Normal Operation
DTP
DTP Voltage
No connect
AVDD
Resulting D xx
Normal operation
10 0000 0000 0000
The PN sequence long pattern produces a pseudorandom
bit sequence that repeats itself every 223 − 1 or 8,388,607 bits.
Refer to Section 5.6 of the ITU-T 0.150 (05/96) standard for a
description of the PN sequence and how it is generated. The
seed value is all 1s (see Table 12 for the initial values) and the
AD9249 inverts the bit stream with relation to the ITU standard.
The output is a parallel representation of the serial PN23 sequence
in MSB-first format. The first output word is the first 14 bits of the
PN23 sequence in MSB aligned format.
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map section
for information about the options that are available.
CSB1 and CSB2 Pins
The CSB1 and CSB2 pins are tied to AVDD for applications that
do not require SPI mode operation. Tying CSB1 and CSB2 high
causes all SCLK and SDIO SPI communication information to be
ignored.
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
CSB1 selects/deselects SPI circuitry affecting outputs D A1 to
D H1 (Bank 1). CSB2 selects/deselects SPI circuitry affecting
outputs D A2 to D H2 (Bank 2).
SDIO/DFS Pin
For applications that do not require SPI mode operation, the CSB1
and CSB2 pins are tied to AVDD, and the SDIO/DFS pin controls
the output data format select as described in Table 13.
It is recommended that CSB1 and CSB2 be controlled with the
same signal; that is, tie them together. In this way, whether tying
them to AVDD or selecting SPI functionality, both banks of ADCs
are controlled identically and are always in the same state.
Table 13. Output Data Format Select Pin Settings
DFS Pin Voltage
Output Mode
Twos complement
Offset binary
RBIAS1 and RBIAS2 Pins
AVDD
GND (Default)
To set the internal core bias current of the ADC, place a 10.0 kΩ,
1% tolerance resistor to ground at each of the RBIAS1 and
RBIAS2 pins.
Rev. 0 | Page 24 of 36
Data Sheet
AD9249
BUILT-IN OUTPUT TEST MODES
from the digital back-end blocks and the test pattern is run
The AD9249 includes a built-in test feature designed to enable
verification of the integrity of each data output channel, as well
as to facilitate board level debugging. Various output test modes
are provided to place predictable values on the outputs of the
AD9249.
through the output formatting block. Some of the test patterns
are subject to output formatting, and some are not. The PN
generators from the PN sequence tests can be reset by setting
Bit 4 or Bit 5 of Register 0x0D. These tests can be performed
with or without an analog signal (if present, the analog signal is
ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
OUTPUT TEST MODES
The output test modes are described in Table 11 and controlled by
the output test mode bits at Address 0x0D. When an output test
mode is enabled, the analog section of the ADC is disconnected
Rev. 0 | Page 25 of 36
AD9249
Data Sheet
SERIAL PORT INTERFACE (SPI)
Other modes involving the CSB1 and CSB2 pins are available.
To permanently enable the device, hold CSB1 and CSB2 low
indefinitely; this is called streaming. CSB1 and CSB2 can stall
high between bytes to allow additional external timing. Tie CSB1
and CSB2 high to place SPI functions in high impedance mode.
This mode turns on any SPI secondary pin functions.
The AD9249 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
offers the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are docu-
mented in the Memory Map section. For general operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI. SPI information specific to the AD9249
is found in the AD9249 datasheet and takes precedence over the
general information found in the AN-877 Application Note.
It is recommended that CSB1 and CSB2 be controlled with the
same signal by tying them together. In this way, whether tying
them to AVDD or selecting SPI functionality, both banks of ADCs
are controlled identically and are always in the same state.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
CONFIGURATION USING THE SPI
Four pins define the SPI of this ADC: the SCLK/DTP pin
(SCLK functionality), the SDIO/DFS pin(SDIO functionality),
and the CSB1 and CSB2 pins (see Table 15). SCLK (a serial
clock) is used to synchronize the read and write data presented
from and to the ADC. SDIO (serial data input/output) serves a
dual function that allows data to be sent to and read from the
internal ADC memory map registers. CSB1 and CSB2 (chip
select bar) are active low controls that enable or disable the read
and write cycles.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to both program the chip and read the contents
of the on-chip memory. The first bit of the first byte in a multibyte
serial data transfer frame indicates whether a read command or a
write command is issued. If the instruction is a readback operation,
performing a readback causes the serial data input/output (SDIO)
pin to change direction from an input to an output at the
appropriate point in the serial frame.
Input data registers on the rising edge of SCLK, and output data
transmits on the falling edge. After the address information passes
to the converter requesting a read, the SDIO line transitions from
an input to an output within 1/2 of a clock cycle. This timing
ensures that when the falling edge of the next clock cycle
occurs, data can be safely placed on this serial line for the
controller to read.
Table 15. Serial Port Interface Pins
Pin
Function
SCLK
Serial clock. The serial shift clock input, which is
(SCLK/DTP) used to synchronize serial interface reads and
writes.
SDIO
Serial data input/output. A dual-purpose pin that
(SDIO/DFS) serves as an input or an output, depending on the
instruction being sent and the relative position in
the timing frame.
All data is composed of 8-bit words. Data can be sent in MSB
first mode or in LSB-first mode. MSB-first mode is the default
on power-up and can be changed via the SPI port configuration
register. For more information about this and other features,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
CSB1,
CSB2
Chip select bar. An active low control that gates
the read and write cycles. CSB1 enables/disables
SPI for eight channels in Bank 1; CSB2 enables/
disables SPI for eight channels in Bank 2.
The falling edge of CSB1 and/or CSB2, in conjunction with the
rising edge of SCLK, determines the start of the framing. For an
example of the serial timing and its definitions, see Figure 50
and Table 5.
tHIGH
tLOW
tCLK
tH
tDS
tS
tDH
CSB1,
CSB2
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 50. Serial Port Interface Timing Diagram
Rev. 0 | Page 26 of 36
Data Sheet
AD9249
pins as static control lines for the output data format, output
HARDWARE INTERFACE
digital test pattern, and power-down feature control. In this
mode, connect CSB1 and CSB2 to AVDD, which disables the
serial port interface.
The pins described in Table 15 comprise the physical interface
between the user programming device and the serial port of the
AD9249. The SCLK/DTP pin (SCLK functionality) and the CSB1
and CSB2 pins function as inputs when using the SPI interface.
The SDIO/DFS pin (SDIO functionality) is bidirectional,
functioning as an input during write phases and as an output
during readback.
When the device is in SPI mode, the PDWN pin (if enabled)
remains active. For SPI control of power-down, set the PDWN pin
to its inactive state (low).
SPI ACCESSIBLE FEATURES
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described further in
the AN-877 Application Note, Interfacing to High Speed ADCs via
SPI. The AD9249 device-specific features are described in detail
in the Memory Map Register Descriptions section following
Table 17, the external memory map register table.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB1 and CSB2 signals, and the SDIO signal
are typically asynchronous to the ADC clock, noise from these
signals can degrade converter performance. If the on-board SPI
bus is used for other devices, it may be necessary to provide
buffers between this bus and the AD9249 to prevent these
signals from transitioning at the converter inputs during critical
sampling periods.
Table 16. Features Accessible Using the SPI
Feature Name
Description
Power Mode
Allows the user to set either power-down mode
or standby mode
Clock
Allows the user to access the DCS, set the clock
divider, set the clock divider phase, and enable
the sync function
Offset
Allows the user to digitally adjust the converter
offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the output mode
Allows the user to set the output clock polarity
Allows scalable power consumption options
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to DRVDD or ground
during device power-on, they are associated with a specific
function. Table 13 and Table 14 describe the strappable
functions supported on the AD9249.
Test I/O
Output Mode
Output Phase
ADC Resolution
CONFIGURATION WITHOUT THE SPI
and Speed Grade based on resolution and speed grade selection
In applications that do not interface to the SPI control registers,
the SDIO/DFS pin, the SCLK/DTP pin, and the PDWN pin
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use the
Rev. 0 | Page 27 of 36
AD9249
Data Sheet
MEMORY MAP
Default Values
READING THE MEMORY MAP REGISTER TABLE
After the AD9249 is reset (via Bit 5 and Bit 2 of Address 0x00),
the registers are loaded with default values. The default values
for the registers are listed in the Default Value (Hex) column
of Table 17, the memory map register table.
Each row in the memory map register table has eight bit locations.
The memory map is divided into three sections: the chip con-
figuration registers (Address 0x00 to Address 0x02); the device
index and transfer registers (Address 0x04, Address 0x05, and
Address 0xFF); and the global ADC function registers, including
setup, control, and test (Address 0x08 to Address 0x109).
Logic Levels
An explanation of logic level terminology follows:
The memory map register table (see Table 17) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the Bit 7 (MSB) heading is the MSB of the binary
8-bit representation. For example, Address 0x05, the Device
Index 1 register, has a hexadecimal default value of 0x3F. This
means that in Address 0x05, Bits[7:6] = 0, and the remaining
bits, Bits[5:0], = 1. This setting is the default channel index
setting. The default value results in all specified ADC channels
receiving the next write command. For more information on
this function and others, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI. This application note
details the functions controlled by Register 0x00 to Register 0xFF.
The remaining registers are documented in the Memory Map
Register Descriptions section.
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
•
Channel Specific Registers
Some channel setup functions can be programmed independently
for each channel. In such cases, channel address locations are
internally duplicated for each channel; that is, each channel has
its own set of registers. These registers and bits are designated in
Table 17 as local. Access these local registers and bits by setting
the appropriate data channel bits (A1, A2 through H1, H2) and
the clock channel bits (DCO 1, DCO 2 and FCO 1, FCO 2),
found in Register 0x04 and Register 0x05. If all the valid bits are
set in Register 0x04 and Register 0x05, the subsequent write to a
local register affects the registers of all the data channels and the
DCO x/FCO x clock channels. In a read cycle, set only one
channel (A1, A2 through H1, H2) to read one local register. If all
the bits are set during a SPI read cycle, the device returns the
value for Channel A1.
Open Locations
All address and bit locations that are not listed in Table 17 are
not currently supported for this device. Write the unused bits of
a valid address location with 0s. Writing to these locations is
required only when some of the bits of an address location are
valid (for example, Address 0x05). Do not write to an address
location if the entire address location is open or if the address is
not listed in Table 17 (for example, Address 0x13).
Registers and bits that are designated as global in Table 17 are
applicable to the channel features for which independent settings
are not allowed; thus, they affect the entire device. The settings
in Register 0x04 and Register 0x05 do not affect the global
registers and bits.
Rev. 0 | Page 28 of 36
Data Sheet
AD9249
MEMORY MAP
The AD9249 uses a 3-wire (bidirectional SDIO) interface and 16-bit addressing. Therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0,
and Bit 3 and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high, the SPI enters a soft reset where all of the user registers revert to
their default values and Bit 2 is automatically cleared.
Table 17. Memory Map Register Table
Reg.
Addr.
(Hex)
Default
Value
(Hex)
Bit 7
(MSB)
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0 = SDIO
active
LSB first
Soft reset 1 =
16-bit
address
1 =
16-bit
address
Soft reset
LSB first
0 = SDIO
active
0x18
Nibbles are
mirrored such
that a given
register value
yields the same
function for
either LSB first
mode or MSB
first mode.
0x01
0x02
Chip ID (global)
8-bit chip ID, Bits[7:0];
0x92 = the AD9249, a 16-channel, 14-bit, 65 MSPS serial LVDS
Read
only;
0x92
Unique chip ID
used to differ-
entiate devices.
Read only.
Chip grade
(global)
Open
Speed grade ID, Bits[6:4];
011 = 65 MSPS
Open
Open
Open
Open
Read
only
Unique speed
grade ID used
to differentiate
graded devices.
Read only.
Device Index and Transfer Registers
Open
0x04
0x05
0xFF
Device Index 2
Device Index 1
Transfer
Open
Open
Open
H1, H2
data
channels
G1, G2
data
channels
F1, F2
data
channels
E1, E2
data
channels
0x0F
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
Open
Open
DCO 1,
DCO 2
clock
FCO 1,
FCO 2
clock
D1, D2
data
channels
C1, C2
data
channels
B1, B2
data
channels
A1, A2
data
channels
0x3F
Bits are set
to determine
which device
on chip
receives the
next write
command.
The default
is all devices
on chip.
channels
channels
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Initiate
override
0x00
0x00
Sets resolution/
sample rate
override.
Global ADC Function Registers
0x08
Power modes
(global)
External
power-
down pin
function;
0 = full
power-
down,
Internal power-down
mode, Bits[1:0];
00 = chip run
01 = full power-down
10 = standby
Determines
various
generic modes
of chip
operation.
11 = digital reset
1 =
standby
0x09
Clock (global)
Open
Open
Open
Open
Open
Open
Open
Duty cycle
stabilizer;
0 = off
0x01
Turns duty
cycle stabilizer
on or off.
1 = on
Rev. 0 | Page 29 of 36
AD9249
Data Sheet
Reg.
Addr.
(Hex)
Default
Value
(Hex)
Bit 7
(MSB)
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Comments
0x0B
Clock divide
(global)
Open
Open
Open
Open
Open
Clock divide ratio, Bits[2:0];
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
Divide ratio
is the value
plus 1.
0x0C
0x0D
Enhancement
control
Open
Open
Open
Open
Open
Chop
Open
Open
0x00
0x00
Enables/
disables chop
mode.
mode;
0 = off
1 = on
Test mode (local
except for PN
sequence resets)
User input test mode,
Bits[7:6];
Reset PN
long gen
Reset
PN
short
Output test mode, Bits[3:0] (local);
0000 = off (default)
When set, test
data is placed
on the output
pins in place
of normal
00 = single
0001 = midscale short
0010 = positive FS
0011 = negative FS
gen
01 = alternate
10 = single once
11 = alternate once
(affects user input test
mode only;
Register 0x0D,
Bits[3:0] = 1000)
data.
0100 = alternating checkerboard
0101 = PN23 sequence
0110 = PN9 sequence
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
0x10
0x14
Offset adjust (local)
Output mode
8-bit device offset adjustment, Bits[7:0] (local);
offset adjust in LSBs from +127 to −128 (twos complement format)
0x00
0x01
Device offset
trim.
Open
LVDS-ANSI/
LVDS-IEEE
option;
0 = LVDS-
ANSI
Open
Open
Open
Output
invert;
0 = not
inverted
1 =
Open
Output
format;
0 = offset
binary
1 = twos
comple-
ment
Configures
outputs and
format of the
data.
1 = LVDS-
IEEE reduced
range link
(global);
inverted
(local)
(default)
(global)
see Table 18
0x15
0x16
Output adjust
Output phase
Open
Open
Open
Output driver
termination,
Bits[5:4];
00 = none
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
Open
Open
Open
FCO x,
DCO x
output
drive (local);
0 = 1× drive
1 = 2× drive
0x00
0x03
Determines
LVDS or
other output
properties.
Input clock phase adjust, Bits[6:4];
(value is number of input clock cycles
of phase delay; see Table 19)
Output clock phase adjust, Bits[3:0];
(setting = 0000 to 1011; see Table 20)
On devices
that use global
clock divide,
determines
which phase
of the divider
output
supplies the
output clock.
Internal
latching is
unaffected.
0x18
VREF
Open
Open
Open
Open
Open
Input full-scale adjustment;
digital scheme, Bits[2:0];
000 = 1.0 V p-p
0x04
Digital adjust-
ment of input
full-scale
voltage. Does
not affect
analog voltage
reference
001 = 1.14 V p-p
010 = 1.33 V p-p
011 = 1.6 V p-p
100 = 2.0 V p-p
Rev. 0 | Page 30 of 36
Data Sheet
AD9249
Reg.
Addr.
(Hex)
Default
Value
(Hex)
Bit 7
(MSB)
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Comments
0x19
USER_PATT1_LSB
(global)
B7
B6
B5
B4
B3
B2
B1
B0
0x00
0x00
0x00
0x00
0x41
User Defined
Pattern 1 LSB.
0x1A
0x1B
0x1C
0x21
USER_PATT1_MSB B15
(global)
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B9
B1
B9
B8
B0
B8
User Defined
Pattern 1 MSB.
USER_PATT2_LSB
(global)
B7
User Defined
Pattern 2 LSB.
USER_PATT2_MSB B15
(global)
B14
B13
B12
B11
B10
Open
User Defined
Pattern 2 MSB.
Serial output data
control (global)
LVDS
output
LSB first
Wordwise DDR, one lane, Bits[6:4];
100 = DDR, one lane
PLL low
encode
rate
Serial output number
of bits, Bits[1:0];
01 = 14 bits
Serial stream
control.
Default causes
MSB first and
the native bit
stream.
mode
10 = 12 bits
0x22
Serial channel
status (local)
Open
Open
Open
Open
Open
Open
Open
Open
Channel
output
reset
Channel
power-
down
0x00
0x00
Powers down
individual
sections of
a converter.
0x100
Resolution/
sample rate
override
Resolution/
sample rate
override
Resolution, Bits[5:4];
01 = 14 bits
Sample rate, Bits[2:0];
000 = 20 MSPS
001 = 40 MSPS
010 = 50 MSPS
011 = 65 MSPS
Resolution/
sample rate
override
(requires
transfer
10 = 12 bits
enable
register,
Register 0xFF).
0x101
0x102
User I/O Control 2
User I/O Control 3
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
SDIO pull-
down
0x00
0x00
Disables SDIO
pull-down.
VCM
power-
down
Open
VCM control.
0x109
Sync
Open
Open
Open
Open
Open
Open
Sync
next
only
Enable sync 0x00
Rev. 0 | Page 31 of 36
AD9249
Data Sheet
Output Mode (Register 0x14)
Bit 7—Open
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Bit 6—LVDS-ANSI/LVDS-IEEE Option
Setting Bit 6 = 1 chooses the LVDS-IEEE (reduced range)
option. (The default setting is LVDS-ANSI.) As described in
Table 18, when either LVDS-ANSI mode or the LVDS-IEEE
reduced range link is selected, the user can select the driver
termination resistor in Register 0x15, Bits[5:4]. The driver
current is automatically selected to give the proper output swing.
Device Index (Register 0x04 and Register 0x05)
There are certain features in the map that can be set independently
for each channel, whereas other features apply globally to all
channels (depending on context), regardless of which are selected.
Bits[3:0] in Register 0x04 and Register 0x05 select which individual
data channels are affected. The output clock channels are selected
in Register 0x05, as well. A smaller subset of the independent
feature list can be applied to those devices.
Table 18. LVDS-ANSI/LVDS-IEEE Options
LVDS-ANSI/
LVDS-IEEE
Option, Bit 6 Mode
Output
Output Driver Output Driver
Termination Current
Transfer (Register 0xFF)
0
1
LVDS-ANSI
User selectable Automatically
selected to give
proper swing
User selectable Automatically
selected to give
All registers except Register 0x100 are updated the moment
they are written. Setting Bit 0 = 1 in the transfer register initializes
the settings in the ADC resolution/sample rate override register
(Address 0x100).
LVDS-IEEE
reduced
range link
proper swing
Power Modes (Register 0x08)
Bits[7:6]—Open
Bits[5:3]—Open
Bit 5—External Power-Down Pin Function
Bit 2—Output Invert
When set (Bit 5 = 1), the external PDWN pin initiates standby
mode. When cleared (Bit 5 = 0), the external PDWN pin
initiates full power-down mode.
Setting Bit 2 = 1 inverts the output bit stream.
Bit 1—Open
Bit 0—Output Format
Bits[4:2]—Open
By default, setting Bit 0 = 1 sends the data output in twos
complement format. Clearing this bit (Bit 0 = 0) changes the
output mode to offset binary.
Bits[1:0]—Internal Power-Down Mode
In normal operation (Bits[1:0] = 00), all ADC channels are active.
In full power-down mode (Bits[1:0] = 01), the digital datapath
clocks are disabled and the digital datapath is reset. Outputs are
disabled.
Output Adjust (Register 0x15)
Bits[7:6]—Open
Bits[5:4]—Output Driver Termination
In standby mode (Bits[1:0] = 10), the digital datapath clocks
and the outputs are disabled.
These bits allow the user to select the internal output driver
termination resistor.
During a digital reset (Bits[1:0] = 11), all the digital datapath clocks
and the outputs (where applicable) on the chip are reset, except
the SPI port. Note that the SPI is always left under control of the
user; that is, it is never automatically disabled or in reset (except
by power-on reset).
Bits[3:1]—Open
Bit 0—FCO x, DCO x Output Drive
Bit 0 of the output adjust register controls the drive strength on
the LVDS driver of the FCO 1, FCO 2, DCO 1, and DCO 2
outputs only. The default value (Bit 0 = 0) sets the drive to 1×.
Increase the drive to 2× by setting the appropriate channel bit in
Register 0x05 and then setting Bit 0 = 1. These features cannot be
used with the output driver termination selected. The termination
selection takes precedence over the 2× driver strength on FCO 1,
FCO 2, DCO 1, and DCO 2 when both the output driver
termination and output drive are selected.
Enhancement Control (Register 0x0C)
Bits[7:3]—Open
Bit 2—Chop Mode
For applications that are sensitive to offset voltages and other
low frequency noise, such as homodyne or direct conversion
receivers, chopping in the first stage of the AD9249 is a feature
that can be enabled by setting Bit 2 = 1. In the frequency domain,
chopping translates offsets and other low frequency noise to
fCLK/2, where they can be filtered.
Bits[1:0]—Open
Rev. 0 | Page 32 of 36
Data Sheet
AD9249
Output Phase (Register 0x16)
Bit 7—Open
Resolution/Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the device
(that is, establish lower power) for applications that do not require
full sample rate. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is set to 1.
Bits[6:4]—Input Clock Phase Adjust
When the clock divider (Register 0x0B) is used, the applied
clock is at a higher frequency than the internal sampling clock.
Bits[6:4] determine at which phase of the external clock the
sampling occurs. This is applicable only when the clock divider
is used. It is prohibited to select a value for Bits[6:4] that is
greater than the value of Bits[2:0], Register 0x0B. See Table 19
for more information.
This function does not affect the sample rate; it affects the
maximum sample rate capability of the ADC, as well as the
resolution.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Table 19. Input Clock Phase Adjust Options
Bit 0—SDIO Pull-Down
Input Clock Phase
Adjust, Bits[6:4]
Number of Input Clock Cycles
of Phase Delay
Set Bit 0 = 1 to disable the internal 30 kΩ pull-down on the
SDIO/DFS pin. This feature limits loading when many devices
are connected to the SPI bus.
000 (Default)
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Set Bit 3 = 1 to power down the internal VCM generator. This
feature is used when applying an external reference.
Bits[2:0]—Open
Bits[3:0]—Output Clock Phase Adjust
See Table 20 for more information.
Table 20. Output Clock Phase Adjust Options
Output Clock, Phase
Adjust, Bits[3:0]
DCO Phase Adjustment
(Degrees Relative to D x Edge)
0000
0
0001
60
0010
0011 (Default)
0100
0101
0110
0111
1000
1001
1010
120
180
240
300
360
420
480
540
600
660
1011
Rev. 0 | Page 33 of 36
AD9249
Data Sheet
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Crosstalk Between Inputs
To avoid crosstalk between inputs, consider the following
guidelines:
Before starting the design and layout of the AD9249 as a system,
it is recommended that the designer become familiar with these
guidelines, which describe the special circuit connections and
layout requirements that are needed for certain pins.
•
•
•
•
•
•
When routing inputs, sequentially alternate input channels
on the top and bottom (or other layer) of the board.
Ensure that the top channels have no vias within 5 mm of
any other input channel via.
For bottom channels, use a via-in-pad to minimize top
metal coupling between channels.
Avoid running input traces parallel with each other that are
nearer than 2 mm apart.
When possible, lay out traces orthogonal to each other and
to any other traces that are not dc.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9249, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, use several different
decoupling capacitors for both high and low frequencies. Place
these capacitors near the point of entry at the PCB level and
near the pins of the device, with minimal trace length.
Secondhand or indirect coupling may occur through non-
related dc traces that bridge the distance between two traces
or vias.
A single PCB ground plane is typically sufficient when using the
AD9249. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
Coupling of Digital Output Switching Noise to Analog
Inputs and Clock
BOARD LAYOUT CONSIDERATIONS
To avoid the coupling of digital output switching noise to the
analog inputs and the clock, use the following guidelines:
For optimal performance, give special consideration to the AD9249
board layout. The high channel count and small footprint of the
AD9249 create a dense configuration that must be managed for
matters relating to crosstalk and switching noise.
•
Vias on the outputs are a main conduit of noise to the vias
on the inputs. Maintain 5 mm of separation between any
output via and any input via.
Sources of Coupling
•
Place the encode clock traces on the top surface. Vias are
not recommended in the clock traces. However, if they are
required, ensure that there are no clock trace vias within
5 mm of any input via or output via.
Trace pairs interfere with each other by inductive coupling and
capacitive coupling. Use the following guidelines:
•
•
Inductive coupling is current induced in a trace by a
changing magnetic field from an adjacent trace, caused by
its changing current flow. Mitigate this effect by making
traces orthogonal to each other whenever possible and by
increasing the distance between them.
Capacitive coupling is charge induced in a trace by the
changing electric field of an adjacent trace. Mitigate this
effect by minimizing facing areas, increasing the distance
between traces, or changing dielectric properties.
Through-vias are particularly good conduits for both types
of coupling and must be used carefully.
Adjacent trace runs on the same layer may cause unbalanced
coupling between channels.
Traces on one layer should be separated by a plane (ac ground)
from the traces on another layer. Significant coupling occurs
through gaps in that plane, such as the setback around
through-vias.
•
Place output surface traces (not imbedded between planes)
orthogonal to one another as much as possible. Avoid parallel
output to input traces within 2 mm.
•
•
Route digital output traces away from the analog input side
of the board.
Coupling among outputs is not a critical issue, but separation
between these high speed output pairs increases the noise
margin of the signals and is good practice.
•
•
•
Rev. 0 | Page 34 of 36
Data Sheet
AD9249
CLOCK STABILITY CONSIDERATIONS
VCM
When powered on, the AD9249 enters an initialization phase
where an internal state machine sets up the biases and the registers
for proper operation. During the initialization process, the AD9249
needs a stable clock. If the ADC clock source is not present or not
stable during ADC power-up, the state machine is disrupted and
the ADC starts up in an unknown state. To correct this, reinvoke an
initialization sequence after the ADC clock is stable by issuing
a digital reset using Register 0x08. In the default configuration
(internal VREF, ac-coupled input) where VREF and VCM are supplied
by the ADC itself, a stable clock during power-up is sufficient.
When VREF or VCM is supplied by an external source, it, too, must
be stable at power-up. Otherwise, a subsequent digital reset, using
Register 0x08, is needed. The pseudocode sequence for a digital
reset follows:
Decouple the VCMx pin to ground with a 0.1 μF capacitor.
REFERENCE DECOUPLING
Decouple the VREF pin externally to ground with a low ESR,
1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic
capacitor.
SPI PORT
Ensure that the SPI port is inactive during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB1, CSB2, and SDIO signals are typically asynchronous
to the ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9249 to prevent these signals from transitioning at the converter
inputs during critical sampling periods.
SPI_Write (0x08, 0x03); # digital reset
SPI_Write (0x08, 0x00); # normal operation
Rev. 0 | Page 35 of 36
AD9249
Data Sheet
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
A1 BALL
CORNER
A1 BALL
CORNER
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
8.80 SQ
G
H
J
0.80
K
L
M
0.60
REF
TOP VIEW
DETAIL A
BOTTOM VIEW
1.70 MAX
1.00 MIN
DETAIL A
0.32 MIN
0.50
0.45
0.40
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1.
Figure 51. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
BC-144-7
BC-144-7
AD9249BBCZ-65
AD9249BBCZRL7-65
AD9249-65EBZ
−40°C to +85°C
−40°C to +85°C
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
1 Z = RoHS Compliant Part.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11536-0-10/13(0)
Rev. 0 | Page 36 of 36
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