AD9260ASZRL [ADI]
16-Bit High Speed Oversampled A/D Converter;
| 型号： | AD9260ASZRL |
| 厂家： | 
ADI |
| 描述： | 16-Bit High Speed Oversampled A/D Converter |
| 文件： | 总36页 (文件大小：569K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-Speed Oversampling CMOS
ADC with 16-Bit Resolution
a
at a 2.5 MHz Output Word Rate
AD9260
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Monolithic 16-Bit, Oversampled A/D Converter
8ꢀ Oversampling Mode, 20 MSPS Clock
2.5 MHz Output Word Rate
RESET/
SYNC
DVSS DVDD
1.01 MHz Signal Passband w/0.004 dB Ripple
Signal-to-Noise Ratio: 88.5 dB
Total Harmonic Distortion: –96 dB
Spurious Free Dynamic Range: 100 dB
Input Referred Noise: 0.6 LSB
Selectable Oversampling Ratio: 1ꢀ, 2ꢀ, 4ꢀ, 8ꢀ
Selectable Power Dissipation: 150 mW to 585 mW
85 dB Stopband Attenuation
VINA
VINB
DIGITAL
OTR
MULTIBIT
SIGMA-DELTA
MODULATOR
DEMODULATOR
12-BIT: 20MHz
16-BIT: 10MHz
STAGE 1:2X
DECIMATION
FILTER
AD9260
BIT1–BIT16
0.004 dB Passband Ripple
Linear Phase
STAGE 2:2X
16-BIT: 5MHz DECIMATION
FILTER
REF TOP
Single +5 V Analog Supply, +5 V/+3 V Digital Supply
Synchronize Capability for Parallel ADC Interface
Twos-Complement Output Data
44-Lead MQFP
REF
REFERENCE
BUFFER
BOTTOM
COMMON
MODE
STAGE 3:2X
DECIMATION
FILTER
16-BIT: 2.5MHz
VREF
SENSE
DAV
BANDGAP
REFERENCE
CLOCK
BUFFER
BIAS
CIRCUIT
MODE
REGISTER
READ
REFCOM
BIAS ADJUST
CLK
MODE
CS
The AD9260 operates on a single +5 V supply, typically con-
suming 585 mW of power. A power scaling circuit is provided
allowing the AD9260 to operate at power consumption levels as
low as 150 mW at reduced clock and data rates. The AD9260 is
available in a 44-lead MQFP package and is specified to operate
over the industrial temperature range.
PRODUCT DESCRIPTION
The AD9260 is a 16-bit, high-speed oversampled analog-to-
digital converter (ADC) that offers exceptional dynamic range
over a wide bandwidth. The AD9260 is manufactured on an
advanced CMOS process. High dynamic range is achieved with
an oversampling ratio of 8× through the use of a proprietary
technique that combines the advantages of sigma-delta and
pipeline converter technologies.
PRODUCT HIGHLIGHTS
The AD9260 is fabricated on a very cost effective CMOS
process. High-speed, precision mixed-signal analog circuits are
combined with high-density digital filter circuits.
The AD9260 is a switched-capacitor ADC with a nominal full-
scale input range of 4 V. It offers a differential input with 60 dB
of common-mode rejection of common-mode signals. The sig-
nal range of each differential input is 1 V centered on a 2.0 V
common-mode level.
The AD9260 offers a complete single-chip 16-bit sampling
ADC with a 2.5 MHz output data rate in a 44-lead MQFP.
Selectable Internal Decimation Filtering—The AD9260
provides a high-performance decimation filter with 0.004 dB
passband ripple and 85 dB of stopband attenuation. The filter
is configurable with options for 1×, 2×, 4×, and 8× decimation.
The on-chip decimation filter is configured for maximum per-
formance and flexibility. A series of three half-band FIR filter
stages provide 8× decimation filtering with 85 dB of stopband
attenuation and 0.004 dB of passband ripple. An onboard digi-
tal multiplexer allows the user to access data from the various
stages of the decimation filter.
Power Scaling—The AD9260 consumes a low 585 mW of power
at 16-bit resolution and 2.5 MHz output data rate. Its power
can be scaled down to as low as 150 mW at reduced clock rates.
The on-chip programmable reference and reference buffer am-
plifier are configured for maximum accuracy and flexibility. An
external reference can also be chosen to suit the user’s specific
dc accuracy and drift requirements.
Single Supply— Both of the analog and digital portions of the
AD9260 can operate off of a single +5 V supply simplifying
system power supply design. The digital logic will also accom-
modate a single +3 V supply for reduced power.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD9260–SPECIFICATIONS
CLOCK INPUT FREQUENCY RANGE
Parameter—Decimation Factor (N)
AD9260 (8)
AD9260 (4)
AD9260 (2)
AD9260 (1)
Units
CLOCK INPUT (Modulator Sample Rate, fCLOCK
)
1
1
1
1
kHz min
20
20
20
20
MHz max
OUTPUT WORD RATE (FS = fCLOCK/N)
Specifications subject to change without notice
0.125
2.5
0.250
5
0.500
10
1
20
kHz min
MHz max
CLOCK = 20 MSPS, VREF = +2.5 V, Input CML = 2.0 V TMIN to TMAX
DC SPECIFICATIONS (AVDD = +5 V, DVDD = +3 V, DRVDD = +3 V, f
unless otherwise noted, RBIAS = 2 kꢁ)
P
arameter—Decimation Factor (N)
AD9260 (8)
16
AD9260 (4)
16
AD9260 (2)
AD9260 (1)
Units
RESOLUTION
16
12
Bits min
INPUT REFERRED NOISE (TYP)
1.0 V Reference
1.40
0.68 (90.6)
2.4
1.2 (86)
6.0
3.7 (76)
1.3
1.0 (63.2)
LSB rms typ
LSB rms typ (dB typ)
2.5 V Reference1
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
No Missing Codes
Offset Error
0.75
0.50
16
0.9 (0.5)
2.75 (0.66)
1.35 (0.7)
0.75
0.50
16
(0.5)
(0.66)
(0.7)
0.75
0.50
16
(0.5)
(0.66)
(0.7)
0.3
0.25
12
(0.5)
(0.66)
(0.7)
LSB typ
LSB typ
Bits Guaranteed
% FSR max (typ @ +25°C)
% FSR max (typ @ +25°C)
% FSR max (typ @ +25°C)
Gain Error2
Gain Error3
TEMPERATURE DRIFT
Offset Error
2.5
22
7.0
2.5
22
7.0
2.5
22
7.0
2.5
22
7.0
ppm/°C typ
ppm/°C typ
ppm/°C typ
Gain Error2
Gain Error3
POWER SUPPLY REJECTION
AVDD, DVDD, DRVDD (+5 V 0.25 V)
0.06
0.06
0.06
0.06
% FSR max
ANALOG INPUT
Input Span
VREF = 1.0 V
VREF = 2.5 V
Input (VINA or VINB) Range
1.6
4.0
+0.5
1.6
4.0
+0.5
1.6
4.0
+0.5
1.6
4.0
+0.5
V p-p Diff. max
V p-p Diff. max
V min
+AVDD – 0.5 +AVDD – 0.5 +AVDD – 0.5 +AVDD – 0.5 V max
Input Capacitance
10.2
10.2
10.2
10.2
pF typ
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Output Voltage Error (1 V Mode)
Output Voltage (2.5 V Mode)
Output Voltage Error (2.5 V Mode)
Load Regulation4
1
1
1
1
V typ
mV max
V typ
14
2.5
35
14
2.5
35
14
2.5
35
14
2.5
35
mV max
1 V REF
2.5 V REF
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
mV max
mV max
REFERENCE INPUT RESISTANCE
8
8
8
8
kΩ
–2–
REV. B
AD9260
Parameter—Decimation Factor (N)
AD9260 (8)
AD9260 (4)
AD9260 (2)
AD9260 (1)
Units
POWER SUPPLIES
Supply Voltages
AVDD
+5
+5.5
+2.7
+5
+5.5
+2.7
+5
+5.5
+2.7
+5
+5.5
+2.7
V ( 5%)
V max
V min
DVDD and DRVDD
Supply Current
IAVDD
115
115
115
6.5
115
134
2.4
3.5
2.6
mA typ
mA max
mA typ
mA max
mA typ
IDVDD
12.5
10.3
IDRVDD
0.450
613
0.850
608
1.7
POWER CONSUMPTION
600
585
630
mW typ
mW max
NOTES
1VINA and VINB Connect to DUT CML.
2Including Internal 2.5 V reference.
3Excluding Internal 2.5 V reference.
4Load regulation with 1 mA load Current (in addition to that required by AD9260).
Specifications subject to change without notice.
(AVDD = +5 V, DVDD = +3 V, DRVDD = +3 V, fCLOCK = 20 MSPS, VREF = +2.5 V, Input CML = 2.0 V TMIN to TMAX
unless otherwise noted, RBIAS = 2 kꢁ)
AC SPECIFICATIONS
Parameter—Decimation Factor (N)
AD9260(8)
AD9260(4)
AD9260(2)
AD9260(1)
Units
DYNAMIC PERFORMANCE
INPUT TEST FREQUENCY: 100 kHz (typ)
Signal-to-Noise Ratio (SNR)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
SNR and Distortion (SINAD)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
Total Harmonic Distortion (THD)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
Spurious Free Dynamic Range (SFDR)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
INPUT TEST FREQUENCY: 500 kHz
Signal-to-Noise Ratio (SNR)
88.5
82.5
82
78
74
68
63
58
dB typ
dB typ
87.5
82
82
77.5
74
69
63
58
dB typ
dB typ
–96
–93
–96
–98
–97
–96
–98
–98
dB typ
dB typ
100
94
98
100
98
94
88
84
dB typ
dB typ
Input Amplitude = –0.5 dBFS
86.5
80.5
82.5
82
74
63
dB typ
dB min
dB typ
Input Amplitude = –6.0 dBFS
SNR and Distortion (SINAD)
Input Amplitude = –0.5 dBFS
77
68
58
86.0
80.0
82.0
81
74
63
dB typ
dB min
dB typ
Input Amplitude = –6.0 dBFS
Total Harmonic Distortion (THD)
Input Amplitude = –0.5 dBFS
77
68
58
–97.0
–90.0
–95.5
–92
–96
92
–89
–89
91
–86
–86
88
dB typ
dB max
dB typ
Input Amplitude = –6.0 dBFS
Spurious Free Dynamic Range (SFDR)
Input Amplitude = –0.5 dBFS
99.0
90.0
98
dB typ
dB max
dB typ
Input Amplitude = –6.0 dBFS
100
91
82
REV. B
–3–
AD9260–SPECIFICATIONS
AC SPECIFICATIONS (Continued)
Parameter—Decimation Factor (N)
AD9260 (8)
AD9260 (4)
AD9260 (2)
AD9260 (1)
Units
DYNAMIC PERFORMANCE (Continued)
INPUT TEST FREQUENCY: 1.0 MHz (typ)
Signal-to-Noise Ratio (SNR)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
SNR and Distortion (SINAD)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
Total Harmonic Distortion (THD)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
Spurious Free Dynamic Range (SFDR)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
INPUT TEST FREQUENCY: 2.0 MHz (typ)
Signal-to-Noise Ratio (SNR)
85
80
82
76
74
68
63
58
dB typ
dB typ
84.5
80
81
76
74
69
63
58
dB typ
dB typ
–102
–96
–96
–94
–82
–84
–79
–77
dB typ
dB typ
105
98
98
96
83
87
80
80
dB typ
dB typ
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
SNR and Distortion (SINAD)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
Total Harmonic Distortion (THD)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
Spurious Free Dynamic Range (SFDR)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
INPUT TEST FREQUENCY: 5.0 MHz (typ)
Signal-to-Noise Ratio (SNR)
82
76
74
68
63
58
dB typ
dB typ
81
76
73
69
62
58
dB typ
dB typ
–101
–95
–80
–80
–75
–76
dB typ
dB typ
104
100
80
83
78
79
dB typ
dB typ
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
SNR and Distortion (SINAD)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
Total Harmonic Distortion (THD)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
Spurious Free Dynamic Range (SFDR)
Input Amplitude = –0.5 dBFS
Input Amplitude = –6.0 dBFS
59
57
dB typ
dB typ
58
57
dB typ
dB typ
–58
–67
dB typ
dB typ
59
70
dB typ
dB typ
INTERMODULATION DISTORTION
fIN1 = 475 kHz, fIN2 = 525 kHz
fIN1 = 950 kHz, fIN2 = 1.050 MHz
–93
–95
–91
–86
–91
–85
–83
–83
dBFS typ
dBFS typ
DYNAMIC CHARACTERISTICS
Full Power Bandwidth
Small Signal Bandwidth (AIN = –20 dBFS)
Aperture Jitter
75
75
2
75
75
2
75
75
2
75
75
2
MHz typ
MHz typ
ps rms typ
Specifications subject to change without notice.
–4–
REV. B
AD9260
DIGITAL FILTER CHARACTERISTICS
Parameter
AD9260
Units
8× DECIMATION (N = 8)
Passband Ripple
0.00125
dB max
Stopband Attenuation
Passband
82.5
dB min
0
MHz min
MHz max
MHz min
MHz max
0.605 × (fCLOCK/20 MHz)
1.870 × (fCLOCK/20 MHz)
18.130 × (fCLOCK/20 MHz)
Stopband
Passband/Transition Band Frequency
(–0.1 dB Point)
0.807 × (fCLOCK/20 MHz)
1.136 × (fCLOCK/20 MHz)
MHz max
MHz max
µs max
µs max
µs max
(–3.0 dB Point)
Absolute Group Delay1
Group Delay Variation
Settling Time (to 0.0007%)1
13.55 × (20 MHz/fCLOCK
)
0
24.2 × (20 MHz/fCLOCK
)
4× DECIMATION (N = 4)
Passband Ripple
Stopband Attenuation
Passband
0.001
82.5
0
dB max
dB min
MHz min
MHz max
MHz min
MHz max
1.24 × (fCLOCK/20 MHz)
Stopband
3.75 × (fCLOCK/20 MHz)
16.25 × (fCLOCK/20 MHz)
Passband/Transition Band Frequency
(–0.1 dB Point)
1.61 × (fCLOCK/20 MHz)
2.272 × (fCLOCK/20 MHz)
MHz max
MHz max
µs max
µs max
µs max
(–3.0 dB Point)
Absolute Group Delay1
Group Delay Variation
Settling Time (to 0.0007%)1
2.90 × (20 MHz/fCLOCK
)
0
5.05 × (20 MHz/fCLOCK
)
2× DECIMATION (N = 2)
Passband Ripple
Stopband Attenuation
0.0005
85.5
0
2.491 × (fCLOCK/20 MHz)
7.519 × (fCLOCK/20 MHz)
12.481 × (fCLOCK/20 MHz)
dB max
dB min
MHz min
MHz max
MHz min
MHz max
Passband
Stopband
Passband/Transition Band Frequency
(–0.1 dB Point)
3.231 × (fCLOCK/20 MHz)
4.535 × (fCLOCK/20 MHz)
MHz max
MHz max
µs max
µs max
µs max
(–3.0 dB Point)
Absolute Group Delay1
Group Delay Variation
Settling Time (to 0.0007%)1
0.80 × (20 MHz/fCLOCK
)
0
1.40 × (20 MHz/fCLOCK
)
1× DECIMATION (N = 1)
Propagation Delay: tPROP
Absolute Group Delay
13
ns max
ns max
(225 × (20 MHz/fCLOCK)) + tPROP
NOTES
1To determine “overall” Absolute Group Delay and/or Settling Time inclusive of delay from the sigma-delta modulator, add Absolute Group Delay and/or Settling
Time pertaining to specific decimation mode to the Absolute Group Delay specified in 1× decimation.
Specifications subject to change without notice.
REV. B
–5–
AD9260–Digital Filter Characteristics
1.0
0
–20
–40
–60
0.8
0.6
0.4
0.2
–80
–100
–120
0
–0.2
–0.4
0
100
200
300
400
500
0
0.2
0.4
0.6
0.8
1.0
1.2
CLOCK PERIODS – RELATIVE TO CLK
FREQUENCY (NORMALIZED TO ꢂ)
Figure 1a. 8× FIR Filter Frequency Response
Figure 1b. 8× FIR Filter Impulse Response
0
–20
–40
–60
1.0
0.8
0.6
0.4
0.2
–80
–100
–120
0
–0.2
0
10
20
30 40
50
60
70
80
90 100 110
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (NORMALIZED TO ꢂ)
CLOCK PERIODS – RELATIVE TO CLK
Figure 2a. 4× FIR Filter Frequency Response
Figure 2b. 4× FIR Filter Impulse Response
0
–20
–40
–60
1.0
0.8
0.6
0.4
0.2
–80
–100
–120
0
–0.2
0
5
10
15
20
0
0.2
0.4
0.6
0.8
1.0
1.2
FREQUENCY (NORMALIZED TO ꢂ)
CLOCK PERIODS – RELATIVE TO CLK
Figure 3a. 2× FIR Filter Frequency Response
Figure 3b. 2× FIR Filter Impulse Response
–6–
REV. B
AD9260
Table I. Integer Filter Coefficients for First Stage Decimation
Filter (23-Tap Halfband FIR Filter)
Table III. Integer Filter Coefficients for Third Stage Decima-
tion Filter (107-Tap Halfband FIR Filter)
Lower
Coefficient
Upper
Coefficient
Integer
Value
Lower
Coefficient
Upper
Coefficient
Integer
Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(23)
H(22)
H(21)
H(20)
H(19)
H(18)
H(17)
H(16)
H(15)
H(14)
H(13)
–1
0
13
0
–66
0
224
0
–642
0
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(107)
H(106)
H(105)
H(104)
H(103)
H(102)
H(101)
H(100)
H(99)
H(98)
H(97)
H(96)
H(95)
H(94)
H(93)
H(92)
H(91)
H(90)
H(89)
H(88)
H(87)
H(86)
H(85)
H(84)
H(83)
H(82)
H(81)
H(80)
H(79)
H(78)
H(77)
H(76)
H(75)
H(74)
H(73)
H(72)
H(71)
H(70)
H(69)
H(68)
H(67)
H(66)
H(65)
H(64)
H(63)
H(62)
H(61)
H(60)
H(59)
H(58)
H(57)
H(56)
H(55)
–1
0
2
0
–2
0
3
0
–3
0
1
0
3
0
–12
0
27
0
–50
0
85
0
–135
0
204
0
–297
0
420
0
–579
0
784
0
–1044
0
1376
0
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(27)
H(28)
H(29)
H(30)
H(31)
H(32)
H(33)
H(34)
H(35)
H(36)
H(37)
H(38)
H(39)
H(40)
H(41)
H(42)
H(43)
H(44)
H(45)
H(46)
H(47)
H(48)
H(49)
H(50)
H(51)
H(52)
H(53)
H(54)
2496
4048
Table II. Integer Filter Coefficients for Second Stage Decima-
tion Filter (43-Tap Halfband FIR Filter)
Lower
Coefficient
Upper
Coefficient
Integer
Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
H(28)
H(27)
H(26)
H(25)
H(24)
H(23)
3
0
–12
0
35
0
–83
0
172
0
–324
0
572
0
–976
0
1680
0
–3204
0
10274
16274
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
–1797
0
2344
0
–3072
0
4089
0
–5624
0
8280
0
NOTE: The composite filter undecimated coefficients (i.e.,
impulse response) in the 4× decimation mode can be determined
by convolving the first stage filter taps with a “zero stuffed”
version of the second stage filter taps (i.e., insert one zero be-
tween samples). Similarly, the composite filter coefficients in the
8× decimation mode can be determined by convolving the taps
of the composite 4× decimation mode (as previously deter-
mined) with a “zero stuffed” version of the third stage filter taps
(i.e., insert three zeros between samples).
–14268
0
43520
68508
REV. B
–7–
AD9260–SPECIFICATIONS
(AVDD = +5 V, DVDD = +5 V, TMIN to TMAX unless otherwise noted)
DIGITAL SPECIFICATIONS
Parameter
AD9260
Units
CLOCK1 AND LOGIC INPUTS
High-Level Input Voltage
(DVDD = +5 V)
+3.5
+2.1
V min
V max
(DVDD = +3 V)
Low-Level Input Voltage
(DVDD = +5 V)
(DVDD = +3 V)
High-Level Input Current (VIN = DVDD)
Low-Level Input Current (VIN = 0 V)
Input Capacitance
+1.0
+0.9
10
V min
V max
µA max
µA max
pF typ
10
5
LOGIC OUTPUTS (with DRVDD = 5 V)
High-Level Output Voltage (IOH = 50 µA)
High-Level Output Voltage (IOH = 0.5 mA)
Low-Level Output Voltage2 (IOL = 0.3 mA)
Low-Level Output Voltage (IOL = 50 µA)
Output Capacitance
+4.5
+2.4
+0.4
+0.1
5
V min
V min
V max
V max
pF typ
LOGIC OUTPUTS (with DRVDD = 3 V)
High-Level Output Voltage (IOH = 50 µA)
Low-Level Output Voltage (IOL = 50 µA)
+2.4
+0.7
V min
V max
NOTES
1Since CLK is referenced to AVDD, +5 V logic input levels only apply.
2The AD9260 is not guaranteed to meet VOL = 0.4 V max for standard TTL load of IOL = 1.6 mA.
Specifications subject to change without notice.
S2
S1
tC
ANALOG INPUT
INPUT CLOCK
tCL
tCH
tDS
tDI
DATA OUTPUT
DAV
tOE
tH
tOD
tDAV
READ
CS
Figure 4a. Timing Diagram
tRES-DAV
tCLK-DAV
Figure 4b. RESET Timing Diagram
–8–
INPUT CLOCK
RESET
DAV
REV. B
AD9260
(AVDD = +5 V, DVDD = +5 V, CL = 20 pF, TMIN to TMAX unless otherwise noted)
SWITCHING SPECIFICATIONS
Parameters
Symbol
AD9260
Units
Clock Period
Data Available (DAV) Period
Data Invalid
tC
tDAV
tDI
tDS
tCH
tCL
tH
tRES–DAV
tCLK–DAV
tOD
50
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
tC × Mode
40% tDAV
tDAV –tH–tDI
22.5
22.5
3.5
10
15
8
Data Setup Time
Clock Pulsewidth High
Clock Pulsewidth Low
Data Hold Time
RESET to DAV Delay
CLOCK to DAV Delay
Three-State Output Disable Time
Three-State Output Enable Time
tOE
45
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
With
Respect
Temperature
Range
Package
Description
Package
Option*
Model
Parameter
to
Min Max
Units
AD9260AS –40°C to +85°C 44-Lead MQFP
S-44
AVDD
DVDD
AVSS
AVDD
DRVDD
DRVSS
REFCOM
CLK, MODE, READ,
CS, RESET
Digital Outputs
VINA, VINB,
CML, BIAS
VREF
AVSS
DVSS
DVSS
DVDD –6.5 +6.5
DRVSS –0.3 +6.5
AVSS
AVSS
–0.3 +6.5
–0.3 +6.5
–0.3 +0.3
V
V
V
V
V
V
V
AD9260EB
Evaluation Board
*S = Metric Quad Flatpack.
THERMAL CHARACTERISTICS
Thermal Resistance
44-Lead MQFP
–0.3 +0.3
–0.3 +0.3
θ
θ
JA = 53.2°C/W
JC = 19°C/W
DVSS
–0.3 DVDD + 0.3
V
DRVSS –0.3 DRVDD + 0.3 V
AVSS
AVSS
AVSS
AVSS
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
+150
V
V
V
V
°C
°C
SENSE
CAPB, CAPT
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
–65
+150
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9260 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–9–
AD9260
APERTURE JITTER
DEFINITIONS OF SPECIFICATION
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes, respectively, must be present over all operating ranges.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N,
NOTE: Conventional INL and DNL measurements don’t really
apply to Σ∆ converters: the DNL looks continually better if
longer data records are taken. For the AD9260, INL and DNL
numbers are given as representative.
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
ZERO ERROR
TOTAL HARMONIC DISTORTION (THD)
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
GAIN ERROR
SIGNAL-TO-NOISE RATIO (SNR)
The first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the nominal full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (+25°C) value to the value at
TWO-TONE SFDR
TMIN or TMAX
.
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
–10–
REV. B
AD9260
PIN CONFIGURATION
42
44 43
PIN 1
41 40 39 38 37 36 35 34
1
2
DVSS
AVSS
33 REFCOM
32 VREF
IDENTIFIER
3
DVDD
31
SENSE
4
AVDD
30
RESET
5
DRVSS
DRVDD
CLK
29 AVSS
28 AVDD
AD9260
TOP VIEW
(Not to Scale)
6
7
27
26
25
24
23
CS
8
DAV
READ
9
OTR
(LSB) BIT16
BIT15
10
11
BIT1 (MSB)
BIT2
BIT14
12 13 14 15 16 17 18 19 20 21 22
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Name
1
DVSS
Digital Ground.
2, 29, 38
AVSS
Analog Ground.
3
DVDD
AVDD
DRVSS
+3 V to +5 V Digital Supply.
+5 V Analog Supply.
Digital Output Driver Ground.
4, 28, 44
5
6
7
DRVDD
CLK
+3 V to +5 V Digital Output Driver Supply.
Clock Input.
8
9
READ
BIT16
BIT15–BIT2
BIT1
OTR
DAV
Part of DSP Interface—Pull Low to Disable Output Bits.
Least Significant Data Bit (LSB).
Data Output Bit.
Most Significant Data Bit (MSB).
Out of Range—Set When Converter or Filter Overflows.
Data Available.
10–23
24
25
26
27
30
31
32
33
34
35
CS
Chip Select (CS): Active LOW.
RESET: Active LOW.
Reference Amplifier SENSE: Selects REF Level.
Input Span Select Reference I/O.
Reference Common.
RESET
SENSE
VREF
REFCOM
MODE
BIAS
Mode Select—Selects Decimation Mode.
Power Bias.
36
37
39
40, 43
41
CAPB
CAPT
CML
NC
VINA
Noise Reduction Pin—Decouples Reference Level.
Noise Reduction Pin—Decouples Reference Level.
Common-Mode Level (AVDD/2.5).
No Connect (Ground for Shielding Purposes).
Analog Input Pin (+).
42
VINB
Analog Input Pin (–).
REV. B
–11–
AD9260–Typical Performance Characteristics
(AVDD = DVDD = DRVDD = +5.0 V, 4 V Input Span, Differential DC Coupled Input with CML = 2.0 V, fCLOCK = 20 MSPS, Full Bias)
0
–20
–40
–60
–80
0
–20
–40
100kHz INPUT
100kHz INPUT
20MHz CLOCK
8ꢀ DECIMATION
20MHz CLOCK
1ꢀ DECIMATION
THD: –96dB
THD: –98dB
–60
–80
–100
–120
–100
–120
1
0
0
2
3
4
5
6
7
8
9
10
0.2
0.4
0.6
0.8
1.2
1.0
FREQUENCY – MHz
FREQUENCY – MHz
Figure 8. Spectral Plot of the AD9260 at 100 kHz Input,
20 MHz Clock, Undecimated (20 MHz Output Data Rate)
Figure 5. Spectral Plot of the AD9260 at 100 kHz Input,
20 MHz Clock, 8× OSR (2.5 MHz Output Data Rate)
0
110
100kHz INPUT
–12dBFS/TONE
–20
20MHz CLOCK
4ꢀ DECIMATION
106
–40
THD: –98dB
102
–60
–6.5dBFS/TONE
98
–80
–100
–120
–26dBFS/TONE
–46dBFS/TONE
94
90
0
0.5
1
1.5
2
2.5
0
0.2
0.4
0.6
0.8
1
FREQUENCY – MHz
FREQUENCY – MHz
Figure 6. Spectral Plot of the AD9260 at 100 kHz Input,
20 MHz Clock, 4× OSR (5 MHz Output Data Rate)
Figure 9. Dual Tone SFDR vs. Input Frequency (F1 = F2,
(F1 – F2, Span = 10% Center Frequency, Mode = 8×)
0
0
DUAL-TONE TEST
100kHz INPUT
f1 = 1.0MHz
–20
–20
20MHz CLOCK
2ꢀ DECIMATION
f2 = 975kHz
20MHz CLOCK
8ꢀ DECIMATION
–40
–40
THD: –98dB
IM3: –94dB
–60
–60
–80
–100
–120
–80
–100
–120
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.2
0.4
0.6
0.8
1
1.2
FREQUENCY – MHz
FREQUENCY – MHz
Figure 7. Spectral Plot of the AD9260 at 100 kHz Input,
20 MHz Clock, 2× OSR (10 MHz Output Data Rate)
Figure 10. Two-Tone Spectral Performance of the
AD9260 Given Inputs at 975 kHz and 1.0 MHz, 20 MHz
Clock, 8× Decimation
–12–
REV. B
AD9260
Typical AC Characterization Curves vs. Decimation Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, AIN = 0.5 dBFS Full Bias)
90
90
8ꢀ MODE
4ꢀ MODE
85
80
75
85
80
8ꢀ MODE
4ꢀ MODE
75
70
2ꢀ MODE
2ꢀ MODE
70
65
60
65
60
1ꢀ MODE
1ꢀ MODE
55
50
55
50
0.1
1
10
0.1
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 14. SINAD vs. Input Frequency (fCLOCK = 10 MSPS)1
Figure 11. SINAD vs. Input Frequency (fCLOCK = 20 MSPS)1
–70
–50
1ꢀ MODE
–75
1ꢀ MODE
–60
–80
–85
–90
–70
–80
2ꢀ MODE
–95
–100
8ꢀ MODE
4ꢀ MODE
2ꢀ MODE
–90
–105
–110
4ꢀ MODE
–100
–115
–120
8ꢀ MODE
–110
0.1
0.1
1
10
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 15. THD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 12. THD vs. Input Frequency (fCLOCK = 20 MSPS)
–70
–50
–75
1ꢀ MODE
1ꢀ MODE
–60
–80
–85
–90
–70
–80
–95
–100
–105
–110
2ꢀ MODE
4ꢀ MODE
2ꢀ MODE
8ꢀ MODE
–90
–100
4ꢀ MODE
–115
–120
8ꢀ MODE
–110
0.1
0.1
1
10
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 16. SFDR vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 13. SFDR vs. Input Frequency (fCLOCK = 20 MSPS)
18× SINAD performance limited by noise contribution of input differential op
amp driver.
REV. B
–13–
AD9260
Typical AC Characterization Curves for 8ꢀ Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias)
90
90
85
80
–0.5dBFS
–6.0dBFS
85
–0.5dBFS
–6.0dBFS
80
75
70
75
70
–20dBFS
–20dBFS
65
60
65
60
0.1
0.1
1
1
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 20. SINAD vs. Input Frequency (fCLOCK = 10 MSPS)1
Figure 17. SINAD vs. Input Frequency (fCLOCK = 20 MSPS)1
–70
–75
–70
–75
–20dBFS
–80
–80
–20dBFS
–85
–85
–90
–0.5dBFS
–90
–95
–6.0dBFS
–95
–6.0dBFS
–100
–100
–105
–0.5dBFS
–105
–110
0.1
0.1
1
1
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 21. THD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 18. THD vs. Input Frequency (fCLOCK = 20 MSPS)
105
105
100
100
–6.0dBFS
–6.0dBFS
95
95
–0.5dBFS
–0.5dBFS
90
90
85
85
–20dBFS
–20dBFS
80
80
0.1
1
0.1
1
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 22. SFDR vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 19. SFDR vs. Input Frequency (fCLOCK = 20 MSPS)
1SINAD performance limited by noise contribution of input differential op amp
driver.
–14–
REV. B
AD9260
Typical AC Characterization Curves for 4ꢀ Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias)
90
90
85
80
85
–0.5dBFS
–6.0dBFS
–0.5dBFS
–6.0dBFS
80
75
70
65
60
75
70
65
60
55
50
–20dBFS
–20dBFS
0.1
1
0.1
10
1
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 26. SINAD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 23. SINAD vs. Input Frequency (fCLOCK = 20 MSPS)
–70
–75
–70
–75
–20dBFS
–80
–80
–0.5dBFS
–85
–90
–85
–0.5dBFS
–20dBFS
–90
–95
–95
–100
–105
–110
–6.0dBFS
–6.0dBFS
–100
–105
–110
0.1
1
0.1
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 27. THD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 24. THD vs. Input Frequency (fCLOCK = 20 MSPS)
110
105
100
110
105
–0.5dBFS
100
95
–6.0dBFS
–6.0dBFS
95
90
90
–20dBFS
85
80
–0.5dBFS
85
80
–20dBFS
0.1
0.1
1
10
1
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 28. SFDR vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 25. SFDR vs. Input Frequency (fCLOCK = 20 MSPS)
REV. B
–15–
AD9260
Typical AC Characterization Curves for 2ꢀ Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias)
80
80
75
70
75
70
65
60
–5.0dBFS
–6.0dBFS
–0.5dBFS
–6.0dBFS
65
60
55
50
–20dBFS
55
50
–20dBFS
0.1
1
10
0.1
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 32. SINAD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 29. SINAD vs. Input Frequency (fCLOCK = 20 MSPS)
–60
–65
–60
–65
–70
–75
–70
–75
–80
–85
–90
–95
–100
–20dBFS
–0.5dBFS
–80
–20dBFS
–85
–90
–0.5dBFS
–6.0dBFS
–95
–6.0dBFS
–100
0.1
1
10
0.1
10
1.0
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 33. THD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 30. THD vs. Input Frequency (fCLOCK = 20 MSPS)
100
95
100
95
–6.0dBFS
90
90
–0.5dBFS
–6.0dBFS
85
85
–20dBFS
–0.5dBFS
80
80
75
75
70
–20dBFS
70
0.1
0.1
1
10
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 34. SFDR vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 31. SFDR vs. Input Frequency (fCLOCK = 20 MSPS)
–16–
REV. B
AD9260
Typical AC Characterization Curves for 1ꢀ Mode
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, Differential DC Coupled Input with CML = 2 V, Full Bias)
70
65
60
55
50
70
65
60
55
50
–0.5dBFS
–0.5dBFS
–6.0dBFS
–6.0dBFS
45
40
45
40
–20dBFS
–20dBFS
0.1
1
10
0.1
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 38. SINAD vs. Input Frequency (fCLOCK = 10 MSPS)
Figure 35. SINAD vs. Input Frequency (fCLOCK = 20 MSPS)
–55
–55
–60
–65
–0.5dBFS
–60
–20dBFS
–65
–20dB
–70
–70
–6.0dBFS
–75
–80
–75
–80
–0.5dBFS
–85
–85
–90
–90
–6.0dBFS
–95
–95
–100
–100
0.1
1
10
0.1
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 36. THD vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 39. THD vs. Input Frequency (fCLOCK = 10 MSPS)
100
95
100
95
–0.5dBFS
90
–0.5dBFS
90
85
85
80
75
70
65
60
55
50
–6.0dBFS
–20dBFS
–6.0dBFS
80
75
70
–20dBFS
65
60
55
50
0.1
1
10
0.1
1
10
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
Figure 37. SFDR vs. Input Frequency (fCLOCK = 20 MSPS)
Figure 40. SFDR vs. Input Frequency (fCLOCK = 10 MSPS)
REV. B
–17–
AD9260
Typical AC Characterization Curves
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, AIN = –0.5 dBFS, Differential DC Coupled Input with CML = 2 V)
100
–60
–65
–70
–75
–80
–85
–90
–95
–100
FULL BIAS
95
90
85
80
75
70
HALF BIAS
F
= 1MHz, 2ꢀ MODE
= 100kHz, 8ꢀ MODE
IN
QUARTER BIAS
65
60
F
IN
55
50
2
5
10
15
20
1.0 1.2
1.4
1.6
1.8 2.0
2.2
2.4
2.6
2.8 3.0
CLOCK FREQUENCY – MHz
COMMON MODE INPUT LEVEL – Volts
Figure 44. THD vs. Common-Mode Input Level (CML)
Figure 41. SFDR vs. Clock Rate (fIN = 100 kHz in 8× Mode)
–40
–50
100
FULL BIAS
80
F
= 20MHz
HALF BIAS
S
–60
–70
F
= 10MHz
60
S
QUARTER BIAS
40
F
= 5MHz
S
–80
–90
20
0
1k
10k
100k
1M
10M
100M
5
10
15
20
25
INPUT FREQUENCY – Hz
CLOCK FREQUENCY – MHz
Figure 45. CMR vs. Input Frequency (VCML = 2 V p-p, 1×
Mode)
Figure 42. SFDR vs. Clock Rate (fIN = 500 kHz in 4× Mode)
100
100
4V SPAN SNR-8ꢀ MODE
FULL BIAS
4V SPAN SFDR-2ꢀ MODE
95
1.6V SPAN SNR-8ꢀ MODE
80
1.6V SPAN SFDR-2ꢀ MODE
HALF BIAS
90
60
85
40
QUARTER BIAS
20
80
75
0
5
10
15
20
25
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
CLOCK FREQUENCY – MHz
FREQUENCY – MHz
Figure 46. 4 V vs. 1.6 V Span SNR/SFDR (fCLOCK = 20 MSPS)
Figure 43. SFDR vs. Clock Rate (fIN = 1.0 MHz in 2× Mode)
–18–
REV. B
AD9260
Additional AC Characterization Curves
(AVDD = DVDD = DRVDD = +5 V, 4 V Input Span, AIN = –0.5 dBFS, Differential DC Coupled Input with CML = 2 V, Full Bias, unless otherwise noted)
120
120
20MSPS-dBFS
FULL BIAS
115
20 MSPS
FULL BIAS
110
10 MSPS
FULL BIAS
110
105
100
10MSPS-dBFS
HALF BIAS
100
90
20MSPS-dBc
FULL BIAS
10MSPS-dBc
HALF BIAS
80
95
90
85
80
20 MSPS
HALF BIAS
70
10 MSPS
HALF BIAS
60
50
–50 –45 –40 –35 –30 –25 –20 –15 –10
– dBFS
–5
0
–60
–50
–40
–30
– dBFS
–20
–10
0
A
IN
A
IN
Figure 47. Single-Tone SFDR vs. Amplitude (fIN =100 kHz,
8× Mode)
Figure 50. Two-Tone SFDR (F1 = 475 kHz, F2 = 525 MHz,
8× Mode)
110
120
FULL BIAS-dBFS
110
105
100
95
10 MSPS
FULL BIAS
100
HALF BIAS-dBFS
90
FULL BIAS-dBc
20 MSPS
FULL BIAS
10 MSPS
HALF BIAS
80
90
HALF BIAS-dBc
70
85
80
60
50
–50 –45 –40 –35 –30 –25 –20 –15 –10
– dBFS
–5
0
–60
–50
–40
–30
–20
–10
0
A
A
– dBFS
IN
IN
Figure 48. Single-Tone SFDR vs. Amplitude (fIN =1.0 MHz,
2× Mode)
Figure 51. Two-Tone SFDR (F1 = 0.95 kHz, F2 = 1.05 MHz,
8× Mode 20 MSPS)
110
120
110
10 MSPS
10 MSPS
FULL BIAS
HALF BIAS
105
100
95
dBFS
100
dBc
90
80
70
20 MSPS
FULL BIAS
90
85
80
60
50
–50 –45 –40 –35 –30 –25 –20 –15 –10
– dBFS
–5
0
–60
–50
–40
–30
– dBFS
–20
–10
0
A
A
IN
IN
Figure 49. Single-Tone SFDR vs. Amplitude (fIN = 500 kHz,
Figure 52. Two-Tone SFDR (F1 = 1.9 MHz, F2 = 2.1 MHz,
2× Mode)
4× Mode 20 MSPS)
REV. B
–19–
AD9260
+
+
+
16
4
4
–
–
–
5B
ADC
5B
DAC
3B
ADC
3B
DAC
3B
ADC
3B
DAC
4B
ADC
+
+
V
INT1
INT2
IN
–
–
PIPELINE CORRECTION LOGIC
8 LSBs
5B
DAC1
5B
DAC2
M
OUT
LSB
–D
+ +
SHUFFLE
Z
DIFFERENTIATOR
C
OUT
CONTROL/TEST
LOGIC
HALF-BAND
DECIMATION FILTER STAGE 1
BANDGAP
REFERENCE
HALF-BAND
DECIMATION FILTER STAGE 2
REFERENCE
BUFFER
HALF-BAND
DECIMATION FILTER STAGE 3
OUTPUT BITS
Figure 53. Simplified Block Diagram
THEORY OF OPERATION
The digital output driver register of the AD9260 features both
READ and CHIP SELECT pins to allow easy interfacing. The
digital supply of the AD9260 is designed to operate over a
2.7 V to 5.25 V supply range, though 3 V supplies are recom-
mended to minimize digital noise on the board. A DATA
AVAILABLE pin allows the user to easily synchronize to the
converter’s decimated output data rate. OUT-OF-RANGE
(OTR) indication is given for an overflow in the pipelined A/D
converter or digital filters. A RESETB function is provided to
synchronize the converter’s decimated data and clear any over-
flow condition in the analog integrators.
The AD9260 utilizes a new analog-to-digital converter architec-
ture to combine sigma-delta techniques with a high-speed,
pipelined A/D converter. This topology allows the AD9260 to
offer the high dynamic range associated with sigma-delta con-
verters while maintaining very wide input signal bandwidth
(1.25 MHz) at a very modest 8× oversampling ratio. Figure 53
provides a block diagram of the AD9260. The differential
analog input is fed into a second order, multibit sigma-delta
modulator. This modulator features a 5-bit flash quantizer and
5-bit feedback. In addition, a 12-bit pipelined A/D quantizes
the input to the 5-bit flash to greater accuracy. A special digital
modulation loop combines the output of the 12-bit pipelined
A/D with the delayed output of the 5-bit flash to produce the
equivalent response of a second order loop with a 12-bit
quantizer and 12-bit feedback. The combination of a second
order loop and multibit feedback provides inherent stability:
the AD9260 is not prone to idle tones or full-scale idiosyncra-
cies sometimes associated with higher order single bit sigma-
delta modulators.
An on-chip reference and reference buffer are included on the
AD9260. The reference can be configured in either a 2.5 V
mode (providing a 4 V pk-pk differential input full scale), a 1 V
mode (providing a 1.6 V pk-pk differential input full scale), or
programmed with an external resistor divider to provide any
voltage level between 1 V and 2.5 V. However, optimum noise and
distortion performance for the AD9260 can only be achieved with a
2.5 V reference as shown in Figure 46.
For users wishing to operate the part at reduced clock frequen-
cies, the bias current of the AD9260 is designed to be scalable.
This scaling is accomplished through use of the proper external
resistor tied to the BIAS pin: the power can be reduced roughly
proportionately to clock frequency by as much as 75% (for clock
rates of 5 MHz). Refer to Figures 41–43 and 47–51 for charac-
terization curves showing performance tradeoffs.
The output of this 12-bit modulator is fed into the digital deci-
mation filter. The voltage level on the MODE pin establishes
the configuration for the digital filter. The user may bring the
data out undecimated (at the clock rate), or at a decimation
factor of 2×, 4×, or a full 8×. The spectra for these four cases
are shown in Figures 5, 6, 7 and 8, all for a 100 kHz full-scale
input and 20 MHz clock. The spectra of the undecimated
output clearly shows the second order shaping characteristic of
the quantization noise as it rises at frequencies above 1.25 MHz.
ANALOG INPUT AND REFERENCE OVERVIEW
Figure 54, a simplified model of the AD9260, highlights the
relationship between the analog inputs, VINA, VINB and the
reference voltage VREF. Like the voltage applied to the top of
the resistor ladder in a flash A/D converter, the value VREF
defines the maximum input voltage to the A/D converter. An
internal reference buffer in the AD9260 scales the reference
voltage VREF before it is applied internally to the AD9260
The on-chip decimation filter provides excellent stopband rejec-
tion to suppress any stray input signal between 1.25 MHz and
18.75 MHz, substantially easing the requirements on any anti-
aliasing filter for the analog input path. The decimation filters
are integrated with symmetric FIR filter structures, providing a
linear phase response and excellent passband flatness.
–20–
REV. B
AD9260
A/D core. The scale factor of this reference buffer is 0.8. Conse-
quently, the maximum input voltage to the A/D core is +0.8 ×
VREF. The minimum input voltage to the A/D core is auto-
matically defined to be –0.8 × VREF. With this scale factor, the
maximum differential input span of 4 V p-p is obtained with a
VREF voltage of 2.5 V. A smaller differential input span may be
obtained by using a VREF voltage of less than 2.5 V at the
expense of ac performance (refer to Figure 46).
ANALOG INPUT OPERATION
The analog input structure of the AD9260 is optimized to meet
the performance requirements for some of the most demanding
communication and data acquisition applications. This input
structure is composed of a switched-capacitor network that
samples the input signal applied to pins VINA and VINB on
every rising edge of the CLK pin. The input switched capaci-
tors are charged to the input voltage during each period of
CLK. The resulting charge, q, on these capacitors is equal to
C × VIN, where C is the input capacitor. The change in charge
on these capacitors, delta q, as the capacitors are charged from a
previous sample of the input signal to the next sample, is ap-
proximated in the following equation,
+0.8ꢀVREF
VINA
16
+
A/D CORE
ꢃ
–
delta q ~ C × deltaVN = C × (VN – VN–2
)
(4)
VINB
where VN represents the present sample of the input signal and
VN–2 represents the sample taken two clock cycles earlier. The
average current flow into the input (provided from an external
source) is given in the following equation,
–0.8ꢀVREF
Figure 54. Simplified Input Model
I = delta q/T ~ C × (VN – VN–2) × fCLOCK
(5)
INPUT SPAN
where T represents the period of CLK and fCLOCK represents the
frequency of CLK. Equations 4 and 5 provide simplifying ap-
proximations of the operation of the analog input structure of
the AD9260. A more exact, detailed description and analysis of
the input operation is provided below.
The AD9260 is implemented with a differential input structure.
This structure allows the common-mode level (average voltage
of the two input pins) of the input signal to be varied indepen-
dently of the input span of the converter over a wide range, as
shown in Figure 44. Specifically, the input to the A/D core is
the difference of the voltages applied at the VINA and VINB
input pins. Therefore, the equation,
SS3
SS1
CS1
VCORE = VINA–VINB
(1)
SH1
VINA
defines the output of the differential input stage and provides
the input to the A/D core.
CPA1
CPA2
CPB1
SS4
SH2
ANALOG
MODULATOR
The voltage, VCORE, must satisfy the condition,
–0.8 × VREF ≤ VCORE ≤ +0.8 × VREF
SS2
CS2
VINB
(2)
CPB2
where VREF is the voltage at the VREF pin.
SH3
SH4
INPUT COMPLIANCE RANGE
In addition to the limitations on the differential span of the
input signal indicated in Equation 2, an additional limitation is
placed on the inputs by the analog input structure of the AD9260.
The analog input structure bounds the valid operating range for
VINA and VINB. The condition,
Figure 55. Detailed Analog Input Structure
Figure 55 illustrates the analog input structure of the AD9260.
For the moment, ignore the presence of the parasitic capacitors
CPA and CPB. The effects of these parasitic capacitors will be
discussed near the end of this section. The switched capacitors,
CS1 and CS2, sample the input voltages applied on pins VINA
and VINB. These capacitors are connected to input pins VINA
and VINB when CLK is low. When CLK rises, a sample of the
input signal is taken on capacitors CS1 and CS2. When CLK is
high, capacitors CS1 and CS2 are connected to the Analog
Modulator. The modulator precharges capacitors CS1 and CS2
to minimize the amount of charge required from any circuit
used in combination with the AD9260 to drive input pins VINA
and VINB. This reduces the input drive requirements of the
analog circuitry driving pins VINA and VINB. The Analog
Modulator precharges the voltages across capacitors CS1 and
CS2, approximately equal to a delayed version of the input
signal. When capacitors CS1 and CS2 are connected to input
pins VINA and VINB, the differential charge, Q(n), on these
capacitors is given in the following equation,
AVSS +0.5 V < VINA < AVDD – 0.5 V
(3)
AVSS +0.5 V < VINB < AVDD + 0.5 V
where AVSS is nominally 0 V and AVDD is nominally +5 V,
defines this requirement. Thus the valid inputs for VINA and
VINB are any combination that satisfies both Equations 2 and
3. Note, the clock clamping method used in the differential
driver circuit shown in Figure 57 is sufficient for protecting the
AD9260 in an undervoltage condition.
For additional information showing the relationships between
VINA, VINB, VREF and the digital output of the AD9260, see
Table V.
Refer to Table IV for a summary of the various analog input
and reference configurations.
Q(n) = q1 – q2 = CS × VCORE
(6)
REV. B
–21–
AD9260
where q1 and q2 are the individual charges stored on capacitors
CS1 and CS2 respectively, and CS is the capacitance value of
CS1 and CS2. When capacitors CS1 and CS2 are connected to
the Analog Modulator during the preceding “precharge” clock
phase, the capacitors are precharged equal to an approximation
of a previous sample of the input signal. Consequently the
differential charge on these capacitors while CLK is high is
given in the following equation,
and CS2 when they are connected to input Pins VINA and
VINB. The nonlinear junction capacitance of Cpb1 and Cpb2
cause charge glitch energy that is nonlinearily related to the
input signal. Therefore, linear settling is difficult to achieve
unless the input source completely settles during one-half
period of CLK. A portion of the glitch impulse energy “kicked”
back at the source is not linearly related to the input signal.
Therefore, the best way to ensure that the input signal settles
linearly is to use wide bandwidth circuitry, which settles as
completely as possible from the glitch during one-half period of
the CLK.
Q(n–1) = CS × VCORE(delay) + CS × Vdelta
(7)
where VCORE(delay) is the value of VCORE sampled during a
previous period of CLK, and Vdelta is the sigma-delta error
voltage left on the capacitors. Vdelta is a natural artifact of the
sigma-delta feedback techniques utilized in the Analog Modula-
tor of the AD9260. It is a small random voltage term that
changes every clock period and varies from 0 to 0.05 × VREF.
The AD9260 utilizes a proprietary clock-boosted boot-strapping
technique to reduce the nonlinear parasitic capacitances of the
internal CMOS switches. This technique improves the linearity
of the input switches and reduces the nonlinear parasitic capaci-
tance. Thus, this technique reduces the nonlinear glitch energy.
The capacitance values for the input capacitors and parasitic
capacitors for the input structure of the AD9260, as illustrated
in Figure 55, are listed as follows.
The analog circuitry used to drive the input pins of the AD9260
must respond to the charge glitch that occurs when capacitors
CS1 and CS2 are connected to input pins VINA and VINB. This
circuitry must provide additional charge, qdelta, to capacitors
CS1 and CS2, which is the difference between the precharged
value, Q(n–1), and the new value, Q(n), as given in the follow-
ing equation,
CS = 3.2 pF, Cpa = 6 pF, Cpb = 1 pF (where CS is the capaci-
tance value of capacitors CS1 and CS2, Cpa is the value of
capacitors Cpa1 and Cpa2, and Cpb is the value of capacitors
Cpb1 and Cpb2). The total capacitance at each input pin is
CIN = CS + Cpa + Cpb = 10.2 pF.
Qdelta = Q(n) – Q(n–1)
(8)
(9)
Qdelta = CS × [VCORE–VCORE(delay) + Vdelta]
Input Driver Considerations
The optimum noise and distortion performance of the AD9260 can
ONLY be achieved when the AD9260 is driven differentially with a
4 V input span . Since not all applications have a signal precon-
ditioned for differential operation, there is often a need to per-
form a single-ended-to-differential conversion. In the case of the
AD9260, a single-ended-to-differential conversion is best realized
using a differential op amp driver. Although a transformer will
perform a similar function for ac signals, its usefulness is pre-
cluded by its inability to directly drive the AD9260 and thus the
additional requirement of an active low noise, low distortion
buffer stage.
DRIVING THE INPUT
Transient Response
The charge glitch occurs once at the beginning of every period
of the input CLK (falling edge), and the sample is taken on
capacitors CS1 and CS2 exactly one-half period later (rising
edge). Figure 56 presents a typical input waveform applied to
input Pins VINA and VINB of the AD9260.
TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE
CLOCK
Single-Ended-to-Differential Op Amp Driver
There are two single-ended-to-differential op amp driver cir-
cuits useful for driving the AD9260. The first circuit, shown in
Figure 57, uses the AD8138 and represents the best choice in
most applications. The AD8138 is a low-distortion differential
ADC driver designed to convert a ground-referenced single-
ended input signal to a differential output signal with a specified
common-mode level for dc-coupling applications. It is capable
of maintaining the typical THD and SFDR performance of the
AD9260 with only a slight degradation in its noise performance
in the 8× mode (i.e., SNR of 85 dB–86 dB).
VINA-VINB
Figure 56. Typical Input Waveform
Figure 56 illustrates the effect of the charge glitch when a source
with nonzero output impedance is used to drive the input pins.
This source must be capable of settling from the charge glitch in
one-half period of the CLK. Unfortunately, the MOS switches
used in any CMOS-switched capacitor circuit (including those
in the AD9260) include nonlinear parasitic junction capaci-
tances connected to their terminals. Figure 55 also illustrates
the parasitic capacitances, Cpa1, Cpb1, Cpa2 and Cpb2, associ-
ated with the input switches.
In this application, the AD8138 is configured for unity gain and
its common-mode output level is set to 2.5 V (i.e., VREF of the
AD9260) to maximize its output headroom while operating from a
single supply. Note, single-supply operation has the benefit of
not requiring an input protection network for the AD9260 in
dc-coupled applications. A simple R-C network at the output is
used to filter out high-frequency noise from the AD8138. Recall,
the AD9260’s small signal bandwidth is 75 MHz, hence any
noise falling within the baseband bandwidth of the AD9260
defined by its sample and decimation rate, as well as “images”
of its baseband response occurring at multiples of the sample
rate, will degrade its overall noise performance.
Parasitic capacitor Cpa1 and Cpa2 are always connected to Pins
VINA and VINB and therefore do not contribute to the glitch
energy. Parasitic capacitors Cpb1 and Cpb2, on the other hand,
cause a charge glitch that adds to that of input capacitors CS1
–22–
REV. B
AD9260
R
499ꢁ
499ꢁ
50ꢁ
V
-VIN
VIN
VINA
CML
R
+5V
50ꢁ
50ꢁ
C
S
VINA
100pF
C
C
100pF
R
AD9260
R
AD8138
VIN
C
AD9260
F
C
D
50ꢁ
V
-VIN
CML
100pF
VINB
C
50ꢁ
F
499ꢁ
R
50ꢁ
C
499ꢁ
S
VINB
100pF
R
C
C
VREF
100pF
10ꢄF
0.1ꢄF
R
R
AD817
Figure 57. AD8138 Single-Ended Differential ADC Driver
CML
1.0ꢄF
0.1ꢄF
The second driver circuit, shown in Figure 58, can provide slightly
enhanced noise performance relative to the AD8138, assuming
low-noise, high-speed op amps are used. This differential op amp
driver circuit is configured to convert and level-shift a 2 V p-p
single-ended, ground-referenced signal to a 4 V p-p differential
signal centered at the common-mode level of the AD9260. The
circuit is based on two op amps that are configured as matched
unity gain difference amplifiers. The single-ended input signal is
applied to opposing inputs of the difference amplifiers, thus
providing differential outputs. The common-mode offset voltage
is applied to the noninverting resistor leg of each difference ampli-
fier providing the required offset voltage. This offset voltage is
derived from the common-mode level (CML) pin of the AD9260
via a low output impedance buffer amplifier capable of driving a
1 µF capacitive load. The common-mode offset can be varied
over a 1.8 V to 2.5 V span without any serious degradation in
distortion performance as shown in Figure 44, thus providing
some flexibility in improving output compression distortion from
some 5 op amps with limited positive voltage swing.
Figure 58. DC-Coupled Differential Driver with
Level-Shifting
beyond the input signals passband by adding a shunt capacitor,
CF, across each op amp’s feedback resistor. This will essentially
establish a low-pass filter which reduces the noise gain to one
beyond the filter’s f–3 dB while simultaneously bandlimiting the
input signal to f–3 dB. Note, the pole established by this filter can
also be used as the real pole of an antialiasing filter. Since the
noise contribution of two op amps from the same product family
are typically equal but uncorrelated, the total output-referred
noise of each op amp will add root-sum square leading to a
further 3 dB degradation in the circuit’s noise performance.
Further out-of-band noise reduction can be realized with the
addition of single-ended and differential capacitors, CS and CD.
The distortion and noise performance of the two op amps
within the signal path are critical in achieving the AD9260’s
optimum performance. Low noise op amps capable of providing
greater than 85 dB THD at 1 MHz while swinging over a 1 V to
3 V range are a rare commodity, yet should only be considered.
The AD9632 op amp was found to provide superb distortion
performance in this circuit due to its ability to maintain excel-
lent distortion performance over a wide bandwidth while swing-
ing over a 1 V to 3 V range. Since the AD9632 is gain-of-two or
greater stable, the use of the noise reduction shunt capacitors
discussed above was prohibited thus degrading its noise perfor-
mance slightly (1 dB–2 dB) when compared to the OPA642.
Note, the majority of the AD9260 test and characterization data
presented in this data sheet was taken using the AD9632 op
amp in this dc coupled driver circuit. This driver circuit is also
provided on the AD9260 evaluation board since the AD8138
was unreleased at that time.
To protect the AD9260 from an undervoltage fault condition
from op amps specified for 5 V operation, two 50 Ω series
resistors and a diode to AGND are inserted between each op
amp output and the AD9260 inputs. The AD9260 will inherently
be protected against any overvoltage condition if the op amps
share the same positive power supply (i.e., AVDD) as the AD9260.
Note, the gain accuracy and common-mode rejection of each dif-
ference amplifier in this driver circuit can be enhanced by using
a matched thin-film resistor network (i.e., Ohmtek ORNA5000F)
for the op amps. Resistor values should be 500 Ω or less to main-
tain the lowest possible noise.
The noise performance of each unity gain differential driver
circuit is limited by its inherent noise gain of two. For unity gain
op amps ONLY, the noise gain can be reduced from two to one
Table IV. Reference Configuration Summary
Reference
Operating Mode
Input Span (VINA–VINB)
(V p-p)
Required VREF
(V)
Connect
To
INTERNAL
INTERNAL
INTERNAL
1.6
4.0
1
2.5
SENSE
SENSE
R1
R2
SENSE
VREF
VREF
REFCOM
VREF and SENSE
SENSE and REFCOM
AVDD
1.6 ≤ SPAN ≤ 4.0 and
SPAN = 1.6 × VREF
1.6 ≤ SPAN ≤ 4.0
1 ≤ VREF ≤ 2.5 and
VREF = (1+R1/R2)
1 ≤ VREF ≤ 2.5
EXTERNAL
EXT. REF.
REV. B
–23–
AD9260
The outputs of each op amp are ac coupled via a small series
resistor and capacitor (i.e., 50 Ω and 0.1 µF) to the respective
inputs of the AD9260. Similar to the dc coupled driver, further
out-of-band noise reduction can be realized with the addition of
100 pF single-ended and differential capacitors, CS and CD.
The lower-cutoff frequency of this ac coupled circuit is deter-
mined by RC and CC in which RC is tied to the common-mode
level pin, CML, of the AD9260 for proper biasing of the inputs.
Although the OPA642 was found to provide the lowest overall
noise and distortion performance (i.e., 88.8 dB and 96 dB
THD @ 100 kHz), the AD8055 (or dual AD8056) suffered
only a 0.5 dB to 1.5 dB degradation in overall performance. It
is worth noting that given the high-level of performance attainable
by the AD9260, special consideration must be given to both the
quality of the test equipment and test setup in its evaluation.
TO A/D
5kꢁ
CAPT
CAPB
6.25kꢁ
A2
5kꢁ
6.25kꢁ
DISABLE
A2
LOGIC
+
–
VREF
A1
1V
7.5kꢁ
5kꢁ
AD9260
Common-Mode Level
SENSE
The CML pin is an internal analog bias point used internally by
the AD9260. This pin must be decoupled to analog ground
with at least a 0.1 µF capacitor as shown in Figure 59. The dc
level of CML is approximately AVDD/2.5. This voltage should
be buffered if it is to be used for any external biasing.
LOGIC
DISABLE
A1
REFCOM
Note: the common-mode voltage of the input signal applied to
the AD9260 need not be at the exact same level as CML. While
this level is recommended for optimal performance, the AD9260 is
tolerant of a range of input common-mode voltages around
AVDD/2.5.
Figure 60. Simplified Reference
controls the position of the switch within the feedback path of
A1. If the SENSE pin is tied to REFCOM, the switch is con-
nected to the internal resistor network, thus providing a VREF
of 2.5 V. If the SENSE pin is tied to the VREF pin via a short
or resistor, the switch is connected to the SENSE pin. A short
will provide a VREF of 1.0 V while an external resistor network
will provide an alternative VREF SPAN between 1.0 V and
2.5 V. The external resistor network may, for example, be
implemented as a resistor divider circuit. This divider circuit
could consist of a resistor (R1) connected between VREF and
SENSE and another resistor (R2) connected between SENSE
and REFCOM. The other comparator controls internal cir-
cuitry that will disable the reference amplifier if the SENSE pin
is tied to AVDD. Disabling the reference amplifier allows the
VREF pin to be driven by an external voltage reference.
CML
0.1ꢄF
AD9260
Figure 59. CML Decoupling
REFERENCE OPERATION
The AD9260 contains an onboard bandgap reference and inter-
nal reference buffer amplifier. The onboard reference provides a
pin-strappable option to generate either a 1 V or 2.5 V output.
With the addition of two external resistors, the user can generate
reference voltages other than 1 V and 2.5 V. Another alterna-
tive is to use an external reference for designs requiring en-
hanced accuracy and/or drift performance. See Table IV for a
summary of the pin-strapping options for the AD9260 reference
configurations. Note, the optimum noise and distortion can only be
achieved with a 2.5 V reference.
The reference buffer circuit, level shifts the reference to an
appropriate common-mode voltage for use by the internal cir-
cuitry. The on-chip buffer provides the low impedance neces-
sary for driving the internal switched capacitor circuits and
eliminates the need for an external buffer op amp.
Figure 60 shows a simplified model of the internal voltage refer-
ence of the AD9260. A pin-strappable reference amplifier
buffers a 1 V fixed reference. The output from the reference
amplifier, A1, appears on the VREF pin and MUST be de-
coupled with 0.1 µF and 10 µF capacitor to REFCOM. The
voltage on the VREF pin determines the full-scale input span of
the A/D. This input span equals:
The actual reference voltages used by the internal circuitry of
the AD9260 appear on the CAPT and CAPB pins. If VREF is
configured for 2.5 V, thus providing a 4 V full-scale input span,
the voltages appear at CAPT and CAPB are 3.0 V and 1.0 V
respectively. For proper operation when using the internal or an
external reference, it is necessary to add a capacitor network to
decouple the CAPT and CAPB pins. Figure 61 shows the rec-
ommended decoupling network. This capacitive network per-
forms the following three functions: (1) along with the reference
amplifier, A2, it provides a low source impedance over a large
frequency range to drive the A/D internal circuitry, (2) it pro-
vides the necessary compensation for A2, and (3) it bandlimits
the noise contribution from the reference. The turn-on time of
the reference voltage appearing between CAPT and CAPB is
approximately 15 ms and should be evaluated in any power-
down mode of operation.
Full-Scale Input Span = 1.6 × VREF
The voltage appearing at the VREF pin, as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators that monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
–24–
REV. B
AD9260
state. Table VI indicates the relationship between the CS and
READ pins and the state of Pins Bit 1–Bit 16.
AD9260
0.1ꢄF
10ꢄF
V
CAPT
REF
+
+
Table VI. CS and READ Pin Functionality
10ꢄF
0.1ꢄF
SENSE
0.1ꢄF
CS
READ
Condition of Data Output Pins
REFCOM
CAPB
0.1ꢄF
Low
Low
High
High
Low
High
Low
High
Data Output Pins in Hi-Z State
ADC Data on Output Pins
Data Output Pins in Hi-Z State
Data Output Pins in Hi-Z State
Figure 61. Recommended Reference Decoupling Network
DIGITAL INPUTS AND OUTPUTS
Digital Outputs
The AD9260 output data is presented in a twos complement
format. Table V indicates the output data formats for various
input ranges and decimation modes. A straight binary output
data format can be created by inverting the MSB.
DAV PIN
The DAV pin indicates when the output data of the AD9260 is
valid. Digital output data is updated on the rising edge of DAV.
The data hold time (tH) is dependent on the external loading of
DAV and the digital data output pins (BIT1–BIT16) as well as
the particular decimation mode. The internal DAV driver is
sized to be larger than the drivers pertaining to the digital data
outputs to ensure that rising edge of DAV occurs before the
data transitions under similar loading conditions (i.e., fanout)
regardless of mode. Note that minimum data hold (tH) of 3.5 ns
is specified in the Figure 4 timing diagram from the 50% point
of DAV’s rising edge to the 50% of data transition using a ca-
pacitive load of 20 pF for DAV and BIT1–BIT16. Applications
interfacing to TTL logic and/or having larger capacitive loading
for DAV than BIT1–BIT16 should consider latching data on
the falling edge of DAV since the falling edge of DAV occurs
well after the data has transitioned in the case of the 2×, 4× and
8× modes. The duty cycle of DAV is approximately 50% and it
remains active independent of CS and READ.
Table V. Output Data Format
Input (V)
Condition (V)
Digital Output
8ꢀ Decimation Mode
VINA–VINB < –0.8 × VREF
VINA–VINB = –0.8 × VREF
VINA–VINB = 0
VINA–VINB = +0.8 × VREF – 1 LSB
VINA–VINB >= + 0.8 × VREF
1000 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1111
4ꢀ Decimation Mode
VINA–VINB < –0.825 × VREF
VINA–VINB = –0.825 × VREF
VINA–VINB = 0
1000 0001 0001 1100
1000 0001 0000 1100
0000 0000 0000 0000
VINA–VINB = +0.825 × VREF – 1 LSB 0111 1110 1110 0011
VINA–VINB >= + 0.825 × VREF
0111 1110 1110 0011
RESET PIN
2ꢀ Decimation Mode
The RESET pin is an asynchronous digital input that is active
low. Upon asserting RESET low, the clocks in the digital deci-
mation filters are disabled, the DAV pin goes low and the data
on the digital output data pins (Bit 1–Bit 16) is invalid. In addi-
tion, the analog modulator in the AD9260 and internal clock
dividers used in the decimation filters are reset and will remain
reset as long as RESET is maintained low. In the 2×, 4×, or 8×
mode, the RESET must remain low for at least a clock period to
ensure all the clock dividers and analog modulator are reset.
Upon bringing RESET high, the internal clock dividers will
begin to count again on the next falling edge of CLK and DAV
will go high approximately 15 ns after this falling edge, resuming
normal operation. Refer to Figure 4b for a timing diagram.
VINA–VINB < –0.825 × VREF
VINA–VINB = –0.825 × VREF
VINA–VINB = 0
VINA–VINB = +0.825 × VREF – 1 LSB 0111 1111 1011 1110
VINA–VINB >= + 0.825 × VREF 0111 1111 1011 1110
1000 0000 0100 0001
1000 0000 0100 0001
0000 0000 0000 0000
The slight different full-scale input voltage conditions and
their corresponding digital output code for the 4× and 2× deci-
mation modes can be attributed to the different digital scaling
factors applied to each of the AD9260’s FIR decimation stages
for filter optimization purposes. Thus, a + full-scale reading of
0111 1111 1111 1111 and – full-scale reading of 1000 0000
0000 0000 is unachievable in the 2× and 4× decimation mode.
As a result, a digital overrange condition can never exist in the
2× and 4× decimation mode and thus OTR being set high indi-
cates an overrange condition in the analog modulator.
The state of the internal decimation filters in the AD9260
remains unchanged when RESET is asserted low. Conse-
quently, when RESET is pulsed low, this resets the analog
modulator but does not clear all the data in the digital filters.
The data in the filters is corrupted by the effect of resetting the
analog modulator (this causes an abrupt change at the input of
the digital filter and this change is unrelated to the signal at the
input of the A/D converter). Similarly, in multiplexed applica-
tions in which the input of the A/D converters sees an abrupt
change, the data in the analog modulator and digital filter will
be corrupted.
The output data format in 1× decimation differs from that in 2×,
4× and 8× decimation modes. In 1× decimation mode the out-
put data remains in a twos complement format, but the digital
numbers are scaled by a factor of 7/128. This factor of 7/128 is
the product of an internal scale factor of 7/8 in the analog modula-
tor and a 1/16 scale factor caused by LSB justification of the
12-bit modulator data.
CS AND READ PINS
For this reason, following a pulse on the RESET pin, or change
in channels (i.e., multiplexed applications only), the decimation
filters must be flushed of their data. These filters have a memory
length, hence delay, equal to the number of filter taps times
the clock rate of the converter. This memory length may be
The CS and READ pins control the state of the output data
pins (BIT1–BIT16) on the AD9260. The CS pin is active low
and the READ pin is active high. When CS and READ are
both active the ADC data is driven on the output data pins,
otherwise the output data pins are in a high-impedance (Hi-Z)
REV. B
–25–
AD9260
interpreted in terms of a number of samples stored in the
decimation filter. For example, if the part is in 8× decimation
mode, the delay is 321/fCLOCK. This corresponds to 321 samples
stored in the decimation filter. These 321 samples must be
flushed from the AD9260 after RESET is pulsed high prior to
reusing the data from the AD9260. That is, the AD9260 should
be allowed to clock for 321 samples as the corrupted data is
flushed from the filters. If the part is in 4× or 2× decimation
mode, then the relatively smaller group delays of the 4× and 2×
decimation filters result fewer samples that must be flushed
from the filters (108 samples and 23 samples respectively).
The second out-of-range detector is placed at the output of the
stage three decimation filter and detects whether the low pass
filtered data has exceeded full scale. When this occurs, the filter
output data is hard limited to full scale. The OTR signal is a
logical OR function of the signals from these two internal out-
of-range detectors. If either of these detectors produces an out-
of-range signal, the OTR pin goes high and the data may be
seriously corrupted.
If the AD9260 is used in a system that incorporates automatic
gain control (AGC), the OTR signal may be used to indicate
that the signal amplitude should be reduced. This may be par-
ticularly effective for use in maximizing the signal dynamic
range if the signal includes high-frequency components that
occasionally exceed full scale by a small amount. If, on the other
hand, the signal includes large amplitude low frequency compo-
nents that cause the digital filters to overrange, this may cause
the low pass digital filter to overrange. In this case the data may
become seriously corrupted and the digital filters may need to
be flushed. See the RESET pin function description above for
an explanation of the requirements for flushing the digital filters.
In 2×, 4× or 8× mode, RESET may be used to synchronize
multiple AD9260s clocked with the same clock. The decimation
filters in the AD9260 are clocked with an internal clock divider.
The state of this clock divider determines when the output data
becomes available (relative to CLK). In order to synchronize
multiple AD9260s clocked with the same clock, it is necessary
that the clock dividers in each of the individual AD9260s are
all reset to the same state. When RESET is asserted low, these
clock dividers are cleared. On the next falling edge of CLK follow-
ing the rising edge of RESET, the clock dividers begin counting
and the clock is applied to the digital decimation filters.
OTR should be sampled with the falling edge of CLK. This
signal is invalid while CLK is HIGH.
OTR PIN
MODE OPERATION
The OTR pin is a synchronous output that is updated each
CLK period. It indicates that an overrange condition has oc-
curred within the AD9260. Ideally, OTR should be latched on
the falling edge of CLK to ensure proper setup-and-hold time.
However, since an overrange condition typically extends well
beyond one clock cycle (i.e., does not toggle at the CLK rate).
OTR typically remains high for more than a clock cycle, allow-
ing it to be successfully detected on the rising edge of CLK or
monitored asynchronously.
The Mode Select Pin (MODE) allows the user to select one of
four available digital filter modes using a single pin. Each mode
configures the internal decimation filter to decimate at: 1×, 2×,
4× or 8×. Refer to Table VII for mode pin ranges.
The mode selection is performed by using a set of internal com-
parators, as illustrated in Figure 62, so that each mode corre-
sponds to a voltage range on the input of the MODE pin. The
output of the comparators are fed into encoding logic where, on
the falling edge of the clock, the encoded data is latched.
An overrange condition must be carefully handled because of
the group delays in the low-pass digital decimation filters in the
output stages of the AD9260. When the input signal exceeds
the full-scale range of the converter, this can have a variety of
effects upon the operation of the AD9260, depending on the
duration and amplitude of this overrange condition. A short
duration overrange condition (<< filter group delay) may cause
the analog modulator to briefly overrange without causing the
data in the low pass digital filters to exceed full scale. The ana-
log modulator is actually capable of processing signals slightly
(3%) beyond the full-scale range of the AD9260 without inter-
nally clipping. A long duration overrange condition will cause
the digital filter data to exceed full scale. For this reason, the
OTR signal is generated using two separate internal out-of-
range detectors.
Table VII. Recommended Mode Pin Ranges and Configurations
Mode Pin
Range
Typical
Mode Pin
Decimation
Mode
0 V–0.5 V
GND
VREF/2
CML
AVDD
8×
2×
4×
1×
0.5 V–1.5 V
1.5 V–3.0 V
3.0 V–5.0 V
BIAS PIN OPERATION
The Bias Select Pin (BIAS) gives the user, who is able to oper-
ate the AD9260 at a slower clock rate, the added flexibility of
running the device in a lower, power consumption mode when it
is clocked at less than 20 MHz.
The first of these out-of-range detectors is placed at the output
of the analog modulator and indicates whether the modulator
output signal has extended 3% beyond the full-scale range of
the converter. If the modulator output signal exceeds 3% be-
yond full scale, the digital data is hard-limited (i.e., clipped) to a
number that is 3% larger than full scale. Due to the delay of the
switched capacitor analog modulator, the OTR signal is delayed
3 1/2 clock cycles relative to the clock edge in which the over-
ranged analog input signal was sampled.
This is accomplished by scaling the bias current of the AD9260
as illustrated in Figure 63. The bias amplifier drives a source
follower and forces 1 V across REXT, which sets the bias current.
This effectively adjusts the bias current in the modulator ampli-
fiers and FLASH preamplifiers. When a large value of REXT is
used, a smaller bias current is available to the internal amplifier
circuitry. As a result these amplifiers need more time to settle,
thus dictating the use of a slower clock as the power is reduced.
Refer to the characterization curves shown in Figures 41–48
revealing the performance tradeoffs.
–26–
REV. B
AD9260
The scaling is accomplished by properly attaching an external
resistor to the BIAS pin of the AD9260 as shown in Table IX.
130
110
FULL BIAS-2kꢁ
R
EXT is normally 2 kΩ for a clock speed of 20 MHz and scales
inversely with clock rate. Because BIAS is an external pin, mini-
mization of capacitance to this pin is recommended in order to
prevent instability of the bias pin amplifier.
90
70
HALF BIAS-4kꢁ
AVDD
4R
50
30
QUARTER BIAS-8kꢁ
3R
MODE PIN
5
10
15
20
SAMPLE RATE – MSPS
ENCODED MODE
LATCH
CLOCK
Figure 64. IAVDD vs. Sample Rate (AVDD = +5 V,
Mode 1×–4×)
2R
16
8ꢀ
4ꢀ
14
R
12
1ꢀ
AVSS
10
2ꢀ
Figure 62. Simplified Mode Pin Circuitry
8
6
4
2
0
BIAS CURRENT
1V
5
10
15
20
BIAS PIN
REXT
SAMPLE RATE – MSPS
Figure 65a. IDVDD/IDRVDD vs. Sample Rate (DVDD = DRVDD =
3 V, fIN = 1 MHz)
Figure 63. Simplified Bias Pin Circuitry
30
8ꢀ
4ꢀ
POWER DISSIPATION CONSIDERATIONS
25
The power dissipation of the AD9260 is dependent on its
application-specific configuration and operating conditions.
The analog power dissipation as shown in Figure 64 is primarily
a function of its power bias setting and sample rate. It remains
insensitive to the particular input waveform being digitized or
digital filter MODE setting. The digital power dissipation is
primarily a function of the digital supply setting (i.e., +3 V to
+5 V), the sample rate and, to a lesser extent, the MODE setting
and input waveform. Figures 65a and 65b show the total current
dissipation of the “combined” digital (DVDD) and digital driver
supply (DRVDD) for +3 V and +5 V supplies. Note, DVDD
and DRVDD are typically derived from the same supply bus
since no degradation in performance results. A 1 MHz full-
scale sine wave was used to ensure maximum digital activity in
the digital filters and the digital drivers had a fanout of one.
Note also that a twofold decrease in digital supply current re-
sults when the digital supply is reduced form +5 V to +3 V.
20
1ꢀ
15
2ꢀ
10
5
0
5
10
15
20
SAMPLE RATE – MSPS
Figure 65b. IDVDD/IDRVDD vs. Sample Rate (DVDD = DRVDD
= 5 V, fIN = 1 MHz)
REV. B
–27–
AD9260
Digital Output Driver Considerations (DRVDD)
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
The AD9260 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V
respectively. The AD9260 output drivers in each mode are
appropriately sized to provide sufficient output current to drive
a wide variety of logic families. However, large drive currents
tend to cause glitches on the supplies and may affect SINAD
performance. Applications requiring the AD9260 to drive large
capacitive loads or large fanout may require additional decou-
pling capacitors on DRVDD. The addition of external buffers or
latches helps reduce output loading while providing effective
isolation from the databus.
It is important to design a layout that prevents noise from coupling
onto the input signal. Digital signals should not be run in parallel
with input signal traces and should be routed away from the
input circuitry. While the AD9260 features separate analog and
digital ground pins, it should be treated as an analog component.
The AVSS, DVSS and DRVSS pins must be joined together directly
under the AD9260. A solid ground plane under the A/D is ac-
ceptable if the power and ground return currents are man-
aged carefully. Alternatively, the ground plane under the A/D
may contain serrations to steer currents in predictable directions
where cross-coupling between analog and digital would other-
wise be unavoidable. The AD9260/EB ground layout, shown in
Figure 76, depicts the serrated type of arrangement. The analog
and digital grounds are connected by a jumper below the A/D.
Clock Input and Considerations
The AD9260 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulse width
high and low (tCH and tCL) specifications for the given A/D as
defined in the Switching Specifications at the beginning of the
data sheet to meet the rated performance specifications. For
example, the clock input to the AD9260 operating at 20 MSPS
may have a duty cycle between 45% to 55% to meet this timing
requirement since the minimum specified tCH and tCL is 22.5 ns.
For clock rates below 20 MSPS, the duty cycle may deviate from
this range to the extent that both tCH and tCL are satisfied.
Analog and Digital Supply Decoupling
The AD9260 features separate analog, digital, and driver supply
and ground pins, helping to minimize digital corruption of sen-
sitive analog signals.
Figure 66 shows the power supply rejection ratio vs. frequency
for a 200 mV p-p ripple applied to AVDD, DVDD, and DAVDD.
All high-speed high-resolution A/Ds are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fIN) due to only aperture jitter (tA) can be calcu-
lated with the following equation:
90
85
DVDD & DRVDD
80
SNR = 20 log10 [1/(2 π fIN tA)]
75
70
65
60
In the equation, the rms aperture jitter, tA, represents the root-
sum square of all the jitter sources which include the clock input,
analog input signal, and A/D aperture jitter specification. For
example, if a 500 kHz full-scale sine wave is sampled by an A/D
with a total rms jitter of 15 ps, the SNR performance of the A/D
will be limited to 86.5 dB.
55
AVDD
50
45
40
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9260. In fact, the CLK input buffer is internally powered
from the AD9260’s analog supply, AVDD. Thus the CLK logic
high and low input voltage levels are +3.5 V and +1.0 V, respec-
tively. Supplies for clock drivers should be separated from the
A/D output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or other method), it should be
retimed by the original clock at the last step.
1000
1
10
100
10000
FREQUENCY – kHz
Figure 66. AD9260 PSRR vs. Frequency (8 × Mode)
In general, AVDD, the analog supply, should be decoupled to
AVSS, the analog common, as close to the chip as physically
possible. Figure 67 shows the recommended decoupling for the
analog supplies; 0.1 µF ceramic chip capacitors should provide
adequately low impedance over a wide frequency range. Note
that the AVDD and AVSS pins are co-located on the AD9260
GROUNDING AND DECOUPLING
Analog and Digital Grounding
4
3
AVDD
AVSS
AVDD 44
AVSS 38
Proper grounding is essential in any high-speed, high-resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
0.1ꢄF
0.1ꢄF
0.1ꢄF
AD9260
AVDD
28
29
1. The minimization of the loop area encompassed by a signal
and its return path.
AVSS
2. The minimization of the impedance associated with ground
and power paths.
Figure 67. Analog Supply Decoupling
3. The inherent distributed capacitor formed by the power plane,
PCB insulation, and ground plane.
–28–
REV. B
AD9260
to simplify the layout of the decoupling capacitors and provide
the shortest possible PCB trace lengths. The AD9260/EB power
plane layout, shown in Figure 77 depicts a typical arrangement
using a multilayer PCB.
Speed Design Techniques seminar book, which is available at
www.analog.com/support/frames/lin_frameset.hml.
INSERT 5/3 VOLT LINEAR REGULATOR
FOR 3 OR 3.3V DIGITAL OPERATION
FERRITE
The digital activity on the AD9260 chip falls into two general
categories: digital logic, and output drivers. The internal digital
logic draws surges of current, mainly during the clock transi-
tions. The output drivers draw large current impulses while the
output bits are changing. The size and duration of these cur-
rents are a function of the load on the output bits: large capaci-
tive loads are to be avoided. Note that the digital logic of the
AD9260 is referenced DVDD while the output drivers are refer-
enced to DRVDD. Also note that the SNR performance of the
AD9260 remains independent of the digital or driver supply
setting.
BEAD CORE*
V
A
10ꢄF
DVDD
DVSS
DRVDD
DRVSS
0.1ꢄF
0.1ꢄF
V
D
AD9260
AVDD
0.1ꢄF
0.1ꢄF
0.1ꢄF
AVSS
BITS 1–16,
DAV
BUFFER
LATCH
AVDD
AVSS
The decoupling shown in Figure 68, a 0.1 µF ceramic chip
capacitor, is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications
involving greater digital loads should consider increasing the
digital decoupling proportionally, and/or using external buffers/
latches.
CLK
AVDD
AVSS
DVDD
3
1
DRVDD
DRVSS
6
5
SAMPLING CLOCK
GENERATOR
0.1ꢄF
0.1ꢄF
AD9260
DVSS
Figure 69.
Figure 68. Digital Supply Decoupling
AD9260 EVALUATION BOARD
GENERAL DESCRIPTION
The AD9260 Evaluation Board is designed to provide an easy
and flexible method of exercising the AD9260 and demonstrate
its performance to data sheet specifications. The evaluation
board is fabricated in four layers: the component layer; the
ground layer; the power layer and the solder layer. The board is
clearly labeled to provide easy identification of components.
Ample space is provided near the analog and clock inputs to
provide additional or alternate signal conditioning.
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low-frequency
ripple to negligible levels. Refer to the AD9260/EB schematic
and layouts in Figures 73–77 for more information regarding the
placement of decoupling capacitors.
An alternative layout and decoupling scheme is shown in Figure
69. This layout and decoupling scheme is well suited for appli-
cations in which multiple AD9260s are located on the same PC
board and/or the AD9260 is part of a multicard mixed signal
system in which grounds are tied back at the system supplies
(i.e., star ground configuration). In this case, the AD9260 is
treated as an analog component in which its analog (i.e.,
AVDD) and digital (DVDD and DRVDD) supplies are derived
from the systems +5 V analog supply and all of the AD9260’s
ground pins are tied directly to the analog ground plane which
resides directly underneath the IC.
FEATURES AND USER CONTROL
•
Jumper Controlled Mode/OSR Selection: The choice of
Mode/OSR can easily be varied by jumping either JP1,
JP2, JP3 or JP4 as illustrated in Figure 71 within the
Mode/OSR Control Block. To obtain the desired mode
refer to Table VIII.
Referring to Figure 69, each supply pin is directly decoupled to
their respective ground pin or analog ground plane via a ceramic
0.1 µF chip capacitor. Surface mount ferrite beads are used to
isolate the analog (AVDD), digital (DVDD), and driver supplies
(DRVDD) of the AD9260 from the +5 V power buss. Properly
selected ferrite beads can provide more than 40 dB of isolation
from high-frequency switching transients originating from AD9260
supply pins. Further noise immunity from noise is provided by
the inherent power-supply rejection of the AD9260 as shown in
Figure 64. If digital operation at 3 V is desirable for power sav-
ings and or to provide for a 3 V digital logic interface, a 5 V to
3 V linear regulator can be used to drive DVDD and/or DRVDD.
A more complete discussion on this layout and decoupling scheme
can be found in Chapter 7, pages 7-27 through 7-55 of the High
Table VIII. AD9260 Evaluation Board Mode Select
Mode/OSR
Connect Jumper
1×
2×
4×
8×
JP4
JP2
JP3
JP1
•
Selectable Power Bias: The power consumption of the
AD9260 can be scaled down if the user is able to operate the
device at a lower clock frequency. As illustrated in Figure 71,
pin cups are provided for the external resistor (R2) tied to
the BIAS pin of the AD9260. Table IX defines the recom-
mended resistance for a given clock speed to obtain the de-
sired power consumption.
REV. B
–29–
AD9260
U5
8
7
6
5
1
2
NC
+VIN
2.5/3V
NC
VCC2
AD780R
R10
1kꢁ
3
4
TEMP
GNDS
1KPOT
VOUT
TRIM
C18
0.1ꢄF
C19
0.1ꢄF
AGND
C14
0.1ꢄF
R3
R12
VREFEXT
JP10
15kꢁ 15kꢁ
+
C12
0.1ꢄF
C13
10ꢄF
Q1
2N2222
R11
49.9ꢁ
AD817R
R9
1kꢁ
1V
U6
R8
390ꢁ
+
R4
R13
C17
10kꢁ 10kꢁ
10ꢄF
C15
0.1ꢄF
AGND
VCC2
AGND
Figure 70. Evaluation Board External Reference Circuitry
Table IX. Evaluation Board Recommended Resistance Value
for External Bias Resistor
The external reference circuitry, is illustrated in Figure 70. By
connecting or disconnecting JP10, the external reference can be
configured for either 1.0 V or 2.5 V. That is, by connecting JP10,
the external reference will be configured to provide a 2.5 V
reference. By leaving JP10 open, the external reference will be
configured to provide a 1.0 V reference.
Resistor
Value
Clock Speed
(max)
Power
Consumption
2 kΩ
4 kΩ
8 kΩ
16 kΩ
20 MHz
10 MHz
5 MHz
585 mW
325 mW
200 mW
150 mW
•
Flexible DC or AC Coupled External Clock Inputs: As
illustrated in Figure 71, the AD9260 Evaluation Board is
designed to allow the user the flexibility of selecting how to
connect the external clock source. It is also equipped with a
playpen area for experimenting with optional clock drivers or
crystals.
2.5 MHz
•
Data Interfacing Controls: The data interfacing controls
(RESETB, CSB, READ, DAV) are all accessible via SMA
connectors (J2–J5) as illustrated in Figure 71 within the data
interfacing control block. The RESETB, CSB and READ
connections are each supplied with two sets or resistor pin
cups to allow the user to pull-up or pull-down each signal to
a fixed state. R5, R6 and R30 will terminate to ground, while
R7, R28 and R29 terminate to DRVDD. The DAV and
OTR signals are also directly connected to the data output
connector P1. All interfacing controls are buffered through
the CMOS line driver 74HC541.
•
Selecting DC or AC Coupled External Clock:
DC Coupled: To directly drive the clock externally via the
CLKIN connector, connect JP11 and disconnect JP12. Note:
50 Ω terminated by R27.
AC Coupled: To ac couple the external clock and level shift it
to midsupply, connect JP12 and disconnect JP11. Note: 50 Ω
terminated by R27.
•
Flexible Input Signal Configuration Circuitry: The
AD9260 Evaluation Board’s Input Signal Configuration Block
is illustrated in Figure 72. It is comprised of an input signal
summing amplifier (U7), a variable input signal common-
mode generator (U10) and a pair of amplifiers (U8 and U9)
that configure the input into a differential signal and drive it,
through a pair of isolation resistors, into the input pins of
AD9260. The user can either input a signal or dual signal
into the evaluation board via the two SMA connectors (J6 and
J7) labeled IN-1 or IN-2.
•
•
Buffered Output Data: The twos complement output data
is buffered through two CMOS noninverting bus transceivers
(U2 and U3) and made available at pin connector P1 as
illustrated in Figure 71 within the data output block.
Jumper Controlled Reference Source: The choice of
reference for the AD9260 can easily be varied between 1.0 V,
2.5 V or external, by using Jumpers JP5, JP6, JP7 and JP9 as
illustrated in Figure 71 within the reference configuration
block. To obtain the desired reference see Table X.
The user should refer to the Driving the Input section of the data
sheet for a detailed explanation of how the inputs are to be driven
and what amplifier requirements are recommended.
Table X. Evaluation Board Reference Pin Configuration
Reference
Voltage
Input Voltage
(pk-pk FS)
•
Selecting Single or Dual Signal Input: The input ampli-
fier (U7) can either be configured as a dual input signal
inverting summer or a single tone inverting buffer. This
flexibility will allow for slightly better noise performance in
the single tone mode due to the inherent noise gain differ-
ence in the two amplifier configurations. An optional feed-
back capacitor (C9) was added to allow the user additional
out-of band filtering of the input signal if needed.
Connect Jumper
2.5 V
1.0 V
External
JP7
JP6
4.0 V
1.6 V
4.0 V
JP5, JP9 and JP10
–30–
REV. B
AD9260
For two-tone input signals: The user would leave jumpers (JP8)
connected and use IN-1 and IN-2 (J7 and J6) as the connec-
tors for the input signals.
3. Bandpass filtering of test signal generators is absolutely
necessary for SNR, THD and IMD tests. Note, a low noise
signal generator along with a high Q bandpass filter is often
necessary to achieve the attainable noise performance of the
AD9260.
For signal tone input signal: The user would remove jumper
(JP8) and use only IN-1 as the input signal connector.
4. Test signal generators must have exceptional noise perfor-
mance to achieve accurate SNR measurements. Good gen-
erators, together with fifth-order elliptical bandpass filters,
are recommended for SNR tests. Narrow bandwidth crystal
filters can also be used to filter generator broadband noise,
but they should be carefully tested for operation at high-
signal levels.
•
Selectable Input Signal Common-Mode Level Source:
The input signal’s common-mode level (CML) can be set by
U10.
To use the Input CML generated by U10: Disconnect jumper
JP13 and Connect resistors RX3 and RX4. The CML gener-
ated by U10 is variable and adjustable using the 1 kΩ
trimpot R35.
5. The analog inputs of the AD9260 should be terminated
directly at the input pin sockets with the correct filter termi-
nating impedance (50 Ω or 75 Ω), or it should be driven by
a low output impedance buffer. Short leads are necessary to
prevent digital noise pickup.
SHIPMENT CONFIGURATION AND QUICK SETUP
•
The AD9260 Evaluation Board is configured as follows when
shipped:
1. 2.5 V external reference/4.0 V differential full-scale input:
JP5, JP9 and JP10 connected, JP6 and JP7 disconnected.
6. A low noise (jitter) clock signal generator is required for
good ADC dynamic performance. A poor generator can
seriously impair good SNR performance particularly at
higher input frequencies. A high-frequency generator, based
on a clock source (e.g., crystal source), is recommended.
Frequency-synthesized clock generators should generally be
avoided because they typically provide poor jitter perfor-
mance. See Note 8 if a crystal-based clock generator is used
during FFT testing.
2. 8× Mode/OSR: JP1 connected, JP2, JP3, and JP4
disconnected.
3. Full Speed Power Bias: R2 = 2 kΩ and connected.
4. CSB pulled low: R6 = 49.9 Ω and connected, R29
disconnected.
5. RESETB pulled high: R7 = 10 kΩ and connected, R30 dis-
connected.
A low jitter clock may be generated by using a high-frequency
clock source and dividing this frequency down with a low noise
clock divider to obtain the AD9260 input CLK. Maintaining a
large amplitude clock signal may also be very beneficial in mini-
mizing the effects of noise in the digital gates of the clock gen-
eration circuitry.
6. READ pulled high: R28 = 10 kΩ and connected, R5
disconnected.
7. Single Tone Input: JP8 removed, input applied via IN-1 (J7).
8. Input signal common-mode level set by Trimpot R35 to
2.0 V: Jumper JP12 is disconnected and resistors Rx4 and
Rx3 are connected.
Finally, special care should be taken to avoid coupling noise
into any digital gates preceding the AD9260 CLK pin. Short
leads are necessary to preserve fast rise times and careful decou-
pling should be used with these digital gates and the supplies
for these digital gates should be connected to the same supplies
as that of the internal AD9260 clock circuitry (Pins 44 and 38).
9. AC Coupled Clock: JP12 connected and JP11 disconnected.
Note: 50 Ω terminated by R27.
QUICK SETUP
1. Connect the required power supplies to the Evaluation
Board as illustrated in Figure 22:
7. Two-tone testing will require isolation between test signal
generators to prevent IMD generation in the test generator
output circuits.
⇒
5 VA supplies to P5—Analog Power
⇒ +5 VA supply to P4—Analog Power
⇒ +5 VD supply to P3—Digital Power
⇒ +5 VD supply to P2—Driver Power
8. A very low side-lobe window must be used for FFT calcula-
tions if generators cannot be phase-locked and set to exact
frequencies.
2. Connect a Clock Source to CLKIN (J1): Note: 50 Ω termi-
nated by R1.
9. A well designed, clean PC board layout will assure proper
operation and clean spectral response. Proper grounding
and bypassing, short lead lengths, separation of analog and
digital signals, and the use of ground planes are particularly
important for high-frequency circuits. Multilayer PC boards
are recommended for best performance, but if carefully
designed, a two-sided PC board with large heavy (20 oz.
foil) ground planes can give excellent results.
3. Connect an Input Signal Source to the IN-1 (J7).
4. Turn On Power!
5. The AD9260 Evaluation Board is now ready for use.
APPLICATION TIPS
1. The ADC analog input should not be overdriven. Using a
signal amplitude slightly lower than FSR will allow a
small amount of “headroom” so that noise or DC offset
voltage will not overrange the ADC and “hard limit” on
signal peaks.
10. Prototype “plug-boards” or wire-wrap boards will not be
satisfactory.
2. Two-tone tests can produce signal envelopes that exceed
FSR. Set each test signal to slightly less than –6 dB to pre-
vent “hard limiting” on peaks.
REV. B
–31–
AD9260
B I T 0 2
B I T 1 4
B I T 0 1 ( M S B )
B I T 1 5
O T R
D A V
C S
B I T 1 6 ( L S B )
R E A D
C L K
D R V D D
D R V S S
A V D D
D V D D
A V S S
R D
S H I E L D E D _ T R A C E
M D A V D D
A V D D
A V S S
R E S E T
S E N S E
V R E F
R E F C O M
F L A V D D
D V D D
D V S S
Figure 71. Evaluation Board Top Level Schematic
–32–
REV. B
AD9260
R18
390ꢁ
C20
0.1ꢄF
VCC2
8
C9
TBD
R19
390ꢁ
U8
6
R21
390ꢁ
R22
3
2
J6
J7
7
JP8
390ꢁ
AD9632
5
IN-2
IN-1
4
VEE
R1
R17
390ꢁ
57.6ꢁ
C16
100pF
R16
390ꢁ
5
U7
6
2
3
4
7
VEE
R20
390ꢁ
R47
R46
50ꢁ
AD9632
8
R15
57.6ꢁ
JP16
JP17
50ꢁ
VINA
VINB
R14
50ꢁ
VCC2
8
R23
C24
100pF
390ꢁ
VCC2
R48
50ꢁ
R49
50ꢁ
U9
6
3
2
7
AD9632
5
4
R24
390ꢁ
C26
100pF
R32
390ꢁ
VEE
R25
390ꢁ
R26
390ꢁ
VCC2
7
CX4
XXX
R34
390ꢁ
RX4
XXX
U10
2
JP12
IKPOT
R35
RX3
XXX
6
9260CML
AD817R
4
3
1kꢁ
C25
0.1ꢄF
+
C23
10ꢄF
C22
0.1ꢄF
Figure 72. Evaluation Board Input Configuration Block
L3
L6
R41
R43
R45
R51
1
1
FLAVDD
P5:+5AUX
VCC2
P4:+5V
R40
R50
+
+
+
+
C36
10ꢄF
C38
0.1ꢄF
C39
0.01ꢄF
C27
47ꢄF
C37
0.1ꢄF
C55
0.1ꢄF
2
1
P5
L7
R53
L4
P5:–5AUX
VEE
MDAVDD
R52
+
C56
47ꢄF
R42
C40
10ꢄF
C42
0.1ꢄF
C43
0.01ꢄF
C57
0.1ꢄF
C41
0.1ꢄF
2
1
P5
L2
R37
P2:VDD
DRVDD
L5
INVDD
R36
+
C28
47ꢄF
R44
C44
10ꢄF
C46
0.1ꢄF
C47
C29
0.1ꢄF
0.01ꢄF
2
C45
0.1ꢄF
P2
2
1
2
P4
VCC2
L2
VEE
VEE
VEE
VCC2
VCC2
R39
P3:D5
DVDD
R38
C48
0.1ꢄF
C49
0.1ꢄF
C50
0.1ꢄF
+
C30
0.1ꢄF
C31
0.1ꢄF
C64
0.1ꢄF
C32
22ꢄF
C34
0.1ꢄF
C35
0.01ꢄF
C33
0.1ꢄF
U7
DRVDD
U8
U9
U7
VCC2
U8
DRVDD
U9
DRVDD
P3
EVALUATION BOARD POWER SUPPLY CONFIGURATION
C51
0.1ꢄF
C52
0.1ꢄF
C53
0.1ꢄF
C54
0.1ꢄF
U10
U2
U3
U4
DEVICE SUPPLY DECOUPLING
Figure 73. Evaluation Board Power Supply Configuration and Coupling
–33–
REV. B
AD9260
Figure 74. Evaluation Board Component Side Layout (Not to Scale)
Figure 75. Evaluation Board Solder Side Layout (Not to Scale)
–34–
REV. B
AD9260
Figure 76. Evaluation Board Ground Plane Layout (Not to Scale)
Figure 77. Evaluation Board Power Plane Layout (Not to Scale)
–35–
REV. B
AD9260
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches).
44-Lead MQFP
(S-44)
13.45 (0.529)
12.95 (0.510)
2.45 (0.096)
10.1 (0.398)
MAX
9.90 (0.390)
1.03 (0.041)
0.73 (0.029)
0
°
44
34
MIN
1
33
SEATING
PLANE
8.45 (0.333)
8.3 (0.327)
TOP VIEW
(PINS DOWN)
11
23
0.25 (0.01)
MIN
12
22
0.23 (0.009)
0.13 (0.005)
0.8 (0.031)
BSC
0.45 (0.018)
0.3 (0.012)
2.1 (0.083)
1.95 (0.077)
–36–
REV. B
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