AD9268-125EBZ [ADI]
1.8 V Dual Analog-to-Digital Converter (ADC);型号: | AD9268-125EBZ |
厂家: | ADI |
描述: | 1.8 V Dual Analog-to-Digital Converter (ADC) |
文件: | 总45页 (文件大小:2071K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9268
FUNCTIONAL BLOCK DIAGRAM
FEATURES
SDIO/ SCLK/
SNR = 78.2 dBFS @ 70 MHz and 125 MSPS
SFDR = 88 dBc @ 70 MHz and 125 MSPS
Low power: 750 mW @ 125 MSPS
AVDD
CSB
DRVDD
DCS
DFS
SPI
AD9268
1.8 V analog supply operation
ORA
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−153.6 dBm/Hz small-signal input noise with 200 Ω input
impedance @ 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
PROGRAMMING DATA
CMOS/LVDS
D15A (MSB)
TO
D0A (LSB)
VIN+A
VIN–A
16
ADC
OUTPUT BUFFER
CLK+
CLK–
DIVIDE 1
TO 8
VREF
SENSE
DCOA
DCOB
DUTY CYCLE
STABILIZER
DCO
GENERATION
REF
SELECT
VCM
RBIAS
VIN–B
VIN+B
ORB
D15B (MSB)
TO
D0B (LSB)
16
CMOS/LVDS
OUTPUT BUFFER
ADC
95 dB channel isolation/crosstalk
Serial port control
MULTICHIP
SYNC
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
AGND
SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FORLVDS PIN NAMES.
APPLICATIONS
Figure 1.
Communications
Diversity radio systems
PRODUCT HIGHLIGHTS
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
5. Pin compatibility with the AD9258, allowing a simple
migration from 16 bits to 14 bits. The AD9268 is also pin
compatible with the AD9251, AD9231, and AD9204 family
of products for lower sample rate, low power applications.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
AD9268* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/27/2017
COMPARABLE PARTS
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TOOLS AND SIMULATIONS
• Visual Analog
• AD9268 IBIS Models
EVALUATION KITS
REFERENCE DESIGNS
• CN0171
• AD9268 Evaluation Board
DOCUMENTATION
REFERENCE MATERIALS
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
Solutions Bulletins & Brochures
• AN-1211: Powering the AD9268 Dual Channel 16-Bit, 125
MSPS Analog-to-Digital Converter with the ADP2114
Synchronous Step-Down DC-to-DC Regulator for
Increased Efficiency
• Test & Instrumentation Solutions Bulletin, Volume 10,
Issue 3
Technical Articles
• Improve The Design Of Your Passive Wideband ADC
Front-End Network
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-742: Frequency Domain Response of Switched-
Capacitor ADCs
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
DESIGN RESOURCES
• AD9268 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AN-878: High Speed ADC SPI Control Software
DISCUSSIONS
• AN-905: Visual Analog Converter Evaluation Tool Version
View all AD9268 EngineerZone Discussions.
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
SAMPLE AND BUY
Data Sheet
Visit the product page to see pricing options.
• AD9268: 16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC) Data Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
User Guides
• UG-003: Evaluating the AD9650/AD9268/AD9258/
AD9251/AD9231/AD9204 Analog-to-Digital Converters
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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AD9268
TABLE OF CONTENTS
Features .............................................................................................. 1
Clock Input Considerations...................................................... 30
Channel/Chip Synchronization................................................ 31
Power Dissipation and Standby Mode .................................... 32
Digital Outputs ........................................................................... 32
Timing ......................................................................................... 33
Built-In Self-Test (BIST) and Output Test .................................. 34
Built-In Self-Test (BIST)............................................................ 34
Output Test Modes..................................................................... 34
Serial Port Interface (SPI).............................................................. 35
Configuration Using the SPI..................................................... 35
Hardware Interface..................................................................... 36
Configuration Without the SPI ................................................ 36
SPI Accessible Features.............................................................. 36
Memory Map .................................................................................. 37
Reading the Memory Map Register Table............................... 37
Memory Map Register Table..................................................... 38
Memory Map Register Descriptions........................................ 40
Applications Information.............................................................. 41
Design Guidelines ...................................................................... 41
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
ADC DC Specifications............................................................... 4
ADC AC Specifications ................................................................. 6
Digital Specifications ................................................................... 7
Switching Specifications ................................................................ 9
Timing Specifications ................................................................ 10
Absolute Maximum Ratings.......................................................... 12
Thermal Characteristics ............................................................ 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 17
Equivalent Circuits......................................................................... 25
Theory of Operation ...................................................................... 26
ADC Architecture ...................................................................... 26
Analog Input Considerations.................................................... 26
Voltage Reference ....................................................................... 29
REVISION HISTORY
9/09—Rev. 0 to Rev. A
Changes to Features List.................................................................. 1
Changes to Specifications Section.................................................. 4
Changes to Table 5.......................................................................... 10
Changes to Typical Performance Characteristics Section......... 17
5/09—Revision 0: Initial Version
Rev. A | Page 2 of 44
AD9268
GENERAL DESCRIPTION
The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS
analog-to-digital converter (ADC). The AD9268 is designed to
support communications applications where high performance,
combined with low cost, small size, and versatility, is desired.
The ADC output data can be routed directly to the two external
16-bit output ports. These outputs can be set to either 1.8 V
CMOS or LVDS.
Flexible power-down options allow significant power savings,
when desired.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases design consid-
erations. A duty cycle stabilizer is provided to compensate for
variations in the ADC clock duty cycle, allowing the converters
to maintain excellent performance.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The AD9268 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
Rev. A | Page 3 of 44
AD9268
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 1.
AD9268BCPZ-80
Temperature Min Typ
AD9268BCPZ-105
Max Min Typ Max Min Typ
16 16
AD9268BCPZ-125
Parameter
Max
Unit
RESOLUTION
ACCURACY
Full
16
Bits
No Missing Codes
Offset Error
Gain Error
Full
Full
Full
Full
Guaranteed
±±.2
±±.4
Guaranteed
±±.2
±±.4
Guaranteed
±±.4
±±.4
±±.4
±2.ꢀ
+1.4 −1.±
±±.ꢀ
±2.ꢀ
+1.3 −1.±
±±.6ꢀ % FSR
±2.ꢀ
+1.2
% FSR
LSB
Differential
−1.±
Nonlinearity (DNL)1
2ꢀ°C
±±.6ꢀ
±2.±
±±.ꢁ
±3.±
±±.ꢁ
±3.±
LSB
LSB
Integral Nonlinearity Full
(INL)1
±4.ꢀ
±ꢀ.1
±ꢀ.ꢀ
2ꢀ°C
LSB
MATCHING
CHARACTERISTIC
Offset Error
Gain Error
Full
Full
±±.1
±±.3
±±.4
±1.3
±±.1
±±.3
±±.4
±1.3
±±.2
±±.3
±±.4ꢀ % FSR
±1.3
% FSR
TEMPERATURE DRIFT
Offset Error
Gain Error
Full
Full
±2
±1ꢀ
±2
±1ꢀ
±2
±1ꢀ
ppm/°C
ppm/°C
INTERNAL VOLTAGE
REFERENCE
Output Voltage Error Full
(1 V Mode)
±ꢀ
ꢀ
±12
±ꢀ
ꢀ
±12
±ꢀ
ꢀ
±12
mV
mV
Load Regulation @
1.± mA
Full
INPUT REFERRED NOISE
VREF = 1.± V
2ꢀ°C
Full
2.1ꢁ
2
2.23
2
2.2ꢁ
2
LSB
rms
ANALOG INPUT
Input Span, VREF =
1.± V
Input Capacitance2
Input Common-
Mode Voltage
V p-p
Full
Full
8
±.9
8
±.9
8
±.9
pF
V
REFERENCE INPUT
RESISTANCE
Full
6
6
6
kΩ
POWER SUPPLIES
Supply Voltage
AVDD
Full
Full
1.ꢁ
1.ꢁ
1.8
1.8
1.9
1.9
1.ꢁ
1.ꢁ
1.8
1.8
1.9
1.9
1.ꢁ
1.ꢁ
1.8
1.8
1.9
1.9
V
V
DRVDD
Supply Current
IAVDD1
IDRVDD1 (1.8 V
CMOS)
Full
Full
234
3ꢀ
24±
293
4ꢀ
3±±
39±
ꢀꢀ
4±±
mA
mA
IDRVDD1 (1.8 V
LVDS)
Full
89
89
94
mA
Rev. A | Page 4 of 44
AD9268
AD9268BCPZ-80
Temperature Min Typ Max Min Typ
AD9268BCPZ-105
AD9268BCPZ-125
Max
Parameter
Max Min Typ
Unit
POWER CONSUMPTION
DC Input
Sine Wave Input1
(DRVDD = 1.8 V
CMOS Output
Mode)
Full
Full
42±
48ꢀ
4ꢀ±
ꢀ6ꢀ
6±8
ꢀ9±
ꢁꢀ±
8±±
ꢁꢁꢁ
mW
mW
Sine Wave Input1
(DRVDD = 1.8 V
LVDS Output
Mode)
Full
ꢀ82
68ꢀ
8ꢁ±
mW
Standby Power3
Full
4ꢀ
±.ꢀ
4ꢀ
±.ꢀ
4ꢀ
±.ꢀ
mW
mW
Power-Down Power Full
2.ꢀ
2.ꢀ
2.ꢀ
1 Measured with a low input frequency, full-scale sine wave, with approximately ꢀ pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
Rev. A | Page ꢀ of 44
AD9268
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 2.
AD9268BCPZ-80
AD9268BCPZ-105
AD9268BCPZ-125
Parameter1
Temp
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = ꢁ± MHz
2ꢀ°C
2ꢀ°C
Full
2ꢀ°C
2ꢀ°C
ꢁ9.ꢁ
ꢁ9.±
ꢁ8.9
ꢁ8.8
ꢁ8.8
ꢁꢁ.2 ꢁ8.2
ꢁ6.ꢀ
dBFS
dBFS
dBFS
dBFS
dBFS
ꢁ8.3
ꢁ8.±
ꢁꢁ.2
ꢁꢁ.1
fIN = 14± MHz
fIN = 2±± MHz
ꢁꢁ.4
ꢁꢀ.ꢀ
ꢁ6.9
ꢁꢀ.±
ꢁꢁ.1
ꢁꢀ.ꢀ
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = ꢁ± MHz
2ꢀ°C
2ꢀ°C
Full
2ꢀ°C
2ꢀ°C
ꢁ9.4
ꢁ8.ꢀ
ꢁ8.3
ꢁ8.6
ꢁ8.3
ꢁ6.8 ꢁꢁ.ꢁ
ꢁ6.2
dBFS
dBFS
dBFS
dBFS
dBFS
ꢁ8.1
ꢁꢁ.ꢁ
ꢁꢁ.1
ꢁ6.8
fIN = 14± MHz
fIN = 2±± MHz
ꢁꢀ.4
ꢁ4.3
ꢁꢀ.9
ꢁ2.2
ꢁꢀ.8
ꢁ4.±
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = ꢁ± MHz
fIN = 14± MHz
fIN = 2±± MHz
2ꢀ°C
2ꢀ°C
2ꢀ°C
2ꢀ°C
12.9
12.8
12.2
12.±
12.ꢁ
12.ꢁ
12.3
11.ꢁ
12.ꢁ
12.6
12.3
12.±
Bits
Bits
Bits
Bits
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz
fIN = ꢁ± MHz
2ꢀ°C
2ꢀ°C
Full
2ꢀ°C
2ꢀ°C
−92
−91
−8ꢁ
−93
−9±
−88
dBc
dBc
dBc
dBc
dBc
−88
−8ꢁ
−8ꢁ
−8ꢁ
−8ꢀ
−84
fIN = 14± MHz
fIN = 2±± MHz
−8±
−82
−84
−ꢁꢁ
−83
−ꢁ9
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = ꢁ± MHz
2ꢀ°C
2ꢀ°C
Full
2ꢀ°C
2ꢀ°C
92
91
8ꢁ
93
9±
88
dBc
dBc
dBc
dBc
dBc
88
8ꢁ
8ꢁ
8ꢁ
8ꢀ
84
fIN = 14± MHz
fIN = 2±± MHz
8±
82
84
ꢁꢁ
83
ꢁ9
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
Without Dither (AIN@ −23 dBFS)
fIN = 2.4 MHz
2ꢀ°C
2ꢀ°C
2ꢀ°C
2ꢀ°C
93
9ꢀ
98
1±2
1±±
96
96
88
89
9±
89
dBFS
dBFS
dBFS
dBFS
fIN = ꢁ± MHz
fIN = 14± MHz
fIN = 2±± MHz
1±±
With On-Chip Dither (AIN @ −23 dBFS)
fIN = 2.4 MHz
fIN = ꢁ± MHz
fIN = 14± MHz
fIN = 2±± MHz
2ꢀ°C
2ꢀ°C
2ꢀ°C
2ꢀ°C
1±ꢁ
1±ꢁ
1±6
1±4
1±6
1±9
1±4
1±8
1±6
1±6
1±4
1±ꢀ
dBFS
dBFS
dBFS
dBFS
Rev. A | Page 6 of 44
AD9268
AD9268BCPZ-80
AD9268BCPZ-105
AD9268BCPZ-125
Parameter1
Temp
Min
Typ
Max
Min
Typ
Max
Min Typ
Max
Unit
WORST OTHER (HARMONIC OR SPUR)
Without Dither
fIN = 2.4 MHz
fIN = ꢁ± MHz
2ꢀ°C
2ꢀ°C
Full
2ꢀ°C
2ꢀ°C
−99
−1±± −96
−96
−98
−96
−1±±
−99
−1±±
−1±± −94
−94
−98
−96
dBc
dBc
dBc
dBc
dBc
−94
−94
fIN = 14± MHz
fIN = 2±± MHz
−98
−94
With On-Chip Dither
fIN = 2.4 MHz
fIN = ꢁ± MHz
2ꢀ°C
2ꢀ°C
Full
2ꢀ°C
2ꢀ°C
−1±8
−1±6 −96
−96
−1±ꢀ
−1±2
−1±ꢁ
−1±ꢁ −9ꢀ
−9ꢀ
−1±4
−1±2
−1±8
−1±6 −9ꢀ
−9ꢀ
−1±3
−99
dBc
dBc
dBc
dBc
dBc
fIN = 14± MHz
fIN = 2±± MHz
TWO-TONE SFDR, WITHOUT DITHER
fIN = 29 MHz (−ꢁ dBFS ), 32 MHz (−ꢁ dBFS)
fIN = 169 MHz (−ꢁ dBFS ), 1ꢁ2 MHz (−ꢁ dBFS)
CROSSTALK2
2ꢀ°C
2ꢀ°C
Full
93
81
92
8±
9±
82
dBc
dBc
dB
−9ꢀ
6ꢀ±
−9ꢀ
6ꢀ±
−9ꢀ
6ꢀ±
ANALOG INPUT BANDWIDTH
2ꢀ°C
MHz
1 See the AN-83ꢀ Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 1±± MHz with −1 dBFS on one channel and no input on the alternate channel.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter
Temperature Min
Typ
Max
Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
±.9
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Full
V
Full
Full
Full
Full
Full
Full
Full
±.3
AGND
±.9
−1±±
−1±±
3.6
AVDD
1.4
V p-p
V
V
+1±±
+1±±
μA
μA
pF
kΩ
4
1±
Input Resistance
8
12
SYNC INPUT
Logic Compliance
Internal Bias
CMOS
±.9
Full
Full
Full
Full
Full
Full
Full
Full
V
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
AGND
1.2
AGND
−1±±
−1±±
AVDD
AVDD
±.6
V
V
V
+1±±
+1±±
μA
μA
pF
kΩ
1
16
Input Resistance
12
2±
Rev. A | Page ꢁ of 44
AD9268
Parameter
LOGIC INPUT (CSB)1
Temperature Min
Typ
Max
Unit
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.22
±
−1±
4±
2.1
±.6
+1±
132
V
V
μA
μA
kΩ
pF
26
2
Input Capacitance
LOGIC INPUT (SCLK/DFS)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.22
±
−92
−1±
2.1
±.6
−13ꢀ
+1±
V
V
μA
μA
kΩ
pF
26
2
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO/DCS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.22
±
−1±
38
2.1
±.6
+1±
128
V
V
μA
μA
kΩ
pF
26
ꢀ
Input Capacitance
LOGIC INPUTS (OEB, PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.22
±
−9±
−1±
2.1
±.6
−134
+1±
V
V
μA
μA
kΩ
pF
26
ꢀ
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = ꢀ± μA
Full
Full
1.ꢁ9
1.ꢁꢀ
V
V
IOH = ±.ꢀ mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = ꢀ± μA
Full
Full
±.2
±.±ꢀ
V
V
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode Full
Output Offset Voltage (VOS), Reduced Swing Mode Full
Full
Full
29±
1.1ꢀ
16±
1.1ꢀ
34ꢀ
1.2ꢀ
2±±
1.2ꢀ
4±±
1.3ꢀ
23±
1.3ꢀ
mV
V
mV
V
1 Pull up.
2 Pull down.
Rev. A | Page 8 of 44
AD9268
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled,
unless otherwise noted.
Table 4.
AD9268BCPZ-80
Temperature Min Typ Max Min Typ
AD9268BCPZ-105
AD9268BCPZ-125
Max Unit
Parameter
Max Min Typ
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (tCLK
Full
625
625
625
MHz
Full
Full
Full
20
10
12.5
80
80
20
10
9.5
105
105
20
10
8
125
125
MSPS
MSPS
ns
)
CLK Pulse Width High (tCH)
3.75
5.95
0.8
8.75
6.55
2.85
4.5
6.65
5.0
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide- Full
by-8 Mode
Full
Full
6.25
6.25
4.75
4.75
2.4
3.8
0.8
4
4
5.6
4.2
ns
ns
ns
0.8
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Full
Full
1.0
0.07
1.0
0.07
1.0
0.07
ns
ps
rms
DATA OUTPUT PARAMETERS
CMOS Mode
2.8
4.2
0
2.8
4.2
0
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO
Full
Full
Full
3.5
3.1
3.5
3.1
2.8
3.5
3.1
4.2
0
ns
ns
ns
2
)
DCO to Data Skew (tSKEW
LVDS Mode
)
−0.6 −0.4
−0.6 −0.4
−0.6 −0.4
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO
Full
Full
Full
Full
2.9
3.7
3.9
4.5
2.9
3.7
3.9
4.5
2.9
3.7
3.9
4.5
ns
ns
2
)
DCO to Data Skew (tSKEW
)
−0.1 +0.2
12
+0.5 −0.1 +0.2
12
+0.5 −0.1 +0.2
12
+0.5 ns
Cycles
CMOS Mode Pipeline Delay
(Latency)
LVDS Mode Pipeline Delay (Latency) Full
Channel A/Channel B
12/12.5
12/12.5
12/12.5
Cycles
Wake-Up Time3
Full
Full
500
2
500
2
500
2
μs
Cycles
Out-of-Range Recovery Time
1 Conversion rate is the clock rate after the divider.
2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. A | Page 9 of 44
AD9268
TIMING SPECIFICATIONS
Table 5.
Parameter
Conditions
Limit
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
±.3 ns typ
±.4± ns typ
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge
2 ns min
2 ns min
4± ns min
2 ns min
2 ns min
1± ns min
1± ns min
1± ns min
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge
1± ns min
Timing Diagrams
N – 1
N + 4
tA
N + 5
N
N + 3
VIN
N + 1
N + 2
tCH
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
tSKEW
N – 12
CH A/CH B DATA
N – 13
N – 11
N – 10
N – 9
N – 8
tPD
Figure 2. CMOS Default Output Mode Data Output Timing
N – 1
N + 4
tA
N + 5
N
N + 3
VIN
N + 1
N + 2
tCH
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
tSKEW
tPD
CH A CH B CH A CH B CH A CH B
CH A CH B
CH A
N – 8
CH A/CH B DATA
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9
Figure 3. CMOS Interleaved Output Mode Data Output Timing
Rev. A | Page 1± of 44
AD9268
N – 1
N + 4
tA
N + 5
N
N + 3
VIN
N + 1
N + 2
tCH
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
tSKEW
CH A CH B CH A CH B CH A CH B
tPD
CH A CH B
CH A
N – 8
CH A/CH B DATA
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9
Figure 4. LVDS Mode Data Output Timing
CLK+
SYNC
tSSYNC
tHSYNC
Figure 5. SYNC Input Timing Requirements
Rev. A | Page 11 of 44
AD9268
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints and maximizes the
thermal capability of the package.
Parameter
ELECTRICAL1
Rating
AVDD to AGND
DRVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB
−±.3 V to +2.± V
−±.3 V to +2.± V
−±.3 V to AVDD + ±.2 V
−±.3 V to AVDD + ±.2 V
−±.3 V to AVDD + ±.2 V
−±.3V to AVDD + ±.2 V
−±.3V to AVDD + ±.2 V
−±.3V to AVDD + ±.2 V
−±.3V to AVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
−±.3V to DRVDD + ±.2V
−±.3 V to DRVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces θJA.
Table 7. Thermal Resistance
Airflow
Velocity
(m/sec)
1, 2
1, 3
1, 4
Package Type
θJA
θJC
1.±
θJB
Unit
°C/W
°C/W
°C/W
64-Lead LFCSP
(CP-64-6)
±
18.ꢀ
16.1
14.ꢀ
1.±
2.ꢀ
9.2
PDWN
D±A/D±B through D1ꢀA/D1ꢀB to
AGND
DCOA/DCOB to AGND
ENVIRONMENTAL
1 Per JEDEC ꢀ1-ꢁ, plus JEDEC 2ꢀ-ꢀ 2S2P test board.
2 Per JEDEC JESDꢀ1-2 (still air) or JEDEC JESDꢀ1-6 (moving air).
3 Per MIL-Std 883, Method 1±12.1.
−±.3 V to DRVDD + ±.2 V
4 Per JEDEC JESDꢀ1-8 (still air).
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
−4±°C to +8ꢀ°C
1ꢀ±°C
ESD CAUTION
Storage Temperature Range
(Ambient)
−6ꢀ°C to +1ꢀ±°C
1 The inputs and outputs are rated to the supply voltage (AVDD or ARVDD) +
±.2 V but should not exceed 2.1 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 12 of 44
AD9268
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
CLK+
CLK–
SYNC
D0B (LSB)
D1B
D2B
D3B
D4B
D5B
DRVDD 10
D6B 11
D7B 12
D8B 13
D9B 14
1
2
3
4
5
6
7
8
9
48 PDWN
47 OEB
46 CSB
45 SCLK/DFS
44 SDIO/DCS
43 ORA
42 D15A (MSB)
41 D14A
40 D13A
39 D12A
38 D11A
AD9268
PARALLEL CMOS
TOP VIEW
(Not to Scale)
37 DRVDD
36 D10A
35 D9A
D10B 15
D11B 16
34 D8A
33 D7A
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
1±, 19, 28, 3ꢁ
49, ꢀ±, ꢀ3, ꢀ4, ꢀ9,
6±, 63, 64
DRVDD
AVDD
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
±
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for proper
operation.
ADC Analog
ꢀ1
ꢀ2
62
61
VIN+A
VIN−A
VIN+B
VIN−B
VREF
Input
Input
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
ꢀꢀ
Input/Output Voltage Reference Input/Output.
ꢀ6
ꢀ8
ꢀꢁ
1
SENSE
RBIAS
VCM
CLK+
CLK−
Input
Voltage Reference Mode Select. See Table 11 for details.
Input/Output External Reference Bias Resistor.
Output
Input
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
2
Input
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Digital Outputs
2ꢀ
26
2ꢁ
29
3±
31
32
D±A (LSB)
D1A
D2A
D3A
D4A
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
DꢀA
D6A
Rev. A | Page 13 of 44
AD9268
Pin No.
Mnemonic
DꢁA
Type
Description
33
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A Overrange Output.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B Overrange Output
Channel A Data Clock Output.
Channel B Data Clock Output.
34
3ꢀ
36
38
39
4±
41
42
43
4
ꢀ
6
ꢁ
8
9
11
12
13
14
1ꢀ
16
1ꢁ
18
2±
21
22
24
23
D8A
D9A
D1±A
D11A
D12A
D13A
D14A
D1ꢀA (MSB)
ORA
D±B (LSB)
D1B
D2B
D3B
D4B
DꢀB
D6B
DꢁB
D8B
D9B
D1±B
D11B
D12B
D13B
D14B
D1ꢀB (MSB)
ORB
DCOA
DCOB
SPI Control
4ꢀ
44
46
SCLK/DFS
SDIO/DCS
CSB
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
Input
SPI Chip Select (Active Low).
ADC Configuration
4ꢁ
48
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.
Rev. A | Page 14 of 44
AD9268
PIN 1
INDICATOR
CLK+
CLK–
SYNC
D0– (LSB)
D0+ (LSB)
D1–
1
2
3
4
5
6
7
8
9
48 PDWN
47 OEB
46 CSB
45 SCLK/DFS
44 SDIO/DCS
43 OR+
D1+
D2–
D2+
42 OR–
AD9268
PARALLEL LVDS
TOP VIEW
41 D15+ (MSB)
40 D15– (MSB)
39 D14+
38 D14–
37 DRVDD
36 D13+
35 D13–
34 D12+
33 D12–
DRVDD 10
D3– 11
D3+ 12
D4– 13
D4+ 14
D5– 15
D5+ 16
(Not to Scale)
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
1±, 19, 28, 3ꢁ
DRVDD
AVDD
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
49, ꢀ±, ꢀ3, ꢀ4, ꢀ9,
6±, 63, 64
±
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for proper
operation.
ADC Analog
ꢀ1
ꢀ2
62
61
VIN+A
VIN−A
VIN+B
VIN−B
VREF
Input
Input
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
ꢀꢀ
Input/Output Voltage Reference Input/Output.
ꢀ6
ꢀ8
ꢀꢁ
1
SENSE
RBIAS
VCM
CLK+
CLK−
Input
Voltage Reference Mode Select. See Table 11 for details.
Input/Output External Reference Bias Resistor.
Output
Input
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
2
Input
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Digital Outputs
ꢀ
4
ꢁ
6
9
8
12
D±+ (LSB)
D±− (LSB)
D1+
D1−
D2+
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data ±—True.
Channel A/Channel B LVDS Output Data ±—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
D2−
D3+
Rev. A | Page 1ꢀ of 44
AD9268
Pin No.
Mnemonic
D3−
Type
Description
11
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data ꢀ—True.
Channel A/Channel B LVDS Output Data ꢀ—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data ꢁ—True.
Channel A/Channel B LVDS Output Data ꢁ—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 1±—True.
Channel A/Channel B LVDS Output Data 1±—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Output Data 12—True.
Channel A/Channel B LVDS Output Data 12—Complement.
Channel A/Channel B LVDS Output Data 13—True.
Channel A/Channel B LVDS Output Data 13—Complement.
Channel A/Channel B LVDS Output Data 14—True.
Channel A/Channel B LVDS Output Data 14—Complement.
Channel A/Channel B LVDS Output Data 1ꢀ—True.
Channel A/Channel B LVDS Output Data 1ꢀ—Complement.
Channel A/Channel B LVDS Overrange Output—True.
Channel A/Channel B LVDS Overrange Output—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
14
13
16
1ꢀ
18
1ꢁ
21
2±
23
22
2ꢁ
26
3±
29
32
31
34
33
36
3ꢀ
39
38
41
4±
43
42
2ꢀ
24
D4+
D4−
Dꢀ+
Dꢀ−
D6+
D6−
Dꢁ+
Dꢁ−
D8+
D8−
D9+
D9−
D1±+
D1±−
D11+
D11−
D12+
D12−
D13+
D13−
D14+
D14−
D1ꢀ+ (MSB)
D1ꢀ− (MSB)
OR+
OR−
DCO+
DCO−
SPI Control
4ꢀ
SCLK/DFS
SDIO/DCS
CSB
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
44
46
Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
Input
SPI Chip Select (Active Low).
ADC Configuration
4ꢁ
48
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.
Rev. A | Page 16 of 44
AD9268
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and
32k sample, TA = 25°C, unless otherwise noted.
0
–20
–40
–60
0
–20
–40
–60
80MSPS
80MSPS
200.3MHz @ –1dBFS
SNR = 74.3dB (75.3dBFS)
SFDR = 83dBc
2.4MHz @ –1dBFS
SNR = 79.0dB (80.0dBFS)
SFDR = 98dBc
SECOND HARMONIC
SECOND HARMONIC
THIRD HARMONIC
–80
–80
–100
–120
THIRD HARMONIC
–100
–120
–140
–140
20
FREQUENCY (MHz)
0
10
20
FREQUENCY (MHz)
30
40
0
10
30
40
Figure 8. AD9268-80 Single-Tone FFT with fIN = 2.4 MHz
Figure 11. AD9268-80 Single-Tone FFT with fIN = 200.1 MHz
0
0
80MSPS
70.1MHz @ –6dBFS
SNR = 73.0dB (79.0dBFS)
SFDR = 98dBc
80MSPS
70.1MHz @ –1dBFS
SNR = 77.5dB (78.5dBFS)
SFDR = 89.2dBc
–20
–40
–60
–20
–40
–60
THIRD HARMONIC
THIRD HARMONIC
–80
–100
–120
–80
–100
–120
SECOND HARMONIC
SECOND HARMONIC
–140
–140
0
10
20
30
40
0
10
20
30
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. AD9268-80 Single-Tone FFT with fIN = 70.1 MHz
Figure 12. AD9268-80 Single-Tone FFT with fIN = 70.1 MHz with Dither
Enabled
0
120
100
80
80MSPS
140.1MHz @ –1dBFS
SNR = 76.0dB (77.0dBFS)
SFDR = 81.1dBc
–20
–40
–60
THIRD HARMONIC
60
SECOND HARMONIC
–80
–100
–120
40
SNR (dBFS)
SFDR (dBc)
20
SNR (dBc)
SFDR (dBFS)
–140
0
0
10
20
FREQUENCY (MHz)
30
40
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
INPUT AMPLITUDE (dBFS)
Figure 10. AD9268-80 Single-Tone FFT with fIN = 140.1 MHz
Figure 13. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN
)
with fIN = 98.12 MHz
Rev. A | Page 1ꢁ of 44
AD9268
200,000
180,000
160,000
140,000
120,000
100,000
80,000
120
110
100
90
2.17 LSB rms
SNRFS (DITHER ON)
SNRFS (DITHER OFF)
SFDRFS (DITHER ON)
SFDRFS (DITHER OFF)
60,000
40,000
80
20,000
0
70
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
INPUT AMPLITUDE (dBFS)
OUTPUT CODE
Figure 14. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 30 MHz with and without Dither Enabled
Figure 17. AD9268-80 Grounded Input Histogram
100
4
2
SNR @ –40°C
SFDR @ –40°C
SNR @ +25°C
SFDR @ +25°C
SNR @ +85°C
SFDR @ +85°C
DITHER ENABLED
DITHER DISABLED
95
90
85
80
75
70
65
0
–2
–4
0
0
50
100
150
200
250
300
10,000
20,000
30,000 40,000
OUTPUT CODE
50,000
60,000
INPUT FREQUENCY (MHz)
Figure 15. AD9268-80 Single-Tone SNR/SFDR vs. Input Frequency (fIN
)
Figure 18. AD9268-80 INL with fIN = 9.7 MHz
with 2 V p-p Full Scale
1.00
105
SNR, CHANNEL B
SFDR, CHANNEL B
SNR, CHANNEL A
SFDR, CHANNEL A
0.75
0.50
100
95
0.25
0
90
–0.25
–0.50
85
80
75
–0.75
–1.00
0
10,000
20,000
30,000 40,000
OUTPUT CODE
50,000
60,000
25
30
35
40
45
50
55
60
65
70
75
80
SAMPLE RATE (MSPS)
Figure 19. AD9268-80 DNL with fIN = 9.7 MHz
Figure 16. AD9268-80 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
Rev. A | Page 18 of 44
AD9268
0
–20
–40
–60
0
–20
–40
–60
105MSPS
105MSPS
200.3MHz @ –1dBFS
SNR = 74.0dB (75.0dBFS)
SFDR = 79dBc
2.4MHz @ –6dBFS
SNR = 78.2dB (79.2dBFS)
SFDR = 90dBc
SECOND
HARMONIC
THIRD HARMONIC
SECOND HARMONIC
THIRD HARMONIC
–80
–100
–120
–80
–100
–120
–140
–140
0
10
20
30
40
50
0
10
20
30
40
50
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. AD9268-105 Single-Tone FFT with fIN = 2.4 MHz
Figure 23. AD9268-105 Single-Tone FFT with fIN = 200.3 MHz
0
0
105MSPS
105MSPS
70.1MHz @ –1dBFS
–20 SNR = 77.5dB (78.5dBFS)
SFDR = 93.0dBc
70.1MHz @ –6dBFS
SNR = 72.7dB (78.7dBFS)
SFDR = 97.6dBc
–20
–40
–60
–40
–60
SECOND
HARMONIC
SECOND
HARMONIC
THIRD HARMONIC
THIRD HARMONIC
–80
–100
–120
–80
–100
–120
–140
–140
0
10
20
30
40
50
0
10
20
30
40
50
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 21. AD9268-105 Single-Tone FFT with fIN = 70.1 MHz
Figure 24. AD9268-105 Single-Tone FFT with fIN = 70.1 MHz with Dither
Enabled
120
100
80
0
105MSPS
140.1MHz @ –1dBFS
SNR = 75.7dB (76.7dBFS)
SFDR = 85.5dBc
–20
–40
–60
SECOND HARMONIC
THIRD HARMONIC
60
–80
–100
–120
40
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
20
0
SFDR (dBFS)
–140
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
0
10
20
30
40
50
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 25. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN
)
Figure 22. AD9268-105 Single-Tone FFT with fIN = 140.1 MHz
with fIN = 98.12 MHz
Rev. A | Page 19 of 44
AD9268
120
110
100
90
250,000
200,000
150,000
100,000
50,000
0
2.23 LSB rms
SNRFS (DITHER ON)
SNRFS (DITHER OFF)
SFDRFS (DITHER ON)
SFDRFS (DITHER OFF)
80
70
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
INPUT AMPLITUDE (dBFS)
OUTPUT CODE
Figure 26. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN
)
Figure 29. AD9268-105 Grounded Input Histogram
with fIN = 30 MHz with and without Dither Enabled
100
6
4
2
0
SNR @ –40°C
SFDR @ –40°C
SNR @ +25°C
SFDR @ +25°C
SNR @ +85°C
SFDR @ +85°C
DITHER ENABLED
DITHER DISABLED
95
90
85
80
75
70
65
–2
–4
–6
0
0
50
100
150
200
250
300
10,000
20,000
30,000 40,000
OUTPUT CODE
50,000
60,000
INPUT FREQUENCY (MHz)
Figure 27. AD9268-105 Single-Tone SNR/SFDR vs. Input Frequency (fIN
)
Figure 30. AD9268-105 INL with fIN = 9.7 MHz
with 2 V p-p Full Scale
105
1.00
SNR, CHANNEL B
SFDR, CHANNEL B
SNR, CHANNEL A
SFDR, CHANNEL A
0.75
0.50
100
95
0.25
0
90
–0.25
–0.50
85
80
75
–0.75
–1.00
25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105
0
10,000
20,000
30,000 40,000
OUTPUT CODE
50,000
60,000
SAMPLE RATE (MSPS)
Figure 28. AD9268-105 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
Figure 31. AD9268-105 DNL with fIN = 9.7 MHz
Rev. A | Page 2± of 44
AD9268
0
0
125MSPS
125MSPS
2.4MHz @ –1dBFS
SNR = 77.7dB (78.7dBFS)
SFDR = 90dBc
140.1MHz @ –1dBFS
SNR = 76.0dB (77.0dBFS)
SFDR = 84.0dBc
–20
–20
–40
–60
–40
–60
SECOND HARMONIC
THIRD HARMONIC
THIRD HARMONIC
SECOND HARMONIC
–80
–80
–100
–120
–140
–100
–120
–140
0
10
20
30
40
50
60
0
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 35. AD9268-125 Single-Tone FFT with fIN = 140.1 MHz
Figure 32. AD9268-125 Single-Tone FFT with fIN = 2.4 MHz
0
0
125MSPS
200.3MHz @ –1dBFS
SNR = 74.7dB (75.7dBFS)
SFDR = 80dBc
125MSPS
30.3MHz @ –1dBFS
SNR = 77.4dB (78.4dBFS)
SFDR = 91.2dBc
–20
–20
–40
–40
–60
–60
THIRD HARMONIC
SECOND HARMONIC
THIRD HARMONIC
–80
–100
–120
–140
–80
SECOND HARMONIC
–100
–120
–140
0
10
20
30
40
50
60
0
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36. AD9268-125 Single-Tone FFT with fIN = 200.3 MHz
Figure 33. AD9268-125 Single-Tone FFT with fIN = 30.3 MHz
0
0
125MSPS
220.1MHz @ –1dBFS
SNR = 74.3dB (75.3dBFS)
SFDR = 78.5dBc
125MSPS
70.1MHz @ –1dBFS
SNR = 77.2dB (78.2dBFS)
SFDR = 87.8dBc
–20
–20
–40
–40
THIRD HARMONIC
–60
–60
SECOND HARMONIC
THIRD HARMONIC
SECOND HARMONIC
–80
–80
–100
–120
–140
–100
–120
–140
0
10
20
30
40
50
60
0
10
20
30
40
50
60
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 37. AD9268-125 Single-Tone FFT with fIN = 220.1 MHz
Figure 34. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz
Rev. A | Page 21 of 44
AD9268
0
120
100
80
125MSPS
SFDR (dBFS)
70.1MHz @ –6dBFS
SNR = 72.2dB (78.2dBFS)
SFDR = 97dBc
–20
–40
–60
–80
SNR (dBFS)
60
SFDR (dBc)
SECOND HARMONIC
THIRD HARMONIC
40
20
0
–100
–120
–140
SNR (dBc)
0
10
20
30
40
50
60
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 41. AD9268-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN
)
Figure 38. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −6 dBFS
with Dither Enabled
with fIN = 2.4 MHz
120
0
SFDR (dBFS)
125MSPS
–15 70.1MHz @ –23dBFS
SNR = 56.8dB (79.8dBFS)
100
SFDR = 67.7dBc
–30
–45
–60
SNR (dBFS)
80
THIRD HARMONIC
60
–75
–90
SECOND HARMONIC
SFDR (dBc)
40
–105
–120
–135
–150
SNR (dBc)
20
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
0
6
12
18
24
30
36
42
48
54
60
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 42. AD9268-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN
)
Figure 39. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS
with Dither Disabled, 1M Sample
with fIN = 98.12 MHz
120
0
125MSPS
–15 70.1MHz @ –23dBFS
SNR = 56.2dB (57.2dBFS)
SFDR (DITHER ON)
110
SFDR = 86.6dBc
–30
–45
–60
100
–75
–90
SECOND HARMONIC
THIRD HARMONIC
SFDR (DITHER OFF)
90
–105
–120
–135
–150
SNR (DITHER OFF)
80
SNR (DITHER ON)
70
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
0
6
12
18
24
30
36
42
48
54
60
INPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 43. AD9268-125 Single Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 30 MHz with and without Dither Enabled
Figure 40. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS
with Dither Enabled, 1M Sample
Rev. A | Page 22 of 44
AD9268
0
–20
100
95
SNR @ –40°C
SFDR @ –40°C
SNR @ +25°C
SFDR @ +25°C
SNR @ +85°C
SFDR @ +85°C
SFDR (dBc)
90
–40
85
–60
IMD3 (dBc)
80
75
70
–80
SFDR (dBFS)
IMD3 (dBFS)
–78
–100
–120
65
–90
–66
–54
–42
–30
–18
–6
0
50
100
150
200
250
300
INPUT AMPLITUDE (dBFS)
INPUT FREQUENCY (MHz)
Figure 47. AD9268-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN
)
Figure 44. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN
)
with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 125 MSPS
with 2 V p-p Full Scale
0
95
90
125MSPS
29.1MHz @ –7dBFS
32.1MHz @ –7dBFS
SFDR = 89dBc (96dBFS)
–20
SFDR (dBc)
–40
85
–60
–80
80
75
70
65
SNR (dBFS)
–100
–120
–140
60
0
10
20
30
40
50
60
0
50
100
150
200
250
300
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 45. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN)
Figure 48. AD9268-125 Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz
with 1 V p-p Full Scale
0
0
125MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
–20
–20
SFDR = 81.8dBc (88.8dBFS)
SFDR (dBc)
–40
–40
–60
–80
IMD3 (dBc)
–60
–80
–100
–120
–140
SFDR (dBFS)
–100
IMD3 (dBFS)
–120
0
10
20
30
40
50
60
–90
–78
–66
–54
–42
–30
–18
–6
FREQUENCY (MHz)
INPUT AMPLITUDE (dBFS)
Figure 49. AD9268-125 Two-Tone FFT with fIN1 = 169.1 MHz and
IN2 = 172.1 MHz
Figure 46. AD9268-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN
)
f
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 125 MSPS
Rev. A | Page 23 of 44
AD9268
1.00
100
SFDR (dBc), CHANNEL B
0.75
0.50
95
0.25
0
90
85
–0.25
–0.50
SFDR (dBc), CHANNEL A
SNR (dBFS), CHANNEL B
80
75
–0.75
–1.00
SNR (dBFS), CHANNEL A
25 35 45 55 65
SAMPLE RATE (MSPS)
0
16,384
32,768
49,152
65,536
75
85
95
105 115 125
OUTPUT CODE
Figure 50. AD9268-125 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
Figure 53. AD9268-125 DNL with fIN = 9.7 MHz
3500
100
90
2.27LSB rms
SFDR (dBc)
SNR (dBFS)
3000
2500
2000
1500
1000
500
80
70
60
50
40
30
0
0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT CODE
Figure 51. AD9268-125 Grounded Input Histogram
Figure 54. SNR/SFDR vs. Input Common Mode (VCM)
with fIN = 30 MHz
4
DITHER ENABLED
DITHER DISABLED
2
0
–2
–4
0
16,384
32,768
49,152
65,536
OUTPUT CODE
Figure 52. AD9268-125 INL with fIN = 9.7 MHz
Rev. A | Page 24 of 44
AD9268
EQUIVALENT CIRCUITS
AVDD
VIN
350Ω
SENSE
Figure 55. Equivalent Analog Input Circuit
Figure 60. Equivalent SENSE Circuit
AVDD
DRVDD
0.9V
26kΩ
10kΩ
10kΩ
350Ω
CLK–
CLK+
CSB
Figure 61. Equivalent CSB Input Circuit
Figure 56. Equivalent Clock Input Circuit
AVDD
DRVDD
VREF
PAD
6kΩ
Figure 62. Equivalent VREF Circuit
Figure 57. Digital Output
DRVDD
26kΩ
350Ω
350Ω
PDWN
SDIO/DCS
26kΩ
Figure 63. Equivalent PDWN Input Circuit
Figure 58. Equivalent SDIO/DCS Circuit
DRVDD
350Ω
SCLK/DFS
OR OEB
26kΩ
Figure 59. Equivalent SCLK/DFS or OEB Input Circuit
Rev. A | Page 2ꢀ of 44
AD9268
THEORY OF OPERATION
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the inputs
to provide dynamic charging currents. This passive network
creates a low-pass filter at the ADC input; therefore, the precise
values are dependent on the application.
The AD9268 dual-core analog-to-digital converter (ADC)
design can be used for diversity reception of signals, in which the
ADCs are operating identically on the same carrier but from two
separate antennae. The ADCs can also be operated with inde-
pendent analog inputs. The user can sample any fS/2 frequency
segment from dc to 200 MHz, using appropriate low-pass or
band-pass filtering at the ADC inputs with little loss in ADC
performance. Operation to 300 MHz analog input is permitted,
but it occurs at the expense of increased ADC noise and distortion.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors should be reduced. In combination with the
driving source impedance, the shunt capacitors limit the input
bandwidth. Refer to the AN-742 Application Note, Frequency
Domain Response of Switched-Capacitor ADCs; the AN-827
Application Note, A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters,”
for more information on this subject (refer to www.analog.com).
BIAS
In nondiversity applications, the AD9268 can be used as a base-
band or direct downconversion receiver, in which one ADC is
used for I input data, and the other is used for Q input data.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9268 are accomplished
using a 3-wire SPI-compatible serial interface.
S
S
C
FB
C
ADC ARCHITECTURE
S
VIN+
The AD9268 architecture consists of a dual front-end sample-
and-hold circuit, followed by a pipelined, switched-capacitor
ADC. The quantized outputs from each stage are combined into
a final 16-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
C
PAR1
C
PAR2
H
S
S
S
C
S
VIN–
C
FB
C
C
PAR1
PAR2
S
BIAS
Figure 64. Switched-Capacitor Input
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digital-
to-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched, and the inputs should be
differentially balanced.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 × VREF.
Input Common Mode
The input stage of each channel contains a differential sampling
circuit that can be ac- or dc-coupled in differential or single-
ended modes. The output staging block aligns the data, corrects
errors, and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing digital output noise to
be separated from the analog core. During power-down, the output
buffers go into a high impedance state.
The analog inputs of the AD9268 are not internally dc biased.
In ac-coupled applications, the user must provide this bias exter-
nally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is
recommended for optimum performance, but the device
functions over a wider range with reasonable performance
(see Figure 54). An on-board common-mode voltage reference
is included in the design and is available from the VCM pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the VCM pin voltage
(typically 0.5 × AVDD). The VCM pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
Information section.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9268 is a differential switched-
capacitor circuit that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the input between sample
mode and hold mode (see Figure 64). When the input is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within ½ of a clock cycle.
Rev. A | Page 26 of 44
AD9268
Common-Mode Voltage Servo
typically at very low levels and do not limit SFDR when the
ADC is quantizing large-signal inputs, dithering converts these
tones to noise and produces a whiter noise floor.
In applications where there may be a voltage loss between the VCM
output of the AD9268 and the analog inputs, the common-mode
voltage servo can be enabled. When the inputs are ac-coupled and
a resistance of >100 Ω is placed between the VCM output and the
analog inputs, a significant voltage drop can occur and the
common-mode voltage servo should be enabled. Setting Bit 0 in
Register 0x0F to a logic high enables the VCM servo mode. In
this mode, the AD9268 monitors the common-mode input level
at the analog inputs and adjusts the VCM output level to keep the
common-mode input voltage at an optimal level. If both channels
are operational, Channel A is monitored. However, if Channel A
is in power-down or standby mode, then the Channel B input is
monitored.
Small-Signal FFT
For small-signal inputs, the front-end sampling circuit typically
contributes very little distortion, and, therefore, the SFDR is likely
to be limited by tones caused by DNL errors due to random com-
ponent mismatches. Therefore, for small-signal inputs (typically,
those below −6 dBFS), dithering can significantly improve
SFDR by converting these DNL tones to white noise.
Static Linearity
Dithering also removes sharp local discontinuities in the INL
transfer function of the ADC and reduces the overall peak-to-
peak INL.
Dither
In receiver applications, utilizing dither helps to reduce DNL errors
that cause small-signal gain errors. Often this issue is overcome
by setting the input noise 5 dB to 10 dB above the converter
noise. By utilizing dither within the converter to correct the
DNL errors, the input noise requirement can be reduced.
The AD9268 has an optional dither mode that can be selected
for one or both channels. Dithering is the act of injecting a known
but random amount of white noise, commonly referred to as
dither, into the input of the ADC. Dithering has the effect of
improving the local linearity at various points along the ADC
transfer function. Dithering can significantly improve the SFDR
when quantizing small-signal inputs, typically when the input
level is below −6 dBFS.
Differential Input Configurations
Optimum performance is achieved while driving the AD9268
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and ADA4938-2 differential drivers
provide excellent performance and a flexible interface to the
ADC.
As shown in Figure 65, the dither that is added to the input of
the ADC through the dither DAC is precisely subtracted out
digitally to minimize SNR degradation. When dithering is
enabled, the dither DAC is driven by a pseudorandom number
generator (PN gen). In the AD9268, the dither DAC is precisely
calibrated to result in only a very small degradation in SNR and
SINAD. The typical SNR and SINAD degradation values, with
dithering enabled, are only 1 dB and 0.8 dB, respectively.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9268 (see Figure 66), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
15pF
200Ω
AD9268
33Ω
5pF
15Ω
VIN
90Ω
DOUT
ADC CORE
VIN–
VIN+
AVDD
76.8Ω
VIN
AD9268
ADA4938-2
0.1µF
DITHER
DAC
33Ω
15Ω
VCM
120Ω
15pF
200Ω
PN GEN
DITHER ENABLE
Figure 66. Differential Input Configuration Using the ADA4938-2
Figure 65. Dither Block Diagram
For baseband applications in which SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 67. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
Large-Signal FFT
In most cases, dithering does not improve SFDR for large-signal
inputs close to full scale, for example, with a −1 dBFS input. For
large-signal inputs, the SFDR is typically limited by front-end
sampling distortion, which dithering cannot improve. However,
even for such large-signal inputs, dithering may be useful for
certain applications because it makes the noise floor whiter.
As is common in pipeline ADCs, the AD9268 contains small
DNL errors caused by random component mismatches that
produce spurs or tones that make the noise floor somewhat
randomly colored part-to-part. Although these tones are
C2
R2
VIN+
R1
2V p-p
49.9Ω
C1
R1
AD9268
R2
VCM
VIN–
0.1µF
C2
Figure 67. Differential Transformer-Coupled Configuration
Rev. A | Page 2ꢁ of 44
AD9268
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
achieved by using a ferrite bead in series with a resistor and
removing the capacitors. However, these values are dependent
on the input signal and should be used only as a starting guide.
Table 10. Example RC Network
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9268. For applications in
which SNR is a key parameter, differential double balun coupling
is the recommended input configuration (see Figure 68). In this
configuration, the input is ac-coupled, and the CML is provided
to each input through a 33 Ω resistor. These resistors compensate
for losses in the input baluns to provide a 50 Ω impedance to
the driver.
Frequency
Range
(MHz)
R1 Series C1 Differential R2 Series C2 Shunt
(Ω Each) (pF)
(Ω Each)
(pF Each)
± to 1±±
1±± to 2±± 1±
1±± to 3±± 1±1
33
ꢀ
ꢀ
1ꢀ
1±
66
1ꢀ
1±
Remove
Remove
1 In this configuration, R1 is a ferrite bead with a value of 1± Ω @ 1±± MHz.
An alternative to using a transformer-coupled input at fre-
quencies in the second Nyquist zone is to use the AD8352
differential driver. An example is shown in Figure 69. See the
AD8352 data sheet for more information.
In the double balun and transformer configurations, the value of
the input capacitors and resistors is dependent on the input fre-
quency and source impedance and may need to be reduced or
removed. Table 10 displays recommended values to set the RC
network. At higher input frequencies, good performance can be
C2
0.1µF
0.1µF
R1
R2
R2
VIN+
2V p-p
33Ω
33Ω
P
A
S
S
P
C1
R1
AD9268
0.1µF
0.1µF
VCM
VIN–
C2
Figure 68. Differential Double Balun Input Configuration
V
CC
0.1µF
0Ω
R
0.1µF
16
1
8, 13
11
0.1µF
0.1µF
ANALOG INPUT
R
R
VIN+
2
200Ω
C
AD9268
AD8352
10
R
G
C
D
D
3
4
5
200Ω
VCM
VIN–
14
0.1µF
ANALOG INPUT
0Ω
0.1µF
0.1µF
Figure 69. Differential Input Configuration Using the AD8352
Rev. A | Page 28 of 44
AD9268
If a resistor divider is connected external to the chip, as shown
in Figure 71, the switch again sets to the SENSE pin. This puts
the reference amplifier in a noninverting mode with the VREF
output, defined as follows:
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9268.
The input range can be adjusted by varying the reference voltage
applied to the AD9268, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the sections that follow. The Reference
Decoupling section describes the best practices PCB layout of
the reference.
R2
R1
⎛
⎝
⎞
⎟
⎠
VREF = 0.5× 1+
⎜
The input range of the ADC always equals twice the voltage at
the reference pin (VREF) for either an internal or an external
reference.
Internal Reference Connection
VIN+A/VIN+B
VIN–A/VIN–B
A comparator within the AD9268 detects the potential at the
SENSE pin and configures the reference into four possible modes,
which are summarized in Table 11. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p full-
scale input. In this mode, with SENSE grounded, the full scale can
also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of
Register 0x18. These bits can be used to change the full scale to
1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p,
as shown in Table 17.
ADC
CORE
VREF
1.0µF
0.1µF
R2
SELECT
LOGIC
SENSE
0.5V
R1
Connecting the SENSE pin to the VREF pin switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output for a 1 V p-p full-scale input.
AD9268
Figure 71. Programmable Reference Configuration
VIN+A/VIN+B
VIN–A/VIN–B
If the internal reference of the AD9268 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 72 shows
how the internal reference voltage is affected by loading.
0
ADC
CORE
VREF
–0.5
1.0µF
0.1µF
VREF = 0.5V
SELECT
LOGIC
–1.0
SENSE
VREF = 1V
0.5V
–1.5
AD9268
–2.0
Figure 70. Internal Reference Configuration
–2.5
–3.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
LOAD CURRENT (mA)
Figure 72. Reference Voltage Accuracy vs. Load Current
Table 11. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
Internal Fixed Reference
AVDD
VREF
N/A
±.ꢀ
2 × external reference
1.±
R2
R1
⎛
⎞
⎟
(see Figure ꢁ1)
±.ꢀ × 1+
Programmable Reference
Internal Fixed Reference
±.2 V to VREF
AGND to ±.2 V
2 × VREF
2.±
⎜
⎝
⎠
1.±
Rev. A | Page 29 of 44
AD9268
External Reference Operation
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9268 to approx-
imately 0.8 V p-p differential.
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 73 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 62). The internal buffer generates the positive
and negative full-scale references for the ADC core. Therefore,
the external reference must be limited to a maximum of 1.0 V.
2.0
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9268 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
®
Mini-Circuits
ADC
ADT1-1WT, 1:1Z
AD9268
0.1µF
0.1µF
XFMR
CLOCK
INPUT
1.5
CLK+
CLK–
100Ω
VREF = 1.0V
1.0
50Ω
0.1µF
SCHOTTKY
DIODES:
HSMS2822
0.5
0
0.1µF
Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)
–0.5
–1.0
ADC
AD9268
1nF
50Ω
1nF
0.1µF
0.1µF
CLOCK
INPUT
CLK+
–1.5
–2.0
CLK–
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
SCHOTTKY
DIODES:
HSMS2822
Figure 73. Typical VREF Drift
Figure 76. Balun-Coupled Differential Clock (Up to 625 MHz)
CLOCK INPUT CONSIDERATIONS
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 77. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock
drivers offer excellent jitter performance.
For optimum performance, the AD9268 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 74) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
AVDD
0.1µF
0.1µF
CLOCK
INPUT
CLK+
ADC
AD9268
AD951x
PECL DRIVER
100Ω
0.9V
0.1µF
0.1µF
CLOCK
INPUT
CLK–
CLK+
CLK–
240Ω
240Ω
50kΩ
50kΩ
4pF
4pF
Figure 77. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 78. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518 clock drivers offer excellent jitter performance.
Figure 74. Equivalent Clock Input Circuit
Clock Input Options
The AD9268 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
0.1µF
0.1µF
CLOCK
INPUT
CLK+
ADC
AD9268
AD951x
LVDS DRIVER
100Ω
0.1µF
Figure 75 and Figure 76 show two preferred methods for clocking
the AD9268 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
0.1µF
CLOCK
INPUT
CLK–
50kΩ
50kΩ
Figure 78. Differential LVDS Sample Clock (Up to 625 MHz)
Rev. A | Page 3± of 44
AD9268
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 ꢀF
capacitor (see Figure 79).
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. For inputs near full scale, the degradation in
SNR from the low frequency SNR (SNRLF) at a given input
frequency (fINPUT) due to jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 (−SNR /10)
]
LF
V
CC
OPTIONAL
100Ω
0.1µF
1
0.1µF
1kΩ
1kΩ
AD951x
CMOS DRIVER
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 80. The measured curve in
Figure 80 was taken using an ADC clock source with approxi-
mately 65 fs of jitter, which combines with the 70 fs of jitter
inherent in the AD9268 to produce the results shown.
80
CLOCK
INPUT
CLK+
ADC
AD9268
50Ω
CLK–
0.1µF
1
50Ω RESISTOR IS OPTIONAL.
Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
0.05ps
Input Clock Divider
75
MEASURED
The AD9268 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. For
divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS) is
optional. For other divide ratios, divide by 3, 5, 6, 7, and 8, the
duty cycle stabilizer must be enabled for proper part operation.
70
0.20ps
65
0.50ps
60
55
50
The AD9268 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
1.00ps
1.50ps
1
10
100
1k
INPUT FREQUENCY (MHz)
Figure 80. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9268.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals and, as a result, may be sensitive to clock
duty cycle. The AD9268 requires a tight tolerance on the clock duty
cycle to maintain dynamic performance characteristics.
The AD9268 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the
perfor-mance of the AD9268. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS
enabled.
Refer to the AN-501 Application Note and the AN-756 Application
Note (see www.analog.com) for more information about jitter
performance as it relates to ADCs.
CHANNEL/CHIP SYNCHRONIZATION
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit. The
duty cycle control loop does not function for clock rates of less
than 20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the clock
rate can change dynamically. A wait time of 1.5 μs to 5 μs is
required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal. During the
time period that the loop is not locked, the DCS loop is bypassed,
and internal device timing is dependent on the duty cycle of the
input clock signal. In such applications, it may be appropriate to
disable the duty cycle stabilizer. In all other applications, enabling
the DCS circuit is recommended to maximize ac performance.
The AD9268 has a SYNC input that offers the user flexible
synchronization options for synchronizing the clock divider.
The clock divider sync feature is useful for guaranteeing synchro-
nized sample clocks across multiple ADCs. The input clock
divider can be enabled to synchronize on a single occurrence of
the SYNC signal or on every occurrence.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally syn-
chronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
Rev. A | Page 31 of 44
AD9268
1.0
0.25
POWER DISSIPATION AND STANDBY MODE
I
AVDD
As shown in Figure 81, the power dissipated by the AD9268
varies with its sample rate. In CMOS output mode, the digital
power dissipation is determined primarily by the strength of the
digital drivers and the load on each output bit.
0.8
0.6
0.4
0.2
0
0.20
0.15
0.10
0.05
0
TOTAL POWER
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (32 plus two DCO
outputs, in the case of the AD9268).
I
DRVDD
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which is
determined by the sample rate and the characteristics of the
analog input signal.
25
35
45
55
65
75
ENCODE FREQUENCY (MSPS)
Figure 83. AD9268-80 Power and Current vs. Encode Frequency (LVDS
Output Mode)
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9268 is placed in power-down
mode. In this state, the ADC typically dissipates 3.3 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD9268 to its normal operating mode.
Reducing the capacitive load presented to the output drivers
reduces digital power consumption. The data in Figure 81 was
taken in LVDS output mode, using the same operating conditions
as those used for the Typical Performance Characteristics.
1.25
0.5
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation.
1.00
0.75
0.50
0.25
0
0.4
0.3
0.2
0.1
0
IAVDD
TOTAL POWER
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required.
IDRVDD
DIGITAL OUTPUTS
The AD9268 output drivers can be configured to interface with
1.8 V CMOS logic families. The AD9268 can also be configured
for LVDS outputs (standard ANSI or reduced output swing mode)
using a DRVDD supply voltage of 1.8 V.
25
50
75
100
125
ENCODE FREQUENCY (MHz)
Figure 81. AD9268-125 Power and Current vs. Encode Frequency (LVDS
Output Mode)
1.0
0.5
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
0.8
0.6
0.4
0.2
0
0.4
0.3
0.2
0.1
0
TOTAL POWER
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The default output mode is CMOS, with each channel output
on separate busses as shown in Figure 2. The output can also be
configured for interleaved CMOS via the SPI port. In interleaved
CMOS mode, the data for both channels is output through the
Channel A output bits, and the Channel B output is placed into
high impedance mode. The timing diagram for interleaved
CMOS output mode is shown in Figure 3.
I
AVDD
I
DRVDD
25
35
45
55
65
75
85
95
105
ENCODE FREQUENCY (MSPS)
Figure 82. AD9268-105 Power and Current vs. Encode Frequency (LVDS
Output Mode)
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12).
Rev. A | Page 32 of 44
AD9268
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
TIMING
The AD9268 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9268.
These transients can degrade converter dynamic performance.
Voltage at Pin
SCLK/DFS
SDIO/DCS
AGND
AVDD
Offset binary (default)
Twos complement
DCS disabled
DCS enabled
(default)
The lowest typical conversion rate of the AD9268 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Digital Output Enable Function (OEB)
The AD9268 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the OEB pin or
through the SPI. If the OEB pin is low, the output data drivers and
DCOs are enabled. If the OEB pin is high, the output data drivers
and DCOs are placed in a high impedance state. This OEB
function is not intended for rapid access to the data bus. Note
that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
Data Clock Output (DCO)
The AD9268 provides two data clock output (DCO) signals
intended for capturing the data in an external register. In CMOS
output mode, the data outputs are valid on the rising edge of DCO,
unless the DCO clock polarity has been changed via the SPI. In
LVDS output mode, the DCO and data output switching edges
are closely aligned. Additional delay can be added to the DCO
output using SPI Register 0x17 to increase the data setup time.
In this case, the Channel A output data is valid on the rising
edge of DCO, and the Channel B output data is valid on the
falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for a
graphical timing description of the output modes.
When using the SPI, the data outputs and DCO of each channel
can be independently three-stated by using the output enable
bar bit (Bit 4) in Register 0x14.
Table 13. Output Data Format
Input (V)
Condition (V)
< −VREF − ±.ꢀ LSB
= −VREF
Offset Binary Output Mode
±±±± ±±±± ±±±± ±±±±
±±±± ±±±± ±±±± ±±±±
1±±± ±±±± ±±±± ±±±±
1111 1111 1111 1111
1111 1111 1111 1111
Twos Complement Mode
1±±± ±±±± ±±±± ±±±±
1±±± ±±±± ±±±± ±±±±
±±±± ±±±± ±±±± ±±±±
±111 1111 1111 1111
±111 1111 1111 1111
OR
1
±
±
±
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
= ±
= +VREF − 1.± LSB
> +VREF − ±.ꢀ LSB
1
Rev. A | Page 33 of 44
AD9268
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9268 includes built-in test features designed to enable
verification of the integrity of each channel as well as facilitate
board level debugging. A BIST (built-in self-test) feature is included
that verifies the integrity of the digital datapath of the AD9268.
Various output test options are also provided to place predictable
values on the outputs of the AD9268.
The outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or reset from the beginning, based
on the value programmed in Register 0x0E, Bit 2. The BIST
signature result varies based on the channel configuration.
OUTPUT TEST MODES
BUILT-IN SELF-TEST (BIST)
The output test options are shown in Table 17. When an output
test mode is enabled, the analog section of the ADC is discon-
nected from the digital back end blocks and the test pattern is run
through the output formatting block. Some of the test patterns are
subject to output formatting, and some are not. The seed value for
the PN sequence tests can be forced if the PN reset bits are used
to hold the generator in reset mode by setting Bit 4 or Bit 5 of
Register 0x0D. These tests can be performed with or without
an analog signal (if present, the analog signal is ignored), but
they do require an encode clock. For more information, see the
AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
The BIST is a thorough test of the digital portion of the selected
AD9268 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs for
512 cycles and stops. The BIST signature value for Channel A or
Channel B is placed in Register 0x24 and Register 0x25. If one
channel is chosen, its BIST signature is written to the two registers.
If both channels are chosen, the results from Channel A are placed
in the BIST signature registers.
Rev. A | Page 34 of 44
AD9268
SERIAL PORT INTERFACE (SPI)
The AD9268 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are docu-
mented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 84
and Table 5.
Other modes involving the CSB are available. When the CSB is
held low indefinitely, which permanently enables the device,
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode. This mode turns
on any SPI pin secondary functions.
CONFIGURATION USING THE SPI
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS
(a serial clock) is used to synchronize the read and write data
presented from and to the ADC. The SDIO/DCS (serial data
input/output) is a dual-purpose pin that allows data to be sent
to and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active-low control that enables or
disables the read and write cycles.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Table 14. Serial Port Interface Pins
Pin
Function
SCLK Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
All data is composed of 8-bit words. Data can be sent in MSB-first
mode or in LSB-first mode. MSB first is the default on power-up
and can be changed via the SPI port configuration register. For
more information about this and other features, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
CSB
Chip Select Bar. An active-low control that gates the read
and write cycles.
tHIGH
tDS
tCLK
tH
tS
tDH
tLOW
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 84. Serial Port Interface Timing Diagram
Rev. A | Page 3ꢀ of 44
AD9268
When the device is in SPI mode, the PDWN and OEB pins
remain active. For SPI control of output enable and power-down,
the OEB and PDWN pins should be set to their default states.
HARDWARE INTERFACE
The pins described in Table 14 comprise the physical interface
between the user programming device and the serial port of the
AD9268. The SCLK pin and the CSB pin function as inputs
when using the SPI. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during
readback.
Table 15. Mode Selection
External
Voltage
Pin
Configuration
SDIO/DCS
AVDD (default) Duty cycle stabilizer enabled
AGND
AVDD
Duty cycle stabilizer disabled
Twos complement enabled
The SPI is flexible enough to be controlled by either FPGAs or
microcontrollers. One method for SPI configuration is
described in detail in the AN-812 Application Note, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
SCLK/DFS
OEB
AGND (default) Offset binary enabled
AVDD Outputs in high impedance
AGND (default) Outputs enabled
AVDD
Chip in power-down or
standby
AGND (default) Normal operation
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9268 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
PDWN
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail in
the AN-877 Application Note, Interfacing to High Speed ADCs via
SPI. The AD9268 part-specific features are described in detail
following Table 17, the external memory map register table.
Some pins serve a dual function when the SPI is not being used.
When the pins are strapped to AVDD or ground during device
power-on, they are associated with a specific function. The
Digital Outputs section describes the strappable functions
supported on the AD9268.
Table 16. Features Accessible Using the SPI
Feature Name
Description
Mode
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the sync
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the output mode,
including LVDS
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
CONFIGURATION WITHOUT THE SPI
Clock
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the
PDWN pin serve as standalone CMOS-compatible control pins.
When the device is powered up, it is assumed that the user
intends to use the pins as static control lines for the duty cycle
stabilizer, output data format, output enable, and power-down
feature control. In this mode, the CSB chip select bar should be
connected to AVDD, which disables the serial port interface.
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Allows the user to set the reference voltage
Rev. A | Page 36 of 44
AD9268
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
An explanation of logic level terminology follows:
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
channel index and transfer registers (Address 0x05 and
Address 0xFF); the ADC functions registers, including setup,
control, and test (Address 0x08 to Address 0x30); and the digital
feature control register (Address 0x100).
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
•
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 through Address 0x18 and Address 0x30 are
shadowed. Writes to these addresses do not affect part
operation until a transfer command is issued by writing 0x01 to
Address 0xFF, setting the transfer bit. This allows these registers
to be updated internally and simultaneously when the transfer
bit is set. The internal update takes place when the transfer bit is
set, and the bit autoclears.
The memory map register table (see Table 17) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x18,
the VREF select register, has a hexadecimal default value of 0xC0.
This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s.
This setting is the default reference selection setting. The default
value uses a 2.0 V p-p reference. For more information on this
function and others, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI. This application note details the
functions controlled by Register 0x00 to Register 0xFF. The
remaining register, Register 0x100, is documented in the Memory
Map Register Table section.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel. In
these cases, channel address locations are internally duplicated for
each channel. These registers and bits are designated in Table 17
as local. These local registers and bits can be accessed by setting
the appropriate Channel A or Channel B bits in Register 0x05.
If both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, only Channel A or Channel B
should be set to read one of the two registers. If both bits are set
during an SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in Table 17 affect the entire
part or the channel features for which independent settings are not
allowed between channels. The settings in Register 0x05 do not
affect the global registers and bits.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
After the AD9268 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
Rev. A | Page 3ꢁ of 44
AD9268
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Default Default
Address Register
(Hex) Name
Chip Configuration Registers
Bit 7
(MSB)
Bit 0
(LSB)
Value
(Hex)
Notes/
Comments
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
±x±±
SPI port
configuration
(global)
±
LSB first
Soft reset
1
1
Soft reset
LSB first
±
±x18
The nibbles
are mirrored
so LSB-first
mode or MSB-
first mode
registers
correctly,
regardless of
shift mode
±x±1
±x±2
Chip ID
(global)
8-bit Chip ID[ꢁ:±]
(AD9268 = ±x32)
(default)
±x32
Read only
Chip grade
(global)
Open
Open
Open
Speed grade ID
±1 = 12ꢀ MSPS
Open
Open
Open
Open
Open
Speed grade
ID used to
differentiate
devices; read
only
1± = 1±ꢀ MSPS
11 = 8± MSPS
Channel Index and Transfer Registers
±x±ꢀ
Channel
index
Open
Open
Open
Open
Data
Channel
B
Data
Channel A
(default)
±x±3
Bits are set
to determine
which device
on the chip
receives the
next write
(default)
command;
applies to local
registers only
±xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Transfer
±x±±
±x8±
Synchronously
transfers data
from the
master shift
register to the
slave
ADC Functions
±x±8
Power modes
(local)
1
External
power-
down pin
function
(local)
± = pdwn
1 = stndby
Open
Internal power-down
mode (local)
±± = normal operation
±1 = full power-down
1± = standby
Determines
various generic
modes of chip
operation
11 = normal operation
±x±9
±x±B
Global clock
(global)
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Duty cycle
stabilizer
(default)
±x±1
±x±±
Clock divide
(global)
Open
Clock divide ratio
±±± = divide by 1
±±1 = divide by 2
±1± = divide by 3
±11 = divide by 4
1±± = divide by ꢀ
1±1 = divide by 6
11± = divide by ꢁ
111 = divide by 8
Clock divide
values other
than ±±±
automatically
cause the duty
cycle stabilizer
to become
active
±x±D
Test mode
(local)
Open
Open
Reset PN
long gen
Reset
PN short
gen
Open
Output test mode
±±± = off (default)
±±1 = midscale short
±1± = positive FS
±11 = negative FS
1±± = alternating checkerboard
1±1 = PN long sequence
11± = PN short sequence
111 = one/zero word toggle
±x±±
When this
register is set,
the test data
is placed on
the output
pins in place of
normal data
Rev. A | Page 38 of 44
AD9268
Default Default
Address Register
Bit 7
(MSB)
Bit 0
(LSB)
Value
(Hex)
Notes/
Comments
(Hex)
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
±x±E
BIST enable
(global)
Open
Open
Open
Open
Open
Open
Reset BIST
sequence
Open
BIST
enable
±x±4
±x±F
ADC input
(global)
Open
Open
Open
Open
Open
Open
Common-
mode
±x±±
servo
enable
±x1±
±x14
Offset adjust
(local)
Offset adjust in LSBs from +12ꢁ to −128
(twos complement format)
±x±±
±x±±
Output mode
Drive
Output
type
± = CMOS
1 = LVDS
(global)
CMOS
Output
enable
bar
Open
(must be
written
low)
Output
invert
(local)
Output format
±± = offset binary
±1 = twos
complement
±1 = gray code
11 = offset binary
(local)
Configures the
outputs and
the format of
the data
strength
± = ANSI
LVDS;
output
interleave
enable
(global)
(local)
1 =
reduced
swing
LVDS
(global)
±x16
Clock phase
control
(global)
Invert
DCO clock
Open
Open
Open
Open
Input clock divider phase adjust
±±± = no delay
±x±±
Allows
selection of
clock delays
into the input
clock divider
±±1 = 1 input clock cycle
±1± = 2 input clock cycles
±11 = 3 input clock cycles
1±± = 4 input clock cycles
1±1 = ꢀ input clock cycles
11± = 6 input clock cycles
111 = ꢁ input clock cycles
±x1ꢁ
DCO output
Open
Open
Open
DCO clock delay
±x±±
delay (global)
(delay = 2ꢀ±± ps × register value/31)
±±±±± = ± ps
±±±±1 = 81 ps
±±±1± = 161 ps
…
1111± = 2419 ps
11111 = 2ꢀ±± ps
±x18
VREF select
(global)
Reference voltage
selection
Open
Open
Open
Open
Open
Open
±xC±
±± = 1.2ꢀ V p-p
±1 = 1.ꢀ V p-p
1± = 1.ꢁꢀ V p-p
11 = 2.± V p-p
(default)
±x24
±x2ꢀ
±x3±
BIST signature
LSB (local)
BIST signature[ꢁ:±]
BIST signature[1ꢀ:8]
±x±±
±x±±
±x±±
Read only
Read only
BIST signature
MSB (local)
Dither enable
(local)
Open
Open
Open
Open
Open
Dither
Open
Open
Open
Open
enable
Digital Feature Control
±x1±±
Sync control
(global)
Open
Open
Open
Clock
Clock
divider
sync
Master
sync
enable
±x±±
divider
next sync
only
enable
Rev. A | Page 39 of 44
AD9268
ignore the rest. The clock divider sync enable bit (Address 0x100,
Bit 1) resets after it syncs.
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Sync Control (Register 0x100)
Bits[7:3]—Reserved
Bit 0—Master Sync Enable
Bit 2—Clock Divider Next Sync Only
Bit 0 must be high to enable any of the sync functions. If the
sync capability is not used this bit should remain low to
conserve power.
If the master sync enable bit (Address 0x100, Bit 0) and the clock
divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows
the clock divider to sync to the first sync pulse it receives and to
Rev. A | Page 4± of 44
AD9268
APPLICATIONS INFORMATION
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged to
prevent solder wicking through the vias, which can compromise
the connection.
DESIGN GUIDELINES
Before starting design and layout of the AD9268 as a system,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements that are needed for certain pins.
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the reflow
process. Using one continuous plane with no partitions guarantees
only one tie point between the ADC and the PCB. For detailed
information about packaging and PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), at www.analog.com.
Power and Ground Recommendations
When connecting power to the AD9268, it is recommended that
two separate 1.8 V supplies be used. Use one supply for analog
(AVDD); use a separate supply for the digital outputs (DRVDD).
For both AVDD and DRVDD several different decoupling capa-
citors should be used to cover both high and low frequencies.
Place these capacitors close to the point of entry at the PCB
level and close to the pins of the part, with minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9268. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
VCM
The VCM pin should be decoupled to ground with a 0.1 ꢀF
capacitor, as shown in Figure 67.
LVDS Operation
RBIAS
The AD9268 defaults to CMOS output mode on power-up.
If LVDS operation is desired, this mode must be programmed,
using the SPI configuration registers after power-up. When the
AD9268 powers up in CMOS mode with LVDS termination
resistors (100 Ω) on the outputs, the DRVDD current can be
higher than the typical value until the part is placed in LVDS
mode. This additional DRVDD current does not cause damage
to the AD9268, but it should be taken into account when consid-
ering the maximum DRVDD current for the part.
The AD9268 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with
a low ESR, 1.0 ꢀF capacitor in parallel with a low ESR, 0.1 ꢀF
ceramic capacitor.
SPI Port
To avoid this additional DRVDD current, the AD9268 outputs
can be disabled at power-up by taking the OEB pin high. After
the part is placed in LVDS mode via the SPI port, the OEB pin
can be taken low to enable the outputs.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9268 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask) copper plane on the PCB should mate to the
AD9268 exposed paddle, Pin 0.
Rev. A | Page 41 of 44
AD9268
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
PIN 1
INDICATOR
64
49
1
48
PIN 1
INDICATOR
0.50
BSC
7.65
7.50 SQ
7.35
8.75
BSC SQ
TOP VIEW
EXPOSED PAD
(BOTTOM VIEW)
0.50
0.40
0.30
16
17
33
32
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 85. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
CP-64-6
CP-64-6
CP-64-6
CP-64-6
AD9268BCPZ-8±1
AD9268BCPZRLꢁ-8±1
AD9268BCPZ-1±ꢀ1
AD9268BCPZRLꢁ-1±ꢀ1 −4±°C to +8ꢀ°C
AD9268BCPZ-12ꢀ1
−4±°C to +8ꢀ°C
AD9268BCPZRLꢁ-12ꢀ1 −4±°C to +8ꢀ°C
AD9268-8±EBZ1
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
CP-64-6
CP-64-6
AD9268-1±ꢀEBZ1
AD9268-12ꢀEBZ1
Evaluation Board
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 42 of 44
AD9268
NOTES
Rev. A | Page 43 of 44
AD9268
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08123-0-9/09(A)
Rev. A | Page 44 of 44
相关型号:
AD9268BCPZ-125
2-CH 16-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC64, 9 X 9 MM, ROHS COMPLIANT, M0-220VMMD-4, LFCSP-64
ROCHESTER
AD9268BCPZ-80
2-CH 16-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC64, 9 X 9 MM, ROHS COMPLIANT, M0-220VMMD-4, LFCSP-64
ROCHESTER
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