AD9281 [ADI]
Dual Channel 8-Bit Resolution CMOS ADC; 双通道8位分辨率的CMOS ADC
| 型号： | AD9281 |
| 厂家： | 
ADI |
| 描述： | Dual Channel 8-Bit Resolution CMOS ADC |
| 文件： | 总19页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Channel 8-Bit
a
Resolution CMOS ADC
AD9281
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Complete Dual Matching ADC
Low Power Dissipation: 225 mW (+3 V Supply)
Single Supply: 2.7 V to 5.5 V
Differential Nonlinearity Error: 0.1 LSB
On-Chip Analog Input Buffers
On-Chip Reference
Signal-to-Noise Ratio: 49.2 dB
Over Seven Effective Bits
Spurious-Free Dynamic Range: –65 dB
No Missing Codes Guaranteed
28-Lead SSOP
AVDD AVSS
DVDD DVSS
CLOCK
IINA
IINB
I
SLEEP
AD9281
"I" ADC
REGISTER
SELECT
REFERENCE
BUFFER
IREFB
IREFT
THREE-
QREFB
QREFT
ASYNCHRONOUS
MULTIPLEXER
STATE
OUTPUT
BUFFER
DATA
8 BITS
VREF
1V
REFSENSE
CHIP
SELECT
QINB
QINA
Q
"Q" ADC
REGISTER
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9281 is a complete dual channel, 28 MSPS, 8-bit
CMOS ADC. The AD9281 is optimized specifically for applica-
tions where close matching between two ADCs is required (e.g.,
I/Q channels in communications applications). The 28 MHz
sampling rate and wide input bandwidth will cover both narrow-
band and spread-spectrum channels. The AD9281 integrates
two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal
voltage reference and multiplexed digital output buffers.
1. Dual 8-Bit, 28 MSPS ADC
A pair of high performance 28 MSPS ADCs that are opti-
mized for spurious free dynamic performance are provided for
encoding of I and Q or diversity channel information.
2. Low Power
Complete CMOS Dual ADC function consumes a low
225 mW on a single supply (on 3 V supply). The AD9281
operates on supply voltages from 2.7 V to 5.5 V.
Each ADC incorporates a simultaneous sampling sample-and-
hold amplifier at its input. The analog inputs are buffered; no
external input buffer op amp will be required in most applica-
tions. The ADCs are implemented using a multistage pipeline
architecture that offers accurate performance and guarantees no
missing codes. The outputs of the ADCs are ported to a multi-
plexed digital output buffer.
3. On-Chip Voltage Reference
The AD9281 includes an on-chip compensated bandgap
voltage reference pin programmable for 1 V or 2 V.
4. On-chip analog input buffers eliminate the need for external
op amps in most applications.
5. Single 8-Bit Digital Output Bus
The AD9281 ADC outputs are interleaved onto a single
output bus saving board space and digital pin count.
The AD9281 is manufactured on an advanced low cost CMOS
process, operates from a single supply from 2.7 V to 5.5 V, and
consumes 225 mW of power (on 3 V supply). The AD9281
input structure accepts either single-ended or differential signals,
providing excellent dynamic performance up to and beyond
14 MHz Nyquist input frequencies.
6. Small Package
The AD9281 offers the complete integrated function in a
compact 28-lead SSOP package.
7. Product Family
The AD9281 dual ADC is pin compatible with a dual 10-bit
ADC (AD9201).
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(AVDD = +3 V, DVDD = +3 V, FSAMPLE = 28 MSPS, VREF = 2 V, INB = 0.5 V, TMIN to TMAX
AD9281–SPECIFICATIONS unless otherwise noted)
Parameter
Symbol
Min
Typ
8
Max
Units
Bits
Condition
RESOLUTION
CONVERSION RATE
FS
28
MHz
(32 MHz at +25°C)
DC ACCURACY
Differential Nonlinearity
Integral Nonlinearity
Differential Nonlinearity (SE)1
Integral Nonlinearity (SE)1
Zero-Scale Error, Offset Error
Full-Scale Error, Gain Error
Gain Match
DNL
INL
DNL
INL
EZS
±0.1
±0.25
±0.2
±0.3
±1
±1.2
±0.2
±1.2
LSB
LSB
LSB
LSB
% FS
% FS
LSB
LSB
REFT = 1.0 V, REFB = 0.0 V
REFT = 1.0 V, REFB = 0.0 V
±1.0
±1.5
±3.2
±5.4
EFS
Offset Match
ANALOG INPUT
Input Voltage Range
Input Capacitance
Aperture Delay
Aperture Uncertainty (Jitter)
Aperture Delay Match
Input Bandwidth (–3 dB)
Small Signal (–20 dB)
Full Power (0 dB)
AIN
CIN
tAP
–0.5
AVDD/2
V
2
4
2
2
pF
ns
ps
ps
tAJ
BW
240
245
MHz
MHz
INTERNAL REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2 V Mode)
Output Voltage Tolerance (2 V Mode)
Load Regulation (1 V Mode)
Load Regulation (2 V Mode)
VREF
VREF
VREF
1
±10
2
±15
±10
±15
V
mV
V
mV
mV
mV
REFSENSE = VREF
REFSENSE = GND
±35
1 mA Load Current
1 mA Load Current
POWER SUPPLY
Operating Voltage
AVDD
DVDD
IAVDD
IDVDD
PD
2.7
2.7
3
3
5.5
5.5
V
V
Supply Current
75
0.1
225
16
0.15
mA
mA
mW
mW
% FS
Power Consumption
Power-Down
Power Supply Rejection
260
STBY = AVDD, Clock Low
PSR
0.75
DYNAMIC PERFORMANCE2
Signal-to-Noise and Distortion
f = 3.58 MHz
f = 14 MHz
Signal-to-Noise
SINAD
46.4
47.8
49.1
48
dB
dB
SNR
f = 3.58 MHz
f = 14 MHz
49.2
48.5
dB
dB
Total Harmonic Distortion
f = 3.58 MHz
f = 14 MHz
Spurious Free Dynamic Range
f = 3.58 MHz
THD
SFDR
–67.5 –49.5
–60
dB
dB
49.6
65
56
–58
0.2
0.08
–62
dB
dB
dB
f = 14 MHz
Two-Tone Intermodulation Distortion3
Differential Phase
Differential Gain
IMD
DP
DG
f = 44.9 MHz and 45.52 MHz
Degree NTSC 40 IRE Mod Ramp
%
dB
FS = 14.3 MHz
Crosstalk Rejection
REV. E
–2–
AD9281
Parameter
Symbol
Min
Typ
Max
Units
Condition
DYNAMIC PERFORMANCE (SE)1
Signal-to-Noise and Distortion
f = 3.58 MHz
Signal-to-Noise
f = 3.58 MHz
Total Harmonic Distortion
f = 3.58 MHz
Spurious Free Dynamic Range
f = 3.58 MHz
SINAD
SNR
47.2
48
dB
dB
dB
dB
THD
–55
–58
SFDR
DIGITAL INPUTS
High Input Voltage
Low Input Voltage
DC Leakage Current
Input Capacitance
VIH
VIL
IIN
2.4
V
V
µA
pF
0.3
±6
2
CIN
LOGIC OUTPUT (with DVDD = 3 V)
High Level Output Voltage
(IOH = 50 µA)
Low Level Output Voltage
(IOL = 1.5 mA)
VOH
VOL
2.88
V
V
0.095
LOGIC OUTPUT (with DVDD = 5 V)
High Level Output Voltage
(IOH = 50 µA)
VOH
4.5
V
Low Level Output Voltage
(IOL = 1.5 mA)
Data Valid Delay
MUX Select Delay
Data Enable Delay
VOL
tOD
tMD
tED
0.4
11
7
V
ns
ns
ns
13
CL = 20 pF. Output Level to
90% of Final Value
Data High-Z Delay
tDHZ
13
ns
CLOCKING
Clock Pulsewidth High
Clock Pulsewidth Low
Pipeline Latency
tCH
tCL
16.9
16.9
ns
ns
Cycles
3.0
NOTES
1SE is single ended input, REFT = 1.5 V, REFB = –0.5 V.
2AIN differential 2 V p-p, REFT = 1.5 V, REFB = –0.5 V.
3IMD referred to larger of two input signals.
Specifications subject to change without notice.
tOD
CLOCK
INPUT
ADC SAMPLE
#4
ADC SAMPLE
#5
ADC SAMPLE
#1
ADC SAMPLE
#2
ADC SAMPLE
#3
SELECT
INPUT
I CHANNEL
OUTPUT ENABLED
tMD
Q CHANNEL
OUTPUT ENABLED
SAMPLE #1-1
Q CHANNEL
OUTPUT
SAMPLE #1
Q CHANNEL
OUTPUT
SAMPLE #2
Q CHANNEL
OUTPUT
SAMPLE #1-2
Q CHANNEL
OUTPUT
SAMPLE #1-3
Q CHANNEL
OUTPUT
DATA
OUTPUT
SAMPLE #1-1
I CHANNEL
OUTPUT
SAMPLE #1
I CHANNEL
OUTPUT
Figure 1. ADC Timing
–3–
REV. E
AD9281
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Description
With
Respect
P
in
No. Name
Parameter
to
Min
Max
Units
1
DVSS
DVDD
NC
NC
D0
Digital Ground
Digital Supply
Not Connected
Not Connected
Bit 0 (LSB)
Bit 1
AVDD
DVDD
AVSS
AVDD
AVSS
DVSS
DVSS
DVDD
AVSS
DVSS
AVSS
AVSS
AVSS
AVSS
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
+6.5
+6.5
+0.3
+6.5
AVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+150
V
V
V
V
V
V
V
V
V
V
°C
°C
2
3
4
CLK
5
Digital Outputs
AINA, AINB
VREF
REFSENSE
REFT, REFB
Junction Temperature
Storage Temperature
Lead Temperature
10 sec
6
D1
7
D2
Bit 2
8
D3
Bit 3
9
D4
Bit 4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D5
Bit 5
–65
+150
D6
Bit 6
D7
Bit 7 (MSB)
+300
°C
SELECT
CLOCK
SLEEP
INA-I
Hi I Channel Out, Lo Q Channel Out
Clock
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
Hi Power Down, Lo Normal Operation
I Channel, A Input
INB-I
I Channel, B Input
REFT-I
REFB-I
AVSS
Top Reference Decoupling, I Channel
Bottom Reference Decoupling, I Channel
Analog Ground
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options*
Model
REFSENSE
VREF
Reference Select
AD9281ARS –40°C to +85°C 28-Lead SSOP
AD9281-EB
RS-28
Internal Reference Output
Analog Supply
Evaluation Board
AVDD
*RS = Shrink Small Outline.
REFB-Q
REFT-Q
INB-Q
Bottom Reference Decoupling, Q Channel
Top Reference Decoupling, Q Channel
Q Channel B Input
PIN CONFIGURATION
INA-Q
Q Channel A Input
DVSS
DVDD
CHIP-SELECT Hi-High Impedance, Lo-Normal Operation
CHIP-SELECT
INA-Q
INB-Q
NC
NC
REFT-Q
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
REFB-Q
AVDD
VREF
(LSB) D0
D1
AD9281
TOP VIEW
(Not to Scale)
Integral nonlinearity refers to the deviation of each individual
code from a line drawn from “zero” through “full scale.” The
point used as “zero” occurs 1/2 LSB before the first code transi-
tion. “Full scale” is defined as a level 1 1/2 LSBs beyond the last
code transition. The deviation is measured from the center of
each particular code to the true straight line.
D2
REFSENSE
AVSS
D3
D4
REFB-I
D5
REFT-I
INB-I
D6
(MSB) D7
SELECT
CLOCK
INA-I
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of the resolution for which no missing codes
(NMC) are guaranteed.
SLEEP
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9281 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. E
–4–
AD9281
AVDD
DRVDD
AVDD
AVDD
AVDD
AVSS
AVDD
AVSS
DRVSS
DRVSS
AVSS
AVSS
AVSS
a. D0–D9
b. Three-State Standby
c. CLK
AVDD
AVDD
AVDD
AVDD
AVDD
REFBS
REFBF
IN
AVSS
AVDD
AVSS
AVSS
AVSS
AVSS
AVSS
d. INA, INB
e. Reference
f. REFSENSE
g. VREF
Figure 2. Equivalent Circuits
scale. Gain error is the deviation of the actual difference be-
tween first and last code transitions and the ideal difference
between the first and last code transitions.
OFFSET ERROR
The first transition should occur at a level 1 LSB above “zero.”
Offset is defined as the deviation of the actual first code transi-
tion from that point.
GAIN MATCH
The change in gain error between I and Q channels.
OFFSET MATCH
The change in offset error between I and Q channels.
PIPELINE DELAY (LATENCY)
The number of clock cycles between conversion initiation and
the associated output data being made available. New output
data is provided every rising clock edge.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the num-
ber of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
MUX SELECT DELAY
The delay between the change in SELECT pin data level and
valid data on output pins.
It is possible to get a measure of performance expressed as N,
the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
POWER SUPPLY REJECTION
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
with the supply at its maximum limit.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and
is expressed as a percentage or in decibels.
APERTURE JITTER
Aperture jitter is the variation in aperture delay for successive
samples and is manifested as noise on the input to the A/D.
SIGNAL-TO-NOISE RATIO (SNR)
APERTURE DELAY
SNR is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Aperture delay is a measure of the Sample-and-Hold Amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
S/N+D is the ratio of the rms value of the measured input sig-
nal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
GAIN ERROR
The first code transition should occur for an analog value 1 LSB
above nominal negative full scale. The last transition should
occur for an analog value 1 LSB below the nominal positive full
REV. E
–5–
AD9281–Typical Characteristic Curves
(AVDD = +3 V, DVDD = +3 V, FS = 28 MHz (50% duty cycle), 2 V input span from –0.5 V to +1.5 V, 2 V internal reference unless otherwise noted)
1
55
–0.5dB
–6dB
50
45
40
35
30
0
–20dB
25
1.0E+05
–1
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
CODE OFFSET
1.0E+06
INPUT FREQUENCY – Hz
1.0E+07
1.0E+08
1.0E+08
1.0E+08
Figure 3. Typical INL
Figure 6. SNR vs. Input Frequency
1
55
–0.5dB
–6dB
50
45
40
35
30
0
–20dB
25
1.0E+05
–1
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240
CODE OFFSET
1.0E+06
INPUT FREQUENCY – Hz
1.0E+07
Figure 4. Typical DNL
Figure 7. SINAD vs. Input Frequency
1.00
0.80
–30
–35
–40
–45
–50
–55
–60
0.60
–20dB
0.40
0.20
0.00
–0.20
–0.40
–0.60
–0.80
–1.00
–6dB
–65
–70
–0.5dB
–1.0
–0.5
0
0.5
1.0
1.5
2.0
1.0E+05
1.0E+06
1.0E+07
INPUT VOLTAGE – Volts
INPUT FREQUENCY – Hz
Figure 5. Input Bias Current vs. Input Voltage
Figure 8. THD vs. Input Frequency
REV. E
–6–
AD9281
1.20E+07
1.00E+07
8.00E+06
6.00E+06
4.00E+06
2.00E+06
0.00E+00
70
65
60
55
50
45
40
35
30
10000000
25
12050
N–1
800
20
1.00E+06
N
N+1
1.00E+07
1.00E+08
CODE
CLOCK FREQUENCY – Hz
Figure 9. THD vs. Clock Frequency
Figure 12. Grounded Input Histogram
1.013
1.012
1.011
1.010
1.009
1.008
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–40
–20
0
20
40
60
80
100
1.00E+06
1.00E+07
1.00E+08
1.00E+09
TEMPERATURE – ؇C
INPUT FREQUENCY – Hz
Figure 10. Voltage Reference Error vs. Temperature
Figure 13. Full Power Bandwidth
240
50
45
40
35
30
235
230
–0.5dB
–6dB
225
220
215
210
205
200
195
190
–20dB
185
25
1.00E+05
0
4
8
12
16
20
24
28
32
1.00E+06
INPUT FREQUENCY – Hz
1.00E+07
1.00E+08
CLOCK FREQUENCY – MHz
Figure 11. Power Consumption vs. Clock Frequency
Figure 14. SNR vs. Input Frequency (Single-Ended)
REV. E
–7–
AD9281
10.0
converter to readily accommodate either single-ended or differ-
ential input signals. This differential structure makes the part
capable of accommodating a wide range of input signals.
FUND
0.0
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–100.0
–110.0
The AD9281 also includes an on-chip bandgap reference and
reference buffer. The reference buffer shifts the ground-referred
reference to levels more suitable for use by the internal circuits
of the converter. Both converters share the same reference and
reference buffer. This scheme provides for the best possible gain
match between the converters while simultaneously minimizing
the channel-to-channel crosstalk.
5TH
6TH
3RD
2ND
7TH
9TH
4TH
8TH
Each A/D converter has its own output latch, which updates on
the rising edge of the input clock. A logic multiplexer, con-
trolled through the SELECT pin, determines which channel is
passed to the digital output pins. The output drivers have their
own supply, allowing the part to be interfaced to a variety of
logic families. The outputs can be placed in a high impedance
state using the CHIP SELECT pin.
0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6
Figure 15a. Simultaneous Operation of I and Q Channels
10.0
FUND
0.0
The AD9281 has great flexibility in its supply voltage. The
analog and digital supplies may be operated from 2.7 V to 5.5 V,
independently of one another.
–10.0
–20.0
–30.0
–40.0
–50.0
–60.0
ANALOG INPUT
Figure 16 shows an equivalent circuit structure for the analog
input of one of the A/D converters. PMOS source-followers
buffer the analog input pins from the charge kickback problems
normally associated with switched capacitor ADC input struc-
tures. This produces a very high input impedance on the part,
allowing it to be effectively driven from high impedance sources.
This means that the AD9281 could even be driven directly by a
passive antialias filter.
5TH
2ND
3RD
–70.0
–80.0
8TH
7TH
6TH
4TH
–90.0
–100.0
–110.0
0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6
Figure 15b. Simultaneous Operation of I and Q Channels
IINA
IINB
BUFFER
BUFFER
OUTPUT
WORD
THEORY OF OPERATION
ADC
CORE
The AD9281 integrates two A/D converters, two analog input
buffers, an internal reference and reference buffer, and an out-
put multiplexer. For clarity, this data sheet refers to the two
converters as “I” and “Q.” The two A/D converters simulta-
neously sample their respective inputs on the rising edge of the
input clock. The two converters distribute the conversion opera-
tion over several smaller A/D sub-blocks, refining the conversion
with progressively higher accuracy as it passes the result from
stage to stage. As a consequence of the distributed conversion,
each converter requires a small fraction of the 256 comparators
used in a traditional flash-type 8-bit ADC. A sample-and-hold
function within each of the stages permits the first stage to oper-
ate on a new input sample while the following stages continue to
process previous samples. This results in a “pipeline processing”
latency of three clock periods between when an input sample is
taken and when the corresponding ADC output is updated into
the output registers.
SHA
+FS
LIMIT LIMIT
–FS
+FS LIMIT =
+V
–FS LIMIT =
–V
V
V
REF
REF/2
REF
REF/2
V
REF
Figure 16. Equivalent Circuit for AD9281 Analog Inputs
The source followers inside the buffers also provide a level-shift
function of approximately 1 V, allowing the AD9281 to accept
inputs at or below ground. One consequence of this structure is
that distortion will result if the analog input comes within 1.4 V
of the positive supply. For optimum high frequency distortion
performance, the analog input signal should be centered accord-
ing to Figure 27.
The capacitance load of the analog input pin is 4 pF to the
analog supplies (AVSS, AVDD).
The AD9281 integrates input buffer amplifiers to drive the
analog inputs of the converters. In most applications, these
input amplifiers eliminate the need for external op amps for the
input signals. The input structure is fully differential, but the
SHA common-mode response has been designed to allow the
Full-scale setpoints may be calculated according to the following
algorithm (VREF may be internally or externally generated):
–FS = VREF – (VREF/2)
+FS = VREF + (VREF/2)
VSPAN = VREF
REV. E
–8–
AD9281
The AD9281 can accommodate a variety of input spans be-
tween 1 V and 2 V. For spans of less than 1 V, expect a propor-
tionate degradation in SNR. Use of a 2 V span will provide the
best noise performance. 1 V spans will provide lower distortion
when using a 3 V analog supply. Users wishing to run with larger
full-scales are encouraged to use a 5 V analog supply (AVDD).
1.5V
0.5V
0.1F
I OR QREFT
I OR QREFB
ANALOG
INPUT
IINA
IINB
10F
0.1F
1k⍀
0.1F
1.0F
0.1F
AD9281
VREF
Single-Ended Inputs: For single-ended input signals, the
signal is applied to one input pin and the other input pin is tied
to a midscale voltage. This midscale voltage defines the center
of the full-scale span for the input signal.
REFSENSE
Figure 18. Example Configuration for 0.5 V–1.5 V ac
Coupled Single-Ended Inputs
EXAMPLE: For a single-ended input range from 0 V to 1 V
applied to IINA, we would configure the converter for a 1 V
reference (see Figure 17) and apply 0.5 V to IINB.
Transformer Coupled Inputs
Another option for input ac coupling is to use a transformer.
This not only provides dc rejection, but also allows truly differ-
ential drive of the AD9281’s analog inputs, which will provide
the optimal distortion performance. Figure 19 shows a recom-
mended transformer input drive configuration. Resistors R1 and
R2 define the termination impedance of the transformer cou-
pling. The center tap of the transformer secondary is tied to the
common-mode voltage, establishing the dc bias point for the
analog inputs.
1V
0V
0.1F
INPUT
IINA
I OR QREFT
10F
0.1F
MIDSCALE
VOLTAGE
= 0.5V (1V)
IINB I OR QREFB
0.1F
10F
0.1F
AD9281
5k⍀
5k⍀
VREF
REF SENSE
IINA
IINB
QINA
QINB
R1
R2
10F
0.1F
AD9281
0.1F
COMMON
MODE
VOLTAGE
Figure 17. Example Configuration for 0 V–1 V Single-
Ended Input Signal
I OR QREFT
0.1F
10F
VREF
I OR QREFB
0.1F
10F
Note that since the inputs are high impedance, this reference
level can easily be generated with an external resistive divider
with large resistance values (to minimize power dissipation). A
decoupling capacitor is recommended on this input to minimize
the high frequency noise-coupling onto this pin. Decoupling
should occur close to the ADC.
0.1F
REFSENSE
Figure 19. Example Configuration for Transformer
Coupled Inputs
Crosstalk: The internal layout of the AD9281, as well as its
pinout, was configured to minimize the crosstalk between the
two input signals. Users wishing to minimize high frequency
crosstalk should take care to provide the best possible decoupling
for input pins (see Figure 20). R and C values will make a pole
dependant on antialiasing requirements. Decoupling is also
required on reference pins and power supplies (see Figure 21).
Differential Inputs
Use of differential input signals can provide greater flexibility in
input ranges and bias points, as well as offering improvements in
distortion performance, particularly for high frequency input
signals. Users with differential input signals will probably want
to take advantage of the differential input structure of the AD9281.
Performance is still very good for single-ended inputs. Convert-
ing a single-ended input to a differential signal for application to
the converter is probably only worth considering for very high
frequency input signals.
IINA
QINA
QINB
AD9281
IINB
AC-Coupled Inputs
If the signal of interest has no dc component, ac coupling can be
easily used to define an optimum bias point. Figure 18 illustrates
one recommended configuration. The voltage chosen for the dc
bias point (in this case the 1 V reference) is applied to both
IINA and IINB pins through 1 kΩ resistors (R1 and R2). IINA
is coupled to the input signal through Capacitor C1, while IINB is
decoupled to ground through Capacitor C2.
Figure 20. Input Loading
V ANALOG
V DIGITAL
AVDD
DVDD
0.1F
0.1F
10F
0.1F
10F
AD9281
I OR QREFT
0.1F
10F
I OR QREFB
0.1F
Figure 21. Reference and Power Supply Decoupling
REV. E
–9–
AD9281
REFERENCE AND REFERENCE BUFFER
Externally Set Voltage Mode (Figure 24)—this mode uses
the on-chip reference, but scales the exact reference level though
the use of an external resistor divider network. VREF is wired to
the top of the network, with the REFSENSE wired to the tap
point in the resistor divider. The reference level (and input full
scale) will be equal to 1 V × (R1 + R2)/R1. This method can be
used for voltage levels from 0.7 V to 2.5 V.
The reference and buffer circuitry on the AD9281 is configured
for maximum convenience and flexibility. An illustration of the
equivalent reference circuit is show in Figure 26. The user can
select from five different reference modes through appropriate
pin-strapping (see Table I below). These pin strapping options
cause the internal circuitry to reconfigure itself for the appropri-
ate operating mode.
1F
Table I. Table of Modes
0.1F
1V
+
VREF
+
–
Mode
Input Span
REFSENSE Pin Figure
–
R2
R1
1 V
2 V
1 V
2 V
VREF
AGND
See Figure
22
23
24
25
REFSENSE
AD9281
0.1F
10F
Programmable
External
1 + (R1/R2)
= External Ref AVDD
AVSS
I OR QREFT
R2
R1
0.1F
VREF = 1 +
I OR QREFB
1 V Mode (Figure 22)—provides a 1 V reference and 1 V input
full scale. Recommended for applications wishing to optimize
high frequency performance, or any circuit on a supply voltage
of less than 4 V. The part is placed in this mode by shorting the
REFSENSE pin to the VREF pin.
0.1F
Figure 24. Programmable Reference
External Reference Mode (Figure 25)—in this mode, the on-
chip reference is disabled, and an external reference applied to
the VREF pin. This mode is achieved by tying the REFSENSE
pin to AVDD.
1V
0V
1V
0V
IINA
IINB
QINA
QINB
1V
0V
1V
0V
5k⍀
IINA
IINB
10F
0.1F
5k⍀
QINA
QINB
5k⍀
AD9281
1V
0.1F
5k⍀
10F
VREF
REFSENSE
I OR QREFT
AD9281
1V
0.1F
EXT
REFERENCE
VREF
0.1F
10F
10F
0.1F
I OR QREFT
0.1F
10F
10F
0.1F
0.1F
I OR QREFB
0.1F
I OR QREFB
0.1F
AVDD
REFSENSE
Figure 22. 0 V to 1 V Input
2 V Mode (Figure 23)—provides a 2 V reference and 2 V input
full scale. Recommended for noise sensitive applications on 5 V
supplies. The part is placed in 2 V reference mode by ground-
ing (shorting to AVSS) the REFSENSE pin.
Figure 25. External Reference
Reference Buffer—The reference buffer structure takes the
voltage on the VREF pin and level-shifts and buffers it for use
by various sub-blocks within the two A/D converters. The two
converters share the same reference buffer amplifier to maintain
the best possible gain match between the two converters. In the
interests of minimizing high frequency crosstalk, the buffered
references for the two converters are separately decoupled on
the IREFB, IREFT, QREFB and QREFT pins, as illustrated in
Figure 26.
2V
0V
2V
0V
IINA
IINB
QINA
QINB
5k⍀
10F
0.1F
5k⍀
AD9281
VREF
0.1F
10F
I OR QREFT
10F
0.1F
0.1F
I OR QREFB
REFSENSE
0.1F
Figure 23. 0 V to 2 V Input
REV. E
–10–
AD9281
feature chip capacitors located close to the converter IC. The
capacitors are connected to either IREFT/IREFB or QREFT/
QREFB. A connection to both sides is not required.
ADC
CORE
0.1F
10F
0.1F
10F
QREFT
0.1F
QREFB
IREFT
0.1F
COMMON-MODE PERFORMANCE
Attention to the common-mode point of the analog input volt-
age can improve the performance of the AD9281. Figure 27
illustrates THD as a function of common-mode voltage (center
point of the analog input span) and power supply.
1V
IREFB
VREF
0.1F
1.0F
0.1F
0.1F
10k⍀
10k⍀
Inspection of the curves will yield the following conclusions:
REFSENSE
1. An AD9281 running with AVDD = 5 V is the easiest to
drive.
INTERNAL
CONTROL
LOGIC
2. Differential inputs are the most insensitive to common-mode
voltage.
AVSS
AD9281
3. An AD9281 powered by AVDD = 3 V and a single ended
input, should have a 1 V span with a common-mode voltage
of 0.75 V.
Figure 26. Reference Buffer Equivalent Circuit and
External Decoupling Recommendation
For best results in both noise suppression and robustness
against crosstalk, the 4-capacitor buffer decoupling arrangement
shown in Figure 26 is recommended. This decoupling should
–3
–13
–23
–33
–15
2V
–25
–35
2V
–43
1V
–45
–53
1V
–55
–65
–63
–73
–0.5
0
0.5
1
1.5
–0.5
0
0.5
1
1.5
CML – V
CML – V
a. Differential Input, 3 V Supplies
c. Single-Ended Input, 3 V Supplies
–35
–15
–25
–35
–45
–40
–45
–50
–55
–60
–65
–70
2V
1V
2V
1V
–55
–65
–0.5
0
0.5
1
1.5
2
2.5
–0.5
0
0.5
1
1.5
2
2.5
CML – V
CML – V
b. Differential Input, 5 V Supplies
d. Single-Ended Input, 5 V Supplies
Figure 27. THD vs. CML Input Span and Power Supply (Analog Input = 1 MHz)
REV. E
–11–
AD9281
SELECT
DIGITAL INPUTS AND OUTPUTS
When the select pin is held LOW, the output word will present
the “Q” level. When the select pin is held HIGH, the “I” level
will be presented to the output word (see Figure 1).
Each of the AD9281 digital control inputs, CHIP SELECT,
CLOCK, SELECT and SLEEP are referenced to AVDD and
AVSS. Switching thresholds will be AVDD/2.
The AD9281’s select and clock pins may be driven by a com-
mon signal source. The data will change in 5 ns to 11 ns after
the edges of the input pulse. The user must make sure the inter-
face latches have sufficient hold time for the AD9281’s delays
(see Figure 28).
The format of the digital output is straight binary. A low power
mode feature is provided such that for STBY = HIGH and the
clock disabled, the static power of the AD9281 will drop below
22 mW.
CLOCK INPUT
The AD9281 clock input is internally buffered with an inverter
powered from the AVDD pin. This feature allows the AD9281
to accommodate either +5 V or +3.3 V CMOS logic input sig-
nal swings with the input threshold for the CLK pin nominally
at AVDD/2.
CLOCK
I
CLOCK
SOURCE
I LATCH
DATA
PROCESSING
SELECT
CLK
DATA
OUT
DATA
Q LATCH
CLOCK
The pipelined architecture of the AD9281 operates on both
rising and falling edges of the input clock. To minimize duty
cycle variations the logic family recommended to drive the clock
input is high speed or advanced CMOS (HC/HCT, AC/ACT)
logic. CMOS logic provides both symmetrical voltage threshold
levels and sufficient rise and fall times to support 28 MSPS
operation. Running the part at slightly faster clock rates may be
possible, although at reduced performance levels. Conversely,
some slight performance improvements might be realized by
clocking the AD9281 at slower clock rates.
Q
PROCESSING
Figure 28. Typical De-Mux Connection
APPLICATIONS
USING THE AD9281 FOR QAM DEMODULATION
QAM is one of the most widely used digital modulation schemes in
digital communication systems. This modulation technique
can be found in both FDMA as well as spread spectrum (i.e.,
CDMA) based systems. A QAM signal is a carrier frequency
which is both modulated in amplitude (i.e., AM modulation)
and in phase (i.e., PM modulation). At the transmitter, it can
be generated by independently modulating two carriers of iden-
tical frequency but with a 90° phase difference. This results in
an inphase (I) carrier component and a quadrature (Q) carrier
component at a 90° phase shift with respect to the I component.
The I and Q components are then summed to provide a QAM
signal at the specified carrier or IF frequency. Figure 29 shows
a typical analog implementation of a QAM modulator using a
dual 10-bit DAC with 2× interpolation, the AD9761. A QAM
signal can also be synthesized in the digital domain thus requir-
ing a single DAC to reconstruct the QAM signal. The AD9853
is an example of a complete (i.e., DAC included) digital QAM
modulator.
The power dissipated by the output buffers is largely propor-
tional to the clock frequency; running at reduced clock rates
provides a reduction in power consumption.
DIGITAL OUTPUTS
Each of the on-chip buffers for the AD9281 output bits (D0–D9)
is powered from the DVDD supply pin, separate from AVDD.
The output drivers are sized to handle a variety of logic families
while minimizing the amount of glitch energy generated. In all
cases, a fan-out of one is recommended to keep the capacitive
load on the output data bits below the specified 20 pF level.
For DVDD = 5 V, the AD9281 output signal swing is compat-
ible with both high speed CMOS and TTL logic families. For
TTL, the AD9281 on-chip, output drivers were designed to
support several of the high speed TTL families (F, AS, S). For
applications where the clock rate is below 28 MSPS, other TTL
families may be appropriate. For interfacing with lower voltage
CMOS logic, the AD9281 sustains 28 MSPS operation with
DVDD = 3 V. In all cases, check your logic family data sheets
for compatibility with the AD9281’s Specification table.
IOUT
DSP
OR
10
TO
MIXER
0
CARRIER
FREQUENCY
AD9761
QOUT
A 2 ns reduction in output delays can be achieved by limiting
the logic load to 5 pF per output line.
90
ASIC
NYQUIST
FILTERS
THREE-STATE OUTPUTS
QUADRATURE
MODULATOR
The digital outputs of the AD9281 can be placed in a high
impedance state by setting the CHIP SELECT pin to HIGH.
This feature is provided to facilitate in-circuit testing or evaluation.
Figure 29. Typical Analog QAM Modulator Architecture
REV. E
–12–
AD9281
At the receiver, the demodulation of a QAM signal back into its
separate I and Q components is essentially the modulation
process explain above but in the reverse order. A common and
traditional implementation of a QAM demodulator is shown in
Figure 30. In this example, the demodulation is performed in
the analog domain using a dual, matched ADC and a quadra-
ture demodulator to recover and digitize the I and Q baseband
signals. The quadrature demodulator is typically a single IC
containing two mixers and the appropriate circuitry to generate
the necessary 90° phase shift between the I and Q mixers’ local
oscillators. Before being digitized by the ADCs, the mixed
down baseband I and Q signals are filtered using matched ana-
log filters. These filters, often referred to as Nyquist or Pulse-
Shaping filters, remove images-from the mixing process and any
out-of-band. The characteristics of the matching Nyquist filters
are well defined to provide optimum signal-to-noise (SNR)
performance while minimizing intersymbol interference. The
ADC’s are typically simultaneously sampling their respective
inputs at the QAM symbol rate or, most often, at a multiple of it
if a digital filter follows the ADC. Oversampling and the use of
digital filtering eases the implementation and complexity of the
analog filter. It also allows for enhanced digital processing for
both carrier and symbol recovery and tuning purposes. The use
of a dual ADC such as the AD9281 ensures excellent gain,
offset, and phase matching between the I and Q channels.
LOGIC
SUPPLY
AVDD
DVDD
A
A
D
ADC
IC
DIGITAL
LOGIC
ICs
C
C
STRAY
ANALOG
CIRCUITS
DIGITAL
CIRCUITS
V
IN
B
A
A
STRAY
I
I
A
D
GND
AVSS
DVSS
= ANALOG
= DIGITAL
A
⌬V
D
A
A
D
Figure 31. Ground and Power Consideration
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from cou-
pling onto the input signal. Digital signals should not be run in
parallel with the input signal traces and should be routed
away from the input circuitry. Separate analog and digital
grounds should be joined together directly under the AD9281 in
a solid ground plane. The power and ground return currents
must be carefully managed. A general rule of thumb for mixed
signal layouts dictates that the return currents from digital cir-
cuitry should not pass through critical analog circuitry.
I
ADC
FROM
PREVIOUS
STAGE
DSP
OR
ASIC
CARRIER
FREQUENCY
LO
90°C
Transients between AVSS and DVSS will seriously degrade
performance of the ADC.
Q
ADC
NYQUIST
FILTERS
If the user cannot tie analog ground and digital ground together
at the ADC, he should consider the configuration in Figure 32.
QUADRATURE
DEMODULATOR
DUAL MATCHED
ADC
Another input and ground technique is shown in Figure 32. A
separate ground plane has been split for RF or hard to manage
signals. These signals can be routed to the ADC differentially or
single ended (i.e., both can either be connected to the driver or
RF ground). The ADC will perform well with several hundred
mV of noise or signals between the RF and ADC analog ground.
Figure 30. Typical Analog QAM Demodulator
GROUNDING AND LAYOUT RULES
As is the case for any high performance device, proper ground-
ing and layout techniques are essential in achieving optimal
performance. The analog and digital grounds on the AD9281
have been separated to optimize the management of return
currents in a system. Grounds should be connected near the
ADC. It is recommended that a printed circuit board (PCB) of
at least four layers, employing a ground plane and power planes,
be used with the AD9281. The use of ground and power planes
offers distinct advantages:
ANALOG
GROUND
DIGITAL
GROUND
RF
GROUND
LOGIC
ADC
AIN
BIN
DATA
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power plane,
PCB insulation and ground plane.
Figure 32. RF Ground Scheme
REV. E
–13–
AD9281
EVALUATION BOARD
should install a jumper at JP22 Pins 1 and 2. If the user wants to
toggle between I and Q channels, then a CMOS level pulse train
should be applied to the “strobe” jack after appropriate jumper
connections.
The AD9281 evaluation board is shipped “ready to run.”
Power and signal generators should be connected as shown in
Figure 33 Then the user can observe the performance of the Q
channel. If the user wants to observe the I channel, then he
+3V
+3V
+5V
DGND2 DRVDD
P1
AGND
DGND1 DVDD
AVDD
SYNTHESIZER
20MHz
CLOCK
2Vp-p
DSP
EQUIPMENT
AD9281
SYNTHESIZER
ANTI-
ALIAS
FILTER
1MHz
1Vp-p
Q IN
Figure 33. Evaluation Board Connections
REV. E
–14–
AD9281
R50
R51
C14
C50
C51
C20
C22
C14
C17
C23
C27
C24
R52
R53
C53
(NOT TO SCALE)
Figure 34. Evaluation Board Solder-Side Silkscreen
(NOT TO SCALE)
Figure 35. Evaluation Board Component-Side Layout
REV. E
–15–
AD9281
(NOT TO SCALE)
Figure 36. Evaluation Board Ground Plane Layout
(NOT TO SCALE)
Figure 37. Evaluation Board Solder-Side Layout
REV. E
–16–
AD9281
I_IN
STROBE
AGND AVDD
CLOCK
DGND1 DVDD
DGND2 DBVDD
BJ3
BJ6
BJ5
BJ4
C40
BJ1
BJ2
C42
AGND
AVDD
J1
J5
J6
C38
+
R38
L2
+ C43
L4
+ C46
L3
C45
C44
R36
C41
JP22
C48
C47
P1
JP16
R37
R13
R11
JP17
V8
JP19
C7
TP4
JP15
JP21
R32
TP7
JP3
T1
JP13
4
TP2
RN1
V1
C6
C15
+
TP1
JP20
C13
JP1
C1 JP2
C3
JP7
JP9
C2
J3
JP10
T2
4
+
C25
JP14
TP5
TP6
RN2
V2
C34
V4
R18
R14
C10
C37
C9
JP12
JP11
C31
R16
+
L5
+
R17
R24
JP4
V6
JP6
C32
D1
JP5
R23
+
C11
R6
TP3
R7
R10
AGND
R8
V3
J4
R12
Q_IN
(NOT TO SCALE)
Figure 38. Evaluation Board Component-Side Silkscreen
(NOT TO SCALE)
Figure 39. Evaluation Board Power Plane Layout
REV. E
–17–
AD9281
Figure 40. Evaluation Board
–18–
REV. E
AD9281
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Shrink Small Outline Package (SSOP)
(RS-28)
0.407 (10.34)
0.397 (10.08)
28
15
14
1
0.07 (1.79)
0.078 (1.98)
PIN 1
0.066 (1.67)
0.068 (1.73)
0.03 (0.762)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.022 (0.558)
0.008 (0.203)
0.002 (0.050)
SEATING
PLANE
0.009 (0.229)
0.005 (0.127)
REV. E
–19–
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