AD9289BBC [ADI]
Quad 8-Bit, 65 MSPS, Serial LVDS A/D Converter;
| 型号： | AD9289BBC |
| 厂家： | 
ADI |
| 描述： | Quad 8-Bit, 65 MSPS, Serial LVDS A/D Converter 转换器 |
| 文件： | 总33页 (文件大小：915K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad 8-Bit, 65 MSPS,
Serial LVDS 3 V A/D Converter
AD9289
FEATURES
Four ADCs in one package
FUNCTIONAL BLOCK DIAGRAM
AVDD
DFS
PDWN
DTP
DRVDD
DRGND
Serial LVDS digital output data rates to 520 Mbps (ANSI-644)
Data and frame clock outputs
SNR = 48 dBc (to Nyquist)
AD9289
VIN+A
VIN–A
8
D1+A
D1–A
SERIAL
LVDS
PIPELINE
ADC
SHA
Excellent linearity
DNL = 0.2 LSB (typical)
INL = 0.25 LSB (typical)
300 MHz full power analog bandwidth
Power dissipation = 112 mW/channel at 65 MSPS
1 Vp-p to 2 Vp-p input voltage range
3.0 V supply operation
VIN+B
VIN–B
8
8
8
D1+B
D1–B
SERIAL
LVDS
PIPELINE
ADC
SHA
SHA
SHA
VIN+C
VIN–C
D1+C
D1–C
SERIAL
LVDS
PIPELINE
ADC
VIN+D
VIN–D
D1+D
D1–D
SERIAL
LVDS
PIPELINE
ADC
Power-down mode
Digital test pattern enable for timing alignments
LOCK
VREF
SENSE
FCO+
FCO–
0.5V
REFT_A
REFB_A
REFT_B
REFB_B
APPLICATIONS
Tape drives
Medical imaging
REF
SELECT
DCO+
DCO–
DATA RATE
MULTIPLIER
SHARED_REF AGND LVDSBIAS CML CLK+ CLK–
Figure 1.
PRODUCT HIGHLIGHTS
PRODUCT DESCRIPTION
The AD9289 is a quad 8-bit, 65 MSPS analog-to-digital conver-
ter (ADC) with an on-chip sample-and-hold circuit that is
designed for low cost, low power, small size, and ease of use.
The product operates at up to a 65 MSPS conversion rate and is
optimized for outstanding dynamic performance where a small
package size is critical.
1. Four ADCs are contained in a small, space-saving package.
2. A data clock out (DCO) is provided, which operates up to
260 MHz and supports double-data rate operation (DDR).
3. The outputs of each ADC are serialized LVDS with data
rates up to 520 Mbps (8 bits × 65 MSPS).
The ADC requires a single, 3 V power supply and an LVDS-
compatible sample rate clock for full performance operation.
No external reference or driver components are required for
many applications.
4. The AD9289 operates from a single 3.0 V power supply.
5. The internal clock duty cycle stabilizer maintains
performance over a wide range of input clock duty cycles.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
capturing data on the output and a frame clock (FCO) trigger
for signaling a new output byte are provided. Power-down is
supported. The ADC typically consumes 7 mW when enabled.
Fabricated on an advanced CMOS process, the AD9289 is
available in a 64-ball mini-BGA package (64-BGA). It is
specified over the industrial temperature range of –40°C
to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD9289* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
TOOLS AND SIMULATIONS
• Visual Analog
• AD9289 IBIS Models
DOCUMENTATION
REFERENCE MATERIALS
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
Technical Articles
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• High-speed ADCs: Preventing Front-end Collisions
• AN-501: Aperture Uncertainty and ADC System
Performance
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-586: LVDS Outputs for High Speed A/D Converters
DESIGN RESOURCES
• AD9289 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
DISCUSSIONS
View all AD9289 EngineerZone Discussions.
• AN-835: Understanding High Speed ADC Testing and
Evaluation
SAMPLE AND BUY
• AN-905: Visual Analog Converter Evaluation Tool Version
Visit the product page to see pricing options.
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
TECHNICAL SUPPORT
End
Submit a technical question or find your regional support
number.
Data Sheet
• AD9289: Quad 8-Bit,65 MSPS Serial LVDS 3V A/D
Converter Data Sheet
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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AD9289
TABLE OF CONTENTS
Specifications..................................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 4
Switching Specifications .............................................................. 5
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Explanation of Test Levels........................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Equivalent Circuits........................................................................... 8
Typical Performance Characteristics ..............................................9
Terminology.................................................................................... 12
Theory of Operation...................................................................... 14
Analog Input and Reference Overview ................................... 14
Clock Input and Considerations .............................................. 15
Evaluation Board ............................................................................ 20
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
10/04—Initial Version: Revision 0
Rev. 0 | Page 2 of 32
AD9289
SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 1.
Parameter
Temperature
Test Level
Min
Typ
Max
Unit
RESOLUTION
8
Bits
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error ꢀ
Gain Matchingꢀ
Full
Full
Full
Full
Full
2±°C
Full
2±°C
Full
VI
VI
VI
VI
VI
V
VI
V
VI
Guaranteed
±±
±ꢀ2
±0.±
±0.2
±0.2
±0.2
±0.2±
±0.2±
±±5
±ꢁ8
±2.±
±0.ꢂ
mV
mV
% FS
% FS
LSB
LSB
LSB
LSB
Differential Nonlinearity (DNL)
±0.ꢁ
±0.ꢁ
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Full
Full
Full
V
V
V
±ꢀꢁ
±ꢃ0
±ꢀ0
ppm/°C
ppm/°C
ppm/°C
Gain Error
1
Reference Voltage (VREF = ꢀ V)
REFERENCE
Output Voltage Error (VREF = ꢀ V)
Load Regulation @ ꢀ.0 mA (VREF = ꢀ V)
Output Voltage Error (VREF = 0.± V)
Load Regulation @ 0.± mA (VREF = 0.± V)
Input Resistance
Full
Full
Full
Full
Full
VI
V
VI
V
±ꢀ0
0.5
±8
0.2
5
±3±
±2ꢁ
mV
mV
mV
mV
kΩ
V
COMMON MODE
Common-Mode Level Output
ANALOG INPUTS
Full
VI
±ꢀ.±
±±0
mV
Differential Input Voltage Range (VREF = ꢀ V)
Differential Input Voltage Range (VREF = 0.± V)
Common-Mode Voltage
Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
Full
Full
Full
Full
Full
VI
VI
V
V
V
2
ꢀ
ꢀ.±
±
300
V p-p
V p-p
V
pF
MHz
AVDD
DRVDD
IAVDD
DRVDD
Power Dissipation2
Power-Down Dissipation
CROSSTALK
Full
Full
Full
Full
Full
Full
Full
IV
IV
VI
VI
VI
VI
V
2.5
2.5
3.0
3.0
ꢀ±0
33
±±0
5
3.3
3.3
ꢀꢁ8
ꢃ0
ꢁ2±
ꢀ2
V
V
2
mA
mA
mW
mW
dB
2
–5±
ꢀ Gain error and gain temperature coefficients are based on the ADC only (with a fixed ꢀ.0 V external reference and a 2 V p-p differential analog input).
2 Power dissipation measured with rated encode and 2.ꢃ MHz analog input at –0.± dBFS.
Rev. 0 | Page 3 of 32
AD9289
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter
Temperature
Full
2±°C
Full
Test Level
Min
Typ
Max
Unit
dB
dB
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.ꢃ MHz
fIN = ꢀ0.3 MHz
fIN = 3± MHz
fIN = 2.ꢃ MHz
fIN = ꢀ0.3 MHz
fIN = 3± MHz
fIN = 2.ꢃ MHz
fIN = ꢀ0.3 MHz
fIN = 3± MHz
fIN = 2.ꢃ MHz
fIN = ꢀ0.3 MHz
fIN = 3± MHz
fIN = 2.ꢃ MHz
fIN = ꢀ0.3 MHz
fIN = 3± MHz
fIN = 2.ꢃ MHz
fIN = ꢀ0.3 MHz
fIN = 3± MHz
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
VI
IV
V
ꢃ5.5
ꢃꢂ.0
ꢃ8.±
ꢃ8.0
ꢃ8.ꢂ
ꢃ8.ꢃ
ꢃ5.±
5.8
ꢃꢁ.5
ꢃ5.ꢁ
dB
SIGNAL-TO-NOISE RATIO (SINAD)
Full
2±°C
Full
dB
dB
dB
ꢃꢁ.2
5.ꢁ
EFFECTIVE NUMBER OF BITS (ENOB)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
WORST HARMONIC (Second or Third)
WORST OTHER (Excluding Second or Third)
Full
2±°C
Full
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
5.5
5.ꢁ
5.ꢃ
Full
2±°C
Full
ꢁꢀ.0
50.0
ꢁ8.0
ꢁ±.0
–5±.0
–50.0
–ꢁ±.0
–50.0
–ꢁ8.0
–ꢁ±.0
–52.0
±ꢃ.0
Full
2±°C
Full
–ꢁꢀ.0
–±ꢃ.0
–ꢁꢀ.0
Full
2±°C
Full
VI
V
–±5.±
TWO TONE INTERMOD DISTORTION (IMD)
AINꢀ and AIN2 = –5.0 dBFS
fINꢀ = ꢀ± MHz
fIN2 = ꢀꢁ MHz
2±°C
DIGITAL SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 3.
Parameter
CLOCK INPUTSꢀ (CLK+, CLK–)
Temperature
Test Level
Min
Typ
Max
Unit
Logic Compliance
LVDS
2±0
Differential Input Voltage
High Level Input Current
Low Level Input Current
Input Common-Mode Voltage
Input Resistance
Full
Full
Full
Full
2±°C
2±°C
IV
VI
VI
IV
V
3±0
30
ꢃ±0
5±
mV p-p
µA
30
5±
µA
ꢀ.ꢀ2±
2.0
ꢀ.2±
ꢀ00
2
ꢀ.35±
V
kΩ
pF
Input Capacitance
V
LOGIC INPUTS (DFS, PDWN, SHARED_REF)
Logic ꢀ Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Full
Full
2±°C
2±°C
IV
IV
V
V
0.8
V
30
ꢃ
kΩ
pF
V
LOCK
LOGIC OUTPUTS (
)
Logic ꢀ Voltage
Logic 0 Voltage
Full
Full
IV
IV
2.ꢃ±
V
V
0.0±
DIGITAL OUTPUTS (Dꢀ+, Dꢀ–)
Logic Compliance
Differential Output Voltage
Output Offset Voltage
Output Coding
LVDS
2ꢁ0
ꢀ.ꢀ±
Full
Full
Full
VI
VI
VI
3±0
ꢀ.2±
ꢃꢃ0
ꢀ.3±
mV
V
Twos complement or binary
ꢀ Clock inputs are LVDS-compatible. They require external dc bias and cannot be ac-coupled.
Rev. 0 | Page ꢃ of 32
AD9289
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 3.0 V, conversion rate = 65 MSPS, 2 V p-p differential input, 1.0 V internal reference, AIN = –0.5 dBFS, unless
otherwise noted.
Table 4.
Parameter
Temp
Test Level
Min
Typ
Max
Unit
CLOCK
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS
Valid Time (tV)ꢀ
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO
Full
Full
Full
Full
VI
IV
VI
VI
ꢁ±
MSPS
MSPS
ns
ꢀ2
ꢁ.ꢂ
ꢁ.ꢂ
5.5
5.5
ns
Full
Full
Full
Full
Full
Full
Full
Full
Full
2±°C
2±°C
Full
IV
VI
V
V
V
0.±
ꢁ.ꢂ
<ꢀ.±
ꢀꢀ.ꢁ
CLK cycles
ns
ps
ps
ns
ns
ps
ps
ꢂ.0
2±0
2±0
ꢂ.0
)
)
DCO Propagation Delay (tCPD
DCO-to-Data Delay (tDATA
DCO-to-FCO Delay (tFRAME
Data-to-Data Skew (tDATA-MAX – tDATA-MIN
V
ꢂ.0
)
)
VI
VI
IV
V
V
IV
±ꢀ00
±ꢀ00
±ꢀ00
ꢀ.8
5
ꢁ
±±±0
±±00
±2±0
)
ps
µs
PLL Lock Time (tLOCK
Wake-Up Time
)
ms
CLK cycles
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
OUT-OF-RANGE RECOVERY TIME
2±°C
2±°C
2±°C
V
V
V
ꢃ.±
<ꢀ
ꢀ
ns
ps rms
CLK cycles
ꢀ
LOCK
Actual valid time is dependent on the moment when
goes low.
TIMING DIAGRAMS
N-1
AIN
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
STATIC
DCO+
STATIC
tFCO
tFRAME
FCO–
FCO+
STATIC
STATIC
STATIC
tDATA
D3
tPD
D1–
D1+
MSB D6
D5
D4
D2
D1 LSB MSB
STATIC
INVALID
(N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-7) (N-6)
LOCK
tV
Figure 2. Timing Diagram
Rev. 0 | Page ± of 32
AD9289
ABSOLUTE MAXIMUM RATINGS
Table 5.
EXPLANATION OF TEST LEVELS
With
Respect
I. 100% production tested.
Parameter
ELECTRICAL
AVDD
DRVDD
AGND
To
Min
Max
Unit
II. 100% production tested at 25°C and guaranteed by design
and characterization at specified temperatures.
AGND
–0.3
–0.3
–0.3
–3.ꢂ
–0.3
+3.ꢂ
+3.ꢂ
+0.3
+3.ꢂ
V
V
V
V
V
DRGND
DRGND
DRVDD
DRGND
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
AVDD
Digital Outputs (Dꢀ+,
Dꢀ–, DCO+, DCO–,
FCO+, FCO–)
DRVDD
V. Parameter is a typical value only.
DRVDD
AVDD
AVDD
AVDD
AVDD
LOCK, LVDSBIAS
CLK+, CLK–
VIN+, VIN–
PDWN, DFS, DTP
REFT, REFB,
DRGND
AGND
AGND
AGND
AGND
–0.3
–0.3
–0.3
–0.3
–0.3
V
V
V
V
V
VI. 100% production tested at 25°C and guaranteed by design
and characterization for industrial temperature range.
SHARED_REF, CML
VREF, SENSE
AGND
–0.3
–ꢃ0
AVDD
+8±
V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ENVIRONMENTAL
Operating
Temperature Range
(Ambient)
Maximum Junction
Temperature
Lead Temperature
(Soldering, ꢀ0 sec)
Storage
°C
ꢀ±0
°C
°C
°C
300
–ꢁ±
+ꢀ±0
Temperature Range
(Ambient)
Thermal
ꢃ0
°C/W
Impedanceꢀ
ꢀ θJA for a ꢃ-layer PCB with solid ground plane in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as ꢃ000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page ꢁ of 32
AD9289
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
Figure 3. BGA Top View (Looking Through)
Table 6. Pin Function Descriptions
Pin
Pin
No.
Aꢀ
Bꢀ
Mnemonic
Dꢀ–A
Dꢀ+A
Description
No.
D±
E±
Mnemonic
Description
ADC A Complement Digital Output
ADC A True Digital Output
Frame Clock Output (MSB Indicator)
True Output
Do Not Connect
Analog Ground
ADC A Analog Input—Complement
ADC A Analog Input—True
LVDS Output Bias Pin
Do Not Connect
Do Not Connect
Frame Clock Output (MSB Indicator)
Complement Output
Do Not Connect
Analog Ground
Analog Supply
Analog Ground
ADC B Analog Input—True
ADC B Complement Digital Output
ADC B True Digital Output
Digital Supply
Digital Ground
Analog Ground
AGND
AGND
REFT_B
REFB_B
VREF
Analog Ground
Analog Ground
Reference Buffer Decoupling (Positive)
Reference Buffer Decoupling (Negative)
Voltage Reference Input/Output
Do Not Connect
Do Not Connect
Digital Supply
Digital Ground
Analog Supply
Analog Ground
Analog Ground
ADC C Analog Input—Complement
ADC D Complement Digital Output
ADC D True Digital Output
Data Format Select
Analog Ground
Analog Ground
Analog Supply
Analog Ground
Cꢀ
FCO+
F±
G±
H±
Aꢁ
Bꢁ
Cꢁ
Dꢁ
Eꢁ
Dꢀ
Eꢀ
Fꢀ
Gꢀ
Hꢀ
A2
B2
C2
DNC
AGND
VIN–A
VIN+A
LVDSBIASꢀ
DNC
DNC
DNC
DRVDD
DRGND
AVDD
AGND
AGND
VIN–C
Dꢀ–D
Dꢀ+D
DFS2
AGND
AGND
AVDD
AGND
VIN+C
DNC
DNC
CLK+
CLK–
PDWN3
VIN–D
VIN+D
DTP3, ꢃ
DNC
FCO–
Fꢁ
Gꢁ
Hꢁ
A5
B5
C5
D5
E5
D2
E2
F2
DNC
AGND
AVDD
AGND
VIN+B
Dꢀ–B
G2
H2
A3
B3
C3
D3
E3
F3
G3
H3
Aꢃ
Bꢃ
Cꢃ
Dꢃ
F5
Dꢀ+B
G5
H5
A8
B8
C8
D8
E8
F8
G8
H8
DRVDD
DRGND
AGND
CML
SHARED_REF3
VIN–B
DNC
ADC C Analog Input—True
Do Not Connect
Do Not Connect
Common Mode Level Output ( = AVDD/2)
Shared Reference Control Bit
ADC B Analog Input—Complement
Do Not Connect
Do Not Connect
Data Clock Output—True
PLL Lock Output
Input Clock—True
Input Clock—Complement
Power Down Selection
ADC D Analog Input—Complement
ADC D Analog Input—True
Digital Test Pattern
DNC
DCO+
LOCK
AVDD
REFT_A
REFB_A
SENSE
Dꢀ–C
Eꢃ
Fꢃ
Gꢃ
Hꢃ
A±
B±
C±
Analog Supply
ꢀ LVDSBIAS use a 3.ꢂ kΩ resistor-to-analog ground to set the LVDS output
differential swing of 3±0 mV p-p.
Reference Buffer Decoupling (Positive)
Reference Buffer Decoupling (Negative)
Reference Mode Selection
ADC C Complement Digital Output
ADC C True Digital Output
2 DFS has an internal on-chip pull-down resistor and defaults to offset binary
output coding if untied. If twos complement output coding is desired then
tie this pin to AVDD.
3 To enable, tie this pin to AVDD. To disable, tie this pin to AGND.
ꢃ DTP has an internal on-chip pull-down resistor.
Dꢀ+C
DCO–
Data Clock Output—Complement
Rev. 0 | Page 5 of 32
AD9289
EQUIVALENT CIRCUITS
AVDD
DRVDD
VIN+, VIN–
V
V
D1–
D1+
V
V
AGND
DRGND
Figure 4. Equivalent Analog Input Circuit
Figure 7. Equivalent Digital Output Circuit
AVDD
DRVDD
CLK+, CLK–
LOCK
25Ω
375Ω
AGND
DRGND
LOCK
Figure 5. Equivalent Clock Input Circuit
Figure 8. Equivalent
Output Circuit
DRVDD
DFS, PDWN,
SHARED_REF
375Ω
DRGND
Figure 6. Equivalent Digital Input Circuit
Rev. 0 | Page 8 of 32
AD9289
TYPICAL PERFORMANCE CHARACTERISTICS
0
75
70
65
60
AIN = –0.5dBFS
SNR = 49.08dB
ENOB = 7.86 BITS
AIN = –0.5dBFS
2V p-p, SFDR (dBc)
SFDR = 70.55dBc
–20
–40
–60
1V p-p, SFDR (dBc)
55
–80
2V p-p, SNR (dB)
50
45
1V p-p, SNR (dB)
30 40
–100
0.0
4.1
8.1
12.2
16.3
20.3
24.4
28.4
32.5
10
20
50
ENCODE (MSPS)
60
70
FREQUENCY (MHz)
Figure 9. Single-Tone 32k FFT With fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Figure 12. SNR/SFDR vs. fSAMPLE, fIN = 2.4 MHz
0
75
70
65
60
AIN = –0.5dBFS
SNR = 48.93dB
ENOB = 7.83 BITS
2V p-p, SFDR (dBc)
–20
–40
–60
SFDR = 71.45dBc
AIN = –0.5dBFS
1V p-p, SFDR (dBc)
55
–80
2V p-p, SNR (dB)
1V p-p, SNR (dB)
50
45
–100
0.0
4.1
8.1
12.2
16.3
20.3
24.4
28.4
32.5
10
20
30
40
50
60
70
FREQUENCY (MHz)
ENCODE (MSPS)
Figure 10. Single-Tone 32k FFT With fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Figure 13. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
0
75
70
65
60
2V p-p, SFDR (dBc)
AIN = –0.5dBFS
AIN = –0.5dBFS
SNR = 48.8dB
ENOB = 7.8 BITS
–20
–40
–60
SFDR = 68.5dBc
1V p-p, SFDR (dBc)
55
–80
2V p-p, SNR (dB)
50
45
1V p-p, SNR (dB)
30 40
–100
0.0
4.1
8.1
12.2
16.3
20.3
24.4
28.4
32.5
10
20
50
ENCODE (MSPS)
60
70
FREQUENCY (MHz)
Figure 11. Single-Tone 32k FFT With fIN = 35 MHz, fSAMPLE = 65 MSP
Figure 14. SNR/SFDR vs. fSAMPLE, fIN = 35 MHz
Rev. 0 | Page ꢂ of 32
AD9289
75
75
60
70dB REFERENCE LINE
70
65
60
55
SFDR (dBc)
2V p-p, SNR (dB)
50
40
1V p-p, SFDR (dBc)
30
20
10
1V p-p, SNR (dB)
50
45
2V p-p, SFDR (dBc)
SNR (dB)
0
–40
–35
–30
–25
–20
–15
–10
–5
0
0.1
1
10
FREQUENCY (MHz)
100
ANALOG INPUT LEVEL (dBFS)
Figure 15. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS,
IN = 2.4 MHz
Figure 18. SNR/SFDR vs. fIN, fSAMPLE = 65 MHz
f
0
–20
–40
–60
75
60
AIN1 AND AIN2 = –7.0dBFS
SFDR = 69.9dBc
IMD2 = 74.9dBc
IMD3 = 72.9dBc
70dB REFERENCE LINE
2V p-p, SNR (dB)
50
40
1V p-p, SFDR (dBc)
30
20
10
0
1V p-p, SNR (dB)
–80
2V p-p, SFDR (dBc)
–100
0.0
4.1
8.1
12.2
16.3
20.3
24.4
28.4
32.5
–40
–35
–30
–25
–20
–15
–10
–5
0
FREQUENCY (MHz)
ANALOG INPUT LEVEL (dBFS)
Figure 16. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS,
IN = 10.3 MHz
Figure 19. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
SAMPLE = 65 MSPS
f
f
75
60
80
70
60
50
40
30
70dB REFERENCE LINE
2V p-p, SNR (dB)
50
40
1V p-p, SFDR (dBc)
70dB REFERENCE LINE
30
20
10
0
1V p-p, SNR (dB)
SFDR (dBc)
20
2V p-p, SFDR (dBc)
10
0
–40
–35
–30
–25
–20
–15
–10
–5
0
–40
–35
–30
–25
–20
–15
–10
–5
0
ANALOG INPUT LEVEL (dBFS)
ANALOG INPUT LEVEL (dBFS)
Figure 17. SNR/SFDR vs. Analog Input Level, fSAMPLE = 65 MSPS,
IN = 35 MHz
Figure 20. Two-Tone SFDR vs. Analog Input Level with fIN1 = 15 MHz and
IN2 = 16 MHz, fSAMPLE = 65 MSPS
f
f
Rev. 0 | Page ꢀ0 of 32
AD9289
0.5
0.4
0.3
0.2
0.1
75
2V p-p, SFDR (dBc)
70
65
1V p-p, SFDR (dBc)
0
–0.1
–0.2
–0.3
60
55
2V p-p, SINAD (dB)
1V p-p, SINAD (dB)
50
45
–0.4
–0.5
0
32
64
96
128
160
192
224
256
–40
–20
0
20
49
60
80
CODE
TEMPERATURE (°C)
Figure 21. SINAD/SFDR vs. Temperature, fSAMPLE = 65 MSPS, fIN 10.3 MHz
Figure 23. Typical DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
0.5
15
10
0.4
0.3
0.2
0.1
5
SHARED REF MODE
(PIN TIED HIGH)
0
–0.1
–0.2
–0.3
0
–5
SHARED REF MODE
(PIN TIED LOW)
–10
–15
–0.4
–0.5
0
32
64
96
128
CODE
160
192
224
256
–40
–20
0
20
49
60
80
TEMPERATURE (°C)
Figure 24. Typical INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Figure 22. Gain vs. Temperature
Rev. 0 | Page ꢀꢀ of 32
AD9289
TERMINOLOGY
Analog Bandwidth
Effective Number of Bits (ENOB)
Analog Bandwidth is the analog input frequency at which the
spectral power of the fundamental frequency (as determined by
the FFT analysis) is reduced by 3 dB from full scale.
For a sine wave, SINAD can be expressed in terms of the
number of bits. Using the following formula, it is possible to
obtain a measure of performance expressed as N, the effective
number of bits:
Aperture Delay
N = (SINAD – 1.76)/6.02
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the 50% point rising
edge of the clock input to the time at which the input signal is
held for conversion.
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
Aperture Uncertainty (Jitter)
Gain Error
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as frequency-dependent noise
on the ADC input.
The largest gain error is specified and is considered the
difference between the measured and ideal full-scale input
voltage range.
Clock Pulse Width and Duty Cycle
Gain Matching
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve a rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Expressed in %FSR. Computed using the following equation:
FSRmax− FSRmin
FSRmax+ FSRmin
GainMatching =
×100%
⎛
⎜
⎝
⎞
⎟
⎠
2
where FSRMAX is the most positive gain error of the ADCs, and
FSRMIN is the most negative gain error of the ADCs.
Crosstalk
Crosstalk is defined as the coupling of a channel when all
channels are driven by a full-scale signal.
Second and Third Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
second or third harmonic component, reported in dBc.
Differential Analog Input Capacitance
The complex impedance simulated at each analog input port.
Differential Analog Input Voltage Range
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from
the middle of each particular code to the true straight line.
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a pin and
subtracting the voltage from a second pin that is 180° out of
phase. Peak-to-peak differential is computed by rotating the
input phase 180° and taking the peak measurement again. The
difference is computed between both peak measurements.
Offset Error
The largest offset error is specified and is considered the
difference between the measured and ideal voltage at the analog
input that produces the midscale code at the outputs.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to an 8-bit resolution indicates that all 256 codes,
respectively, must be present over all operating ranges.
Rev. 0 | Page ꢀ2 of 32
AD9289
Signal-to Noise and Distortion (SINAD) Ratio
Offset Matching
SINAD is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for SINAD is expressed in decibels.
Expressed in mV. Computed using the following equation:
OffsetMatching = OFFMAX − OFFMIN
where OFFMAX is the most positive offset error and OFFMIN is the
most negative offset error.
Signal-to-Noise Ratio (SNR)
Out-of-Range Recovery Time
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Spurious-Free Dynamic Range (SFDR)
Output Propagation Delay
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX
.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It may be reported in dBc
(i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full scale).
Rev. 0 | Page ꢀ3 of 32
AD9289
THEORY OF OPERATION
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can
be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependent on
the application.
Each A/D converter in the AD9289 architecture consists of a
front send sample-and-hold amplifier (SHA) followed by a
pipe-lined, switched capacitor ADC. The pipelined ADC is
divided into two sections, consisting of six 1.5-bit stages and a
final 2-bit flash. Each stage provides sufficient overlap to correct
for flash errors in the preceding stages. The quantized outputs
from each stage are combined into a final 8-bit result in the
digital correc-tion logic. The pipelined architecture permits the
first stage to operate on a new input sample, while the
remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
The analog inputs of the AD9289 are not internally dc biased. In
ac-coupled applications, the user must provide this bias exter-
nally. Setting the device so that VCM = AVDD/2 is recommended
for optimum performance, but the device functions over a
wider range with reasonable performance (see Figure 26 and
Figure 27).
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor digital-
to-analog converter (DAC) and interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
75
2V p-p, SFDR (dBc)
70
1V p-p, SFDR (dBc)
65
60
55
50
45
The input stage contains a differential SHA that can be config-
ured as ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data and carries out the
error correction. The data is serialized and aligned to the frame,
output clock, and lock detection circuitry.
2V p-p, SNR (dB)
1V p-p, SNR (dB)
40
35
ANALOG INPUT AND REFERENCE OVERVIEW
0
0.5
1.0
1.5
2.0
2.5
3.0
ANALOG INPUT COMMON-MODE VOLTAGE (V)
The analog input to the AD9289 is a differential-switched
capacitor SHA that has been designed for optimum perfor-
mance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance, as shown in Figure 26 sand Figure 27.
An input common-mode voltage of midsupply minimizes
signal dependent errors and provides optimum performance.
Figure 26. SNR, SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz,
f
SAMPLE = 65 MSPS
75
2V p-p, SFDR (dBc)
70
65
60
H
1V p-p, SFDR (dBc)
55
50
45
S
S
2V p-p, SNR (dB)
1V p-p, SNR (dB)
VIN+
VIN–
C
PAR
40
35
S
0
0.5
1.0
1.5
2.0
2.5
3.0
C
PAR
ANALOG INPUT COMMON-MODE VOLTAGE (V)
S
Figure 27. SNR, SFDR vs. Common-Mode Voltage, fIN = 35 MHz,
SAMPLE = 65 MSPS
f
H
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
Figure 25. Switched-Capacitor SHA Input UPDATE
The clock signal alternately switches the SHA between sample
mode and hold mode (see Figure 25). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
Rev. 0 | Page ꢀꢃ of 32
AD9289
An internal reference buffer creates the positive and negative
reference voltages, REFT and REFB, respectively, that defines
the span of the ADC core. The output common-mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as
AVDD
VIN+
R
R
2Vp-p
49.9Ω
AD9289
C
AVDD
1kΩ
VIN–
AGND
REFT = 1/2 (AVDD + VREF)
1kΩ
REFB = 1/2 (AVDD − VREF)
0.1µF
Span = 2 × (REFT − REFB) = 2 × VREF
Figure 29. Differential Transformer-Coupled Configuration
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance. Figure 30 details a typical single-
ended input configuration.
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V or adjusted within the same range, as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved by setting the AD9289
to the largest input span of 2 V p-p.
The SHA should be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined in Figure 26 and Figure 27.
10µF
AVDD
1kΩ
R
VIN+
0.1µF
1kΩ
2V p-p
49.9Ω
AD9289
C
Differential Input Configurations
AVDD
R
Optimum performance is achieved by driving the AD9289 in a
differential input configuration. For baseband applications, the
AD8351 differential driver provides excellent performance and
a flexible interface to the ADC (see Figure 28).
1kΩ
1kΩ
VIN–
AGND
10µF
0.1µF
Figure 30. Single-Ended Input Configuration
1kΩ
1kΩ
10kΩ
0.1µF
0.1µF
1kΩ
1kΩ
CLOCK INPUT AND CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Typically, a 5% tolerance is
required on the clock duty cycle to maintain dynamic perfor-
mance characteristics. The AD9289 has a self-contained clock
duty cycle stabilizer that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows a wide range of clock input duty cycles
without affecting the performance of the AD9289.
AVDD
VIN–
0.1µF
0.1µF
V
CM
10Ω
R
PWUP
GP1
GP2
25Ω
50Ω
25Ω
AD8351
C
AD9289
R
1V p-p
VIN+
AGND
10Ω
0.1µF
AVDD
1.2kΩ
1kΩ
1kΩ
Figure 28. Differential Input Configuration Using the AD8351
An on-board phase-locked loop (PLL) multiplies the input
clock rate for the purpose of shifting the serial data out. As a
result, any change to the sampling frequency requires a
minimum of 100 clock periods to allow the PLL to reacquire
and lock to the new rate.
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9289. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. An
example of this is shown in Figure 29.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
Rev. 0 | Page ꢀ± of 32
AD9289
By asserting the PDWN pin high, the AD9289 is placed in
standby mode. In this state, the ADC typically dissipates 7 mW.
During standby the LVDS output drivers are placed in a high
impedance state. Reasserting the PDWN pin low returns the
AD9289 into its normal operational mode.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fA) due only to aperture jitter (tA) can be
calculated with the following equation:
SNR degradation = 20 × log10 [1/2 × π × fA × tA]
In standby mode, low power dissipation is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately 1 s to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
In the equation, the rms aperture jitter, tA, represents the root
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Applications that require undersampling are particularly
sensitive to jitter.
The LVDS clock input should be treated as an analog signal in
cases where aperture jitter may affect the dynamic range of the
AD9289. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the
last step.
Digital Outputs
The AD9289’s differential outputs conform to the ANSI-644
LVDS standard. To set the LVDS bias current place a resistor
(RSET is nominally equal to 3.9 kΩ) to ground at the
LVDSBIAS pin. The RSET resistor current is derived on-chip
and sets the output current at each output equal to a nominal
3.5 mA. A 100 Ω differential termination resistor placed at the
LVDS receiver inputs results in a nominal 350 mV swing at
the receiver. To adjust the differential signal swing, simply
change the resistor to a different value, as shown in Table 7.
The AD9289 can also support a single-ended CMOS clock.
Refer to the evaluation board schematics to enable this feature.
Power Dissipation and Standby Mode
As shown in Figure 31, the power dissipated by the AD9289 is
proportional to its sample rate. The digital power dissipation
does not vary because it is determined primarily by the strength
of the digital drivers and the load on each output bit.
Table 7. LVDSBIAS Pin Configuration
RSET
Differential Output Swing
3.ꢁk
3.ꢂk (Default)
ꢃ.3k
35± mV p-p
3±0 mV p-p
32±mV p-p
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in
Figure 31 was collected while a 5 pF load was placed on each
output driver.
The AD9289’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capa-
bility for superior switching performance in noisy environ-
ments. Single point-to-point net topologies are recommended
with a 100 Ω termination resistor placed as close to the receiver
as possible. It is recommended to keep the trace length no
longer than 12 inches and to keep differential output traces
close together and at equal lengths.
The analog circuitry of the AD9289 is optimally biased to
achieve excellent performance while affording reduced
power consumption.
600
180
160
140
120
100
550
I
AVDD
The format of the output data can be selected as offset binary or
twos complement. A quick example of each output coding
format can be found in Table 8. The DFS pin is used to set the
format (see Table 9).
500
450
POWER
80
60
40
Table 8. Digital Output Coding
VIN+ −
VIN− Input
Span = 2 V
VIN+ −
Digital
Digital
VIN− Input
Span = 1 V
p-p (V)
Output Offset
Binary
(D7...D0)
Output Twos
Complement
(D7...D0)
400
350
I
DRVDD
20
0
Code p-p (V)
2±±
ꢀ28
ꢀ25
0
ꢀ.000
0
0.±00
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ000 0000
0ꢀꢀꢀ ꢀꢀꢀꢀ
0000 0000
0ꢀꢀꢀ ꢀꢀꢀꢀ
0000 0000
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ000 0000
10
20
30
40
50
60
70
0
ENCODE (MSPS)
−0.0058ꢀ
−ꢀ.00
−0.003ꢂꢀ
−0.±000
Figure 31. Supply Current vs. fSAMPLE for fIN = 10.3 MHz
Rev. 0 | Page ꢀꢁ of 32
AD9289
Table 9. Data Format Configuration
Voltage Reference
DFS Mode
Data Format
A stable and accurate 0.5 V voltage reference is built into the
AD9289. The input range can be adjusted by varying the refer-
ence voltage applied to the AD9289, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
AVDD
AGND
Twos complement
Offset binary
Timing
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to eight
bits times the sample clock rate, with a maximum of 520 MHz
(8 bits x 65 MSPS = 520 MHz). The lowest typical conversion
rate is 12 MSPS.
The shared reference mode (see Figure 32) allows the user to
externally connect the reference buffers from the quad ADC for
better gain and offset matching performance. If the ADCs are to
function independently, the reference decoupling can be treated
independently and can provide better isolation between the four
channels. To enable shared reference mode, the SHARED_REF
pin must be tied high and external reference buffer decoupling
pins must be externally shorted. (REFT_A must be externally
shorted to REFT_B and REFB_A must be shorted to REFB_B.)
Note that Channels A and B are referenced to REFT_A and
REFB_A and Channels C and D are referenced to REFT_B
and REFB_B.
Two output clocks are provided to assist in capturing data from
the AD9289. The DCO is used to clock the output data and is
equal to four times the sampling clock (CLK) rate. Data is
clocked out of the AD9289 and can be captured on the rising
and falling edges of the DCO that supports double-data rate
operation (DDR). The frame clock out (FCO) signals the start
of a new output byte and is equal to the sampling clock rate. See
the timing diagram shown in Figure 2 for more information.
Table 10. Reference Settings
Resulting
Pin
LOCK
SENSE
Voltage
Resulting
VREF (V)
Differential Span
(V p-p)
Selected Mode
The AD9289 contains an internal PLL that is used to generate
External
Reference
AVDD
N/A
2 × External
Reference
the DCO. When the PLL is locked, the
indicating valid data on the outputs.
signal will be low,
LOCK
Internal,
VREF
0.±
ꢀ.0
ꢀ V p-p FSR
If for any reason the PLL loses lock, the
signal goes high
LOCK
Programmable
0.2 V to
VREF
0.± ×
(ꢀ + R2/Rꢀ)
2 × VREF
2.0
as soon as the lock circuitry detects an unlocked condition.
While the PLL is unlocked, the data outputs and DCO remains
Internal,
2 V p-p FSR
AGND to
0.2 V
ꢀ.0
in the last known state. If the
signal goes high in the
LOCK
middle of a byte, no data or DCO signals will be available for
the rest of the byte. It takes at least 1.8 µs at 65 MSPS to regain
lock once it is lost. Note that regaining lock is sample rate-
dependent and takes at least 100 input periods after the PLL
acquires the input clock.
Internal Reference Connection
A comparator within the AD9289 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 10. If SENSE is grounded,
the reference amplifier switch is connected to the internal resis-
tor divider (see Figure 33), setting VREF to 1 V. Connecting the
SENSE pin to the VREF pin switches the amplifier output to the
SENSE pin, configuring the internal op amp circuit as a voltage
follower and providing a 0.5 V reference output. If an external
resistor divider is connected as shown in Figure 34 the switch is
again set to the SENSE pin. This puts the reference amplifier in
a noninverting mode with the VREF output defined as
Once the PLL regains lock the DCO starts. The first valid data
byte is indicated by the FCO signal. The FCO rising edge occurs
0.5 to <1.5 input clock periods after
goes low.
LOCK
CML Pin
A common-mode level output is available at Pin F3. This output
self biases to AVDD/2. This is a relatively high impedance
output (2.5k nominal), which may need to be considered when
used as a reference.
R2
R1
⎛
⎝
⎞
⎟
⎠
VREF = 0.5× 1 +
⎜
DTP Pin
In all reference configurations, REFT_A and REFT_B and
REFB_A and REFB_B establish their input span of the ADC
core. The input range of the ADC always equals twice the
voltage at the reference pin for either an internal or an external
reference.
When the digital test pattern (DTP) pin is enabled (pulled to
AVDD), all of the ADC channel outputs shift out the following
pattern: 11000000. The FCO and DCO outputs still work as
usual while all channels shift out the test pattern. This pattern
allows the user to perform timing alignment adjustments
between the DCO and the output data.
Rev. 0 | Page ꢀ5 of 32
AD9289
VIN+A (+B)
VIN–A (–B)
VIN+A (+B)
VIN–A (–B)
REFT_A
REFT_A
0.1µF
0.1µF
0.1µF
0.1µF
+
+
A CORE
B CORE
A CORE
B CORE
10µF
10µF
REFB_A
REFB_A
V
V
REF
REF
0.1µF
0.1µF
V
V
REF
REF
10µF
0.1µF
10µF
0.1µF
R2
SELECT
LOGIC
SELECT
LOGIC
SENSE
SENSE
R1
0.5V
0.5V
VIN+C (+D)
VIN–C (–D)
VIN+C (+D)
VIN–C (–D)
REFT_B
REFT_B
V
V
REF
REF
0.1µF
0.1µF
0.1µF
0.1µF
+
+
C CORE
D CORE
C CORE
D CORE
10µF
10µF
REFB_B
REFB_B
AVDD
SHARED_REF
CONTROL
CONTROL
SHARED_REF
Figure 32. Shared Reference Mode Enabled
Figure 34. Programmable Reference Configuration
VIN+A (+B)
VIN–A (–B)
If the internal reference of the AD9289 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 35
depicts how the internal reference voltage is affected by loading.
REFT_A
0.1µF
0.1µF
+
A CORE
B CORE
10µF
REFB_A
V
0.05
REF
0.1µF
V
REF
0
10µF
0.1µF
–0.05
SELECT
LOGIC
V
= 0.5V
REF
–0.10
–0.15
–0.20
–0.25
–0.30
SENSE
0.5V
V
= 1.0V
REF
VIN+C (+D)
VIN–C (–D)
REFT_B
V
REF
–0.35
–0.40
0.1µF
0.1µF
+
C CORE
D CORE
10µF
0
0.5
1.0
I
1.5
(mA)
2.0
2.5
REFB_B
LOAD
SHARED_REF
CONTROL
Figure 35. VREF Accuracy vs. Load
Figure 33. Internal Reference Configuration
Rev. 0 | Page ꢀ8 of 32
AD9289
External Reference Operation
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT_A and REFT_B and
REFB_A and REFB_B , for the ADC core. The input span is
always twice the value of the reference voltage; therefore, the
external reference must be limited to a maximum of 1 V.
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
characteristics. Figure 36 shows the typical drift characteristics
of the internal shared reference in both 1 V and 0.5 V modes.
0.15
V
= 0.5V
0.10
0.05
0
REF
Power and Ground Recommendations
V
= 1.0V
REF
When connecting power to the AD9289, it is recommended that
two separate 3.0 V supplies be used. One for analog (AVDD)
and one for digital (DRVDD). If only one supply is available
then it should be routed to the AVDD first and tapped off and
isolated with a ferrite bead or filter choke with decoupling
capacitors proceeding. One may want to use several different
decoupling capacitors to cover both high and low frequencies.
These should be located close the point of entry at the pc board
level as well as close to the parts with minimal trace length.
–0.05
–0.10
–0.15
–0.20
–0.25
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
A single pc board ground plane should be sufficient when using
the AD9289. With proper decoupling and smart partitioning of
the pc board’s analog, digital, and clock sections, optimum
performance is easily achieved.
Figure 36. Typical VREF Drift
Rev. 0 | Page ꢀꢂ of 32
AD9289
EVALUATION BOARD
the signal sources that are used have very low phase noise
(< 1 ps rms jitter) to realize the ultimate performance of the
converter. Proper filtering of the analog input signal to
remove harmonics and lower the integrated or broadband
noise at the input is also necessary to achieve the specified
noise performance.
The AD9289 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially
through a transformer (default) or the AD8351 driver. Provi-
sions have also been made to drive the ADC single-ended.
Separate power pins are provided to isolate the DUT from the
support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 37 shows the typical bench characterization setup used
to evaluate the ac performance of the AD9289. It is critical that
See Figure 37 to Figure 47 for complete schematics and layout
plots, which demonstrate the routing and grounding techniques
that should be applied at the system level.
3.0V
3.0V
3.3V
–
+
–
+
–
+
HSC-ADC-FPGA
HIGH-SPEED
DE-SERIALIZATION
BOARD
HSC-ADC-EVAL-DC
FIFO DATA
CAPTURE
PC
RUNNING
ADC
ROHDE AND SCHWARZ,
SMHU,
BOARD
ANALYZER
BAND-PASS
FILTER
XFMR
INPUT
2V p-p SIGNAL
SYNTHESIZER
CHA–CHD
8-BIT
SERIAL
LVDS
2 CH
8-BIT
PARALLEL
CMOS
AD9289
USB
CONNECTION
EVALUATION BOARD
ROHDE AND SCHWARZ,
SMHU,
CLK
2V p-p SIGNAL
SYNTHESIZER
Figure 37. Evaluation Board Connections
Rev. 0 | Page 20 of 32
AD9289
U7
D N C
D N C
C H D
C H D
D
D 1 +
A 2
B 7
A 7
D – D 1
B 2
C H A
C H A
F C O
F C O
A – D 1
D N C
A 1
B 1
B 8
A
D 1 +
F C O
F C O +
D N C
D N C
D N C
A 8
E 8
–
W N P D
C 2
C 1
D 2
D 1
F 1
G 1
E 1
E 2
H 2
H 3
F 2
G 2
C L K +
C 8
D 8
C 7
F 8
–
C L K
D F S
A _ N V I
A _ N V I
D _ N V I
A – N V I
A + N V I
D – N V I
D + N V I
D _ N V I
G 8
A G N D
A G N D
B + N V I
A G N D
D 7
A G N D
E 7
H 7
H 6
E 4
C _ N V I
C _ N V I
D D
C + N V I
C – N V I
D D A V
B _ N V I
B _ N V I
B – N V I
D D A V
D D
D U T _ A V
D U T _ A V
A G N D
A G N D
E 5
Figure 38. Evaluation Board Schematic, DUT, VREF, and Clock Inputs
Rev. 0 | Page 2ꢀ of 32
AD9289
J P 2 0
J P 1 9
J P 1 8
J P 2 6
J P 2 9
J P 2 8
J P 2 1 J P 2 4
J P 2 5 J P 2 7
Figure 39. Evaluation Board Schematic, DUT Analog Input
Rev. 0 | Page 22 of 32
AD9289
A D 8 3 5 1
A D 8 3 5 1
A D 8 3 5 1
A D 8 3 5 1
Figure 40. Evaluation Board Schematic, Optional DUT Analog Input Drive
Rev. 0 | Page 23 of 32
AD9289
T P 1 8
T P 1 6
T P 1 5
T P 1 4
J P 1
J P 2
J P 4
Figure 41. Evaluation Board Schematic, Power, and Decoupling
Rev. 0 | Page 2ꢃ of 32
AD9289
Figure 42. Evaluation Board Layout, Primary Side
Figure 43. Evaluation Board Layout, Primary Side (With Ground Copper Pour)
Rev. 0 | Page 2± of 32
AD9289
Figure 44. Evaluation Board Layout, Ground Plane
Figure 45. Evaluation Board Layout, Power Plane
Rev. 0 | Page 2ꢁ of 32
AD9289
Figure 46. Evaluation Board Layout, Secondary Side
Figure 47. Evaluation Board Layout, Secondary Side (With Ground Copper Pour)
Rev. 0 | Page 25 of 32
AD9289
Table 11. Evaluation Board Bill of Materials (BOM)
Qnty.
per
Board
Item
REFDES
Device
Package
Value
Manufacturing
Mfg. Part Number
ꢀ
ꢀ
ADꢂ28ꢂ BGA
REVA/PCB
PCB
PCB
PCB
PCSM
PCSM
2
3
ꢀ
8
Assembly
Rꢃꢁ, Rꢃ8, Rꢁ0, Rꢁꢀ,
Rꢂ8, Rꢂꢂ, Rꢀꢀ3, Rꢀꢀꢃ
R±, R5, R8, Rꢂ, Rꢀ0,
Rꢀ5, R33, R3ꢂ
R22,Rꢃꢂ, R±2, R±±,
R5ꢂ, Rꢂ2, Rꢀ0ꢀ, Rꢀ0ꢁ
Rꢀꢀ,Rꢀꢃ, R23, R25,
R3ꢀ, R3ꢃ, Rꢃꢃ, Rꢃ5
Protronics
Yageo America
Protronics
ꢂC0ꢃ02ꢀA0R00JLHF3
RES_ꢃ02
RES_ꢃ02
RES_ꢃ02
RES_ꢃ02
ꢃ02
ꢃ02
ꢃ02
ꢃ02
0
ꢃ
±
ꢁ
8
8
8
ꢀ0
2±
33
Susumu Co Ltd
Susumu Co Ltd
Susumu Co Ltd
RR0±ꢀ0R-ꢀ00-D
RR0±ꢀ0R-2ꢃ0-D
RR0±ꢀ0R-330-D
5
8
ꢂ
ꢃ
ꢀ
8
R38, R±ꢁ, Rꢂꢀ, Rꢀ05
R53
Rꢃ±, R±0, R±5, R±8,
RES_ꢃ02
RES_ꢃ02
RES_ꢃ02
ꢃ02
ꢃ02
ꢃ02
±0
ꢀ00
ꢀK
Panasonic-ECG
Yageo America
Panasonic-ECG
ERJ-LꢀꢃKF±0MU
ꢂC0ꢃ02ꢀAꢀ000FLHF3
ERJ-2GEJꢀ02X
Rꢂ3, Rꢂꢃ, Rꢀ08, Rꢀꢀꢀ
ꢀ0
ꢀꢀ
ꢃ
ꢀ3
R3±, R±3, R8ꢀ, Rꢀ03
RES_ꢃ02
RES_ꢃ02
ꢃ02
ꢃ02
ꢀ.2K
ꢀ0K
Panasonic-ECG
Susumu Co Ltd
ERJ-2GEJꢀ22X
RR0±ꢀ0P-ꢀ03-D
Rꢁ, R32, R3ꢁ, R±ꢀ,
R±ꢃ, R52, R5±, R58,
Rꢂ0, Rꢀ00, Rꢀ0ꢃ, R35,
R5ꢁ
ꢀ2
ꢁ
Rꢁ2, Rꢁ3, Rꢁꢃ, Rꢁ±,
Rꢁꢁ, R5ꢀ
BRESꢁ03
ꢁ03
0
Panasonic-ECG
ERJ-3GEY0R00V
ꢀ3
ꢀꢃ
ꢀ
±
Rꢀ02
Rꢀ±, R30, Rꢃꢀ, Rꢃ2,
R83
BRESꢁ03
BRESꢁ03
ꢁ03
ꢁ03
22
±0
Susumu Co Ltd
Susumu Co Ltd
RR08ꢀꢁQ-220-D
RR08ꢀꢁQ-ꢃꢂRꢂ-D-ꢁ8R
ꢀ±
23
Rꢀ, Rꢀ2, Rꢀ3, Rꢀꢁ,
Rꢀ8, Rꢀꢂ, R20, R2ꢀ,
R2ꢃ, R2ꢂ, Rꢃ0, Rꢃ3,
R±ꢂ, Rꢁ8, Rꢁꢂ, R50,
R5ꢃ, R55, R80, R82,
R8ꢃ, Rꢀ0ꢂ, Rꢀꢀ0
BRESꢁ03
ꢁ03
ꢀK
Susumu Co Ltd
RR08ꢀꢁP-ꢀ02-D
ꢀꢁ
ꢀ5
ꢀ8
2
ꢃ
3ꢁ
Rꢂꢁ, Rꢂ5
Cꢀ0, C2ꢀ, C30, Cꢃꢀ
BRESꢁ03
CAPꢃ02
CAPꢃ02
ꢁ03
ꢃ02
ꢃ02
XXX
20PF
ꢀUF
Kemet
Panasonic-ECG
C0ꢃ02C220J±GACTU
ECJ-0EFꢀCꢀ0ꢃZ
Cꢀ, C3±, Cꢃꢃ, Cꢃ5,
C80, C2±0, Cꢁ00,
Cꢀꢀ, Cꢀ2, Cꢀꢃ, C35,
Cꢃ0, Cꢃ8, Cꢁ3, Cꢁꢃ,
Cꢁ±, Cꢁꢁ, Cꢁ5, Cꢁ8,
Cꢁꢂ, C50, C5ꢀ, C52,
C53
ꢀꢂ
ꢀ5
C2, C3, Cꢃ,
BYPASSCAP
ꢁ03
0.ꢀUF
Kemet
C0ꢁ03Cꢀ0ꢃZ3VACTU
C±, Cꢁ, C5, Cꢀ±, Cꢀꢁ,
Cꢀ8, C20, C2±, C2ꢂ,
C3ꢁ, C±3, Cꢀ08,
Cꢀꢀ0, Cꢀ83
20
2ꢀ
22
3
3
ꢀꢁ
Cꢀ00, Cꢀ20, Cꢀꢁ3
Cꢀ50, Cꢀ5ꢀ, Cꢀ5ꢁ
Lꢀ, L2 ,L3, Lꢃ, Lꢁ, Lꢂ,
Lꢀ0, Lꢀꢀ, Lꢀ2, Lꢀ3,
Lꢀꢂ, L20, L2ꢀ, L22,
L25, L28
TANTALUMB
TANTALUMB
INDUCTOR_ꢁ ꢁ03
80±
TꢃꢂꢀB0ꢁK0ꢀ
ꢀ0UF
ꢀ0UF
ꢀ20NH
Panasonic-ECG
Kemet
Murata
ECJ-2FB0Jꢀ0ꢁM
TꢃꢂꢀBꢀ0ꢁK0ꢀꢁAS
BLMꢀ8BB5±0SNꢀD
23
2ꢃ
3
ꢀ
L±,L5,L8
Pꢁ
INDꢀ2ꢀ0
PTMICROꢁ
ꢀ2ꢀ0
PTMICROꢁ
ꢀ0UH
ꢁ-Pole PCB
Header
Panasonic-ECG
Wieland
ELJ-SAꢀ00KF
Z±.±3ꢀ.3ꢁ2±.0
Rev. 0 | Page 28 of 32
AD9289
Qnty.
per
Board
Item
REFDES
Device
Package
Value
Manufacturing
Mfg. Part Number
ꢀ
ꢁ-Pole PCB
Connector
Wieland
2±.ꢁ00.±ꢁ±3.0
2±
±
Pꢀ, P2, P3, Pꢃ, P±
SMBMST
SMB
SMBMST
Amphenol-RF
Division
ꢂ0ꢀ-ꢀꢃꢃ-8RFX
2ꢁ
25
ꢃ
ꢀ
Tꢀ, T2, T3, Tꢃ
Uꢀ5
ADTꢀ-ꢀWT
HEADER
CD±ꢃ2_Xꢁ±
2MMSMT-852 WMꢀ8ꢀ±8-
ND
ADTꢀ-ꢀWT
Minicircuits
Molex/Waldom
Electronics Corp
ADTꢀ-ꢀWT
852ꢁ5-08±0
28
2ꢂ
ꢀ
ꢀ
U±
Jꢁ
DIFF_CONN
MINIJMPR3
FCN_2ꢁ8M0ꢀ DIFF_CONN
2MMSMT-852 MINIJMPR3
Fujitsu
Molex/Waldom
Electronics Corp
FCN-2ꢁ8M0ꢀ2-G/ꢀD
852ꢁ5-08±0
30
3ꢀ
2
2
JPꢀ, JP2
SGLJMPR
ꢀꢀ/ꢃ"
SGLJMPR
NYLON
852ꢁ5-08±0
ꢀ/ꢃ" ꢁ-32
Samtec
RAF
TSW-ꢀ20-05-G-S
ꢃ0ꢃ0-ꢁ32-N
STANDOFF
32
33
2
ꢀ
ꢁ-32NUTS
5ꢃVHC0ꢃMTC TSSOP-ꢀꢃ
NYLON
ꢁ-32
5ꢃVHC0ꢃ
RAF
Fairchild
Semiconductor
Fairchild
Semiconductor
ADI
30±8-N
5ꢃVHC0ꢃMTC
Uꢀ
U2
Uꢃ
3ꢃ
3±
ꢀ
ꢀ
FINꢀ0ꢀ5M
MO8A_(SOIC) FINꢀ0ꢀ5M
FINꢀ0ꢀ5M
ADꢂ28ꢂBBC-
ꢁ±
ꢂ28ꢂBGA
ꢂ28ꢂBGA
ADꢂ28ꢂBBC-ꢁ±
3ꢁ
35
ꢀ
ꢃ
Uꢁ
ADR±ꢀ0
AD83±ꢀARM
SOT23
MSOP0ꢀ0
ADR±ꢀ0
AD83±ꢀ
ADI
ADI
ADR±ꢀ0
AD83±ꢀARM
U5, U8, Uꢂ, Uꢀ0
Rev. 0 | Page 2ꢂ of 32
AD9289
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
8.00
BSC SQ
8
7
6
5
4
3
2
1
A
B
C
D
E
F
BALL A1
INDICATOR
5.60
BSC SQ
TOP VIEW
0.80
BSC
G
H
BOTTOM VIEW
DETAIL A
DETAIL A
1.70
1.55
1.35
1.31
1.21
1.10
0.34 NOM
0.25 MIN
COPLANARITY
0.12
0.55
0.50
0.45
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-205-BA
Figure 48. 64-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-64-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADꢂ28ꢂBBC
ADꢂ28ꢂ-ꢁ±EB
–ꢃ0°C to +8±°C
ꢁꢃ-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
BC-ꢁꢃ-ꢀ
Rev. 0 | Page 30 of 32
AD9289
NOTES
Rev. 0 | Page 3ꢀ of 32
AD9289
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03682-0-10/04(0)
Rev. 0 | Page 32 of 32
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