AD9387NK [ADI]
High Performance, Low Power HDMI⑩/DVI Transmitter; 高性能，低功耗HDMI⑩ / DVI发送器
| 型号： | AD9387NK |
| 厂家： | 
ADI |
| 描述： | High Performance, Low Power HDMI⑩/DVI Transmitter |
| 文件： | 总12页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance, Low Power
HDMI™/DVI Transmitter
Preliminary Technical Data
AD9387NK
FEATURES
FUNCTIONAL BLOCK DIAGRAM
INT
SCL SDA
MCL MDA
General
Low power HDMI/DVI transmitter ideal for portable
applications
Compatible with HDMI v. 1.3, DVI v. 1.0, and HDCP v. 1.2
Single 1.8 V power supply
INTERRUPT
HANDLER
HPD
2
I C
SLAVE
HDCP
CORE
Video/audio inputs accept logic levels from 1.8 V to 3.3 V
64-lead LFCSP, Pb-free package
76-ball CSP_BGA, Pb-free package
Digital video
80 MHz operation supports all resolutions from 480i to
1080i and XGA at 75 Hz
Programmable 2-way color space converter
Supports RGB, YCbCr, and DDR
Supports ITU656-based embedded syncs
Automatic input video format timing detection (CEA-861D)
Digital audio
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
8-channel, uncompressed LPCM I2S audio up to 192 kHz
Special features for easy system design
On-chip MPU with I2C® master to perform HDCP
operations and EDID reading operations
5 V tolerant I2C and HPD I/Os, no extra device needed
No audio master clock needed for supporting S/PDIF
and I2S
HDCP-EDID
MICRO-
REGISTER
CONFIGURATION
LOGIC
CONTROLLER
DDCSDA
DDCSCL
2
I C
MASTER
CLK
VSYNC
HSYNC
DE
VIDEO
DATA
CAPTURE
Tx0[1:0]
Tx1[1:0]
Tx2[1:0]
TxC[1:0]
COLOR
SPACE
CONVER-
SION
HDMI
Tx
CORE
4:2:2 TO
4:4:4
CONVER-
SION
D[23:0]
XOR
MASK
S/PDIF
MCLK
AUDIO
DATA
CAPTURE
2
I S[3:0]
LRCLK
SCLK
AD9387NK
Figure 1.
On-chip MPU reports HDMI events through interrupts and
registers
APPLICATIONS
Digital video cameras
Digital still cameras
Personal media players
Cellular handsets
DVD players and recorders
Digital set-top boxes
A/V receivers
The AD9387NK supports both S/PDIF and 8-channel I2S audio.
Its high fidelity, 8-channel I2S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo LPCM
audio or compressed audio, including Dolby® Digital, DTS®,
and THX®.
HDMI repeater/splitter
The AD9387NK helps reduce system design complexity and cost
by incorporating such features as an internal MPU for HDCP
operations, an I2C master for EDID reading, a single 1.8 V power
supply, and 5 V tolerance on the I2C and hot plug detect pins.
GENERAL DESCRIPTION
The AD9387NK is an 80 MHz, high definition multimedia
interface (HDMI) v.1.3 transmitter. It supports HDTV formats
up to 720p and 1080i and computer graphic resolutions up to
XGA (1024 × 768 @ 75Hz). With the inclusion of HDCP, the
AD9387NK allows the secure transmission of protected content,
as specified by the HDCP v.1.1 protocol.
Fabricated in an advanced CMOS process, the AD9387NK
is available in a space saving, 76-ball CSP_BGA or 64-lead LFCSP
surface-mount package. Both packages are available as Pb-free
parts and are specified from −25°C to +85°C.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD9387NK
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Design Resources ..........................................................................7
Document Conventions ...............................................................7
PCB Layout Recommendations.......................................................8
Power Supply Bypassing...............................................................8
Digital Inputs .................................................................................8
External Swing Resistor................................................................8
Output Signals ...............................................................................8
Outline Dimensions..........................................................................9
Ordering Guide .............................................................................9
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Explanation of Test Levels........................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Applications Information ................................................................ 7
Rev. PrA | Page 2 of 12
Preliminary Technical Data
AD9387NK
SPECIFICATIONS
Table 1.
AD9387NK-BCPZ-80/AD9387NK-BBCZ-80
Test Level 1
Min
Typ
Max Unit
Parameter
Conditions
Temp
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Capacitance
DIGITAL OUTPUTS
Full
Full
25°C
VI
VI
V
1.4
3.5
0.7
V
V
pF
3
Output Voltage, High (VOH
Output Voltage, Low (VOL
)
Full
Full
VI
VI
VDD − 0.1
V
V
)
0.4
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case
V
V
V
15.2
59
+25
°C/W
°C/W
°C
θJA Junction-to-Ambient
Ambient Temperature
DC SPECIFICATIONS
Input Leakage Current (IIL)
Input Clamp Voltage
Full
−25
−10
+85
+10
25°C
25°C
25°C
VI
V
V
V
IV
μA
V
V
V
ꢀA
−16 mA
+16 mA
−0.8
+0.8
AVCC
Differential High Level Output Voltage
Differential Output Short-Circuit Current
POWER SUPPLY
10
VDD (All) Supply Voltage
VDD Supply Voltage Noise
Power-Down Current
Transmitter Supply Current2
Transmitter Total Power
AC SPECIFICATIONS
Full
Full
25°C
25°C
Full
IV
V
IV
IV
VI
1.71
1.8
1.89
50
V
mV p-p
ꢀA
mA
mW
10
55
100
CLK Frequency
25°C
25°C
Full
Full
Full
IV
IV
IV
IV
IV
VI
VI
VI
VI
VI
13.5
48
80
52
2
MHz
%
ns
ns
ns
TMDS Output CLK Duty Cycle
Worst Case CLK Input Jitter
Input Data Setup Time
Input Data Hold Time
TMDS Differential Swing
VSYNC and HSYNC Delay from DE Falling Edge
VSYNC and HSYNC Delay to DE Rising Edge
DE High Time
1
1
800
1000 1200 mV
1
1
UI3
UI3
25°C
25°C
8191 UI3
UI3
DE Low Time
138
Differential Output Swing
Low-to-High Transition Time
High-to-Low Transition Time
AUDIO AC TIMING
25°C
25°C
VII
VII
75
75
490
490
Ps
Ps
Sample Rate
I2S and S/PDIF
Full
IV
IV
IV
IV
IV
32
192
1
kHz
UI3
ns
ns
ꢀs
I2S Cycle Time
25°C
25°C
25°C
25°C
I2S Setup Time
15
0
75
I2S Hold Time
Audio Pipeline Delay
1 See the Explanation of Test Levels section.
2 Using low output drive strength.
3 UI = unit interval.
Rev. PrA | Page 3 of 12
AD9387NK
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
EXPLANATION OF TEST LEVELS
I.
100% production tested.
Parameter
Rating
Digital Inputs
5 V to 0.0 V
20 mA
−40°C to +85°C
−65°C to +150°C
150°C
II.
100% production tested at 25°C and sample tested at
specified temperatures.
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
III.
IV.
Sample tested only.
Parameter is guaranteed by design and characterization
testing.
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
V.
Parameter is a typical value only.
VI.
100% production tested at 25°C; guaranteed by design
and characterization testing.
VII.
Limits defined by HDMI specification; guaranteed by
design and characterization testing.
ESD CAUTION
Rev. PrA | Page 4 of 12
Preliminary Technical Data
AD9387NK
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
DVDD
D0
DE
HSYNC
VSYNC
CLK
1
2
3
4
5
6
7
8
9
48 DVDD
47 D15
46 D16
45 D17
44 D18
43 D19
42 D20
41 D21
40 D22
+
S/PDIF
MCLK
AD9387NK
2
I S0
TOP VIEW
(Not to Scale)
2
I S1 10
39 D23
2
I S2 11
38 MCL
37 MDA
36 SDA
35 SCL
34 DDCSDA
33 DDCSCL
2
I S3 12
10 9
8 7 6 5 4 3 2 1
SCLK 13
LRCLK 14
PVDD 15
PVDD 16
A
B
C
D
E
F
G
H
J
K
BOTTOM VIEW
(Not to Scale)
NOTES
1. GND PADDLE ON BOTTOM OF PACKAGE.
Figure 3. 76-Ball BGA Configuration (Top View)
Figure 2. 64-Lead LFCSP Pin Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
BGA
LFCSP
A1 to A10,
B1 to B10, C9,
C10, D9, D10
39 to 47,
50 to 63, 2
D[23:0]
I
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels
from 1.8 V to 3.3 V.
D1
C2
C1
D2
J3
6
3
4
5
CLK
DE
HSYNC
VSYNC
EXT_SWG
I
I
I
I
I
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this
pin and ground.
18
K3
E2
E1
20
7
HPD
I
I
I
Hot Plug Detect Signal. This indicates to the interface if the receiver is
connected. Supports CMOS logic levels from 1.8 V to 5.0 V.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a
Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
S/PDIF
MCLK
8
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling
frequency (fS), 256 × fS, 384 × fS, or 512 × fS. Supports CMOS logic levels from 1.8
V to 3.3 V.
F2, F1, G2, G1
9 to 12
I2S[3:0]
I
I2S Audio Data Inputs. These represent the eight channels of audio (two per
input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V.
H2
H1
J7
13
14
26
SCLK
LRCLK
PD/A0
I
I
I
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I2C Address Selection. The I2C address and the PD
polarity are set by the PD/A0 pin state when the supplies are applied to the
AD9387NK. Supports CMOS logic levels from 1.8 V to 3.3 V.
K1, K2
21, 22
30, 31
TxC−/TxC+
Tx2−/Tx2+
O
O
Differential Clock Output. Differential clock output at pixel clock rate; TMDS
logic level.
Differential Output Channel 2. Differential output of the red data at 10× the pixel
clock rate; TMDS logic level.
K10, J10
Rev. PrA | Page 5 of 12
AD9387NK
Preliminary Technical Data
Pin No.
Mnemonic
Type1
Description
BGA
LFCSP
K7, K8
27, 28
Tx1−/Tx1+
O
Differential Output Channel 1. Differential output of the green data at 10× the
pixel clock rate; TMDS logic level.
K4, K5
H10
24, 25
32
Tx0−/Tx0+
INT
O
O
Differential Output Channel 0. Differential output of the blue data at 10× the
pixel clock rate; TMDS logic level.
Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is
recommended.
J2, J5, J8, K9
D5, D6, D7, E7
AVDD
DVDD
P
P
1.8 V Power Supply for TMDS Outputs.
1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to
the digital logic and I/Os. They should be filtered and as quiet as possible.
19, 23, 29
1,48,49
15, 16, 17
G4, G5, J1
PVDD
GND
P
P
1.8 V PLL Power Supply. The most sensitive portion of the AD9387NK is the clock
generation circuitry. These pins provide power to the clock PLL. The designer
should provide quiet, noise-free power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that the
AD9387NK be assembled on a single, solid ground plane with careful attention
given to ground current paths.
64, Paddle
on bottom
side
D4, E4, F4, J4,
G6, J6, K6, F7,
G7, H9, J9
F9
36
35
37
38
34
33
SDA
C2
C2
C2
C2
C2
C2
Serial Port Data I/O. This pin serves as the serial port data I/O slave for register
access. Supports CMOS logic levels from 1.8V to 3.3V.
Serial Port Data Clock. This pin serves as the serial port data clock slave for
register access. Supports CMOS logic levels from 1.8V to 3.3V.
Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus.
Supports 5 V CMOS logic level.
Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC
bus. Supports 5 V CMOS logic level.
F10
E10
E9
SCL
MDA
MCL
G9
DDCSDA
DDCSCL
G10
1 I = input, O = output, P = power supply, C = control.
2 For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from flatpanel_apps@analog.com.
Rev. PrA | Page 6 of 12
Preliminary Technical Data
AD9387NK
APPLICATIONS INFORMATION
DESIGN RESOURCES
DOCUMENT CONVENTIONS
Analog Devices, Inc. evaluation kits, reference design schematics,
and other support documentation are available under NDA
from flatpanel_apps@analog.com.
In this data sheet, data is represented using the conventions
described in Table 4.
Table 4. Document Conventions
Data
Other resources include the following:
Type Format
•
EIA/CEA-861D, a technical specifications document that
describes audio and video infoframes, as well as the E-EDID
structure for HDMI. It is available from the Consumer
Electronics Association (CEA).
0xNN Hexadecimal (Base 16) numbers are represented using
the C language notation, preceded by 0x.
0bNN Binary (Base 2) numbers are represented using the C
language notation, preceded by 0b.
•
•
HDMI v. 1.3, a defining document for HDMI 1.3, and
HDMI Compliance Test Specification v. 1.3. They are
available from HDMI Licensing, LLC.
HDCP Specification v1.1, the defining technical specifications
document for the HDCP v. 1.1. It is available from Digital
Content Protection, LLC.
NN
Decimal (Base 10) numbers are represented using no
additional prefixes or suffixes.
Bits are numbered in little endian format; that is, the
least significant bit of a byte or word is referred to as Bit 0.
Bit
Rev. PrA | Page 7 of 12
AD9387NK
PCB LAYOUT RECOMMENDATIONS
Other Input Signals
The AD9387NK is a high precision, high speed analog device.
For maximum performance, it is important that board layout
be optimized.
The HPD must be connected to the HDMI connector. A 10 kΩ
pull-down resistor to ground is also recommended.
POWER SUPPLY BYPASSING
The PD/A0 input pin can be connected to GND or supply
(through a resistor or a control signal). The device address and
power-down polarity are set by the state of the PD/A0 pin when
the AD9387NK supplies are applied/enabled. For example, if
the PD/A0 pin is low (when the supplies are turned on), then
the device address is 0x72 and the power-down is active high.
If the PD/A0 pin is high (when the supplies are turned on),
the device address is 0x7A and the power down is active low.
It is recommended that each power supply pin be bypassed
with a 0.1 μF capacitor. The exception is when two or more
supply pins are adjacent to each other. For these groupings of
powers and grounds, it is necessary to have only one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Avoid placing the
capacitor on the opposite side of the PC board from the
AD9387NK, as doing so interposes resistive vias in the path.
The SCL and SDA pins should be connected to the I2C master.
A pull-up resistor of 2 kꢀ to 1.8 V or 3.3 V is recommended.
The bypass capacitors should be located between the power plane
and the power pin. Current should flow from the power plane
to the capacitor to the power pin. Do not make a power connection
between the capacitor and the power pin. Placing a via underneath
the capacitor pads, down to the power plane, is generally the
best approach.
EXTERNAL SWING RESISTOR
The external swing resistor must be connected directly to the
EXT_SWG pin and ground. The external swing resistor must
have a value of 887 Ω ( 1% tolerance). Avoid running any high
speed ac or noisy signals next to, or close to, the EXT_SWG pin.
It is particularly important to maintain low noise and good
stability of PVDD (the PLL supply). Abrupt changes in PVDD
can result in similarly abrupt changes in sampling clock phase
and frequency. Such changes can be avoided by careful attention
to regulation, filtering, and bypassing. It is best practice to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD and PVDD).
OUTPUT SIGNALS
TMDS Output Signals
The AD9387NK has three TMDS data channels (0, 1, and 2)
that output signals up to 800 MHz, as well as the TMDS output
data clock. To minimize the channel-to-channel skew, make the
trace length of these signals the same. Also, these traces need
a 50 ꢀ characteristic impedance and should be routed as 100 ꢀ
differential pairs. Best practice recommends routing these lines on
the top PCB layer, avoiding the use of vias.
It is also recommended that a single ground plane be used
for the entire board. Experience has repeatedly shown that
the noise performance is the same or better with a single
ground plane. Using multiple ground planes can be detri-
mental because each separate ground plane is smaller, and
long ground loops can result.
Other Output Signals (non TMDS)
DDCSCL and DDCSDA
The DDCSCL and DDCSDA outputs need a minimum amount
of capacitance loading to ensure the best signal integrity. The
DDCSCL and DDCSDA capacitance loading must be less than
50 pF to meet the HDMI compliance specification. The DDCSCL
and DDCSDA must be connected to the HDMI connector, and
a pull-up resistor to 5 V is required. The pull-up resistor must
have a value between 1.5 kΩ and 2 kΩ.
DIGITAL INPUTS
Video and Audio Data Input Signals
The digital inputs on the AD9387NK are designed to work with
signals ranging from 1.8 V to 3.3 V logic level. Therefore, no extra
components need to be added when using 3.3 V logic. Any
noise that gets onto the clock input (labeled CLK) trace adds
jitter to the system. Therefore, minimize the video clock input
(Pin 6, CLK) trace length, and do not run any digital or other
high frequency traces near it. Make sure to match the length of
the input data signals to optimize data capture, especially for
high frequency modes, such as 720p or XGA at 75 Hz and
double data rate input formats.
INT Pin
The INT pin is an output that should be connected to the system
microcontroller. A pull-up resistor to 1.8 V or 3.3 V is required
for proper operation; the recommended value is 2 kΩ.
MCL and MDA
The MCL and MDA outputs should be connected to the EEPROM
containing the HDCP key (if HDCP is implemented). Pull-up
resistors of 2 kΩ are recommended.
Rev. PrA | Page 8 of 12
Preliminary Technical Data
OUTLINE DIMENSIONS
AD9387NK
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
49
48
64
1
PIN 1
INDICATOR
+
4.85
4.70 SQ*
4.55
8.75
BSC SQ
EXPOSED PAD**
TOP
VIEW
(BOTTO M VIEW)
0.45
0.40
0.35
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
64 LFCSP (LEAD FRAME CHIP SCALE PACKAGE)
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
*
**Note: PAD is CONNECTED to GND
DIMENSIONS in Millimeters
Figure 4. 64-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-64)
Dimensions shown in millimeters
A1 CORNER
INDEX AREA
6.10
6.00 SQ
5.90
10
9
8
7
6
5
3
4
2
1
A
B
C
D
E
F
BALL A1
PAD CORNER
4.50
BSC SQ
TOP VIEW
0.50
BSC
G
H
J
K
BOTTOM VIEW
DETAILA
0.75
REF
DETAIL A
*
1.40 MAX
0.65 MIN
0.15 MIN
COPLANARITY
0.08 MAX
0.35
0.30
0.25
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-225
WITH THE EXCEPTION TO PACKAGE HEIGHT.
Figure 5. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
6 mm × 6 mm × 1.4 mm
(BC-76)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9387NKBCPZ-801
AD9387NKBBCZ-801
AD9387NKBBCZRL-801
AD9387NK/PCB
Temperature Range
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
Package Description
Package Option
64-Lead Formed Chip Scale Package
CP-64
BC-76
BC-76
76-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
76-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
1 Z = Pb-free part.
Rev. PrA | Page 9 of 12
AD9387NK
NOTES
Rev. PrA | Page 10 of 12
Preliminary Technical Data
NOTES
AD9387NK
Rev. PrA | Page 11 of 12
AD9387NK
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06507-0-12/06(PrA)
Rev. PrA | Page 12 of 12
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SPECIALTY CONSUMER CIRCUIT, PQFP144, 20 X 20 MM, ROHS COMPLIANT, PLASTIC, MS-026BFB, LQFP-144
ROCHESTER
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