AD9393_技术文档

Low Power HDMI Display Interface

AD9393

FEATURES

FUNCTIONAL BLOCK DIAGRAM

HDMI interface

SERIAL

SCL

SDA

REGISTER

AND

Supports high bandwidth digital content protection

RGB to YCrCb 2-way color conversion

1.8 V/3.3 V power supply

POWER

MANAGEMENT

R/G/B 8 × 3

OR YCrCb

D[23:0]

DCLK

76-ball BGA package

RGB and YCrCb output formats

Digital video interface

HDMI 1.2a, DVI 1.0

80 MHz HDMI receiver

DATACK

HSOUT

VSOUT

DE

Rx0+

Rx0–

H

SYNC

V

SYNC

Rx1+

Rx1–

DE

HDMI

RECEIVER

Supports high bandwidth digital content protection

(HDCP 1.1)

SPDIF

Rx2+

Rx2–

8-CHANNEL

I S

RxC+

RxC–

RTERM

Digital audio interface

2

HDMI 1.2a-compatible audio interface

S/PDIF (IEC60958-compatible) digital audio output

Multichannel I²S audio output (up to 8 channels)

MCLK

SCLK

LRCLK

MCL

MDA

HDCP

AD9393

DDC_SCL

DDC_SDA

APPLICATIONS

Portable low power TV

HDTV

Figure 1.

Projectors

LCD monitor

GENERAL DESCRIPTION

The AD9393 offers a High-Definition Multimedia Interface

(HDMI™) receiver integrated on a single chip. Support is also

included for high bandwidth digital content protection (HDCP).

of a video receiver, decryption of encoded data at the receiver,

and renewability of that authentication during transmission as

specified by the HDCP 1.1 protocol.

The AD9393 contains a HDMI 1.2a-compatible receiver and

supports HDTV formats (up to 720p or 1080i) and displays

resolutions up to XGA (1024 × 768 @ 75 Hz). The receiver

features an intrapair skew tolerance of up to one full clock

cycle. With the inclusion of HDCP, displays may now receive

encrypted video content. The AD9393 allows for authentication

Fabricated in an advanced CMOS process, the AD9393 is

provided in a space-saving 76-ball, surface-mount, Pb-free,

ball grid array (BGA) and is specified over the −10°C to

+80°C temperature range.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9393

TABLE OF CONTENTS

Features .............................................................................................. 1

2-Wire Serial Register Map ........................................................... 12

2-Wire Serial Control Register Details........................................ 22

Chip Identification..................................................................... 22

BT656 Generation...................................................................... 24

Color Space Conversion............................................................ 25

2-Wire Serial Control Port............................................................ 31

Data Transfer via Serial Interface............................................. 31

Serial Interface Read/Write Examples..................................... 32

PCB Layout Recommendations.................................................... 33

Power Supply Bypassing............................................................ 33

Outputs (Both Data and Clocks).............................................. 33

Digital Inputs .............................................................................. 33

Color Space Converter (CSC) Common Settings...................... 34

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Digital Interface Electrical Characteristics ............................... 4

Absolute Maximum Ratings............................................................ 5

Explanation of Test Levels........................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Design Guide..................................................................................... 8

General Description..................................................................... 8

Digital Inputs ................................................................................ 8

Serial Control Port ....................................................................... 8

Output Signal Handling............................................................... 8

Power Management...................................................................... 8

Timing............................................................................................ 9

HDMI Receiver............................................................................. 9

DE Generator................................................................................ 9

4:4:4 to 4:2:2 Filter ........................................................................ 9

Audio PLL Setup......................................................................... 10

Audio Board Level Muting........................................................ 11

Output Data Formats................................................................. 11

HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting

for AD9393) ................................................................................ 34

HDTV YCrCb (16 to 235) to RGB (0 to 255)......................... 34

SDTV YCrCb (0 to 255) to RGB (0 to 255)............................ 34

SDTV YCrCb (16 to 235) to RGB (0 to 255).......................... 35

RGB (0 to 255) to HDTV YCrCb (0 to 255)........................... 35

RGB (0 to 255) to HDTV YCrCb (16 to 235)......................... 35

RGB (0 to 255) to SDTV YCrCb (0 to 255)............................ 36

RGB (0 to 255) to SDTV YCrCb (16 to 235).......................... 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

AD9393

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V_DD, V_D= 3.3 V, DV_DD= PV_DD= 1.8 V, unless otherwise noted.

Table 1.

Parameter

Temp

Test Level

Min

Typ

Max

Unit

DIGITAL INPUTS (5 V Tolerant)

Input Voltage, High (V_IH)

Input Voltage, Low (V_IL)

Input Current, High (I_IH)

Input Current, Low (I_IL)

Input Capacitance

Full

25°C

VI

V

2.6

V

μA

pF

0.8

−82

82

3

DIGITAL OUTPUTS

Output Voltage, High (V_OH)

Output Voltage, Low (V_OL)

Duty Cycle, DCLK

Full

VI

V

V_DD− 0.1

45

V

%

0.4

55

50

Output Coding

Binary

THERMAL CHARACTERISTICS

θ_JAJunction-to-Ambient

θ_JCJunction-to-Case

V

59

15.2

°C/W

Rev. 0 | Page 3 of 40

AD9393

DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS

V_DD= V_D=3.3 V, DV_DD= PV_DD= 1.8 V, unless otherwise noted.

Table 2.

Test

Parameter

Level Conditions

Min

Typ

Max Unit

DC DIGITAL I/O Specifications

High-Level Input Voltage (V_IH)

Low-Level Input Voltage (V_IL)

High-Level Output Voltage (V_OH)

Low-Level Output Voltage (V_OL)

VI

2.5

V

0.8

0.1

V

V_DD− 0.1

DC SPECIFICATIONS

Output High Level

I_OHD(V_OUT= V_OH)

Output Low Level

I_OLD(V_OUT= V_OL)

DCLK High Level

V_OHC(V_OUT= V_OH)

DCLK Low Level

V_OLC(V_OUT= V_OL)

IV

Output drive = high strength

Output drive = low strength

Output drive = high strength

Output drive = low strength

Output drive = high strength

Output drive = low strength

Output drive = high strength

Output drive = low

36

24

12

8

40

20

30

15

mA

mV

Differential Input Voltage, Single-Ended Amplitude

75

700

POWER SUPPLY

V_D

V_DD

DV_DD

PV_DD

IV

3.15

1.7

3.3

1.8

485

3.47

347

1.9

V

1.7

1.9

Power—54 MHz, YCrCb 422, CSC Disabled

mW

Supply Current (Worst Pattern)¹

I_VD

I_VDD

I_DVDD

I_PVDD

V

95

18

51

26

593

mA

mW

2

Power—74.25 MHz, RGB, CSC Disabled

Supply Current (Worst Pattern)¹

I_VD

I_VDD

I_DVDD

V

VI

109

38

66

26

130

mA

mW

I_PVDD

Power-Down Power

AC SPECIFICATIONS

Intrapair (+ to −) Differential Input Skew (t_DPS

Channel-to-Channel Differential Input Skew (t_CCS

Low-to-High Transition Time for Data and Controls (D_LHT

)

IV

VI

0.4

0.6

t_BIT

t_PIXEL

ps

ns

%

MHz

)

Output drive = high; C_L= 10 pF

Output drive = low; C_L= 5 pF

Output drive = high; C_L= 10 pF

Output drive = low; C_L= 5 pF

Output drive = high; C_L= 10 pF

Output drive = low; C_L= 5 pF

Output drive = high; C_L= 10 pF

Output drive = low; C_L= 5 pF

1000

Low-to-High Transition Time for DCLK (D_LHT

High-to-Low Transition Time for Data and Controls (D_HLT

High-to-Low Transition Time for DCLK (D_HLT

)

Clock-to-Data Skew³(t_SKEW

Duty Cycle, DCLK³

)

−0.5

45

20

+2.0

80

50

DCLK Frequency (f_CIP)

¹Worst-case pattern is alternating black and white pixels.

²DCLK load = 10 pF, data load = 5 pF.

³Drive strength = high.

Rev. 0 | Page 4 of 40

AD9393

ABSOLUTE MAXIMUM RATINGS

Table 3.

EXPLANATION OF TEST LEVELS

I

100% production tested.

Parameter

Rating

V_D

V_DD

DV_DD

3.6 V

1.98 V

II

100% production tested at 25°C and sample tested at

specified temperatures.

III

IV

Sample tested only.

PV_DD

Digital Inputs

1.98 V

5 V to 0.0 V

20 mA

−25°C to +85°C

−65°C to +150°C

150°C

Parameter is guaranteed by design and characterization

testing.

Digital Output Current

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Maximum Case Temperature

V

Parameter is a typical value only.

VI

100% production tested at 25°C; guaranteed by design

and characterization testing.

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 40

AD9393

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

D14

D15

D16

D18

D20

D22

DCLK HSOUT

O/E

SDA

A

B

C

D

E

F

D13

D11

D9

D12

D10

D8

D17

D19

D21

D23

DE

VSOUT

PD

SCL

GND

FILT

GND

MDA

MCL

GND

Rx2+

Rx2–

GND

V

GND

DD

D7

D6

GND

V

D

AD9393

TOP VIEW

(Not to Scale)

D5

D4

V

D

PV

DD

D3

D2

SCLK

DV

DD

LRCLK

PV

DD

G

H

J

DD

DDC_

SCL

D1

D0

DDC_

SDA

GND

RxC–

MCLK

RxC+

I2S3

GND

I2S2

I2S1

I2S0

GND

SPDIF RTERM

Rx0–

Rx0+

Rx1–

Rx1+

GND

K

Figure 2. Pin Configuration

Table 4. Complete Pin List

Pin No.

Inputs

B9

Mnemonic

Description

Value

PD

Power-Down Control. Power-Down Control/Three-State Control. The function

of this pin is programmable via Register 0x26[2:1].

3.3 V CMOS

Digital Video Data Inputs

K5, K4, K8, K7, J10, K10

Rx0+, Rx0−,

Rx1+, Rx1−,

Rx2+, Rx2−

Digital Input Channel x True/Complement. These six pins receive three pairs of TMDS

transition minimized differential signaling (TMDS ) pixel data (at 10× the pixel

rate) from a digital graphics transmitter.

Digital Video Clock Inputs

K2, K1

RxC+, RxC−

D[23:0]

Digital Data Clock True/Complement. This clock pair receives a TMDS clock at

1× pixel data rate.

TMDS

V_DD

Outputs

B6, A6, B5, A5, B4,

A4, B3, A3, A2, A1,

B1, B2, C1, C2, D1,

D2, E1, E2, F1, F2,

G1, G2, H1, H2

Data Outputs. In RGB,

D[23:16] = Red[7:0]

D[15:8] = Green[7:0]

D[7:0] = Blue[7:0]

See Table 6

A7

DCLK

Data Output Clock. This is the main clock output signal used to strobe the

output data and HSOUT into external logic. Four possible output clocks can

be selected with Register 0x25[7:6]. These are related to the pixel clock (½×

pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted

pixel clock). They are produced by the internal PLL clock generator and are

synchronous with the pixel clock. The polarity of DCLK can also be inverted via

Register 0x24[0].

V_DD

A8

HSOUT

HSYNC Output Clock (Phase-Aligned with DCLK). Horizontal sync output. A

reconstructed and phase-aligned version of the HSYNC input. Both the

polarity and duration of this output can be programmed via serial bus

registers. By maintaining alignment with DCLK and data, data timing with

respect to horizontal sync can always be determined.

V_DD

Rev. 0 | Page 6 of 40

AD9393

Pin No.

Mnemonic

Description

Value

B8

VSOUT

VSYNC Output Clock (Phase-Aligned with DCLK). Vertical Sync Output. The

separated VSYNC from a composite signal or a direct passthrough of the

VSYNC signal. The polarity of this output can be controlled via the serial bus

bit (Register 0x24[6]).

V_DD

A9

O/E

FILT

Odd/Even Field Output for Interlaced Video. This output identifies whether the V_DD

current field (in an interlaced signal) is odd or even. The polarity of this signal

is programmable via Register 0x24[4].

References

D10

Connection for External Filter Components for Audio PLL. For proper operation,

the audio clock generator PLL requires an external filter. Connect the filter

shown in Figure 6 to this pin. For optimal performance, minimize noise and

parasitics on this node. For more information, see the PCB Layout

Recommendations section.

PV_DD

Power Supply¹

E7, F7

V_D

HDMI Terminator Power Supply (3.3 V). These pins supply power to the HDMI

terminators. They should be as quiet and filtered as possible.

3.3 V

V_DD

D4, D5

Digital Output Power Supply (1.8 V to 3.3 V). A large number of output pins (up

to 27) switching at high speed (up to 80 MHz) generates many power supply

transients (noise). These supply pins are identified separately from the V_Dpins,

so output noise transferred into the sensitive circuitry can be minimized. If the

AD9393 is interfacing with lower voltage logic, V_DDcan be connected to a

lower supply voltage (as low as 1.8 V) for compatibility.

1.8 V to 3.3

V

F9, G9

G6, G7

PV_DD

PLL Power Supply (1.8 V). The most sensitive portion of the AD9393 is the

clock generation circuitry. These pins provide power to the clock PLL and help

the user design for optimal performance. The user should provide quiet,

noise-free power to these pins.

Digital Logic Power Supply (1.8 V). These pins supply power to the digital

logic.

1.8 V

DV_DD

GND

C9, C10, D6, D7, D9, E4,

E9, E10,

F4, H10, J1, K3, K6, K9

Ground. The ground return for all circuitry on chip. It is recommended that the 0 V

AD9393 be assembled on a single solid ground plane, with careful attention

to ground current paths.

Control

A10

SDA

SCL

Serial Port Data I/O for Programming the AD9393 Registers. The I²C address is

Address 0x98.

Serial Port Data Clock for Programming the AD9393 Registers.

3.3 V CMOS

B10

HDCP

H9

3.3 V CMOS

DDC_SCL

DDC_SDA

HDCP Slave Serial Port Data Clock for HDCP Communications to Transmitter.

3.3 V CMOS

J9

HDCP Slave Serial Port Data I/O for HDCP Communications to Transmitter. The

I²C address is Address 0x74 or Address 0x76.

F10

G10

MDA

MCL

Master Serial Port I/O to EEPROM with HDCP Keys—I²C Address is 0xA0.

Master Serial Port Data Clock to EEPROM with HDCP Keys.

3.3 V CMOS

Audio Data Outputs

J7

J6

J5

J4

J3

J2

G4

G5

S/PDIF

I2S0

I2S1

I2S2

I2S3

MCLK

SCLK

LRCLK

S/PDIF Digital Audio Output.

V_DD

I²S Audio (Channel 1, Channel 2). Channel 0 and Channel 1 Audio Output.

I²S Audio (Channel 3, Channel 4). Channel 2 and Channel 3 Audio Output.

I²S Audio (Channel 5, Channel 6). Channel 4 and Channel 5 Audio Output.

I²S Audio (Channel 7, Channel 8). Channel 6 and Channel 7 Audio Output.

Audio Master Clock Output for S/PDIF Data.

Audio Serial Clock Output for I²S Data.

Data Output Clock for Left and Right Audio Channels.

Data Enable

B7

DE

Data Enable for Active Data Pixels.

3.3 V CMOS

500 Ω

RTERM

J8

RTERM

Sets Internal Termination Resistance. Place a 500 Ω (1% tolerance) resistor from

this pin to ground. This sets the internal termination of TMDS lines to 50 Ω.

¹The supplies should be sequenced such that V_Dand V_DDare never less than 300 mV below DV_DD. At no time should DV_DDbe more than 300 mV greater than V_Dor V_DD

.

Rev. 0 | Page 7 of 40

AD9393

DESIGN GUIDE

GENERAL DESCRIPTION

SERIAL CONTROL PORT

The AD9393 is a fully integrated solution for receiving DVI/

HDMI signals and is capable of decoding HDCP-encrypted

signals through connections to an external EEPROM. The

circuit is ideal for providing an interface for HDTV monitors

or as the front end to high performance video scan converters.

The serial control port is designed for 3.3 V logic. However, it is

tolerant of 5 V logic signals.

OUTPUT SIGNAL HANDLING

The digital outputs operate from 1.8 V to 3.3 V (V_DD).

POWER MANAGEMENT

Implemented in a high performance CMOS process, the

interface can capture signals with pixel rates of up to 80 MHz.

To determine the correct power state, the AD9393 uses the

activity detect circuits, the active interface bits in the serial bus,

the active interface override bits, the power-down bit, and the

power-down ball. There are three power modes: full power,

auto power-down, and power-down.

The AD9393 includes all necessary circuitry for decoding

TMDS signaling including those encrypted with HDCP.

Included in the output formatting is a color space converter

(CSC), which accommodates any input color space and can

output any color space. All controls are programmable via a

2-wire serial interface. Full integration of these sensitive mixed

signal functions makes system design straight forward and less

sensitive to the physical and electrical environment.

Table 5 summarizes how the AD9393 determines which power

mode to use and which circuitry is powered on/off in each of

these modes. The power-down command has first priority and

the automatic circuitry second priority. The power-down ball

(Ball B8—polarity set by Register 0x26[3]) can drive the chip

into two power-down options. Bit 2 of Register 0x26 controls

these two options. Bit 0 controls whether the chip is powered

down or the outputs are placed in high impedance mode. Bit 7

to Bit 4 of Register 0x26 control whether the outputs, Sony/

Philips digital interface (S/PDIF), or Inter-IC Sound bus (I²S or

IIS) outputs are in high impedance mode or not. See the 2-Wire

Serial Control Register Detail section for the details.

DIGITAL INPUTS

The digital control inputs (I²C) on the AD9393 operate to 3.3 V

CMOS levels. In addition, all digital inputs except the TMDS

inputs (HDMI/DVI) are 5 V tolerant. Applying 5 V to them

does not cause any damage. The TMDS input pairs (Rx0 ,

Rx1 , Rx2 , and RxC ) must maintain a 100 Ω differential

impedance (through proper PCB layout) from the connector to

the input where they are internally terminated (50 Ω to 3.3 V).

If additional ESD protection is desired, using a low capacitance

ESD protection varistor offers 8 kV of protection to the HDMI

TMDS lines.

Table 5. Power-Down Mode Descriptions

Inputs

Auto PD Enable²

Mode

Power-Down¹

Power-On/Comments

Full Power

Auto Power-Down

Power-Down

1

0

X

1

X

Everything

Serial bus, sync activity detect, band gap reference

¹Power-down is controlled via Bit 0 in Register 0x26.

²Auto power-down is controlled via Bit 7 in Register 0x27.

Rev. 0 | Page 8 of 40

AD9393

TIMING

DE GENERATOR

The output data clock signal is created so that its rising edge

always occurs between data transitions and can be used to latch

the output data externally.

The AD9393 has an on-board generator for DE, for the start

of active video (SAV), and for the end of active video (EAV), all

of which are necessary for describing the complete data stream

for a BT656-compatible output. This signal alerts the following

circuitry, which are displayable video pixels.

Figure 3 shows the timing operation of the AD9393.

t_PER

4:4:4 TO 4:2:2 FILTER

t_DCYCLE

The AD9393 contains a filter that allows it to convert a

signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining

the maximum accuracy and fidelity of the original signal.

DATACK

t_SKEW

Input Color Space to Output Color Space

DATA

HSOUT

The AD9393 can accept a wide variety of input formats and

either retain that format or convert to another. Input formats

supported are

Figure 3. Output Timing

•

4:4:4 YCrCb 8-bit

4:2:2 YCrCb 8-, 10-, and 12-bit

RGB 8-bit

HDMI RECEIVER

The HDMI receiver section of the AD9393 allows the reception

of a digital video stream (which is backward compatible with

DVI and able to accommodate video of various formats (RGB,

YCrCb 4:4:4, 4:2:2)). The receiver also allows up to eight channels

of audio. Infoframes are transmitted carrying information about

the video format, audio clocks, and many other items necessary

for a monitor to utilize fully the information stream available.

Output modes supported are

•

4:4:4 YCrCb 8-bit

4:2:2 YCrCb 8-, 10-, and 12-bit

Dual 4:2:2 YCrCb 8-bit

Color Space Conversion (CSC) Matrix

The earlier digital visual interface (DVI) format was restricted

to an RGB 24-bit color space only. Embedded in this data stream

were HSYNCs, VSYNCs, and display enable (DE) signals; but

no audio information. The HDMI specification allows trans-

mission of all the DVI capabilities, but adds several YCrCb

formats that make the inclusion of a programmable color space

converter (CSC) a very desirable feature. With this feature, the

scaler following the AD9393 can specify that it always wishes to

receive a particular format, for instance, 4:2:2 YCrCb, regardless

of the transmitted mode. If RGB is sent, the CSC can easily

convert that to 4:2:2 YCrCb while relieving the scaler of this

task.

The CSC matrix in the AD9393 consists of three identical

processing channels. In each channel, three input values are

multiplied by three separate coefficients. An offset value for

each row of the matrix and a scaling multiple for all values

are also included. Each value has a 13-bit, twos complement

resolution to ensure the signal integrity is maintained. The

CSC is designed to run at speeds up to 80 MHz supporting

resolutions up to 720p at 60 Hz. With any-to-any color space

support, formats such as RGB, YUV, YCrCb, and others are

supported by the CSC.

The main inputs, R_IN, G_IN, and B_IN, come from the 8-bit or 12-

bit inputs from each channel. These inputs are based on the

input format detailed in Table 30 to Table 52. The mapping of

these inputs to the CSC inputs is shown in Table 6.

In addition, the HDMI specification supports the transmission

of up to eight channels of S/PDIF or I²S audio. The audio infor-

mation is separated into packets and transmitted during the

video blanking periods along with specific information about

the clock frequency. Part of this audio information (audio

infoframe) tells the user how many channels of audio are being

transmitted, where the channels should be placed, information

regarding the source (make, model), and other data.

Table 6. CSC Port Mapping

Input Channel

R/Cr (D[23:16])

Gr/Y (D[15:8])

B/Cb (D[7:0])

CSC Input Channel

R_IN

G_IN

B_IN

Rev. 0 | Page 9 of 40

AD9393

One of the three input channels is represented in Figure 4.

In each processing channel, the three inputs are multiplied

by three separate coefficients marked a1, a2, and a3. These

coefficients are divided by 4096 to obtain nominal values

ranging from −0.9998 to +0.9998. The variable labeled a4 is

used as an offset control. The CSC_MODE setting is the same

for all three processing channels. This multiplies all coefficients

audio, but also the sampling frequency (f_S). The audio info-

frame also contains information about the N and CTS values

used to recreate the clock. With this information, it is possible

to regenerate the audio sampling frequency. The audio clock is

regenerated by dividing the 20-bit CTS value into the TMDS

clock, then multiplying by the 20-bit N value. This yields a

multiple of the sampling frequency of either 128 × f_Sor 256 ×

f_S. It is possible for this to be specified up to 1024 × f_S.

and offsets by a factor of 2^CSC_MODE

.

SOURCE DEVICE

SINK DEVICE

The functional diagram for a single channel of the CSC (as

shown in Figure 4) is repeated for the remaining G and B

channels. The coefficients for these channels are b1, b2, b3,

b4, c1, c2, c3, and c4.

CTS*

CYCLE

TIME

DIVIDE

BY

128 × f_S

COUNTER

N

CSC_MODE[1:0]

128 × f_S

TMDS

CLOCK

N*

a4[12:0]

a1[12:0]

VIDEO

÷ CTS

× N

CLOCK

×4

×2

2

1

0

1

4096

REGISTER

N

R

G

B

[11:0]

+

×

N

IN

R

[11:0]

OUT

a2[12:0]

*N AND CTS VALUES ARE TRANSMITTED USING THE

AUDIO CLOCK REGENERATION PACKET. VIDEO

CLOCK IS TRANSMITTED ON TMDS CLOCK CHANNEL.

1

4096

×

Figure 5. N and CTS for Audio Clock

a3[12:0]

To provide the most flexibility in configuring the audio

sampling clock, an additional PLL is employed. The PLL

characteristics are determined by the loop filter design (see

Figure 6), the PLL charge pump current, and the VCO range

setting.

1

4096

×

Figure 4. Single CSC Channel

A programming example and register settings for several

common conversions are listed in the Color Space Converter

PV

DD

C

Z

80nF

P

8nF

(CSC) Common Settings section.

R

1.5kΩ

Z

For a detailed functional description and more programming

examples that are compatible with the AD9393, refer to the

AN-795 Application Note, AD9880 Color Space Converter

User's Guide.

FILT

Figure 6. PLL Loop Filter Detail

To fully support all audio modes for all video resolutions up

to 1080i, it is necessary to adjust certain audio-related registers

from their power-on default values. Table 7 describes these

registers and gives the recommended settings.

AUDIO PLL SETUP

Data contained in the audio infoframes (among other registers)

defines for the AD9393 HDMI receiver not only the type of

Table 7. Audio Register Settings

Recommended

Register Bits Setting

Function

Comments

0x01

0x02

0x03

[7:0] 0x00

[7:4] 0x40

[7:6] 01

PLL divisor (MSBs)

PLL divisor (LSBs)

VCO range

The video PLL is used for the audio clock circuit when in HDMI mode. This

is done automatically.

[5:3] 010

Charge pump current

PLL enable

[2]

1

In HDMI mode, this bit enables a lower frequency to be used for audio

MCLK generation.

0x34

0x58

[5:4] 11

Audio frequency mode

override

Allows the chip to determine the low frequency mode of the audio PLL.

[7]

1

MCLK PLL enable

MCLK PLL divisor

This enables the analog PLL to be used for audio MCLK generation.

[6:4] 001

When the analog PLL is enabled for MCLK generation, another frequency

divider is provided; these bits set the divisor to 2.

[3]

0

N/CTS disable

The N and CTS values should always be enabled.

[2:0] 0**

MCLK sampling

frequency

000 = 128 × f_S

001 = 256 × f_S

010 = 384 × f_S

011 = 512 × f_S

Rev. 0 | Page 10 of 40

AD9393

This information is the fundamental difference between DVI

AUDIO BOARD LEVEL MUTING

and HDMI transmissions and is located in the read-only registers

Register 0x5A to Register 0xEE. In addition to this information,

registers are provided to indicate that new information has been

received. Registers with addresses ending in 7 or F beginning

with Register 0x87 contain the new data flags (NDF)

information. All of these registers contain the same information

and all are reset when any of them are read. Although there is

no external interrupt signal, it is very easy for the user to read

any of the NDF registers to see if there is new information to be

processed.

The audio can be muted through the infoframes or locally

via the serial bus registers. This can be controlled with

Register 0x57, Bits[7:6].

AVI Infoframes

The HDMI TMDS transmission contains infoframes with

specific information for the monitor such as:

•

Audio information

•

Two channels to eight channels of audio identified

Audio coding

OUTPUT DATA FORMATS

•

Audio sampling frequency

Speaker placement

N and CTS values (for reconstruction of the audio)

Muting

The AD9393 supports 4:4:4, 4:2:2, double data-rate (DDR), and

BT656 output formats. Register 0x25[3:0] controls the output

mode. These modes and the pin mapping are illustrated in

Table 8.

Source information

•

CD

SACD

DVD

•

Video information

•

Video ID code (per CEA861B)

Color space

Aspect ratio

Horizontal and vertical bar information

MPEG frame information (I, B, or P frame)

Vendor (transmitter source) name and product model

Table 8. Output Formats¹

Bits D[23:0]

Port

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

4:4:4

Red/Cr [7:0]

CbCr [7:0]

Green/Y [7:0]

Y [7:0]

Blue/Cb [7:0]

DDR 4:2:2 ↑ CbCr ↓ Y, Y

4:2:2

4:4:4 DDR

DDR ↑ G [3:0]

DDR ↓ R [7:0]

DDR ↑ B [7:4]

DDR ↑ B [3:0]

DDR ↓ G [7:4]

DDR 4:2:2 ↑ CbCr [11:0]

DDR 4:2:2 ↓ Y, Y [11:0]

Y [11:0]

4:2:2 to 12-bit CbCr [11:0]

¹Arrows indicate clock edge. The rising edge of clock = ↑, the falling edge = ↓.

Rev. 0 | Page 11 of 40

AD9393

2-WIRE SERIAL REGISTER MAP

The AD9393 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to

write and read the control registers through the 2-wire serial interface port.

Table 9. Control Register Map

Default

Hex Address

Read/Write

Bits

Value

Register Name

Description

0x00

Read

[7:0]

00000000

Chip revision

Chip revision ID. Revision is read [7:4] = major revision. [3:0]

= minor revision.

0x01

0x02

0x03

Read/write

[7:0]

[7:4]

[7:6]

[5:3]

[2]

01101001

1101xxxx

01xxxxxx

xx001xxx

xxxxx0xx

PLL divider MSB

PLL divider LSB

VCO range

PLL feedback divider value MSB.

PLL feedback divider value LSB.

VCO range.

Charge pump

Charge pump current control for PLL.

This bit enables a lower frequency to be used for audio

MCLK generation.

PLL enable

0x11

0x12

Read/write

[7:0]

[7]

00000000

1xxxxxxx

Reserved

Must be set to 0x00 (default).

0 = active low.

Input HSYNC polarity

1 = active high.

[6]

[5]

[4]

x0xxxxxx

xx1xxxxx

xxx0xxxx

HSYNC polarity override

Input VSYNC polarity

VSYNC polarity override

0 = auto HSYNC polarity.

1 = manual HSYNC polarity.

0 = active low.

1 = active high.

0 = auto VSYNC polarity.

1 = manual VSYNC polarity.

MSB of HSYNCs per VSYNC.

HSYNCs per VSYNC count.

VSYNC duration.

0x17

0x18

0x22

0x23

Read

[3:0]

[7:0]

xxxx0000

HSYNCs per VSYNC MSB

HSYNCs per VSYNC LSB

VSYNC duration

Read

00000000

Read/write

4

32

HSYNC duration

HSYNC duration. Sets the duration of the output HSYNC in

pixel clocks.

0x24

Read/write

[7]

[6]

[5]

[4]

1xxxxxxx

x1xxxxxx

xx1xxxxx

xxx1xxxx

HSYNC output polarity

VSYNC output polarity

DE output polarity

Output HSYNC polarity.

0 = active low output.

1 = active high output.

Output VSYNC polarity.

0 = active low output.

1 = active high output.

Output DE polarity.

0 = negative output.

1 = positive output.

Field output polarity

Output field polarity.

0 = active low output.

1 = active high output.

0 = noninverted clock output.

1 = inverted clock output.

[0]

xxxxxxx0

01xxxxxx

Output CLK invert

Output CLK select

0x25

Read/write

[7:6]

Selects which clock to use on output ball. 1× CLK is divided

down from TMDS clock input when pixel repetition is in use.

00 = ½× CLK.

01 = 1× CLK.

10 = 2× CLK.

11 = 90° phase 1× CLK.

[5:4]

[3:2]

xx11xxxx

xxxx00xx

Output drive strength

Output mode

Sets the drive strength of the outputs. 00 = lowest, 11 =

highest.

Selects the data output mapping.

00 = 4:4:4 mode (normal).

01 = 4:2:2 + DDR 4:2:2 on D[7:0].

10 = DDR 4:4:4 + DDR 4:2:2 on D[7:0].

11 = 12-bit 4:2:2.

[1]

[0]

xxxxxx1x

xxxxxxx0

Primary output enable

Enables primary output.

Secondary output enable

Enables secondary output (DDR 4:2:2 in Output Mode 1

and Output Mode 2).

Rev. 0 | Page 12 of 40

AD9393

Default

Value

Hex Address

Read/Write

Bits

[7]

Register Name

Description

0x26

Read/write

0xxxxxxx

xx0xxxxx

xxx0xxxx

xxxx1xxx

Output three-state

S/PDIF three-state

I²S three-state

Three-state the outputs.

Three-state the S/PDIF output.

Three-state the I²S output and the MCLK output.

Sets polarity of power-down ball.

0 = active low.

[5]

[4]

[3]

Power-down ball polarity

1 = active high.

[2:1]

xxxxx00x

Power-down ball function

Selects the function of the power-down ball.

0x = power-down.

1x = three-state outputs.

0 = normal.

[0]

[7]

[6]

xxxxxxx0

1xxxxxxx

x0xxxxxx

Power-down

1 = power-down.

0x27

Read/write

Auto power-down enable

HDCP A0

0 = disable auto low power state.

1 = enable auto low power state.

Sets the LSB of the address of the HDCP I2C. Set to 1 only

for a second receiver in a dual-link configuration.

[5]

[4]

xx0xxxxx

xxx0xxxx

Clock test

BT656 EN

Must be written to 0.

Enables EAV/SAV codes to be inserted into the video

output data.

[3]

xxxx0xxx

xxxxx000

011000xx

Force DE generation

Interlace offset

VSYNC delay

Allows use of the internal DE generator—not the DE

transmitted over TMDS.

[2:0]

[7:2]

Sets the difference (in HSYNCs) in field length between

Field 0 and Field 1.

0x28

0x29

Read/write

Sets the delay (in lines) from the VSYNC leading edge to

the start of active video.

[1:0]

[7:0]

xxxxxx01

00000100

HSYNC delay MSB

HSYNC delay LSB

HSYNC delay MSB of Register 0x29.

Sets the delay (in pixels) from the HSYNC leading edge to

the start of active video.

0x2A

0x2B

0x2C

0x2D

0x2E

Read/write

[3:0]

[7:0]

[3:0]

[7:0]

[7]

xxxx0101

00000000

xxxx0010

11010000

0xxxxxxx

x00xxxxx

Line width MSB

Line width LSB

Screen height MSB

Screen height LSB

CTRL EN

Line width MSB of Register 0x2B.

Sets the width of the active video line in pixels.

Screen height MSB of Register 0x2D.

Sets the height of the active screen in lines.

Allows CTRL[3:0] to be output on the I²S data pins.

00 = I²S mode.

[6:5]

I²S output mode

01 = right-justified.

10 = left-justified.

11 = raw IEC60958 mode.

[4:0]

[6]

xxx11000

x0xxxxxx

xx0xxxxx

xxx0xxxx

I²S bit width

TMDS sync detect

TMDS active

AV mute

Sets the desired bit width for right-justified mode.

Detects a TMDS DE.

0x2F

0x30

Read

[5]

Detects a TMDS clock.

[4]

Gives the status of AV mute based on general control

packets.

[3]

xxxx0xxx

xxxxx000

x0xxxxxx

HDCP keys read

Returns 1 when read of EEPROM keys is successful.

Returns quality number based on DE edges.

[2:0]

[6]

HDMI quality

HDMI content encrypted

This bit is high when HDCP decryption is in use (content is

protected). The signal goes low when HDCP is not being

used. Use this bit to allow copying of the content. The bit

should be sampled at regular intervals because it can

change on a frame-by-frame basis.

[5]

xx0xxxxx

xxx0xxxx

xxxx0000

HDMI HSYNC polarity

HDMI VSYNC polarity

HDMI pixel repetition

Returns HDMI HSYNC polarity.

Returns HDMI VSYNC polarity.

[4]

[3:0]

Returns current HDMI pixel repetition amount. 0 = 1×,

1 = 2× … The clock and data outputs are automatically

decimated by this value.

Rev. 0 | Page 13 of 40

AD9393

Default

Value

Hex Address

Read/Write

Bits

[5:4]

[3]

Register Name

Audio setup

Description

0x34

Read/write

xx00xxxx

xxxx0xxx

Must be written to 0b11 for proper operation.

0 = repeat Cr and Cb values.

Upconversion mode

1 = interpolate Cr and Cb values.

Enables the FIR filter for 4:2:2 CrCb output.

[2]

[1]

xxxxx0xx

xxxxxx0x

CrCb filter enable

CSC_ENABLE

Enables the color space converter (CSC). The default

settings for the CSC provide HDTV-to-RGB conversion.

Sets the fixed point position of the CSC coefficients,

including the A4, B4, and C4 offsets.

0x35

0x36

Read/write

[6:5]

x01xxxxx

CSC_MODE

00 = 1.0, −4096 to +4095.

01 = 2.0, −8192 to +8190.

1x = 4.0, −16,384 to +16,380.

[4:0]

[7:0]

xxx01100

01010010

CSC_COEFF_A1 MSB

CSC_COEFF_A1 LSB

MSB of Register 0x36.

Color space converter (CSC) coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x38.

0x37

0x38

Read/write

[4:0]

[7:0]

xxx01000

00000000

CSC_COEFF_A2 MSB

CSC_COEFF_A2 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x3A.

0x39

0x3A

Read/write

[4:0]

[7:0]

xxx00000

00000000

CSC_COEFF_A3 MSB

CSC_COEFF_A3 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x3C.

0x3B

0x3C

Read/write

[4:0]

[7:0]

xxx11001

11010111

CSC_COEFF_A4 MSB

CSC_COEFF_A4 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x3E.

0x3D

0x3E

Read/write

[4:0]

[7:0]

xxx11100

01010100

CSC_COEFF_B1 MSB

CSC_COEFF_B1 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x40.

0x3F

0x40

Read/write

[4:0]

[7:0]

***01000

00000000

CSC_COEFF_B2 MSB

CSC_COEFF_B2 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x42.

0x41

0x42

Read/write

[4:0]

[7:0]

xxx11110

10001001

CSC_COEFF_B3 MSB

CSC_COEFF_B3 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x44.

0x43

0x44

Read/write

[4:0]

[7:0]

xxx00010

10010010

CSC_COEFF_B4 MSB

CSC_COEFF_B4 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x46.

0x45

0x46

Read/write

[4:0]

[7:0]

xxx00000

00000000

CSC_COEFF_C1 MSB

CSC_COEFF_C1 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

Rev. 0 | Page 14 of 40

AD9393

Default

Value

Hex Address

0x47

Read/Write

Read/write

Bits

[4:0]

[7:0]

Register Name

Description

xxx01000

00000000

CSC_COEFF_C2 MSB

CSC_COEFF_C2 LSB

MSB of Register 0x48.

0x48

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x4A.

0x49

0x4A

Read/write

[4:0]

[7:0]

xxx01110

10000111

CSC_COEFF_C3 MSB

CSC_COEFF_C3 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

MSB of Register 0x4C.

0x4B

0x4C

Read/write

[4:0]

[7:0]

xxx11000

10111101

CSC_COEFF_C4 MSB

CSC_COEFF_C4 LSB

CSC coefficient for equation:

R_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

G_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

B_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

Must be written to 0x3B.

0x4D

0x4E

0x4F

0x50

0x56

0x57

Read/write

[7:0]

[7]

00110110

00100000

00001111

0xxxxxxx

x0xxxxxx

xxxx0xxx

xxxxx0xx

0

TMDS PLL Control1

TMDS PLL Control2

TMDS PLL Control3

Test

Must be written to 0x6D.

Must be written to 0x54.

Must be written to 0x20 for proper operation.

Test

Must be written to 0x0F (default) for proper operation.

A1 overrides the AV mute value with Bit 6.

Sets AV mute value if override is enabled.

Disables mute of video during AV mute.

Disables mute of audio during AV mute.

MCLK PLL enable—uses analog PLL.

AV mute override

AV mute value

Disable video mute

Disable audio mute

MCLK PLL enable

MCLK PLL_N

[6]

[3]

[2]

0x58

0x59

Read/write

[7]

[6:4]

0

MCLK PLL_N [2:0]—this controls the division of the MCLK

out of the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4 …

[3]

0

N_CTS_DISABLE

MCLK FS_N

Prevents the N/CTS packet on the link from writing to the N

and CTS registers.

[2:0]

Controls the multiple of 128 f_Sused for MCLK out.

0 = 128 × f_S, 1 = 256 × f_S, 2 = 384 × f_S, 7 = 1024 × f_S.

[6]

[5]

0

MDA/MCL PU

CLK term O/R

This disables the MDA/MCL pull-ups.

Clock termination power-down override: 0 = auto,

1 = manual.

[4]

0

Manual CLK term

FIFO reset UF

Clock termination: 0 = normal, 1 = disconnected.

This bit resets the audio FIFO if underflow is detected.

This bit resets the audio FIFO if overflow is detected.

This bit three-states the MDA/MCL lines.

[2]

[1]

FIFO reset OF

[0]

MDA/MCL three-state

Packet detected

0x5A

Read

[6:0]

These seven bits are updated if any specific packet has

been received since last reset or loss of clock detect.

Normal is 0x00.

Bit Data Packet Detected

0

1

2

3

4

5

6

AVI infoframe.

Audio infoframe.

SPD infoframe.

MPEG source infoframe.

ACP packets.

ISRC1 packets.

ISRC2 packets.

0x5B

Read

[3]

0

HDMI mode

0 = DVI, 1 = HDMI.

Rev. 0 | Page 15 of 40

AD9393

Default

Value

Hex Address

Read/Write

Bits

[7:6]

[5:3]

Register Name

Channel status

PCM audio data

Description

0x5E

Read

0

Mode = 00. All others are reserved.

When Bit 1 = 0 (linear PCM):

000 = two audio channels without pre-emphasis.

001 = two audio channels with 50 μs/15 μs pre-emphasis.

010 = reserved.

011 = reserved.

[2]

[1]

[0]

0

Copyright information

0 = software for which copyright is asserted.

1 = software for which no copyright is asserted.

Linear PCM identification

0 = audio sample word represents linear PCM samples.

1 = audio sample word used for other purposes.

Use of channel

status block

0 = consumer use of channel status block.

Per HDMI

Audio Channel Status

0x5F

Read

[7:0]

0

Channel status

category code

0x60

Read

[7:4]

[3:0]

[5:4]

0

Channel number

Source number

Clock accuracy

Per HDMI

0x61

Clock accuracy.

00 = Level II.

01 = Level III.

10 = Level I.

11 = reserved.

0011 = 32 kHz.

0000 = 44.1 kHz.

1000 = 88.2 kHz.

1100 = 176.4 kHz.

0010 = 48 kHz.

1010 = 96 kHz.

1110 = 192 kHz.

Word length.

[3:0]

0

Sampling frequency

0x62

Read

Word length

0000 = not specified.

0100 = 16 bits.

0011 = 17 bits.

0010 = 18 bits.

0001 = 19 bits.

0101 = 20 bits.

1000 = not specified.

1100 = 20 bits.

1011 = 21 bits.

1010 = 22 bits.

1001 = 23 bits.

1101 = 24 bits.

0x7B

Read

[7:0]

0

CTS[19:12]

Cycle time stamp. This 20-bit value is used with the N value

to regenerate an audio clock. For the remaining bits, see

Register 0x7C and Register 0x7D.

0x7C

0x7D

Read

[7:0]

[7:4]

[3:0]

0

CTS[11:4]

CTS[3:0]

N[19:16]

See Register 0x7B

20-bit N used with CTS to regenerate the audio clock. For

remaining bits, see Register 0x7E and Register 0x7F.

0x7E

Read

[7:0]

0

N[15:8]

N[7:0]

See Register 0x7D

0x7F

AVI Infoframe

0x80

Read

[7:0]

0

AVI infoframe version

Rev. 0 | Page 16 of 40

AD9393

Default

Value

Hex Address

Read/Write

Bits

Register Name

Description

0x81

Read

[6:5]

0

Y[1:0]

Y[1:0] indicates RGB, 4:2:2, or 4:4:4.

00 = RGB.

01 = YCrCb 4:2:2.

10 = YCrCb 4:4:4.

[4]

0

Active format information

status

Active format information present.

0 = no data.

1 = active format information valid.

B[1:0].

[3:2]

Bar information

00 = no bar information.

01 = horizontal bar information valid.

10 = vertical bar information valid.

11 = horizontal and vertical bar information valid.

[1:0]

[7:6]

[5:4]

[3:0]

0

Scan information

Colorimetry

S[1:0].

00 = no information.

01 = overscanned (television).

10 = underscanned (computer).

C[1:0].

0x82

Read

00 = no data.

01 = SMPTE 170M, ITU601.

10 = ITU709.

Picture aspect ratio

Active format aspect ratio

M[1:0].

00 = no data.

01 = 4:3.

10 = 16:9.

R[3:0].

1000 = same as picture aspect ratio.

1001 = 4:3 (center).

1010 = 16:9 (center).

1011 = 14:9 (center).

SC[1:0].

0x83

Read

[1:0]

0

Nonuniform picture scaling

00 = no known nonuniform scaling.

01 = picture has been scaled horizontally.

10 = picture has been scaled vertically.

11 = picture has been scaled horizontally and vertically.

0x84

0x85

Read

[6:0]

[3:0]

0

Video identification code

Pixel repeat

VIC[6:0] video identification code—refer to CEA EDID short

video descriptors.

PR[3:0] specifies how many times a pixel has been

repeated.

0000 = no repetition (pixel sent once).

0001 = pixel sent twice (repeated once).

0010 = pixel sent three times.

1001 = pixel sent 10 times.

0xA to 0xF reserved.

0x86

0x87

Read

[7:0]

[6:0]

0

Active line start LSB

New data flags

This represents the line number of the end of the top

horizontal bar. If 0, there is no horizontal bar. Combines

with Register 0x88 for a 16-bit value.

New data flags. These eight bits are updated if any specific

data changes. Normal (no NDFs) is 0x00. When any NDF

register is read, all bits reset to 0x00. All NDF registers

contain the same data.

Bit Data Packet Changed

0

1

2

3

4

5

6

AVI infoframe.

Audio infoframe.

SPD infoframe.

MPEG source infoframe.

ACP packets.

ISRC1 packets.

ISRC2 packets.

Rev. 0 | Page 17 of 40

AD9393

Default

Value

Hex Address

0x88

Read/Write

Read

Bits

[7:0]

Register Name

Description

0

Active line start MSB

Active line end LSB

Active line start MSB (see Register 0x86).

0x89

Read

This represents the line number of the beginning of a lower

horizontal bar. If greater than the number of active video

lines, there is no lower horizontal bar. Combines with

Register 0x8A for a 16-bit value.

0x8A

0x8B

Read

[7:0]

0

Active line end MSB

Active pixel start LSB

Active line end MSB. See Register 0x89.

This represents the last pixel in a vertical pillar bar at the

left side of the picture. If 0, there is no left bar. Combines

with Register 0x8C for a 16-bit value.

0x8C

0x8D

Read

[7:0]

0

Active pixel start MSB

Active pixel end LSB

Active pixel start MSB. See Register 0x8B.

This represents the first horizontal pixel in a vertical pillar-bar

at the right side of the picture. If greater than the maximum

number of horizontal pixels, there is no vertical bar. Com-

bines with Register 0x8E for a16-bit value.

0x8E

0x8F

0x90

0x91

Read

[7:0]

[6:0]

[7:0]

[7:4]

0

Active pixel end MSB

New data flags

Active pixel end MSB. See Register 0x8D.

New data flags (see Register 0x87).

Per HDMI

Audio infoframe version

Audio coding type

CT[3:0]. Audio coding type.

0x00 = refer to stream header.

0x01 = IEC60958 PCM.

0x02 = AC3.

0x03 = MPEG1 (Layer 1 and Layer 2).

0x04 = MP3 (MPEG1 Layer 3).

0x05 = MPEG2 (multichannel).

0x06 = AAC.

0x07 = DTS.

0x08 = ATRAC.

[2:0]

[4:2]

0

Audio coding count

Sampling frequency

CC[2:0]. Audio channel count.

000 = refer to stream header.

001 = two channels.

010 = three channels.

111 = eight channels.

SF[2:0]. Sampling frequency.

000 = refer to stream header.

001 = 32 kHz.

0x92

Read

010 = 44.1 kHz (CD).

011 = 48 kHz.

100 = 88.2 kHz.

101 = 96 kHz.

110 = 176.4 kHz.

111 = 192 kHz.

[1:0]

[7:0]

0

Sample size

SS [1:0]. Sample size.

00 = refer to stream header.

01 = 16 bits.

10 = 20 bits.

11 = 24 bits.

0x93

Read

Maximum bit rate

Maximum bit rate (compressed audio only). The value of

this field multiplied by 8 kHz represents the maximum bit

rate.

0x94

0x95

Read

[7:0]

[7]

0

Speaker mapping

Down-mix

CA[7:0]. Speaker mapping or placement for up to eight

channels. See Table 24.

DM_INH: down-mix inhibit.

0 = permitted or no information.

1 = prohibited.

[6:3]

0

Level shift

LSV[3:0]: level shift values with attenuation information.

0000 = 0 dB attenuation.

0001 = 1 dB attenuation.

. . .

1111 = 15 dB attenuation.

Rev. 0 | Page 18 of 40

AD9393

Default

Value

Hex Address

0x96

Read/Write

Read

Bits

[7:0]

[6:0]

Register Name

Description

0

Reserved.

0x97

Read

New data flags

New data flags (see Register 0x87).

Source Product Description (SPD) Infoframe

0x98

Read

[7:0]

0

Source product description

(SPD) infoframe version

Per HDMI

0x99

Read

[7:0]

Vender Name Character 1

Vender name character 1 (VN1) 7-bit ASCII code. The first of

eight characters naming the product company.

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

Read

[7:0]

[6:0]

[7:0]

0

VN2

VN2.

VN3

VN3.

VN4

VN4.

VN5

VN5.

VN6

VN6.

New data flags

VN7

New data flags (see Register 0x87).

VN7.

VN8.

VN8

Product Description

Character 1

Product Description Character 1 (PD1) 7-bit ASCII code. The

first of 16 characters that contains the model number and a

short description.

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

Read

[7:0]

[6:0]

[7:0]

[6:0]

[7:0]

0

PD2

PD2.

PD3

PD3.

PD4

PD4.

PD5

PD5.

New data flags

PD6

New data flags (see Register 0x87).

PD6.

PD7

PD7.

PD8

PD8.

PD9

PD9.

PD10

PD10.

PD11

PD11.

PD12

PD12.

New data flags

PD13

New data flags (see Register 0x87).

PD13.

PD14

PD14.

PD15

PD15.

PD16

PD16.

Source device

Information code

This is a code that classifies the source device.

0x00 = unknown.

0x01 = digital STB.

0x02 = DVD.

0x03 = D-VHS.

0x04 = HDD video.

0x05 = DVC.

0x06 = DSC.

0x07 = video CD.

0x08 = game.

0x09 = PC general.

New data flags (see Register 0x87).

0xB7

Read

[6:0]

0

New data flags

MPEG Source Infoframe

0xB8

Read

[7:0]

0

MPEG source infoframe

version

0xB9

Read

MB[0]

MB[0] (lower byte of MPEG bit rate in hertz). This is the

lower eight bits of 32 bits (4 bytes) that specify the MPEG

bit rate in hertz.

0xBA

0xBB

0xBC

Read

[7:0]

0

MB[1]

MB[2]

MB[3]

MB[1].

MB[2].

MB[3] (upper byte).

Rev. 0 | Page 19 of 40

AD9393

Default

Value

Hex Address

Read/Write

Bits

Register Name

Description

0xBD

Read

[4]

0

Field repeat

FR—new field or repeated field.

0 = new field or picture.

1 = repeated field.

[1:0]

0

MPEG frame

MF[1:0]. This identifies whether frame is an I, B, or P picture.

00 = unknown.

01 = I picture.

10 = B picture.

11 = P picture.

0xBE

0xBF

0xC0

Read

[7:0]

[6:0]

[7:0]

0

Reserved.

New data flags

New data flags (see Register 0x87).

Audio content protection

packet (ACP) type

Audio content protection packet (ACP) type.

0x00 = generic audio.

0x01 = IEC60958-identified audio.

0x02 = DVD audio.

0x03 = reserved for super audio CD (SACD).

0x04 to 0xFF = reserved.

ACP Packet Byte 0 (ACP_PB0).

ACP_PB1.

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

0xC8

Read

[7:0]

[6:0]

[7]

0

ACP Packet Byte 0

ACP_PB1

ACP_PB2

ACP_PB2.

ACP_PB3

ACP_PB3.

ACP_PB4

ACP_PB4.

ACP_PB5

ACP_PB5.

New data flags

ISRC1 continued

New data flags (see Register 0x87).

International standard recording code (ISRC1) continued.

This indicates an ISRC2 packet is being transmitted.

[6]

0

ISRC1 valid

0 = ISRC1 status bits and PBs not valid.

1 = ISRC1 status bits and PBs valid.

[2:0]

ISRC1 status

001 = starting position.

010 = intermediate position.

100 = final position.

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

Read

[7:0]

[6:0]

[7:0]

[6:0]

[7:0]

0

ISRC1 Packet Byte 0

ISRC1_PB1

ISRC1 Packet Byte 0 (ISRC1_PB0).

ISRC1_PB1.

ISRC1_PB2

ISRC1_PB2.

ISRC1_PB3

ISRC1_PB3.

ISRC1_PB4

ISRC1_PB4.

ISRC1_PB5

ISRC1_PB5.

New data flags

ISRC1_PB6

New data flags (see Register 0x87).

ISRC1_PB6.

ISRC1_PB7

ISRC1_PB7.

ISRC1_PB8

ISRC1_PB8.

ISRC1_PB9

ISRC1_PB9.

ISRC1_PB10

ISRC1_PB11

ISRC1_PB12

New data flags

ISRC1_PB13

ISRC1_PB14

ISRC1_PB15

ISRC1_PB16

ISRC2 Packet Byte 0

ISRC1_PB10.

ISRC1_PB11.

ISRC1_PB12.

New data flags (see Register 0x87).

ISRC1_PB13.

ISRC1_PB14.

ISRC1_PB15.

ISRC1_PB16.

ISRC2 Packet Byte 0 (ISRC2_PB0). This is transmitted only

when the ISRC bit continues (Register 0xC8, Bit[7]) is set to 1.

0xDD

0xDE

0xDF

0xE0

0xE1

0xE2

Read

[7:0]

[6:0]

[7:0]

0

ISRC2_PB1

ISRC2_PB2

New data flags

ISRC2_PB3

ISRC2_PB4

ISRC2_PB5

ISRC2_PB1.

ISRC2_PB2.

New data flags (see Register 0x87).

ISRC2_PB3.

ISRC2_PB4.

ISRC2_PB5.

Rev. 0 | Page 20 of 40

AD9393

Default

Value

Hex Address

0xE3

Read/Write

Read

Bits

[7:0]

[6:0]

[7:0]

Register Name

ISRC2_PB6

Description

0

ISRC2_PB6.

0xE4

ISRC2_PB7

ISRC2_PB7.

0xE5

ISRC2_PB8

ISRC2_PB8.

0xE6

ISRC2_PB9

ISRC2_PB9.

0xE7

New data flags

ISRC2_PB10

ISRC2_PB11

ISRC2_PB12

ISRC2_PB13

ISRC2_PB14

ISRC2_PB15

ISRC2_PB16

New data flags (see Register 0x87).

ISRC2_PB10.

0xE8

Read

0xE9

ISRC2_PB11.

0xEA

0xEB

ISRC2_PB12.

ISRC2_PB13.

0xEC

ISRC2_PB14.

0xED

0xEE

ISRC2_PB15.

ISRC2_PB16.

Rev. 0 | Page 21 of 40

AD9393

2-WIRE SERIAL CONTROL REGISTER DETAILS

This section describes certain register details. Note that not all

registers are discussed in this section.

0x25—Bits[7:6], Output CLK Select

These bits select the clock output on the DCLK ball. They

include ½× clock, a 2× clock, a 90° phase shifted clock, or

the normal pixel clock. The power-up default setting is 01.

See Table 10.

CHIP IDENTIFICATION

0x00—Bits[7:0], Chip Revision

An 8-bit value that reflects the current chip revision.

Table 10. Output Clock Select

0x17—Bits[3:0], HSYNCs per VSYNC MSB

Select

Result

These bits are four MSBs of the 12-bit counter that reports the

number of HSYNCs per VSYNC on the active input. This is

useful in determining the mode and aid in setting the PLL

divide ratio.

00

01

10

11

½× pixel clock

1× pixel clock

2× pixel clock

90° phase 1× pixel clock

0x18—Bit[7:0], HSYNCs per VSYNC LSB

These bits are eight LSBs of the 12-bit counter that reports the

number of HSYNCs per VSYNCs on the active input.

0x25—Bits[5:4], Output Drive Strength

These two bits select the drive strength for all the high speed

digital outputs (except the VSOUT, HSOUT, and O/E). Higher

drive strength results in faster rise/fall times and in general

makes it easier to capture data. Lower drive strength results in

slower rise/fall times and helps to reduce EMI and digitally

generated power supply noise. The power-up default setting is

11. See Table 11.

0x23—Bits[7:0], HSYNC Duration

These bits are an 8-bit register that sets the duration of the

HSYNC output pulse. The leading edge of the HSYNC output

is triggered by the internally generated, phase-adjusted PLL

feedback clock. The AD9393 then counts a number of pixel

clocks equal to the value in this register. This triggers the

trailing edge of the HSYNC output, which is also phase-

adjusted. The power-up default is 32.

Table 11. Output Drive Strength

Output Drive

Result

0x24—Bit[7], HSYNC Output Polarity

00

01

10

11

Low output drive strength

Medium low output drive strength

Medium high output drive strength

High output drive strength

This bit sets the polarity of the HSYNC output. Setting this bit

to 0 sets the HSYNC output to active low. Setting this bit to 1

sets the HSYNC output to active high. The power-up default

setting is 1.

0x25—Bits[3:2], Output Mode

0x24—Bit[6], VSYNC Output Polarity

These bits choose between four options for the output mode.

4:4:4 mode is standard RGB; 4:2:2 mode is YCrCb, which

reduces the number of active output pins from 24 to 16; 4:4:4

is double data rate (DDR) output mode; and the data is RGB

mode that changes on every clock edge. The power-up default

setting is 00. See Table 12.

This bit sets the polarity of the VSYNC output. Setting this bit to 0

sets the VSYNC output to active low. Setting this bit to 1 sets the

VSYNC output to active high. The power-up default is 1.

0x24—Bit[5] DE Output Polarity

This bit sets the polarity of the display enable (DE). 0 = DE

output polarity is negative. 1 = DE output polarity is positive.

The power-up default is 1.

Table 12. Output Mode

Output

Mode

0x24—Bit[4], Field Output Polarity

Result

00

01

10

11

4:4:4 RGB mode

This bit sets the polarity of the odd/even field output signal on

Ball A7. 0 = active low = even field; active high = odd field. 1 =

active high = odd field; active high = even field. The power-up

default setting is 1.

4:2:2 YCrCb mode + DDR 4:2:2 on D[7:0] (secondary)

DDR 4:4:4 DDR mode + DDR 4:2:2 on D[7:0] (secondary)

12-bit 4:2:2

0x24—Bit[0], Output CLK Invert

This bit allows inversion of the output clock as specified by

Register 0x25, Bits[7:6]. 0 = noninverted clock. 1 = inverted

clock. The power-up default setting is 0.

Rev. 0 | Page 22 of 40

AD9393

0x25—Bit[1], Primary Output Enable

0x26—Bit[0], Power-Down

This bit places the primary output in active or high impedance

mode. The primary output is designated when using either 4:2:2

or DDR 4:4:4. In these modes, the data on the red and green

output channels (D[23:8]) is the primary output, whereas the

output data on the blue channel (D[7:0], DDR YCrCb) is the

secondary output. Double data rate 0 = primary output is in

high impedance mode. 1 = primary output is enabled. The

power-up default setting is 1.

This bit is used to put the chip in power-down mode. In this

mode, the power dissipation is reduced to a fraction of the

typical power (see Table 2 for exact power dissipation). When

in power-down, the HSOUT, VSOUT, DCLK, and all 24 of the

data outputs are put into a high impedance state. Circuit blocks

that continue to be active during power-down include the

voltage references, sync detection, and the serial register. These

blocks facilitate a fast start up from power-down. 0 = normal

operation. 1 = power-down. The power-up default setting is 0.

0x25—Bit[0], Secondary Output Enable

0x27—Bit[7], Auto Power-Down Enable

This bit places the secondary output in active or high impe-

dance mode. The secondary output is designated when using

either 4:2:2 or DDR 4:4:4. In these modes, the data on the blue

output channel (D[7:0]) is the secondary output and the output

data on the red and green channels (D[23:8]) is the primary

output. Secondary output is always a DDR YCrCb data mode.

0 = secondary output is in high impedance mode. 1 = second-

ary output is enabled. The power-up default setting is 0.

This bit enables the chip to go into low power mode, or seek

mode if no sync inputs are detected. 0 = auto power-down

disabled. 1 = chip powers down if no sync inputs are present.

The power-up default setting is 1.

0x27—Bit[6], HDCP A0

This bit sets the LSB of the address of the HDCP I²C. Set this bit

to 1 only for a second receiver in a dual-link configuration. The

power-up default is 0.

0x26—Bit[7], Output Three-State

When enabled, this bit puts all outputs in a high impedance

state. 0 = normal outputs. 1 = all outputs in high impedance

mode. The power-up default setting is 0.

0x27—Bit[5], Clock Test

The power-up default setting is 0.

0x26—Bit[5], S/PDIF Three-State

When enabled, this bit places the S/PDIF audio output pins in a

high impedance state. 0 = normal S/PDIF output. 1 = S/PDIF

pins in high impedance mode. The power-up default setting is 0.

0x26—Bit[4], I²S Three-State

When enabled, this bit places the I²S output pins in a high

impedance state. 0 = normal I²S output. 1 = I²S pins are in

high impedance mode. The power-up default setting is 0.

0x26—Bit[3], Power-Down Ball Polarity

This bit defines the polarity of the input power-down ball.

0 = power-down ball is active low. 1 = power-down ball is

active high. The power-up default setting is 1.

0x26—Bits[2:1], Power-Down Ball Function

These bits define the different operational modes of the power-

down ball. These bits are functional only when the power-down

ball is active; when it is inactive, the part is powered up and

functioning. 0x = the chip is powered down and all outputs are

in high impedance mode. 1x = the chip remains powered up,

but all outputs are in three-state outputs mode. The power-up

default setting is 00.

Rev. 0 | Page 23 of 40

AD9393

0x2E—Bits[6:5], I²S Output Mode

BT656 GENERATION

These bits select between four options for the I²S output: I²S,

right-justified, left-justified, or raw IEC60958 mode. The

power-up default setting is 00. See Table 13.

0x27—Bit[4], BT656 EN

This bit enables the output to be BT656-compatible with the

defined start of active video (SAV) and the end of active video

(EAV) controls to be inserted. These require specification of the

number of active lines, active pixels per line, and delays to place

these markers. 0 = disable BT656 video mode. 1 = enable BT656

video mode. The power-up default setting is 0.

Table 13. I²S Output Select

I²S Output Mode

Result

00

01

10

11

I²S mode

Right-justified

Left-justified

Raw IEC60958 mode

0x27—Bit[3], Force DE Generation

This bit allows the use of the internal DE generator in DVI

mode. 0 = internal DE generation disabled. 1 = force DE

generation via programmed registers. The power-up default

setting is 0.

0x2E—Bits[4:0], I²S Bit Width

These bits set the I²S bit width for right-justified mode. The

power-up default setting is 24 bits.

0x27—Bits[2:0], Interlace Offset

These bits define the offset in HSYNCs from Field 0 to Field 1.

The power-up default setting is 000.

0x2F—Bit[6], TMDS Sync Detect

This read-only bit indicates the presence of a TMDS DE.

0 = no TMDS DE present. 1 = TMDS DE detected.

0x28—Bits[7:2], VSYNC Delay

These bits set the delay (in lines) from the leading edge of

VSYNC to active video. The power-up default setting is 24d.

0x2F—Bit[5], TMDS Active

This read-only bit indicates the presence of a TMDS clock.

0 = no TMDS clock present. 1 = TMDS clock detected.

0x28—Bits[1:0], HSYNC Delay MSB and 0x29—Bits[7:0],

HSYNC Delay LSB

0x2F—Bit[4], AV Mute

These 10 bits set the delay (in pixels) from the HSYNC leading

edge to the start of active video. The power-up default setting is

0x104.

This read-only bit indicates the presence of AV mute based on

general control packets. 0 = AV not muted. 1 = AV muted.

0x2F—Bit[3], HDCP Keys Read

0x2A—Bits[3:0], Line Width MSB and 0x2B—Bits[7:0]

Line Width LSB

This read-only bit reports if the HDCP keys were read

successfully. 0 = failure to read HDCP keys. 1 = HDCP

keys read.

These 12 bits set the width of the active video line (in pixels).

The power-up default setting is 0x500.

0x2F—Bits[2:0], HDMI Quality

0x2C—Bits[3:0], Screen Height MSB and 0x2D—Bits[7:0]

Screen Height LSB

These read-only bits indicate a level of HDMI quality based

on the DE (display enable) edges. A larger number indicates

a higher quality.

These 12 bits set the height of the active screen (in lines). The

power-up default setting is 0x2D0.

0x30—Bit[6], HDMI Content Encrypted

0x2E—Bit[7], CTRL EN

This read-only bit is high when HDCP decryption is in use

(content is protected). The signal goes low when HDCP is

not being used. Use this bit to to allow copying of the content.

Sample the bit at regular intervals because it can change on a

frame-by-frame basis. 0 = HDCP not in use. 1 = HDCP

decryption in use.

When set, this bit allows CTRL[3:0] signals decoded from the

DVI to be output on the I²S data pins. 0 = I²S signals on I²S

lines. 1 = CTRL[3:0] output on I²S lines. The power-up default

setting is 0.

Rev. 0 | Page 24 of 40

AD9393

0x30—Bit[5], HDMI HSYNC Polarity

COLOR SPACE CONVERSION

This read-only bit indicates the polarity of the HDMI HSYNC.

0 = HDMI HSYNC polarity is active low. 1 = HDMI HSYNC

polarity is active high.

The default power up values for the color space converter

coefficients (Register 0x34 through Register 0x4C) are set

for ATSC RGB-to-YCrCb conversion. They are completely

programmable for other conversions.

0x30—Bit[4], HDMI VSYNC Polarity

0x34—Bit[1], CSC_ENABLE

This read-only bit indicates the polarity of the HDMI VSYNC.

0 = HDMI VSYNC polarity is low active. 1 = HDMI VSYNC

polarity is high active.

This bit enables the color space converter. 0 = disable color

space converter. 1 = enable color space converter. The power-

up default setting is 0.

0x30—Bits[3:0], HDMI Pixel Repetition

0x35—Bits[6:5], CSC_MODE

These read-only bits indicate the pixel repetition on HDMI.

0 = 1×, 1 = 2×, 2 = 3×, with a maximum repetition of 10× (0x9).

See Table 14.

These two bits set the fixed-point position of the CSC

coefficients, including the A4, B4, and C4 offsets.

Table 14.

Table 15. CSC Fixed Point Converter Mode

Select

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

Repetition Multiplier

Select

Result

1×

2×

3×

4×

5×

6×

7×

8×

9×

10×

00

01

1x

1.0, −4096 to +4095

2.0, −8192 to +8190

4.0, −16,384 to +16,380

0x35—Bits[4:0], CSC_COEFF_A1 MSB and 0x36—

Bits[7:0], CSC_COEFF_A1 LSB

Register 0x35[4:0] form the five MSBs of the Color Space

Conversion Coefficient A1. These bits, combined with the

eight LSBs of Register 0x36 form a 13-bit, twos complement

coefficient, which is user programmable. The equation takes

the form of:

0x34—Bit[5:4], Audio Setup

R

G

B

_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

This bit must be written to 0b11 for proper audio operation.

0x34—Bit[3], Up Conversion Mode

The default value for the 13-bit A1 coefficient is 0x0C52.

0 = repeat Cb and Cr values. 1 = interpolate Cb and Cr values.

0x34—Bit[2], CrCb Filter Enable

0x37—Bits[4:0], CSC_COEFF_A2 MSB and 0x38—

Bits[7:0], CSC _COEFF_A2 LSB

Enables the FIR filter for 4:2:2 CrCb output.

Register 0x37[4:0] form the five MSBs of the Color Space

Conversion Coefficient A2. Combined with the eight LSBs of

Register 0x38, these bits form a 13-bit, twos complement

coefficient that is user programmable. The equation takes

the form of:

R

_OUT= (A1 × R_IN) + (A2 × G_IN) + (A3 × B_IN) + A4

_OUT= (B1 × R_IN) + (B2 × G_IN) + (B3 × B_IN) + B4

_OUT= (C1 × R_IN) + (C2 × G_IN) + (C3 × B_IN) + C4

The default value for the 13-bit A2 coefficient is 0x0800.

G

B

Rev. 0 | Page 25 of 40

AD9393

0x39—Bits[4:0], CSC_COEFF_A3 MSB and 0x3A—

Bits[7:0], CSC_COEFF_A3 LSB

0x58—Bit[3], N_CTS_Disable

This bit prevents the N/CTS packet on the link from writing to

the N and CTS registers.

The default value for the 13-bit A3 is 0x00000.

0x3B—Bits[4:0], CSC_COEFF_A4 MSB and 0x3C—

Bits[7:0], CSC_COEFF_A4 LSB

0x58—Bits[2:0], MCLK FS_N

These bits control the multiple of 128 f_Sused for MCLK out. See

Table 17.

The default value for the 13-bit A4 is 0x19D7.

0x3D—Bits[4:0], CSC_COEFF_B1 MSB and 0x3E—

Bits[7:0], CSC_COEFF_B1 LSB

Table 17.

MCLK FS_N [2:0]

f_SMultiple

128

256

384

512

640

768

896

1024

The default value for the 13-bit B1 is 0x1C54.

0

1

2

3

4

5

6

7

0x3F—Bits[4:0], CSC_COEFF_B2 MSB and 0x40—

Bits[7:0], CSC_COEFF_B2 LSB

The default value for the 13-bit B2 is 0x0800.

0x41—Bits[4:0], CSC_COEFF_B3 MSB and 0x42—

Bits[7:0], CSC_COEFF_B3 LSB

The default value for the 13-bit B3 is 0x1E89.

0x43—Bits[4:0], CSC_COEFF_B4 MSB and 0x44—

Bits[7:0], CSC_COEFF_B4 LSB

0x59—Bit[6], MDA/MCL PU

The default value for the 13-bit B4 is 0x0291.

This bit disables the MDA/MCL pull-ups.

0x59—Bit[5], CLK Term O/R

0x45—Bits[4:0], CSC_COEFF_C1 MSB and 0x46—

Bits[7:0], CSC_COEFF_C1 LSB

This bit allows for overriding during power-down.

0 = auto, 1 = manual.

The default value for the 13-bit C1 is 0x0000.

0x47—Bits[4:0], CSC_COEFF_C2 MSB and 0x48—

Bits[7:0], CSC_COEFF_C2 LSB

0x59—Bit[4], Manual CLK Term

This bit allows normal clock termination or disconnects this.

0 = normal, 1 = disconnected.

The default value for the 13 bit C2 is 0x0800.

0x49—Bits[4:0], CSC_COEFF_C3 MSB and 0x4A—

Bits[7:0], CSC_COEFF_C3 LSB

0x59—Bit[2], FIFO Reset UF

This bit resets the audio FIFO if underflow is detected.

0x59—Bit[1], FIFO Reset OF

The default value for the 13-bit C3 is 0x0E87.

0x4B—Bits[4:0], CSC_COEFF_C4 MSB and 0x4C—

Bits[7:0], CSC_COEFF_C4 LSB

This bit resets the audio FIFO if overflow is detected.

0x59—Bit[0], MDA/MCL Three-State

The default value for the 13-bit C4 is 0x18BD.

0x58—Bit[7], MCLK PLL Enable

This bit three-states the MDA/MCL lines to allow in-circuit

programming of the EEPROM.

This bit enables the use of the analog PLL.

0x58—Bits[6:4], MCLK PLL_N

0x5A—Bits[6:0], Packet Detected

This register indicates if a data packet in specific sections has

been detected. These seven bits are updated if any specific

packet has been received since the last reset or loss of clock

detect. The default setting is 0x00. See Table 18.

These bits control the division of the MCLK out of the PLL. See

Table 16.

MCLK PLL_N [2:0]

MCLK Divide Value

Table 18.

0

1

2

3

4

5

6

7

/1

/2

/3

/4

/5

/6

/7

/8

Packet Detect Bit

Packet Detected

AVI infoframe

Audio infoframe

SPD infoframe

MPEG source infoframe

ACP packets

0

1

2

3

4

5

6

ISRC1 packets

ISRC2 packets

Rev. 0 | Page 26 of 40

AD9393

0x89—Bits[7:0], Active Line End LSB and 0x8A—

Bits[7:0], Active Line End MSB

0x5B—Bit[3], HDMI Mode

0 = DVI, 1 = HDMI.

These bits indicate the last line of active video. All lines past

this comprise a lower horizontal bar. This is used in letter-box

modes. If the 2-byte value is greater than the number of lines in

the display, there is no lower horizontal bar.

0x7B—Bits[7:0], CTS[19:12], 0x7C—Bits[7:0] CTS[11:4],

and 0x7D—Bits[7:4], CTS[3:0]

These bits are the most significant eight bits of a 20-bit word used

with the 20-bit N term in the regeneration of the audio clock.

0x8B—Bits[7:0], Active Pixel Start LSB and 0x8C—

Bits[7:0], Active Pixel Start MSB

0x7D—Bits[3:0], N[19:16], 0x7E—Bits[7:0], N[15:8], and

0x7F—Btis[7:0], N[7:0]

These bits indicate the first pixel in the display, which is active

video. All pixels before this comprise a left vertical bar. If the

2-byte value is 0x00, there is no left bar.

These are the most significant four bits of a 20-bit word used

with the 20-bit CTS term to regenerate the audio clock.

0x81—Bits[6:5], Y[1:0]

0x8D—Bits[7:0], Active Pixel End LSB and 0x8E—

Bits[7:0], Active Pixel End MSB

This register indicates whether data is RGB, 4:4:4, or 4:2:2.

These bits indicate the last active video pixel in the display. All

pixels past this comprise a right vertical bar. If the 2-byte value

is greater than the number of pixels in the display, there is no

vertical bar.

Table 19.

Y

00

01

10

Video Data

RGB

YCrCb 4:2:2

YCrCb 4:4:4

0x8F—Bits[6:0], New Data Flags

See the 0x87—Bits[6:0], New Data Flags (NDF) section.

0x91—Bits[7:4], Audio Coding Type

0x81—Bit[4], Active Format Information Status

0 = no data. 1 = active format information valid.

0x84—Bits[6:0], Video Identification Code

See the CEA EDID short video descriptors in EIA/CEA-861B.

0x85—Bits[3:0], Pixel Repeat

These bits identify the audio coding so that the receiver may

process audio properly. See Table 21.

Table 21.

CT[3:0]

Audio Coding

Refer to stream header

IEC60958 PCM

AC3

0x0

0x1

0x2

This value indicates how many times the pixel was repeated,

for example, 0x0 = no repeats, sent once, 0x8 = eight repeats,

sent nine times.

0x3

0x4

0x5

0x6

MPEG1 (Layer 1 and Layer 2)

MP3 (MPEG1 Layer 3)

MPEG2 (multichannel)

AAC

0x86—Bits[7:0], Active Line Start LSB and 0x88—

Bits[7:0] Active Line Start MSB

These bits indicate the beginning line of active video. All

lines before this comprise a top horizontal bar. This is used

in letter box modes. If the 2-byte value is 0x00, there is no

horizontal bar.

0x7

DTS

0x8

ATRAC

0x91—Bits[2:0], Audio Channel Count

0x87—Bits[6:0], New Data Flags (NDF)

These bits specify how many audio channels (2 channels to

8 channels) are being sent.

This register indicates whether data in specific sections has

changed. In the address space from 0x80 to 0xFF, each register

address ending in 0b111 (for example, 0x87, 0x8F, 0x97, 0xAF)

is an NDF register. They all have the same data and all are reset

when any one of them is read. See Table 20.

Table 22.

CC[2:0]

Channel Count

000

Refer to stream header

Table 20.

NDF Bit Number

001

010

011

100

101

110

111

2

3

4

5

6

7

8

Changes Occurred

AVI infoframe

Audio infoframe

SPD infoframe

MPEG source infoframe

ACP packets

ISRC1 packets

0

1

2

3

4

5

6

ISRC2 packets

Rev. 0 | Page 27 of 40

AD9393

Table 23.

0x93—Bits[7:0], Maximum Bit Rate

Abbreviation

Speaker Placement

Front left

Front center

For compressed audio only, when this value is multiplied by

8 kHz, it represents the maximum bit rate. A value of 0x08 in

this field yields a maximum bit rate of (8 kHz × 8 kHz = 64 kHz).

FL

FC

FR

FCL

FCR

RL

Front right

0x94—Bits[7:0], Speaker Mapping

Front center left

Front center right

Rear left

Bits[4:0] define the suggested placement of speakers. Bits[7:5]

are currently not available. See Table 23 and Table 24.

RC

Rear center

RR

Rear right

RCL

RCR

LFE

Rear center left

Rear center right

Low frequency effect

Table 24. Speaker Mapping

CA

Channel Number

Bit 4

0

1

Bit 3

0

1

0

1

Bit 2

0

1

0

1

0

1

0

1

Bit 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Bit 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8

7

6

5

4

3

2

1

FR

FL

LFE

FC

RC

RL

FC

RR

FC

RC

FC

RRC

FRC

RLC

FLC

FC

LFE

v

LFE

v

FC

LFE

RC

RL

FC

LFE

v

LFE

RR

FC

LFE

Rev. 0 | Page 28 of 40

AD9393

0x95—Bits[6:3], Level Shift

0xB7—Bits[6:0], New Data Flags

These bits define the amount of attenuation. The value directly

corresponds to the amount of attenuation: for example, 0000 =

0 dB, 0001 = 1 dB, … ,1111 = 15 dB attenuation.

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

0xB9—Bits[7:0], MB0

0x97—Bits[6:0], New Data Flags

These are the lower eight bits of 32 bits that specify the MPEG

bit rate in hertz.

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

0xBD—Bit[4], Field Repeat

0x99—Bits[7:0], Vender Name Character 1

This defines whether the field is new or repeated. 0 = new field

or picture. 1 = repeated field.

This is the first character in eight that is the name of the

vendor that appears on the product. The data characters are

7-bit ASCII code.

0xBD—Bits[1:0], MPEG Frame

This identifies the frame as I, B, or P. See Table 26.

0x9F—Bits[6:0], New Data Flags

Table 26.

MF[1:0]

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

Frame Type

Unknown

I (picture)

B (picture)

P (picture)

00

01

0xA2—Bits[7:0], Product Description Character 1

This is the first character of 16, which contains the model

number and a short description of the product. The data

characters are 7-bit ASCII code.

10

11

0xA7—Bits[6:0], New Data Flags

0xBF—Bits[6:0], New Data Flags

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

0xAF—Bits[6:0], New Data Flags

0xC0—Bits[7:0], Audio Content Protection Packet (ACP

Type)

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

These bits define which audio content protection is used.

0xB4—Bits[7:0], Source Device Information Code

Table 27.

Code

These bytes classify the source device. See Table 25.

ACP Type

0x00

0x01

0x02

0x03

Generic audio

IEC 60958-identified audio

DVD-audio

Reserved for super audio CD (SACD)

Reserved

Table 25.

SDI Code

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

Source

Unknown

Digital STB

DVD

D-VHS

HDD video

DVC

DSC

Video CD

Game

0x04 to 0xFF

0xC7—Bits[6:0], New Data Flags

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

0xC8—Bit[7], ISRC1 Continued

This bit indicates that a continuation of the 16 ISRC1 packet

bytes (an ISRC2 packet) is being transmitted.

PC general

Rev. 0 | Page 29 of 40

AD9393

0xC8—Bit[6], ISRC1 Valid

0xD7—Bits[6:0], New Data Flags

This bit is an indication of whether the ISRC1 packet bytes are

valid. 0 = ISRC1 status bits and PBs not valid. 1 = ISRC1 status

bits and PBs valid.

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

0xDC—Bits[7:0], ISRC2 Packet Byte 0 (ISRC2_PB0)

0xC8—[2:0], ISRC Status

This is transmitted only when the ISRC continued bit

(Register 0xC8 Bit 7) is set to 1.

These bits define where in the ISRC track the samples are. At

least two transmissions of 001 occur at the beginning of the

track, while continuous transmission of 010 occurs in the

middle of the track, followed by at least two transmissions of

100 near the end of the track.

0xDF—Bits[6:0], New Data Flags

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

0xE7—Bits[6:0], New Data Flags

0xCF—Bits[6:0], New Data Flags

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

See the 0x87—Bits[6:0], New Data Flags (NDF) section for a

description.

Rev. 0 | Page 30 of 40

AD9393

2-WIRE SERIAL CONTROL PORT

A 2-wire serial interface control interface is provided in the

AD9393.

DATA TRANSFER VIA SERIAL INTERFACE

For each byte of data read or written, the MSB is the first bit of

the sequence.

The 2-wire serial interface is comprised of a clock (SCL) and a

bidirectional data (SDA) ball. The HDMI flat panel interface

acts as a slave for receiving and transmitting data over the serial

interface. When the serial interface is not active, the logic levels

on SCL and SDA are pulled high by external pull-up resistors.

If the AD9393 does not acknowledge the master device during a

write sequence, the SDA remains high so the master can gener-

ate a stop signal. If the master device does not acknowledge the

AD9393 during a read sequence, the AD9393 interprets this as

the end of data. The SDA remains high, so the master can

generate a stop signal.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Change data on

SDA only when SCL is low. If SDA changes state while SCL is

high, the serial interface interprets that action as a start or stop

sequence.

To write data to specific control registers of the AD9393, the

8-bit address of the control register of interest must be written

after the slave address has been established. This control register

address is the base address for subsequent write operations. The

base address autoincrements by 1 for each byte of data written

after the data byte intended for the base address. If more bytes

are transferred than there are available addresses, the address

does not increment and remains at its maximum value. Any

base address higher than the maximum value does not produce

an acknowledge signal.

There are six components to serial bus operation:

•

Start signal

Slave address byte

Base register address byte

Data byte to read or write

Stop signal

Acknowledge (ACK)

Data are read from the control registers of the AD9393 in a

similar manner. Reading requires two data transfer operations:

When the serial interface is inactive (SCL and SDA are high),

communications are initiated by sending a start signal. The start

signal is a high-to-low transition on SDA while SCL is high.

This signal alerts all slave devices that a data transfer sequence

is coming.

•

The base address must be written with the R/W bit of the

slave address byte low to set up a sequential read operation.

W

•

Reading (the R/ bit of the slave address byte high)

begins at the previously established base address. The

address of the read register autoincrements after each

byte is transferred.

The first eight bits of data transferred after a start signal

comprise an 7-bit slave address (the first 7 bits) and a single

W

R/ bit (the eight bit). The R/ bit indicates the direction of

the data transfer, read from (1) or write to (0) the slave device. If

the transmitted slave address matches the address of the device,

the AD9393 acknowledges by bringing SDA low on the ninth

SCL pulse. If the addresses do not match, the AD9393 does not

acknowledge.

To terminate a read/write sequence to the AD9393, a stop signal

must be sent. A stop signal comprises a low-to-high transition

of SDA while SCL is high.

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first genera-

ting a stop signal to terminate the current communication.

This is used to change the mode of communication (read,

write) between the slave and master without releasing the

serial interface lines.

Table 28. Serial Port Addresses

Bit 7

A₆(MSB)

1

Bit 6

Bit 5

Bit 4

Bit 3

A₂

1

Bit 2

A₁

0

Bit 1

A₀

0

Bit 0

A₅

0

A₄

0

A₃

1

R/W

SDA

t_BUFF

t_STAH

t_DSU

t_DHO

t_STOSU

t_STASU

t_DAL

SCL

t_DAH

Figure 7. Serial Port Read/Write Timing

Rev. 0 | Page 31 of 40

AD9393

SERIAL INTERFACE READ/WRITE EXAMPLES

Write to one control register:

Read from one control register:

1. Start signal

W

2. Slave address byte (R/ bit = low)

W

2. Slave address byte (R/ bit = low)

3. Base address byte

4. Start signal

3. Base address byte

4. Data byte to base address

5. Stop signal

W

5. Slave address byte (R/ bit = high)

6. Data byte from base address

7. Stop signal

Write to four consecutive control registers:

1. Start signal

Read from four consecutive control registers:

1. Start signal

W

2. Slave address byte (R/ bit = low)

3. Base address byte

W

2. Slave address byte (R/ bit = low)

4. Data byte to base address

5. Data byte to (base address + 1)

6. Data byte to (base address + 2)

7. Data byte to (base address + 3)

8. Stop signal

3. Base address byte

4. Start signal

5. Slave address byte (R/ bit = high)

6. Data byte from base address

7. Data byte from (base address + 1)

8. Data byte from (base address + 2)

9. Data byte from (base address + 3)

10. Stop signal

W

SDA

SCL

BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

ACK

BIT 7

Figure 8. Serial Interface—Typical Byte Transfer

Rev. 0 | Page 32 of 40

AD9393

PCB LAYOUT RECOMMENDATIONS

The AD9393 is a high precision, high speed digital device. To

achieve the maximum performance from the part, it is impor-

tant to have a well laid-out board. The following sections are a

guide for designing a board using the AD9393.

In some cases, using separate ground planes is unavoidable, so

it is recommended to place a single ground plane under the

AD9393. The location of the split should be at the receiver of

the digital outputs. In this case, it is even more important to

place components wisely because the current loops are much

longer (current takes the path of least resistance).

POWER SUPPLY BYPASSING

It is recommended to bypass each power supply ball with a

0.1 μF capacitor. The exception is in the case where two or

more supply pins are adjacent to each other. For these groupings

of powers/grounds, it is only necessary to have one bypass

capacitor. The fundamental idea is to have a bypass capacitor

within about 0.5 cm of each power ball. Also, avoid placing

the capacitor on the opposite side of the PC board from the

AD9393, because that interposes resistive vias in the path.

OUTPUTS (BOTH DATA AND CLOCKS)

Try to minimize the trace length that the digital outputs have

to drive. Longer traces have higher capacitance, which require

more current that causes more internal digital noise.

Shorter traces reduce the possibility of reflections.

Adding a series resistor of value 50 Ω to 200 Ω can suppress

reflections, reduce EMI, and reduce the current spikes inside

the AD9393. If series resistors are used, place them as close as

possible to the AD9393 pins (although try not to add vias or

extra length to the output trace to move the resistors closer).

The bypass capacitors should be physically located between the

power plane and the power ball. Current should flow from the

power plane to the capacitor to the power ball. Do not make the

power connection between the capacitor and the power ball.

Placing a via underneath the capacitor pads down to the power

plane is generally the best approach.

If possible, limit the capacitance that each of the digital outputs

drives to less than 10 pF. This can be accomplished easily by

keeping traces short and by connecting the outputs to only one

device. Loading the outputs with excessive capacitance increases

the current transients inside of the AD9393 and creates more

digital noise on its power supplies.

It is particularly important to maintain low noise and good

stability of PV_DD(the clock generator supply). Abrupt changes

in PV_DDcan result in similarly abrupt changes in sampling

clock phase and frequency. This can be avoided by paying

careful attention to regulation, filtering, and bypassing. It is

highly desirable to provide separate regulated supplies for

each of the circuitry groups (V_Dand PV_DD).

DIGITAL INPUTS

The digital inputs on the AD9393 are designed to work with

3.3 V signals, but are tolerant of 5.0 V signals. Therefore, no

extra components need to be added if using 5.0 V logic.

Some graphic controllers use substantially different levels of

power when active (during active picture time) and when idle

(during HSYNC and VSYNC periods). This can result in a

measurable change in the voltage supplied to the regulator,

which can in turn produce changes in the regulated supply

voltage. This can be mitigated by regulating the PV_DDfrom a

different, cleaner power source (for example, from a 12 V supply).

Any noise that enters the HSYNC input trace can add jitter to

the system. Therefore, minimize the trace length and do not run

any digital or other high frequency traces near it.

It is recommended to use a single ground plane for the entire

board. Experience has shown repeatedly that the noise perfor-

mance is the same or better with a single ground plane. Using

multiple ground planes can be detrimental because each separate

ground plane is smaller and long ground loops can result.

Rev. 0 | Page 33 of 40

AD9393

COLOR SPACE CONVERTER (CSC) COMMON SETTINGS

HDTV YCRCB (0 TO 255) TO RGB (0 TO 255) (DEFAULT SETTING FOR AD9393)

Table 29.

Register

Address

Value

Red/Cr Coeff 1

0x36

Red/Cr Coeff 2

0x38

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x0C

0x37

0x08

0x39

0x00

0x3B

0x19

0x52

0x00

0xD7

Table 30.

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x1C

0x3F

0x08

0x41

0x3E

0x43

0x02

0x54

0x00

0x89

0x91

Table 31.

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x00

0x47

0x08

0x49

0x0E

0x4B

0x18

0x00

0x87

0xBD

HDTV YCRCB (16 TO 235) TO RGB (0 TO 255)

Table 32.

Register

Address

Value

Red/Cr Coeff 1

0x36

Red/Cr Coeff 2

0x38

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x47

0x37

0x04

0x39

0x00

0x3B

0x1C

0x2C

0xA8

0x00

0x1F

Table 33.

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x1D

0x3F

0x04

0x41

0x1F

0x43

0x01

0xDD

0xA8

0x26

0x34

Table 34.

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x00

0x47

0x04

0x49

0x08

0x4B

0x1B

0x00

0xA8

0x 75

0x7B

SDTV YCRCB (0 TO 255) TO RGB (0 TO 255)

Table 35.

Register

Address

Value

Red/Cr Coeff 1

0x36

Red/Cr Coeff 2

0x38

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x2A

0x37

0x08

0x39

0x00

0x3B

0x1A

0xF8

0x00

0x84

Table 36.

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x1A

0x3F

0x08

0x41

0x1D

0x43

0x04

0x6A

0x00

0x50

0x23

Table 37.

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x00

0x47

0x08

0x49

0x0D

0x4B

0x19

0x00

0xDB

0x12

Rev. 0 | Page 34 of 40

AD9393

SDTV YCRCB (16 TO 235) TO RGB (0 TO 255)

Table 38.

Register

Address

Value

Red/Cr Coeff 1

0x36

Red/Cr Coeff 2

0x38

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x35

0x46

0x37

0x04

0x39

0x00

0x3B

0x1C

0x3C

0x84

0x63

0xA8

0x00

Table 39.

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x1C

0x3F

0x04

0x41

0x1E

0x43

0x02

0xC0

0xA8

0x6F

0x1E

Table 40.

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x00

0x47

0x04

0x49

0x08

0x4B

0x1B

0x00

0xA8

0x11

0xAD

RGB (0 TO 255) TO HDTV YCRCB (0 TO 255)

Table 41.

Register

Address

Value

Red/Cr Coeff 1

0x36

Red/Cr Coeff 2

0x38

Red/Cr Coeff

0x3A

Red/Cr Offset

0x3C

0x35

0x08

0x37

0x18

0x39

0x1F

0x3B

0x08

0x2D

0x93

0x3F

0x00

Table 42.

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x03

0x3F

0x0B

0x41

0x01

0x43

0x00

0x68

0x71

0x27

0x00

Table 43.

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x1E

0x47

0x19

0x49

0x08

0x4B

0x08

0x21

0xB2

0x2D

0x00

RGB (0 TO 255) TO HDTV YCRCB (16 TO 235)

Table 44.

Register

Address

Value

Red/Cr Coeff 1

0x36

Red/Cr Coeff 2

0x38

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x07

0x37

0x19

0x39

0x1F

0x3B

0x08

0x06

0xA0

0x5B

0x00

Table 45.

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x02

0x3F

0x09

0x41

0x00

0x43

0x01

0xED

0xD3

0xFD

0x00

Table 46.

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x1E

0x47

0x1A

0x49

0x07

0x4B

0x08

0x64

0x96

0x06

0x00

Rev. 0 | Page 35 of 40

AD9393

RGB (0 TO 255) TO SDTV YCRCB (0 TO 255)

Table 47.

Register

Address

Value

Red/Cr Coeff 1

0x36

Red/Cr Coeff 2

0x38

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x08

0x37

0x19

0x39

0x1E

0x3B

0x08

0x2D

0x27

0xAC

0x00

Table 48.

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x04

0x3F

0x09

0x41

0x01

0x43

0x00

0xC9

0x64

0xD3

0x00

Table 49.

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x1D

0x47

0x1A

0x49

0x08

0x4B

0x08

0x3F

0x93

0x2D

0x00

RGB (0 TO 255) TO SDTV YCRCB (16 TO 235)

Table 50.

Register

Address

Value

Red/Cr Coeff 1

0x36

Red/Cr Coeff 2

0x38

Red/Cr Coeff 3

0x3A

Red/Cr Offset

0x3C

0x35

0x07

0x37

0x1A

0x39

0x1E

0x3B

0x08

0x06

0x1E

0xDC

0x00

Table 51.

Register

Address

Value

Green/Y Coeff 1

0x3E

Green/Y Coeff 2

0x40

Green/Y Coeff 3

0x42

Green/Y Offset

0x44

0x3D

0x04

0x3F

0x08

0x41

0x01

0x43

0x01

0x1C

0x11

0x91

0x00

Table 52.

Register

Address

Value

Blue/Cb Coeff 1

0x46

Blue/Cb Coeff 2

0x48

Blue/Cb Coeff 3

0x4A

Blue/Cb Offset

0x4C

0x45

0x1D

0x47

0x1B

0x49

0x07

0x4B

0x08

0xA3

0x57

0x06

0x00

Rev. 0 | Page 36 of 40

AD9393

OUTLINE DIMENSIONS

A1 CORNER

INDEX AREA

6.10

6.00 SQ

5.90

10

9

8

7

6

5

3

4

2

1

A

B

C

D

E

F

BALL A1

PAD CORNER

4.50

BSC SQ

TOP VIEW

0.50

BSC

G

H

J

K

BOTTOM VIEW

DETAIL A

0.75

REF

DETAIL A

*

1.40 MAX

0.65 MIN

0.15 MIN

COPLANARITY

0.08 MAX

0.35

0.30

0.25

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-225

WITH THE EXCEPTION TO PACKAGE HEIGHT.

Figure 9. 76-Pin Chip Scale Package Pin Grid Array [CSP_BGA]

6 mm × 6 mm × 1.2 mm

(BC-76-2)

Dimensions shown in millimeters

ORDERING GUIDE

Max Speed

Temperature

Model

(MHz) Digital

Range

Package Description

Package Option

BC-76-2

AD9393BBCZ-80¹

AD9393BBCZRL-80¹

AD9393/PCBZ¹

80

−10°C to +80°C

76-Pin Chip Scale Package Pin Grid Array (CSP_BGA)

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. 0 | Page 37 of 40

AD9393

NOTES

Rev. 0 | Page 38 of 40

AD9393

NOTES

Rev. 0 | Page 39 of 40

AD9393

NOTES

registered trademarks are the property of their respective owners.

D08043-0-10/09(0)

Rev. 0 | Page 40 of 40


型号：	AD9393
厂家：	ADI
描述：	Low Power HDMI Display Interface 低功耗HDMI显示接口
文件：	总40页 (文件大小：819K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9393 [ADI]

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