AD9410BSQZ [ADI]
IC 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP80, POWER, HEAT SINK, PLASTIC, LQFP-80, Analog to Digital Converter;
| 型号： | AD9410BSQZ |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP80, POWER, HEAT SINK, PLASTIC, LQFP-80, Analog to Digital Converter 转换器 |
| 文件： | 总20页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 210 MSPS
A/D Converter
a
AD9410
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SNR = 54 dB with 99 MHz Analog Input
500 MHz Analog Bandwidth
V
V
V
REF
REF
OUT
AGND
DGND
D
DD CC
IN
On-Chip Reference and Track/Hold
1.5 V p-p Differential Analog Input Range
5.0 V and 3.3 V Supply Operation
3.3 V CMOS/TTL Outputs
AD9410
REFERENCE
OR
A
10
PORT
A
D9 –D0
A
A
Power: 2.1 W Typical at 210 MSPS
Demultiplexed Outputs Each at 105 MSPS
Output Data Format Option
Data Sync Input and Data Clock Output Provided
Interleaved or Parallel Data Output Option
10
A
A
ADC
10-BIT
CORE
IN
T/H
IN
OR
B
10
PORT
B
D9 –D0
B
B
DS
DS
ENCODE
ENCODE
TIMING AND
SYNCHRONIZATION
APPLICATIONS
DCO
Communications and Radar
Local Multipoint Distribution Service (LMDS)
High-End Imaging Systems and Projectors
Cable Reverse Path
DCO
DFS
I/P
Point-to-Point Radio Link
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
High Resolution at High Speed—The architecture is specifically
designed to support conversion up to 210 MSPS with outstand-
ing dynamic performance.
The AD9410 is a 10-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is opti-
mized for high-speed conversion and ease of use. The product
operates at a 210 MSPS conversion rate, with outstanding
dynamic performance over its full operating range.
Demultiplexed Output—Output data is decimated by two and
provided on two data ports for ease of data transport.
The ADC requires a 5.0 V and 3.3 V power supply and up to a
210 MHz differential clock input for full performance operation.
No external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS-compatible,
and separate output power supply pins also support interfacing
with 3.3 V logic.
Output Data Clock—The AD9410 provides an output data
clock synchronous with the output data, simplifying the timing
between data and other logic.
Data Synchronization—A DS input is provided to allow for
synchronization of two or more AD9410s in a system, or
to synchronize data to a specific output port in a single
AD9410 system.
The clock input is differential and TTL/CMOS-compatible. The
10-bit digital outputs can be operated from 3.3 V (2.5 V to 3.6 V)
supplies. Two output buses support demultiplexed data up to
105 MSPS rates, and binary or two’s complement output coding
format is available. A data sync function is provided for timing-
dependent applications. An output clock simplifies interfacing to
external logic. The output data bus timing is selectable for parallel
or interleaved mode, allowing for flexibility in latching output data.
Fabricated on an advanced BiCMOS process, the AD9410
is available in an 80-lead surface-mount plastic package
(PowerQuad®2) specified over the industrial temperature range
(–40°C to +85°C).
PowerQuad is a registered trademark of Amkor Electronics, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD9410–SPECIFICATIONS
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS;
T = 25ꢀC; unless otherwise noted.)
DC SPECIFICATIONS
A
Test
Parameter
Temp
Level
Min
Typ
Max
Unit
RESOLUTION
10
Bits
DC ACCURACY
No Missing Codes1
Differential Nonlinearity
Full
25°C
Full
25°C
Full
25°C
Full
IV
I
VI
I
VI
I
V
Guaranteed
0.5
–1.0
–1.0
–2.5
–3.0
–6.0
+1.25
+1.5
+2.5
+3.0
+6.0
LSB
LSB
LSB
LSB
% FS
ppm/°C
Integral Nonlinearity
1.65
Gain Error
Gain Tempco
0
130
ANALOG INPUT
Input Voltage Range (With Respect to AIN)
Common-Mode Voltage
Input Offset Voltage
Full
Full
25°C
Full
Full
Full
Full
25°C
25°C
V
V
I
VI
VI
V
VI
V
768
3.0
+3
mV p-p
V
mV
mV
V
ppm/°C
Ω
pF
–15
–20
2.4
+15
+20
2.6
Reference Voltage
Reference Tempco
Input Resistance
Input Capacitance
Analog Bandwidth, Full Power
2.5
50
875
3
500
610
1250
V
MHz
POWER SUPPLY
Power Dissipation AC2
Power Dissipation DC3
25°C
Full
Full
Full
25°C
V
2.1
2.0
128
401
+0.5
W
W
mA
mA
mV/V
VI
VI
VI
I
2.4
3
IVCC
145
480
+7.5
3
IVD
Power Supply Rejection Ratio PSRR
–7.5
NOTES
1Package heat slug should be attached when operating at greater than 70°C ambient temperature.
2Encode = 210 MSPS, AIN = –0.5 dBFS 10 MHz sine wave, IVDD = 31 mA typical at CLOAD = 5 pF.
3Encode = 210 MSPS, AIN = dc, outputs not switching.
Specifications subject to change without notice.
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock
input = 210 MSPS; T = 25ꢀC; unless otherwise noted.)
SWITCHING SPECIFICATIONS
A
Test
Parameter
Temp
Level
Min
Typ
Max
Unit
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Full
Full
VI
IV
IV
IV
V
210
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
Cycles
100
Encode Pulsewidth High (tEH
)
25°C
25°C
25°C
25°C
Full
1.2
1.2
2.4
2.4
1.0
0.65
Encode Pulsewidth Low (tEL
)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Valid Time (tV)
Output Propagation Delay (tPD
Output Rise Time (tR)
V
VI
VI
V
3.0
)
Full
7.4
25°C
25°C
Full
Full
Full
Full
Full
Full
1.8
1.4
4.8
1
Output Fall Time (tF)
V
CLKOUT Propagation Delay1 (tCPD
)
VI
IV
IV
IV
VI
VI
2.6
0
0.5
6.4
2
Data to DCO Skew (tPD–tCPD
DS Setup Time (tSDS
DS Hold Time (tHDS
)
)
)
0
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
A = 6, B = 6
A = 7, B = 6
NOTES
1CLOAD = 5 pF.
Specifications subject to change without notice.
–2–
REV. 0
AD9410
DIGITAL SPECIFICATIONS (V = 3.3 V, V = 3.3 V, V = 5.0 V; 2.5 V external reference; A = –0.5 dBFS;
Clock input = 210 MSPS; TA = 25ꢀC; unless otherwise noted.)
DD
D
CC
IN
Test
Parameter
Temp
Level
Min
Typ
Max
Unit
DIGITAL INPUTS
DFS, Input Logic “1” Voltage
DFS, Input Logic “0” Voltage
DFS, Input Logic “1” Current
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
IV
IV
V
V
V
V
IV
V
V
IV
V
4
V
V
µA
µA
µA
µA
V
kΩ
V
V
V
1
50
50
400
1
DFS, Input Logic “0” Current
I/P Input Logic “1” Current1
I/P Input Logic “0” Current1
ENCODE, ENCODE Differential Input Voltage
ENCODE, ENCODE Differential Input Resistance
ENCODE, ENCODE Common-Mode Input Voltage2
DS, DS Differential Input Voltage
DS, DS Common-Mode Input Voltage
Digital Input Pin Capacitance
0.4
0.4
1.6
1.5
1.5
3
V
pF
DIGITAL OUTPUTS
Logic “1” Voltage (VDD = 3.3 V)
Logic “0” Voltage (VDD = 3.3 V)
Output Coding
Full
Full
VI
VI
VDD – 0.05
0.05
Binary or Two’s Complement
V
V
NOTES
1I/P pin Logic “1” = 5 V, Logic “0” = GND. It is recommended to place a series 2.5 kΩ ( 10%) resistor to VDD when setting to Logic “1” to limit input current.
2See Encode Input section in Applications section.
Specifications subject to change without notice.
(VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = –0.5 dBFS; Clock input = 210 MSPS;
T = 25ꢀC; unless otherwise noted.)
A
AC SPECIFICATIONS
Test
Level
Parameter
Temp
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
25°C
25°C
V
V
2
2
ns
ns
f
IN = 10.3 MHz
fIN = 82 MHz
IN = 160 MHz
25°C
25°C
25°C
I
I
V
52.5
52
55
54
53
dB
dB
dB
f
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
f
f
IN = 10.3 MHz
IN = 82 MHz
25°C
25°C
25°C
I
51
50
54
53
52
dB
dB
dB
I
fIN = 160 MHz
Effective Number of Bits
V
f
f
IN = 10.3 MHz
IN = 82 MHz
25°C
25°C
25°C
I
8.3
8.1
8.8
8.6
8.4
Bits
Bits
Bits
I
fIN = 160 MHz
Second Harmonic Distortion
V
f
f
IN = 10.3 MHz
IN = 82 MHz
25°C
25°C
25°C
I
–56
–55
–65
–63
–65
dBc
dBc
dBc
I
fIN = 160 MHz
Third Harmonic Distortion
V
f
f
IN = 10.3 MHz
IN = 82 MHz
25°C
25°C
25°C
I
–58
–57
–69
–67
–62
dBc
dBc
dBc
I
fIN = 160 MHz
Spurious Free Dynamic Range (SFDR)
V
f
f
IN = 10.3 MHz
IN = 82 MHz
25°C
25°C
25°C
I
56
54
61
60
58
dBc
dBc
dBc
I
fIN = 160 MHz
V
Two-Tone Intermod Distortion IMD1
fIN1 = 80.3 MHz, fIN2 = 81.3 MHz
25°C
V
58
dBFS
NOTES
1IN1, IN2 level = –7 dBFS.
Specifications subject to change without notice.
REV. 0
–3–
AD9410
Figure 1. Timing Diagram
–4–
REV. 0
AD9410
ABSOLUTE MAXIMUM RATINGS1
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
VD, VCC, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to VCC + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . 0 V to VDD + 0.5 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to VD + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature2 . . . . . . . . . . . . . . . . 150°C
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
NOTES
V. Parameter is a typical value only.
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability. Stresses
above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
2Typical
soldered), for multilayer board in still air with solid ground plane.
θJA = 22°C/W (heat slug not soldered), typical θJA = 16°C/W (heat slug
ORDERING GUIDE
Temperature
Package
Package
Option
Model
Range
Description
AD9410BSQ
AD9410/PCB
–40°C to +85°C
25°C
PowerQuad 2
Evaluation Board
SQ-80
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9410 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
AD9410
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1, 2, 8, 9, 12, 13, 16, 17, 20, 21, 24,
27, 28, 29, 30, 71, 72, 73, 74, 77, 78
AGND
Analog Ground.
3, 7, 14, 15
4
5
6
10
11
18
19
22
23
VCC
5 V Supply. (Regulate to within 5%.)
Internal Reference Output.
Internal Reference Input.
Do Not Connect.
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Data Sync (Input)—True. Tie LOW if not used.
Data Sync (Input)—Complement. Float and decouple with 0.1 µF
capacitor if not used.
REFOUT
REFIN
DNC
AIN
AIN
ENCODE
ENCODE
DS
DS
25, 26, 31, 32, 69, 70, 75, 76
33, 40, 49, 52, 59, 68
34, 41, 48, 53, 60, 67
35–39
42–46
47
VD
DGND
VDD
DB0–DB4
DB5–DB9
ORB
3.3 V Analog Supply. (Regulate to within 5%.)
Digital Ground.
3.3 V Digital Output Supply. (2.5 V to 3.6 V)
Digital Data Output for Channel B. (LSB = DB0.)
Digital Data Output for Channel B. (MSB = DB9.)
Data Overrange for Channel B.
50
51
DCO
DCO
Clock Output—Complement.
Clock Output—True.
54–58
61–65
66
79
80
D
D
ORA
DFS
I/P
A0–DA4
A5–DA9
Digital Data Output for Channel A. (LSB = DA0.)
Digital Data Output for Channel A. (MSB = DA9.)
Data Overrange for Channel A.
Data Format Select. HIGH = Two’s Complement, LOW = Binary.
Interleaved or Parallel Output Mode. Low = Parallel Mode, High =
Interleaved Mode. If tying high, use a current limiting series resistor
(2.5 kΩ) to the 5 V supply.
–6–
REV. 0
AD9410
PIN CONFIGURATION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
V
DD
DGND
AGND
AGND
1
2
PIN 1
IDENTIFIER
D
D
D
D
D
V
A4
A3
A2
A1
A0
V
3
CC
4
REF
OUT
REF
5
IN
6
DNC
(LSB)
V
7
CC
AGND
AGND
8
DD
DGND
DCO
9
AD9410
TOP VIEW
80-Lead PowerQuad2
(Not to Scale)
10
11
A
A
IN
DCO
IN
DGND
AGND 12
AGND 13
V
DD
OR
D
B
V
V
14
15
CC
CC
(MSB)
B9
45
44
43
42
41
D
D
D
D
V
AGND 16
AGND 17
B8
B7
B6
B5
DD
ENCODE 18
19
ENCODE
20
AGND
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
DNC ꢂ DO NOT CONNECT
REV. 0
–7–
AD9410
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Out-of-Range Recovery Time
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Noise (For Any Range Within the ADC)
Differential Analog Input Voltage Range
FSdBm − SIGNALdBFS
VNOISE = |Z|×0.001×10
10
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential voltage
is computed by observing the voltage on a single pin and subtract-
ing the voltage from the other pin, which is 180 degrees out of
phase. Peak-to-peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement
again. The difference is then computed between both peak
measurements.
Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level, and SIGNAL is the signal level within the ADC
reported in dB below full scale. This value includes both thermal
and quantization noise.
Power Supply Rejection Ratio
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
The ratio of a change in input offset voltage to a change in
power supply voltage.
Effective Number of Bits
Signal-to-Noise-and-Distortion (SINAD)
The effective number of bits (ENOB) is calculated from the
measured SINAD based on the equation.
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics, but excluding dc.
Full Scale Amplitude
Input Amplitude
SINADMEASURED – 1.76 dB + 20 log
Signal-to-Noise Ratio (Without Harmonics)
ENOB =
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
6.02
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing implica-
tions of changing tENCH in text. At a given clock rate, these specs
define an acceptable ENCODE duty cycle.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or dBFS (always
related back to converter full scale).
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Transient Response Time
Transient response time is defined as the time it takes for the
ADC to reacquire the analog input after a transient from 10%
above negative full scale to 10% below positive full scale.
2
V
FULL SCALErms
Z INPUT
POWERFULL SCALE = 10 log
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
0.001
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
Worst Other Spur
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least-square curve fit.
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
–8–
REV. 0
AD9410
Table I. Output Coding (VREF = 2.5 V)
Digital Outputs
Offset Binary
Digital Outputs
Two’s Complement
Step
AIN–AIN
ORA, ORB
> 0.768
0.768
11 1111 1111
11 1111 1111
01 1111 1111
01 1111 1111
1
0
•
1023
•
•
•
•
•
•
•
•
•
513
512
511
•
0.0015
0.0
10 0000 0001
10 0000 0000
01 1111 1111
•
00 0000 0001
00 0000 0000
11 1111 1111
•
0
0
0
•
•
0
1
–0.0015
•
•
•
•
•
0
–0.768
< –0.768
00 0000 0000
00 0000 0000
10 0000 0000
10 0000 0000
V
CC
V
CC
1.5kꢃ
1.5kꢃ
A
A
VREFOUT
IN
IN
2.25kꢃ
2.25kꢃ
Figure 6. Equivalent Reference Output Circuit
Figure 2. Equivalent Analog Input Circuit
V
CC
V
CC
DFS
100kꢃ
VREFIN
Figure 7. Equivalent DFS Input Circuit
Figure 3. Equivalent Reference Input Circuit
V
CC
17.5kꢃ
V
CC
300ꢃ
300ꢃ
DS
DS
450ꢃ
450ꢃ
17kꢃ
8kꢃ
17kꢃ
8kꢃ
7.5kꢃ
ENCODE
ENCODE
100ꢃ
100ꢃ
Figure 8. Equivalent DS Input Circuit
Figure 4 Equivalent Encode Input Circuit
V
CC
17.5kꢃ
V
300ꢃ
DD
I/P
DIGITAL
OUTPUT
7.5kꢃ
Figure 9. Equivalent I/P Input Circuit
Figure 5. Equivalent Digital Output Circuit
REV. 0
–9–
AD9410–Typical Performance Characteristics
55
54
53
52
51
50
49
48
47
46
45
0
ENCODE = 210MSPS
IN
SNR = 54.5dB
SINAD = 53.5dB
A
= 40MHz @ –0.5dBFS
–20
–40
SNR
–60
–80
SINAD
–100
–120
0
50
100
150
– MHz
200
250
0
105
MHz
A
IN
TPC 1. Single Tone at 40 MHz, Encode = 210 MSPS
TPC 4. SNR/SINAD vs. AIN Encode = 210 MSPS
0
55.0
ENCODE = 210MSPS
IN
54.5
A
= 100MHz @ –0.5dBFS
SNR
–20
–40
SNR = 53.5dB
SINAD = 52.5dB
54.0
53.5
53.0
–60
52.5
SINAD
52.0
51.5
51.0
50.5
50.0
–80
–100
–120
0
105
100
120
140
160
180
200
220
240
MHz
MHz
TPC 2. Single Tone at 100 MHz, Encode = 210 MSPS
TPC 5. SNR/SINAD vs. FS AIN = 70 MHz
60
55
50
45
40
35
0
ENCODE = 210MSPS
IN
SNR = 53dB
SINAD = 52dB
A
= 160MHz @ –0.5dBFS
–20
–40
SNR
SINAD
–60
–80
–100
–120
30
0
0.5
1.0
1.5
2.0
ns
2.5
3.0
3.5
4.0
0
105
MHz
TPC 3. Single Tone at 160 MHz, Encode = 210 MSPS
TPC 6. SNR/SINAD vs. Encode Positive Pulsewidth
(FS = 210 MSPS, AIN = 70 MHz)
–10–
REV. 0
AD9410
0
–20
2.52
2.51
2.50
2.49
2.48
2.47
2.46
ENCODE = 210MSPS
1, A 2 = –7dBFS
SFDR = 62dBFS
A
IN
IN
–40
–60
–80
–100
–120
0
105
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
MHz
ANALOG SUPPLY
TPC 7. Two Tone Test AIN 1 = 80.3 MHz, AIN 2 = 81.3 MHz
TPC 10. VREFOUT vs. Analog 5 V Supply
55.5
55.0
54.5
460
410
360
310
260
210
160
110
60
IAhi3
54.0
SNR
53.5
53.0
52.5
IAhi5
Ivdd
SINAD
52.0
10
100
51.5
–40
–20
0
20
40
60
80
100
120
120
140
160
180
200
220
TEMPERATURE – ꢀC
MSPS
TPC 8. SNR/SINAD vs. Temperature,
Encode = 210 MSPS, AIN = 70 MHz
TPC 11. Power Supply Currents vs. Encode
74
72
70
68
66
64
62
60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
H2
H3
58
–40
–20
0
20
40
60
80
100
120
0
0.5
1.0
1.5
2.0
2.5
mA
TEMPERATURE – ꢀC
TPC 9. Second and Third Harmonics vs. Temperature;
IN = 70 MHz, Encode = 210 MSPS
TPC 12. VREFOUT vs. ILOAD
A
REV. 0
–11–
AD9410
5.1
4.9
4.7
4.5
4.3
4.1
3.9
2.503
2.502
2.501
2.500
2.499
2.498
2.497
2.496
T
PD
T
V
T
CPD
–40
–20
0
20
40
60
80
–40
–20
0
20
40
60
80
TEMPERATURE – ꢀC
TEMPERATURE – ꢀC
TPC 13. VREFOUT vs. Temperature
TPC 14. TPD, TV, TCPD vs. Temperature
–12–
REV. 0
AD9410
Analog Input
APPLICATION NOTES
THEORY OF OPERATION
The analog input to the AD9410 is a differential buffer. For
best dynamic performance, impedances at AIN and AIN should
match. The analog input has been optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance will degrade
significantly if the analog input is driven with a single-ended
signal. A wideband transformer such as Minicircuits ADT1-1WT
can be used to provide the differential analog inputs for applica-
tions that require a single-ended-to-differential conversion. Both
analog inputs are self-biased by an on-chip resistor divider to a
nominal 3 V. (See Equivalent Circuits section.)
The AD9410 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantiza-
tion by the flash 10-bit core. For ease of use the part includes
an onboard reference and input logic that accepts TTL, CMOS,
or PECL levels.
USING THE AD9410
ENCODE Input
Any high-speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A Track/Hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at the
A/D output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9410, and the
user is advised to give commensurate thought to the clock source.
To limit SNR degradation to less than 1 dB, a clock source with
less than 1.25 ps rms jitter is required for sampling at Nyquist.
(Valpey Fisher VF561 is an example.) Note that required jitter
accuracy is a function of input frequency and amplitude. Consult
Analog Devices’ application note AN-501, “Aperture Uncer-
tainty and ADC System Performance,” for more information.
Special care was taken in the design of the Analog Input section
of the AD9410 to prevent damage and corruption of data when the
input is overdriven. The nominal input range is 1.5 V diff p-p.
The nominal differential input range is 768 mV p-p × 2.
A
IN
3.384
3.000
The ENCODE input is fully TTL/CMOS-compatible. The
clock input can be driven differentially or with a single-ended
signal. Best performance will be obtained when driving the clock
differentially. Both ENCODE inputs are self-biased to 1/3 × VCC
by a high impedance resistor divider. (See Equivalent Circuits
section.) Single-ended clocking, which may be appropriate for
lower frequency or nondemanding applications, is accomplished
by driving the ENCODE input directly and placing a 0.1 µF
capacitor at ENCODE.
A
IN
2.616
Figure 12. Typical Analog Input Levels
Digital Outputs
The digital outputs are TTL/CMOS-compatible for lower power
consumption. The outputs are biased from a separate supply
(VDD), allowing easy interface to external logic. The outputs are
CMOS devices which will swing from ground to VDD (with no
dc load). It is recommended to minimize the capacitive load the
ADC drives by keeping the output traces short (<1 inch, for a
total CLOAD < 5 pF). It is also recommended to place low value
(20 Ω) series damping resistors on the data lines to reduce switch-
ing transient effects on performance.
ENCODE AD9410
TTL/CMOS
GATE
ENCODE
0.1ꢄF
Figure 10. Driving Single-Ended Encode Input at
TTL/CMOS Levels
An example where the clock is obtained from a PECL driver is
shown in Figure 11. Note that the PECL driver is ac-coupled to
the ENCODE inputs to minimize input current loading. The
AD9410 can be dc-coupled to PECL logic levels resulting in the
ENCODE input currents increasing to approximately 8 mA
typically. This is due to the difference in dc bias between the
ENCODE inputs and a PECL driver. (See Equivalent Cir-
cuits section.)
Clock Outputs (DCO, DCO)
The input ENCODE is divided by two and available off-chip at
DCO and DCO. These clocks can facilitate latching off-chip,
providing a low skew clocking solution (see timing diagram).
These clocks can also be used in multiple AD9410 systems to
synchronize the ADCs. Depending on application, DCO or
DCO can be buffered and used to drive the DS inputs on a
second AD9410, ensuring synchronization. The on-chip clock
buffers should not drive more than 5 pF–7 pF of capacitance to
limit switching transient effects on performance.
0.1
ꢄF
ENCODE AD9410
PECL
GATE
ENCODE
Voltage Reference
0.1
ꢄF
510ꢃ
510ꢃ
A stable and accurate 2.5 V voltage reference is built into the
AD9410 (VREF OUT). The input range can be adjusted by
varying the reference voltage. No appreciable degradation in
performance occurs when the reference is adjusted 5%. The full-
scale range of the ADC tracks reference voltage changes linearly
within the 5% tolerance.
GND
Figure 11. Driving the Encode Inputs Differentially
REV. 0
–13–
AD9410
Timing
Data Sync (DS)
The AD9410 provides latched data outputs, with six pipeline
delays in interleaved mode (see Figure 1). In parallel mode, the
A Port has one additional cycle of latency added on-chip to line
up transitions at the data ports—resulting in a latency of seven
cycles for the A Port. The length of the output data lines and
loads placed on them should be minimized to reduce transients
within the AD9410; these transients can detract from the
converter’s dynamic performance.
The Data Sync input, DS, can be used in applications requir-
ing that a given sample will appear at a specific output Port A or
B. When DS is held high, the ADC data outputs and clock do not
switch and are held static. Synchronization is accomplished by the
assertion (falling edge) of DS, within the timing constraints
TSDS and THDS relative to an encode rising edge. (On initial
synchronization THDS is not relevant.) If DS falls within the
required setup time (TSDS) before a given encode rising edge N,
the analog value at that point in time will be digitized and avail-
able at Port B six cycles later (interleaved mode). The very next
sample, N+1, will be sampled by the next rising encode edge and
available at Port A six cycles after that encode edge (interleaved
mode). In dual parallel mode the A Port has a seven cycle latency,
the B Port has a six cycle latency, but data is available at the
same time.
The minimum guaranteed conversion rate of the AD9410 is
100 MSPS. At internal clock rates below 100 MSPS, dynamic
performance may degrade. Note that lower effective sampling
rates can be obtained simply by sampling just one output port—
decimating the output by two. Lower sampling frequencies can
also be accommodated by restricting the duty cycle of the clock
such that the clock high pulsewidth is a maximum of 5 ns.
EVALUATION BOARD
REFERENCE
The AD9410 evaluation board offers an easy way to test the
AD9410. The board requires an analog input, clock, and 3 V,
5 V power supplies. The digital outputs and output clocks are
available at a standard 80-lead header P2, P3. The board has
several different modes of operation, and is shipped in the fol-
lowing configuration:
The AD9410 has an on-chip reference of 2.5 V available at
REFOUT (Pin 4). Most applications will simply tie this output
to the REFIN input (Pin 5). This is accomplished by placing a
jumper at E1, E6. An external reference can be used placing a
jumper at E1, E3.
Output Timing
•
•
•
Output Timing = Parallel Mode
Output Format = Offset Binary
Internal Voltage Reference
The chip has two timing modes (see timing diagram). Inter-
leaved mode is selected by Jumper E11, E7. Parallel mode is
selected by Jumper E11, E14.
Power Connector
Data Format Select
Power is supplied to the board via detachable 4-pin power strips
P1, P4, P5.
Data Format Select sets the output data format that the ADC
outputs. Setting DFS (Pin 79) low at E12, E10 sets the output
format to be offset binary; setting DFS high at E12, E16 sets the
output to be two’s complement.
VDAC – Optional DAC Supply Input (3.3 V)
EXT REF – Optional External VREF Input (2.5 V)
V
DD – Logic Supply (3.3 V)
DS Pin
3.3 VA – Analog Supply (3.3 V)
5 V – Analog Supply (5 V)
The DS, DS inputs are available at SMB connectors J9X and
J10X. The board is shipped with DS pulled to ground by R26.
DS is floating (R25X is not placed).
Analog Inputs
The evaluation board accepts a 1.5 V p-p analog input signal
centered at ground at SMB J8. This input is terminated to 50 Ω
on the board at the transformer secondary, but can be termi-
nated at the SMB if an alternative termination is desired. The
input is ac-coupled prior to the transformer. The transformer is
band limited to frequencies between approximately 1 MHz and
400 MHz.
DAC Outputs
Each channel is reconstructed by an on-board dual channel
DAC, an AD9751 to assist in debug. The performance of the
DAC has not been optimized and will not give an accurate
measure of the full performance of the ADC. It is a current
output DAC with on-board 50 Ω termination resistors. The
outputs are available at J3 and J4.
Encode
The encode input to the board is at SMB connector J1. The
input is terminated on the board with 50 Ω to ground. The
(>0.5 V p-p) input is ac-coupled and drives a high-speed
differential line receiver (MC10EL16). This receiver provides
sub- nanosecond rise times at its outputs—a requirement for
the ADC clock inputs for optimum performance. The EL16
outputs are PECL levels and are ac-coupled to meet the common-
mode dc levels at the AD9410 encode inputs.
–14–
REV. 0
AD9410
GND
GND
GND
5V
5V
C1
C2
C3
C5
C4
C40
0.1ꢄF
MC10EL16
10ꢄF
10ꢄF
10ꢄF
10ꢄF
10ꢄF
ꢅ
ꢅ
ꢅ
ꢅ
ꢅ
R14
8.2kꢃ
R19
R11
330ꢃ
C7
1
2
3
4
8
7
6
5
5V
NC
VCC
Q
8.2kꢃ
J1
0.1ꢄF
EXT REF VDAC
VDD
3.3VA
5V
D
ENCT
ENCC
U1
C6
D
Q
R8
0.1ꢄF
1
2
3
4
VDAC
GND
GND
R9
24kꢃ
50ꢃ
R18
24kꢃ
C8
0.1ꢄF
R15
330ꢃ
VBB
GND
VEE
GND
P4
EXT REF
GND
GND
GND GND
GND
5V
VDD
1
2
3
4
GND
C14
0.1ꢄF
3.3VA
GND
R4
2.5kꢃ
R6
100ꢃ
C10
0.1ꢄF
3.3VA
P1
P5
GND
VDD/3.3V
GND
GND
C11
GND
NOTE:
DA9
DA8
DA7
R3, R6, R7, R24 OPTIONAL
E10
E16
E12
0.1ꢄF
R7
100ꢃ
(CAN BE ZERO ꢃ)
1
2
3
4
3.3VA
GND
5V
R24
GND
GND
100ꢃ
3.3VA
GND
3.3VA
GND
5V
DA6
E7
E11
DA5
DAOR
R3
100ꢃ
GND
GND
GND
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
E14
C12
0.1ꢄF
GND
V
60
1
2
3
4
5
6
7
AGND
VDD
GND
DA4
DA3
DA2
GND
GND
DD
C27
0.1ꢄF
AGND
59
58
57
56
DGND
V
D
GND
5V
CC
A4
C28
0.1ꢄF
REF
D
OUT
E6
E3 E1
A3
EXT
REF
REF
D
IN
A2
DNC
D
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
A1
DA1
DA0
V
5V
CC
D
A0
C26
0.1ꢄF
AGND
AGND
8
9
V
VDD
C21
0.1ꢄF
DD
GND
GND
DGND
DCO
GND
T1
6
1
2
3
A
10
11
GND
C7
0.1ꢄF
IN
DCOT
DCOC
GND
AD9410
U3
R27
GND
5
4
A
J8
IN
50ꢃ
DCO
12 AGND
GND GND
1:1
AIN
DGND
C24
AGND
13
14
15
R23
50ꢃ
C25
0.1ꢄF
V
VDD
C22
0.1ꢄF
DD
0.1ꢄF
GND
V
GND
CC
DBOR
DB9
DB8
DB7
DB6
DB5
OR
D
B
GND
GND
V
5V
CC
B9
B8
B7
B6
B5
GND
GND
16 AGND
AGND
D
D
D
D
V
17
18 ENCODE
ENCT
ENCC
GND
19
20
ENCODE
VDD
AGND
DD
C18
0.1ꢄF
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
GND
J9X
GND
3.3VA
DB0
3.3VA
GND
GND
GND
C15
DB1
DB2
R26
50ꢃ
DB3
0.1ꢄF
DB4
GND
C19
J10X
GND
0.1ꢄF
VDD
GND
R25X
50ꢃ
3.3VA
GND
GND
C16
0.1ꢄF
3.3VA
Figure 13a. PCB Schematic
REV. 0
–15–
AD9410
Figure 13b. PCB Schematic (Continued)
–16–
REV. 0
AD9410
J3
GND
C3
0.1ꢄF
R1
50ꢃ
GND
VDAC
R10
2kꢃ
J4
GND
GND
R12
50ꢃ
C23
0.1ꢄF
GND
R5
392ꢃ
GND
GND
VDAC
VDAC
C33
VDAC
E2
1ꢄF
E4
GND
E5
R13
392ꢃ
C20
0.1ꢄF
E31
VDAC
GND GND
E29
GND
E30
GND
48 47 46 45 44 43 42 41
38 37
40 39
E32
E33
VDAC
GND
1
2
36
E34
35
34
33
32
31
30
29
28
27
26
25
DCOCA
3
DCOTA
GND
4
5
DN0
VDAC
C13
0.1ꢄF
6
DN1
DN2
DN3
E35
DM9
DM8
AD9751
U2
GND
7
8
9
DM7
DM6
DN4
DN5
DN6
DN7
10
11
12
DM5
DM4
13 14
23 24
15 16 17 18 19 20 21 22
DM3
DM1
DM2 DM0
DN8
GND
DN9
C17
0.1ꢄF
GND
VDAC
Figure 13c. PCB Schematic (Continued)
TROUBLESHOOTING
If the board does not seem to be working correctly, try the
following:
• Try running encode clock and analog input at low speeds
(10 MSPS/1 MHz) and monitor latch outputs, DAC outputs,
and ADC outputs for toggling.
•
•
Verify power at IC pins.
The AD9410 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or
fitness for a particular purpose.
Check that all jumpers are in the correct position for the
desired mode of operation.
•
Verify VREF is at 2.5 V.
REV. 0
–17–
AD9410
EVALUATION BOARD LAYOUT
Figure 14. Top Silkscreen
Figure 17. Bottom Components and Routing
Figure 15. Split Power Plane
Figure 18. Bottom Silkscreen
Figure 19. Top Components and Routing
Figure 16. Ground Plane
–18–
REV. 0
AD9410
AD9410 Evaluation Board Bill of Material
Quantity
Reference Description
Device
Package
Value
5
29
1
31
6
C1–C5
Capacitor
TAJD
603
1206
10 µF
0.1 µF
1 µF
C6–C30, C32, C37, C39, C40
C33
E1–E7, E10–E12, E14, E16–E35
J1, J3, J4, J8, J9X, J10X
P1, P4, P5
Capacitor
Capacitor
Ehole
SMB
3
4-Pin Power
Connector
40-Pin Header
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
RPACK
25.531.3425.0
25.602.5453.0
Wieland
2
7
8
1
1
2
1
2
2
5
8
P2, P3
R1, R8, R12, R23*, R25X, R26, R27
R2, R3, R4, R6, R24, R37, R42, R43
R13
R7
R9, R18
R10
R11, R15
R14, R19
1206
1206
1206
1206
1206
1206
1206
1206
1206
766163220G
22 Ω
ADT1-1WT
SOIC8
LQFP48
LQFP80
SOIC24
SOIC14
50 Ω
100 Ω
392 Ω
100 Ω
24 kΩ
2 kΩ
330 Ω
8.2 kΩ
0 Ω
R5, R16, R17, R44, R45
R28, R29, R32, R34, R36, R38–R40
CTS
1
1
1
1
2
1
T1
U1
U2
U3
U4, U5
U9
Transformer (1:1)
MC10EL16
AD9751
AD9410
74LCX821
74AC86
Minicircuits
*Optional R23 not placed on board (50 Ω termination resistor).
REV. 0
–19–
AD9410
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead PowerQuad 2 (LQFP_ED)
(SQ-80)
0.630 (16.00) SQ
0.063 (1.60)
MAX
0.551 (14.00) SQ
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
80
80
61
61
60
60
1
1
0.120 (3.04) ꢆ 45ꢀC CHAMFER
4 PLACES
SEATING
PLANE
PIN 1
BOTTOM
VIEW
0.413 (10.50)
0.394 (10.00) REF
0.374 (9.50)
TOP VIEW
(PINS DOWN)
NICKEL PLATED
XX
COPLANARITY
0.004 (0.10)
MAX
20
41
20
41
21
40
40
21
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
0.413 (10.50)
0.394 (10.00) REF
0.374 (9.50)
0.006 (0.15)
0.002 (0.05)
CONTROLLING DIMENSION IN MILLIMETERS.
CENTER FIGURES ARE TYPICAL UNLESS
OTHERWISE NOTED.
0.008 (0.20)
0.004 (0.09)
0.015 (0.38)
0.013 (0.32)
0.009 (0.22)
7ꢀ
0ꢀ
0.0256 (0.65)
BSC
NOTE
The AD9410 has a conductive heat slug to help dissipate heat
and ensure reliable operation of the device over the full indus-
trial temperature range. The slug is exposed on the bottom of
the package. It is recommended that no PCB traces or vias be
located under the package that could come in contact with the
conductive slug. Attaching the slug to a ground plane while not
required in most applications will reduce the junction tempera-
ture of the device which may be beneficial in high temperature
environments.
–20–
REV. 0
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