AD9445-BB-LVDS/PCB [ADI]
14-Bit, 105/125 MSPS, IF Sampling ADC;
| 型号： | AD9445-BB-LVDS/PCB |
| 厂家： | 
ADI |
| 描述： | 14-Bit, 105/125 MSPS, IF Sampling ADC |
| 文件： | 总41页 (文件大小：797K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445
FUNCTIONAL BLOCK DIAGRAM
FEATURES
125 MSPS guaranteed sampling rate (AD9445BSV-125)
78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p)
74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p)
77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p)
74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p)
73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p)
102 dBFS 2-tone SFDR with 30 MHz and 31 MHz
92 dBFS 2-tone SFDR with 170 MHz and 171 MHz
60 fsec rms jitter
AGND AVDD1 AVDD2 DRGND DRVDD
RF ENABLE
DFS
AD9445
DCS MODE
OUTPUT MODE
OR
BUFFER
14
VIN+
VIN–
2
PIPELINE
ADC
CMOS
OR
LVDS
OUTPUT
STAGING
T/H
28
D13 TO D0
DCO
2
CLOCK
CLK+
CLK–
AND TIMING
MANAGEMENT
REF
Excellent linearity
DNL = 0.25 LSB typical
VREF SENSE REFT REFB
INL = 0.8 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
Figure 1.
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
high IF sampling mode, and output data mode.
3.3 V and 5 V supply operation
The AD9445 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP/EP) specified over the
industrial temperature range −40°C to +85°C.
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
PRODUCT HIGHLIGHTS
1. High performance: outstanding SFDR performance for IF
sampling applications such as multicarrier, multimode 3G,
and 4G cellular base station receivers.
Radar
Infrared imaging
Medical imaging
Communications instrumentation
2. Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
GENERAL DESCRIPTION
The AD9445 is a 14-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip IF sampling track-and-hold
circuit. It is optimized for performance, small size, and ease of
use. The product operates at up to a 125 MSPS conversion rate
and is designed for multicarrier, multimode receivers, such as
those found in cellular infrastructure equipment.
3. Packaged in a Pb-free, 100-lead TQFP/EP package.
4. Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is
beyond the selected input range.
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
6. RF enable pin allows users to configure the device for
optimum SFDR when sampling frequencies above 210 MHz
(AD9445-125) or 240 MHz (AD9445-105).
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD9445* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
TOOLS AND SIMULATIONS
• Visual Analog
• AD9445 IBIS Models
DOCUMENTATION
REFERENCE DESIGNS
• CN0046
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-1204: Using the ADL5562 Differential Amplifier to
Drive Wide Bandwidth ADCs
REFERENCE MATERIALS
• AN-1408: Using the AD8376 VGA to Drive Wide
Bandwidth ADCs for High IF AC-Coupled Applications
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
DESIGN RESOURCES
• AD9445 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
DISCUSSIONS
• AN-741: Little Known Characteristics of Phase Noise
View all AD9445 EngineerZone Discussions.
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
SAMPLE AND BUY
Visit the product page to see pricing options.
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-835: Understanding High Speed ADC Testing and
Evaluation
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
Data Sheet
• AD9445: 14-Bit, 105/125 MSPS, IF Sampling ADC Data
Sheet
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AD9445
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology.......................................................................................9
Pin Configurations and Function Descriptions......................... 10
Equivalent Circuits......................................................................... 15
Typical Performance Characteristics ........................................... 16
Theory of Operation ...................................................................... 24
Analog Input and Reference Overview................................... 24
Clock Input Considerations...................................................... 26
Power Considerations................................................................ 27
Digital Outputs ........................................................................... 27
Timing ......................................................................................... 27
Operational Mode Selection..................................................... 28
Evaluation Board ............................................................................ 29
Outline Dimensions....................................................................... 37
Ordering Guide .......................................................................... 37
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9445
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.
Table 1.
AD9445BSVZ-105
AD9445BSVZ-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
ACCURACY
Full
14
14
Bits
No Missing Codes
Offset Error
Full
Full
25°C
Full
25°C
Full
Guaranteed
3
Guaranteed
3
−7
+7
−7
+7
mV
mV
% FSR
% FSR
LSB
Gain Error
−3
−2
−0.6
5
+3
+2
+0.65
−3
−2
−0.6
5
+3
+2
+0.65
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
0.25
0.65
0.25
0.ꢀ
25°C
Full
LSB
LSB
−1.6
0.9
+1.6
1.1
−2
+2
VOLTAGE REFERENCE
Output Voltage VREF = 1.0 V
Load Regulation @ 1.0 mA
Reference Input Current (External VREF = 1.6 V)
INPUT REFERRED NOISE
ANALOG INPUT
Full
Full
Full
25°C
1.0
2
0.9
1.0
2
1.1
V
mV
μA
1.0
1.0
LSB rms
Input Span
VREF = 1.6 V
VREF = 1.0 V
Full
Full
Full
Full
Full
Full
3.2
2.0
3.5
3.2
2.0
3.5
V p-p
V p-p
V
V
kΩ
Internal Input Common-Mode Voltage
External Input Common-Mode Voltage
Input Resistance2
Input Capacitance2
POWER SUPPLIES
Supply Voltage
3.1
3.9
3.1
3.9
1
6
1
6
pF
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current1
Full
Full
Full
Full
3.14
4.75
3.0
3.3
5.0
3.46
5.25
3.6
3.14
4.75
3.0
3.3
5.0
3.46
5.25
3.6
V
V
V
V
3.0
3.3
3.6
3.0
3.3
3.6
AVDD1
Full
Full
Full
Full
335
169
63
364
196
7ꢀ
3ꢀ4
172
63
424
199
7ꢀ
mA
mA
mA
mA
AVDD21, 3
IDRVDD1—LVDS Outputs
IDRVDD1—CMOS Outputs
PSRR
14
14
Offset
Gain
Full
Full
1
0.2
1
0.2
mV/V
%/V
POWER CONSUMPTION
LVDS Outputs
CMOS Outputs (DC Input)
Full
Full
2.2
2.0
2.4
2.3
2.1
2.6
W
W
1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3 For RF ENABLE = AVDD1, IAVDD2 increases by ~30 mA, which increases power dissipation.
Rev. 0 | Page 3 of 40
AD9445
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 2.0 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, RF ENABLE = ground, unless otherwise noted.
Table 2.
AD9445BSVZ-105
AD9445BSVZ-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz
fIN = 30 MHz
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
74.3
74.3
74.1
73.ꢀ
dB
dB
dB
dB
dB
dB
dB
dB
dB
73.3
73
72.9
72.2
72.2
71.4
72.9
72.5
72.3
72
71.4
71.3
fIN = 170 MHz
fIN = 225 MHz1
73.6
73
73.2
72.9
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
72.1
71
70.5
72
71
70.5
fIN = 10 MHz (3.2 V p-p Input)
fIN = 30 MHz (3.2 V p-p Input)
fIN = 170 MHz (3.2 V p-p Input)
fIN = 225 MHz (3.2 V p-p Input)1
fIN = 300 MHz (3.2 V p-p Input)2
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz
25°C
25°C
25°C
25°C
25°C
77.6
77.5
76
75.3
73.7
77.3
77.3
76
75.4
73.5
dB
dB
dB
dB
dB
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
74.2
74.2
73.9
73.7
dB
dB
dB
dB
dB
dB
dB
dB
dB
fIN = 30 MHz
73.2
72.ꢀ
72.3
71.4
71.3
70.2
72.ꢀ
72.3
72.4
71.9
70.7
69.3
fIN = 170 MHz
fIN = 225 MHz1
73.3
72.5
73.0
72.5
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
71.7
67.2
65.2
71.5
66.3
64.3
fIN = 10 MHz (3.2 V p-p Input)
fIN = 30 MHz (3.2 V p-p Input)
fIN = 170 MHz (3.2 V p-p Input)
fIN = 225 MHz (3.2 V p-p Input)1
fIN = 300 MHz (3.2 V p-p Input)2
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
25°C
25°C
25°C
25°C
25°C
77.4
77.3
75.7
75.1
72.5
76.9
76.ꢀ
75.4
75.2
71.ꢀ
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
25°C
25°C
12.2
12.2
12.1
12.0
11.ꢀ
11.7
11.6
12.2
12.1
12.0
12.0
11.ꢀ
11.7
11.6
Bits
Bits
Bits
Bits
Bits
Bits
Bits
fIN = 30 MHz
fIN = 170 MHz
fIN = 225 MHz1
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
Rev. 0 | Page 4 of 40
AD9445
AD9445BSVZ-105
AD9445BSVZ-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE
(SFDR, Second or Third Harmonic)
fIN = 10 MHz
fIN = 30 MHz
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
95
92
95
94
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
ꢀ4
ꢀ3
ꢀ2
76
75
76
ꢀ5
ꢀ2
ꢀ0
ꢀ3
75
75
fIN = 170 MHz
fIN = 225 MHz1
94
ꢀ7
91
ꢀꢀ
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
ꢀ7
75
70
ꢀ7
73
69
fIN = 10 MHz (3.2 V p-p Input)
fIN = 30 MHz (3.2 V p-p Input)
fIN = 170 MHz (3.2 V p-p Input)
fIN = 225 MHz (3.2 V p-p Input)1
fIN = 300 MHz (3.2 V p-p Input)2
25°C
25°C
25°C
25°C
25°C
92
ꢀꢀ
ꢀ6
ꢀ1
77
92
91
ꢀ6
ꢀ0
76
dBc
dBc
dBc
dBc
dBc
WORST SPUR EXCLUDING SECOND OR
THIRD HARMONICS
fIN = 10 MHz
fIN = 30 MHz
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
−97
−99
−97
−9ꢀ
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−90
−90
−92
−ꢀꢀ
−ꢀ6
−90
−ꢀ9
−ꢀꢀ
−ꢀ5
−ꢀ4
−ꢀ0
−ꢀ2
fIN = 170 MHz
fIN = 225 MHz1
−99
−94
−93
−94
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
−97
−93
−ꢀ2
−92
−93
−ꢀ7
fIN = 10 MHz (3.2 V p-p Input)
fIN = 30 MHz (3.2 V p-p Input)
fIN = 170 MHz (3.2 V p-p Input)
fIN = 225 MHz (3.2 V p-p Input)1
fIN = 300 MHz (3.2 V p-p Input)2
TWO-TONE SFDR
25°C
25°C
25°C
25°C
25°C
−97
−97
−97
−95
−93
−95
−95
−95
−94
−91
dBc
dBc
dBc
dBc
dBc
fIN = 30.3 MHz @ −7 dBFS,
31.3 MHz @ −7 dBFS
fIN = 170.3 MHz @ −7 dBFS,
171.3 MHz @ −7 dBFS
25°C
25°C
Full
102
92
102
91
dBFS
dBFS
MHz
ANALOG BANDWIDTH
615
615
1 RF ENABLE = low (AGND ) for AD9445-105; RF ENABLE = high (AVDD1) for AD9445-125.
2 RF ENABLE = high (AVDD1).
Rev. 0 | Page 5 of 40
AD9445
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
AD9445BSVZ-105
AD9445BSVZ-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D13, OTR)1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
Full
Full
Full
Full
Full
2.0
2.0
V
V
μA
μA
pF
0.ꢀ
200
+10
0.ꢀ
200
+10
−10
3.25
−10
3.25
2
2
Full
Full
V
V
0.2
0.2
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D13, OTR)
VOD Differential Output Voltage2
VOS Output Offset Voltage
Full
Full
247
1.125
545
1.375
247
1.125
545
1.375
mV
V
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
Full
Full
Full
Full
0.2
1.3
1.1
0.2
1.3
1.1
V
V
kΩ
pF
1.5
1.4
2
1.6
1.7
1.5
1.4
2
1.6
1.7
1 Output voltage levels measured with 5 pF load on each output.
2 LVDS RTERM = 100 Ω.
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
AD9445BSVZ-105
AD9445BSVZ-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
Full
Full
Full
Full
Full
105
125
MSPS
MSPS
ns
ns
ns
10
10
9.5
3.ꢀ
3.ꢀ
ꢀ.0
3.2
3.2
CLK Pulse Width High1 (tCLKH
)
CLK Pulse Width Low1 (tCLKL
)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD)2 (Dx, DCO+)
Output Propagation Delay—LVDS (tPD)3 (Dx+), (tCPD)3 (DCO+)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Full
Full
Full
Full
Full
3.35
3.6
13
3.35
3.6
13
ns
ns
Cycles
ns
fsec
rms
2.1
4.ꢀ
2.3
4.ꢀ
60
60
1 With duty cycle stabilizer (DCS) enabled.
2 Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3 LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
Rev. 0 | Page 6 of 40
AD9445
TIMING DIAGRAMS
N – 1
N
N + 1
A
IN
tCLKL
tCLKH
1/fS
CLK+
CLK–
tPD
N
N + 1
N – 12
13 CLOCK CYCLES
N – 13
DATA OUT
DCO+
DCO–
tCPD
Figure 2. LVDS Mode Timing Diagram
N
N – 1
N + 1
VIN
N + 2
tCLKL
tCLKH
CLK–
CLK+
tPD
13 CLOCK CYCLES
N – 13
N – 12
N – 1
N
DX
DCO+
DCO–
Figure 3. CMOS Timing Diagram
Rev. 0 | Page 7 of 40
AD9445
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
With
Respect
To
Parameter
ELECTRICAL
AVDD1
AVDD2
DRVDD
AGND
AVDD1
AVDD2
AVDD2
D0 to D13
CLK+/CLK−
OUTPUT MODE, DCS
MODE, DFS, SFDR,
RF ENABLE
VIN+, VIN−
VREF
SENSE
REFT, REFB
ENVIRONMENTAL
Storage Temperature
Range
Operating Temperature
Range
Lead Temperature
(Soldering 10 sec)
Rating
AGND
AGND
DGND
DGND
DRVDD
DRVDD
AVDD1
DGND
AGND
AGND
−0.3 V to +4 V
−0.3 V to +6 V
−0.3 V to +4 V
−0.3 V to +0.3 V
−4 V to +4 V
−4 V to +6 V
−4 V to +6 V
–0.3 V to DRVDD + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
THERMAL RESISTANCE
The heat sink of the AD9445 package must be soldered to ground.
Table 6.
Package Type
θJA
θJB
θJC
Unit
100-lead TQFP/EP
19.ꢀ
ꢀ.3
2
°C/W
Typical θJA = 19.8°C/W (heat sink soldered) for multilayer
board in still air.
AGND
AGND
AGND
AGND
–0.3 V to AVDD2 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board
in still air.
Typical θJC = 2°C/W (junction to exposed heat sink) represents
the thermal resistance through heat sink path.
–65°C to +125°C
–40°C to +ꢀ5°C
300°C
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θJA. It is required that the exposed heat sink be soldered to
the ground plane.
Junction Temperature
150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page ꢀ of 40
AD9445
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Aperture Delay (tA)
Offset Error
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
The major carry transition should occur for an analog value of
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Power-Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at the maximum
limit.
Effective Number of Bits (ENOB)
Signal-to-Noise and Distortion (SINAD)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
(
SINAD −1.76
)
Signal-to-Noise Ratio (SNR)
ENOB =
6.02
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Gain Error
The first code transition should occur at an analog value of
½ LSB above negative full scale. The last transition should occur
at an analog value of 1½ LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may be a harmonic. SFDR can be reported in dBc (that is, degrades
as signal level is lowered) or dBFS (always related back to converter
full scale).
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX
.
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Rev. 0 | Page 9 of 40
AD9445
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DCS MODE
DNC
DRGND
D8+
PIN 1
2
3
OUTPUT MODE
DFS
D8–
4
D7+
5
LVDS_BIAS
AVDD1
SENSE
VREF
D7–
6
D6+
7
D6–
8
DCO+
DCO–
D5+
AD9445
LVDS MODE
TOP VIEW
9
AGND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
REFT
(Not to Scale)
REFB
D5–
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AGND
DRVDD
DRGND
D4+
D4–
D3+
D3–
D2+
D2–
D1+
D1–
VIN+
D0+
VIN–
D0– (LSB)
DNC
DNC
AGND
AVDD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNC = DO NOT CONNECT
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
Rev. 0 | Page 10 of 40
AD9445
Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode
Pin No.
Mnemonic
Description
1
DCS MODE
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to
enable DCS (recommended); DCS = high (AVDD1) to disable DCS.
2, 49 to 52
3
DNC
OUTPUT MODE
Do Not Connect. These pins should float.
CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
4
DFS
Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.
5
LVDS_BIAS
AVDD1
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
3.3 V ( 5%) Analog Supply.
6, 1ꢀ to 20, 32 to 34, 36, 3ꢀ,
43 to 45, 92 to 97
7
SENSE
VREF
Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to
AVDD1 for external reference.
1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 μF and 10 μF capacitors.
ꢀ
9, 21, 24, 39, 42, 46, 91, 9ꢀ, 99, AGND
Exposed Heat Sink
Analog Ground. The exposed heat sink on the bottom of the package must be
connected to AGND.
10
REFT
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB
(Pin 14) with 0.1 μF and 10 μF capacitors.
11
REFB
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 13) with 0.1 μF and 10 μF capacitors.
12 to 17, 25 to 31, 35, 37
22
23
40
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
D0− (LSB)
D0+
D1−
D1+
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
DCO−
DCO+
D6−
D6+
D7−
D7+
Dꢀ−
Dꢀ+
D9−
D9+
D10−
D10+
D11−
D11+
5.0 V Analog Supply ( 5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
D0 Complement Output Bit (LVDS Levels).
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
Dꢀ Complement Output Bit.
Dꢀ True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
41
47, 63, 75, ꢀ7
4ꢀ, 64, 76, ꢀꢀ
53
54
55
56
57
5ꢀ
59
60
61
62
65
66
67
6ꢀ
69
70
71
72
73
74
77
7ꢀ
79
ꢀ0
ꢀ1
ꢀ2
Rev. 0 | Page 11 of 40
AD9445
Pin No.
ꢀ3
ꢀ4
Mnemonic
D12−
D12+
Description
D12 Complement Output Bit.
D12 True Output Bit.
ꢀ5
ꢀ6
ꢀ9
90
D13−
D13+ (MSB)
OR−
D13 Complement Output Bit.
D13 True Output Bit.
Out-of-Range Complement Output Bit.
Out-of-Range True Output Bit.
OR+
100
RF ENABLE
RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of
the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies <210 MHz for 125 MSPS
speed grade and <230 MHz for the 105 MSPS speed grade. For applications with analog
inputs >225 MHz for the 125 MSPS speed grade and >230 MHz for the 105 MSPS speed
grade, this pin should be connected to AVDD1 for optimum SFDR performance. Power
dissipation from AVDD2 increases by 150 mW to 200 mW.
Rev. 0 | Page 12 of 40
AD9445
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DCS MODE
DNC
DRGND
D2
PIN 1
2
3
OUTPUT MODE
DFS
D1
4
D0 (LSB)
DNC
5
LVDS_BIAS
AVDD1
SENSE
VREF
6
DNC
7
DNC
8
DCO+
DCO–
DNC
AD9445
9
AGND
CMOS MODE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
REFT
TOP VIEW
(Not to Scale)
REFB
DNC
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD1
AVDD1
AVDD1
AGND
DRVDD
DRGND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
VIN+
DNC
VIN–
DNC
AGND
DNC
AVDD2
DNC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNC = DO NOT CONNECT
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
Rev. 0 | Page 13 of 40
AD9445
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode
Pin No.
Mnemonic Description
1
DCS MODE
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable
DCS (recommended); DCS = high (AVDD1) to disable DCS.
Do Not Connect. These pins should float.
2, 49 to 62, 65 to 66, 69 to 71 DNC
3
4
5
OUTPUT
MODE
DFS
CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
3.3 V ( 5%) Analog Supply.
LVDS_BIAS
AVDD1
6, 1ꢀ to 20, 32 to 34, 36, 3ꢀ,
43 to 45, 92 to 97
7
SENSE
VREF
AGND
REFT
Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1 for
external reference.
1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 μF and 10 μF capacitors.
Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB
(Pin 14) with 0.1 μF and 10 μF capacitors.
ꢀ
9, 21, 24, 39, 42, 46, 91, 9ꢀ,
99, Exposed Heat Sink
10
11
REFB
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 13) with 0.1 μF and 10 μF capacitors.
12 to 17, 25 to 31, 35, 37
22
23
40
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
DCO−
DCO+
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
Dꢀ
D9
5.0 V Analog Supply ( 5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Data Clock Output—Complement.
Data Clock Output—True.
D0 True Output Bit (CMOS levels).
D1 True Output Bit.
D2 True Output Bit.
D3 True Output Bit.
D4 True Output Bit.
D5 True Output Bit.
D6 True Output Bit.
D7 True Output Bit.
Dꢀ True Output Bit.
D9 True Output Bit.
41
47, 63, 75, ꢀ7
4ꢀ, 64, 76, ꢀꢀ
67
6ꢀ
72
73
74
77
7ꢀ
79
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
ꢀ9
90
100
D10
D11
D12
D13 (MSB)
OR
D10 True Output Bit.
D11 True Output Bit.
D12 True Output Bit.
D13 True Output Bit.
Out-of-Range True Output Bit.
RF ENABLE
RF ENABLE CMOS-compatible Control Pin. Optimizes the configuration of the analog front end.
Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input
frequencies <210 MHz for 125 MSPS speed grade and <230 MHz for the 105 MSPS speed grade.
For applications with analog inputs >225 MHz for the 125 MSPS speed grade and >230 MHz
for the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR.
Power dissipation from AVDD2 increases by 150 mW to 200 mW.
Rev. 0 | Page 14 of 40
AD9445
EQUIVALENT CIRCUITS
AVDD2
VIN+
6pF
1k
Ω
Ω
DRVDD
X1
T/H
3.5V
1k
DX
AVDD2
VIN–
6pF
Figure 6. Equivalent Analog Input Circuit
Figure 9. Equivalent CMOS Digital Output Circuit
VDD
DRVDD DRVDD
RF ENABLE, DCS
MODE, OUTPUT
MODE, DFS
K
1.2V
30kΩ
LVDS_BIAS
3.74kΩ
I
LVDSOUT
Figure 10. Equivalent Digital Input Circuit,
DFS, DCS MODE, OUTPUT MODE
Figure 7. Equivalent LVDS_BIAS Circuit
AVDD2
DRVDD
3kΩ
3kΩ
CLK+
CLK–
V
V
DX–
V
DX+
V
2.5k
Ω
2.5k
Ω
Figure 11. Equivalent Sample Clock Input Circuit
Figure 8. Equivalent LVDS Digital Output Circuit
Rev. 0 | Page 15 of 40
AD9445
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25°C, 2.0 V p-p differential
input, AIN = −1.0 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted.
0
–10
0
–10
125MSPS
125MSPS
30.3MHz @ –1.0dBFS
SNR = 73.4dB
225.3MHz @ –1.0dBFS
SNR = 72.9dB
–20
–20
ENOB = 12.1BITS
SFDR = 94dBc
ENOB = 12.1BITS
SFDR = 88dBc
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0
15.625
31.250
46.875
62.500
0
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. AD9445-125 64k Point Single-Tone FFT/125 MSPS/30.3 MHz
Figure 15. AD9445-125 64k Point Single-Tone FFT/125 MSPS/225.3 MHz
0
0
125MSPS
125MSPS
–10
–10
100.3MHz @ –1.0dBFS
300.3MHz @ –1.0dBFS
SNR = 0dB
SNR = 72.0dB
–20
–20
ENOB = 12.1BITS
ENOB = 11.8BITS
SFDR = 96dBc
SFDR = 87dBc
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0
15.625
31.250
FREQUENCY (MHz)
46.875
62.500
0
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
Figure 13. AD9445-125 64k Point Single-Tone FFT/125 MSPS/100.3 MHz
Figure 16. AD9445-125 64k Point Single-Tone FFT/125 MSPS/300.3 MHz
0
0
125MSPS
125MSPS
–10
–10
170.3MHz @ –1.0dBFS
450.3MHz @ –1.0dBFS
SNR = 73.2dB
SNR = 70.5dB
–20
–20
ENOB = 12.0BITS
ENOB = 11.6BITS
SFDR = 91dBc
SFDR = 69dBc
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0
15.625
31.250
FREQUENCY (MHz)
46.875
62.500
0
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
Figure 14. AD9445-125 64k Point Single-Tone FFT/125 MSPS/170.3 MHz
Figure 17. AD9445-125 64k Point Single-Tone FFT/125 MSPS/450.3 MHz
Rev. 0 | Page 16 of 40
AD9445
100
95
100
95
SFDR +85°C
SFDR +85°C
SFDR –40°C
SFDR +25°C
SFDR –40°C
90
90
SFDR +25°C
85
80
75
70
65
85
80
75
70
65
SNR +25°C
SNR –40°C
SNR –40°C
SNR +25°C
SNR +85°C
SNR +85°C
60
55
60
55
0
50
100
150
200
250
300
350
400
450
0
50
100
150
200
250
300
350
400
450
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 18. AD9445-125 SNR/SFDR vs. Analog Input Frequency,
125 MSPS, 2.0 V p-p Input Range
Figure 21. AD9445-125 SNR/SFDR vs. Analog Input Frequency,
125 MSPS, 3.2 V p-p Input Range
100
105
SFDR +25°C
SFDR +85°C
95
90
85
125M SFDR dBc
100
95
90
85
80
75
70
105M SFDR dBc
SFDR –40°C
SNR +25°C
SNR –40°C
80
75
70
65
60
55
SNR +85°C
125M SNR dB
105M SNR dB
100 120
SAMPLE RATE (MSPS)
0
10
20
30
40
50
60
70
80
90
100
0
20
40
60
80
140
ANALOG INPUT FREQUENCY (MHz)
Figure 19. AD9445-125 SNR/SFDR vs. Analog Input Frequency,
3.2 V p-p Input Range, 125 MSPS, CMOS Output Mode
Figure 22. AD9445 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz
120
120
SFDR dBFS
SFDR dBFS
100
80
100
80
SNR dBFS
SNR dBFS
60
60
40
40
SFDR dBc
SFDR dBc
20
20
SNR dB
SNR dB
0
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
ANALOG INPUT AMPLITUDE (dB)
ANALOG INPUT AMPLITUDE (dB)
Figure 20. AD9445-125 SNR/SFDR vs. Analog Input Level,
125 MSPS/225.3 MHz
Figure 23. AD9445-125 SNR/SFDR vs. Analog Input Level,
125 MSPS/225.3 MHz, CMOS Output Mode
Rev. 0 | Page 17 of 40
AD9445
0
0
–10
105MSPS
105MSPS
–10
–20
30.3MHz @ –1.0dBFS
SNR = 74.3dB
225.3MHz @ –1.0dBFS
SNR = 73.0dB
–20
ENOB = 12.2BITS
SFDR = 92dBc
ENOB = 12.0BITS
SFDR = 87dBc
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0
13.125
26.250
FREQUENCY (MHz)
39.375
52.500
0
13.125
26.250
39.375
52.500
FREQUENCY (MHz)
Figure 24. AD9445-105 64k Point Single-Tone FFT/105 MSPS/30.3 MHz
Figure 27. AD9445-105 64k Point Single-Tone FFT/105 MSPS/225.3 MHz
0
0
105MSPS
105MSPS
–10
–10
100.3MHz @ –1.0dBFS
300.3MHz @ –1.0dBFS
SNR = 73.5dB
SNR = 72.1dB
–20
–20
ENOB = 11.8BITS
ENOB = 11.8BITS
SFDR = 93dBc
SFDR = 87dBc
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0
13.125
26.250
FREQUENCY (MHz)
39.375
52.500
0
13.125
26.250
FREQUENCY (MHz)
39.375
52.500
Figure 25. AD9445-105 64k Point Single-Tone FFT/105 MSPS/100.3 MHz
Figure 28. AD9445-105 64k Point Single-Tone FFT/105 MSPS/300.3 MHz
0
0
105MSPS
105MSPS
–10
–10
170.3MHz @ –1.0dBFS
450.3MHz @ –1.0dBFS
SNR = 73.6dB
SNR = 70.5dB
–20
–20
ENOB = 12.1BITS
ENOB = 11.6BITS
SFDR = 94dBc
SFDR = 70dBc
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–100
–110
–120
–130
0
13.125
26.250
39.375
52.500
0
13.125
26.250
FREQUENCY (MHz)
39.375
52.500
FREQUENCY (MHz)
Figure 26. AD9445-105 64k Point Single-Tone FFT/105 MSPS/170.3 MHz
Figure 29. AD9445-105 64k Point Single-Tone FFT/105 MSPS/450.3 MHz
Rev. 0 | Page 1ꢀ of 40
AD9445
100
95
100
95
SFDR +25°C
SFDR –40°C
SFDR +25°C
SFDR –40°C
90
90
SFDR +85°C
SFDR +85°C
85
80
75
70
65
85
80
75
70
65
SNR –40°C
SNR –40°C
SNR +25°C
SNR +85°C
SNR +85°C
SNR +25°C
60
55
60
55
0
50
100
150
200
250
300
350
400
450
0
50
100
150
200
250
300
350
400
450
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 30. AD9445-105 SNR/SFDR vs. Analog Input Frequency,
105 MSPS, 2.0 V p-p
Figure 33. AD9445-105 SNR/SFDR vs. Analog Input Frequency,
105 MSPS, 3.2 V p-p
100
100
SFDR +25°C
SFDR +85°C
SFDR –40°C
95
90
85
80
75
70
65
60
SFDR dBc
95
90
85
80
75
70
65
SNR –40°C
SNR +25°C
SNR dB
SNR +85°C
60
55
2.7
2.9
3.1
3.3
3.5
3.7
3.9
4.1
4.3
0
20
40
60
80
100
120
140
160
180
ANALOG INPUT COMMON-MODE VOLTAGE
ANALOG INPUT FREQUENCY (MHz)
Figure 31. AD9445-105 SNR/SFDR vs. Analog Input Frequency,
3.2 V p-p Input Range, 105 MSPS, CMOS Output Mode
Figure 34. AD9445-105 SNR/SFDR vs. Analog Input Common Mode,
105 MSPS/10.3 MHz
120
120
SFDR dBFS
SFDR dBFS
100
80
100
80
SNR dBFS
SNR dBFS
60
60
SFDR dBc
40
20
0
40
SFDR dBc
20
SNR dB
SNR dB
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
ANALOG INPUT AMPLITUDE (dB)
ANALOG INPUT AMPLITUDE (dB)
Figure 32. AD9445-105 SNR/SFDR vs. Analog Input Level,
105 MSPS/225.3 MHz
Figure 35. AD9445-105 SNR/SFDR vs. Analog Input Level,
105 MSPS/225.3 MHz, CMOS Output Mode
Rev. 0 | Page 19 of 40
AD9445
0
–10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
125MSPS
30.3MHz @ –7.0dBFS
31.3MHz @ –7.0dBFS
SFDR = 102dBFS
–20
–30
SFDR dBc
–40
–50
WORST IMD3 dBc
–60
–70
–80
–90
–100
–110
–120
–130
SFDR dBFS
–110
–120
WORST IMD3 dBFS
–140
0
13.625
27.250
40.875
54.500
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
FREQUENCY (MHz)
FUNDAMENTAL LEVEL (dB)
Figure 36. AD9445-125 64k Point Two-Tone FFT/
125 MSPS/30.3 MHz, 31.3 MHz
Figure 39. AD9445-125 Two-Tone SFDR vs. Analog Input Level
125 MSPS/170.3 MHz, 171.3 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
105MSPS
–10
30.3MHz @ –7.0dBFS
31.3MHz @ –7.0dBFS
SFDR = 102dBFS
–20
–30
SFDR dBc
–40
–50
–60
WORST IMD3 dBc
–70
–80
–90
–100
–110
–120
–130
–140
SFDR dBFS
–110
–120
WORST IMD3 dBFS
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
0
13.125
26.250
39.375
52.500
FUNDAMENTAL LEVEL (dB)
FREQUENCY (MHz)
Figure 37. AD9445-125 Two-Tone SFDR vs. Analog Input Level
125 MSPS/30.3 MHz, 31.3 MHz
Figure 40. AD9445-105 64k Point Two-Tone FFT/105 MSPS/30.3 MHz, 31.3 MHz
0
0
–10
–20
125MSPS
–10
170.3MHz @ –7.0dBFS
171.3MHz @ –7.0dBFS
SFDR = 91dBFS
–20
–30
–30
–40
SFDR dBc
–40
–50
–50
–60
WORST IMD3 dBc
–60
–70
–80
–70
–80
–90
–90
–100
–110
–120
–130
–140
SFDR dBFS
–100
–110
–120
WORST IMD3 dBFS
0
13.625
27.250
40.875
54.500
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
FREQUENCY (MHz)
FUNDAMENTAL LEVEL (dB)
Figure 38. AD9445-125 64k Point Two-Tone FFT/
125 MSPS/170.3 MHz, 171.3 MHz
Figure 41. AD9445-105 Two-Tone SFDR vs. Analog Input Level
105 MSPS/30.3 MHz, 31.3 MHz
Rev. 0 | Page 20 of 40
AD9445
25000
20000
15000
10000
5000
0
30000
25000
20000
15000
10000
5000
0
23754
SAMPLE SIZE = 65538
22190
26294
16117
15743
9003
7968
3493
3350
1355
1127
307
N – 4 N – 3 N – 2 N – 1
227
N + 1 N + 2 N + 3 N + 4
62
75
3
2
2
N – 4 N – 3 N – 2 N – 1
N
N + 1 N + 2 N + 3 N + 4
N
OUTPUT CODE
OUTPUT CODE
Figure 42. AD9445-125 Grounded Input Histogram
Figure 45. AD9445-105 Grounded Input Histogram
0
–10
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
105MSPS
170.3MHz @ –7.0dBFS
171.3MHz @ –7.0dBFS
SFDR = 92dBFS
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–0.7
–0.8
0
13.125
26.250
39.375
52.500
–40
–20
0
20
40
60
80
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 43. AD9445-105 64k Point Two-Tone FFT/105 MSPS/170.3 MHz, 171.3 MHz
Figure 46. AD9445-125 Gain vs. Temperature
0.4
0.3
0
–10
–20
0.2
–30
–40
–50
–60
–70
–80
–90
–100
SFDR dBc
0.1
WORST IMD3 dBc
0
–0.1
–0.2
–0.3
–0.4
SFDR dBFS
–110
–120
WORST IMD3 dBFS
0
4096
8192
12288
16384
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
OUTPUT CODE
FUNDAMENTAL LEVEL (dB)
Figure 44. AD9445-105 Two-Tone SFDR vs. Analog Input Level
105 MSPS/170.3 MHz, 171.3 MHz
Figure 47. AD9445-105 DNL Error vs. Output Code, 105 MSPS, 10.3 MHz
Rev. 0 | Page 21 of 40
AD9445
0.4
1.0
0.8
0.3
0.6
0.2
0.4
0.1
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
0
4096
8192
12288
16384
0
4096
8192
12288
16384
OUTPUT CODE
OUTPUT CODE
Figure 48. AD9445-125 DNL Error vs. Output Code, 125 MSPS, 10.3 MHz
Figure 51. AD9445-125 INL Error vs. Output Code, 125 MSPS, 10.3 MHz
400
350
1.014
1.012
1.010
1.008
1.006
1.004
1.002
300
AVDD1
250
200
AVDD2
150
100
DRVDD
50
0
0
20
40
60
80
100
120
140
160
–40
–20
0
20
40
60
80
SAMPLE RATE (MSPS)
TEMPERATURE (°C)
Figure 52. AD9445-105 Power Supply Current vs. Sample Rate
10.3 MHz @ −1 dBFS
Figure 49. AD9445-125 VREF vs. Temperature
78
0.5
0.4
0.3
77
170.3MHz SNR dB
76
0.2
0.1
75
74
73
72
71
225.3MHz SNR dB
300.3MHz SNR dB
0
–0.1
–0.2
–0.3
–0.4
–0.5
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
0
4096
8192
12288
16384
ANALOG INPUT RANGE (V p-p)
OUTPUT CODE
Figure 53. AD9445-125 SNR vs. Analog Input Range, 125 MSPS/170.3 MHz,
225.3 MHz, 300.3 MHz
Figure 50. AD9445-105 INL Error vs. Output Code, 105 MSPS, 10.3 MHz
Rev. 0 | Page 22 of 40
AD9445
78
77
95
90
85
80
75
70
170.3MHz SFDR dBc
76
75
170.3MHz SFDR dBc
225.3MHz SFDR dBc
300.3MHz SFDR dBc
225.3MHz SFDR dBc
74
73
72
71
300.3MHz SFDR dBc
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
ANALOG INPUT RANGE (V p-p)
ANALOG INPUT RANGE (V p-p)
Figure 54. AD9445-105 SNR vs. Analog Input Range,
105 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz
Figure 57. AD9445-105 SFDR vs. Analog Input Range,
105 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz
400
81
350
300
250
200
150
100
50
80
79
78
77
76
75
74
AVDD1
AVDD2
105M SNR dBFS
125M SNR dBFS
DRVDD
20
0
0
40
60
80
100
120
140
160
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
SAMPLE RATE (MSPS)
ANALOG INPUT RANGE (V p-p)
Figure 55. AD9445-125 Power Supply Current vs. Sample Rate
10.3 MHz @ −1 dBFS
Figure 58. SNR vs. Analog Input Range, 2.3 MHz @ −30 dBFS
95
90
170.3MHz SFDR dBc
85
80
225.3MHz SFDR dBc
75
300.3MHz SFDR dBc
70
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2
ANALOG INPUT RANGE (V p-p)
Figure 56. AD9445-125 SFDR vs. Analog Input Range, 125 MSPS/170.3 MHz,
225.3 MHz, 300.3 MHz
Rev. 0 | Page 23 of 40
AD9445
THEORY OF OPERATION
connected to AGND). Because of this trim and the maximum ac
performance provided by the 2.0 V p-p analog input range, there
is little benefit to using analog input ranges <2 V p-p. Users are
cautioned that the differential nonlinearity of the ADC varies
with the reference voltage. Configurations that use <2.0 V p-p
may exhibit missing codes and, therefore, degraded noise and
distortion performance.
The AD9445 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 14-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.
VIN+
ANALOG INPUT AND REFERENCE OVERVIEW
VIN–
REFT
A stable and accurate 0.5 V band gap voltage reference is built
into the AD9445. The input range can be adjusted by varying
the reference voltage applied to the AD9445, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly.
0.1μF
+
ADC
CORE
0.1μF
10μF
REFB
0.1μF
VREF
0.1μF
+
10μF
SELECT
LOGIC
Internal Reference Connection
SENSE
A comparator within the AD9445 detects the potential at the
SENSE pin and configures the reference into three possible states,
which are summarized in Table 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 59), setting VREF to ~1.0 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a ~1.0 V
reference output. If a resistor divider is connected as shown in
Figure 60, the switch again sets to the SENSE pin. This puts the
reference amplifier in a noninverting mode with the VREF
output defined as
0.5V
AD9445
Figure 59. Internal Reference Configuration
VIN+
VIN–
REFT
0.1μF
0.1μF
REFB
+
ADC
CORE
10μF
R2
R1
⎛
⎝
⎞
⎟
⎠
VREF = 0.5V × 1+
⎜
0.1μF
VREF
+
10μF
0.1μF
In all reference configurations, REFT and REFB drive the
analog-to-digital conversion core and establish its input span.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
SELECT
LOGIC
R2
SENSE
R1
0.5V
Internal Reference Trim
AD9445
The internal reference voltage is trimmed during the production
test to adjust the gain (analog input voltage range) of the AD9445.
Therefore, there is little advantage to the user supplying an external
voltage reference to the AD9445. The gain trim is performed
with the AD9445 input range set to 2.0 V p-p nominal (SENSE
Figure 60. Programmable Reference Configuration
Table 9. Reference Configuration Summary
Selected Mode
SENSE Voltage
Resulting VREF (V)
N/A
Resulting Differential Span (V p-p)
2 × external reference
2 × VREF
External Reference
Programmable Reference
AVDD1
0.2 V to VREF
R2
R1
⎛
⎝
⎞
⎟
⎠
(See Figure 60)
0.5 × 1 +
⎜
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
Rev. 0 | Page 24 of 40
AD9445
External Reference Operation
The AD9445’s internal reference is trimmed to enhance the gain
accuracy of the ADC. An external reference may be more stable
over temperature, but the gain of the ADC is not likely to improve.
Figure 49 shows the typical drift characteristics of the internal
reference in both 1 V and 0.5 V modes.
VIN+
VIN–
1V p-p
3.5V
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1.6 V.
DIGITAL OUT = ALL 1s
DIGITAL OUT = ALL 0s
Figure 61. Differential Analog Input Range for VREF = 1.0 V
Therefore, the analog source driving the AD9445 should be ac-
coupled to the input pins. The recommended method for driving
the analog input of the AD9445 is to use an RF transformer to
convert single-ended signals to differential (see Figure 62).
Series resistors between the output of the transformer and the
AD9445 analog inputs help isolate the analog input source from
switching transients caused by the internal sample-and-hold
circuit. The series resistors, along with the 1 kΩ resisters connected
to the internal 3.5 V bias, must be considered in impedance
matching the transformer input. For example, if RT is set to
51 Ω, RS is set to 33 Ω, and there is a 1:1 impedance ratio trans-
former, the input will match a 50 Ω source with a full-scale drive
of 10.0 dBm. The 50 Ω impedance matching can also be incor-
porated on the secondary side of the transformer, as shown in
the evaluation board schematic (see Figure 67).
Analog Inputs
As with most new high speed, high dynamic range ADCs, the
analog input to the AD9445 is differential. Differential inputs
improve on-chip performance because signals are processed
through attenuation and gain stages. Most of the improvement
is a result of differential analog stages having high rejection of
even-order harmonics. There are also benefits at the PCB level.
First, differential inputs have high common-mode rejection of
stray signals, such as ground and power noise. Second, they
provide good rejection of common-mode signals, such as local
oscillator feedthrough. The specified noise and distortion of the
AD9445 cannot be realized with a single-ended analog input, so
such configurations are discouraged. Contact sales for
recommendations of other 14-bit ADCs that support single-
ended analog input configurations.
R
ADT1–1WT
S
ANALOG
INPUT
SIGNAL
VIN+
R
T
AD9445
R
S
With the 1 V reference, which is the nominal value (see the
Internal Reference Trim section), the differential input range of
the AD9445 analog input is nominally 2.0 V p-p or 1.0 V p-p on
each input (VIN+ or VIN−).
VIN–
0.1μF
Figure 62. Transformer-Coupled Analog Input Circuit
High IF Applications
The AD9445 analog input voltage range is offset from ground
by 3.5 V. Each analog input connects through a 1 kΩ resistor to
the 3.5 V bias voltage and to the input of a differential buffer.
The internal bias network on the input properly biases the
buffer for maximum linearity and range (see the Equivalent
Circuits section).
In applications where the analog input frequency range is
>100 MHz, the phase and amplitude matching at the analog
inputs becomes critical to optimize performance of the ADC.
The circuit in Figure 63 can be used to optimize the matching of
these parameters. This configuration uses a double balun config-
uration that has low parasitics, high bandwidth, and parasitic
cancellation.
ETC1–1–13
ETC1–1–13
33
33
Ω
Ω
25
Ω
Ω
VIN+
CT
AD9445
0.1μ
F
0.1μF
25
VIN–
50Ω
SOURCE
Figure 63. Double Balun-Coupled Analog Input Circuit
Rev. 0 | Page 25 of 40
AD9445
Schottky diodes across the secondary of the transformer limit
clock excursions into the AD9445 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9445
and limits the noise presented to the sample clock inputs.
CLOCK INPUT CONSIDERATIONS
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the analog-to-
digital output. For that reason, considerable care was taken in
the design of the clock inputs of the AD9445, and the user is
advised to give careful thought to the clock source.
If a low jitter clock is available, it may help to band-pass filter
the clock reference before driving the ADC clock inputs.
Another option is to ac couple a differential ECL/PECL signal
to the encode input pins, as shown in Figure 65.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be
sensitive to the clock duty cycle. Commonly a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9445 contains a clock duty
cycle stabilizer (DCS) that retimes the nonsampling edge,
providing an internal clock signal with a nominal 50% duty
cycle. Noise and distortion performance are nearly flat for a
30% to 70% duty cycle with the DCS enabled. The DCS circuit
locks to the rising edge of CLK+ and optimizes timing
ADT1–1WT
CLOCK
SOURCE
CLK+
0.1μF
AD9445
CLK–
HSMS2812
DIODES
Figure 64. Crystal Clock Oscillator, Differential Encode
VT
0.1μF
ENCODE
internally. This allows for a wide range of input duty cycles at
the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates of less than
30 MHz nominally. The loop is associated with a time constant
that should be considered in applications where the clock rate
can change dynamically, requiring a wait time of 1.5 μs to 5 μs
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time that
the loop is not locked, the DCS loop is bypassed, and the internal
device timing is dependent on the duty cycle of the input clock
signal. In such an application, it may be appropriate to disable
the duty cycle stabilizer. In all other applications, enabling the
DCS circuit is recommended to maximize ac performance.
ECL/
PECL
AD9445
0.1μF
ENCODE
VT
Figure 65. Differential ECL for Encode
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fINPUT) and rms amplitude due only to aperture jitter
(tJ) can be calculated using the following equation:
SNR = 20 log[2πfINPUT × tJ]
In the equation, the rms aperture jitter represents the root-
mean-square of all jitter sources, which includes the clock
input, analog input signal, and ADC aperture jitter
specification. IF undersampling applications are particularly
sensitive to jitter, see Figure 66.
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the duty cycle
stabilizer, and logic high (AVDD1 = 3.3 V) disables the
controller.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9445. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or another
method), it should be synchronized by the original clock during
the last step.
The AD9445 input sample clock signal must be a high quality,
extremely low phase noise source to prevent degradation of
performance. Maintaining 14-bit accuracy places a premium on
the encode clock phase noise. SNR performance can easily
degrade by 3 dB to 4 dB with 70 MHz analog input signals
when using a high jitter clock source. (See the AN-501
Application Note, Aperture Uncertainty and ADC System
Performance.) For optimum performance, the AD9445 must be
clocked differentially. The sample clock inputs are internally
biased to ~2.2 V, and the input signal is usually ac-coupled into
the CLK+ and CLK− pins via a transformer or capacitors.
Figure 64 shows one preferred method for clocking the
AD9445. The clock source (low jitter) is converted from single-
ended to differential using an RF transformer. The back-to-back
Rev. 0 | Page 26 of 40
AD9445
75
70
65
60
55
50
45
40
resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
0.2ps
0.5ps
performance, including both SFDR and SNR, is maximized
when the AD9445 is used in LVDS mode; designers are
encouraged to take advantage of this mode. The AD9445
outputs include complimentary LVDS outputs for each data bit
(Dx+/Dx−), the overrange output (OR+/OR−), and the output
data clock output (DCO+/DCO−). The RSET resistor current is
multiplied on-chip, setting the output current at each output
equal to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential
termination resistor placed at the LVDS receiver inputs results
in a nominal 350 mV swing at the receiver. LVDS mode
facilitates interfacing with LVDS receivers in custom ASICs and
FPGAs that have LVDS capability for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended, with a 100 Ω termination resistor
placed as close to the receiver as possible. It is recommended to
keep the trace length less than 2 inches and to keep differential
output trace lengths as equal as possible.
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
1
10
100
1000
INPUT FREQUENCY (MHz)
Figure 66. SNR vs. Input Frequency and Jitter
POWER CONSIDERATIONS
Care should be taken when selecting a power source. The use of
linear dc supplies is highly recommended. Switching supplies
tend to have radiated components that may be received by the
AD9445. Each of the power supply pins should be decoupled as
closely to the package as possible using 0.1 μF chip capacitors.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic
performance, the AD9445 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR. The output clock is provided as a differential CMOS signal,
DCO+/DCO−. Lower supply voltages are recommended to
avoid coupling switching transients back to the sensitive analog
sections of the ADC. The capacitive load to the CMOS outputs
should be minimized, and each output should be connected to a
single gate through a series resistor (220 Ω) to minimize
switching transients caused by the capacitive loading.
The AD9445 has separate digital and analog power supply pins.
The analog supplies are denoted AVDD1 (3.3 V) and AVDD2
(5 V), and the digital supply pins are denoted DRVDD. Although
the AVDD1 and DRVDD supplies can be tied together, best
performance is achieved when the supplies are separate. This is
because the fast digital output swings can couple switching
current back into the analog supplies. Note that both AVDD1
and AVDD2 must be held within 5% of the specified voltage.
The DRVDD supply of the AD9445 is a dedicated supply for the
digital outputs in either LVDS or CMOS output mode. When in
LVDS mode, the DRVDD should be set to 3.3 V. In CMOS
mode, the DRVDD supply can be connected from 2.5 V to
3.6 V for compatibility with the receiving logic.
TIMING
The AD9445 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of CLK+. Refer to Figure 2 and
Figure 3 for detailed timing diagrams.
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ RSET
Rev. 0 | Page 27 of 40
AD9445
RF ENABLE
OPERATIONAL MODE SELECTION
The RF ENABLE pin is a CMOS-compatible control pin that
optimizes the configuration of the AD9445 analog front end.
The crossover analog input frequency for determining the
RF ENABLE connection differs for the 105 MSPS and 125 MSPS
speed grades. For the 125 MSPS speed grade, connecting the
RF ENABLE to AGND optimizes SFDR performance for appli-
cations with analog input frequencies <210 MHz. For applications
with analog inputs >210 MHz, this pin should be connected to
AVDD1 for optimum SFDR performance. Connecting this pin to
AVDD1 reconfigures the ADC, thereby improving high IF and RF
spurious performance. Operating in this mode increases power dis-
sipation from AVDD2 by 150 mW to 200 mW. For the 105 MSPS
speed grade, connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies
<230 MHz. For applications with analog inputs >230 MHz, this
pin should be connected to AVDD1 to optimize performance.
Data Format Select
The data format select (DFS) pin of the AD9445 determines
the coding format of the output data. This pin is 3.3 V CMOS-
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Output Mode Select
The OUPUT MODE pin controls the logic compatibility, as well
as the pinout of the digital outputs. This pin is a CMOS-compatible
input. With OUTPUT MODE = 0 (AGND), the AD9445 outputs
are CMOS compatible, and the pin assignment for the device is
as defined in Table 8. With OUTPUT MODE = 1 (AVDD1, 3.3
V), the AD9445 outputs are LVDS compatible, and the pin
assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
Table 10. Digital Output Coding
VIN+ − VIN−
Input Span = 3.2 V p-p (V)
VIN+ − VIN−
Input Span = 2 V p-p (V)
Digital Output
Offset Binary (D13••••••D0)
Digital Output
Twos Complement (D13••••••D0)
Code
16,3ꢀ3 +1.600
+1.000
0
−0.000122
−1.00
11 1111 1111 1111
10 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
01 1111 1111 1111
00 0000 0000 0000
11 1111 1111 1111
10 0000 0000 0000
ꢀ192
ꢀ191
0
0
−0.000195
−1.60
Rev. 0 | Page 2ꢀ of 40
AD9445
EVALUATION BOARD
Evaluation boards are offered to configure the AD9445 in
either CMOS or LVDS mode only. This design represents a
recommended configuration for using the device over a wide
range of sampling rates and analog input frequencies. These
evaluation boards provide all the support circuitry required to
operate the ADC in its various modes and configurations.
Complete schematics are shown in Figure 67 through Figure 70.
Gerber files are available from engineering applications demon-
strating the proper routing and grounding techniques that should
be applied at the system level.
The LVDS mode evaluation boards include an LVDS-to-CMOS
translator, making them compatible with the high speed ADC
FIFO evaluation kit (HSC-ADC-EVALA-SC). The kit includes a
high speed data capture board that provides a hardware solution
for capturing up to 32 kB samples of high speed ADC output
data in a FIFO memory chip (user upgradeable to 256 kB
samples). Software is provided to enable the user to download
the captured data to a PC via the USB port. This software also
includes a behavioral model of the AD9445 and many other
high speed ADCs.
It is critical that signal sources with very low phase noise
(<60 fsec rms jitter) be used to realize the ultimate performance
of the converter. Proper filtering of the input signal to remove
harmonics and lower the integrated noise at the input is also
necessary to achieve the specified noise performance.
Behavioral modeling of the AD9445 is also available at
www.analog.com/ADIsimADC. The ADIsimADC™ software
supports virtual ADC evaluation using ADI proprietary behavioral
modeling technology. This allows rapid comparison between
the AD9445 and other high speed ADCs with or without
hardware evaluation boards.
The evaluation boards are shipped with a 115 V ac to 6 V dc
power supply. The evaluation boards include low dropout
regulators to generate the various dc supplies required by the
AD9445 and its support circuitry. Separate power supplies are
provided to isolate the DUT from the support circuitry. Each
input configuration can be selected by proper connection of
various jumpers (see Figure 67).
The user can choose to remove the translator and terminations
to access the LVDS outputs directly.
Rev. 0 | Page 29 of 40
AD9445
1
2
XTALPWR
EXTREF
DRGND
P1
P2
3
4
P3
P4
DRVDD
1
2
P1
P2
GND
VCC
GND
5V
3
4
P3
P4
H4
MTHOLE6
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
D0_T
D0_C
DRVDD
D11_C/D6_Y
D11_T/D7_Y
DRVDD
D11_C
D11_T
D12_C
D12_T
D13_C
D13_T
D14_C
D14_T
D15_C
D15_T
DRGND
DRVDD
OR_C
D0_T
D0_C (LSB)
DRVDD
DRGND
GND
H3
MTHOLE6
DRVDD
DRGND
AGND
AVDD1
AVDD1
AVDD1
AGND
ENCB
D12_C/D8_Y
D12_T/D9_Y
D13_C/D10_Y
D13_T/D11_Y
D14_C/D12_Y
D14_T/D13_Y
D15_C/D14_Y
(MSB) D15_T/D15_Y
DRGND
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
H1
MTHOLE6
VCC
VCC
GND
VCC
H2
MTHOLE6
GND
DRGND
ENCB
ENC
ENC
AGND
GND
VCC
5V
DRVDD
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
DOR_C
DOR_T/DOR_Y
GND
OR_T
VCC
5V
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
AGND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
5V
EPAD
101
OPTIONAL
C91
0.1μF
ETC1-1-13
+
PRI
SEC
Figure 67. AD9445 Evaluation Board Schematic
Rev. 0 | Page 30 of 40
AD9445
C R 1
2
1
3
1
2
3
C R 2
Figure 68. AD9445 Evaluation Board Schematic (Continued)
Rev. 0 | Page 31 of 40
AD9445
BYPASS CAPACITORS
VCC
GND
VCC
GND
+
C64
10μF
C43
0.1μF
C35
0.1μF
C32
0.1μF
C30
0.01μF
C28
0.1μF
C27
0.1μF
C90
0.1μF
C50
0.1μF
C60
0.1μF
C10
0.1μF
C61
0.1μF
C75
0.1μF
C11
XX
C14
XX
C17
XX
C16
XX
C15
XX
C31
XX
C38
XX
C29
XX
C19
XX
DRVDD
DRGND
5V
DRVDD
+
C65
10μF
C47
0.1μF
C23
0.1μF
C21
0.1μF
C20
0.1μF
C69
XX
C70
XX
C45
XX
C49
XX
DRGND
EXTREF
+
+
C56
10μF
C85
0.1μF
C53
0.1μF
C52
0.1μF
C58
0.01μF
C37
0.1μF
C48
0.1μF
C18
0.1μF
C55
10μF
GND
5V
GND
C72
XX
C73
XX
C108
XX
C109
XX
C110
XX
GND
5V
C94
C95
C22
C59
C93
C96
C97
C84
C46
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
GND
Figure 69. AD9445 Evaluation Board Schematic (Continued)
Rev. 0 | Page 32 of 40
AD9445
Figure 70. AD9445 Evaluation Board Schematic (Continued)
Rev. 0 | Page 33 of 40
AD9445
Table 11. AD9445-125 Baseband Customer Evaluation Board Bill of Materials
Item Qty. Reference Designator Description
Package
Value
Manufacturer
Mfg. Part No.
1
7
C4, C6, C33, C34, Cꢀ7,
Cꢀꢀ, Cꢀ9
Capacitor
TAJD
10 ꢁF
Digi-Key Corporation 47ꢀ-1699-2
2
44
C2, C3, C5, C7, Cꢀ,
C9, C10, C11, C12,
C15, C20, C21, C22,
C23, C26, C27, C2ꢀ,
C32, C35, C3ꢀ, C40,
C42, C43, C46, C47,
C4ꢀ, C50, C52, C53,
C59, C60, C76, C77,
C7ꢀ, Cꢀ2, Cꢀ4, Cꢀ5,
Cꢀ6, C90, C91, C94,
C95, C96, C97
Capacitor
402
0.1 ꢁF
Digi-Key Corporation PCC2146CT-ND
3
4
5
6
7
ꢀ
2
4
1
1
1
20
C30, C5ꢀ
C39, C56, C64, C65
C51
CR1
CR2
E1, E2, E3, E4, E5, E6,
E9, E10, E14, E1ꢀ, E19,
E20, E24, E25, E26, E27,
E30, E31, E36, E41
Capacitor
Capacitor
Capacitor
Diode
Diode
Header
201
TAJD
ꢀ05
SOT23M5
SOT23M5
EHOLE
0.01 ꢁF Digi-Key Corporation 445-1796-1-ND
10 ꢁF
10 ꢁF
Digi-Key Corporation 47ꢀ-1699-2
Digi-Key Corporation 490-1717-1-ND
Digi-Key Corporation MA3X71600LCT-ND
Digi-Key Corporation MA3X71600LCT-ND
Mouser Electronics
517-6111TG
9
10
11
2
1
3
J1, J4
L1
L3, L4, L5
SMA
Inductor
EMIFIL®
SMA
0603A
1206MIL
Digi-Key Corporation ARFX1231-ND
10 nH
Coilcraft, Inc.
0603CS-10NXGBU
ꢀ1-BLM31P500S
Mouser Electronics
BLM31PG500SN1L
12
13
14
15
16
17
1ꢀ
19
20
21
22
23
24
25
26
27
2ꢀ
1
1
1
1
4
1
2
2
2
1
1
2
1
1
2
2
23
P4
P7
R3
Rꢀ
PJ-002A
Header
Resistor
Resistor
Resistor
BRES402
Resistor
Resistor array
Transformer
AD9445BSVZ-125
ADP333ꢀ-5
ADP333ꢀ-3.3
SN75LVDT3ꢀ6
SN75LVDT390
Resistor
PJ-002A
C40MS
402
402
402
402
402
16PIN
ADT1-1WT
SV-100-3
SOT-223HS
SOT-223HS
TSSOP64
SOIC16PW
402
Digi-Key Corporation CP-002A-ND
Samtec, Inc. TSW-120-0ꢀ-L-D-RA
3.74 kΩ Digi-Key Corporation P3.74KLCT-ND
50 Ω
0 Ω
1 kΩ
33 Ω
22 Ω
Digi-Key Corporation P49.9LCT-ND
Digi-Key Corporation P0.0JCT-ND
Digi-Key Corporation P1.0KLCT-ND
Digi-Key Corporation P33JCT-ND
Digi-Key Corporation 742C163220JCT-ND
R10, R19, R39, L2
R11
R2ꢀ, R35
RZ4, RZ5
T3, T5
U1
U14
U3, U7
Uꢀ
U15
Mini-Circuits
ADT1-1WT
Analog Devices, Inc.
Analog Devices, Inc.
Analog Devices, Inc.
AD9445BSVZ-125
ADP333ꢀ-5
ADP333ꢀ-33
Arrow Electronics, Inc. SN75LVDT3ꢀ6DGG
Arrow Electronics, Inc. SN75LVDT390PW
Digi-Key Corporation P36JCT-ND
Digi-Key Corporation 47ꢀ-1699-2
R4, R6
C1, C44, C551
36 Ω
10 ꢁF
XX
Capacitor
CAP402
TAJD
402
C13, C14, C16, C17,
C1ꢀ, C19, C29, C31,
C36, C37, C41, C45,
C49, C61, C69, C70,
C72, C73, C75, C93,
C10ꢀ, C109, C1101
29
30
31
32
33
34
35
1
C9ꢀ1
Capacitor
Header
SMA
Header
BRES402
BRES402
ECLOSC
ꢀ05
EHOLE
SMA
C40MS
402
402
10 ꢁF
Digi-Key Corporation 490-1717-1-ND
E151
Mouser Electronics
Digi-Key Corporation ARFX1231-ND
Samtec, Inc. TSW-120-0ꢀ-L-D-RA
517-6111TG
J51
P61
2
3
1
R1, R21
R5, R7, R91
U21
XX
XX
DIP4(14)
Rev. 0 | Page 34 of 40
AD9445
Item Qty. Reference Designator Description
Package
MTHOLE6
SM-22
Value
Manufacturer
Mfg. Part No.
36
37
3ꢀ
4
2
2
H1, H2, H3, H41
T1, T21
P21, P221
MTHOLE6
Balun transformer
Term strip
M/A-COM
Newark Electronics
ETC1-1-13
PTMICRO4
1 Parts not populated.
Table 12. AD9445-125 IF Customer Evaluation Board Bill of Materials
Item Qty. Reference Designator Description Package
Value
Manufacturer
MFG_PART_NO
1
7
C4, C6, C33, C34, Cꢀ7,
Cꢀꢀ, Cꢀ9
Capacitor
TAJD
10 ꢁF
Digi-Key Corporation 47ꢀ-1699-2
2
44
C2, C3, C5, C7, Cꢀ,
C9, C10, C11, C12,
C15, C20, C21, C22,
C23, C26, C27, C2ꢀ,
C32, C35, C3ꢀ, C40,
C42, C43, C46, C47,
C4ꢀ, C50, C52, C53,
C59, C60, C76, C77,
C7ꢀ, Cꢀ2, Cꢀ4, Cꢀ5,
Cꢀ6, C90, C91, C94,
C95, C96, C97
Capacitor
402
0.1 ꢁF
Digi-Key Corporation PCC2146CT-ND
3
4
5
6
7
ꢀ
2
4
1
1
1
20
C30, C5ꢀ
C39, C56, C64, C65
C51
CR1
CR2
E1, E2, E3, E4, E5, E6,
E9, E10, E14, E1ꢀ, E19,
E20, E24, E25, E26, E27,
E30, E31, E36, E41
Capacitor
Capacitor
Capacitor
Diode
Diode
Header
201
TAJD
ꢀ05
SOT23M5
SOT23M5
EHOLE
0.01 ꢁF Digi-Key Corporation 445-1796-1-ND
10 ꢁF
10 ꢁF
Digi-Key Corporation 47ꢀ-1699-2
Digi-Key Corporation 490-1717-1-ND
Digi-Key Corporation MA3X71600LCT-ND
Digi-Key Corporation MA3X71600LCT-ND
Mouser Electronics
517-6111TG
9
2
1
3
1
1
1
1
4
1
2
2
1
1
J1, J4
L1
L3, L4, L5
P4
P7
R3
Rꢀ
R10, R19, R39, L2
R11
R2ꢀ, R35
RZ4, RZ5
U1
SMA
Inductor
SMA
0603A
Digi-Key Corporation ARFX1231-ND
10
11
12
13
14
15
16
17
1ꢀ
19
20
21
10 nH
Coilcraft, Inc.
Mouser Electronics
0603CS-10NXGBU
ꢀ1-BLM31P500S
EMIFIL® BLM31PG500SN1L 1206MIL
PJ-002A
Header
Resistor
Resistor
Resistor
BRES402
Resistor
PJ-002A
C40MS
402
402
402
402
402
16PIN
SV-100-3
SOT-
Digi-Key Corporation CP-002A-ND
Samtec, Inc. TSW-120-0ꢀ-L-D-RA
3.74 kΩ Digi-Key Corporation P3.74KLCT-ND
50 Ω
0 Ω
1 kΩ
33 Ω
22 Ω
Digi-Key Corporation P49.9LCT-ND
Digi-Key Corporation P0.0JCT-ND
Digi-Key Corporation P1.0KLCT-ND
Digi-Key Corporation P33JCT-ND
Digi-Key Corporation 742C163220JCT-ND
Resistor array
AD9445BSVZ-125
ADP333ꢀ-5
Analog Devices, Inc.
Analog Devices, Inc.
AD9445BSVZ-125
ADP333ꢀ-5
U14
223HS
22
23
24
25
26
27
2ꢀ
2
1
1
2
1
1
2
U3, U7
Uꢀ
U15
T1, T2
R5
T3
ADP333ꢀ-3.3
SN75LVDT3ꢀ6
SN75LVDT390
Balun transformer
Resistor
SOT-223HS
TSSOP64
SOIC16PW
SM-22
402
ADT1-1WT
TAJD
Analog Devices, Inc.
Arrow Electronics, Inc. SN75LVDT3ꢀ6DGG
Arrow Electronics, Inc. SN75LVDT390PW
M/A-COM
Digi-Key Corporation P49.9LCT-ND
Mini-Circuits ADT1-1WT
Digi-Key Corporation 47ꢀ-1699-2
ADP333ꢀ-3.3
ETC-1-1-13
36 Ω
Transformer
Capacitor
C1, C44, C551
10 ꢁF
Rev. 0 | Page 35 of 40
AD9445
Item Qty. Reference Designator Description
Package
Value
Manufacturer
MFG_PART_NO
29
23
C13, C14, C16, C17,
C1ꢀ, C19, C29, C31,
C36, C37, C41, C45,
C49, C61, C69, C70,
C72, C73, C75, C93,
C10ꢀ, C109, C1101
CAP402
402
XX
30
31
32
33
34
35
36
37
3ꢀ
39
40
1
C9ꢀ1
Capacitor
Header
SMA
ꢀ05
EHOLE
SMA
C40MS
402
402
DIP4(14)
MTHOLE6
402
ADT1-1WT
PTMICRO4
10 ꢁF
Digi-Key Corporation 409-1717-1-ND
Mouser Electronics 517-6111TG
Digi-Key Corporation ARFX1231-ND
E151
J51
P61
Header
Samtec, Inc.
TSW-120-0ꢀ-L-D-RA
2
3
1
4
2
1
2
R1, R21
R5, R7, R91
U21
BRES402
BRES402
ECLOSC
MTHOLE6
Resistor
Transformer
Term strip
XX
XX
H1, H2, H3, H41
R4, R61
T51
36
Digi-Key Corporation P36JCT-ND
Mini-Circuits
ADT1-1WT
P21, P221
Newark Electronics
1 Parts not populated.
Rev. 0 | Page 36 of 40
AD9445
OUTLINE DIMENSIONS
16.00 BSC SQ
1.20
MAX
0.75
0.60
0.45
14.00 BSC SQ
100
1
76
75
76
75
100
1
PIN 1
EXPOSED
PAD
9.50 SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
BOTTOM VIEW
(PINS UP)
50
51
25
25
26
49
50
26
3.5°
0°
0.08 MAX
COPLANARITY
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
0.15
0.05
SEATING
PLANE
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 71. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9445BSVZ-1251
AD9445BSVZ-1051
AD9445-IF-LVDS/PCB
AD9445-BB-LVDS/PCB
Temperature Range
–40°C to +ꢀ5°C
–40°C to +ꢀ5°C
Package Description
Package Option
SV-100-3
SV-100-3
100-Lead TQFP_EP
100-Lead TQFP_EP
AD9445-125 IF (>100 MHz) LVDS Mode Evaluation Board
AD9445-125 Baseband (<100 MHz) LVDS Mode Evaluation Board
1 Z = Pb-free part.
Rev. 0 | Page 37 of 40
AD9445
NOTES
Rev. 0 | Page 3ꢀ of 40
AD9445
NOTES
Rev. 0 | Page 39 of 40
AD9445
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05489–0–10/05(0)
Rev. 0 | Page 40 of 40
相关型号：
AD9445BSV-105
1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100, LEAD FREE, PLASTIC, MS-026-AED, TQFP-100
ADI
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