AD95160 [ADI]
14-Channel Clock Generator with Integrated 2.8 GHz VCO; 14通道时钟发生器，集成2.8 GHz的VCO
| 型号： | AD95160 |
| 厂家： | 
ADI |
| 描述： | 14-Channel Clock Generator with Integrated 2.8 GHz VCO |
| 文件： | 总2页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Channel Clock Generator with
Integrated 2.8 GHz VCO
AD9516-0
Preliminary Technical Data
FEATURES
Low Broadband Jitter, < 500 Femtoseconds RMS
On-Chip 2.60 GHz – 2.95 GHz VCO
Low Phase Noise, Integer-N Frequency Synthesizer
Digital or Analog PLL Lock Detect
On-chip dividers may be set to any integer value, 1-32. In
addition, the LVDS/CMOS channels use cascaded dividers for a
maximum divide ratio of 1024. Each LVDS/CMOS channel
also offers an adjustable delay from 1.5 ns to 10 ns, programmed
as 64 steps.
Programmable Delays in R and N path
Supports Internal or External VCO
Two Reference Clock Inputs, A and B
Frequencies to 250 MHz
On-Chip Reference Clock Monitors
Auto and Manual Switchover, Holdover
Up to 14 Low Jitter Clock Drivers
The AD9516-0 is available in a 64-lead LFCSP and may be
operated from a single 3.3 V supply. If an external VCO is used,
the VCP pin may be set to a max value of 5.5V. The power
supply to the LVPECL outputs may be varied to support 2.5V or
3.3V LVPECL outputs. The AD9516-0 operates over the
standard industrial range of-40°C to +85°C.
Six LVPECL Outputs Operate to Max VCO Frequency
Four/Eight LVDS/CMOS outputs run 1 GHz/250 MHz
Programmable Dividers with Phase Offset
Programmable Delay on Four Channels
Serial Control Port
A
÷R
CP
B
PFD
VCO
÷N
64-lead LFCSP package
z
APPLICATIONS
Low Jitter Clock Generation and Clock Distribution
Wired and Wireless Infrastructure
Base Stations, Optical Networks, Cable Head-Ends
Instrumentation and Imaging
Test Equipment, ATE
6 LVPECL OUTPUTS
z
z
z
z
DIVIDER
z
z
DIVIDER
DIVIDER
Clean Clocks for ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
Clock Cleanup and Distribution for Line Cards
GENERAL DESCRIPTION
4/8 LVDS/CMOS OUTPUTS
The AD9516-0 generates up to fourteen output clocks from a
single input reference frequency. Integrated on chip is a
complete PLL with VCO, programmable dividers, adjustable
delay blocks, and multiple output logic stages. Sub-picosecond
jitter performance is maintained using on-chip 2.60 – 2.95 GHz
VCO. The AD9516 also supports the use of an external
VCO/VCXO/VCSO up to 2.4 GHz.
z
z
DELAY
DELAY
DELAY
DELAY
DIVIDER
DIVIDER
z
The AD9516-0 features six LVPECL outputs (grouped in three
pairs), which operate up to the maximum frequency of on-chip
VCO. The remaining outputs are user-programmed as either
LVDS (four max) or CMOS (eight max). The programmable
outputs operate to 1 GHz in LVDS mode and to 250MHz in
CMOS mode.
AD9516-0
Figure 1. Basic Block Diagram
Rev. prA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2005 Analog Devices, Inc. All rights reserved.
Preliminary Technical Data
OUTLINE DIMENSIONS
AD9516-0
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 x 9 mm Body, Very Thin Quad
(CP-64-4)
a
Dimensions shown in millimeters
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
64
49
48
1
PIN 1
INDICATOR
6.35
6.20 SQ
6.05
8.75
BSC SQ
TOP
VIEW
EXPOSED PAD
(BOTTOM VIEW)
0.45
0.40
0.35
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.50 BSC
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 2. Outline Dimensions
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06419-0-10/06(PrA)
Rev. prA | Page 2 of 2
相关型号：
AD9517-1BCPZ
9517 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48
ROCHESTER
©2020 ICPDF网 联系我们和版权申明