AD9517-2_技术文档

12-Output Clock Generator with

Integrated 2.2 GHz VCO

Data Sheet

AD9517-2

FEATURES

FUNCTIONAL BLOCK DIAGRAM

CP

LF

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 2.05 GHz to 2.33 GHz

External VCO/VCXO to 2.4 GHz optional

1 differential or 2 single-ended reference inputs

Reference monitoring capability

Automatic revertive and manual reference

switchover/holdover modes

Accepts LVPECL, LVDS, or CMOS references to 250 MHz

Programmable delays in path to PFD

Digital or analog lock detect, selectable

2 pairs of 1.6 GHz LVPECL outputs

Each output pair shares a 1-to-32 divider with coarse

phase delay

Additive output jitter: 225 fs rms

Channel-to-channel skew paired outputs of <10 ps

2 pairs of 800 MHz LVDS clock outputs

Each output pair shares two cascaded 1-to-32 dividers

with coarse phase delay

REF1

REF2

STATUS

MONITOR

REFIN

CLK

VCO

DIVIDER

AND MUXs

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

DIV/Φ

LVPECL

Δt

DIV/Φ

LVDS/CMOS

SERIAL CONTROL PORT

AND

AD9517-2

DIGITAL LOGIC

Additive output jitter: 275 fs rms

Figure 1.

Fine delay adjust (Δt) on each LVDS output

Each LVDS output can be reconfigured as two 250 MHz

CMOS outputs

Automatic synchronization of all outputs on power-up

Manual output synchronization available

Available in a 48-lead LFCSP

The AD9517-2 features four LVPECL outputs (in two pairs)

and four LVDS outputs (in two pairs). Each LVDS output can

be reconfigured as two CMOS outputs. The LVPECL outputs

operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and

the CMOS outputs operate to 250 MHz.

For applications that require additional outputs, a crystal reference

input, zero-delay, or EEPROM for automatic configuration at

startup, the AD9520 and AD9522 are available. In addition,

the AD9516 and AD9518 are similar to the AD9517 but have

a different combination of outputs.

APPLICATIONS

Low jitter, low phase noise clock distribution

10/40/100 Gb/sec networking line cards, including SONET,

Synchronous Ethernet, OTU2/3/4

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

Each pair of outputs has dividers that allow both the divide

ratio and coarse delay (or phase) to be set. The range of division

for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs

allow a range of divisions up to a maximum of 1024.

ATE and high performance instrumentation

GENERAL DESCRIPTION

The AD9517-2 is available in a 48-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated

by connecting the charge pump supply (VCP) to 5 V. A

separate LVPECL power supply can be from 2.5 V to 3.3 V

(nominal).

The AD9517-2¹provides a multi-output clock distribution

function with subpicosecond jitter performance, along with an

on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz

to 2.33 GHz. Optionally, an external VCO/VCXO of up to

2.4 GHz can be used.

The AD9517-2 emphasizes low jitter and phase noise to maximize

data converter performance, and it can benefit other applications

with demanding phase noise and jitter requirements.

The AD9517-2 is specified for operation over the industrial

range of −40°C to +85°C.

¹AD9517 is used throughout the data sheet to refer to all the members of the

AD9517 family. However, when AD9517-2 is used, it refers to that specific

member of the AD9517 family.

Rev. F

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

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AD9517-2

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

ESD Caution ............................................................................... 17

Pin Configuration and Function Descriptions .......................... 18

Typical Performance Characteristics .......................................... 20

Terminology.................................................................................... 26

Detailed Block Diagram ................................................................ 27

Theory of Operation ...................................................................... 28

Operational Configurations...................................................... 28

Digital Lock Detect (DLD) ....................................................... 37

Clock Distribution ..................................................................... 41

Reset Modes ................................................................................ 49

Power-Down Modes.................................................................. 50

Serial Control Port ......................................................................... 51

Serial Control Port Pin Descriptions....................................... 51

General Operation of Serial Control Port .............................. 51

The Instruction Word (16 Bits) ............................................... 52

MSB/LSB First Transfers........................................................... 52

Thermal Performance.................................................................... 55

Control Registers............................................................................ 56

Control Register Map Overview .............................................. 56

Control Register Map Descriptions......................................... 59

Applications Information ............................................................. 76

Frequency Planning Using the AD9517 ................................. 76

Using the AD9517 Outputs for ADC Clock Applications... 76

LVPECL Clock Distribution..................................................... 77

LVDS Clock Distribution.......................................................... 77

CMOS Clock Distribution........................................................ 78

Outline Dimensions....................................................................... 79

Ordering Guide .......................................................................... 79

Applications ...................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications .................................................................................... 4

Power Supply Requirements....................................................... 4

PLL Characteristics ...................................................................... 4

Clock Inputs.................................................................................. 6

Clock Outputs............................................................................... 6

Timing Characteristics ................................................................ 8

Clock Output Additive Phase Noise (Distribution Only;

VCO Divider Not Used).............................................................. 9

Clock Output Absolute Phase Noise (Internal VCO Used). 10

Clock Output Absolute Time Jitter (Clock Generation Using

Internal VCO)............................................................................. 11

Clock Output Absolute Time Jitter (Clock Cleanup Using

Internal VCO)............................................................................. 11

Clock Output Absolute Time Jitter (Clock Generation Using

External VCXO) ......................................................................... 11

Clock Output Additive Time Jitter (VCO Divider Not Used)

....................................................................................................... 12

Clock Output Additive Time Jitter (VCO Divider Used) .... 12

Delay Block Additive Time Jitter............................................. 13

Serial Control Port ..................................................................... 13

PD SYNC

RESET

Pins..................................................... 14

,

, and

LD, STATUS, and REFMON Pins........................................... 14

Power Dissipation ...................................................................... 15

Timing Diagrams............................................................................ 16

Absolute Maximum Ratings ......................................................... 17

Thermal Resistance.................................................................... 17

Rev. F | Page 2 of 80

Data Sheet

AD9517-2

REVISION HISTORY

1/2010—Rev. 0 to Rev. A

9/2020—Rev. E to Rev. F

Added 48-Lead LFCSP Package (CP-48-8)....................Universal

Changes to Features, Applications, and General Description....1

Change to CPRSET Pin Resistor Parameter .................................4

Changes to Table 4............................................................................6

Changed CP-48-8 to CP-48-9 ..................................... Throughout

Changes to Figure 6 ........................................................................18

Updated Outline Dimensions .......................................................79

Changes to Ordering Guide...........................................................79

Changes to V

_CPSupply Parameter................................................14

3/2013—Rev. D to Rev. E

Changes to Table 19........................................................................16

Added Exposed Paddle Notation to Figure 6; Changes to

Table 20 ............................................................................................17

Change to High Frequency Clock Distribution—CLK or

Changes to Table 52........................................................................57

Changes to Table 57........................................................................70

1/2012—Rev. C to Rev. D

External VCO > 1600 MHz Section; Change to Table 22.........27

Changes to Table 24........................................................................29

Change to Configuration and Register Settings Section ...........31

Change to Phase Frequency Detector (PFD) Section................32

Changes to Charge Pump (CP), On-Chip VCO, PLL

External Loop Filter, and PLL Reference Inputs Sections.........33

Change to Figure 46; Added Figure 47........................................33

Changes to Reference Switchover and VCXO/VCO

Feedback Divider N—P, A, B, R Sections....................................34

Changes to Table 28........................................................................35

Change to Holdover Section .........................................................37

Changes to VCO Calibration Section ..........................................39

Changes to Clock Distribution Section .......................................40

Change to Clock Frequency Division Section;

Changes to Table 62........................................................................75

5/2011—Rev. B to Rev. C

Changes to Features, Applications, and General Description

Sections...............................................................................................1

Change to CPRSET Pin Resistor Parameter, Table 1 ..................4

Changes to Table 2............................................................................4

Changes to Table 4............................................................................6

Changes to Logic 1 Current and Logic 0 Current

Parameters, Table 15.......................................................................14

Changes to Table 20........................................................................18

Change to Caption, Figure 8..........................................................20

Change to Caption, Figure 15 .......................................................21

Change to Captions, Figure 25 and Figure 26.............................23

Added Figure 41; Renumbered Sequentially...............................25

Changes to On-Chip VCO Section ..............................................34

Changes to Reference Switchover Section...................................35

Changes to Prescaler Section and Change to

Change to Table 34 .........................................................................41

Changes to Channel Dividers—LVDS/CMOS Outputs

Section; Change to Table 39 ..........................................................43

Change to Write Section................................................................50

Change to MSB/LSB First Transfers ............................................51

Change to Figure 64........................................................................52

Added Thermal Performance Section .........................................54

Changes to 0x003 Register Address .............................................55

Changes to Table 53........................................................................58

Changes to Table 54........................................................................59

Changes to Table 55........................................................................65

Changes to Table 56........................................................................67

Changes to Table 57........................................................................69

Changes to Table 58........................................................................71

Changes to Table 59........................................................................72

Changes to Table 60 and Table 61................................................74

Added Frequency Planning Using the AD9517 Section ...........75

Changes to Figure 70 and Figure 72; Added Figure 71 .............76

Changes to LVDS Clock Distribution Section............................76

Added Exposed Paddle Notation to Outline Dimensions ........78

Changes to Ordering Guide ..........................................................78

Comments/Conditions Column, Table 28..................................36

Changes to Automatic/Internal Holdover Mode Section

and Frequency Status Monitors Section......................................39

Changes to VCO Calibration Section ..........................................40

Changes to Clock Distribution Section........................................41

Changes to Write Section...............................................................51

Change to The Instruction Word (16 Bits) Section ...................52

Change to Figure 65........................................................................53

Change to Thermal Performance Section ...................................55

Changes to Register Address 0x01C, Bits[4:3], Table 52...........56

Changes to Address 0x017, Bits[1:0] and Address 0x018,

Bits[2:0], Table 54 ...........................................................................62

Changes to Register Address 0x01C, Bits[5:1], Table 54...........64

Change to LVPECL Clock Distribution Section ........................77

5/2010—Rev. A to Rev. B

Changes to Default Values of LVDS/CMOS Outputs

Section in Table 52..........................................................................56

Changes to Register 0x140, Bit 0; Register 0x142, Bit 0;

Register 0x143, Bit 0 in Table 57...................................................69

Updated Outline Dimensions, Changes to Ordering Guide ....78

7/2007—Revision 0: Initial Version

Rev. F | Page 3 of 80

AD9517-2

Data Sheet

SPECIFICATIONS

Typical is given for V_S= V_{S_LVPECL}= 3.3 V 5ꢀ; V_S≤ V_CP≤ 5.25 V; T_A= 25°C; R_SET= 4.12 kΩ; CP_RSET= 5.1 kΩ, unless otherwise noted.

Minimum and maximum values are given over full V_Sand T_A(−40°C to +85°C) variation.

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter

Min

3.135

2.375

V_S

Typ

Max

3.465

V_S

Unit

V

kΩ

Test Conditions/Comments

3.3 V 5ꢀ

Nominally 2.5 V to 3.3 V 5ꢀ

Nominally 3.3 V to 5.0 V 5ꢀ

Sets internal biasing currents; connect to ground

Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);

actual current can be calculated by CP_lsb = 3.06/CPRSET;

connect to ground

V_S

V_{S_LVPECL}

V_CP

RSET Pin Resistor

CPRSET Pin Resistor

3.3

5.25

4.12

5.1

2.7

10

BYPASS Pin Capacitor

220

nF

Bypass for internal LDO regulator; necessary for LDO stability;

connect to ground

PLL CHARACTERISTICS

Table 2.

Parameter

Min

2050

0.5

Typ

Max

Unit

Test Conditions/Comments

VCO (ON-CHIP)

Frequency Range

VCO Gain (K_VCO

2335

MHz

MHz/V

V

See Figure 15

See Figure 10

)

50

Tuning Voltage (V_T)

V_CP

0.5

−

V_CP≤ V_Swhen using internal VCO; outside of this range, the CP

spurs may increase due to CP up/down mismatch

Frequency Pushing (Open-Loop)

Phase Noise at 100 kHz Offset

Phase Noise at 1 MHz Offset

REFERENCE INPUTS

1

MHz/V

dBc/Hz f = 2175 MHz

−107

−124

REFIN

Differential mode (can accommodate single-ended input by ac

Differential Mode (REFIN,

)

grounding undriven input)

Input Frequency

0

250

MHz

Frequencies below about 1 MHz should be dc-coupled; be

careful to match V_CM(self-bias voltage)

Input Sensitivity

250

mV p-p PLL figure of merit (FOM) increases with increasing slew rate

(see Figure 14); the input sensitivity is sufficient for ac-coupled

LVDS and LVPECL signals

Self-Bias Voltage, REFIN

REFIN

1.35

1.30

4.0

1.60

1.50

4.8

1.75

1.60

5.9

V

Self-bias voltage of REFIN¹

REFIN¹

Self-Bias Voltage,

Self-bias voltage of

Self-biased¹

Input Resistance, REFIN

kΩ

REFIN

4.4

5.3

6.4

Self-biased¹

Input Resistance,

Dual Single-Ended Mode (REF1, REF2)

Input Frequency (AC-Coupled)

Input Frequency (DC-Coupled)

Input Sensitivity (AC-Coupled)

Input Logic High

Two single-ended CMOS-compatible inputs

Slew rate > 50 V/μs

Slew rate > 50 V/μs; CMOS levels

Should not exceed V_Sp-p

20

0

250

MHz

V p-p

V

0.8

2.0

Input Logic Low

0.8

V

Input Current

Pulse Width High/Low

−100

1.8

+100

μA

ns

This value determines the allowable input duty cycle and is the

amount of time that a square wave is high/low

Input Capacitance

2

pF

REFIN

Each pin, REFIN/

(REF1/REF2)

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency

100

45

MHz

ns

Antibacklash pulse width = 1.3 ns, 2.9 ns

Antibacklash pulse width = 6.0 ns

Register 0x017[1:0] = 01b

Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b

Register 0x017[1:0] = 10b

Antibacklash Pulse Width

1.3

2.9

6.0

Rev. F | Page 4 of 80

Data Sheet

AD9517-2

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CHARGE PUMP (CP)

I_CPSink/Source

CP_Vis CP pin voltage; V_CPis charge pump power supply voltage

Programmable

High Value

Low Value

4.8

0.60

2.5

2.7/10

1

2

1.5

2

mA

ꢀ

kΩ

nA

ꢀ

With CPRSET = 5.1 kΩ

Absolute Accuracy

CPRSET Range

I_CPHigh Impedance Mode Leakage

Sink-and-Source Current Matching

I_CPvs. CP_V

I_CPvs. Temperature

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 1 FD

CP_V= V_CP/2 V

0.5 < CP_V< V_CP− 0.5 V

CP_V= V_CP/2 V

ꢀ

See the VCXO/VCO Feedback Divider N—P, A, B, R section

300

600

900

200

1000

2400

3000

300

MHz

P = 2 FD

P = 3 FD

P = 2 DM (2/3)

P = 4 DM (4/5)

P = 8 DM (8/9)

P = 16 DM (16/17)

P = 32 DM (32/33)

Prescaler Output Frequency

A, B counter input frequency (prescaler input frequency

divided by P)

PLL DIVIDER DELAYS

Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 54

000

001

010

011

100

101

110

111

Off

ps

330

440

550

660

770

880

990

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge

Pump/Phase Frequency Detector

(In-Band Is Within the LBW of the PLL)

The PLL in-band phase noise floor is estimated by measuring

the in-band phase noise at the output of the VCO and

subtracting 20 log(N) (where N is the value of the N divider)

At 500 kHz PFD Frequency

At 1 MHz PFD Frequency

At 10 MHz PFD Frequency

At 50 MHz PFD Frequency

PLL Figure of Merit (FOM)

−165

−162

−151

−143

−220

dBc/Hz

dBc/Hz Reference slew rate > 0.25 V/ns; FOM + 10 log(f_PFD) is an approxi-

mation of the PFD/CP in-band phase noise (in the flat region)

inside the PLL loop bandwidth; when running closed-loop, the

phase noise, as observed at the VCO output, is increased by

20 log(N)

PLL DIGITAL LOCK DETECT WINDOW²

Signal available at LD, STATUS, and REFMON pins when selected

by appropriate register settings

Required to Lock (Coincidence of Edges)

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

Selected by Register 0x017[1:0] and Register 0x018[4]

3.5

7.5

3.5

ns

Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b

Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b

Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

To Unlock After Lock (Hysteresis)²

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6.0 ns)

7

15

11

ns

Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b

Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b

Register 0x017[1:0] = 10b; Register 0x018[4] = 0b

1

REFIN

REFIN and

self-bias points are offset slightly to avoid chatter on an open input condition.

²For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

Rev. F | Page 5 of 80

AD9517-2

Data Sheet

CLOCK INPUTS

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK INPUTS (CLK, CLK)

Input Frequency

Differential input

0¹

2.4

1.6

GHz

High frequency distribution (VCO divider)

Distribution only (VCO divider bypassed)

Input Sensitivity, Differential

Input Level, Differential

150

mV p-p

Measured at 2.4 GHz; jitter performance is improved

with slew rates > 1 V/ns

Larger voltage swings may turn on the protection

diodes and may degrade jitter performance

2

V p-p

Input Common-Mode Voltage, V_CM1.3

1.57

1.8

V

Self-biased; enables ac coupling

With 200 mV p-p signal applied; dc-coupled

CLK ac-coupled; CLK ac-bypassed to RF ground

Self-biased

Input Common-Mode Range, V_CMR

Input Sensitivity, Single-Ended

Input Resistance

1.3

150

4.7

2

mV p-p

kΩ

pF

3.9

5.7

Input Capacitance

¹Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V_CM

.

CLOCK OUTPUTS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Termination = 50 Ω to V_S− 2 V

Differential (OUT, OUT)

LVPECL CLOCK OUTPUTS

OUT0, OUT1, OUT2, OUT3

Output Frequency, Maximum

2950

MHz

V

Using direct to output; see Figure 25 for peak-to-peak

differential amplitude

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

Output Differential Voltage (V_OD)

V_{S_LVPECL}

1.12

V_{S_LVPECL}

2.03

−

V_{S_LVPECL}

0.98

V_{S_LVPECL}

1.77

−

V_{S_LVPECL}

− 0.84

V_{S_LVPECL}

− 1.49

V

550

790

980

mV

This is V_OH− V_OLfor each leg of a differential pair for

default amplitude setting with driver not toggling;

the peak-to-peak amplitude measured using a

differential probe across the differential pair with

the driver toggling is roughly 2× these values (see

Figure 25 for variation over frequency)

LVDS CLOCK OUTPUTS

OUT4, OUT5, OUT6, OUT7

Output Frequency

Differential termination 100 Ω at 3.5 mA

Differential (OUT, OUT)

800

454

25

MHz

mV

The AD9517 outputs toggle at higher frequencies,

but the output amplitude may not meet the V_OD

specification; see Figure 26

V_OH− V_OLmeasurement across a differential pair at

the default amplitude setting with output driver not

toggling; see Figure 26 for variation over frequency

Output Differential Voltage (V_OD)

Delta V_OD

247

360

mV

This is the absolute value of the difference between

V

_ODwhen the normal output is high vs. when the

complementary output is high

Output Offset Voltage (V_OS)

Delta V_OS

1.125

1.24

14

1.375

25

V

mV

(V_OH+ V_OL)/2 across a differential pair

This is the absolute value of the difference between

V

_OSwhen the normal output is high vs. when the

complementary output is high

Output shorted to GND

Short-Circuit Current (I_SA, I_SB)

24

mA

Rev. F | Page 6 of 80

Data Sheet

AD9517-2

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CMOS CLOCK OUTPUTS

OUT4A, OUT4B, OUT5A, OUT5B,

OUT6A, OUT6B, OUT7A, OUT7B

Output Frequency

Output Voltage

High (V_OH)

Low (V_OL)

Single-ended; termination = 10 pF

See Figure 27

250

0.1

MHz

V_S− 0.1

V

At 1 mA load

Source Current

Static

Dynamic

Exceeding these values can result in damage to the part

20

16

mA

Sink Current

Static

Dynamic

Exceeding these values can result in damage to the part

8

16

mA

Rev. F | Page 7 of 80

AD9517-2

Data Sheet

TIMING CHARACTERISTICS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL

Output Rise Time, t_RP

Output Fall Time, t_FP

Termination = 50 Ω to V_S− 2 V; level = 810 mV

20ꢀ to 80ꢀ, measured differentially

80ꢀ to 20ꢀ, measured differentially

70

180

ps

PROPAGATION DELAY, t_PECL, CLK-TO-LVPECL OUTPUT

High Frequency Clock Distribution Configuration

Clock Distribution Configuration

Variation with Temperature

OUTPUT SKEW, LVPECL OUTPUTS¹

LVPECL Outputs That Share the Same Divider

LVPECL Outputs on Different Dividers

All LVPECL Outputs Across Multiple Parts

LVDS

835

773

995

933

0.8

1180 ps

1090 ps

See Figure 43

See Figure 45

ps/°C

5

13

15

ps

40

220

ps

Termination = 100 Ω differential; 3.5 mA

20ꢀ to 80ꢀ, measured differentially²

Delay off on all outputs

Output Rise Time, t_RL

Output Fall Time, t_FL

170

160

350

ps

PROPAGATION DELAY, t_LVDS, CLK-TO-LVDS OUTPUT

For All Divide Values

1.4

1.8

2.1

ns

Variation with Temperature

OUTPUT SKEW, LVDS OUTPUTS¹

LVDS Outputs That Share the Same Divider

LVDS Outputs on Different Dividers

All LVDS Outputs Across Multiple Parts

CMOS

1.25

ps/°C

Delay off on all outputs

6

25

62

150

430

ps

Termination = open

20ꢀ to 80ꢀ; C_LOAD= 10 pF

80ꢀ to 20ꢀ; C_LOAD= 10 pF

Fine delay off

Output Rise Time, t_RC

Output Fall Time, t_FC

495

475

1000 ps

985

ps

PROPAGATION DELAY, t_CMOS, CLK-TO-CMOS OUTPUT

For All Divide Values

1.6

2.1

2.6

ns

ps/°C

Variation with Temperature

OUTPUT SKEW, CMOS OUTPUTS¹

CMOS Outputs That Share the Same Divider

All CMOS Outputs on Different Dividers

All CMOS Outputs Across Multiple Parts

DELAY ADJUST³

Shortest Delay Range⁴

Zero Scale

Full Scale

Longest Delay Range⁴

Fine delay off

4

28

66

180

675

ps

LVDS and CMOS

Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 101111b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

Register 0x0A1 (0x0A4, 0x0A7, 0x0AA), Bits[5:0] = 000000b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 000000b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 001100b

Register 0x0A2 (0x0A5, 0x0A8, 0x0AB), Bits[5:0] = 101111b

50

540

315

880

680

ps

1180 ps

Zero Scale

Quarter Scale

Full Scale

200

1.72

5.7

570

2.31

8.0

950

2.89

10.1

ps

ns

Delay Variation with Temperature

Short Delay Range⁵

Zero Scale

Full Scale

Long Delay Range⁵

0.23

−0.02

ps/°C

Zero Scale

Full Scale

0.3

0.24

ps/°C

¹This is the difference between any two similar delay paths while operating at the same voltage and temperature.

²Corresponding CMOS drivers set to A for noninverting and B for inverting.

³The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.

⁴Incremental delay; does not include propagation delay.

⁵All delays between zero scale and full scale can be estimated by linear interpolation.

Rev. F | Page 8 of 80

Data Sheet

AD9517-2

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

CLK = 1 GHz, Output = 1 GHz

Divider = 1

Distribution section only; does not include PLL and VCO

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

−109

−118

−130

−139

−144

−146

−147

−149

dBc/Hz

At 10 MHz Offset

At 100 MHz Offset

CLK = 1 GHz, Output = 200 MHz

Divider = 5

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−120

−126

−139

−150

−155

−157

dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE

CLK = 1.6 GHz, Output = 800 MHz

Divider = 2

Distribution section only; does not include PLL and VCO

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

−103

−110

−120

−127

−133

−138

−147

−149

dBc/Hz

At 10 MHz Offset

At 100 MHz Offset

CLK = 1.6 GHz, Output = 400 MHz

Divider = 4

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−114

−122

−132

−140

−146

−150

−155

dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE

CLK = 1 GHz, Output = 250 MHz

Divider = 4

Distribution section only; does not include PLL and VCO

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−110

−120

−127

−136

−144

−147

−154

dBc/Hz

Rev. F | Page 9 of 80

AD9517-2

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK = 1 GHz, Output = 50 MHz

Divider = 20

Input slew rate > 1 V/ns

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

−124

−134

−142

−151

−157

−160

−163

dBc/Hz

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL ABSOLUTE PHASE NOISE

VCO = 2.335 GHz; Output = 2.335 GHz

At 1 kHz Offset

Internal VCO; direct to LVPECL output

−46

−78

−105

−124

−141

−146

dBc/Hz

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

At 10 MHz Offset

At 40 MHz Offset

VCO = 2.175 GHz; Output = 2.175 GHz

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

−51

−80

−107

−124

−142

−146

dBc/Hz

At 10 MHz Offset

At 40 MHz Offset

VCO = 2.05 GHz; Output = 2.05 GHz

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

−53

−82

−108

−127

−142

−147

dBc/Hz

At 10 MHz Offset

At 40 MHz Offset

Rev. F | Page 10 of 80

Data Sheet

AD9517-2

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

Table 8.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical

setup where the reference source is clean,

so a wider PLL loop bandwidth is used;

reference = 15.36 MHz; R = 1

VCO = 2.21 GHz; LVPECL = 245.76 MHz; PLL LBW = 138 kHz

VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 138 kHz

VCO = 2.21 GHz; LVPECL = 61.44 MHz; PLL LBW = 138 kHz

146

329

151

329

203

376

fs rms Integration BW = 200 kHz to 10 MHz

fs rms Integration BW = 12 kHz to 20 MHz

fs rms Integration BW = 200 kHz to 10 MHz

fs rms Integration BW = 12 kHz to 20 MHz

fs rms Integration BW = 200 kHz to 10 MHz

fs rms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

Table 9.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical

setup where the reference source is jittery,

so a narrower PLL loop bandwidth is used;

reference = 10.0 MHz; R = 20

VCO = 2.18 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz

VCO = 2.21 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz

515

570

fs rms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 10.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical

setup using an external 245.76 MHz VCXO

(Toyocom TCO-2112); reference = 15.36 MHz;

R = 1

LVPECL = 245.76 MHz; PLL LBW = 125 Hz

LVPECL = 122.88 MHz; PLL LBW = 125 Hz

LVPECL = 61.44 MHz; PLL LBW = 125 Hz

54

77

109

79

114

163

124

176

259

fs rms Integration BW = 200 kHz to 5 MHz

fs rms Integration BW = 200 kHz to 10 MHz

fs rms Integration BW = 12 kHz to 20 MHz

fs rms Integration BW = 200 kHz to 5 MHz

fs rms Integration BW = 200 kHz to 10 MHz

fs rms Integration BW = 12 kHz to 20 MHz

fs rms Integration BW = 200 kHz to 5 MHz

fs rms Integration BW = 200 kHz to 10 MHz

fs rms Integration BW = 12 kHz to 20 MHz

Rev. F | Page 11 of 80

AD9517-2

Data Sheet

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 11.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include

PLL and VCO; uses rising edge of clock signal

CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1

CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4

CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16

40

80

215

fs rms BW = 12 kHz to 20 MHz

fs rms Calculated from SNR of ADC method;

DCC not used for even divides

CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5

LVDS OUTPUT ADDITIVE TIME JITTER

245

fs rms Calculated from SNR of ADC method; DCC on

Distribution section only; does not include

PLL and VCO; uses rising edge of clock signal

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;

VCO Divider Not Used

85

fs rms BW = 12 kHz to 20 MHz

CLK = 1 GHz; LVDS = 200 MHz; Divider = 5

CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16

113

280

fs rms BW = 12 kHz to 20 MHz

fs rms Calculated from SNR of ADC method;

DCC not used for even divides

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include

PLL and VCO; uses rising edge of clock signal

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16

365

fs rms Calculated from SNR of ADC method;

DCC not used for even divides

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 12.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include

PLL and VCO; uses rising edge of clock signal

CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210

285

350

fs rms Calculated from SNR of ADC method

LVDS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include

PLL and VCO; uses rising edge of clock signal

fs rms Calculated from SNR of ADC method

CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include

PLL and VCO; uses rising edge of clock signal

fs rms Calculated from SNR of ADC method

CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

Rev. F | Page 12 of 80

Data Sheet

AD9517-2

DELAY BLOCK ADDITIVE TIME JITTER

Table 13.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER¹

Incremental additive jitter

100 MHz Output

Delay (1600 μA, 0x1C) Fine Adj. 000000b

Delay (1600 μA, 0x1C) Fine Adj. 101111b

Delay (800 μA, 0x1C) Fine Adj. 000000b

Delay (800 μA, 0x1C) Fine Adj. 101111b

Delay (800 μA, 0x4C) Fine Adj. 000000b

Delay (800 μA, 0x4C) Fine Adj. 101111b

Delay (400 μA, 0x4C) Fine Adj. 000000b

Delay (400 μA, 0x4C) Fine Adj. 101111b

Delay (200 μA, 0x1C) Fine Adj. 000000b

Delay (200 μA, 0x1C) Fine Adj. 101111b

Delay (200 μA, 0x4C) Fine Adj. 000000b

Delay (200 μA, 0x4C) Fine Adj. 101111b

0.54

0.60

0.65

0.85

0.79

1.2

2.0

1.3

2.5

ps rms

1.9

3.8

¹This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

SERIAL CONTROL PORT

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 30 kΩ pull-up resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SCLK (INPUT)

2.0

V

μA

pF

0.8

3

110

2

SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

Output Logic 0 Voltage

TIMING

2.0

2.7

V

μA

pF

0.8

1

110

2

V

nA

pF

0.8

10

20

2

V

0.4

25

Clock Rate (SCLK, 1/t_SCLK

Pulse Width High, t_HIGH

Pulse Width Low, t_LOW

SDIO to SCLK Setup, t_DS

SCLK to SDIO Hold, t_DH

)

MHz

ns

16

2

1.1

SCLK to Valid SDIO and SDO, t_DV

CS to SCLK Setup and Hold, t_S, t_H

CS Minimum Pulse Width High, t_PWH

8

ns

2

3

ns

Rev. F | Page 13 of 80

AD9517-2

Data Sheet

PD, SYNC, AND RESET PINS

Table 15.

Parameter

Min Typ Max Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

These pins each have a 30 kΩ internal pull-up

resistor

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

Capacitance

2.0

V

μA

pF

0.8

1

110

2

RESET TIMING

Pulse Width Low

SYNC TIMING

50

ns

Pulse Width Low

1.5

High speed

clock cycles

High speed clock is CLK input signal

LD, STATUS, AND REFMON PINS

Table 16.

Parameter

Min Typ Max Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

When selected as a digital output (CMOS);

there are other modes in which these pins

are not CMOS digital outputs; see Table 54,

Register 0x017, Register 0x01A, and

Register 0x01B

Output Voltage High (V_OH)

Output Voltage Low (V_OL)

MAXIMUM TOGGLE RATE

2.7

V

0.4

100

MHz

Applies when mux is set to any divider or

counter output or PFD up/down pulse; also

applies in analog lock detect mode; usually

debug mode only; beware that spurs may

couple to output when any of these pins are

toggling

ANALOG LOCK DETECT

Capacitance

3

pF

On-chip capacitance; used to calculate RC

time constant for analog lock detect

readback; use a pull-up resistor

REF1, REF2, AND VCO FREQUENCY STATUS MONITOR

Normal Range

1.02

8

MHz

kHz

Frequency above which the monitor always

indicates the presence of the reference

Frequency above which the monitor always

indicates the presence of the reference

Extended Range (REF1 and REF2 Only)

LD PIN COMPARATOR

Trip Point

1.6

V

Hysteresis

260

mV

Rev. F | Page 14 of 80

Data Sheet

AD9517-2

POWER DISSIPATION

Table 17.

Parameter

Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION, CHIP

Power-On Default

1.0

1.4

1.2

2.0

W

No clock; no programming; default register values;

does not include power dissipated in external resistors

Full Operation; CMOS Outputs at 195 MHz

Full Operation; LVDS Outputs at 195 MHz

PLL on; internal VCO = 2335 MHz; VCO divider = 2;

all channel dividers on; six LVPECL outputs at 584 MHz;

eight CMOS outputs (10 pF load) t 195 MHz; all fine delay on,

maximum current; does not include power dissipated

in external resistors

PLL on; internal VCO = 2335 MHz, VCO divider = 2; all channel

dividers on; six LVPECL outputs at 584 MHz; four LVDS outputs

at 195 MHz; all fine delay on, maximum current; does not

include power dissipated in external resistors

1.4

2.1

W

PD Power-Down

75

31

185

mW PD pin pulled low; does not include power dissipated

in terminations

mW PD pin pulled low; PLL power-down Register 0x010[1:0] = 01b;

SYNC power-down, Register 0x230[2] = 1b; REF for distribution

power-down, Register 0x230[1] = 1b

PD Power-Down, Maximum Sleep

V_CPSupply

4

4.8

mW PLL operating; typical closed-loop configuration

Power delta when a function is enabled/disabled

mW VCO divider bypassed

mW All references off to differential reference enabled

mW All references off to REF1 or REF2 enabled; differential

reference not enabled

POWER DELTAS, INDIVIDUAL FUNCTIONS

VCO Divider

REFIN (Differential)

30

20

4

REF1, REF2 (Single-Ended)

VCO

70

mW CLK input selected to VCO selected

PLL

75

30

mW PLL off to PLL on, normal operation; no reference enabled

mW Divider bypassed to divide-by-2 to divide-by-32

Channel Divider

LVPECL Channel (Divider Plus Output Driver)

160

mW No LVPECL output on to one LVPECL output on,

independent of frequency

LVPECL Driver

90

mW Second LVPECL output turned on, same channel

LVDS Channel (Divider Plus Output Driver)

120

mW No LVDS output on to one LVDS output on; see Figure 8 for

dependence on output frequency

LVDS Driver

50

mW Second LVDS output turned on, same channel

CMOS Channel (Divider Plus Output Driver)

100

mW Static; no CMOS output on to one CMOS output on; see

Figure 9 for variation over output frequency

CMOS Driver (Second in Pair)

CMOS Driver (First in Second Pair)

Fine Delay Block

0

30

50

mW Static; second CMOS output, same pair, turned on

mW Static; first output, second pair, turned on

mW Delay block off to delay block enabled; maximum current

setting

Rev. F | Page 15 of 80

AD9517-2

Data Sheet

TIMING DIAGRAMS

t_CLK

CLK

DIFFERENTIAL

80%

t_PECL

LVDS

t_LVDS

20%

t_RL

t_FL

t_CMOS

CLK

Figure 2. CLK/

to Clock Output Timing, DIV = 1

Figure 4. LVDS Timing, Differential

DIFFERENTIAL

80%

SINGLE-ENDED

80%

LVPECL

CMOS

10pF LOAD

20%

t_RP

t_FP

t_RC

t_FC

Figure 3. LVPECL Timing, Differential

Figure 5. CMOS Timing, Single-Ended, 10 pF Load

Rev. F | Page 16 of 80

Data Sheet

AD9517-2

ABSOLUTE MAXIMUM RATINGS

Table 18.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

VS, VS_LVPECL to GND

VCP to GND

REFIN, REFIN to GND

REFIN to REFIN

−0.3 V to +3.6 V

−0.3 V to +5.8 V

−0.3 V to V_S+ 0.3 V

−3.3 V to +3.3 V

−0.3 V to V_S+ 0.3 V

−1.2 V to +1.2 V

−0.3 V to V_S+ 0.3 V

RSET to GND

CPRSET to GND

CLK, CLK to GND

CLK to CLK

THERMAL RESISTANCE

Table 19.

Package Type¹

θ_JA

Unit

SCLK, SDIO, SDO, CS to GND

48-Lead LFCSP

24.7

°C/W

OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, −0.3 V to V_S+ 0.3 V

OUT3, OUT3,OUT4, OUT4, OUT5, OUT5,

OUT6, OUT6, OUT7, OUT7 to GND

¹Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-2.

SYNC to GND

−0.3 V to V_S+ 0.3 V

150°C

−65°C to +150°C

300°C

REFMON, STATUS, LD to GND

Junction Temperature¹

Storage Temperature Range

Lead Temperature (10 sec)

ESD CAUTION

¹See Table 19 for θ_JA

.

Rev. F | Page 17 of 80

AD9517-2

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFMON

LD

36

1

2

35 OUT4 (OUT4A)

VCP

34

33

OUT4 (OUT4B)

OUT5 (OUT5A)

3

4

CP

STATUS

REF_SEL

SYNC

LF

5

32 OUT5 (OUT5B)

31 VS

AD9517-2

6

TOP VIEW

7

30

29

28

27

26

25

VS

(Not to Scale)

8

OUT7 (OUT7B)

OUT7 (OUT7A)

OUT6 (OUT6B)

OUT6 (OUT6A)

9

BYPASS

VS

10

11

12

CLK

NOTES

1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE

CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 6. Pin Configuration

Table 20. Pin Function Descriptions

Input/

Output Pin Type

Pin No.

Mnemonic

Description

1

I

3.3 V CMOS REFMON

Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,

Register 0x01B.

2

3

O

I

3.3 V CMOS LD

Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,

Register 0x01A.

Power Supply for Charge Pump (CP); V_S≤ V_CP≤ 5.0 V. This pin is usually 3.3 V for

most applications; but if a 5 V external VCXO is used, this pin should be 5 V.

Power

VCP

4

5

6

O

I

3.3 V CMOS CP

3.3 V CMOS STATUS

3.3 V CMOS REF_SEL

Charge Pump (Output). Connects to external loop filter.

Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.

Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ

pull-down resistor.

7

8

9

I

3.3 V CMOS SYNC

Manual Synchronizations and Manual Holdover. This pin initiates a manual

synchronization and is also used for manual holdover. Active low. This pin has an

internal 30 kΩ pull-up resistor.

Loop Filter (Input). Connects to VCO control voltage node internally. This pin has

31 pF of internal capacitance to ground, which may influence the loop filter design

for large loop bandwidths.

Loop filter

LF

O

I

Loop filter

Power

BYPASS

VS

This pin is for bypassing the LDO to ground with a capacitor.

3.3 V Power Pins.

10, 24, 25,

30, 31, 36,

37, 43, 45

11

I

Differential

clock input

CLK

Along with CLK, this is the self-biased differential input for the clock distribution

section. This pin can be left floating if internal VCO is used.

Along with CLK, this is the self-biased differential input for the clock distribution

section. This pin can be left floating if internal VCO is used.

12

Differential

clock input

13

14

I

3.3 V CMOS SCLK

3.3 V CMOS CS

Serial Control Port Data Clock Signal.

Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up

resistor.

Rev. F | Page 18 of 80

Data Sheet

AD9517-2

Input/

Output Pin Type

Pin No.

15

16

Mnemonic

3.3 V CMOS SDO

3.3 V CMOS SDIO

Description

O

I/O

Serial Control Port. Unidirectional serial data output.

Serial Control Port. Bidirectional serial data input/output and unidirectional serial

data input.

17

I

3.3 V CMOS RESET

3.3 V CMOS PD

Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.

Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.

Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.

18

I

21, 40

42

41

I

Power

VS_LVPECL

O

LVPECL

OUT0

LVPECL Output; One Side of a Differential LVPECL Output.

39

38

OUT1

19

20

OUT2

22

23

OUT3

35

LVDS or

CMOS

OUT4 (OUT4A)

LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

34

O

I

LVDS or

CMOS

LVDS or

CMOS

LVDS or

CMOS

LVDS or

CMOS

LVDS or

CMOS

LVDS or

CMOS

LVDS or

CMOS

Current set

resistor

OUT4 (OUT4B)

OUT5 (OUT5A)

OUT5 (OUT5B)

OUT6 (OUT6A)

OUT6 (OUT6B)

OUT7 (OUT7A)

OUT7 (OUT7B)

RSET

LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

LVDS/CMOS Output; One Side of a Differential LVDS Output

or a Single-Ended CMOS Output.

Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ.

33

32

26

27

28

29

44

46

Current set

resistor

Reference

input

Reference

input

CPRSET

Resistor connected here sets CP current range. Nominal value = 5.1 kΩ.

47

REFIN (REF2)

REFIN (REF1)

GND

Along with REFIN, this is the self-biased differential input for the PLL reference.

Alternatively, this pin is a single-ended input for REF2.

Along with REFIN, this is the self-biased differential input for the PLL reference.

Alternatively, this pin is a single-ended input for REF1.

Ground. The external paddle on the bottom of the package must be connected to

ground for proper operation.

48

I

EPAD

GND

Rev. F | Page 19 of 80

AD9517-2

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

240

48

46

44

42

40

38

36

34

32

30

2 CHANNELS—4 LVPECL

220

200

180

2 CHANNELS—2 LVPECL

160

140

1 CHANNEL—1 LVPECL

120

100

0

500

1000

1500

2000

2500

3000

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

FREQUENCY (MHz)

VCO FREQUENCY (GHz)

Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs

Figure 10. VCO K_VCOvs. Frequency

180

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2 CHANNELS—4 LVDS

160

PUMP DOWN

PUMP UP

140

2 CHANNELS—2 LVDS

120

100

1 CHANNEL—1 LVDS

80

0

200

400

600

800

0

0.5

1.0

1.5

2.0

2.5

3.0

FREQUENCY (MHz)

VOLTAGE ON CP PIN (V)

Figure 8. Current vs. Frequency—LVDS Outputs

(Includes Clock Distribution Current Draw)

Figure 11. Charge Pump Characteristics at VCP = 3.3 V

240

220

200

180

160

140

120

100

80

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2 CHANNELS—8 CMOS

2 CHANNELS—2 CMOS

PUMP DOWN

PUMP UP

1 CHANNEL—2 CMOS

1 CHANNEL—1 CMOS

0

50

100

150

200

250

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

FREQUENCY (MHz)

VOLTAGE ON CP PIN (V)

Figure 9. Current vs. Frequency—CMOS Outputs

Figure 12. Charge Pump Characteristics at VCP = 5.0 V

Rev. F | Page 20 of 80

Data Sheet

AD9517-2

10

0

–140

–145

–150

–155

–160

–165

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–170

0.1

CENTER 122.88MHz

5MHz/DIV

SPAN 50MHz

1

10

100

PFD FREQUENCY (MHz)

Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;

LBW = 138 kHz; I_CP= 3.0 mA; f_VCO= 2.21 GHz

Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

10

–210

–212

–214

–216

–218

–220

–222

–224

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

CENTER 122.88MHz

100kHz/DIV

SPAN 1MHz

0

0.5

1.0

1.5

2.0

2.5

SLEW RATE (V/ns)

Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;

LBW = 138 kHz; I_CP= 3.0 mA; f_VCO= 2.21 GHz

REFIN

Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/

10

0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

CENTER 122.88MHz

100kHz/DIV

SPAN 1MHz

2.0

2.1

2.2

2.3

2.4

FREQUENCY (GHz)

Figure 15. VCO Tuning Voltage vs. Frequency

(Note that VCO calibration centers the dc tuning voltage

for the PLL setup that is active during calibration.)

Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;

LBW = 138 kHz; I_CP= 3.0 mA; f_VCO= 2.21 GHz

Rev. F | Page 21 of 80

AD9517-2

Data Sheet

1.0

0.4

0.2

0.6

0.2

0

–0.2

–0.6

–0.2

–0.4

–1.0

0

5

10

15

20

25

0

1

2

TIME (ns)

Figure 19. LVPECL Output (Differential) at 100 MHz

Figure 22. LVDS Output (Differential) at 800 MHz

1.0

0.6

2.8

1.8

0.2

–0.2

–0.6

–1.0

0.8

–0.2

0

20

40

60

80

100

0

1

2

TIME (ns)

Figure 20. LVPECL Output (Differential) at 1600 MHz

Figure 23. CMOS Output at 25 MHz

0.4

0.2

2.8

1.8

0

0.8

–0.2

–0.4

–0.2

0

2

4

6

8

10

12

0

5

10

15

20

25

TIME (ns)

Figure 21. LVDS Output (Differential) at 100 MHz

Figure 24. CMOS Output at 250 MHz

Rev. F | Page 22 of 80

Data Sheet

AD9517-2

1600

–70

–80

1400

1200

1000

–90

–100

–110

–120

–130

–140

–150

800

0

1

2

3

10k

100k

1M

10M

100M

FREQUENCY (GHz)

FREQUENCY (Hz)

Figure 25. LVPECL Differential Swing vs. Frequency

Using a Differential Probe Across the Output Pair

Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2335 MHz

–80

–90

700

600

500

–100

–110

–120

–130

–140

–150

0

100

200

300

400

500

600

700

800

10k

100k

1M

10M

100M

FREQUENCY (MHz)

FREQUENCY (Hz)

Figure 26. LVDS Differential Swing vs. Frequency

Using a Differential Probe Across the Output Pair

Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2175 MHz

–80

–90

C

= 2pF

L

3

2

1

0

C

= 10pF

–100

–110

–120

–130

–140

–150

L

C

= 20pF

L

0

100

200

300

400

500

600

10k

100k

1M

10M

100M

OUTPUT FREQUENCY (MHz)

FREQUENCY (Hz)

Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2050 MHz

Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load

Rev. F | Page 23 of 80

AD9517-2

Data Sheet

–120

–125

–130

–135

–140

–145

–150

–155

–160

–110

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 31. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1

Figure 34. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1

–100

–110

–120

–130

–140

–150

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 35. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2

Figure 32. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5

–120

–100

–130

–140

–150

–160

–170

–110

–120

–130

–140

–150

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 36. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20

Figure 33. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1

Rev. F | Page 24 of 80

Data Sheet

AD9517-2

–100

–110

–120

–130

–140

–150

–160

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4

Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) at

245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

1000

–110

OC-48 OBJECTIVE MASK

AD9517

–120

–130

–140

–150

–160

100

f

OBJ

10

1

NOTE: 375UI MAX AT 10Hz OFFSET IS THE

MAXIMUM JITTER THAT CAN BE

GENERATED BY THE TEST EQUIPMENT.

FAILURE POINT IS GREATER THAN 375UI.

0.1

0.01

0.1

1

10

100

1000

1k

10k

100k

1M

10M

100M

JITTER FREQUENCY (kHz)

FREQUENCY (Hz)

Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO at

2.21 GHz; PFD = 15.36 MHz; LBW = 138 kHz; LVPECL Output = 122.88 MHz

Figure 41. GR-253 Jitter Tolerance Plot

–80

–90

–100

–110

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 2.18 GHz;

PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz

Rev. F | Page 25 of 80

AD9517-2

Data Sheet

TERMINOLOGY

Time Jitter

Phase Jitter and Phase Noise

Phase noise is a frequency domain phenomenon. In the time

domain, the same effect is exhibited as time jitter. When

observing a sine wave, the time of successive zero crossings

varies. In a square wave, the time jitter is a displacement of the

edges from their ideal (regular) times of occurrence. In both

cases, the variations in timing from the ideal are the time jitter.

Because these variations are random in nature, the time jitter is

specified in units of seconds root mean square (rms) or 1 sigma

of the Gaussian distribution.

An ideal sine wave can be thought of as having a continuous

and even progression of phase with time from 0° to 360° for

each cycle. Actual signals, however, display a certain amount

of variation from ideal phase progression over time. This

phenomenon is called phase jitter. Although many causes can

contribute to phase jitter, one major cause is random noise,

which is characterized statistically as being Gaussian (normal)

in distribution.

This phase jitter leads to a spreading out of the energy of the

sine wave in the frequency domain, producing a continuous

power spectrum. This power spectrum is usually reported as

a series of values whose units are dBc/Hz at a given offset in

frequency from the sine wave (carrier). The value is a ratio

(expressed in dB) of the power contained within a 1 Hz

bandwidth with respect to the power at the carrier frequency.

For each measurement, the offset from the carrier frequency

is also given.

Time jitter that occurs on a sampling clock for a DAC or an

ADC decreases the signal-to-noise ratio (SNR) and dynamic

range of the converter. A sampling clock with the lowest possible

jitter provides the highest performance from a given converter.

Additive Phase Noise

Additive phase noise is the amount of phase noise that can

be attributed to the device or subsystem being measured. The

phase noise of any external oscillators or clock sources is

subtracted. This makes it possible to predict the degree to

which the device impacts the total system phase noise when

used in conjunction with the various oscillators and clock

sources, each of which contributes its own phase noise to the

total. In many cases, the phase noise of one element dominates

the system phase noise. When there are multiple contributors

to phase noise, the total is the square root of the sum of squares

of the individual contributors.

It is meaningful to integrate the total power contained within

some interval of offset frequencies (for example, 10 kHz to

10 MHz). This is called the integrated phase noise over that

frequency offset interval and can be readily related to the time

jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of

ADCs, DACs, and RF mixers. It lowers the achievable dynamic

range of the converters and mixers, although they are affected

in somewhat different ways.

Additive Time Jitter

Additive time jitter is the amount of time jitter that can

be attributed to the device or subsystem being measured. The

time jitter of any external oscillators or clock sources is subtracted.

This makes it possible to predict the degree to which the device

impacts the total system time jitter when used in conjunction with

the various oscillators and clock sources, each of which contributes

its own time jitter to the total. In many cases, the time jitter of

the external oscillators and clock sources dominates the system

time jitter.

Rev. F | Page 26 of 80

Data Sheet

AD9517-2

DETAILED BLOCK DIAGRAM

REF_ SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

VCO

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4 (OUT4A)

OUT4 (OUT4B)

ΔT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT5 (OUT5A)

OUT5 (OUT5B)

ΔT

OUT6 (OUT6A)

OUT6 (OUT6B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

ΔT

AD9517-2

Figure 42. Detailed Block Diagram

Rev. F | Page 27 of 80

AD9517-2

Data Sheet

THEORY OF OPERATION

Table 21. Default Settings of Some PLL Registers

OPERATIONAL CONFIGURATIONS

Register

Function

The AD9517 can be configured in several ways. These

configurations must be set up by loading the control registers

(see Table 52 and Table 53 through Table 62). Each section or

function must be individually programmed by setting the

appropriate bits in the corresponding control register or registers.

0x010[1:0] = 01b

0x1E0[2:0] = 010b

0x1E1[0] = 0b

0x1E1[1] = 0b

PLL asynchronous power-down (PLL off).

Set VCO divider = 4.

Use the VCO divider.

CLK selected as the source.

High Frequency Clock Distribution—CLK or External

VCO > 1600 MHz

When using the internal PLL with an external VCO, the PLL

must be turned on.

The AD9517 power-up default configuration has the PLL

powered off and the routing of the input set so that the

Table 22. Settings When Using an External VCO

Register

Function

CLK

CLK/

input is connected to the distribution section

0x010[1:0] = 00b

0x010 to 0x01D

PLL normal operation (PLL on).

through the VCO divider (divide-by-2/divide-by-3/divide-by-4/

divide-by-5/divide-by-6). This is a distribution only mode that

allows for an external input up to 2400 MHz (see Table 3). The

maximum frequency that can be applied to the channel dividers

is 1600 MHz; therefore, higher input frequencies must be divided

down before reaching the channel dividers. This input routing

can also be used for lower input frequencies, but the minimum

divide is 2 before the channel dividers.

PLL settings. Select and enable a reference

input; set R, N (P, A, B), PFD polarity, and I_CP,

according to the intended loop configuration.

0x1E1[1] = 0b

CLK selected as the source.

An external VCO requires an external loop filter that must be

connected between CP and the tuning pin of the VCO. This

loop filter determines the loop bandwidth and stability of the

PLL. Make sure to select the proper PFD polarity for the VCO

being used.

When the PLL is enabled, this routing also allows the use of the

PLL with an external VCO or VCXO with a frequency of less

than 2400 MHz. In this configuration, the internal VCO is not

used and is powered off. The external VCO/VCXO feeds

directly into the prescaler.

Table 23. Setting the PFD Polarity

Register

Function

0x010[7] = 0b

PFD polarity positive (higher control voltage

produces higher frequency).

The register settings shown in Table 21 are the default values of

these registers at power-up or after a reset operation. If the

contents of the registers are altered by prior programming after

power-up or reset, these registers can also be set intentionally to

these values.

0x010[7] = 1b

PFD polarity negative (higher control

voltage produces lower frequency).

After the appropriate register values are programmed,

Register 0x232 must be set to 0x01 for the values to take effect.

Rev. F | Page 28 of 80

Data Sheet

AD9517-2

REF_ SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

VCO

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4 (OUT4A)

OUT4 (OUT4B)

ΔT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT5 (OUT5A)

OUT5 (OUT5B)

ΔT

OUT6 (OUT6A)

OUT6 (OUT6B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

ΔT

AD9517-2

Figure 43. High Frequency Clock Distribution or External VCO > 1600 MHz

Rev. F | Page 29 of 80

AD9517-2

Data Sheet

REF_ SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

VCO

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4 (OUT4A)

OUT4 (OUT4B)

ΔT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT5 (OUT5A)

OUT5 (OUT5B)

ΔT

OUT6 (OUT6A)

OUT6 (OUT6B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

ΔT

AD9517-2

Figure 44. Internal VCO and Clock Distribution

Internal VCO and Clock Distribution

Table 24. Settings When Using Internal VCO

Register

Function

When using the internal VCO and PLL, the VCO divider must

be employed to ensure that the frequency presented to the channel

dividers does not exceed their specified maximum frequency of

1600 MHz (see Table 3). The internal PLL uses an external loop

filter to set the loop bandwidth. The external loop filter is also

crucial to the loop stability.

0x010[1:0] = 00b

0x010 to 0x01D

PLL normal operation (PLL on).

PLL settings. Select and enable a reference

input; set R, N (P, A, B), PFD polarity, and I_CP

according to the intended loop configuration.

Reset VCO calibration. This is not required

the first time after power-up, but it must be

performed subsequently.

Set VCO divider to divide-by-2, divide-by-3,

divide-by-4, divide-by-5, and divide-by-6.

Use the VCO divider as the source for the

distribution section.

0x018[0] = 0b,

0x232[0] = 1b

When using the internal VCO, it is necessary to calibrate the

VCO (Register 0x018[0]) to ensure optimal performance.

0x1E0[2:0]

For internal VCO and clock distribution applications, use the

register settings that are shown in Table 24.

0x1E1[0] = 0b

0x1E1[1] = 1b

0x018[0] = 1b,

0x232[0] = 1b

Select VCO as the source.

Initiate VCO calibration.

Rev. F | Page 30 of 80

Data Sheet

AD9517-2

REF_ SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

VCO

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4 (OUT4A)

OUT4 (OUT4B)

ΔT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT5 (OUT5A)

OUT5 (OUT5B)

ΔT

OUT6 (OUT6A)

OUT6 (OUT6B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

ΔT

AD9517-2

Figure 45. Clock Distribution or External VCO < 1600 MHz

Rev. F | Page 31 of 80

AD9517-2

Data Sheet

Clock Distribution or External VCO < 1600 MHz

When using the internal PLL with an external VCO of

When the external clock source to be distributed or the external

VCO/VCXO is less than 1600 MHz, a configuration that bypasses

the VCO divider can be used. This configuration differs from the

High Frequency Clock Distribution—CLK or External VCO >

1600 MHz section only in that the VCO divider (divide-by-2,

divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed.

This limits the frequency of the clock source to <1600 MHz (due to

the maximum input frequency allowed at the channel dividers).

<1600 MHz, the PLL must be turned on.

Table 26. Settings for Using Internal PLL with External VCO <

1600 MHz

Register

Function

0x1E1[0] = 1b

Bypass the VCO divider as source for

distribution section

0x010[1:0] = 00b PLL normal operation (PLL on), along with

other appropriate PLL settings in Register 0x010

to Register 0x01D

Configuration and Register Settings

For clock distribution applications where the external clock is

<1600 MHz, use the register settings that are shown in Table 25.

An external VCO/VCXO requires an external loop filter that

must be connected between CP and the tuning pin of the

VCO/VCXO. This loop filter determines the loop bandwidth

and stability of the PLL. Make sure to select the proper PFD

polarity for the VCO/VCXO being used.

Table 25. Settings for Clock Distribution <1600 MHz

Register

Function

0x010[1:0] = 01b

0x1E1[0] = 1b

PLL asynchronous power-down (PLL off)

Bypass the VCO divider as source for

distribution section

Table 27. Setting the PFD Polarity

Register

Function

0x1E1[1] = 0b

CLK selected as the source

0x010[7] = 0b

PFD polarity positive (higher control voltage

produces higher frequency)

0x010[7] = 1b

PFD polarity negative (higher control

voltage produces lower frequency)

After the appropriate register values are programmed,

Register 0x232 must be set to 0x01 for the values to take effect.

Rev. F | Page 32 of 80

Data Sheet

AD9517-2

Phase-Locked Loop (PLL)

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DIST

REF

REFERENCE

SWITCHOVER

LD

LOCK

DETECT

REF1

REF2

STATUS

PROGRAMMABLE

R DELAY

HOLD

R DIVIDER

PLL

REF

REFIN (REF1)

REFIN (REF2)

PHASE

CHARGE PUMP

FREQUENCY

DETECTOR

CP

N DIVIDER

P, P + 1

LOW DROPOUT

REGULATOR (LDO)

BYPASS

A/B

PROGRAMMABLE

N DELAY

PRESCALER

COUNTERS

VCO STATUS

LF

STATUS

VCO

DIVIDE BY

2, 3, 4, 5, OR 6

0

1

CLK

1

0

Figure 46. PLL Functional Blocks

The AD9517 includes an on-chip PLL with an on-chip VCO.

The PLL blocks can be used either with the on-chip VCO to

create a complete phase-locked loop or with an external VCO

or VCXO. The PLL requires an external loop filter, which

usually consists of a small number of capacitors and resistors.

The configuration and components of the loop filter help to

establish the loop bandwidth and stability of the operating PLL.

These are managed through programmable register settings

(see Table 52 and Table 54) and by the design of the external

loop filter. Successful PLL operation and satisfactory PLL loop

performance are highly dependent upon proper configuration

of the PLL settings. The design of the external loop filter is

crucial to the proper operation of the PLL. A thorough

knowledge of PLL theory and design is helpful.

The AD9517 PLL is useful for generating clock frequencies

from a supplied reference frequency. This includes conversion

of reference frequencies to much higher frequencies for subsequent

division and distribution. In addition, the PLL can be exploited to

clean up jitter and phase noise on a noisy reference. The exact

choices of PLL parameters and loop dynamics are very application

specific. The flexibility and depth of the AD9517 PLL allow the

part to be tailored to function in many different applications

and signal environments.

ADIsimCLK™ (V1.2 or later) is a free program that can help

with the design and exploration of the capabilities and features

of the AD9517, including the design of the PLL loop filter. It is

available at www.analog.com/clocks.

Phase Frequency Detector (PFD)

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. The PFD includes a programmable

delay element that controls the width of the antibacklash pulse.

This pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. The

antibacklash pulse width is set by Register 0x017[1:0].

Configuration of the PLL

The AD9517 allows flexible configuration of the PLL,

accommodating various reference frequencies, PFD

comparison frequencies, VCO frequencies, internal or external

VCO/VCXO, and loop dynamics. This is accomplished by the

various settings that include the R divider, the N divider, the

PFD polarity (only applicable to external VCO/VCXO), the

antibacklash pulse width, the charge pump current, the

selection of internal VCO or external VCO/VCXO, and the

loop bandwidth.

An important limit to keep in mind is the maximum frequency

allowed into the PFD, which in turn determines the correct

antibacklash pulse setting. The antibacklash pulse setting is

specified in the phase/frequency detector parameter of Table 2.

Rev. F | Page 33 of 80

AD9517-2

Data Sheet

When using an external VCO, the external loop filter should be

referenced to ground. See Figure 48 for an example of an external

loop filter for a PLL using an external VCO.

Charge Pump (CP)

The charge pump is controlled by the PFD. The PFD monitors

the phase and frequency relationship between its two inputs,

and tells the CP to pump up or pump down to charge or

discharge the integrating node (part of the loop filter). The

integrated and filtered CP current is transformed into a voltage

that drives the tuning node of the internal VCO through the LF

pin (or the tuning pin of an external VCO) to move the VCO

frequency up or down. The CP can be set (Register 0x010[6:4])

for high impedance (allows holdover operation), for normal

operation (attempts to lock the PLL loop), for pump up, or for

pump down (test modes). The CP current is programmable in

eight steps from (nominally) 600 μA to 4.8 mA. The exact value

of the CP current LSB is set by the CPRSET resistor, which is

nominally 5.1 kΩ. If the value of the resistor connected to the

CP_RSET pin is doubled, the resulting charge pump current

range becomes 300 μA to 2.4 mA.

AD9517-2

VCO

LF

31pF

R2

CP

R1

C2

CHARGE

PUMP

C1

C3

BYPASS

C

= 220nF

BP

Figure 47. Example of External Loop Filter for a PLL Using the Internal VCO

AD9517-2

EXTERNAL

VCO/VCXO

CLK/CLK

CP

On-Chip VCO

R2

R1

The AD9517 includes an on-chip VCO covering the frequency

range shown in Table 2. The calibration procedure ensures that

the VCO operating voltage is centered for the desired VCO

frequency. The VCO must be calibrated when the VCO loop

is first set up, as well as any time the nominal VCO frequency

changes. However, once the VCO is calibrated, the VCO has

sufficient operating range to stay locked over temperature and

voltage extremes without needing additional calibration. See

the VCO Calibration section for additional information.

CHARGE

PUMP

C1

C2

C3

Figure 48. Example of External Loop Filter for a PLL Using an External VCO

PLL Reference Inputs

The AD9517 features a flexible PLL reference input circuit that

allows either a fully differential input or two separate single-ended

inputs. The input frequency range for the reference inputs is

specified in Table 2. Both the differential and the single-ended

inputs are self-biased, allowing for easy ac coupling of input

signals.

The on-chip VCO is powered by an on-chip, low dropout

(LDO), linear voltage regulator. The LDO provides some

isolation of the VCO from variations in the power supply

voltage level. The BYPASS pin should be connected to ground

by a 220 nF capacitor to ensure stability. This LDO employs the

same technology used in the anyCAP® line of regulators from

Analog Devices, Inc., making it insensitive to the type of

capacitor used. Driving an external load from the BYPASS pin

is not supported.

The differential input and the single-ended inputs share the two

REFIN

pins, REFIN and

(REF1 and REF2, respectively). The

desired reference input type is selected and controlled by

Register 0x01C (see Table 52 and Table 54).

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly (~100 mV, see Table 2) to

prevent chattering of the input buffer when the reference is

slow or missing. This increases the voltage swing that is required

of the driver and overcomes the offset. The differential

reference input can be driven by either ac-coupled LVDS or ac-

coupled LVPECL signals.

Note that the reference input signal must be present and the

VCO divider must not be static during VCO calibration.

PLL External Loop Filter

When using the internal VCO, the external loop filter should

be referenced to the BYPASS pin for optimal noise and

spurious performance. An example of an external loop filter for

a PLL that uses the internal VCO is shown in Figure 47. The

third-order design shown in Figure 47 usually offers best

performance. A loop filter must be calculated for each desired PLL

configuration. The values of the components depend upon the

VCO frequency, the K_VCO, the PFD frequency, the CP current, the

desired loop bandwidth, and the desired phase margin. The loop

filter affects the phase noise, loop settling time, and loop stability.

A basic knowledge of PLL theory is helpful for understanding

loop filter design. ADIsimCLK can help with the calculation of a

loop filter according to the application requirements.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine-wave or square wave.

Each single-ended input can be independently powered down

when not needed to increase isolation and reduce power. Either

a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential reference input is powered down whenever the

PLL is powered down, or when the differential reference input

is not selected. The single-ended buffers power down when the

PLL is powered down, and when their individual power down

Rev. F | Page 34 of 80

Data Sheet

AD9517-2

registers are set. When the differential mode is selected, the

single-ended inputs are powered down.

Automatic revertive switchover relies on the REFMON pin to

indicate when REF1 disappears. By programming Register 0x01B =

0xF7 and Register 0x01C = 0x26, the REFMON pin is

programmed to be high when REF1 is invalid, which commands

the switch to REF2. When REF1 is valid again, the REFMON

pin goes low, and the part again locks to REF1. It is also possible to

use the STATUS pin for this function, and REF2 can be used as

the preferred reference.

In differential mode, the reference input pins are internally self-

biased so that they can be ac-coupled via capacitors. It is possible to

dc couple to these inputs. If the differential REFIN is driven by a

single-ended signal, the unused side (

) should be

REFIN

decoupled via a suitable capacitor to a quiet ground. Figure 49

shows the equivalent circuit of REFIN.

A switchover deglitch feature ensures that the PLL does not

receive rising edges that are far out of alignment with the newly

selected reference.

V

S

85kΩ

Automatic nonrevertive switching is not supported.

REF1

Reference Divider R

The reference inputs are routed to the reference divider, R.

R (a 14-bit counter) can be set to any value from 0 to 16383

by writing to Register 0x011 and Register 0x012. (Both R = 0 and

R = 1 give divide-by-1.) The output of the R divider goes to one

of the PFD inputs to be compared to the VCO frequency

divided by the N divider. The frequency applied to the PFD

must not exceed the maximum allowable frequency, which

depends on the antibacklash pulse setting (see Table 2).

V

S

10kΩ 12kΩ

150Ω

REFIN

150Ω

10kΩ 10kΩ

The R counter has its own reset. R counter can be reset using

the shared reset bit of the R, A, and B counters. It can also be

V

S

REF2

SYNC

reset by a

operation.

85kΩ

VCXO/VCO Feedback Divider N—P, A, B, R

The N divider is a combination of a prescaler (P) and two

counters, A and B. The total divider value is

N = (P × B) + A

Figure 49. REFIN Equivalent Circuit

where the value of P can be 2, 4, 8, 16, or 32.

Prescaler

Reference Switchover

The AD9517 supports dual single-ended CMOS inputs, as well

as a single differential reference input. In the dual single-ended

reference mode, the AD9517 supports automatic and manual

PLL reference clock switching between REF1 (on Pin REFIN)

The prescaler of the AD9517 allows for two modes of

operation: a fixed divide (FD) mode of 1, 2, or 3, and dual

modulus (DM) mode where the prescaler divides by P and (P +

1) {2 and 3, 4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The

prescaler modes of operation are given in Table 54, Register

0x016[2:0]. Not all modes are available at all frequencies (see

Table 2).

REFIN

and REF2 (on Pin

). This feature supports networking

and other applications that require smooth switching of redundant

references. When used in conjunction with the automatic holdover

function, the AD9517 can achieve a worst-case reference input

switchover with an output frequency disturbance as low as 10

ppm.

When operating the AD9517 in dual modulus mode (P//P + 1),

the equation used to relate input reference frequency to VCO

output frequency is

When using reference switchover, the single-ended reference

inputs should be dc-coupled CMOS levels and never be allowed

to go to high impedance. If these inputs are allowed to go to high

impedance, noise may cause the buffer to chatter, causing a

false detection of the presence of a reference.

f

_VCO= (f_REF/R) × (P × B + A) = f_REF× N/R

However, when operating the prescaler in an FD mode of 1,

2, or 3, the A counter is not used (A = 0) and the equation

simplifies to

Reference switchover can be performed manually or auto-

matically. Manual switchover is performed either through

Register 0x01C or by using the REF_SEL pin. Manual switchover

requires the presence of a clock on the reference input that is being

switched to, or that the deglitching feature be disabled (Register

0x01C[7]). The reference switching logic fails if this condition

is not met, and the PLL does not reacquire.

f

_VCO= (f_REF/R) × (P × B) = f_REF× N/R

When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,

in which case the previous equation also applies.

Rev. F | Page 35 of 80

AD9517-2

Data Sheet

By using combinations of the DM and FD modes, the AD9517

can achieve values of N all the way down to N = 1 and up to N

= 26,2175. Table 28 shows how a 10 MHz reference input can

be locked to any integer multiple of N.

CLK) divided by P. For example, a dual modulus mode of P = 8/9

is not allowed if the VCO frequency is greater than 2400 MHz

because the frequency going to the A/B counter is too high.

When the AD9517 B counter is bypassed (B = 1), the A counter

should be set to 0, and the overall resulting divide is equal to

the prescaler setting, P. The possible divide ratios in this mode

are 1, 2, 3, 4, 8, 16, and 32. This mode is useful only when an

external VCO/VCXO is used because the frequency range of

the internal VCO requires an overall feedback divider greater than

32.

Note that the same value of N can be derived in different ways,

as illustrated by the case of N = 12. The user can choose a fixed

divide mode of P = 2 with B = 6; use the dual modulus mode of

2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with

A = 0, B = 3.

The maximum frequency into the prescaler in 2/3 dual-modulus

mode is limited to 200 MHz. There are only two cases where this

frequency limitation limits the flexibility of that N divider: N =

7 and N = 11. In these two cases, the maximum frequency into

the prescaler is 300 MHz and is achieved by using the P = 1 FD

mode. In all other cases, the user can achieve the desired N

divider value by using the other prescaler modes.

Although manual reset is not normally required, the A/B counters

have their own reset bit. Alternatively, the A and B counters can be

reset using the shared reset bit of the R, A, and B counters. Note

that these reset bits are not self-clearing.

SYNC

R, A, and B Counters—

The R, A, and B counters can also be reset simultaneously through

SYNC

Pin Reset

A and B Counters

the

(see Table 54). The

R and N Divider Delays

pin. This function is controlled by Register 0x019[7:6]

The B counter must be ≥3 or bypassed, and, unlike the R counter,

A = 0 is actually zero.

SYNC

pin reset is disabled by default.

When the prescaler is in dual-modulus mode, the A counter

must be less than the B counter.

Both the R and N dividers feature a programmable delay cell.

These delays can be enabled to allow adjustment of the phase

relationship between the PLL reference clock and the VCO or

CLK. Each delay is controlled by three bits. The total delay

range is about 1 ns. See Register 0x019 in Table 54.

The maximum input frequency to the A/B counter is reflected

in the maximum prescaler output frequency (~300 MHz) that is

specified in Table 2. This is the prescaler input frequency (VCO or

Table 28. Using a 10 MHz Reference Input to Generate Different VCO Frequencies

f_REF

f_VCO

(MHz)

R

1

P

1

2

1

2

A

X

0

B

1

3

4

5

3

N

1

2

3

4

5

6

7

(MHz) Mode Comments/Conditions

10

20

30

40

50

60

70

FD

DM

P = 1, B = 1 (A and B counters are bypassed)

P = 2, B = 1 (A and B counters are bypassed)

A counter is bypassed

1

Maximum frequency into prescaler in P = 2/3 mode is 200 MHz.

If N = 7 or N = 11 is desired for prescaler input frequency of 200 MHz

to 300 MHz, use P = 1, and N = 7 or 11, respectively.

10

1

10

1

2

8

16

32

8

2

1

6

7

6

0

14

3

4

8

9

80

90

DM

18

9

47

25

16

150

151

1510

200

270

1500

1510

2000

2700

1

16

P = 8 is not allowed (2700 ÷ 8 > 300 MHz)

P = 32 is not allowed (A > B not allowed)

P = 32, A = 22, B = 84

10

32

22

84

2710

DM

P = 16 is also permitted

Rev. F | Page 36 of 80

Data Sheet

AD9517-2

when it is selected as the output from the LD pin control

(Register 0x01A[5:0]).

DIGITAL LOCK DETECT (DLD)

By selecting the proper output through the mux on each pin,

the DLD function can be made available at the LD, STATUS,

and REFMON pins. The DLD circuit indicates a lock when the

time difference of the rising edges at the PFD inputs is less than

a specified value (the lock threshold). The loss of a lock is

indicated when the time difference exceeds a specified value

(the unlock threshold). Note that the unlock threshold is wider

than the lock threshold, which allows some phase error in

excess of the lock window to occur without chattering on the

lock indicator.

The current source lock detect provides a current of 110 μA

when DLD is true, and it shorts to ground when DLD is false.

If a capacitor is connected to the LD pin, it charges at a rate that

is determined by the current source during the DLD true time

but is discharged nearly instantly when DLD is false. By

monitoring the voltage at the LD pin (top of the capacitor), it is

possible to get a logic high level only after the DLD has been

true for a sufficiently long time. Any momentary DLD false

resets the charging. By selecting a properly sized capacitor, it is

possible to delay a lock detect indication until the PLL is stably

locked and the lock detect does not chatter.

The lock detect window timing depends on three settings:

the digital lock detect window bit (Register 0x018[4]), the

antibacklash pulse width setting (Register 0x017[1:0], see Table 2),

and the lock detect counter (Register 0x018[6:5]). A lock is not

indicated until there is a programmable number of consecutive

PFD cycles with a time difference that is less than the lock detect

threshold. The lock detect circuit continues to indicate a lock

until a time difference greater than the unlock threshold occurs

on a single subsequent cycle. For the lock detect to work properly,

the period of the PFD frequency must be greater than the unlock

threshold. The number of consecutive PFD cycles required for lock

is programmable (Register 0x018[6:5]).

The voltage on the capacitor can be sensed by an external

comparator connected to the LD pin. However, there is an

internal LD pin comparator that can be read at the REFMON

pin control (Register 0x01B[4:0]) or the STATUS pin control

(Register 0x017[7:2]) as an active high signal. It is also available as

an active low signal (REFMON, Register 0x01B[4:0] and

STATUS, Register 0x017[7:2]). The internal LD pin comparator

trip point and hysteresis are listed in Table 16.

AD9517-2

110µA

Analog Lock Detect (ALD)

DLD

V

OUT

LD

The AD9517 provides an ALD function that can be selected for

use at the LD pin. There are two versions of ALD, as follows:

C



N-channel open-drain lock detect. This signal requires a

pull-up resistor to the positive supply, VS. The output is

normally high with short, low-going pulses. Lock is indicated

by the minimum duty cycle of the low-going pulses.

P-channel open-drain lock detect. This signal requires a

pull-down resistor to GND. The output is normally low

with short, high-going pulses. Lock is indicated by the

minimum duty cycle of the high-going pulses.

LD PIN

COMPARATOR

REFMON

OR

STATUS

Figure 51. Current Source Lock Detect



CLK

External VCXO/VCO Clock Input (CLK/

)

CLK is a differential input that can be used as an input to drive

the AD9517 clock distribution section. This input can receive

up to 2.4 GHz. The pins are internally self-biased, and the input

signal should be ac-coupled via capacitors.

The analog lock detect function requires an R-C filter to

provide a logic level indicating lock/unlock.

CLOCK INPUT

STAGE

V

= 3.3V

S

V

S

AD9517-2

R2

V

OUT

R1

LD

CLK

ALD

C

2.5kΩ

5kΩ

2.5kΩ

Figure 50. Example of Analog Lock Detect Filter

Using N-Channel Open-Drain Driver

5kΩ

Current Source Digital Lock Detect (DLD)

Figure 52. CLK Equivalent Input Circuit

During the PLL locking sequence, it is normal for the DLD

signal to toggle a number of times before remaining steady

when the PLL is completely locked and stable. There may be

applications where it is desirable to have DLD asserted only

after the PLL is solidly locked. This is made possible by using

the current source lock detect function. This function is set

CLK

The CLK/

input can be used either as a distribution-only

input (with the PLL off), or as a feedback input for an external

VCO/VCXO using the internal PLL when the internal VCO is

not used. The CLK/

to 2.4 GHz.

CLK

input can be used for frequencies up

Rev. F | Page 37 of 80

AD9517-2

Data Sheet

Holdover

Automatic/Internal Holdover Mode

The AD9517 PLL has a holdover function. Holdover is

implemented by putting the charge pump into a state of high

impedance. This is useful when the PLL reference clock is lost.

Holdover mode allows the VCO to maintain a relatively

constant frequency even though there is no reference clock.

Without this function, the charge pump is placed into a

constant pump-up or pump-down state, resulting in a massive

VCO frequency shift. Because the charge pump is placed in a

high impedance state, any leakage that occurs at the charge

pump output or the VCO tuning node causes a drift of the

VCO frequency. This can be mitigated by using a loop filter

that contains a large capacitive component because this drift is

limited by the current leakage induced slew rate (I_LEAK/C) of the

VCO control voltage. For most applications, the frequency

accuracy is sufficient for 3 sec to 5 sec.

When enabled, this function automatically puts the charge pump

into a high impedance state when the loop loses lock. The

assumption is that the only reason the loop loses lock is due to

the PLL losing the reference clock; therefore, the holdover function

puts the charge pump into a high impedance state to maintain

the VCO frequency as close as possible to the original frequency

before the reference clock disappears. See Figure 53 for a flowchart

of the automatic/internal holdover function operation.

PLL ENABLED

LOOP OUT OF LOCK. DIGITAL LOCK

NO

DETECT SIGNAL GOES LOW WHEN THE

LOOP LEAVES LOCK AS DETERMINED

BY THE PHASE DIFFERENCE AT THE

DLD == LOW

INPUT OF THE PFD.

SYNC

Both a manual holdover, using the

pin, and an automatic

holdover mode are provided. To use either function, the

holdover function must be enabled (Register 0x01D[0] and

Register 0x01D[2]).

YES

NO

ANALOG LOCK DETECT PIN INDICATES

LOCK WAS PREVIOUSLY ACHIEVED.

(0x1D[3] = 1: USE LD PIN VOLTAGE

WITH HOLDOVER.

WAS

Note that the VCO cannot be calibrated with the holdover

enabled because the holdover resets the N divider during

calibration, which prevents proper calibration. Disable

holdover before issuing a VCO calibration.

LD PIN == HIGH

WHEN DLD WENT

LOW?

0x1D[3] = 0: IGNORE LD PIN VOLTAGE,

TREAT LD PIN AS ALWAYS HIGH.)

YES

Manual Holdover Mode

CHARGE PUMP IS MADE

HIGH IMPEDANCE.

PLL COUNTERS CONTINUE

OPERATING NORMALLY.

A manual holdover mode can be enabled that allows the user to

place the charge pump into a high impedance state when the

HIGH IMPEDANCE

CHARGE PUMP

SYNC

pin is asserted low. This operation is edge sensitive, not

YES

level sensitive. The charge pump enters a high impedance state

immediately. To take the charge pump out of a high impedance

NO

CHARGE PUMP REMAINS HIGH

IMPEDANCE UNTIL THE REFERENCE

HAS RETURNED.

SYNC

state, take the

pin high. The charge pump then leaves

REFERENCE

EDGE AT PFD?

high impedance state synchronously with the next PFD rising

edge from the reference clock. This prevents extraneous charge

SYNC

pump events from occurring during the time between

YES

going high and the next PFD event. This also means that the

charge pump stays in a high impedance state as long as there is

no reference clock present.

TAKE CHARGE PUMP OUT OF

HIGH IMPEDANCE. PLL CAN

NOW RESETTLE.

RELEASE

CHARGE PUMP

HIGH IMPEDANCE

The B-counter (in the N divider) is reset synchronously with

the charge pump leaving the high impedance state on the

reference path PFD event. This helps align the edges out of the

R and N dividers for faster settling of the PLL. Because the

prescaler is not reset, this feature works best when the B and R

numbers are close because this results in a smaller phase

difference for the loop to settle out.

YES

NO

WAIT FOR DLD TO GO HIGH. THIS TAKES

5 TO 255 CYCLES (PROGRAMMING OF

THE DLD DELAY COUNTER) WITH THE

REFERENCE AND FEEDBACK CLOCKS

INSIDE THE LOCK WINDOW AT THE PFD.

THIS ENSURES THAT THE HOLDOVER

FUNCTION WAITS FOR THE PLL TO SETTLE

AND LOCK BEFORE THE HOLDOVER

FUNCTION CAN BE RETRIGGERED.

DLD == HIGH

When using this mode, set the channel dividers to ignore the

Figure 53. Flowchart of Automatic/Internal Holdover Mode

SYNC

pin (at least after an initial

event). If the dividers

SYNC

are not set to ignore the

pin, the distribution outputs turn

The holdover function senses the logic level of the LD pin as a

condition to enter holdover. The signal at LD can be from the

DLD, ALD, or current source LD mode. It is possible to disable

the LD comparator (Register 0x01D[3]), which causes the holdover

function to always sense LD as high.

SYNC

off each time

is taken low to put the part into holdover.

Rev. F | Page 38 of 80

Data Sheet

AD9517-2

For example, to use automatic holdover with the following:

If DLD is used, it is possible for the DLD signal to chatter some

while the PLL is reacquiring lock. The holdover function may

retrigger, thereby preventing the holdover mode from ever

terminating. Use of the current source lock detect mode is

recommended to avoid this situation (see the Current Source

Digital Lock Detect section).



Automatic reference switchover, prefer REF1

Digital lock detect: five PFD cycles, high range window

Automatic holdover using the LD pin comparator

Set the following registers (in addition to the normal PLL registers):

Once in holdover mode, the charge pump stays in a high

impedance state as long as there is no reference clock present.



Register 0x018[6:5] = 00b; lock detect counter = five cycles.

Register 0x018[4] = 0b; lock detect window = high range.

Register 0x018[3] = 0b; DLD normal operation.

Register 0x01A[5:0] = 000100b; current source lock detect

mode.

Register 0x01B[7:0] = 0xF7; set REFMON pin to status of

REF1 (active low).

Register 0x01C[2:1] = 11b; enable REF1 and REF2 input

buffers.

As in the external holdover mode, the B counter (in the N

divider) is reset synchronously with the charge pump leaving

the high impedance state on the reference path PFD event. This

helps align the edges out of the R and N dividers for faster

settling of the PLL and to reduce frequency errors during

settling. Because the prescaler is not reset, this feature works

best when the B and R numbers are close because this results in

a smaller phase difference for the loop to settle out.



Register 0x01D[3] = 1b; enable LD pin comparator.

Register 0x01D[2]=1b; enable the holdover function.

After leaving holdover, the loop then reacquires lock and the

LD pin must charge (if Register 0x01D[3] = 1) before it can

re-enter holdover (CP high impedance).

R

egister 0x01D[1] = 0b; use internal/automatic holdover

mode.



Register 0x01D[0] = 1b; enable the holdover function.

(VCO calibration must be complete before this bit is enabled.)

Connect REFMON pin to REFSEL pin.

The holdover function always responds to the state of the

currently selected reference (Register 0x01C). If the loop loses

lock during a reference switchover (see the Reference Switchover

section), holdover is triggered briefly until the next reference clock

edge at the PFD.

Frequency Status Monitors

The AD9517 contains three frequency status monitors that are

used to indicate if the PLL reference (or references in the case

of single-ended mode) and the VCO have fallen below a

threshold frequency. A diagram showing their location in the

PLL is shown in Figure 54. The VCO status frequency monitor

is also capable of monitoring the CLK input if the CLK input is

selected as the input to the N divider.

The following registers affect the internal/automatic holdover

function:



Register 0x018[6:5], lock detect counter. These bits change

the number of consecutive PFD cycles with edges inside the

lock detect window that are required for the DLD indicator

to indicate lock. This impacts the time required before the

LD pin can begin to charge as well as the delay from the end

of a holdover event until the holdover function can be

reengaged.

The PLL reference frequency monitors have two threshold

frequencies: normal and extended (see Table 16). The reference

frequency monitor thresholds are selected in Register 0x01A.

The frequency monitor status can be found in Register 0x01F,

Bits[3:1].



Register 0x018[3], disable digital lock detect. This bit must

be set to 0b to enable the DLD circuit. Internal/automatic

holdover does not operate correctly without the DLD

function enabled.

Register 0x01A[5:0], lock detect pin output select. Set these

bits to 000100b for the current source lock detect mode if

using the LD pin comparator. Load the LD pin with a

capacitor of an appropriate value.

Register 0x01D[3], enable LD pin comparator. 1 = enable,

0 = disable. When disabled, the holdover function always

senses the LD pin as high.



Register 0x01D[1], enable external holdover control.

Register 0x01D[0] and Register 0x01D[2], holdover

function enable. If holdover is disabled, both external

and internal/automatic holdover are disabled.

Rev. F | Page 39 of 80

AD9517-2

Data Sheet

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

HOLD

REFIN (REF2)

N DIVIDER

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

PROGRAMMABLE

N DELAY

CP

P, P + 1

A/B

PRESCALER

COUNTERS

LF

VCO STATUS

VCO

STATUS

0

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

Figure 54. Reference and VCO Status Monitors

7. The PLL loop is closed.

8. The PLL locks.

VCO Calibration

The AD9517 on-chip VCO must be calibrated to ensure proper

operation over process and temperature. VCO calibration centers

the dc voltage at the internal VCO input (at the LF pin) for the

selected configuration; this is normally required only during initial

configuration and any time the PLL settings change. VCO calibra-

tion is controlled by a calibration controller driven by the R divider

output. The calibration requires that the input reference clock be

present at the REFIN pins, and that the PLL be set up properly

to lock the PLL loop. During the first initialization after a power-

up or a reset of the AD9517, a VCO calibration sequence is

initiated by setting Register 0x018[0] = 1b. This can be done

during initial setup, before executing an update registers (Register

0x232[0] = 1b). Subsequent to initial setup, a VCO calibration

sequence is initiated by resetting Register 0x018[0] = 0b, executing

an update registers operation, setting Register 0x018[0] = 1b, and

executing another update registers operation. A readback bit,

Bit 6 in Register 0x1F, indicates when a VCO calibration is

finished by returning a logic true (that is, 1b).

A sync is executed during the VCO calibration; therefore,

the outputs of the AD9517 are held static during the

calibration, which prevents unwanted frequencies from being

produced. However, at the end of a VCO calibration, the

outputs may resume clocking before the PLL loop is completely

settled.

The VCO calibration clock divider is set as shown in Table 54

(Register 0x018[2:1]).

The calibration divider divides the PFD frequency (reference

frequency divided by R) down to the calibration clock. The

calibration occurs at the PFD frequency divided by the

calibration divider setting. Lower VCO calibration clock

frequencies result in longer times for a calibration to be

completed.

The VCO calibration clock frequency is given by

f

_{CAL_CLOCK}= f_REFIN/(R × cal_div)

where:

_REFINis the frequency of the REFIN signal.

The sequence of operations for the VCO calibration is as follows:

1. Program the PLL registers to the proper values for the PLL

loop. Note that that automatic holdover mode must be

disabled, and the VCO divider must not be set to “Static.”

2. Ensure that the input reference signal is present.

3. For the initial setting of the registers after a power-up or reset,

initiate VCO calibration by setting Register 0x018[0] = 1b.

Subsequently, whenever a calibration is desired, set

Register 0x018[0] = 0b, update registers; and then set

Register 0x018[0] = 1b, update registers.

f

R is the value of the R divider.

cal_div is the division set for the VCO calibration divider

(Register 0x018[2:1]).

The VCO calibration takes 4400 calibration clock cycles.

Therefore, the VCO calibration time in PLL reference clock

cycles is given by

Time to Calibrate VCO =

4. A sync operation is initiated internally, causing the outputs

to go to a static state determined by normal sync function

operation.

4400 × R × cal_div PLL Reference Clock Cycles

Table 29. Example Time to Complete a VCO Calibration

with Different f_REFINFrequencies

5. The VCO calibrates to the desired setting for the requested

f_REFIN(MHz) R Divider PFD

Time to Calibrate VCO

VCO frequency.

SYNC

6. Internally, the

continue clocking.

100

10

1

10

100

100 MHz 88 μs

signal is released, allowing outputs to

1 MHz

8.8 ms

88 ms

100 kHz

Rev. F | Page 40 of 80

Data Sheet

AD9517-2

VCO calibration must be manually initiated. This allows for

flexibility in deciding what order to program registers and

when to initiate a calibration, instead of having it happen every

time certain PLL registers have their values change. For

example, this allows for the VCO frequency to be changed by

small amounts without having an automatic calibration occur

each time; this should be done with caution and only when the

user knows that the VCO control voltage is not going to exceed

the nominal best performance limits. For example, a few 100 kHz

steps are fine, but a few MHz might not be. In addition, because

the calibration procedure results in rapid changes in the VCO

frequency, the distribution section is automatically placed in

SYNC until the calibration is finished. Therefore, this

The channel dividers allow for a selection of various duty

cycles, depending on the currently set division. That is, for any

specific division, D, the output of the divider can be set to high

for N + 1 input clock cycles and low for M + 1 input clock

cycles (where D = N + M + 2). For example, a divide-by-5 can

be high for one divider input cycle and low for four cycles, or a

divide-by-5 can be high for three divider input cycles and low

for two cycles. Other combinations are also possible.

The channel dividers include a duty-cycle correction function

that can be disabled. In contrast to the selectable duty cycle

just described, this function can correct a non-50ꢀ duty cycle

caused by an odd division. However, this requires that the

division be set by M = N + 1.

temporary loss of outputs must be expected.

In addition, the channel dividers allow a coarse phase offset or

delay to be set. Depending on the division selected, the output

can be delayed by up to 31 input clock cycles. The divider

outputs can also be set to start high or start low.

A VCO calibration should be initiated under the following

conditions:



After changing any of the PLL R, P, B, and A divider

settings, or after a change in the PLL reference clock

frequency. This, in effect, means any time a PLL register

or reference clock is changed such that a different VCO

frequency results.

Whenever system calibration is desired. The VCO is

designed to operate properly over extremes of temperatures

even when it is first calibrated at the opposite extreme.

However, a VCO calibration can be initiated at any time,

if desired.

Internal VCO or External CLK as Clock Source

The clock distribution of the AD9517 has two clock input

sources: an internal VCO or an external clock connected to the

CLK

CLK/

pins. Either the internal VCO or CLK must be

chosen as the source of the clock signal to distribute. When the

internal VCO is selected as the source, the VCO divider must

be used. When CLK is selected as the source, it is not necessary

to use the VCO divider if the CLK frequency is less than the

maximum channel divider input frequency (1600 MHz);

otherwise, the VCO divider must be used to reduce the

frequency to one acceptable by the channel dividers. Table 30

shows how the VCO, CLK, and VCO divider are selected.

Register 0x1E1[1:0] selects the channel divider source and

determines whether the VCO divider is used. It is not possible

to select the VCO without using the VCO divider.

CLOCK DISTRIBUTION

A clock channel consists of a pair (or double pair, in the case of

CMOS) of outputs that share a common divider. A clock

output consists of the drivers that connect to the output pins.

The clock outputs have either LVPECL or LVDS/CMOS signal

levels at the pins.

The AD9517 has four clock channels: two channels are

LVPECL (four outputs); two channels are LVDS/CMOS (up to

four LVDS outputs or up to eight CMOS outputs).

Table 30. Selecting VCO or CLK as Source for Channel

Divider and Whether VCO Divider Is Used

Register

0x1E1

Each channel has its own programmable divider that divides

the clock frequency that is applied to its input. The LVPECL

channel dividers can divide by any integer from 2 to 32, or

the divider can be bypassed to achieve a divide by one. Each

LVDS/CMOS channel divider contains two of these divider

blocks in a cascaded configuration. The total division of the

channel is the product of the divide value of the cascaded dividers.

This allows divide values of (1 to 32) × (1 to 32), or up to 1024

(note that this is not all values from 1 to 1024 but only the set

of numbers that are the product of the two dividers).

Bit 1 Bit 0 Channel Divider Source

VCO Divider

Used

Not used

Used

0

1

0

1

0

1

CLK

VCO

Not allowed

CLK or VCO Direct to LVPECL Outputs

It is possible to connect either the internal VCO or the CLK

(whichever is selected as the input to the VCO divider) directly

to the LVPECL outputs, OUT0 to OUT3. This configuration

can pass frequencies up to the maximum frequency of the VCO

directly to the LVPECL outputs. The LVPECL outputs may not

be able to provide a full voltage swing at the highest

frequencies.

If the user wishes to use the channel dividers, the VCO divider

must be used after the on-chip VCO. This is because the internal

VCO frequency is above the maximum channel divider input

frequency (1600 MHz). The VCO divider can be set to divide

by 2, 3, 4, 5, or 6. External clock signals connected to the CLK

input also require the VCO divider if the frequency of the

signal is greater than 1600 MHz.

Rev. F | Page 41 of 80

AD9517-2

Data Sheet

To connect the LVPECL outputs directly to the internal VCO

or CLK, the VCO divider must be selected as the source to the

distribution section, even if no channel uses it.

The channel dividers feeding the LVPECL output drivers

contain one 2-to-32 frequency divider. This divider provides

for division by 2 to 32. Division by 1 is accomplished by

bypassing the divider. The dividers also provide for a

programmable duty cycle, with optional duty-cycle correction

when the divide ratio is odd. A phase offset or delay in

increments of the input clock cycle is selectable. The channel

dividers operate with a signal at their inputs up to 1600 MHz.

The features and settings of the dividers are selected by

programming the appropriate setup

Either the internal VCO or the CLK can be selected as the

source for the direct-to-output routing.

Table 31. Settings for Routing VCO Divider Input Directly

to LVPECL Outputs

Register Setting

0x1E1[1:0] = 00b

0x1E1[1:0] = 10b

0x192[1] = 1b

Selection

CLK is the source; VCO divider selected

VCO is the source; VCO divider selected

Direct to OUT0 and OUT1 outputs

Direct to OUT2 and OUT3 outputs

and control registers (see Table 52 through Table 62).

VCO Divider

0x198[1] = 1b

The VCO divider provides frequency division between the

internal VCO or the external CLK input and the clock

distribution channel dividers. The VCO divider can be set

to divide by 2, 3, 4, 5, or 6 (see Table 60, Register 0x1E0[2:0]).

Clock Frequency Division

The total frequency division is a combination of the VCO

divider (when used) and the channel divider. When the VCO

divider is used, the total division from the VCO or CLK to the

output is the product of the VCO divider (2, 3, 4, 5, and 6) and

the division of the channel divider. Table 32 and Table 33

indicate how the frequency division for a channel is set. For the

LVPECL outputs, there is only one divider per channel. For the

LVDS/ CMOS outputs, there are two dividers (X.1, X.2)

cascaded per channel.

Channel Dividers—LVPECL Outputs

Each pair of LVPECL outputs is driven by a channel divider.

There are two channel dividers (0, 1) driving four LVPECL

outputs (OUT0 to OUT3). Table 34 gives the register locations

used for setting the division and other functions of these

dividers. The division is set by the values of M and N. The

divider can be bypassed (equivalent to divide-by-1, divider circuit

is powered down) by setting the bypass bit. The duty-cycle

correction can be enabled or disabled according to the setting

of the DCCOFF bits.

Table 32. Frequency Division for Divider 0 and Divider 1

CLK

or VCO

Selected Divider

CLK/VCO 2 to 6

VCO

Channel

Divider

Direct to

Output

Frequency

Division

Table 34. Setting D_Xfor Divider 0 and Divider 1¹

1 (bypassed) Yes

1 (bypassed) No

2 to 32

1

Low Cycles High Cycles

(2 to 6) × (1)

(2 to 6) ×

(2 to 32)

Divider

M

N

Bypass

DCCOFF

0x192[0]

0x198[0]

No

0

1

0x190[7:4]

0x196[7:4]

0x190[3:0]

0x196[3:0]

0x191[7]

0x197[7]

CLK

Not used

1 (bypassed) No

2 to 32 No

1

2 to 32

¹Note that the value stored in the register = # of cycles minus 1.

Channel Frequency Division (0, 1)

Table 33. Frequency Division for Divider 2 and Divider 3

For each channel (where the channel number is x: 0, 1), the

frequency division, D_X, is set by the values of M and N

(four bits each, representing Decimal 0 to Decimal 15), where

CLK

or VCO

Selected Divider

Channel Divider

VCO

Frequency

Division

X.1

X.2

CLK/VCO 2 to 6

1

(2 to 6) ×

Number of Low Cycles = M + 1

Number of High Cycles = N + 1

(bypassed) (bypassed) (1) × (1)

2 to 32

CLK/VCO 2 to 6

1

(2 to 6) ×

(bypassed) (2 to 32) × (1)

2 to 32

The cycles are cycles of the clock signal currently routed to the

input of the channel dividers (VCO divider out or CLK).

2 to 32

(2 to 6) ×

(2 to 32) ×

(2to 32)

When a divider is bypassed, D_X= 1.

CLK

Not used

Not used 2 to 32

1

Otherwise, D_X= (N + 1) + (M + 1) = N + M + 2. This allows

each channel divider to divide by any integer from 2 to 32.

(2 to 32) × (1)

2 to 32 ×

(2 to 32)

2 to 32

Rev. F | Page 42 of 80

Data Sheet

AD9517-2

Duty Cycle and Duty-Cycle Correction (0, 1)

The duty cycle of the clock signal at the output of a channel is a

result of some or all of the following conditions:

Table 36. Duty Cycle with VCO Divider; Input Duty Cycle Is X%

D_X

Output Duty Cycle

VCO

Divider N + M + 2 DCCOFF = 1

DCCOFF = 0

Even

1 (divider

bypassed)

Odd = 3 1 (divider

bypassed)

Odd = 5 1 (divider

bypassed)

50ꢀ



What are the M and N values for the channel?

Is the DCC enabled?

Is the VCO divider used?

What is the CLK input duty cycle? (The internal VCO has

a 50ꢀ duty cycle.)

33.3ꢀ

40ꢀ

(1 + Xꢀ)/3

(2 + Xꢀ)/5

Even

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

50ꢀ,

requires M = N

50ꢀ,

requires M = N + 1

The DCC function is enabled by default for each channel divider.

However, the DCC function can be disabled individually for each

channel divider by setting the DCCOFF bit for that channel.

Odd

Certain M and N values for a channel divider result in a non-50ꢀ

duty cycle. A non-50ꢀ duty cycle can also result with an even

division, if M ≠ N. The duty-cycle correction function

automatically corrects non-50ꢀ duty cycles at the channel

divider output to 50ꢀ duty cycle. Duty-cycle correction

requires the following channel divider conditions:

Odd = 3 Even

Odd = 3 Odd

Odd = 5 Even

Odd = 5 Odd

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

50ꢀ,

requires M = N

(3N + 4 + Xꢀ)/(6N + 9),

requires M = N + 1

50ꢀ,

requires M = N

(5N + 7 + Xꢀ)/(10N +

15), requires M = N + 1



An even division must be set as M = N.

An odd division must be set as M = N + 1.

Table 37. Channel Divider Output Duty Cycle When the

VCO Divider Is Not Used

Input

When not bypassed or corrected by the DCC function, the duty

cycle of each channel divider output is the numerical value of

(N + 1)/(N + M + 2), expressed as a percentage (ꢀ).

Clock

Duty

Cycle

D_X

Output Duty Cycle

The duty cycle at the output of the channel divider for various

configurations is shown in Table 35 to Table 37.

N + M + 2 DCCOFF = 1

DCCOFF = 0

Any

50ꢀ

Xꢀ

1

1 (divider

bypassed)

(N + 1)/

(M + N + 2)

(N + 1)/

(M + N + 2)

(N + 1)/

(M + N + 2)

Same as input

duty cycle

50ꢀ, requires M = N

Table 35. Duty Cycle with VCO Divider; Input Duty Cycle Is 50%

Even

Odd

VCO

D_X

Output Duty Cycle

Divider

N + M + 2 DCCOFF = 1 DCCOFF = 0

50ꢀ, requires

M = N + 1

(N + 1 + Xꢀ)/(2 × N + 3),

requires M = N + 1

Even

1 (divider

bypassed)

50ꢀ

Odd = 3

Odd = 5

1 (divider

bypassed)

1 (divider

bypassed)

33.3ꢀ

40ꢀ

50ꢀ

The internal VCO has a duty cycle of 50ꢀ. Therefore, when the

VCO is connected directly to the output, the duty cycle is 50ꢀ.

If the CLK input is routed directly to the output, the duty cycle of

the output is the same as the CLK input.

Even, Odd Even

(N + 1)/

(N + M + 2)

(N + 1)/

50ꢀ; requires M = N

50ꢀ; requires M = N + 1

Even, Odd Odd

(N + M + 2)

Rev. F | Page 43 of 80

AD9517-2

Data Sheet

Channel Dividers—LVDS/CMOS Outputs

Phase Offset or Coarse Time Delay (0, 1)

Channel Divider 2 and Channel Divider 3 each drive a pair of

LVDS outputs, giving a total of four LVDS outputs (OUT4 to

OUT7). Alternatively, each of these LVDS differential outputs

can be configured individually as a pair (A and B) of CMOS single-

ended outputs, providing for up to eight CMOS outputs. By

default, the B output of each pair is off but can be turned on as

desired.

Each channel divider allows for a phase offset, or a coarse time

delay, to be programmed by setting register bits (see Table 38).

These settings determine the number of cycles (successive

rising edges) of the channel divider input frequency by which

to offset, or delay, the rising edge of the output of the divider.

This delay is with respect to a nondelayed output (that is, with a

phase offset of zero). The amount of the delay is set by five bits

loaded into the phase offset (PO) register plus the start high (SH)

bit for each channel divider. When the start high bit is set, the

delay is also affected by the number of low cycles (M) that are

programmed for the divider.

Channel Divider 2 and Channel Divider 3 each consist of two

cascaded, 2 to 32, frequency dividers. The channel frequency

division is D_X.1× D_X.2or up to 1024. Divide-by-1 is achieved by

bypassing one or both of these dividers. Both of the dividers

also have DCC enabled by default, but this function can be

disabled, if desired, by setting the DCCOFF bit of the channel.

A coarse phase offset or delay is also programmable (see the

Phase Offset or Coarse Time Delay (Divider 2 and Divider 3)

section). The channel dividers operate up to 1600 MHz. The

features and settings of the dividers are selected by programming

the appropriate setup and control registers (seeTable 52 andTable

53 through Table 62).

The sync function must be used to make phase offsets effective

(see the Synchronizing the Outputs—Sync Function section).

Table 38. Setting Phase Offset and Division for Divider 0 and

Divider 1

Start

Phase

Low Cycles High Cycles

Divider High (SH) Offset (PO)

M

N

0

1

0x191[4]

0x197[4]

0x191[3:0]

0x197[3:0]

0x190[7:4]

0x196[7:4]

0x190[3:0]

0x196[3:0]

Table 39. Setting Division (D_X) for Divider 2, Divider 3¹

Let

Divider

M

N

Bypass

DCCOFF

0x19D[0]

0x1A2[0]

Δt = delay (in seconds).

Δc = delay (in cycles of clock signal at input to D_X).

T_X= period of the clock signal at the input of the divider, D_X

(in seconds).

2

3

2.1 0x199[7:4]

2.2 0x19B[7:4]

3.1 0x19E[7:4]

3.2 0x1A0[7:4]

0x199[3:0]

0x19B[3:0]

0x19E[3:0]

0x1A0[3:0]

0x19C[4]

0x19C[5]

0x1A1[4]

0x1A1[5]

Φ = 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]

¹Note that the value stored in the register = # of cycles minus 1.

The channel divide-by is set as N = high cycles and M = low cycles.

Channel Frequency Division (Divider 2 and Divider 3)

Case 1

The division for each channel divider is set by the bits in the

registers for the individual dividers (X.Y = 2.1, 2.2, 3.1, and 3.2)

For Φ ≤ 15:

Δt = Φ × T_X

Δc = Δt/T_X= Φ

Number of Low Cycles = M_X.Y+ 1

Number of High Cycles = N_X.Y+ 1

Case 2

When both X.1 and X.2 are bypassed, D_X= 1 × 1 = 1.

When only X.2 is bypassed, D_X= (N_X.1+ M_X.1+ 2) × 1.

For Φ ≥ 16:

Δt = (Φ − 16 + M + 1) × T_X

Δc = Δt/T_X

When both X.1 and X.2 are not bypassed, D_X= (N_X.1+ M_X.1+ 2) ×

(N_X.2+ M_X.2+ 2).

By giving each divider a different phase offset, output-to-output

delays can be set in increments of the channel divider input

clock cycle. Figure 55 shows the results of setting such a coarse

offset between outputs.

By cascading the dividers, channel division up to 1024 can be

obtained. However, not all integer value divisions from 1 to

1024 are obtainable; only the values that are the product of the

separate divisions of the two dividers (D_X.1× D_X.2) can be realized.

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CHANNEL

DIVIDER INPUT

Tx

If only one divider is needed when using Divider 2 and Divider 3,

use the first one (X.1) and bypass the second one (X.2). Do not

bypass X.1 and use X.2.

TPUTS

CHANNEL DIVIDER OU

%

DIV = 4, DUTY = 50

SH = 0

PO = 0

DIVIDER 0

DIVIDER 1

DIVIDER 2

SH = 0

PO = 1

SH = 0

PO = 2

1 × Tx

2 × Tx

Figure 55. Effect of Coarse Phase Offset (or Delay)

Rev. F | Page 44 of 80

Data Sheet

AD9517-2

Table 42. Divider 2 and Divider 3 Duty Cycle; VCO Divider

Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO

Divider Input Duty Cycle = 50%

Duty Cycle and Duty-Cycle Correction (Divider 2 and

Divider 3)

The same duty cycle and DCC considerations apply to Divider

2 and Divider 3 as to Divider 0 and Divider 1 (see the Duty

Cycle and Duty-Cycle Correction (0, 1) section); however, with

these channel dividers, the number of possible configurations is

even more complex.

D_X.1

D_X.2

Output

Duty

VCO

Divider N_X.1+ M_X.1+ 2

N_X.2+ M_X.2+ 2

Cycle

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

1

50ꢀ

Duty-cycle correction on Divider 2 and Divider 3 requires the

following channel divider conditions:

Even (N_X.1= M_X.1)

Odd (M_X.1= N_X.1+ 1)

Even (N_X.1= M_X.1)

Odd (M_X.1= N_X.1+ 1) Even (N_X.2= M_X.2)

Odd (M_X.1= N_X.1+ 1) Odd (M_X.2= N_X.2+ 1) 50ꢀ



An even D_X.Ymust be set as M_X.Y= N_X.Y(low cycles = high

cycles).

Even (N_X.2= M_X.2)



An odd D_X.Ymust be set as M_X.Y= N_X.Y+ 1 (the number of

low cycles must be one greater than the number of high

cycles).



If only one divider is bypassed, it must be the second

divider, X.2.

If only one divider has an even divide-by, it must be the

second divider, X.2.

Table 43. Divider 2 and Divider 3 Duty Cycle; VCO Divider

Used; Duty Cycle Correction On (DCCOFF = 0); VCO

Divider Input Duty Cycle = X%

The possibilities for the duty cycle of the output clock from

Divider 2 and Divider 3 are shown in Table 40 through Table 44.

D_X.1

D_X.2

Table 40. Divider 2 and Divider 3 Duty Cycle; VCO Divider

Used; Duty Cycle Correction Off (DCCOFF = 1)

VCO

Output

Duty Cycle

Divider N_X.1+ M_X.1+ 2 N_X.2+ M_X.2+ 2

Even

1

50ꢀ

(1 + Xꢀ)/3

(2 + Xꢀ)/5

D_X.1

D_X.2

VCO

Divider

Output

Duty Cycle

Odd = 3

Odd = 5

Even

N_X.1+ M_X.1+ 2 N_X.2+ M_X.2+ 2

Even

1

50ꢀ

33.3ꢀ

40ꢀ

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

Even

(N_X.1= M_X.1)

Even

(N_X.1= M_X.1)

Odd

(M_X.1= N_X.1+ 1)

Odd = 3

Odd = 5

Even

1

50ꢀ

Odd

Even, odd

Even

Odd

Even

Odd

Even, odd

1

Odd = 3 Odd

(M_X.1= N_X.1+ 1)

Odd = 5 Odd

(M_X.1= N_X.1+ 1)

Even

(3N_X.1+ 4 + Xꢀ)/

(6N_X.1+ 9)

(5N_X.1+ 7 + Xꢀ)/

(10N_X.1+ 15)

Even, odd

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

Even

Odd

Even

Odd

Even

(N_X.2= M_X.2)

Even

(N_X.2= M_X.2)

50ꢀ

(N_X.1= M_X.1)

Even

(N_X.1= M_X.1)

Odd

Table 41. Divider 2 and Divider 3 Duty Cycle; VCO Divider

Not Used; Duty Cycle Correction Off (DCCOFF = 1)

D_X.1

D_X.2

Output

Duty Cycle

Input Clock

Duty Cycle

Even

N_X.1+ M_X.1+ 2 N_X.2+ M_X.2+ 2

(M_X.1= N_X.1+ 1) (N_X.2= M_X.2)

Odd Even

(M_X.1= N_X.1+ 1) (N_X.2= M_X.2)

Odd Odd

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1)

Odd = 3 Odd

Odd

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1)

50ꢀ

Xꢀ

50ꢀ

1

50ꢀ

Xꢀ

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

(N_X.2+ 1)/

Even, odd

(6N_X.1N_X.2+ 9N_X.1

9N_X.2+ 13 + Xꢀ)/

(3(2N_X.1+ 3)

+

Xꢀ

Even, odd

1

50ꢀ

Xꢀ

Even, odd

(2N_X.2+ 3))

Odd = 5 Odd

Odd

(10N_X.1N_X.2+ 15N_X.1+

15N_X.2+ 22 + Xꢀ)/

(5(2 N_X.1+ 3)

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1)

(N_X.2+ M_X.2+ 2)

(2 N_X.2+ 3))

Rev. F | Page 45 of 80

AD9517-2

Data Sheet

Table 44. Divider 2 and Divider 3 Duty Cycle; VCO Divider

Not Used; Duty Cycle Correction On (DCCOFF = 0)

Input

Let

Δt = delay (in seconds).

Φ_x.y= 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +

1 × PO[0].

D_X.1

D_X.2

Clock

Duty

Cycle

T

_X.1= period of the clock signal at the input to D_X.1(in seconds).

_X.2= period of the clock signal at the input to D_X.2(in seconds).

N_X.1+ M_X.1+ 2 N_X.2+ M_X.2+ 2

Output Duty Cycle

50ꢀ

1

Even

1

50ꢀ

Case 1

(N_X.1= M_X.1)

When Φ_x.1≤ 15 and Φ_x.2≤ 15:

Δt = Φ_x.1× T_X.1+ Φ_X.2× T_x.2

Case 2

Xꢀ

1

Even

(N_X.1= M_X.1)

1

Xꢀ (High)

50ꢀ

Xꢀ

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

1

50ꢀ

When Φ_x.1≤ 15 and Φ_x.2≥ 16:

Δt = Φ_X.1× T_X.1+ (Φ_X.2− 16 + M_X.2+ 1) × T_X.2

Case 3

(N_X.1+ 1 + Xꢀ)/

(2N_X.1+ 3)

50ꢀ

Xꢀ

Even

(N_X.1= M_X.1)

Even

(N_X.1= M_X.1)

Even

(N_X.2= M_X.2)

Even

(N_X.2= M_X.2)

50ꢀ

When Φ_X.1≥ 16 and Φ_X.2≤ 15:

Δt = (Φ_X.1− 16 + M_X.1+ 1) × T_X.1+ Φ_X.2× T_X.2

Case 4

50ꢀ

Xꢀ

Odd

Even

(M_X.1= N_X.1+ 1) (N_X.2= M_X.2)

Odd Even

(M_X.1= N_X.1+ 1) (N_X.2= M_X.2)

Odd Odd

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1)

Odd Odd

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1) 3N_X.2+ 4 + Xꢀ)/

((2N_X.1+ 3)(2N_X.2+ 3))

When Φ_X.1≥ 16 and Φ_X.2≥ 16:

Δt =

50ꢀ

Xꢀ

(Φ_X.1− 16 + M_X.1+ 1) × T_X.1+ (Φ_X.2− 16 + M_X.2+ 1) × T_X.2

Fine Delay Adjust (Divider 2 and Divider 3)

(2N_X.1N_X.2+ 3N_X.1

+

Each AD9517 LVDS/CMOS output (OUT4 to OUT7) includes

an analog delay element that can be programmed to give

variable time delays (Δt) in the clock signal at that output.

Phase Offset or Coarse Time Delay (Divider 2 and Divider 3)

VCO

BYPASS

Divider 2 and Divider 3 can be set to have a phase offset or

delay. The phase offset is set by a combination of the bits in the

phase offset and start high registers (see Table 45).

CLK DIVIDER

CMOS

LVDS

CMOS

OUTM

ΔT

FINE DELAY

ADJUST

OUTPUT

DIVIDER

X.1

DIVIDER

X.2

Table 45. Setting Phase Offset and Division for Divider 2 and

Divider 3

DRIVERS

BYPASS

ΔT

CMOS

LVDS

CMOS

OUTN

Start

Phase

Low

High

Divider High (SH) Offset (PO)

Cycles M

Cycles N

FINE DELAY

ADJUST

2

3

2.1 0x19C[0]

2.2 0x19C[1]

3.1 0x1A1[0]

3.2 0x1A1[1]

0x19A[3:0]

0x19A[7:4]

0x19F[3:0]

0x19F[7:4]

0x199[7:4]

0x19B[7:4]

0x19E[7:4]

0x1A0[7:4]

0x199[3:0]

0x19B[3:0]

0x19E[3:0]

0x1A0[3:0]

Figure 56. Fine Delay (OUT4 to OUT7)

The amount of delay applied to the clock signal is determined

by programming four registers per output (see Table 46).

Table 46. Setting Analog Fine Delays

OUTPUT

Ramp

Delay

Fraction

Delay

Bypass

(LVDS/CMOS) Capacitors Current

OUT4

OUT5

OUT6

OUT7

0x0A1[5:3]

0x0A4[5:3]

0x0A7[5:3]

0x0AA[5:3]

0x0A1[2:0]

0x0A4[2:0]

0x0A7[2:0]

0x0AA[2:0]

0x0A2[5:0]

0x0A5[5:0]

0x0A8[5:0]

0x0AB[5:0]

0x0A0[0]

0x0A3[0]

0x0A6[0]

0x0A9[0]

Rev. F | Page 46 of 80

Data Sheet

AD9517-2

Synchronization of the outputs is executed in several ways,

as follows:

Calculating the Fine Delay

The following values and equations are used to calculate the

delay of the delay block.

SYNC

pin low and then releasing it (manual



By forcing the

sync).

I

_RAMP(μA) = 200 × (Ramp Current + 1)



By setting and then resetting any one of the following three

bits: the soft sync bit (Register 0x230[0]), the soft reset bit

(Register 0x000[2] [mirrored]), and the power-down

distribution reference bit (Register 0x230[1]).

Number of Capacitors = Number of Bits =

0 in Ramp Capacitors + 1

Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;

001 = 2 + 1 = 3; 111 = 0 + 1 = 1.



By executing synchronization of the outputs as part of the

chip power-up sequence.

Delay Range (ns) = 200 × ((No. of Caps + 3)/(I_RAMP)) × 1.3286

 No.of Caps 1

RESET

By forcing the

reset).

pin low and then releasing it (chip

10^4



6









Offset



ns



 0.34 



1600  I_RAMP



I_RAMP

PD

By forcing the

down).

pin low and then releasing it (chip power-

Delay Full Scale (ns) = Delay Range + Offset

Following completion of a VCO calibration. An internal

SYNC signal is automatically asserted at the beginning of

a VCO calibration and then released upon its completion.

Fine Delay (ns) =

Delay Range × Delay Fraction × (1/63) + Offset

Note that only delay fraction values up to 47 decimal (101111b;

0x2F) are supported.

The most common way to execute the sync function is to use

SYNC

the

pin to do a manual synchronization of the outputs.

SYNC

In no case can the fine delay exceed one-half of the output clock

period. If a delay longer than half of the clock period is attempted,

the output stops clocking.

This requires a low-going signal on the

pin, which is

held low and then released when synchronization is desired.

The timing of the sync operation is shown in Figure 57 (using

VCO divider) and Figure 58 (VCO divider not used). There is

an uncertainty of up to one cycle of the clock at the input to the

channel divider due to the asynchronous nature of the SYNC

signal with respect to the clock edges inside the AD9517. The

The delay function adds some jitter that is greater than that

specified for the nondelayed output. This means that the delay

function should be used primarily for clocking digital chips,

such as FPGA, ASIC, DUC, and DDC. An output with this

delay enabled may not be suitable for clocking data converters.

The jitter is higher for long full scales because the delay block

uses a ramp and trip points to create the variable delay. A

slower ramp time produces more time jitter.

SYNC

delay from the

rising edge to the beginning of synchronized

output clocking is between 14 and 15 cycles of clock at the channel

divider input, plus either one cycle of the VCO divider input

(see Figure 57), or one cycle of the channel divider input (see

Figure 58), depending on whether the VCO divider is used.

Cycles are counted from the rising edge of the signal.

Synchronizing the Outputs—Sync Function

The AD9517 clock outputs can be synchronized to each other.

Outputs can be individually excluded from synchronization.

Synchronization consists of setting the nonexcluded outputs to

a preset set of static conditions and subsequently releasing these

outputs to continue clocking at the same instant with the preset

conditions applied. This allows for the alignment of the edges

of two or more outputs or for the spacing of edges according to

the coarse phase offset settings for two or more outputs.

Another common way to execute the sync function is by setting

and resetting the soft sync bit at Register 0x230[0] (see Table 53

through Table 62 for details). Both the setting and resetting

of the soft sync bit require an update all registers operation

(Register 0x232[0] = 1) to take effect.

Rev. F | Page 47 of 80

AD9517-2

Data Sheet

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER OUTPUT STATIC

INPUT TO VCO DIVIDER

1

11

13

14

1

2

3

4

5

6

7

9

10

12

INPUT TO CHANNEL DIVIDER

8

SYNC PIN

OUTPUT OF

CHANNEL DIVIDER

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

Figure 57. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER OUTPUT STATIC

INPUT TO CLK

1

11

13

14

IINPUT TO CHANNEL DIVIDER

1

2

3

4

5

6

7

9

10

12

8

SYNC PIN

OUTPUT OF

CHANNEL DIVIDER

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

Figure 58. SYNC Timing When VCO Divider Is Not Used—CLK Input Only

A sync operation brings all outputs that have not been excluded

(by the nosync bit) to a preset condition before allowing the

outputs to begin clocking in synchronicity. The preset

condition takes into account the settings in each of the

channel’s start high bit and its phase offset. These settings

govern both the static state of each output when the sync

operation is happening and the state and relative phase of the

outputs when they begin clocking again upon completion of the

sync operation. Between outputs and after synchronization, this

allows for the setting of phase offsets.

Each channel (a divider and its outputs) can be excluded from

any sync operation by setting the nosync bit of the channel.

Channels that are set to ignore SYNC (excluded channels) do

not set their outputs static during a sync operation, and their

outputs are not synchronized with those of the nonexcluded

channels.

Clock Outputs

The AD9517 offers three different output level choices:

LVPECL, LVDS, and CMOS. OUT0 to OUT3 are LVPECL

differential outputs; and OUT4 to OUT7 are LVDS/CMOS

outputs. These outputs can be configured as either LVDS

differential or as pairs of single-ended CMOS outputs.

The AD9517 outputs are in pairs, sharing a channel divider per

pair (two pairs of pairs, four outputs, in the case of CMOS).

The synchronization conditions apply to both outputs of a pair.

Rev. F | Page 48 of 80

Data Sheet

AD9517-2

LVPECL Outputs—OUT0 to OUT3

The LVPECL differential voltage (V_OD) is selectable from ~400 mV

to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]). The

LVPECL outputs have dedicated pins for power supply

(VS_LVPECL), allowing a separate power supply to be used.

V_{S_LVPECL}can be from 2.5 V to 3.3 V.

3.5mA

OUT

The LVPECL output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVPECL output can be powered

down or powered up as needed. Because of the architecture of

the LVPECL output stages, there is the possibility of electrical

overstress and breakdown under certain power-down conditions.

For this reason, the LVPECL outputs have several power-down

modes. This includes a safe power-down mode that continues

to protect the output devices while powered down, although it

consumes somewhat more power than a total power-down. If

the LVPECL output pins are terminated, it is best to select the

safe power-down mode. If the pins are left floating (i.e., not

connected), total power-down mode is fine.

3.5mA

Figure 60. LVDS Output Simplified Equivalent Circuit with

3.5 mA Typical Current Source

Each LVDS/CMOS output can be powered-down as needed to

save power. The CMOS output power-down is controlled by

the same bit that controls the LVDS power-down for that

output. This power-down control affects both CMOS Output A

and CMOS Output B. However, when CMOS Output A is

powered up, CMOS Output B can be powered on or off

separately.

V

S

3.3V

OUT

Figure 61. CMOS Equivalent Output Circuit

RESET MODES

The AD9517 has several ways to force the chip into a reset

condition that restores all registers to their default values and

makes these settings active.

GND

Figure 59. LVPECL Output Simplified Equivalent Circuit

Power-On Reset—Start-Up Conditions When V_SIs

Applied

LVDS/CMOS Outputs—OUT4 to OUT7

OUT4 to OUT7 can be configured as either an LVDS

differential output or as a pair of CMOS single-ended outputs.

The LVDS outputs allow for selectable output current from

~1.75 mA to ~7 mA.

A power-on reset (POR) is issued when the V_Spower supply is

turned on. This initializes the chip to the power-on conditions

that are determined by the default register settings. These are

indicated in the Default Value (Hex) column of Table 52. At

power-on, the AD9517 also executes a sync operation, which

brings the outputs into phase alignment according to the

default settings.

The LVDS output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVDS output can be powered down

if not needed to save power.

RESET

Asynchronous Reset via the

An asynchronous hard reset is executed by momentarily

OUT4 to OUT7 can also be CMOS outputs. Each LVDS output

can be configured to be two CMOS outputs. This provides for

up to eight CMOS outputs: OUT4A, OUT4B, OUT5A, OUT5B,

OUT6A, OUT6B, OUT7A, and OUT7B. When an output is

configured as CMOS, CMOS Output A is automatically turned on.

CMOS Output B can be turned on or off independently. The

relative polarity of the CMOS outputs can also be selected for

any combination of inverting and noninverting (see Table 57,

Register 0x140[7:5], Register 0x141[7:5], Register 0x142[7:5],

and Register 0x143[7:5]).

RESET

pulling

settings.

low. A reset restores the chip registers to the default

Soft Reset via Register 0x00[2]

A soft reset is executed by writing Register 0x000[2] and

Register 0x000[5] = 1b. This bit is not self-clearing; it must be

cleared by writing Register 0x000[2] and Register 0x000[5] = 0b to

reset it and complete the soft reset operation. A soft reset restores

the default values to the internal registers. The soft reset bit does

Rev. F | Page 49 of 80

AD9517-2

Data Sheet

not require an update registers command (Register 0x232) to be

issued.

In asynchronous power-down mode, the device powers down

as soon as the registers are updated.

In synchronous power-down mode, the PLL power-down is

gated by the charge pump to prevent unwanted frequency

jumps. The device goes into power-down on the occurrence of

the next charge pump event after the registers are updated.

POWER-DOWN MODES

PD

Chip Power-Down via

The AD9517 can be put into a power-down condition by

PD

pulling the

functions and currents inside the AD9517. The chip remains in

PD

pin low. Power-down turns off most of the

Distribution Power-Down

The distribution section can be powered down by writing

Register 0x230[1] = 1b. This turns off the bias to the distribution

section. If the LVPECL power-down mode is normal operation

(00b), it is possible for a low impedance load on that LVPECL

output to draw significant current during this power-down. If

the LVPECL power-down mode is set to 11b, the LVPECL

output is not protected from reverse bias and may be damaged

under certain termination conditions.

this power-down state until

is brought back to logic high.

When the AD9517 wakes up, it returns to the settings

programmed into its registers prior to the power-down, unless

the registers are changed by new programming while the

pin is held low.

PD

The

power-down shuts down the currents on the chip, except

the bias current that is necessary to maintain the LVPECL outputs

in a safe shutdown mode. This is needed to protect the LVPECL

output circuitry from damage that could be caused by certain

termination and load configurations when tristated. Because

this is not a complete power-down, it can be called sleep mode.

Individual Clock Output Power-Down

Any of the clock distribution outputs can be powered down

individually by writing to the appropriate registers. The register

map details the individual power-down settings for each output

(see Table 52). The LVDS/CMOS outputs can be powered

down, regardless of their output load configuration.

PD

When the AD9517 is in a

following state:

power-down, the chip is in the



The PLL is off (asynchronous power-down).

The VCO is off.

The CLK input buffer is off.

The LVPECL outputs have multiple power-down modes

(see Table 56), which give some flexibility in dealing with the

various output termination conditions. When the mode is set to

10b, the LVPECL output is protected from reverse bias to

2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is

not protected from reverse bias and can be damaged under

certain termination conditions. This setting also affects the

operation when the distribution block is powered down with

Register 0x230[1] = 1b (see the Distribution Power-Down section).

All dividers are off.

All LVDS/CMOS outputs are off.

All LVPECL outputs are in safe off mode.

The serial control port is active, and the chip responds to

commands.

If the AD9517 clock outputs must be synchronized to each

other, a SYNC is required upon exiting power-down (see the

Synchronizing the Outputs—Sync Function section). A VCO

calibration is not required when exiting power-down.

Individual Circuit Block Power-Down

Other AD9517 circuit blocks (such as CLK, REF1, and REF2)

can be powered down individually. This gives flexibility in

configuring the part for power savings whenever certain chip

functions are not needed.

PLL Power-Down

The PLL section of the AD9517 can be selectively powered down.

There are three PLL operating modes set by Register 0x010[1:0],

as shown in Table 54.

Rev. F | Page 50 of 80

Data Sheet

AD9517-2

SERIAL CONTROL PORT

The AD9517 serial control port is a flexible, synchronous, serial

communications port that allows an easy interface with many

industry-standard microcontrollers and microprocessors. The

AD9517 serial control port is compatible with most synchronous

transfer formats, including both the Motorola SPI® and Intel®

SSR® protocols. The serial control port allows read/write access

to all registers that configure the AD9517. Single or multiple

byte transfers are supported, as well as MSB first or LSB first

transfer formats. The AD9517 serial control port can be

configured for a single bidirectional I/O pin (SDIO only)

or for two unidirectional I/O pins (SDIO/SDO). By default,

the AD9517 is in bidirectional mode, long instruction (long

instruction is the only instruction mode supported).

During this period, the serial control port state machine enters

a wait state until all data is sent. If the system controller decides

to abort the transfer before all of the data is sent, the state machine

must be reset, either by completing the remaining transfers or

CS

by returning

low for at least one complete SCLK cycle (but

CS

less than eight SCLK cycles). Raising

on a nonbyte

boundary terminates the serial transfer and flushes the buffer.

In the streaming mode (see Table 47), any number of data bytes

can be transferred in a continuous stream. The register address

is automatically incremented or decremented (see the MSB/LSB

CS

First Transfers section).

must be raised at the end of the last

byte to be transferred, thereby ending the stream mode.

Communication Cycle—Instruction Plus Data

SERIAL CONTROL PORT PIN DESCRIPTIONS

There are two parts to a communication cycle with the

AD9517. The first part writes a 16-bit instruction word into the

AD9517, coincident with the first 16 SCLK rising edges. The

instruction word provides the AD9517 serial control port with

information regarding the data transfer, which is the second

part of the communication cycle. The instruction word defines

whether the upcoming data transfer is a read or a write, the

number of bytes in the data transfer, and the starting register

address for the first byte of the data transfer.

SCLK (serial clock) is the serial shift clock. This pin is an input.

SCLK is used to synchronize serial control port reads and

writes. Write data bits are registered on the rising edge of this

clock, and read data bits are registered on the falling edge. This

pin is internally pulled down by a 30 kΩ resistor to ground.

SDIO (serial data input/output) is a dual-purpose pin that acts

as either an input only (unidirectional mode) or as both an

input/output (bidirectional mode). The AD9517 defaults to the

bidirectional I/O mode (Register 0x000[0] = 0b).

Write

SDO (serial data out) is used only in the unidirectional I/O

mode (Register 0x000[0] = 1b) as a separate output pin for

reading back data.

If the instruction word is for a write operation, the second part

is the transfer of data into the serial control port buffer of the

AD9517. Data bits are registered on the rising edge of SCLK.

CS

(chip select bar) is an active low control that gates the read

The length of the transfer (1, 2, 3 bytes or streaming mode) is

indicated by two bits ([W1:W0]) in the instruction byte. When

CS

and write cycles. When

is high, SDO and SDIO are in a high

impedance state. This pin is internally pulled up by a 30 kΩ

resistor to VS.

CS

the transfer is 1, 2, or 3 bytes, but not streaming,

can be raised

after each sequence of eight bits to stall the bus (except after the

last byte, where it ends the cycle). When the bus is stalled, the serial

13

SCLK

AD9517-2

SERIAL

CONTROL

PORT

CS

transfer resumes when

is lowered. Raising

on a nonbyte

14

CS

15

boundary resets the serial control port. During a write, streaming

mode does not skip over reserved or blank registers; therefore,

the user must know the bit pattern to write to the reserved

registers to preserve proper operation of the part. Refer to the

control register map (see Table 52) to determine if the default

value for reserved registers is nonzero. It does not matter what

data is written to blank registers.

SDO

16

SDIO

Figure 62. Serial Control Port

GENERAL OPERATION OF SERIAL CONTROL PORT

A write or a read operation to the AD9517 is initiated by

CS

pulling

low.

stalled high is supported in modes where three or fewer bytes

of data (plus instruction data) are transferred (see Table 47).

CS

Because data is written into a serial control port buffer area,

and not directly into the actual control registers of the AD9517,

an additional operation is needed to transfer the serial control

port buffer contents to the actual control registers of the

AD9517, thereby causing them to become active. The update

registers operation consists of setting Register 0x232[0] = 1b

(this bit is self-clearing). Any number of bytes of data can be

changed before an update registers operation is executed. The

update registers operation simultaneously actuates all register

changes that have been written to the buffer since any previous

update.

CS

In these modes,

boundary, allowing time for the system controller to process

CS

can temporarily return high on any byte

the next byte.

can go high on byte boundaries only and can

go high during either part (instruction or data) of the transfer.

Rev. F | Page 51 of 80

AD9517-2

Data Sheet

The 13 bits found in [A12:A0] select the address within the

register map that is written to or read from during the data

transfer portion of the communications cycle. Only

Bits[A9:A0] are needed to cover the range of the 0x232 registers

used by the AD9517. Bits[A12:A10] must always be set to 0b.

For multibyte transfers, this address is the starting byte address.

In MSB first mode, subsequent bytes decrement the address.

Read

If the instruction word is for a read operation, the next N × 8

SCLK cycles clock out the data from the address specified in the

instruction word, where N is 1 to 3 as determined by [W1:W0].

If N = 4, the read operation is in streaming mode, continuing

until

is raised. Streaming mode does not skip over reserved

CS

MSB/LSB FIRST TRANSFERS

or blank registers. The readback data is valid on the falling

edge of SCLK.

The AD9517 instruction word and byte data can be MSB first

or LSB first. Any data written to Register 0x000 must be mirrored;

the upper four bits (Bits[7:4]) with the lower four bits (Bits[3:0).

This makes it irrelevant whether LSB first or MSB first is in

effect. As an example of this mirroring, see the default setting

for this register: 0x18, which mirrors Bit 4 and Bit 3. This sets

the long instruction mode (which is the default and the only

mode that is supported).

The default mode of the AD9517 serial control port is the

bidirectional mode. In bidirectional mode, both the sent data

and the readback data appear on the SDIO pin. It is also possible to

set the AD9517 to unidirectional mode via the SDO active bit,

Register 0x000[0] = 1b. In unidirectional mode, the readback

data appears on the SDO pin.

A readback request reads the data that is in the serial control

port buffer area, or the data that is in the active registers (see

Figure 63). Readback of the buffer or active registers is controlled

by Register 0x004[0].

The default for the AD9517 is MSB first.

When LSB first is set by Register 0x000[1] and Register 0x000[6],

it takes effect immediately because it affects only the operation of

the serial control port and does not require that an update be

executed.

The AD9517 supports only the long instruction mode; therefore,

Register 0x000[4:3] must be set to 11b. (This register uses mirrored

bits.) Long instruction mode is the default at power-up or reset.

When MSB first mode is active, the instruction and data bytes

must be written from MSB to LSB. Multibyte data transfers in

MSB first format start with an instruction byte that includes the

register address of the most significant data byte. Subsequent

data bytes must follow in order from the high address to the

low address. In MSB first mode, the serial control port internal

address generator decrements for each data byte of the

multibyte transfer cycle.

The AD9517 uses Register Address 0x000 to Register

Address 0x232.

SCLK

SDIO

SDO

UPDATE

REGISTERS

CS

SERIAL

CONTROL

PORT

When LSB first is active, the instruction and data bytes must be

written from LSB to MSB. Multibyte data transfers in LSB first

format start with an instruction byte that includes the register

address of the least significant data byte followed by multiple

data bytes. The internal byte address generator of the serial

control port increments for each byte of the multibyte

transfer cycle.

WRITE REGISTER 0x232 = 0x01

TO UDATE REGISTERS

Figure 63. Relationship Between Serial Control Port Buffer Registers and

Active Registers of the AD9517

THE INSTRUCTION WORD (16 BITS)

W

The MSB of the instruction word is R/ , which indicates

The AD9517 serial control port register address decrements

from the register address just written toward 0x000 for multibyte

I/O operations if the MSB first mode is active (default). If the LSB

first mode is active, the register address of the serial control port

increments from the address just written toward Address 0x232

for multibyte I/O operations.

whether the instruction is a read or a write. The next two bits,

[W1:W0], indicate the length of the transfer in bytes. The final

13 bits are the address ([A12:A0]) at which to begin the read or

write operation.

For a write, the instruction word is followed by the number of

bytes of data indicated by Bits[W1:W0] (see Table 47).

Streaming mode always terminates when it hits Address 0x232.

Note that unused addresses are not skipped during multibyte

I/O operations.

Table 47. Byte Transfer Count

W1

W0

Bytes to Transfer

0

1

0

1

0

1

2

3

Table 48. Streaming Mode (No Addresses Are Skipped)

Write Mode Address Direction Stop Sequence

LSB first

MSB first

Increment

Decrement

0x230, 0x231, 0x232, stop

0x001, 0x000, 0x232, stop

Streaming mode

Rev. F | Page 52 of 80

Data Sheet

AD9517-2

Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

LSB

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

I0

R/W

W1

W0

A12 = 0

A11 = 0

A10 = 0

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

CS

SCLK DON'T CARE

DON'T CARE

SDIO

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data

CS

SCLK

DON'T CARE

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

SDIO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDO DON'T CARE

16-BIT INSTRUCTION HEADER

REGISTER (N) DATA

REGISTER (N – 1) DATA

REGISTER (N – 2) DATA

REGISTER (N – 3) DATA

DON'T

CARE

Figure 65. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data

t_DS

t_HIGH

t_S

t_C

t_DH

t_CLK

t_LOW

CS

DON’T CARE

SCLK

SDIO

R/W

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

D4

D3

D2

D1

D0

DON’T CARE

Figure 66. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

CS

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N – 1

Figure 67. Timing Diagram for Serial Control Port Register Read

Rev. F | Page 53 of 80

AD9517-2

Data Sheet

CS

SCLK DON'T CARE

DON'T CARE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

DON'T CARE

SDIO

Figure 68. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data

t_S

t_C

CS

t_CLK

t_HIGH

t_LOW

t_DS

SCLK

SDIO

t_DH

BIT N

BIT N + 1

Figure 69. Serial Control Port Timing—Write

Table 50. Serial Control Port Timing

Parameter

Description

t_DS

t_DH

t_CLK

t_S

Setup time between data and rising edge of SCLK

Hold time between data and rising edge of SCLK

Period of the clock

Setup time between CS falling edge and SCLK rising edge (start of communication cycle)

Setup time between SCLK rising edge and CS rising edge (end of communication cycle)

Minimum period that SCLK should be in a logic high state

t_C

t_HIGH

t_LOW

t_DV

Minimum period that SCLK should be in a logic low state

SCLK to valid SDIO and SDO (see Figure 67)

Rev. F | Page 54 of 80

Data Sheet

AD9517-2

THERMAL PERFORMANCE

Table 51. Thermal Parameters for the 48-Lead LFCSP

Symbol

Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board

Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air)

Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)

Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air)

Junction-to-board thermal resistance, natural convection per JEDEC JESD51-8 (still air)

Value (°C/W)

24.7

21.6

19.4

12.9

θ_JA

θ_JMA

θ_JB

Ψ_JB

Junction-to-board characterization parameter, natural convection per JEDEC JESD51-6 (still air)

and JEDEC JESD51-8

11.9

Ψ_JB

Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)

and JEDEC JESD51-8

Junction-to-board characterization parameter, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air)

and JEDEC JESD51-8

11.8

11.6

θ_JC

Ψ_JT

Junction-to-case thermal resistance (die-to-heat sink) per MIL-STD-883, Method 1012.1

1.3

0.1

0.2

0.3

Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air)

Junction-to-top-of-package characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-2 (still air)

Junction-to-top-of-package characterization parameter, 2.0 m/sec airflow per JEDEC JESD51-2 (still air)

Use the following equation to determine the junction

temperature of the AD9517 on the application PCB:

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first-order

approximation of T_Jby the following equation

T_J= T_CASE+ (Ψ_JT× PD)

T_J= T_A+ (θ_JA× PD)

where:

T_Jis the junction temperature (°C).

where T_Ais the ambient temperature (°C).

T

_CASEis the case temperature (°C) measured by the user at the

Values of θ_JCare provided for package comparison and PCB

design considerations when an external heat sink is required.

top center of the package.

Ψ_JTis the value from Table 51.

PD is the power dissipation of the device (see Table 17).

Values of Ψ_JBare provided for package comparison and PCB

design considerations.

Rev. F | Page 55 of 80

AD9517-2

Data Sheet

CONTROL REGISTERS

CONTROL REGISTER MAP OVERVIEW

Table 52. Control Register Map Overview

Reg.

Addr.

Default

Value

(Hex)

Parameter

Bit 7 (MSB) Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

(Hex)

Serial Port Configuration

0x000

Serial port

SDO

LSB first

Soft reset

Long

Soft reset

LSB first

SDO active

0x18

configuration

active

instruction

0x001

0x002

0x003

0x004

Blank

Reserved

Part ID

Part ID (read only)

0x91

0x00

Readback

control

Blank

Read back

active

registers

PLL

0x010

PFD and

PFD

Charge pump current

Charge pump mode

PLL power-down

0x7D

charge pump

polarity

0x011

0x012

0x013

0x014

0x015

0x016

R counter

14-bit R divider, Bits[7:0] (LSB)

14-bit R divider, Bits[13:8] (MSB)

6-bit A counter

13-bit B counter, Bits[7:0] (LSB)

13-bit B counter, Bits[12:8] (MSB)

B counter Prescaler P

0x01

0x00

0x03

0x00

0x06

Blank

A counter

B counter

Blank

Reset R

counter

PLL Control 1

Set CP pin

to V_CP/2

Reset A and

B counters

Reset all

counters

bypass

0x017

0x018

PLL Control 2

PLL Control 3

STATUS pin control

Antibacklash pulse width

0x00

0x06

Reserved

Lock detect counter

Digital lock

detect

Disable

digital lock

detect

VCO calibration divider

VCO cal now

window

0x019

PLL Control 4

SYNC

R path delay

N path delay

0x00

R, A, B counters

pin reset

0x01A PLL Control 5

Reserved

Reference

frequency

monitor

LD pin control

threshold

0x01B

PLL Control 6

VCO

frequency

monitor

REF2

REF1 (REFIN)

frequency

monitor

REFMON pin control

0x00

REFIN

(

)

frequency

monitor

0x01C PLL Control 7

0x01D PLL Control 8

Disable

switchover REF2

deglitch

Select

Use

REF_SEL pin

Reserved

REF2

power-on

REF1

power-on

Differential

reference

0x00

Reserved

PLL status

register

disable

LD pin

comparator

enable

Holdover

enable

External

holdover

control

Holdover

enable

0x01E

0x01F

PLL Control 9

PLL readback

Reserved

0x00

N/A

Reserved

VCO cal

finished

Holdover

active

REF2

selected

VCO

frequency >

threshold

REF2

REF1

Digital

lock detect

frequency > frequency >

threshold threshold

0x020

to

Blank

0x04F

Rev. F | Page 56 of 80

Data Sheet

AD9517-2

Reg.

Addr.

Default

Value

(Hex)

Parameter

Bit 7 (MSB) Bit 6

Bit 5

Bit 4

Blank

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

(Hex)

Fine Delay Adjust—OUT4 to OUT7

0x0A0 OUT4 delay

bypass

OUT4 delay

bypass

0x01

0x00

0x01

0x00

0x01

0x00

0x01

0x00

0x0A1 OUT4 delay

full-scale

Blank

OUT4 ramp capacitors

OUT4 ramp current

0x0A2 OUT4 delay

fraction

OUT4 delay fraction

OUT5 delay fraction

OUT6 delay fraction

OUT7 delay fraction

0x0A3 OUT5 delay

bypass

Blank

OUT5 delay

bypass

OUT5 ramp current

0x0A4 OUT5 delay

full-scale

Blank

OUT5 ramp capacitors

0x0A5 OUT5 delay

fraction

0x0A6 OUT6 delay

bypass

Blank

OUT6 delay

bypass

0x0A7 OUT6 delay

full-scale

Blank

OUT6 ramp capacitors

OUT6 ramp current

0x0A8 OUT6 delay

fraction

0x0A9 OUT7 delay

bypass

Blank

OUT7 delay

bypass

0x0AA OUT7 delay

full-scale

Blank

OUT7 ramp capacitors

OUT7 ramp current

0x0AB OUT7 delay

fraction

0x0AC

to

Blank

0x0EF

LVPECL Outputs

0x0F0

OUT0

Blank

OUT0

invert

OUT0 LVPECL

differential voltage

OUT0 power-down

0x08

0x0A

0x0F1

OUT1

invert

OUT1 LVPECL

differential voltage

OUT1 power-down

0x0F2,

0x0F3

Reserved

0x0F4

OUT2

OUT3

Blank

OUT2

invert

OUT2 LVPECL

differential voltage

OUT2 power-down

OUT3 power-down

0x08

0x0A

0x0F5

OUT3

invert

OUT3 LVPECL

differential voltage

0x0F6

to

Blank

0x13F

LVDS/CMOS Outputs

0x140

0x141

0x142

0x143

OUT4

OUT5

OUT6

OUT7

OUT4 CMOS

output polarity

OUT4 LVDS/ OUT4

OUT4 select

LVDS/CMOS

OUT4 LVDS

output current

OUT4

power-down

0x42

0x43

0x42

0x43

CMOS

CMOS B

output

polarity

OUT5 CMOS

output polarity

OUT5 LVDS/ OUT5

OUT5 select

LVDS/CMOS

OUT5 LVDS

output current

OUT5

power-down

CMOS

CMOS B

output

polarity

OUT6 CMOS

output polarity

OUT6 LVDS/ OUT6

OUT6 select

LVDS/CMOS

OUT6 LVDS

output current

OUT6

power-down

CMOS

CMOS B

output

polarity

OUT7 CMOS

output polarity

OUT7 LVDS/ OUT7

OUT7 select

LVDS/CMOS

OUT7 LVDS

output current

OUT7

power-down

CMOS

CMOS B

output

polarity

0x144

to

Blank

0x18F

Rev. F | Page 57 of 80

AD9517-2

Data Sheet

Reg.

Addr.

Default

Value

(Hex)

Parameter

Bit 7 (MSB) Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

(Hex)

LVPECL Channel Dividers

0x190

0x191

0x192

Divider 0

(PECL)

Divider 0 low cycles

Divider 0 high cycles

Divider 0 phase offset

0x00

0x80

0x00

Divider 0

bypass

Divider 0

nosync

Divider 0

force high

Divider 0

start high

Blank

Reserved

Divider 0

direct to

output

Divider 0

DCCOFF

0x193

to

Reserved

0x195

0x196

0x197

0x198

Divider1

(PECL)

Divider 1 low cycles

Divider 1 high cycles

Divider 1 phase offset

0x00

Divider 1

bypass

Divider 1

nosync

Blank

Divider 1

force high

Divider 1

start high

Reserved

Divider 1

direct to

output

Divider 1

DCCOFF

LVDS/CMOS Channel Dividers

0x199

Divider 2

Low Cycles Divider 2.1

High Cycles Divider 2.1

0x22

(LVDS/CMOS)

0x19A

0x19B

Phase Offset Divider 2.2

Low Cycles Divider 2.2

Phase Offset Divider 2.1

High Cycles Divider 2.2

0x00

0x11

0x19C

0x19D

0x19E

Reserved

Bypass

Divider 2.2

Bypass

Divider 2.1

Divider 2

nosync

Divider 2

force high

Start High

Divider 2.2

Start High

Divider 2.1

0x00

0x22

Blank

Reserved

Divider 2

DCCOFF

Divider 3

(LVDS/CMOS)

Low Cycles Divider 3.1

High Cycles Divider 3.1

0x19F

0x1A0

0x1A1

Phase Offset Divider 3.2

Low Cycles Divider 3.2

Phase Offset Divider 3.1

High Cycles Divider 3.2

0x00

0x11

0x00

Reserved

Bypass

Divider 3.2

Bypass

Divider 3.1

Divider 3

nosync

Divider 3

Start High

Divider 3.2

Start High

Divider 3.1

force high

0x1A2

0x1A3

Blank

Reserved

Divider 3

DCCOFF

0x00

Reserved

Blank

0x1A4

to

0x1DF

VCO Divider and CLK Input

0x1E0

0x1E1

VCO divider

Input CLKs

Blank

Reserved

VCO Divider

0x02

0x00

Reserved

Power

down

clock input

section

Power down

VCO clock

interface

Power

down VCO

and CLK

Select

VCO or CLK

Bypass VCO

divider

0x1E2

to

Blank

0x22A

System

0x230

Power-down

and sync

Reserved

Power

down sync

Power

down

Soft sync

0x00

distribution

reference

0x231

Blank

Reserved

0x00

Update All Registers

0x232

Update all

registers

Blank

Update all

registers (self-

clearing bit)

Rev. F | Page 58 of 80

Data Sheet

AD9517-2

CONTROL REGISTER MAP DESCRIPTIONS

Table 53 through Table 62 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal

address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2].

Table 53. Serial Port Configuration and Part ID

Reg.

Addr

(Hex)

Bits

Name

Description

0x000

[7:4]

Mirrored, Bits[3:0]

Bits[7:4] should always mirror Bits[3:0] so that it does not matter whether the part

is in MSB or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows:

Bit 7 = Bit 0.

Bit 6 = Bit 1.

Bit 5 = Bit 2.

Bit 4 = Bit 3.

3

Long instruction

Short/long instruction mode. This part uses long instruction mode only, so this bit should

always be set to 1b.

0: 8-bit instruction (short).

1: 16-bit instruction (long) (default).

Soft reset.

1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to

0b to complete reset operation.

2

1

Soft reset

LSB first

MSB or LSB data orientation.

0: data-oriented MSB first; addressing decrements (default).

1: data-oriented LSB first; addressing increments.

Selects unidirectional or bidirectional data transfer mode.

0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default).

1: SDO used for read, SDIO used for write; unidirectional mode.

Uniquely identifies the dash version (-0 through -4) of the AD9517

AD9517-0: 0x11

AD9517-1: 0x51

AD9517-2: 0x91

AD9517-3: 0x53

AD9517-4: 0xD3

0

SDO active

0x003

0x004

[7:0]

Part ID (read only)

0

Read back active registers Selects register bank used for a readback.

0: reads back buffer registers (default).

1: reads back active registers.

Rev. F | Page 59 of 80

AD9517-2

Data Sheet

Table 54. PLL

Reg.

Addr.

(Hex)

Bits

Name

Description

0x010

7

PFD polarity

Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires

positive polarity; Bit 7 = 0b.

0: positive; higher control voltage produces higher frequency (default).

1: negative; higher control voltage produces lower frequency.

Charge pump current (with CPRSET = 5.1 kΩ).

[6:4]

CP current

6

0

1

5

0

1

0

1

4

0

1

0

1

0

1

0

1

I_CP(mA)

0.6

1.2

1.8

2.4

3.0

3.6

4.2

4.8 (default)

[3:2]

[1:0]

CP mode

Charge pump operating mode.

3

0

1

2

0

1

0

1

Charge Pump Mode

High impedance state.

Force source current (pump up).

Force sink current (pump down).

Normal operation (default).

PLL power-down

PLL operating mode.

1

0

1

0

1

0

1

Mode

Normal operation.

Asynchronous power-down (default).

Normal operation.

Synchronous power-down.

0x011

0x012

[7:0]

[5:0]

14-bit R divider,

Bits[7:0] (LSB)

R divider LSBs—lower eight bits (default = 0x01).

14-bit R divider,

Bits[13:8] (MSB)

R divider MSBs—upper six bits (default = 0x00).

0x013

0x014

[5:0]

[7:0]

6-bit A counter

A counter (part of N divider) (default = 0x00).

13-bit B counter,

Bits[7:0] (LSB)

B counter (part of N divider)—lower eight bits (default = 0x03).

0x015

0x016

[4:0]

7

13-bit B counter,

Bits[12:8] (MSB)

B counter (part of N divider)—upper five bits (default = 0x00).

Set CP pin to V_CP/2

Reset R counter

Sets the CP pin to one-half of the V_CPsupply voltage.

0: CP normal operation (default).

1: CP pin set to V_CP/2.

6

5

4

3

Resets R counter (R divider).

0: normal (default).

1: holds the R counter in reset.

Reset A, B counters Resets A and B counters (part of N divider).

0: normal (default).

1: holds the A and B counters in reset.

Reset all counters Resets R, A, and B counters.

0: normal (default).

1: holds the R, A, and B counters in reset.

B counter

bypass

B counter bypass. This is valid only when operating the prescaler in FD mode.

0: normal (default).

1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.

Rev. F | Page 60 of 80

Data Sheet

AD9517-2

Reg.

Addr.

(Hex)

Bits

Name

Description

0x016

[2:0]

Prescaler P

Prescaler: DM = dual modulus and FD = fixed divide.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Mode

FD

Prescaler

Divide-by-1.

FD

Divide-by-2.

DM

FD

Divide-by-2 (2/3 mode).

Divide-by-4 (4/5 mode).

Divide-by-8 (8/9 mode).

Divide-by-16 (16/17 mode).

Divide-by-32 (32/33 mode) (default).

Divide-by-3.

0x017

[7:2]

STATUS pin

control

Selects the signal that is connected to the STATUS pin.

Level or

Dynamic

7

0

6

0

X

5

0

X

4

0

1

X

3

0

1

0

1

X

2

0

1

0

1

0

1

0

X

Signal

Signal at STATUS Pin

Ground (dc) (default).

N divider output (after the delay).

R divider output (after the delay).

A divider output.

LVL

DYN

LVL

Prescaler output.

PFD up pulse.

PFD down pulse.

Ground (dc); for all other cases of 0XXXXXb not specified above.

The selections that follow are the same as REFMON.

Ground (dc).

1

0

1

0

1

0

1

0

1

0

1

LVL

DYN

LVL

REF1 clock (differential reference when in differential mode).

REF2 clock (not available in differential mode).

Selected reference to PLL (differential reference when in differential mode).

Unselected reference to PLL (not available in differential mode).

Status of selected reference (status of differential reference); active

high.

1

0

1

0

LVL

Status of unselected reference (not available in differential mode);

active high.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

DYN

LVL

Status REF1 frequency (active high).

Status REF2 frequency (active high).

(Status REF1 frequency) AND (status REF2 frequency).

(DLD) AND (status of selected reference) AND (status of VCO).

Status of VCO frequency (active high).

Selected reference (low = REF1, high = REF2).

Digital lock detect (DLD); active high.

Holdover active (active high).

LD pin comparator output (active high).

VS (PLL supply).

REF1 clock

REF2 clock

(differential reference when in differential mode).

(not available in differential mode).

Selected reference to PLL

(differential reference when in differential mode).

Unselected reference to PLL

(not available when in differential mode).

Status of selected reference (status of differential reference); active low.

Status of unselected reference (not available in differential mode); active low.

Status of REF1 frequency (active low).

Status of REF2 frequency (active low).

(Status of REF1 frequency) AND (status of REF2 frequency).

1

0

1

0

LVL

(DLD) AND (status of selected reference) AND (status of VCO).

1

0

1

0

1

0

1

0

1

LVL

Status of VCO frequency (active low).

Selected reference (low = REF2, high = REF1).

Digital lock detect (DLD) (active low).

Holdover active (active low).

LD pin comparator output (active low).

Rev. F | Page 61 of 80

AD9517-2

Data Sheet

Reg.

Addr.

(Hex)

Bits

Name

Description

0x017

[1:0]

Antibacklash

pulse width

1

0

1

0

1

0

1

Antibacklash Pulse Width (ns)

2.9 (default). This is the recommended setting; it does not normally need to be changed.

1.3. This setting may be necessary if the PFD frequency > 50 MHz.

6.0.

2.9.

0x018

[6:5]

Lock detect

counter

Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked

condition.

6

0

1

5

0

1

0

1

PFD Cycles to Determine Lock

5 (default).

16.

64.

255.

4

Digital lock detect

window

If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock

detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.

0: high range (default).

1: low range.

3

Disable digital

lock detect

Digital lock detect operation.

0: normal lock detect operation (default).

1: disables lock detect.

[2:1]

VCO cal divider

VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.

2

0

1

0

1

0

1

VCO Calibration Clock Divider

2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is f_REF/R.

4. This setting is fine for PFD frequencies < 25 MHz.

8. This setting is fine for PFD frequencies < 50 MHz.

16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.

0

VCO cal now

Bit used to initiate the VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate

calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0b (if

not zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1b, followed by another update

bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the PLL losing lock.

The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.

0x019

[7:6]

R, A, B counters

7

0

1

6

0

1

0

1

Action

SYNC

(default).

pin reset

Does nothing on

Asynchronous reset.

Synchronous reset.

SYNC

Does nothing on

.

[5:3]

[2:0]

R path delay

N path delay

R path delay (default = 0x00) (see Table 2).

N path delay (default = 0x00) (see Table 2).

Rev. F | Page 62 of 80

Data Sheet

AD9517-2

Reg.

Addr.

(Hex)

Bits

Name

Description

Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO

0x01A

6

Reference

frequency monitor frequency monitor’s detection threshold (see Table 16: REF1, REF2, and VCO frequency status monitor parameter).

threshold

0: frequency valid if frequency is above the higher frequency threshold (default).

1: frequency valid if frequency is above the lower frequency threshold.

Selects the signal that is connected to the LD pin.

[5:0]

LD pin control

Level or

Dynamic

5

0

4

0

X

3

0

X

2

0

1

X

1

0

1

0

X

0

1

0

1

0

X

Signal

Signal at LD Pin

LVL

Digital lock detect (high = lock, low = unlock) (default).

P-channel, open-drain lock detect (analog lock detect).

N-channel, open-drain lock detect (analog lock detect).

High-Z LD pin.

DYN

HIZ

CUR

LVL

Current source lock detect (110 μA when DLD is true).

Ground (dc); for all other cases of 0XXXXXb not specified above.

The selections that follow are the same as REFMON.

Ground (dc).

1

0

1

0

1

0

1

0

1

0

1

0

1

0

LVL

DYN

LVL

REF1 clock (differential reference when in differential mode).

REF2 clock (not available in differential mode).

Selected reference to PLL (differential reference when indifferential mode).

Unselected reference to PLL (not available in differential mode).

Status of selected reference (status of differential reference); active high.

LVL

Status of unselected reference (not available in differential mode);

active high.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

DYN

Status REF1 frequency (active high).

Status REF2 frequency (active high).

(Status REF1 frequency) AND (status REF2 frequency).

(DLD) AND (status of selected reference) AND (status of VCO).

Status of VCO frequency (active high).

Selected reference (low = REF1, high = REF2).

Digital lock detect (DLD); active high.

Holdover active (active high).

Not available. Do not use.

VS (PLL supply).

REF1 clock

REF2 clock

(differential reference when in differential mode).

(not available in differential mode).

Selected reference to PLL

mode).

(differential reference when in differential

1

0

1

0

1

DYN

LVL

Unselected reference to PLL

(not available when in differential mode).

Status of selected reference (status of differential reference); active

low.

1

0

1

0

LVL

Status of unselected reference (not available in differential mode);

active low.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

Status of REF1 frequency (active low).

Status of REF2 frequency (active low).

(Status of REF1 frequency) AND (status of REF2 frequency)

.

(DLD) AND (status of selected reference) AND (status of VCO)

Status of VCO frequency (active low).

Selected reference (low = REF2, high = REF1).

Digital lock detect (DLD); active low.

Holdover active (active low).

.

Not available. Do not use.

Rev. F | Page 63 of 80

AD9517-2

Data Sheet

Reg.

Addr.

(Hex)

Bits

Name

Description

0x01B

7

VCO

Enables or disables VCO frequency monitor.

frequency monitor 0: disables VCO frequency monitor (default).

1: enables VCO frequency monitor.

6

5

REFIN

REF2 (

Enables or disables REF2 frequency monitor.

)

frequency monitor 0: disables REF2 frequency monitor (default).

1: enables REF2 frequency monitor.

REF1 (REFIN)

REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs

frequency monitor (as selected by differential reference mode).

0: disables REF1 (REFIN) frequency monitor (default).

1: enables REF1 (REFIN) frequency monitor.

[4:0]

REFMON

Selects the signal that is connected to the REFMON pin.

pin control

Level or

Dynamic

4

0

1

3

0

1

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Signal

LVL

DYN

LVL

DYN

LVL

Signal at REFMON Pin

Ground (dc) (default).

REF1 clock (differential reference when in differential mode).

REF2 clock (not available in differential mode).

Selected reference to PLL (differential reference when in differential mode).

Unselected reference to PLL (not available in differential mode).

Status of selected reference (status of differential reference); active high.

Status of unselected reference (not available in differential mode); active high.

Status REF1 frequency (active high).

Status REF2 frequency (active high).

(Status REF1 frequency) AND (status REF2 frequency).

(DLD) AND (status of selected reference) AND (status of VCO).

Status of VCO frequency (active high).

Selected reference (low = REF1, high = REF2).

Digital lock detect (DLD); active low.

Holdover active (active high).

LD pin comparator output (active high).

VS (PLL supply).

REF1 clock

REF2 clock

(differential reference when in differential mode).

(not available in differential mode).

Selected reference to PLL

(differential reference when in differential mode).

Unselected reference to PLL

(not available in differential mode).

Status of selected reference (status of differential reference); active low.

Status of unselected reference (not available in differential mode); active low.

Status of REF1 frequency (active low).

Status of REF2 frequency (active low).

(Status of REF1 frequency) AND (Status of REF2 frequency)

.

(DLD) AND (Status of selected reference) AND (Status of VCO)

Status of VCO frequency (active low).

.

Selected reference (low = REF2, high = REF1).

Digital lock detect (DLD); active low.

Holdover active (active low).

LD pin comparator output (active low).

0x01C

7

6

5

Disable

Disables or enables the switchover deglitch circuit.

0: enables switchover deglitch circuit (default).

1: disables switchover deglitch circuit.

If Register 0x01C, Bit 5 = 0b, selects reference for PLL.

0: selects REF1 (default).

switchover

deglitch

Select REF2

1: selects REF2.

Use REF_SEL pin

Sets method of PLL reference selection.

0: uses Register 0x01C, Bit 6 (default).

1: uses REF_SEL pin.

Rev. F | Page 64 of 80

Data Sheet

AD9517-2

Reg.

Addr.

(Hex)

Bits

[4:3]

2

Name

Description

0x01C

Reserved

Reserved (default: 00b).

This bit turns the REF2 power on.

0: REF2 power off (default).

1: REF2 power on.

REF2 power-on

1

0

REF1 power-on

This bit turns the REF1 power on.

0: REF1 power off (default).

1: REF1 power on.

Differential

reference

Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic

switchover between REF1 and REF2 to work.

0: single-ended reference mode (default).

1: differential reference mode.

0x01D

4

3

PLL status

Disables the PLL status register readback.

0: PLL status register enable (default).

1: PLL status register disable.

register disable

LD pin comparator Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When

enable

in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if

the PLL was previously in a locked state (see Figure 53). Otherwise, this function can be used with the REFMON and

STATUS pins to monitor the voltage on this pin.

0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default).

1: enables LD pin comparator.

2

1

Holdover enable

Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration.

0: holdover disabled (default).

1: holdover enabled.

External

SYNC

pin. (This disables the internal holdover mode.)

Enables the external hold control through the

0: automatic holdover mode—holdover controlled by automatic holdover circuit. (default)

SYNC

holdover control

1: external holdover mode—holdover controlled by

pin.

0

6

5

4

3

Holdover enable

VCO cal finished

Holdover active

REF2 selected

Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration.

0: holdover disabled (default).

1: holdover enabled.

0x01F

Read-only register: indicates status of the VCO calibration.

0: VCO calibration not finished.

1: VCO calibration finished.

Read-only register: indicates if the part is in the holdover state (see Figure 53). This is not the same as holdover enabled.

0: not in holdover.

1: holdover state active.

Read-only register: indicates which PLL reference is selected as the input to the PLL.

0: REF1 selected (or differential reference if in differential mode).

1: REF2 selected.

VCO frequency >

threshold

Read-only register: indicates if the VCO frequency is greater than the threshold (see Table 16: REF1, REF2, and VCO

frequency status monitor).

0: VCO frequency is less than the threshold.

1: VCO frequency is greater than the threshold.

2

1

0

REF2 frequency >

threshold

Read-only register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by

Register 0x1A, Bit 6.

0: REF2 frequency is less than threshold frequency.

1: REF2 frequency is greater than threshold frequency.

REF1 frequency >

threshold

Read-only register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency

set by Register 0x01A, Bit 6.

0: REF1 frequency is less than threshold frequency.

1: REF1 frequency is greater than threshold frequency.

Read-only register: digital lock detect.

0: PLL is not locked.

Digital lock detect

1: PLL is locked.

Rev. F | Page 65 of 80

AD9517-2

Data Sheet

Table 55. Fine Delay Adjust—OUT4 to OUT7

Reg.

Addr.

(Hex)

Bits

Name

Description

0x0A0

0

OUT4 delay bypass

Bypasses or uses the delay function.

0: uses delay function.

1: bypasses delay function (default).

0x0A1

[5:3] OUT4 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the

number of the capacitors and the ramp current sets the delay full scale.

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Number of Capacitors

4 (default)

3

2

3

2

1

[2:0] OUT4 ramp current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the delay full scale.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current (μA)

200 (default)

400

600

800

1000

1200

1400

1600

0x0A2

0x0A3

[5:0] OUT4 delay fraction

Selects the fraction of the full-scale delay desired (6-bit binary).

A setting of 000000b gives zero delay.

Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).

0

OUT5 delay bypass

Bypasses or uses the delay function.

0: uses delay function.

1: bypasses delay function (default).

0x0A4

[5:3] OUT5 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the

number of the capacitors and the ramp current sets the delay full scale.

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Number of Capacitors

4 (default)

3

2

3

2

1

Rev. F | Page 66 of 80

Data Sheet

AD9517-2

Reg.

Addr.

(Hex)

Bits

Name

Description

0x0A4

[2:0] OUT5 ramp current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the delay full scale.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current (μA)

200 (default)

400

600

800

1000

1200

1400

1600

0x0A5

0x0A6

[5:0] OUT5 delay fraction

Selects the fraction of the full-scale delay desired (6-bit binary).

A setting of 000000b gives zero delay.

Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).

0

OUT6 delay bypass

Bypasses or uses the delay function.

0: uses delay function.

1: bypasses delay function (default).

0x0A7

[5:3] OUT6 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the

number of capacitors and the ramp current sets the delay full scale.

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Number of Capacitors

4 (default)

3

2

3

2

1

[2:0] OUT6 ramp current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the delay full scale.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current (μA)

200 (default)

400

600

800

1000

1200

1400

1600

0x0A8

0x0A9

[5:0] OUT6 delay fraction

Selects the fraction of the full-scale delay desired (6-bit binary).

A setting of 000000b gives zero delay.

Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).

0

OUT7 delay bypass

Bypasses or uses the delay function.

0: uses delay function.

1: bypasses delay function (default).

Rev. F | Page 67 of 80

AD9517-2

Data Sheet

Reg.

Addr.

(Hex)

Bits

Name

Description

0x0AA [5:3] OUT7 ramp capacitors Selects the number of ramp capacitors used by the delay function. The combination of the

number of capacitors and the ramp current sets the delay full scale.

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Number of Capacitors

4 (default)

3

2

3

2

1

[2:0] OUT7 ramp current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the delay full scale.

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current Value (μA)

200 (default)

400

600

800

1000

1200

1400

1600

0x0AB

[5:0] OUT7 delay fraction

Selects the fraction of the full-scale delay desired (6-bit binary).

A setting of 000000b gives zero delay.

Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).

Table 56. LVPECL Outputs

Reg.

Addr.

(Hex) Bits

Name

Description

0x0F0

4

OUT0 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2]

OUT0 LVPECL

Sets the LVPECL output differential voltage (V_OD).

differential voltage

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

[1:0]

OUT0 power-down

LVPECL power-down modes.

1

0

1

Mode

Output

On

Off

Normal operation (default).

Partial power-down, reference on;

use only if there are no external load resistors.

1

0

1

Partial power-down, reference on, safe LVPECL power-down.

Total power-down, reference off;

use only if there are no external load resistors.

Off

Rev. F | Page 68 of 80

Data Sheet

AD9517-2

Reg.

Addr.

(Hex) Bits

Name

Description

0x0F1

0x0F4

0x0F5

4

OUT1 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2]

OUT1 LVPECL

Sets the LVPECL output differential voltage (V_OD).

differential voltage

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

[1:0]

OUT1 power-down

LVPECL power-down modes.

1

0

1

Mode

Output

Normal operation.

Partial power-down, reference on; use only if there are no external load

resistors.

On

Off

1

0

1

Partial power-down, reference on, safe LVPECL power-down (default).

Total power-down, reference off; use only if there are no external load

resistors.

Off

4

OUT2 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2]

OUT2 LVPECL

Sets the LVPECL output differential voltage (V_OD).

differential voltage

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

[1:0]

OUT2 power-down

LVPECL power-down modes.

1

0

1

Mode

Output

On

Off

Normal operation (default).

Partial power-down, reference on; use only if there are no external load

resistors.

1

0

1

Partial power-down, reference on, safe LVPECL power-down.

Total power-down, reference off; use only if there are no external load

resistors.

Off

4

OUT3 invert

Sets the output polarity.

0: noninverting (default).

1: inverting.

[3:2]

OUT3 LVPECL

Sets the LVPECL output differential voltage (V_OD).

differential voltage

3

0

1

2

0

1

0

1

V_OD(mV)

400

600

780 (default)

960

[1:0]

OUT3 power-down

LVPECL power-down modes.

1

0

1

Mode

Output

On

Off

Normal operation.

Partial power-down, reference on; use only if there are no external

load resistors.

1

0

1

Partial power-down, reference on, safe LVPECL power-down (default).

Total power-down, reference off; use only if there are no external

load resistors.

Off

Rev. F | Page 69 of 80

AD9517-2

Data Sheet

Table 57. LVDS/CMOS Outputs

Reg.

Addr.

(Hex) Bits

Name

Description

0x140 [7:5]

OUT4 output polarity

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.

In LVDS mode, only Bit 5 determines LVDS polarity.

7

0

1

0

1

6

0

1

0

1

0

1

0

1

5

0

1

OUT4A (CMOS)

Noninverting

Inverting

Noninverting

OUT4B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT4 (LVDS)

Noninverting

Noninverting (default)

Noninverting

Inverting

4

OUT4 CMOS B

In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.

0: turns off the CMOS B output (default).

1: turns on the CMOS B output.

3

OUT4 select LVDS/CMOS

OUT4 LVDS output current

Selects LVDS or CMOS logic levels.

0: LVDS (default).

1: CMOS.

[2:1]

Sets output current level in LVDS mode. This has no effect in CMOS mode.

2

0

1

0

1

0

1

Current (mA)

Recommended Termination (Ω)

1.75

3.5

5.25

7

100

100 (default)

50

0

OUT4 power-down

Powers down output (LVDS/CMOS).

0: power on (default).

1: power off.

0x141 [7:5]

OUT5 output polarity

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.

In LVDS mode, only Bit 5 determines LVDS polarity.

7

0

1

0

1

6

0

1

0

1

0

1

0

1

5

0

1

OUT5A (CMOS)

Noninverting

Inverting

Noninverting

OUT5B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT5 (LVDS)

Noninverting

Noninverting (default)

Noninverting

Inverting

4

OUT5 CMOS B

In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.

0: turns off the CMOS B output (default).

1: turns on the CMOS B output.

3

OUT5 select LVDS/CMOS

OUT5 LVDS output current

Selects LVDS or CMOS logic levels.

0: LVDS (default).

1: CMOS.

[2:1]

Sets output current level in LVDS mode. This has no effect in CMOS mode.

2

0

1

0

1

0

1

Current (mA)

Recommended Termination (Ω)

1.75

3.5

5.25

7

100

100 (default)

50

Rev. F | Page 70 of 80

Data Sheet

AD9517-2

Reg.

Addr.

(Hex) Bits

Name

Description

0x141

0

OUT5 power-down

Powers down output (LVDS/CMOS).

0: power on.

1: power off (default).

0x142 [7:5]

OUT6 output polarity

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.

In LVDS mode, only Bit 5 determines LVDS polarity.

7

0

1

0

1

6

0

1

0

1

0

1

0

1

5

0

1

OUT6A (CMOS)

Noninverting

Inverting

Noninverting

OUT6B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT6 (LVDS)

Noninverting

Noninverting (default)

Noninverting

Inverting

4

OUT6 CMOS B

In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.

0: turns off the CMOS B output (default).

1: turns on the CMOS B output.

3

OUT6 select LVDS/CMOS

OUT6 LVDS output current

Selects LVDS or CMOS logic levels.

0: LVDS (default).

1: CMOS.

[2:1]

Sets output current level in LVDS mode. This has no effect in CMOS mode.

2

0

1

0

1

0

1

Current (mA)

Recommended Termination (Ω)

100

100 (default)

50

1.75

3.5

5.25

7

0

OUT6 power-down

Powers down output (LVDS/CMOS).

0: power on (default).

1: power off.

0x143 [7:5]

OUT7 output polarity

In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.

In LVDS mode, only Bit 5 determines LVDS polarity.

7

0

1

0

1

6

0

1

0

1

0

1

0

1

5

0

1

OUT7A (CMOS)

Noninverting

Inverting

Noninverting

OUT7B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT7 (LVDS)

Noninverting

Noninverting (default)

Noninverting

Inverting

4

3

OUT7 CMOS B

In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.

0: turns off the CMOS B output (default).

1: turns on the CMOS B output.

OUT7 select LVDS/CMOS

Selects LVDS or CMOS logic levels.

0: LVDS (default).

1: CMOS.

Rev. F | Page 71 of 80

AD9517-2

Data Sheet

Reg.

Addr.

(Hex) Bits

Name

Description

Sets output current level in LVDS mode. This has no effect in CMOS mode.

0x143 [2:1]

OUT7 LVDS output current

2

0

1

0

1

0

1

Current (mA)

Recommended Termination (Ω)

1.75

3.5

5.25

7

100

100 (default)

50

0

OUT7 power-down

Powers down output (LVDS/CMOS).

0: power on.

1: power off (default).

Table 58. LVPECL Channel Dividers

Reg.

Addr.

(Hex) Bits

Name

Description

0x190 [7:4]

Divider 0 low cycles

Number of clock cycles (minus 1) of the divider input during which divider output stays

low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0]

Divider 0 high cycles

Divider 0 bypass

Number of clock cycles (minus 1) of the divider input during which divider output stays

high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x191

7

6

5

4

Bypasses and powers down the divider; routes input to divider output.

0: uses divider.

1: bypasses divider (default).

Divider 0 nosync

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Divider 0 force high

Divider 0 start high

Forces divider output to high. This requires that nosync (Bit 6) also be set.

0: divider output forced to low (default).

1: divider output forced to high.

Selects clock output to start high or start low.

0: starts low (default).

1: starts high.

[3:0]

1

Divider 0 phase offset

Phase offset (default = 0x0).

0x192

Divider 0 direct to output

Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.

0: OUT0 and OUT1 are connected to Divider 0 (default).

1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.

If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.

If Register 0x1E1[1:0] = 01b, there is no effect.

0

Divider 0 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

0x196 [7:4]

[3:0]

Divider 1 low cycles

Divider 1 high cycles

Divider 1 bypass

Number of clock cycles of the divider input during which divider output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

Number of clock cycles (minus 1) of the divider input during which divider output stays

high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x197

7

6

5

Bypasses and powers down the divider; routes input to divider output.

0: uses divider (default).

1: bypasses divider.

Divider 1 nosync

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Divider 1 force high

Forces divider output to high. This requires that nosync (Bit 6) also be set.

0: divider output forced to low (default).

1: divider output forced to high.

Rev. F | Page 72 of 80

Data Sheet

AD9517-2

Reg.

Addr.

(Hex) Bits

Name

Description

0x197

4

Divider 1 start high

Selects clock output to start high or start low.

0: starts low (default).

1: starts high.

[3:0]

1

Divider 1 phase offset

Phase offset (default = 0x0).

0x198

Divider 1 direct to output

Connects OUT2 and OUT3 to Divider 2 or directly to VCO or CLK.

0: OUT2 and OUT3 are connected to Divider 1 (default).

1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.

If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.

If Register 0x1E1[1:0] = 01b, there is no effect.

0

Divider 1 DCCOFF

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

Table 59. LVDS/CMOS Channel Dividers

Reg.

Addr.

(Hex)

Bits

Name

Description

0x199 [7:4] Low Cycles Divider 2.1

Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0] High Cycles Divider 2.1

Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x19A [7:4] Phase Offset Divider 2.2

Refer to LVDS/CMOS channel divider function description (default = 0x0).

[3:0] Phase Offset Divider 2.1

0x19B [7:4] Low Cycles Divider 2.2

Number of clock cycles (minus 1) of 2.2 divider input during which 2.2 output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0] High Cycles Divider 2.2

Number of clock cycles (minus 1)of 2.2 divider input during which 2.2 output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x19C

5

4

3

2

1

0

Bypass Divider 2.2

Bypass Divider 2.1

Divider 2 nosync

Bypasses (and powers down) 2.2 divider logic, routes clock to 2.2 output.

0: does not bypass (default).

1: bypasses.

Bypasses (and powers down) 2.1 divider logic, routes clock to 2.1 output.

0: does not bypass (default).

1: bypasses.

No sync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Forces Divider 2 output high. Requires that nosync also be set.

0: forces low (default).

Divider 2 force high

Start High Divider 2.2

Start High Divider 2.1

Divider 2 DCCOFF

1: forces high.

Divider 2.2 start high/low.

0: starts low (default).

1: starts high.

Divider 2.1 start high/low.

0: starts low (default).

1: starts high.

0x19D

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

0x19E [7:4] Low Cycles Divider 3.1

[3:0] High Cycles Divider 3.1

Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

Rev. F | Page 73 of 80

AD9517-2

Data Sheet

Reg.

Addr.

(Hex)

Bits

Name

Description

0x19F [7:4] Phase Offset Divider 3.2

[3:0] Phase Offset Divider 3.1

Refer to LVDS/CMOS channel divider function description (default = 0x0).

0x1A0 [7:4] Low Cycles Divider 3.2

Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low.

A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).

[3:0] High Cycles Divider 3.2

Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays high.

A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).

0x1A1

5

4

3

2

1

0

Bypass Divider 3.2

Bypass Divider 3.1

Divider 3 nosync

Bypasses (and powers down) 3.2 divider logic; routes clock to 3.2 output.

0: does not bypass (default).

1: bypasses.

Bypasses (and powers down) 3.1 divider logic; routes clock to 3.1 output.

0: does not bypass (default).

1: bypasses.

Nosync.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Forces Divider 3 output high. Requires that nosync also be set.

0: forces low (default).

Divider 3 force high

Start High Divider 3.2

Start High Divider 3.1

Divider 3 DCCOFF

1: forces high.

Divider 3.2 start high/low.

0: starts low (default).

1: starts high.

Divider 3.1 start high/low.

0: starts low (default).

1: starts high.

0x1A2

Duty-cycle correction function.

0: enables duty-cycle correction (default).

1: disables duty-cycle correction.

Rev. F | Page 74 of 80

Data Sheet

AD9517-2

Table 60. VCO Divider and CLK Input

Reg.

Addr

(Hex) Bits

Name

Description

0x1E0 [2:0]

VCO divider

2

0

1

0

1

0

1

0

1

0

1

Divide

2.

3.

4 (default).

5.

6.

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

1

0

1

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

Output static. Note that setting the VCO divider static should occur only

after VCO calibration.

0x1E1

4

3

2

1

Power down clock input section

Power down VCO clock interface

Power down VCO and CLK

Select VCO or CLK

Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).

0: normal operation (default).

1: power-down.

Powers down the interface block between VCO and clock distribution.

0: normal operation (default).

1: power-down.

Powers down both VCO and CLK input.

0; normal operation (default).

1: power-down.

Selects either the VCO or the CLK as the input to VCO divider.

0: selects external CLK as input to VCO divider (default).

1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is

selected.

0

Bypass VCO divider

Bypasses or uses the VCO divider.

0: uses VCO divider (default).

1: bypasses VCO divider; cannot select VCO as input when this is selected.

Table 61. System

Reg.

Addr.

(Hex) Bits Name

Description

0x230

2

1

0

Power down sync

Powers down the sync function.

0: normal operation of the sync function (default).

1: powers down sync circuitry.

Power down distribution reference Powers down the reference for distribution section.

0: normal operation of the reference for the distribution section (default).

1: powers down the reference for the distribution section.

Soft sync

The soft sync bit works the same as the SYNC pin, except that the polarity of the bit

is reversed. That is, a high level forces selected channels into a predetermined static

state, and a 1-to-0 transition triggers a sync.

0: same as SYNC high (default).

1: same as SYNC low.

Table 62. Update All Registers

Reg.

Addr

(Hex) Bits Name

Description

0x232

0

Update all registers

This bit must be set to 1b to transfer the contents of the buffer registers into the active

registers. This bit is self-clearing; that is, it does not have to be set back to 0b.

1 (self-clearing): updates all active registers to the contents of the buffer registers.

Rev. F | Page 75 of 80

AD9517-2

Data Sheet

APPLICATIONS INFORMATION

on the sampling clock. Considering an ideal ADC of infinite

resolution where the step size and quantization error can be

ignored, the available SNR can be expressed approximately by

FREQUENCY PLANNING USING THE AD9517

The AD9517 is a highly flexible PLL. When choosing the PLL

settings and version of the AD9517, keep in mind the following

guidelines.













1

SNR(dB)  20log

2f_At_J

The AD9517 has the following four frequency dividers: the

reference (or R) divider, the feedback (or N) divider, the VCO

divider, and the channel divider. When trying to achieve a

particularly difficult frequency divide ratio requiring a large

amount of frequency division, some of the frequency division

can be done by either the VCO divider or the channel divider,

thus allowing a higher phase detector frequency and more

flexibility in choosing the loop bandwidth.

where:

f_Ais the highest analog frequency being digitized.

t_Jis the rms jitter on the sampling clock.

Figure 70 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

110

18

1

SNR = 20log

2πf_At_J

100

90

80

70

60

50

40

30

Within the AD9517 family, lower VCO frequencies generally

result in slightly lower jitter. The difference in integrated jitter

(from 12 kHz to 20 MHz offset) for the same output frequency

is usually less than 150 fs over the entire VCO frequency range

(1.45 GHz to 2.95 GHz) of the AD9517 family. If the desired

frequency plan can be achieved with a version of the AD9517

that has a lower VCO frequency, choosing the lower frequency

part results in the lowest phase noise and the lowest jitter.

However, choosing a higher VCO frequency may result in more

flexibility in frequency planning.

16

14

12

10

8

t_J

=

0

1

0

f_S

2

0

f_S

4

0

1

2

p

s

p

1

0

p

s

6

10

100

f_A(MHz)

1k

Choosing a nominal charge pump current in the middle of the

allowable range as a starting point allows the designer to increase

or decrease the charge pump current, and thus allows the

designer to fine-tune the PLL loop bandwidth in either

direction.

Figure 70. SNR and ENOB vs. Analog Input Frequency

See the AN-756 Application Note, Sampled Systems and the Effects

of Clock Phase Noise and Jitter; and the AN-501 Application Note,

Aperture Uncertainty and ADC System Performance, at

www.analog.com.

ADIsimCLK is a powerful PLL modeling tool that can be

downloaded from www.analog.com. It is a very accurate tool for

determining the optimal loop filter for a given application.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. (Distributing a single-ended clock on a noisy PCB

may result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.) The

AD9517 features both LVPECL and LVDS outputs that provide

differential clock outputs, which enable clock solutions that

maximize converter SNR performance. The input requirements

of the ADC (differential or single-ended, logic level,

USING THE AD9517 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed ADC is extremely sensitive to the quality of its

sampling clock. An ADC can be thought of as a sampling

mixer, and any noise, distortion, or timing jitter on the clock is

combined with the desired signal at the analog-to-digital

output. Clock integrity requirements scale with the analog

input frequency and resolution, with higher analog input

frequency applications at ≥14-bit resolution being the most

stringent. The theoretical SNR of an ADC is limited by the

ADC resolution and the jitter

termination) should be considered when selecting the best

clocking/converter solution.

Rev. F | Page 76 of 80

Data Sheet

AD9517-2

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter-follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue. In the case

shown in Figure 72, where VS_LVPECL = 2.5 V, the 50 Ω

termination resistor that is connected to ground should be

changed to 19 Ω.

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs of the AD9517 provide the lowest jitter

clock signals that are available from the AD9517. The LVPECL

outputs (because they are open emitter) require a dc termination

to bias the output transistors. The simplified equivalent circuit in

Figure 59 shows the LVPECL output stage.

In most applications, an LVPECL far-end Thevenin

termination (see Figure 71) or Y-termination (see Figure 72) is

recommended. In each case, the V_Sof the receiving buffer

should match the V_{S_LVPECL}voltage. If it does not, ac coupling is

recommended (see Figure 73). In the case of Figure 73, pull-

Thevenin-equivalent termination uses a resistor network to

provide 50 Ω termination to a dc voltage that is below V_OLof

the LVPECL driver. In this case, VS_LVPECL on the AD9517

should equal V_Sof the receiving buffer. Although the resistor

combination shown in Figure 72 results in a dc bias point of

VS_LVPECL − 2 V, the actual common-mode voltage is

VS_LVPECL − 1.3 V because additional current ﬂows from the

AD9517 LVPECL driver through the pull-down resistor.

down resistors of <150 Ω are not recommended when V_{S_LVEPCL}

3.3 V; if used, damage to the LVPECL drivers may result. The

minimum recommended pull-down resistor size for V_{S_LVPECL}

2.5 V is 100 Ω.

=

The resistor network is designed to match the transmission line

impedance (50 Ω) and the switching threshold (V_S− 1.3 V).

V

S_DRV

V

The circuit is identical when VS_LVPECL = 2.5 V, except that the

pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.

S_LVPECL

LVPECL

V

S

127Ω

50Ω

LVDS CLOCK DISTRIBUTION

SINGLE-ENDED

(NOT COUPLED)

LVPECL

The AD9517 provides four clock outputs (OUT4 to OUT7) that

are selectable as either CMOS or LVDS level outputs. LVDS is a

differential output option that uses a current mode output

stage. The nominal current is 3.5 mA, which yields 350 mV output

swing across a 100 Ω resistor. An output current of 7 mA is also

available in cases where a larger output swing is required. The

LVDS output meets or exceeds all ANSI/TIA/EIA-644

specifications.

50Ω

83Ω

Figure 71. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination

V

= 3.3V

S_LVPECL

LVPECL

S

Z

= 50Ω

0

A recommended termination circuit for the LVDS outputs is

shown in Figure 74.

50Ω

LVPECL

V

0

S

Figure 72. DC-Coupled 3.3 V LVPECL Y-Termination

100Ω

LVDS

DIFFERENTIAL (COUPLED)

V

S_LVPECL

S

0.1nF

Figure 74. LVDS Output Termination

100Ω DIFFERENTIAL

See the AN-586 Application Note, LVDS Data Outputs for

High-Speed Analog-to-Digital Converters for more information on

LVDS.

(COUPLED)

100Ω

LVPECL

0.1nF

200Ω

TRANSMISSION LINE

200Ω

Figure 73. AC-Coupled LVPECL with Parallel Transmission Line

Rev. F | Page 77 of 80

AD9517-2

Data Sheet

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9517 do not supply enough current

to provide a full voltage swing with a low impedance resistive,

far-end termination, as shown in Figure 76. The far-end

termination network should match the PCB trace impedance and

provide the desired switching point. The reduced signal swing

may still meet receiver input requirements in some

applications. This can be useful when driving long trace lengths

on less critical nets.

CMOS CLOCK DISTRIBUTION

The AD9517 provides four clock outputs (OUT4 to OUT7)

that are selectable as either CMOS or LVDS level outputs.

When selected as CMOS, each output becomes a pair of CMOS

outputs, each of which can be individually turned on or off and

set as noninverting or inverting. These outputs are 3.3 V CMOS

compatible.

Whenever single-ended CMOS clocking is used, some of the

following general guidelines should be used.

VS

Point-to-point nets should be designed such that a driver has

only one receiver on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net.

100Ω

50Ω

10Ω

CMOS

100Ω

Figure 76. CMOS Output with Far-End Termination

Series termination at the source is generally required to provide

transmission line matching and/or to reduce current transients

at the driver. The value of the resistor is dependent on the

board design and timing requirements (typically 10 Ω to 100 Ω is

used).

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9517 offers both LVPECL and

LVDS outputs that are better suited for driving long traces

where the inherent noise immunity of differential signaling

provides superior performance for clocking converters.

CMOS outputs are also limited in terms of the capacitive load

or trace length that they can drive. Typically, trace lengths of

less than 3 inches are recommended to preserve signal rise/fall

times and preserve signal integrity.

60.4Ω

(1.0 INCH)

10Ω

CMOS

MICROSTRIP

Figure 75. Series Termination of CMOS Output

Rev. F | Page 78 of 80

Data Sheet

AD9517-2

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

7.10

0.30

0.23

0.18

7.00 SQ

6.90

PIN 1

INDICATOR

AREA

PIN 1

IONS

INDICATOR AR EA OP T

(SEE DETAIL A)

37

36

48

1

0.50

BSC

5.65

EXPOSED

PAD

5.50 SQ

5.35

24

13

0.45

0.40

0.35

0.20 MIN

BOTTOM VIEW

5.50 REF

TOP VIEW

END VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD

Figure 77. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.75 mm Package Height

(CP-48-9)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-48-9

AD9517-2ABCPZ

AD9517-2ABCPZ-RL7

AD9517-2A/PCBZ

−40°C to +85°C

48-Lead Lead Frame Chip Scale Package (LFCSP)

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. F | Page 79 of 80

AD9517-2

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D06426-9/20(F)

Rev. F | Page 80 of 80


型号：	AD9517-2
厂家：	ADI
描述：	12-Output Clock Generator with Integrated 2.2 GHz VCO
文件：	总80页 (文件大小：844K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9517-2 [ADI]

相关型号：

AD9517-2A/PCBZ

AD9517-2ABCPZ

AD9517-2ABCPZ

AD9517-2ABCPZ-RL7

AD9517-2BCPZ

AD9517-3

AD9517-3ABCPZ

AD9517-3ABCPZ-RL7

AD9517-3BCPZ

AD9517-4

AD9517-4A/PCBZ

AD9517-4ABCPZ