AD9530BCPZ [ADI]
4 CML Output, Low Jitter Clock Generator;
| 型号： | AD9530BCPZ |
| 厂家： | 
ADI |
| 描述： | 4 CML Output, Low Jitter Clock Generator |
| 文件： | 总41页 (文件大小：979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4 CML Output, Low Jitter Clock Generator
with an Integrated 5.4 GHz VCO
Data Sheet
AD9530
FEATURES
GENERAL DESCRIPTION
Fully integrated, ultralow noise phase-locked loop (PLL)
4 differential, 2.7 GHz common-mode logic (CML) outputs
2 differential reference inputs with programmable internal
termination options
The AD9530 is a fully integrated PLL and distribution supporting,
clock cleanup, and frequency translation device for 40 Gbps/
100 Gbps OTN applications. The internal PLL can lock to one
of two reference frequencies to generate four discrete output
frequencies up to 2.7 GHz.
<232 fs rms absolute jitter (12 kHz to 20 MHz) with a non-
ideal reference and 8 kHz loop bandwidth
<100 fs rms absolute jitter (12 kHz to 20 MHz) with an 80 kHz
loop bandwidth and low jitter input reference clock
Supports low loop bandwidths for jitter attenuation
Manual switchover
The AD9530 features an internal 5.11 GHz to 5.4 GHz, ultralow
noise voltage controlled oscillator (VCO). All four outputs are
individually divided down from the internal VCO using two high
speed VCO dividers (the Mx dividers) and four individual 8-bit
channel dividers (the Dx dividers). The high speed VCO dividers
offer fixed divisions of 2, 2.5, 3, and 3.5 for wide coverage of
possible output frequencies. The AD9530 is configurable for
loop bandwidths <15 kHz to attenuate reference noise.
Single 2.5 V typical supply voltage
48-lead, 7 mm × 7 mm LFCSP
APPLICATIONS
40 Gbps/100 Gbps optical transport network (OTN) line side
clocking
The AD9530 is available in a 48-lead LFCSP and operates from a
single 2.5 V typical supply voltage.
Clocking of high speed analog-to-digital converters (ADCs)
and digital-to-analog converters (DACs)
Data communications
The AD9530 operates over the extended industrial temperature
range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
OUT1
AD9530
D1 DIVIDER
(1 TO 255)
OUT1
REFA
REFA
OUT2
D2 DIVIDER
(1 TO 255)
M1 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
OUT2
R DIVIDER
(1 TO 255)
800MHz MAX
PLL
OUT3
OUT3
REFB
REFB
D3 DIVIDER
(1 TO 255)
M2 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
OUT4
OUT4
D4 DIVIDER
(1 TO 255)
SERIAL PORT AND
CONTROL LOGIC
SDIO SDO SCLK CS
LD
CML 50Ω SOURCE TERMINATED
2.7GHz MAX
Figure 1.
Rev. 0
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www.analog.com
Tel: 781.329.4700
Technical Support
AD9530
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 27
Power Supply Recommendations............................................. 27
Using the AD9530 Outputs for ADC Clock Applications .... 27
Typical Application Block Diagram......................................... 28
Control Registers............................................................................ 29
Control Register Map Overview .............................................. 29
Control Register Map Descriptions ............................................. 31
SPI Configuration (Register 0x000 to Register 0x001) ......... 31
Status (Register 0x002) .............................................................. 32
Chip Type (Register 0x003) ...................................................... 32
Product ID (Register 0x004 to Register 0x005)...................... 32
Part Version (Register 0x006)................................................... 33
User Scratchpad 1 (Register 0x00A)........................................ 33
SPI Version (Register 0x00B).................................................... 33
Vendor ID (Register 0x00C to Register 0x00D)..................... 33
IO_UPDATE (Register 0x00F)................................................. 33
R Divider (Reference Input Divider) (Register 0x010) ......... 33
R Divider Control (Register 0x011)......................................... 34
Reference Input A (Register 0x012)......................................... 34
Reference Input B (Register 0x013) ......................................... 34
OUT1 Divider (Register 0x014)............................................... 35
OUT1 Driver Control Register (Register 0x015)................... 35
OUT2 Divider (Register 0x016)............................................... 35
OUT2 Driver Control (Register 0x017) .................................. 35
OUT3 Divider (Register 0x018)............................................... 36
OUT3 Driver Control (Register 0x019) .................................. 36
OUT4 Divider (Register 0x01A).............................................. 36
OUT4 Driver Control (Register 0x01B).................................. 36
VCO Power (Register 0x01C)................................................... 37
PLL Lock Detect Control (Register 0x01D) ........................... 37
PLL Lock Detect Readback (Registers 0x01E to 0x01F)....... 37
M1, M2, M3 Dividers (Register 0x020 to Register 0x022) ... 38
M3 Divider (Register 0x022) .................................................... 39
N Divider (Register 0x023) ....................................................... 39
N Divider Control (Register 0x024) ........................................ 39
Charge Pump (Register 0x025) ................................................ 39
Phase Frequency Dectector (Register 0x026)......................... 39
Loop Filter (Register 0x027) ..................................................... 40
VCO Frequency (Register 0x028)............................................ 40
User Scratchpad2 (Register 0x0FE) ......................................... 40
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Supply Voltage and Temperature Range.................................... 4
Supply Current.............................................................................. 4
Power Dissipation......................................................................... 5
REFA and REFB Input Characteristics...................................... 6
PLL Characteristics ...................................................................... 7
PLL Digital Lock Detect .............................................................. 7
Clock Outputs (Internal Termination Disabled) ..................... 7
Clock Outputs (Internal Termination Enabled)....................... 8
Clock Output Absolute Time Jitter (Low Loop
Bandwidth).................................................................................... 9
Clock Output Absolute Time Jitter (High Loop
Bandwidth).................................................................................. 10
RESET
and REF_SEL Pins ........................................................ 10
LD Pin .......................................................................................... 10
Serial Control Port ..................................................................... 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Detailed Functional Block Diagram ........................................ 18
Overview...................................................................................... 18
Configuration of the PLL .......................................................... 18
Reset Modes ................................................................................ 21
Power-Down Modes................................................................... 21
Input/Output Termination Recommendations.......................... 22
Serial Control Port.......................................................................... 23
SPI Serial Port Operation .......................................................... 23
Power Dissipation and Thermal Considerations ....................... 26
Clock Speed and Driver Mode ................................................. 26
Evaluation of Operating Conditions........................................ 26
Thermally Enhanced Package Mounting Guidelines............ 26
Rev. 0 | Page 2 of 41
Data Sheet
AD9530
User Scratchpad3 (Register 0x0FF) ..........................................40
Outline Dimensions........................................................................41
Ordering Guide ...........................................................................41
REVISION HISTORY
4/16—Revision 0: Initial Version
Rev. 0 | Page 3 of 41
AD9530
Data Sheet
SPECIFICATIONS
Typical values are given for VDD = 2.5 V 5%, TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD
range and TA (−40°C to +85°C) variations listed in Table 1.
SUPPLY VOLTAGE AND TEMPERATURE RANGE SPECIFICATIONS
Table 1.
Parameter
Symbol
Min
Typ Max
Unit Test Conditions/Comments
SUPPLY VOLTAGE
VDD
2.375 2.5
2.625
V
2.5 V 5%
TEMPERATURE
Ambient Temperature Range
Junction Temperature1
TA
TJ
−40
+25 +85
°C
°C
115
1 The is the maximum junction temperature for which device performance is guaranteed. Note that the Absolute Maximum Ratings section may have a higher
maximum junction temperature, but device operation or performance is not guaranteed above the number that appears here. To calculate the junction temperature,
see the Power Dissipation and Thermal Considerations section.
SUPPLY CURRENT SPECIFICATIONS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY CURRENT OTHER THAN CLOCK THE
DISTRIBUTION CHANNEL
Current listed in the Typ column is at nominal VDD at
25°C; current listed in the Max column is at
maximum VDD and worst case temperature
Typical Operation 1
fRTWO = 5300.16 MHz; VCO mode = low power;
REFA enabled at 110.42 MHz; REFB disabled;
R divider = 1; M1 and M3 divider = 3; M2 divider =
powered down; phase frequency detector (PFD) =
110.42 MHz; OUT1 CML output at 1766.72 MHz;
OUT2, OUT3, and OUT4 outputs and dividers
powered down; single-ended output swing level =
800 mV; outputs terminated externally with 50 Ω
to VDD
Reference Input VDD (Pin 3 and Pin 7)
PLL VDD (Pin 12)
8.2
10.7
24
mA
mA
mA
Combined current of Pin 3 and Pin 7
18.2
747
Rotary Travelling Wave Oscillator (RTWO) VDD
(Pin 20 to Pin 23)
860
Combined current of Pin 20 to Pin 23
SUPPLY CURRENT FOR AN INDIVIDUAL CLOCK
DISTRIBUTION CHANNEL
Each output channel has a dedicated VDD pin; all
current values are listed for a single driver supply
pin operating at 1766.72 MHz; output terminated
externally, 50 Ω to VDD; these specifications include
the current required for the external load resistors
CML
Internal Termination Disabled
800 mV
900 mV
28.8
30.7
32.6
34.5
35.5
37.6
39.8
41.8
mA
mA
mA
mA
1000 mV
1100 mV
Internal Termination Enabled
800 mV
47.6
51.5
55.3
59.0
57.2
61.5
65.8
70.1
mA
mA
mA
mA
900 mV
1000 mV
1100 mV
Rev. 0 | Page 4 of 41
Data Sheet
AD9530
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CURRENT DELTAS, INDIVIDUAL FUNCTIONS
Current delta when a function is enabled/disabled
from Typical Operation 1
VCO High Performance Mode Enabled
REFx/REFx Receiver1
133.5 160.0 mA
Current increase when the VCO mode is changed
from low power mode to high performance mode;
combined current delta of Pin 20 to Pin 23
2.5
3.3
mA
mA
Current increase when REFB is enabled with a
110.42 MHz reference input; combined current
delta of Pin 3 and Pin 7
Reference Divider
−0.55 −0.39
Delta from bypassing reference divider to using
reference divider = 2; total feedback division
doubled to preserve lock; combined current delta
of Pin 3 and Pin 7
Output Channel
28.4
33.3
mA
One output channel enabled by powering up
M2 divider = 3; D3 and D4 divider = 1; OUT3 and
OUT4 enabled to 800 mV; no internal termination;
associated low-dropout regulators (LDOs)
enabled; includes the current required by the
external termination; both outputs at 1766.72 MHz
Mx Divider On/Off
33.2
28.4
36.2
33.4
mA
mA
This is the current consumption delta between
an Mx (where x is 0, 1, or 2) divider powered up
and powered down; these dividers are a part of
the RTWO VDD (Pin 20 to Pin 23) power domain
Single Output Plus Associated Channel Divider
(OUT1: Pin 31, OUT2: Pin 35, OUT3: Pin 41,
OUT4: Pin 45)
One output driver enabled by powering up the
driver and channel divider (does not include
power on the extra M2 divider); includes the
current required by the external termination;
output = 1766.72 MHz
1 Where x is either A or B.
POWER DISSIPATION SPECIFICATIONS
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
TOTAL POWER DISSIPATION
Does not include power dissipated in external resistors;
all CML outputs terminated with 50 Ω to VDD; internal
output termination is disabled; output amplitude set
to 1.0 V; reference inputs set to ac-coupled mode
Power-On Default
Power-Down Mode
Typical Operation 2
2.284
0.338
2.344
2.750
W
W
W
0.480
2.82
fRTWO = 5302.5 MHz; VCO mode = high performance;
REFA enabled at 101 MHz, ac-coupled; REFB disabled;
R divider = 1; M1 divider and M3 divider = 2.5;
PFD = 101 MHz; OUT1 and OUT2 CML outputs at
2121 MHz; OUT3 and OUT4 disabled; output swing
level = 800 mV; outputs terminated externally to 50 Ω
to VDD and internal termination disabled; M2 divider
and LDO powered down; D3 and D4 dividers and
associated LDOs disabled
All Blocks Running
fRTWO = 5400 MHz; VCO mode = high performance;
REFA and REFB enabled at 100 MHz; ac-coupled mode;
R divider = 1; M divider = 2; PFD = 100 MHz; four CML
outputs at 2700 MHz
800 mV Output Swing, Without
Internal Output Termination
2.536
2.796
3.02
W
W
Single-ended output swing level = 800 mV and
internal termination off
1100 mV Output Swing with Internal
Output Termination
3.326
Single-ended output swing level = 1100 mV and
internal termination on
Rev. 0 | Page 5 of 41
AD9530
Data Sheet
REFA/REFA AND REFB/REFB INPUT CHARACTERISTICS
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC-COUPLED LVDS MODE (REFA, REFA;
REFB, REFB)
DC-coupled LVDS mode (REFx_TERM_SEL = 00);
includes an internal 100 Ω differential termination;
inputs are not self biased in this setting
Input Frequency
Input Sensitivity
6
800
MHz
Assumes a minimum of 494 mV p-p differential
amplitude as measured with a differential probe at
the REFx input pins
494
0.4
mV p-p
Peak-to-peak differential voltage swing across the
pins to ensure switching between logic levels as
measured with a differential probe
Common-Mode Input Voltage
Differential Input Resistance
1.4
V
Allowable common-mode voltage for dc coupling
110
3
Ω
Differential input resistance measured across the REFx
and REFx pins
Input Capacitance
pF
Input capacitance measured from each REFx pin to GND
DC-COUPLED CML MODE (REFA, REFA,
REFB, REFB)
DC-coupled (REFx_TERM_SEL = 01); includes an internal
termination of 50 Ω from each REFx input to GND;
inputs are not self biased in this setting
Input Frequency
Input Sensitivity
6
800
0.4
MHz
Assumes a minimum of 494 mV p-p differential
amplitude as measured with a differential probe at
the REFx input pins
494
0.3
mV p-p
Peak-to-peak differential voltage swing across pins to
ensure switching between logic levels as measured
with a differential probe
Common-Mode Input Voltage
Single-Ended Input Resistance
Input Capacitance
V
Allowable common-mode voltage for dc coupling
Input resistance measured from each REFx pin to GND
Input capacitance measured from each REFx pin to GND
55
3
Ω
pF
AC-COUPLED CML MODE (REFA, REFA,
REFB, REFB)
AC-coupled mode (REFx_TERM_SEL = 10); includes an
internal termination of 50 Ω from each REFx input to a
nominal dc bias of 0.35 V
Input Frequency
Input Sensitivity
6
800
MHz
Assumes a minimum of 494 mV p-p differential
amplitude as measured with a differential probe at
the REFx input pins
494
0.32
mV p-p
Peak-to-peak differential voltage swing across pins to
ensure switching between logic levels as measured
with a differential probe
Input Self Bias Voltage (VTT)
(Internally Generated)
0.355
105
3
0.39
V
Self bias voltage of the REFx and REFx inputs in ac-
coupled mode (REFx_TERM_SEL = 10)
Differential Input Resistance
Ω
pF
Differential input resistance measured across the REFx
and REFx pins
Input Capacitance
Input capacitance measured from each REFx pin to GND
DC-COUPLED HIGH-Z MODE (REFA, REFA,
REFB, REFB)
DC-coupled high-Z mode (REFx_TERM_SEL = 11) places
the REFx inputs into a high impedance state; inputs
are not self biased in this setting
Input Frequency
Input Sensitivity
6
800
1.4
MHz
Assumes a minimum of 500 mV p-p differential
amplitude as measured with a differential probe at
the REFx input pins
494
0.4
mV p-p
Peak-to-peak differential voltage swing across pins to
ensure switching between logic levels as measured
with a differential probe
Common-Mode Input Voltage
Differential Input Resistance
V
10.3
3
kΩ
Differential input resistance measured across the REFx
and REFx pins
Input Capacitance
pF
Input capacitance measured from each REFx pin to GND
Rev. 0 | Page 6 of 41
Data Sheet
AD9530
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DUTY CYCLE
Duty cycle bounds are set by pulse width high and pulse
width low
Pulse Width
Low
600
600
ps
ps
High
PLL CHARACTERISTICS
Table 5.
Parameter
RTWO
Min Typ Max Unit
Test Conditions/Comments
Frequency Range
5.11
5.4
GHz
VCO Gain (KVCO
)
180
MHz/V
PHASE FREQUENCY DETECTOR (PFD)
PFD Input Frequency
6
6
800
500
MHz
MHz
Antibacklash pulse width disabled (Register 0x026, Bit 1 = 0)
Antibacklash pulse width enabled (Register 0x026, Bit 1 = 1)
CHARGE PUMP (CP)
Sink/Source Current (ICP)
0.05
2.6
3.2
mA
µF
Register 0x025, Bits[5:0] controls the charge pump current (see
Table 56)
LOOP FILTER
External Loop Filter Capacitor
Maximum value for the C2 capacitor in Figure 16; using a loop filter
capacitor value larger than the maximum may affect device
functionality
POWER-ON RESET (POR) TIMER
Internal Wait Time
2
sec
Minimum wait time implemented before issuing the first RTWO
calibration after a POR
PLL DIGITAL LOCK DETECT SPECIFICATIONS
Table 6.
Parameter
PLL DIGITAL LOCK DETECT WINDOW1
Min
0.020
Typ Max Unit Test Conditions/Comments
Signal available at the LD pin and in Register 0x01F, Bit 2
Lock Threshold
300 ppm Lock threshold is selected by Register 0x01D, Bits[3:1], which is
the threshold for transitioning from unlock to lock and vice
versa
1 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the lock detector update interval (see Table 48).
CLOCK OUTPUTS (INTERNAL TERMINATION DISABLED) SPECIFICATIONS
Table 7.
Parameter
CML MODE
800 mV
Min
Typ
Max Unit Test Conditions/Comments
All outputs are externally terminated with 50 Ω to VDD
Output Frequency
5.725
2700 MHz
Rise Time/Fall Time (20% to 80%)
Duty Cycle
78
107
53
54
57
53
ps
%
%
%
%
47
48
45
48
Any Mx divider, output divider ≠ 1
Mx divider = 2, output divider = 1
Mx divider = 2.5, output divider = 1
Mx divider = 3, output divider = 1
51
51
50
Output Differential Voltage, Magnitude 600
845
1090 mV
Voltage difference between the output pins; output driver is
static; in normal operation, the peak-to-peak amplitude is
approximately 2× this value if measured with a differential probe
Common-Mode Output Voltage
1.82
2.075 2.32
V
Measured with output driver static
Rev. 0 | Page 7 of 41
AD9530
Data Sheet
Parameter
Min
Typ
Max Unit Test Conditions/Comments
All outputs are externally terminated with 50 Ω to VDD
900 mV
Output Frequency
5.725
2700 MHz
Rise Time/Fall Time (20% to 80%)
Duty Cycle
77
98
53
54
57
53
ps
%
%
%
%
47
48
45
49
Any Mx divider, output divider ≠ 1
Mx divider = 2, output divider = 1
Mx divider = 2.5, output divider = 1
Mx divider = 3, output divider = 1
51
51
51
Output Differential Voltage, Magnitude 675
950
1340 mV
Voltage difference between the output pins; output driver is
static; in normal operation, the peak-to-peak amplitude is
approximately 2× this value if measured with a differential probe
Common-Mode Output Voltage
1000 mV
1.76
2.03
76
2.29
V
Measured with output driver static
All outputs are externally terminated with 50 Ω to VDD
Output Frequency
5.725
2700 MHz
Rise Time/Fall Time (20% to 80%)
Duty Cycle
105
53
54
57
52
ps
%
%
%
%
47
48
45
49
Any Mx divider, output divider ≠ 1
Mx divider = 2, output divider = 1
Mx divider = 2.5, output divider = 1
Mx divider = 3, output divider = 1
51
51
51
Output Differential Voltage, Magnitude 730
1040 1340 mV
Voltage difference between the output pins; output driver is
static; in normal operation, the peak-to-peak amplitude is
approximately 2× this value if measured with a differential probe
Common-Mode Output Voltage
1100 mV
1.69
1.97
76
2.25
V
All outputs are externally terminated with 50 Ω to VDD
Output Frequency
5.725
2700 MHz
Rise Time/Fall Time (20% to 80%)
Duty Cycle
104
53
54
57
52
ps
%
%
%
%
47
48
45
49
Any Mx divider, output divider ≠ 1
Mx divider = 2, output divider = 1
Mx divider = 2.5, output divider = 1
Mx divider = 3, output divider = 1
51
51
50
Output Differential Voltage, Magnitude 815
1140 1480 mV
Voltage difference between the output pins; output driver is
static; in normal operation, the peak-to-peak amplitude is
approximately 2× this value if measured with a differential probe
Common-Mode Output Voltage
1.61
1.92
2.22
V
Measured with output driver static
CLOCK OUTPUTS (INTERNAL TERMINATION ENABLED) SPECIFICATIONS
Table 8.
Parameter
CML MODE
800 mV
Min
Typ
Max Unit Test Conditions/Comments
All outputs are externally terminated with 50 Ω to VDD
Output Frequency
5.725
2700 MHz
Rise Time/Fall Time (20% to 80%)
Duty Cycle
55
75
53
56
60
53
ps
%
%
%
%
47
48
43
48
590
Any Mx divider, output divider ≠ 1
Mx divider = 2, output divider = 1
Mx divider = 2.5, output divider = 1
Mx divider = 3, output divider = 1
52
51
51
Output Differential Voltage, Magnitude
Common-Mode Output Voltage
830
1070 mV
Voltage difference between the output pins; output driver is
static; in normal operation, the peak-to-peak amplitude is
approximately 2× this value if measured with a differential probe
1.9
2.08
2.26
V
Measured with output driver static
Rev. 0 | Page 8 of 41
Data Sheet
AD9530
Parameter
Min
Typ
Max Unit Test Conditions/Comments
All outputs are externally terminated with 50 Ω to VDD
900 mV
Output Frequency
5.725
2700 MHz
Rise Time/Fall Time (20% to 80%)
Duty Cycle
53
70
53
56
60
53
ps
%
%
%
%
47
48
43
48
660
Any Mx divider, output divider ≠ 1
Mx divider = 2, output divider = 1
Mx divider = 2.5, output divider = 1
Mx divider = 3, output divider = 1
52
51
51
Output Differential Voltage, Magnitude
Common-Mode Output Voltage
930
1200 mV
Voltage difference between the output pins; output driver is
static; in normal operation, the peak-to-peak amplitude is
approximately 2× this value if measured with a differential probe
1.83
2.03
53
2.23
V
Measured with output driver static
1000 mV
All outputs are externally terminated with 50 Ω to VDD
Output Frequency
5.725
2700 MHz
Rise Time/Fall Time (20% to 80%)
Duty Cycle
71
53
56
60
53
ps
%
%
%
%
47
47
43
48
735
Any Mx divider, output divider ≠ 1
Mx divider = 2, output divider = 1
Mx divider = 2.5, output divider = 1
Mx divider = 3, output divider = 1
52
52
51
Output Differential Voltage, Magnitude
Common-Mode Output Voltage
1025 1335 mV
Voltage difference between the output pins; output driver is
static; in normal operation, the peak-to-peak amplitude is
approximately 2× this value if measured with a differential probe
1.83
2.03
53
2.23
V
Measured with output driver static
1100 mV
All outputs are externally terminated with 50 Ω to VDD
Output Frequency
5.725
2700 MHz
Rise Time/Fall Time (20% to 80%)
Duty Cycle
72
53
56
60
54
ps
%
%
%
%
47
47
43
48
810
Any Mx divider, output divider ≠ 1
Mx divider = 2, output divider = 1
Mx divider = 2.5, output divider = 1
Mx divider = 3, output divider = 1
52
52
51
Output Differential Voltage, Magnitude
Common-Mode Output Voltage
1125 1455 mV
Voltage difference between the output pins; output driver is
static; in normal operation, the peak-to-peak amplitude is
approximately 2× this value if measured with a differential probe
1.71
1.93
53.7
2.23
V
Measured with output driver static
Measured with output driver static
INTERNAL OUTPUTTERMINATION
RESISTANCE
Ω
CLOCK OUTPUT ABSOLUTE TIME JITTER (LOW LOOP BANDWIDTH) SPECIFICATIONS
Table 9.
Parameter
Min Typ Max Unit
Test Conditions/Comments
CML OUTPUT ABSOLUTE TIME JITTER
REFA enabled and ac-coupled; R divider = 1; Mx divider value varies;
loop bandwidth = 8 kHz; output divider bypassed unless otherwise
noted; single-ended output swing level = 1000 mV; no internal
termination; VCO in high power mode, integration bandwidth =
12 kHz to 20 MHz
fOUT = 2700 MHz
fOUT = 2100 MHz
fOUT = 2050 MHz
fOUT = 1768 MHz
fOUT = 1500 MHz
fOUT = 100 MHz
219
220
214
219
210
232
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Reference frequency = 100 MHz, Mx divider = 2
Reference frequency = 100 MHz, Mx divider = 2.5
Reference frequency = 102.5 MHz, Mx divider = 2.5
Reference frequency = 104 MHz, Mx divider = 3
Reference frequency = 100 MHz, Mx divider = 3.5
Reference frequency = 100 MHz, Mx divider = 3, output divider
(Dx divider) = 17
Rev. 0 | Page 9 of 41
AD9530
Data Sheet
CLOCK OUTPUT ABSOLUTE TIME JITTER (HIGH LOOP BANDWIDTH) SPECIFICATIONS
Table 10.
Parameter
Min Typ Max Unit
93 fs rms
Test Conditions/Comments
CML OUTPUT ABSOLUTE TIME JITTER
REFA enabled and ac-coupled; R divider = 1; Mx divider value = 2; loop
bandwidth = 80 kHz; output divider bypassed; single-ended output
swing level = 1000 mV; no internal termination; VCO in high power
mode; reference frequency = 860 MHz; output frequency = 2.58 GHz;
integration bandwidth = 12 kHz to 20 MHz; absolute jitter value also
depends on the noise of the input clock in the 12 kHz to 80 kHz range
RESET AND REF_SEL PINS SPECIFICATIONS
Table 11.
Parameter
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Voltage
Logic 1
VDD − 0.5
VDD
0.5
V
V
Logic 0
Current
Logic 1
1
µA
µA
pF
Logic 0
36
3
Capacitance
RESET TIMING
Pulse Width Low
100
50
ns
RESET Inactive to Start of Register Programming
ms
LD PIN SPECIFICATIONS
Table 12.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS
1 mA output load
Output Voltage
High
VOH
VOL
VDD − 0.5
V
V
Low
0.5
SERIAL CONTROL PORT SPECIFICATIONS
Table 13.
Parameter
CS (INPUT)
Input Voltage
Logic 1
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
CS has an internal 75 kΩ pull-up resistor
VDD − 0.4
V
V
Logic 0
0.4
Input Current
Logic 1
1
µA
µA
pF
Logic 0
32
3
Input Capacitance
SCLK (INPUT)
Input Voltage
Logic 1
SCLK has an internal 75 kΩ pull-down resistor
VDD − 0.4
V
V
Logic 0
0.4
Input Current
Logic 1
45
1
µA
µA
pF
Logic 0
Input Capacitance
3
Rev. 0 | Page 10 of 41
Data Sheet
AD9530
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SDIO (INPUT)
Input Voltage
Logic 1
VDD − 0.4
V
V
Logic 0
0.4
Input Current
Logic 1
1
1
3
µA
µA
pF
Logic 0
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Voltage
Logic 1
1 mA load current
VDD − 0.2
V
V
Logic 0
0.2
40
TIMING
See Figure 26 through Figure 30 and Table 21
Clock Rate (SCLK)
Pulse Width High
Pulse Width Low
SDIO to SCLK Setup
SCLK to SDIO Hold
SCLK to Valid SDIO and SDO
CS to SCLK Setup
CS to SCLK Hold
CS Minimum Pulse Width High
1/tSCLK
tHIGH
tLOW
tDS
MHz
ns
6
6
ns
1.8
0.6
ns
tDH
ns
tDV
10
ns
tS
0.6
3.5
1.5
ns
tH
ns
tPWH
ns
Rev. 0 | Page 11 of 41
AD9530
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 14.
THERMAL RESISTANCE
Parameter
Rating
Table 15. Thermal Resistance (Simulated)
Airflow
VDD, BP_CAP_1, BP_CAP_2, BP_CAP_3,
REFA, REFA, REFB, REFB, SCLK, SDIO,
SDO, CS, OUT1, OUT1, OUT2, OUT2,
OUT3, OUT3, OUT4, OUT4, RESET, and
REF_SEL to GND
2.625 V
Package
Type
Velocity
(m/sec)
1, 2
1, 3,4
1, 4, 5
1, 2, 4
θJA
θJC
θJB
ΨJT
Unit
48-Lead
LFCSP
0
25.8
22.2
19.7
2.8
7.5
0.20
N/A
N/A
°C/W
°C/W
°C/W
1.0
2.5
N/A
N/A
N/A
N/A
Junction Temperature1
150°C
Storage Temperature Range
Operating Temperature Range
Lead Temperature (10 sec)
−65°C to +150°C
−40°C to +85°C
300°C
1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-Std 883, Method 1012.1.
4 N/A means not applicable.
5 Per JEDEC JESD51-8 (still air).
1 See Table 15 for θJA.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 12 of 41
Data Sheet
AD9530
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
36 DNC
VDD
LF_1
DNC
35
3
VDD
34 OUT2
4
5
6
7
8
9
10
REFA
REFA
GND
33 OUT2
32
GND
31 VDD
30 OUT1
29
OUT1
28 GND
27 GND
AD9530
TOP VIEW
VDD
(Not to Scale)
REFB
REFB
GND
11
VDD 12
REF_SEL
26 BP_CAP_3
25 BP_CAP_2
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.
2. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT
MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO
ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE,
AND MECHANICAL STRENGTH BENEFITS.
Figure 2. Pin Configuration
Table 16. Pin Function Descriptions
Pin No. Mnemonic
Type1 Description
1
LF_1
O
Loop Filter Connection, Negative Output Side of the Active Loop Filter Op Amp. Connect the PLL active
loop filter components (R1, C1, and C2) to this pin and LF_2 (Pin 48).
2, 19,
36, 37,
46
DNC
N/A
Do Not Connect. Do not connect to this pin.
3
4
5
VDD
REFA
REFA
P
I
Power Supply for REFA.
Reference Clock Input A. This pin, along with REFA, is the first differential reference input for the PLL.
I
Complimentary Reference Clock Input A. This pin, along with REFA, is the first differential reference
input for the PLL.
6
7
8
9
GND
VDD
REFB
REFB
GND
Ground for the REFA Power Supply. Connect this pin to ground.
Power Supply for REFB.
P
I
Reference Clock Input B. This pin, along with REFB, is the second differential reference input for the PLL.
I
Complimentary Reference Clock Input B. This pin, along with REFB, is the second differential reference
input for the PLL.
10
11
GND
GND
I
Ground for the REFB Power Supply. Connect this pin to ground.
REF_SEL
Reference Input Select. This pin is the digital input to select REFA or REFB as the active reference to the
PLL. This pin has an internal 75 kΩ pull-up resistor. Logic high (default) selects REFA. Logic low selects REFB.
12
13
14
15
16
17
18
VDD
RESET
SDO
SDIO
SCLK
CS
P
I
Power Supply for the Serial Port Interface (SPI) and the PFD.
Chip Reset, Active Low. This pin has an internal 75 kΩ pull-up resistor.
Serial Control Port Unidirectional Serial Data Output. This pin is high impedance during 3-wire SPI mode.
Serial Control Port Bidirectional Serial Data Input/Output.
O
I/O
I
Serial Control Port Clock Signal. This pin has an internal 75 kΩ pull-down resistor.
Serial Control Port Chip Select, Active Low. This pin has an internal 75 kΩ pull-up resistor.
PLL Lock Detect Output.
I
LD
O
P
20 to
23
VDD
2.5 V Power Supply for the RTWO Internal LDO.
24
25
26
27
28
BP_CAP_1
BP_CAP_2
BP_CAP_3
GND
O
RTWO LDO Op Amp Bypass Capacitor. Connect an external 0.01 µF capacitor from this pin to GND.
RTWO LDO Bypass Capacitor. Connect an external 1 µF capacitor from this pin to GND.
RTWO Bias Supply Bypass Capacitor. This pin can be left unconnected (floating).
Ground for RTWO Power Supply. Connect this pin to ground.
O
O
GND
GND
GND
Ground for OUT1 Power Supply. Connect this pin to ground.
Rev. 0 | Page 13 of 41
AD9530
Data Sheet
Pin No. Mnemonic
Type1 Description
29
OUT1
O
CML Complementary Output 1. This pin requires a 50 Ω to VDD termination even if the output is
unused. See the CML Output Drivers section for more information.
30
OUT1
O
CML Output 1. This pin requires a 50 Ω termination to VDD, even if the output is unused. See the CML
Output Drivers section for more information.
31
32
33
34
35
38
39
40
41
42
43
44
45
47
48
VDD
P
Power Supply for OUT1.
GND
OUT2
OUT2
VDD
GND
O
Ground for OUT2 Power Supply. Connect this pin to ground.
CML Complementary Output 2.
O
CML Output 2.
P
Power Supply for OUT2.
GND
OUT3
OUT3
VDD
GND
O
Ground for OUT3 Power Supply. Connect this pin to ground.
CML Complementary Output 3.
O
CML Output 3.
P
Power Supply for OUT3.
GND
OUT4
OUT4
VDD
GND
O
Ground for OUT4 Power Supply. Connect this pin to ground.
CML Complementary Output 4.
O
CML Output 4.
P
Power Supply for OUT4.
LF_3
LF_2
O
Loop Filter Connection. Connect an external capacitor (CA) between this pin and ground.
O
Loop Filter Connection. This pin is the output side of the active loop filter op amp. Connect the PLL
active loop filter components (R1, C1, and C2) to this pin and LF_1 (Pin 1).
EP
GND
Exposed Pad. The exposed pad is a ground connection on the chip that must be soldered to the analog
ground of the printed circuit board (PCB) to ensure proper functionality and heat dissipation, noise, and
mechanical strength benefits.
1 O means output, N/A means not applicable, P means power, I means input, GND means ground, and I/O means input/output.
Rev. 0 | Page 14 of 41
Data Sheet
AD9530
TYPICAL PERFORMANCE CHARACTERISTICS
CML = 1.1V
CML = 1.0V
CML = 0.9V
CML = 0.8V
CML = 1.1V
CML = 1.0V
CML = 0.9V
CML = 0.8V
350mV/DIV
2.5ns/DIV
40.0GS/s IT 1.0ps/pt
A
CH1
–7.0mV
350mV/DIV
100ps/DIV
40.0GS/s IT 500fs/pt
A
CH1
42.0mV
Figure 3. CML Output Waveform (Differential) at 101 MHz,
Internal Termination Disabled
Figure 6. CML Output Waveform (Differential) at 2650 MHz,
Internal Termination Enabled
1.8
CML = 1.1V
CML = 1.0V
CML = 0.9V
CML = 0.8V
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
CML = 0.8V, TERMINATION ON
CML = 0.9V, TERMINATION ON
CML = 1.0V, TERMINATION ON
CML = 1.1V, TERMINATION ON
350mV/DIV
2.5ns/DIV
40.0GS/s IT 1.0ps/pt
A
CH1
–7.0mV
OUTPUT FREQUENCY (MHz)
Figure 4. CML Output Waveform (Differential) at 101 MHz,
Internal Termination Enabled
Figure 7. Differential Voltage Amplitude vs. Output Frequency, Internal
Termination Enabled
1.8
CML = 0.8V, TERMINATION OFF
CML = 0.9V, TERMINATION OFF
CML = 1.0V, TERMINATION OFF
CML = 1.1V, TERMINATION OFF
CML = 1.1V
CML = 1.0V
CML = 0.9V
CML = 0.8V
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
350mV/DIV
100ps/DIV
40.0GS/s IT 500fs/pt
A
CH1
42.0mV
OUTPUT FREQUENCY (MHz)
Figure 5. CML Output Waveform (Differential) at 2650 MHz,
Internal Termination Disabled
Figure 8. Differential Voltage Amplitude vs. Output Frequency,
Internal Termination Disabled
Rev. 0 | Page 15 of 41
AD9530
Data Sheet
–20
–30
–40
–50
–60
–70
–20
–30
1: 100Hz, –73.4750dBc/Hz
2: 1kHz, –66.6660dBc/Hz
3: 10kHz, –86.8162dBc/Hz
4: 100kHz, –115.4368dBc/Hz
5: 1MHz, –138.1587dBc/Hz
6: 10MHz, –151.7467dBc/Hz
7: 100MHz, –149.6761dBc/Hz
1: 100Hz, –77.9943dBc/Hz
2: 1kHz, –72.9378dBc/Hz
3: 10kHz, –90.9651dBc/Hz
4: 100kHz, –119.4690dBc/Hz
5: 1MHz, –141.9879dBc/Hz
6: 10MHz, –155.3944dBc/Hz
7: 100MHz, –161.6441dBc/Hz
–40
–50
–60
–70
2
2
–80
–80
1
1
–90
–100
–110
–120
–130
–90
3
3
–100
–110
–120
–130
–140
–150
–160
–170
–180
4
4
5
5
NOISE:
NOISE:
–140
–150
–160
–170
–180
7
ANALYSIS RANGE X: START 12kHz
STOP 20MHz
ANALYSIS RANGE X: START 10.006kHz
STOP 19.988MHz
INTG NOISE: –51.4221dBc/19.69MHz
RMS NOISE: 3.79671mRAD
217.536mdeg
INTG NOISE: –55.5777dBc/19.69MHz
RMS NOISE: 2.35304mRAD
134.819mdeg
7
6
6
RMS JITTER: 223.802fsec
RESIDUAL FM: 1.57236kHz
RMS JITTER: 211.82fsec
RESIDUAL FM: 1.03174kHz
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. Phase Noise, fOUT = 2.7 GHz, Loop Bandwidth = 8 kHz
Figure 12. Phase Noise, fOUT = 1.768 GHz, Loop Bandwidth = 8 kHz
–20
–20
1: 100Hz, –77.2438dBc/Hz
–30
1: 100Hz, –78.6193dBc/Hz
–30
2: 1kHz, –72.2169dBc/Hz
2: 1kHz, –73.4151dBc/Hz
–40
–50
3: 10kHz, –89.3822dBc/Hz
4: 100kHz, –118.0579dBc/Hz
5: 1MHz, –140.6235dBc/Hz
6: 10MHz, –153.7840dBc/Hz
7: 100MHz, –158.1045dBc/Hz
–40
–50
3: 10kHz, –92.6392dBc/Hz
4: 100kHz, –120.8504dBc/Hz
5: 1MHz, –143.4421dBc/Hz
6: 10MHz, –156.4311dBc/Hz
7: 100MHz, –160.8215dBc/Hz
–60
–60
–70
–70
2
–80
–80
2
1
1
–90
–90
3
3
–100
–110
–120
–130
–140
–150
–160
–170
–180
–100
–110
–120
–130
–140
–150
–160
–170
–180
4
4
5
5
NOISE:
NOISE:
ANALYSIS RANGE X: START 12kHz
STOP 20MHz
ANALYSIS RANGE X: START 12kHz
STOP 20MHz
7
INTG NOISE: –54.1475dBc/19.69MHz
RMS NOISE: 2.77421mRAD
158.951mdeg
INTG NOISE: –57.0182/19.69MHz
RMS NOISE: 1.99345mRAD
114.216mdeg
7
6
6
RMS JITTER: 210.252fsec
RESIDUAL FM: 1.23877kHz
RMS JITTER: 211.512fsec
RESIDUAL FM: 924.222kHz
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 10. Phase Noise, fOUT = 2.1 GHz, Loop Bandwidth = 8 kHz
Figure 13. Phase Noise, fOUT = 1.5 GHz, Loop Bandwidth = 8 kHz,
High Performance Mode
–20
–40
1: 100Hz, –76.5195dBc/Hz
–30
1: 1Hz, –94.3202dBc/Hz
–50
2: 1kHz, –72.1524dBc/Hz
2: 10kHz, –109.4110dBc/Hz
–40
–50
3: 10kHz, –90.4665dBc/Hz
4: 100kHz, –118.45978dBc/Hz
5: 1MHz, –141.0204dBc/Hz
6: 10MHz, –153.8759dBc/Hz
7: 100MHz, –164.4190dBc/Hz
3: 100kHz, –114.0837dBc/Hz
–60
4: 1MHz, –139.4227dBc/Hz
5: 10MHz, –151.9086dBc/Hz
–70
6: 40MHz, –157.7001dBc/Hz
–60
–80
–90
–70
2
–80
1
–100
–110
–120
–130
–140
–150
–160
–170
–180
1
–90
3
–100
–110
–120
–130
–140
–150
–160
–170
–180
2
3
4
5
NOISE:
NOISE:
4
ANALYSIS RANGE X: START 12kHz
STOP 20MHz
ANALYSIS RANGE X: START 12kHz
STOP 20MHz
6
INTG NOISE: –54.8028/19.69MHz
RMS NOISE: 2.57262mRAD
174.4mdeg
INTG NOISE: –59.5089dBc/19.69MHzMHz
RMS NOISE: 1.49648mRAD
85.7421mdeg
5
7
6
RMS JITTER: 199.729fsec
RESIDUAL FM: 1.22141kHz
RMS JITTER: 92.314fsec
RESIDUAL FM: 1.58172kHz
100
1k
10k
100k
1M
10M
100M
1k
10k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Phase Noise, fOUT = 2.05 GHz, Loop Bandwidth = 8 kHz
Figure 14. Phase Noise, fIN = 860 MHz, fOUT = 2.58 GHz,
Loop Bandwidth = 80 kHz, ICP = 2.4 mA, High Performance Mode
Rev. 0 | Page 16 of 41
Data Sheet
AD9530
TERMINOLOGY
Phase Jitter
Time Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time, and this
phenomenon is called phase jitter. Although many factors can
contribute to phase jitter, one major factor is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in seconds root
mean square (rms) or 1 sigma of the Gaussian distribution.
Phase jitter leads to a spreading out of the energy of the sine
wave in the frequency domain, producing a continuous power
spectrum. This power spectrum is usually reported as a series of
values whose units are dBc/Hz at a given offset in frequency
from the sine wave (carrier). The value is a ratio (expressed in
decibels) of the power contained within a 1 Hz bandwidth with
respect to the power at the carrier frequency. For each measurement,
the offset from the carrier frequency is also given.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that can be
attributed to the device or subsystem being measured. The phase
noise of any external oscillators or clock sources is subtracted,
making it possible to predict the degree to which the device
impacts the total system phase noise when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own phase noise to the total. In many cases, the
phase noise of one element dominates the system phase noise.
When there are multiple contributors to phase noise, the total is
the square root of the sum of squares of the individual contributors.
Absolute Phase Noise
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval; it is related to the time jitter due to the
phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of ADCs,
DACs, and RF mixers. It lowers the achievable dynamic range of
the converters and mixers, although they are affected in somewhat
different ways. Absolute phase noise is the actual measured
noise from the AD9530, and includes the input reference and
power supply noise.
Additive Time Jitter
Additive time jitter is the amount of time jitter that can be attri-
buted to the device or subsystem being measured. The time jitter of
any external oscillators or clock sources is not a part of this jitter
number. This makes it possible to predict the degree to which the
device impacts the total system time jitter when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own time jitter to the total. In many cases,
the time jitter of the external oscillators and clock sources
dominates the system time jitter.
Rev. 0 | Page 17 of 41
AD9530
Data Sheet
THEORY OF OPERATION
DETAILED FUNCTIONAL BLOCK DIAGRAM
REF_SEL
LF_1
LF_2
LF_3
BP_CAP_1
BP_CAP_2
BP_CAP_3
OUT1
OUT1
D1 DIVIDER
(1 TO 255)
OUT2
OUT2
D2 DIVIDER
(1 TO 255)
5.11GHz TO 5.4GHz
REFA
REFA
M1 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
CHARGE
PUMP
R DIVIDER
(1 TO 255)
PFD
REFB
REFB
M2 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
OUT3
OUT3
D3 DIVIDER
(1 TO 255)
V
REF
OUT4
OUT4
SDIO
SDO
SCLK
CS
D4 DIVIDER
(1 TO 255)
CONTROL
INTERFACE
(SPI)
N DIVIDER
(1 TO 255)
M3 DIVIDER
÷2, ÷2.5, ÷3, ÷3.5
LOCK
DETECTOR
AD9530
LD
Figure 15. Detailed Functional Block Diagram
Phase Frequency Detector (PFD)
OVERVIEW
The PFD takes inputs from the R divider output and the
feedback divider path to produce an output proportional to the
phase and frequency difference between them. The PFD includes
an adjustable delay element that controls the width of the anti-
backlash pulse. This pulse ensures that there is no dead zone in
the PFD transfer function and minimizes phase noise and
reference spurs.
The AD9530 is a fully integrated, integer-N PLL with an ultralow
noise, internal 5.11 GHz to 5.4 GHz RTWO capable of generating
<232 fs rms, (12 kHz to 20 MHz) jitter clocking signals with a
nonideal reference. The AD9530 is tailored for 40 Gbps and
100 Gbps OTN applications with stringent converter and ASIC
clocking specifications.
The AD9530 includes an on-chip PLL, an internal RTWO, and
four output channels with integrated dividers and CML drivers.
The PLL contains a partially internal active loop filter, which
requires a small number of external components to obtain loop
bandwidths lower than 15 kHz for reference phase noise
attenuation.
The maximum allowable input frequency into the PFD is specified
in the PFD parameter in Table 5.
Charge Pump (CP)
The CP is controlled by the PFD. The PFD monitors the phase
and frequency relationship between its two inputs and causes
the CP to pump up or pump down to charge or discharge, respec-
tively, the integrating node, which is part of the loop filter. The
integrated and filtered CP current is transformed into a voltage
that drives the tuning node of the RTWO to move the RTWO
frequency up or down. The CP current is programmable in 52 steps,
where each step corresponds to a current increase of 50 µA.
Calculate the CP current (ICP) by
The four outputs of the AD9530 feature individual dividers to
generate four separate frequencies up to 2.7 GHz.
CONFIGURATION OF THE PLL
Configuration of the PLL is accomplished by programming the
various settings for the R divider, N divider, M3 divider, charge
pump current, and a calibration of the RTWO. The combination of
these settings and the loop filter determine the PLL loop
bandwidth and stability.
ICP (µA) = 50 × (1 + x)
where x is the value written to Register 0x025, Bits[5:0].
Successful PLL operation and satisfactory PLL loop performance
are highly dependent on proper configuration of the internal PLL
settings and loop filter. ADIsimCLK™ is a free program that helps
the design and exploration of the capabilities and features of the
AD9530, including the design of the PLL loop filter.
Rev. 0 | Page 18 of 41
Data Sheet
AD9530
PLL Active Loop Filter
Use the ADIsimCLK design tool to design and simulate loop
filters with varying bandwidths.
The AD9530 active loop filter consists of an internal op amp,
internal passive components, and external passive components.
Proper loop filter configuration is application dependent. An
example of a second-order loop filter is shown in Figure 16.
PLL Reference Inputs
The AD9530 features two fully differential PLL reference inputs
that are routed through a 2:1 mux to a common R divider. The
differential reference input receiver has four internal termination/
biasing options to accommodate many input logic types. A
functional diagram of the reference input receiver is shown in
Figure 17. Table 18 details the four possible reference input
termination and common-mode settings achievable by writing
to Register 0x012, Bits[3:2] and Register 0x013, Bits[3:2]. The
input frequency specifications for the reference inputs are listed
in Table 4.
ACTIVE LOOP FILTER WITH DUAL PATH
OP AMP
BIAS
C
MAIN
VREF
V
V
TUNE_MAIN
TUNE_TEMP
R
MAIN
RTWO
C
IN
R
A_ONCHIP
LF_1
LF_2
C1
LF_3
OFF-CHIP
COMPONENTS
50Ω
C
A_OFFCHIP
10kΩ
R2
C2
VTT BIAS
GND
Figure 16. External Second-Order Loop Filer Configuration
10kΩ
50Ω
C1, C2, CA_OFFCHIP, and R2 are external components required for
proper loop filter operation. All internal loop filter components
(RMAIN, RA_ONCHIP, CMAIN) are fixed with the exception of CIN, which
has available settings of 5 pF to 192.5 pF by programming
Register 0x027, Bits[5:2]. This capacitance setting alters the
bandwidth of the loop filter op amp. CIN is composed of a fixed
5 pF capacitor and a bank of 15 selectable 12.5 pF capacitors.
Calculate the CIN value by
Figure 17. Reference Input Receiver Functional Diagram
REFx
Each REFx/
receiver can be disabled by setting the
associated reference enable bit to 0.
RTWO
The internal RTWO tunes from 5.11 GHz to 5.4 GHz and is
powered by the VDD supply pins (Pin 20 to Pin 23). The RTWO
has two modes: high performance mode and low power mode.
These modes are set by Register 0x01C, Bit 0. These modes
enable optimization between the phase noise performance and
power consumption. See the Power Supply Recommendations
section for a recommended power supply configuration for
Pin 20 to Pin 23.
CIN = 5 pF + 12.5 pF × Register 0x027, Bits[5:2]
Note that RMAIN and CMAIN in Figure 16 form a pole at
approximately 2 MHz.
Table 17 shows the typical loop filter component values and CP
settings for an 8 kHz loop bandwidth.
The maximum allowable capacitance value for the external loop
filter design is shown in Table 5. Exceeding this value may cause
various functions of the AD9530 to become unstable.
Table 17. Typical Loop Filter Components and ICP Settings for 8 kHz Loop Bandwidth
Reference (MHz)
R Divider
Feedback Divider (N × M3)
C1 (nF)
C2 (µF)
R2 (Ω)
CA_OFFCHIP (µF)
ICP (mA)
181.5
÷1
÷30
10
0.47
255
0.1
0.3
Table 18. Possible Reference Input Termination Settings
REFx/REFx Input Termination Select Settings
Mode Name
On-Chip Termination
100 Ω differential
50 Ω to GND
Common-Mode Bias
DC-Coupled LVDS
DC-Coupled, Internally Biased
AC-Coupled
00
High-Z
GND
01 (default)
10
11
50 Ω to 0.35 V
0.35 V
GND
DC-Coupled High-Z
10 kΩ to GND
Rev. 0 | Page 19 of 41
AD9530
Data Sheet
RTWO Calibration
and N dividers have individual resets located at Register 0x022,
Bit 0, and Register 0x024, Bit 0, respectively.
The RTWO calibration function selects the appropriate RTWO
frequency band for a given configuration. A calibration is
performed by toggling Register 0x001, Bit 2 from 0 to 1. The
command sequence to issue a VCO calibration is as follows:
M1 and M2 Dividers (M1 and M2)
The M1 and M2 dividers (Register 0x020, Bits[4:3] and
Register 0x021, Bits[4:3], respectively) have fixed divide
values of 2, 2.5, 3, and 3.5.
1. Write the desired AD9530 configuration, including the
divider and output driver settings.
The M1 and M2 dividers provide frequency division between the
RTWO output and the clock distribution channel dividers (Dx).
2. Set Register 0x001, Bit 2 = 0 (CALIBRATE VCO bit).
Note that this is a self clearing bit.
The M1 and M2 dividers have individual resets located at
Register 0x020, Bit 0, and Register 0x021, Bit 0, respectively.
A calibration is required after initial power-up, after subsequent
resets, and after any changes to the input reference frequency or
the divide settings that affect the RTWO operating frequency. A
2 sec wait timer is activated at power-up to gate the first calibration.
This wait time is not enforced for subsequent calibrations after
power-on. See the CML Output Drivers section for more
details. The PLL reference must be active and stable and the
PLL must be configured to a valid operational state prior to
issuing a calibration. After a calibration, all of the internal
dividers are synchronized automatically to ensure proper phase
alignment of the PLL and distribution.
Channel Dividers (Dx)
The AD9530 has four 8-bit channel dividers (Dx) which are
identical to the R and N dividers. Dx can be set to any value
from 1 to 255. Setting the divide value for D1 through D4 is
accomplished by writing Register 0x014, Register 0x016,
Register 0x018, and Register 0x01A, respectively. The D1 through
D4 reset bits that reset D1 through D4 are located in Bit 0 of
Register 0x015, Register 0x017, Register 0x019, and
Register 0x01B, respectively. A setting of 0 disables the divider.
Reference Switchover
Dividers Sync
The AD9530 supports two separate differential reference inputs.
Manual switchover is performed between these inputs by either
writing to Register 0x011, Bit 2 and Bit 1, or by using the REF_SEL
pin. Register 0x011, Bit 2 sets whether the REF_SEL pin or the
reference select register controls the reference input mux. Default
operation ignores the REF_SEL pin setting and uses the value of
Register 0x011, Bit 1.
Use a sync to phase align all of the AD9530 internal dividers to a
common point in time. A global sync of all dividers is performed
after a VCO calibration. To perform a VCO calibration, write a
1 to Bit 2 of Register 0x001. A VCO calibration must be
performed after power up, as well as any time a different VCO
frequency is selected.
To sync all of the dividers after programming them, without the
VCO frequency, write a 1 to Bit 1 of Register 0x001.
Dividers (R, Mx, N, and Dx)
The AD9530 contains multiple dividers that configure the PLL
for a given frequency plan. Each divider has an associated reset
bit that is self clearing. Resetting a divider is required every time
the divide value of that driver is changed. Issuing a reset of a
single divider does not clear the current divide value.
Lock Detector
The AD9530 features a frequency lock detect signal that
corresponds to whether the PLL reference and feedback edges are
within a certain frequency of one another. The exact frequency
lock threshold to indicate a PLL lock is user programmable in
Register 0x01D, Bits[3:1]. The three register bits allow the
frequency lock threshold to span 20 ppb to 300 ppm.
Reference Divider (R Divider)
The reference inputs are routed through a 2:1 mux into a
common 8-bit R divider. R can be set to any value from 1 to 255
(Register 0x010, Bits[7:0]). Setting Register 0x010 = 0x0A is
equivalent to an R divider setting of 10.
If the frequency error between the reference and feedback edges
is lower than the specified lock threshold, the LD pin goes high and
the PLL_LOCKED bit = 1. The LD pin and the PLL_LOCKED bit
go low when the error between the reference and feedback
edges is greater than the frequency lock threshold.
The frequency out of the R divider must not exceed the maximum
allowable frequency of the PFD listed in Table 5.
The lock detector also outputs an 11-bit word located in
Register 0x01E, Bits[7:0] and Register 0x01F, Bits[1:0]. Bit 10
through Bit 0 contain a binary value representative of the measured
frequency lock error, and Bit 11 indicates whether the 10-bit
value is expressed in ppm (parts per million) or ppb (parts per
billion). Note that this 11th bit is found in Register 0x01F, Bit 3.
The R divider has its own reset located in Register 0x011. This
reset bit is self clearing.
M3 and N Feedback Dividers
The total feedback division from the RTWO to the PFD is the
product of the M3 and N dividers. The N divider (Register 0x023,
Bits[7:0]) functions identically to the R divider described in the
Reference Divider (R Divider) section. The M3 divider
(Register 0x022, Bits[3:2]) is limited to fixed divide values of 2,
2.5, 3, and 3.5 and acts as a prescaler to the N divider. The M3
Rev. 0 | Page 20 of 41
Data Sheet
AD9530
CML Output Drivers
the 2 sec counter finishes, the user can issue a VCO calibration
and outputs begin toggling ~500 ns later.
The AD9530 has four CML output drivers that are operable up to
2.7 GHz. Each output driver must be externally terminated as
shown in the Input/Output Termination Recommendations
section. The output voltage swing, internal termination, and
power-down of each CML driver are configurable by writing to
the appropriate registers. An initial calibration of the internal
termination and voltage swing is performed after a POR event.
This calibration requires that OUT1 is terminated, regardless of
whether the driver is needed in a specific design. A functional
diagram of the output driver is shown in Figure 18.
2 sec Wait Timer
The 2 sec wait timer ensures that all internal supplies are stable
before allowing the user to issue a VCO calibration. This timer
only starts after a POR. The user may program all the necessary
registers during this time, including the VCO calibration bit. After
the timer times out and a reference input is applied, the
calibration issues, allowing the PLL to lock and the outputs to
toggle. The maximum internal wait time is shown in Table 5.
RESET
Hardware Reset via the
Pin
V
DD
RESET
Driving the
pin to a Logic 0 and then back to a Logic 1
V
DD
restores the chip to the on-chip default register settings.
50Ω
50Ω
Soft Reset via the Serial Port
The serial port control register allows a soft reset by setting
Register 0x000, Bit 7 and Bit 1. When these bits are set, the chip
restores to the on-chip default settings, except for Register 0x000
and Register 0x001. Register 0x000 and Register 0x001 retain
the values prior to reset, except for the self clearing bits. However,
the self clearing operation does not complete until an additional
serial port SCLK cycle occurs; the AD9530 is held in reset until
this additional SCLK cycle.
MN2
MN3
MN0
MN1
18mA TO 24mA
18mA TO 24mA
Individual Divider Reset via the Serial Port
Figure 18. CML Output Simplified Equivalent Circuit
Every divider in the AD9530 has the ability to reset individually
by using the appropriate reset bit. This reset does not clear the
value written in the specific divider register but restarts the
divider count to 0, which results in a phase adjustment. See the
associated divider section or the register map for the location of
these bits.
The CML differential voltage (VOD) is selectable from 0.8 V to 1.1 V
via Bits[5:4] of Register 0x015, Register 0x017, Register 0x019,
and Register 0x01B.
The AD9530 has optional internal termination for cases where
transmission line impedance mismatch between the CML output
and the receiver causes increased reflections at high output
frequencies. These terminations improve impedance match
traces at high frequency at the expense of drawing twice as
much current as the default operating condition.
POWER-DOWN MODES
Sleep Mode via the Serial Port
Place the AD9530 in sleep mode by writing Register 0x002,
Bits[1:0] = 11. This mode powers down the following blocks:
For Register 0x015 (for OUT1), Register 0x017 (for OUT2),
Register 0x019 (for OUT3), and Register 0x01B (for OUT4),
setting the OUTx_TERM_EN (Bit 3) = 1 enables the on-chip
termination and is configurable for each driver.
•
•
•
•
•
•
•
All OUTx drivers
All REFx inputs
All Mx dividers
Each CML output can be enabled as needed by altering the
appropriate OUTx_ENABLE bit.
RTWO power set to minimum
CP current set to minimum
PFD
RESET MODES
Loop filter op amp
The AD9530 has a POR and several other ways to apply a reset
condition to the chip.
Individual Clock Input and Output Power-Down
Power down any of the reference inputs or clock distribution
outputs by individually writing to the appropriate registers. The
register map details the individual power-down settings for
each input and output.
Power-On Reset (POR)
During chip power-up, a POR pulse is issued when VDD
reaches ~2 V and restores the chip to the default on-chip
setting. At this point, a 2 sec counter is started to allow all the
user device settings to load and the RTWO to stabilize. After
Rev. 0 | Page 21 of 41
AD9530
Data Sheet
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
Figure 19 through Figure 24 illustrate the recommended input and output connections for connecting the AD9530 to other devices.
V
= 2.5V
V
= 2.5V
DD
V
DD
DD
0.1µF
0.1µF
V
= 2.5V
DD
50Ω
0.1µF
0.1µF
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
100Ω
HSTL
AD9530
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
50Ω
AD9530
CML
Figure 22. REFx Input Termination Recommendation for High Speed
Transceiver Logic (HSTL) Drivers
Figure 19. CML AC-Coupled Output Driver (External Termination Required
When Using the Internal Termination Option)
V
= 3.3V
V
= 2.5V
DD
V
= 2.5V
DD
DD
0.1µF
V
= 2.5V
V = V
S DD
DD
100Ω DIFFERENTIAL
50Ω
(COUPLED)
100Ω
LVPECL
AD9530
0.1µF TRANSMISSION LINE
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
50Ω
AD9530
CML
200Ω
200Ω
Figure 23. REFx Input Termination Recommendation for 3.3V LVPECL Drivers
Figure 20. CML DC-Coupled Output Driver (External Termination Required
When Using the Internal Termination Option)
V
V
DD
DD
V
= 2.5V
DD
V
V
DD
DD
50Ω
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
100Ω
LVDS
AD9530
100Ω DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
50Ω
CML
AD9530
Figure 24. REFx Input Termination Recommendation for 2.5V CML Drivers
Figure 21. REFx Input Termination Recommendation for LVDS Drivers
Rev. 0 | Page 22 of 41
Data Sheet
AD9530
SERIAL CONTROL PORT
The AD9530 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The serial control port allows read/write access to the AD9530
register map.
The following product specific items are defined in the unified
SPI protocol:
•
•
•
Analog Devices unified SPI protocol Revision: 1.0.
Chip type: 0x05 (0x05 indicates a clock chip).
Product ID: 10011b (in this case) uniquely identifies the
device as AD9530. No other Analog Devices clock IC
supporting unified SPI has this identifier.
Physical layer: 3-wire and 4-wire supported and 2.5 V
operation supported.
The AD9530 uses the Analog Devices, Inc., unified SPI protocol.
The unified SPI protocol guarantees that all new Analog Devices
products using the unified protocol have consistent serial port
characteristics. The SPI port configuration is programmable via
Register 0x0000. This register is a part of the SPI control logic
rather than in the register map.
•
•
•
•
Optional single-byte instruction mode: not supported.
Data link: not used.
SPI SERIAL PORT OPERATION
Control: not used.
Pin Descriptions
Communication Cycle—Instruction Plus Data
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 40 MHz.
The unified SPI protocol consists of a two part communication
cycle. The first part is a 16-bit instruction word that is coincident
with the first 16 SCLK rising edges and a payload. The instruction
word provides the AD9530 serial control port with information
W
regarding the payload. The instruction word includes the R/ bit
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB-first
and LSB-first data formats. Both the hardware configuration
and data format features are programmable. The 3-wire mode
uses the SDIO (serial data input/output) pin for transferring
data in both directions. The 4-wire mode uses the SDIO pin
for transferring data to the AD9530, and the SDO pin for
transferring data from the AD9530.
that indicates the direction of the payload transfer (that is, a
read or write operation). The instruction word also indicates
the starting register address of the first payload byte.
Write
If the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9530. Data
bits are registered on the rising edge of SCLK. Generally, it does
not matter what data is written to blank registers; however, it is
customary to use 0s. Note that there may be reserved registers
with default values not equal to 0x00; however, every effort was
made to avoid this.
CS
The
(chip select) pin is an active low control that gates read
CS
and write operations. Assertion (active low) of the
pin initiates a
write or read operation to theAD9530 SPI port. Any number of
data bytes can be transferred in a continuous stream. The register
address is automatically incremented or decremented based on the
Most of the serial port registers are buffered (see the Buffered/
Active Registers section for details on the difference between
buffered and active registers). Therefore, data written into
buffered registers does not take effect immediately. An additional
operation is needed to transfer buffered serial control port
contents to the registers that actually control the device. This
transfer is accomplished with an IO_UPDATE operation, which
is performed in one of two ways. One method is to write a Logic 1
to Register 0x00F, Bit 0 (this bit is an autoclearing bit). The user
can change as many register bits as desired before executing an
IO_UPDATE command. The IO_UPDATE operation transfers
the buffer register contents to their active register counterparts.
CS
setting of the address ascension bit (Register 0x0000).
must be
deasserted at the end of the last byte transferred, thereby ending
the stream mode. This pin is internally connected to a 10 kΩ pull-
CS
up resistor. When
is high, the SDIO and SDO pins go into a
high impedance state.
Implementation Specific Details
A detailed description of the unified SPI protocol can be found
at www.analog.com/ADISPI, which covers items such as timing,
command format, and addressing.
Rev. 0 | Page 23 of 41
AD9530
Data Sheet
Read
SPI MSB/LSB First Transfers
If the instruction word indicates a read operation, the next
N × 8 SCLK cycles clock out the data starting from the address
specified in the instruction word. N is the number of data bytes
read. The readback data is driven to the pin on the falling edge
and must be latched on the rising edge of SCLK. Blank registers
are not skipped over during readback.
The AD9530 instruction word and payload can be MSB first or
LSB first. The default for the AD9530 is MSB first. The LSB first
mode can be set by writing a 1 to Register 0x000, Bit 6 and Bit 1.
Immediately after the LSB first bit is set, subsequent serial
control port operations are LSB first.
Address Ascension
A readback operation takes data from either the serial control
port buffer registers or the active registers, as determined by
Register 0x001, Bit 5.
If the address ascension bit (Register 0x000, Bit 5 and Bit 2) = 0,
the serial control port register address decrements from the
specified starting address toward Address 0x0000.
SPI Instruction Word (16 Bits)
If the address ascension bit (Register 0x0000, Bit 5 and Bit 2) = 1,
the serial control port register address increments from the
starting address toward Address 0x0FF. Reserved addresses are
not skipped during multibyte input/output operations;
therefore, write the default value to a reserved register and 0s to
unmapped registers. Note that it is more efficient to issue a new
write command than to write the default value to more than
two consecutive reserved (or unmapped) registers.
W
The MSB of the 16-bit instruction word is R/ , which indicates
whether the instruction is a read or a write. The next 15 bits are
the register address (A14 to A0), which indicates the starting
register address of the read/write operation (see Table 20). Note
that, because there are no registers that require more than
13 address bits, A14 and A13 are ignored and treated as zeros.
Table 19. Streaming Mode (No Addresses Skipped)
Address Ascension
Increment
Stop Sequence
0x0000 … 0x1FFF
0x1FFF … 0x0000
Decrement
Table 20. Serial Control Port, 16-Bit Instruction Word
MSB
LSB
I0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
SCLK DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
SDIO
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA
Figure 25. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data
CS
SCLK
DON'T CARE
DON'T CARE
SDIO
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA
SDO DON'T CARE
16-BIT INSTRUCTION HEADER
DON'T
CARE
Figure 26. Serial Control Port Read—MSB First, Address Decrement, Four Bytes of Data
tDS
tHIGH
tS
tC
tCLK
tDH
tLOW
CS
DON'T CARE
DON'T CARE
DON'T CARE
SCLK
SDIO
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
Figure 27. Timing Diagram for Serial Control Port Write—MSB First
Rev. 0 | Page 24 of 41
Data Sheet
AD9530
CS
SCLK
tDV
SDIO
SDO
DATA BIT N
DATA BIT N – 1
Figure 28. Timing Diagram for Serial Control Port Register Read—MSB First
CS
SCLK DON'T CARE
DON'T CARE
DON'T CARE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA
DON'T CARE
SDIO
Figure 29. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data
tS
tC
CS
tCLK
tHIGH
tLOW
tDS
SCLK
SDIO
tDH
BIT N
BIT N + 1
Figure 30. Serial Control Port Timing—Write
Table 21. Serial Control Port Timing
Parameter
Description
tDS
tDH
tCLK
tS
Setup time between data and the rising edge of SCLK (see Figure 27 and Figure 30)
Hold time between data and the rising edge of SCLK (see Figure 27 and Figure 30)
Period of the clock (see Figure 27 and Figure 30)
CS
(see Figure 27 and Figure 30)
Setup time between the
falling edge and the SCLK rising edge (start of the communication cycle)
tC
CS
Setup time between the SCLK rising edge and rising edge (end of the communication cycle)
(see Figure 27 and Figure 30)
tHIGH
tLOW
tDV
Minimum period that SCLK is in a logic high state (see Figure 27 and Figure 30)
Minimum period that SCLK is in a logic low state (see Figure 27 and Figure 30)
SCLK to valid SDIO (see Figure 28)
Rev. 0 | Page 25 of 41
AD9530
Data Sheet
POWER DISSIPATION AND THERMAL CONSIDERATIONS
The AD9530 is a multifunctional, high speed device that targets
a wide variety of clock applications. The numerous innovative
features contained in the device each consume incremental power.
If all outputs are enabled in the maximum frequency and mode
that have the highest power, the safe thermal operating conditions
of the device may be exceeded. Careful analysis and consideration
of power dissipation and thermal management are critical
elements in the successful application of the AD9530.
CLOCK SPEED AND DRIVER MODE
Clock speed directly and linearly influences the total power
dissipation of the device and, therefore, the junction temperature.
Table 3 lists the currents required by the driver for a single
output frequency. If using the current vs. frequency graphs
provided in the Typical Performance Characteristics section,
subtract the power into the load using the following equation:
P
LOAD = (Differential Output Voltage Swing2/50 Ω)
The AD9530 is specified to operate within the industrial
temperature range of –40°C to +85°C. This specification is
conditional, such that the absolute maximum junction
temperature is not exceeded (as specified in Table 14). At
high operating temperatures, extreme care must be taken
when operating the device to avoid exceeding the junction
temperature and potentially damaging the device.
EVALUATION OF OPERATING CONDITIONS
The first step in evaluating the operating conditions is to
determine the AD9530 maximum power consumption for the
user configuration by referring to the values in Table 2. The
maximum PD excludes power dissipated in the load resistors of
the drivers because such power is external to the device. Use the
current dissipation specifications listed in Table 2, as well as the
power dissipation numbers in Table 3 to calculate the total
power dissipated for the desired configuration.
Many variables contribute to the operating junction temperature
within the device, including
•
•
•
•
Selected driver mode of operation
Output clock speed
The second step in evaluating the operating conditions is to
multiply the power dissipated by the thermal impedance to
determine the maximum power gradient. For this example, a
thermal impedance of θJA = 21.1°C/W is used.
Supply voltage
Ambient temperature
The combination of these variables determines the junction
temperature within the AD9530 for a given set of operating
conditions.
Example 1
Example 1 is as follows:
(1358 mW × 21.1°C/W) = 29°C
With an ambient temperature of 85°C, the junction temperature is
TJ = 85°C + 29°C = 114°C
The AD9530 is specified for an ambient temperature (TA). To
ensure that TA is not exceeded, use an airflow source.
Use the following equation to determine the junction
temperature on the application PCB:
This junction temperature is below the maximum allowable
temperature.
TJ = TCASE + (ΨJT × PD)
Example 2
where:
TJ is the junction temperature (°C).
Example 2 is as follows:
T
CASE is the case temperature (°C) measured at the top center of
the package.
JT is the value from Table 14.
(1630 mW × 21.1°C/W) = 34°C
With an ambient temperature of 85°C, the junction temperature is
TJ = 85°C + 34°C = 119°C
Ψ
PD is the power dissipation of the AD9530.
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the equation
This junction temperature is greater than the maximum allowable
temperature. The ambient temperature must be lowered by 4°C
to operate in the condition of Example 2.
TJ = TA + (θJA × PD)
THERMALLY ENHANCED PACKAGE MOUNTING
GUIDELINES
where TA is the ambient temperature (°C).
See the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP), for more
information about mounting devices with an exposed pad.
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of ΨJB are provided for package comparison and PCB
design considerations.
Rev. 0 | Page 26 of 41
Data Sheet
AD9530
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
Figure 32 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
The AD9530 only requires 2.5 V for operation, but proper isolation
between power domains is beneficial for performance. Figure 31
shows the recommended Analog Devices power solutions for
the best possible performance of the AD9530. These devices are
also featured on the evaluation board.
110
18
1
SNR = 20log
2πfAtJ
100
90
80
70
60
50
40
30
16
14
12
10
8
tJ
tJ
tJ
=
=
=
1
0
2
0
4
0
0
f
0
f
0
f
s
s
s
ADP7158
ADP2386
BUCK
(RECOMMENDED)
OR
3.4V
6V
INPUT
2.5V: VDD RTWO
(PINS 20 TO 23)
ADP1741
REGULATOR
tJ
tJ
LDO
=
=
1
2
p
s
s
p
ADM7154
LDO
2.5V: VDD OUT
AND VDD REF
(PIN 3, PIN 7, PIN 31,
PIN 35, PIN 41, PIN 45)
tJ
=
1
0
p
s
ADP151
LDO
2.5V: VDD DIGITAL
(PIN 12)
6
10
100
fA (MHz)
1k
Figure 31. Power Supply Recommendation
USING THE AD9530 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Figure 32. SNR and ENOB vs. Analog Input Frequency (fA)
For more information, see the AN-756 Application Note,
Sampled Systems and the Effects of Clock Phase Noise and Jitter,
and the AN-501 Application Note, Aperture Uncertainty and
ADC System Performance.
Any high speed ADC is extremely sensitive to the quality of the
sampling clock of the AD9530. An ADC can be thought of as a
sampling mixer, and any noise, distortion, or time jitter on the
clock is combined with the desired signal at the analog-to-digital
output. Clock integrity requirements scale with the analog input
frequency and resolution, with higher analog input frequency
applications at ≥14-bit resolution being the most stringent. The
theoretical SNR of an ADC is limited by the ADC resolution and
the jitter on the sampling clock. Considering an ideal ADC of
infinite resolution, where the step size and quantization error
can be ignored, the available SNR can be expressed
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. Distributing a single-ended clock on a noisy PCB can
result in coupled noise on the sampling clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.
The differential CML outputs of the AD9530 enable clock
solutions that maximize converter SNR performance.
approximately by
Consider the input requirements of the ADC (differential or single-
ended, logic level termination) when selecting the best clocking/
converter solution.
1
SNR(dB) 20log
2fAtJ
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Rev. 0 | Page 27 of 41
AD9530
Data Sheet
TYPICAL APPLICATION BLOCK DIAGRAM
AD9554
(QUAD CHANNEL DPLL)
AD9530
10 × 10Gbps
10 × 10Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
HIGH
SPEED
Tx DAC
NPU
OPTICAL
FRONT
END
TO NETWORK
FRAMER/
FEC
FRAMER/
TRAFFIC
PHY
MANAGEMENT
OPTICAL
MODULE
FPGA/ASIC
AD9554
(QUAD CHANNEL DPLL)
AD9530
DEMAPPING
CONTROL
10 × 10Gbps
10 × 10Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
25Gbps TO 28Gbps
HIGH
SPEED
Tx DAC
NPU
FROM NETWORK
OPTICAL
FRONT
END
FRAMER/
FEC
FRAMER/
PHY
TRAFFIC
MANAGEMENT
OPTICAL
MODULE
FPGA/ASIC
TRx
MODULES
3 × AD9554-1
(QUAD CHANNEL
DPLL)
10Gbps SERDES
Figure 33. Typical Application Block Diagram, 100 Gbps Muxponder with the AD9530
Rev. 0 | Page 28 of 41
Data Sheet
AD9530
CONTROL REGISTERS
CONTROL REGISTER MAP OVERVIEW
When writing to registers with bits that are marked reserved,
take care to always write the default value for the reserved bits.
Register addresses that are not listed in Table 22 are not used
and writing to those registers has no effect. Registers that are
marked as reserved must never have their values changed.
Unused and reserved registers are in the control register map
but are not in the control register description tables.
Table 22. Control Register Map
Reg.
Addr.
(Hex) Register Name Bit 7
Default
Value
(Hex)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB) Bit 0
0x000 SPI_CONFIGA
0x001 SPI_CONFIGB
0x002 STATUS
SOFT_RESET LSB_FIRST ADDRESS_ASCEND
SDO_ACTIVE
ADDRESS_
ASCEND
LSB_FIRST
SOFT_RESET
0x00
SINGLE_
INSTRUCTION
RESERVED READ_BUFFER
RESERVED
CALIBRATE VCO DIVIDER_RESET RESERVED
0x00
PLL_LOCKED SIGNAL_
PRESENT
FEEDBACK_OK
REFERENCE_
OK
RESERVED SLEEP
Varies
0x003 CHIP_TYPE
0x004 PRODUCT_
ID[11:0]
RESERVED
CHIP_TYPE, Bits[3:0]
RESERVED
0x05
0x3F
0x01
0x14
0x00
0x00
0x00
0x00
PRODUCT_ID, Bits[3:0]
0x005
PRODUCT_ID, Bits[11:4]
0x006 PART_VERSION
0x007 RESERVED
0x008 RESERVED
0x009 RESERVED
PART VERSION
RESERVED
RESERVED
RESERVED
0x00A USER_
SCRATCHPAD1
USER_SCRATCHPAD1, Bits[7:0]
0x00B SPI_VERSION
0x00C VENDOR_ID
0x00D VENDOR_ID
0x00E RESERVED
0x00F IO_UPDATE
0x010 R_DIVIDER
SPI_VERSION, Bits[7:0]
VENDOR_ID, Bits[7:0]
VENDOR_ID, Bits[15:8]
RESERVED
0x00
0x56
0x04
0x00
0x00
0x01
0x06
RESERVED
IO_UPDATE
R_DIVIDER, Bits[7:0]
0x011 R_DIVIDER_
CTRL
RESERVED
REFIN_OVERRIDE_ REFIN_INPUT_
REFIN_DIV_
RESET
PIN_SEL
REFA_TERM_SEL
REFB_TERM_SEL
SEL
0x012 REF_A
RESERVED
RESERVED
REFA_LDO_EN
REFB_LDO_EN
REFA_EN
REFB_EN
0x07
0x06
0x01
0x24
0x013 REF_B
0x014 OUT1_DIVIDER
OUT1_DIVIDER, Bits[7:0]
0x015 OUT1_DRIVER_
CONTROL
RESERVED
RESERVED
RESERVED
RESERVED
OUT1_AMP_TRIM
OUT1_TERM_ OUT1_LDO_EN
EN
OUT1_EN
OUT2_EN
OUT3_EN
OUT4_EN
OUT1_
DIVIDER_RESET
0x016 OUT2_DIVIDER
OUT2_DIVIDER, Bits[7:0]
0x01
0x24
0x017 OUT2_DRIVER_
CONTROL
OUT2_AMP_TRIM
OUT3_AMP_TRIM
OUT2_TERM_ OUT2_LDO_EN
EN
OUT2_
DIVIDER_RESET
0x018 OUT3_DIVIDER
OUT3_DIVIDER, Bits[7:0]
0x01
0x24
0x019 OUT3_DRIVER_
CONTROL
OUT3_TERM_ OUT3_LDO_EN
EN
OUT3_
DIVIDER_RESET
0x01A OUT4_DIVIDER
OUT4_DIVIDER, Bits[7:0]
0x01
0x24
0x01B OUT4_DRIVER_
CONTROL
OUT4_AMP_TRIM
RESERVED
OUT4_TERM_ OUT4_LDO_EN
EN
OUT4_
DIVIDER_RESET
0x01C VCO_POWER
VCO_LDO_WAIT_ VCO_POWER
OVERRIDE
0x01
0x0C
Varies
0x01D PLL_LOCKDET_
CONTROL
RESERVED
PLL_LOCK_
DET_START
PLL_LOCK_DET_ERROR, Bits[7:0]
PLL_LOCK_DET_ERR_THRESHOLD, Bits[2:0]
PLL_LOCK_
DET_RESET
0x01E PLL_LOCKDET_
READBACK1
0x01F PLL_LOCKDET_
READBACK2
RESERVED
RESERVED
RESERVED
PLL_LOCK_
DET_DONE
PLL_LOCK_
DET_RANGE
PLL_LOCKED
M1_LDO_EN
M2_LDO_EN
PLL_LOCK_DET_ERROR, Bits[9:8] Varies
0x020 M1_DIVIDER
0x021 M2_DIVIDER
0x022 M3_DIVIDER
0x023 N_DIVIDER
M1_DIVIDER
M1_EN
M2_EN
M3_EN
M1_DIVIDER_
RESET
0x16
0x16
0x02
0x0A
M2_DIVIDER
M2_DIVIDER_
RESET
RESERVED
M3_DIVIDER
M3_DIVIDER_
RESET
N_DIVIDER
Rev. 0 | Page 29 of 41
AD9530
Data Sheet
Reg.
Addr.
(Hex) Register Name Bit 7
Default
Value
(Hex)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB) Bit 0
0x024 N_DIVIDER_
CTRL
RESERVED
N_DIVIDER_
RESET
0x00
0x025 CHARGE_PUMP
RESERVED
CP_CURRENT
0x07
0x01
0x026 PHASE_
FREQUENCY_
DETECTOR
RESERVED
PFD_EN_
ANTIBACKLASH
PFD_ENABLE
0x027 LOOP_FILTER
RESERVED
RESERVED
LOOP_FILTER_CAP
LOOP_FILTER_
BIAS_EN
LOOP_FILTER_ 0x13
AMP_EN
0x028 VCO_READBACK
0x0FC RESERVED
VCO_FREQ_AUTOCAL
0x00
0x00
0x00
0x00
RESERVED
RESERVED
0x0FD RESERVED
0x0FE USER_
SCRATCHPAD2
USER_SCRATCHPAD2, Bits[7:0]
0x0FF USER_
SCRATCHPAD3
USER_SCRATCHPAD3, Bits[7:0]
0x00
Rev. 0 | Page 30 of 41
Data Sheet
AD9530
CONTROL REGISTER MAP DESCRIPTIONS
Table 23 through Table 61 provide detailed descriptions for each of the control register functions. The registers are listed by hexadecimal address.
Bit fields noted as live indicate that the register write takes effect immediately. Bit fields that are not noted as live only take effect after an
IO_UPDATE is issued by writing 0x01 to Register 0x00F.
SPI CONFIGURATION (REGISTER 0x000 AND REGISTER 0x001)
Table 23. Bit Descriptions for SPI_CONFIGA (Default: 0x00)
Bits
Bit Name
Settings
Description
Reset
Access
7
SOFT_RESET
Master SPI reset. Setting this self clearing bit to 1 resets the AD9530.
This bit is live.
0b
W
6
LSB_FIRST
Selects SPI LSB first mode. This bit is live.
MSB first SPI access.
0b
0b
0b
0b
0b
0b
RW
RW
RW
RW
RW
W
0
1
LSB first SPI access.
5
ADDRESS_ASCEND
SDO_ACTIVE
ADDRESS_ASCEND
LSB_FIRST
Selects SPI address ascend mode. This bit is live.
SPI streaming mode addresses decrement (default).
SPI streaming mode addresses increment.
Selects SPI 4-pin mode, which enables the SDO pin. This bit is live.
SPI 3-pin mode. The SDIO pin is bidirectional (default).
SPI 4-pin mode. The SDI and SDO pins are unidirectional.
Selects SPI address ascend mode. This bit is live.
SPI streaming mode addresses decrement (default).
SPI streaming mode addresses increment.
Selects SPI LSB first mode. This bit is live.
MSB first SPI access (default).
0
1
[4:3]
0
1
2
1
0
0
1
0
1
LSB first SPI access.
SOFT_RESET
Master SPI reset. Setting this self clearing bit to 1 resets the AD9530.
This bit is live.
Table 24. Bit Descriptions for SPI_CONFIGB (Default: 0x00)
Bits
Bit Name
Settings
Description
Reset
Access
7
SINGLE_INSTRUCTION
Single instruction mode. This bit is live.
SPI streaming mode (default).
SPI single instruction mode.
0b
RW
0
1
0
6
5
RESERVED
When writing to Register 0x001, this bit must be 0b.
0b
0b
W
READ_BUFFER
For buffered registers, this bit controls whether the value read from
the serial port is from the actual (active) registers or the buffered copy.
RW
0
1
Reads values currently applied to the internal logic of the device (default).
Reads buffered values that take effect on the next assertion of
IO_UPDATE.
[4:3]
2
RESERVED
00 When writing to Register 0x001, these bits must be 00b.
00b
0b
W
W
CALIBRATE VCO
VCO calibration. Setting this self clearing bit performs a VCO
calibration, which must be performed at startup as well as any time
the VCO frequency is changed. A VCO calibration also automatically
performs a divider reset (Bit 1 in this register). This bit is live.
1
0
DIVIDER_RESET
RESERVED
Divider reset. Writing a 1 to this self clearing register stalls the outputs, 0b
reset all dividers, and reenable the outputs. A divider reset must be
performed any time the divider values are changed. Note that if the
divider value change results in a different VCO frequency, the
CALIBRATE VCO bit (Bit 2 in this register) must be used instead.
This bit is live.
W
W
0
When writing to Register 0x001, this bit must be 0b.
0
Rev. 0 | Page 31 of 41
AD9530
Data Sheet
STATUS (REGISTER 0x002)
Table 25. Bit Descriptions for STATUS (Default: Varies1)
Bits
Bit Name
Settings
Description
Reset
Access
7
PLL_LOCKED
PLL lock detect status readback
PLL unlocked
Varies
R
0
1
PLL locked
6
5
4
SIGNAL_PRESENT
FEEDBACK_OK
REFERENCE_OK
Reference signal present
Varies
Varies
Varies
R
R
R
0
1
Reference input signal not detected
Reference input signal detected
Feedback signal valid from N divider
Feedback signal from N divider not detected
Feedback signal from N divider detected
Logical AND of reference input signal and feedback signal
0
1
0
1
Either the reference input clock is not detected or the feedback signal is
not detected, or neither are detected
Reference input signal and feedback signal both detected
[3:2]
[1:0]
RESERVED
SLEEP
00 When writing to Register 0x002, these bits must be 00b
00b
00b
W
Sleep mode
RW
00 Normal operation (default)
01 Undefined
10 Undefined
11 Sleep mode
1 The default value reads 0xF0 under normal operation if the PLL is locked.
CHIP TYPE (REGISTER 0x003)
Table 26. Bit Descriptions for CHIP_TYPE (Default: 0x05)
Bits
[7:4]
[3:0]
Bit Name
Settings
Description
Reset
0x0
Access
RESERVED
Reserved.
R
R
CHIP_TYPE,
Bits[3:0]
The Analog Devices unified SPI protocol reserves this read only register
location for identifying the type of device. The default value of 0x05 identifies
the AD9530 as a clock IC.
0x5
PRODUCT ID (REGISTER 0x004 AND REGISTER 0x005)
Table 27. Bit Descriptions for PRODUCT_ID[3:0] (Default: 0x3F)
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
PRODUCT_ID,
Bits[3:0]
The Analog Devices unified SPI protocol reserves this read only register
location as the lower four bits of the clock part serial ID that (along with
Register 0x005) uniquely identifies the AD9530 within the Analog Devices
clock chip family. No other Analog Devices chip that adheres to the Analog
Devices unified SPI has these values for Register 0x003, Register 0x004,
and Register 0x005.
0x3
R
[3:0]
RESERVED
Reserved.
0xF
R
Table 28. Bit Descriptions for PRODUCT_ID[11:4] (Default: 0x01)
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PRODUCT_ID,
Bits[11:4]
The Analog Devices unified SPI protocol reserves this read only register
location as the upper eight bits of the clock part serial ID that (along with
Register 0x004) uniquely identifies the AD9530 within the Analog Devices
clock chip family. No other Analog Devices chip that adheres to the Analog
Devices unified SPI has these values for Register 0x003, Register 0x004,
and Register 0x005.
0x01
R
Rev. 0 | Page 32 of 41
Data Sheet
AD9530
PART VERSION (REGISTER 0x006)
Table 29. Bit Descriptions for PART_VERSION (Default: 0x14)
Bits
Bit Name
Settings
Description
Reset
0x00
Access
[7:0]
PART VERSION
The Analog Devices unified SPI protocol reserves this read only register
location for identifying the die revision.
R
USER SCRATCH PAD 1 (REGISTER 0x00A)
Table 30. Bit Descriptions for USER_SCRATCHPAD1 (Default: 0x00)
Bits
Bit Name
Settings Description
Reset Access
[7:0]
USER_SCRATCHPAD1,
Bits[7:0]
0x00 to This register has no effect on device operation. It is available for serial port
0xFF debugging or register setting revision control. There are two additional
user scratch pad registers at Address 0x0FE and Address 0x0FF.
0x00
RW
SPI VERSION (REGISTER 0x00B)
Table 31. Bit Descriptions for SPI_VERSION (Default: 0x00)
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
SPI_VERSION,
Bits[7:0]
The Analog Devices unified SPI protocol reserves this read only register
location for identifying the version of the unified SPI protocol.
0x00
R
VENDOR ID (REGISTER 0x00C AND REGISTER 0x00D)
Table 32. Bit Descriptions for VENDOR ID (Default: 0x56)
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VENDOR_ID,
Bits[7:0]
The Analog Devices unified SPI protocol reserves this read only register
location for identifying Analog Devices as the chip vendor of this device.
All Analog Devices parts adhering to the unified serial port specification
have the same value in this register.
0x56
R
Table 33. Bit Descriptions for VENDOR_ID (Default: 0x04)
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
VENDOR_ID,
Bits[15:8]
The Analog Devices unified SPI protocol reserves this read only register
location for identifying Analog Devices as the chip vendor of this part. All
Analog Devices parts adhering to the unified serial port specification have
the same value in this register.
0x04
R
IO_UPDATE (REGISTER 0x00F)
Table 34. Bit Descriptions for IO_UPDATE (Default: 0x00)
Bits
[7:1]
0
Bit Name
RESERVED
IO_UPDATE
Settings
Description
Reset
0x00
0b
Access
W
0x00 When writing to Register 0x00F, these bits must be 0x0.
Writing a 1 to this bit transfers the data in the serial input/output
buffer registers to the internal control registers of the device. This is a
live and autoclearing bit.
W
R DIVIDER—REFERENCE INPUT DIVIDER (REGISTER 0x010)
Table 35. Bit Descriptions for R_DIVIDER (Default: 0x01)
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
R_DIVIDER,
Bits[7:0]
0x01 to PLL reference divider. These bits control the divide ratio of the R divider.
0xFF Divide ratio goes from ÷1 (by writing 0x01) to ÷255 (by writing 0xFF).
0x01
RW
Rev. 0 | Page 33 of 41
AD9530
Data Sheet
R DIVIDER CONTROL (REGISTER 0x011)
Table 36. Bit Descriptions for R_DIVIDER_CTRL (Default: 0x06)
Bits
[7:3]
2
Bit Name
Settings
Description
Default Access
RESERVED
00000b When writing to Register 0x011, these bits must be 00000b.
Reference input override pin selection.
00000b RW
REFIN_OVERRIDE_PIN_SEL
1b
RW
0
REFIN_INPUT_SEL bit (in this register) controls reference input
selection.
1
REF_SEL pin controls reference input selection. REFA is selected if
the REF_SEL pin is high. REFB is selected if the REF_SEL pin is low.
1
0
REFIN_INPUT_SEL
REFIN_DIV_RESET
Reference input selection.
1b
0b
RW
W
0
1
Select REFB input if REFIN_OVERRIDE_PIN_SEL = 0.
Select REFA input if REFIN_OVERRIDE_PIN_SEL = 0.
Reference input divider reset (autoclearing). Setting this (self
clearing) bit resets the R divider. This bit is live, meaning
IO_UPDATE is not needed for it to take effect.
REFERENCE INPUT A (REGISTER 0x012)
Table 37. Bit Descriptions for REF_A (Default: 0x07)
Bits
[7:4]
[3:2]
Bit Name
Settings
Description
Default Access
RESERVED
00 When writing to Register 0x012, these bits must be 0x0
Reference A input termination select
0x0
01b
W
REFA_TERM_SEL
RW
00 LVDS mode (100 Ω across the inputs)
01 DC-coupled mode (50 Ω to ground) (default)
10 AC-coupled mode (50 Ω to 0.35 V, internal)
11 DC-coupled high-Z mode
1
0
REFA_LDO_EN
REFA_EN
Reference A enable LDO
1b
1b
RW
RW
0
1
Disabled
Enabled (default)
Reference A enable
Disabled
0
1
Enabled (default)
REFERENCE INPUT B (REGISTER 0x013)
Table 38. Bit Descriptions for REF_B (Default: 0x06)
Bits
[7:4]
[3:2]
Bit Name
Settings
Description
Default Access
RESERVED
00 When writing to Register 0x013, these bits must be 0x0
Reference B input termination select
00 LVDS mode (100 Ω across the inputs)
01 DC-coupled mode (50 Ω to ground) (default)
10 AC-coupled mode (50 Ω to 0.35 V, internal)
11 DC-coupled high-Z mode
0x0
01b
W
REFB_TERM_SEL
RW
1
0
REFB_LDO_EN
REFB_EN
Reference B enable LDO
1b
0b
RW
RW
0
1
Disabled
Enabled (default)
Reference B enable
Disabled (default)
Enabled
0
1
Rev. 0 | Page 34 of 41
Data Sheet
AD9530
OUT1 DIVIDER (REGISTER 0x014)
Table 39. Bit Descriptions for OUT1_DIVIDER (Default: 0x01)
Bits
Bit Name
Settings
Description
Default Access
[7:0]
OUT1_DIVIDER,
Bits[7:0]
0x00 to Output 1 divider. These bits control the divide ratio of the output divider.
0xFF Divide ratio goes from ÷1 (by writing 0x01) to ÷255 (by writing 0xFF).
Writing 0x00 disables the divider.
0x01
RW
OUT1 DRIVER CONTROL REGISTER (REGISTER 0x015)
Table 40. Bit Descriptions for OUT1_DRIVER_CONTROL (Default: 0x24)
Bits
[7:6]
[5:4]
Bit Name
Settings
Description
Default Access
RESERVED
00 When writing to Register 0x015, these bits must be 00b.
00b
10b
W
OUT1_AMP_TRIM
Output 1 amplitude voltage trim.
00 0.8 V.
RW
01 0.9 V.
10 1.0 V (default).
11 1.1 V.
3
2
1
0
OUT1_TERM_EN
OUT1_LDO_EN
OUT1_EN
Output 1 on-chip termination.
0b
1b
0b
0b
RW
RW
RW
W
0
1
Disabled (default).
Enabled.
Output 1 enable LDO.
Disabled.
0
1
Enabled (default).
Output 1 enable.
Disabled (default).
Enabled.
0
1
OUT1_DIVIDER_RESET
Setting this (self clearing) bit resets the Output 1 divider. This bit is
live, meaning IO_UPDATE is not needed for it to take effect.
OUT2 DIVIDER (REGISTER 0x016)
Table 41. Bit Descriptions for OUT2_DIVIDER (Default: 0x01)
Bits
Bit Name
Settings
Description
Default Access
0x01 RW
[7:0]
OUT2_DIVIDER,
Bits[7:0]
0x00 to
0xFF
Output 2 divider. These bits control the divide ratio of the output divider.
Divide ratio goes from ÷1 (by writing 0x01) to ÷255 (by writing 0xFF).
Writing 0x00 disables the divider.
OUT2 DRIVER CONTROL (REGISTER 0x017)
Table 42. Bit Descriptions for OUT2_DRIVER_CONTROL (Default: 0x24)
Bits
[7:6]
[5:4]
Bit Name
Settings
Description
Default Access
RESERVED
00 When writing to Register 0x017, these bits must be 00b.
00
W
OUT2_AMP_TRIM
Output 2 amplitude voltage trim.
00 0.8 V.
10b
RW
01 0.9 V.
10 1.0 V (default).
11 1.1 V.
3
2
1
OUT2_TERM_EN
OUT2_LDO_EN
OUT2_EN
Output 2 on-chip termination.
0b
1b
0b
RW
RW
RW
0
1
Disabled (default).
Enabled.
Output 2 enable LDO.
Disabled.
0
1
Enabled (default).
Output 2 enable.
Disabled (default).
Enabled.
0
1
Rev. 0 | Page 35 of 41
AD9530
Data Sheet
Bits
Bit Name
OUT2_DIVIDER_RESET
Settings
Description
Default Access
0
Setting this (self clearing) bit resets the Output 2 divider. This bit is
live, meaning IO_UPDATE is not needed for it to take effect.
0b
W
OUT3 DIVIDER (REGISTER 0x018)
Table 43. Bit Descriptions for OUT3_DIVIDER (Default: 0x01)
Bits
Bit Name
Settings
Description
Default Access
0x01 RW
[7:0]
OUT3_DIVIDER,
Bits[7:0]
0x00 to Output 3 divider. These bits control the divide ratio of the output divider.
0xFF Divide ratio goes from ÷1 (by writing 0x01) to ÷255 by writing 0xFF.
Writing 0x00 disables the divider.
OUT3 DRIVER CONTROL (REGISTER 0x019)
Table 44. Bit Descriptions for OUT3_DRIVER_CONTROL (Default: 0x24)
Bits
[7:6]
[5:4]
Bit Name
Settings
Description
Default Access
RESERVED
When writing to Register 0x019, these bits must be 00b.
Output 3 amplitude voltage trim.
00b
10b
N/A
RW
OUT3_AMP_TRIM
00 0.8 V.
01 0.9 V.
10 1.0 V (default).
11 1.1 V.
3
2
1
0
OUT3_TERM_EN
OUT3_LDO_EN
OUT3_EN
Output 3 on-chip termination.
Disabled (default).
0b
1b
0b
0b
RW
RW
RW
W
0
1
Enabled.
Output 3 enable LDO.
Disabled.
0
1
Enabled (default).
Output 3 enable.
Disabled (default).
Enabled.
0
1
OUT3_DIVIDER_RESET
Setting this (self clearing) bit resets the Output 3 divider. This bit is
live, meaning IO_UPDATE is not needed for it to take effect.
OUT4 DIVIDER (REGISTER 0x01A)
Table 45. Bit Descriptions for OUT4_DIVIDER (Default: 0x01)
Bits
Bit Name
Settings
Description
Default Access
0x01 RW
[7:0]
OUT4_DIVIDER,
Bits[7:0]
0x00 to Output 4 divider. These bits control the divide ratio of the output divider.
0xFF Divide ratio goes from ÷1 (by writing 0x01) to ÷255 by writing 0xFF.
Writing 0x00 disables the divider.
OUT4 DRIVER CONTROL (REGISTER 0x01B)
Table 46. Bit Descriptions for OUT4_DRIVER_CONTROL (Default: 0x24)
Bits
[7:6]
[5:4]
Bit Name
Settings
Description
Default Access
RESERVED
00 When writing to Register 0x01B, these bits must be 00b.
00b
10b
W
OUT4_AMP_TRIM
Output 4 amplitude voltage trim.
00 0.8 V.
RW
01 0.9 V.
10 1.0 V (default).
11 1.1 V.
3
OUT4_TERM_EN
Output 4 on-chip termination.
0b
RW
0
1
Disabled (default).
Enabled.
Rev. 0 | Page 36 of 41
Data Sheet
AD9530
Bits
Bit Name
Settings
Description
Default Access
2
OUT4_LDO_EN
Output 4 enable LDO.
Disabled.
1b
0b
0b
RW
RW
W
0
1
Enabled (default).
Output 4 enable.
Disabled (default).
Enabled.
1
0
OUT4_EN
0
1
OUT4_DIVIDER_RESET
Setting this (self clearing) bit resets the Output 4 divider. This bit is
live, meaning IO_UPDATE is not needed for it to take effect.
VCO POWER (REGISTER 0x01C)
Table 47. Bit Descriptions for VCO_POWER (Default: 0x01)
Bits
[7:2]
1
Bit Name
Settings
Description
Default
000000b
0b
Access
W
RESERVED
000000b When writing to Register 0x01C, these bits must be 00b
VCO LDO wait state override
VCO_LDO_WAIT_OVERRIDE
RW
0
1
Wait 2 sec on startup for VCO LDO stability (default)
Do not wait for VCO LDO stability
VCO power mode
0
VCO_POWER
1b
RW
0
1
Low power mode
High power mode (lower jitter) (default)
PLL LOCK DETECT CONTROL (REGISTER 0x01D)
Table 48. Bit Descriptions for PLL_LOCKDET_CONTROL (Default: 0x0C)
Bits
[7:5]
4
Bit Name
Settings
Description
Default Access
RESERVED
000b When writing to Register 0x01D, these bits must be 000b.
000b
0b
W
PLL_LOCK_DET_START
PLL lock detect start measurement. This live bit enables the
lock detector.
RW
0
1
PLL lock detector disabled (default).
PLL lock detector enabled.
[3:1]
PLL_LOCK_DET_ERR_
THRESHOLD, Bits[2:0]
000b to PLL lock detect frequency error threshold (ppb is parts per
111b billion and ppm is parts per million).The frequency accuracy of
the lock detector is 25% of the lock detect setting. For example,
for the 15 ppb setting, the actual accuracy of the lock detector
is 11 ppb to 19 ppb.
010b
RW
000b Threshold: 15 ppb. Update interval: 670 ms.
001b Threshold: 60 ppb. Update interval: 170 ms.
010b Threshold: 238 ppb. Update interval: 42 ms (default).
011b Threshold: 954 ppb. Update interval: 10 ms.
100b Threshold: 3.8 ppm. Update interval: 2.6 ms.
101b Threshold: 15 ppm. Update interval: 660 µs.
110b Threshold: 61 ppm. Update interval: 160 µs.
111b Threshold: 244 ppm. Update interval: 41 µs.
PLL lock detect disable.
0
PLL_LOCK_DET_RESET
0b
RW
0
1
PLL lock detector enabled (default).
PLL lock detector disabled.
PLL LOCK DETECT READBACK (REGISTER 0x01E AND REGISTER 0x01F)
Table 49. Bit Descriptions for PLL_LOCKDET_READBACK1 (Read Only; No Default Value)
Bits Bit Name
Settings Description
PLL lock detect error, Bits[7:0]. This read only register, along with Bits[1:0] Varies
of Register 0x01F, form a 10-bit number that allows the user to read back
Default Access
[7:0] PLL_LOCK_DET_ERROR,
Bits[7:0]
R
the magnitude of the frequency error at the phase frequency detector.
Bit 3 in Register 0x01F indicates whether the phase error measurement is
in parts per million (ppm) or parts per billion (ppb).
Rev. 0 | Page 37 of 41
AD9530
Data Sheet
Table 50. Bit Descriptions for PLL_LOCKDET_READBACK2 (Read Only; No Default Value)
Bits
[7:5]
4
Bit Name
Settings
Description
Default Access
RESERVED
000b When writing to Register 0x01F, these bits must be 000b.
PLL lock detect measurement done.
000b
R
R
R
PLL_LOCK_DET_DONE
PLL_LOCK_DET_RANGE
Varies
Varies
3
PLL lock detect error range.
0
1
The read back error is expressed in ppb (parts per billion).
The read back error is expressed in ppm (parts per million).
PLL lock detect status readback.
PLL unlocked.
2
PLL_LOCKED
Varies
Varies
R
R
0
1
PLL locked.
[1:0]
PLL_LOCK_DET_ERROR,
Bits[9:8]
PLL lock detect error, Bits[9:8]. These read only register bits, along
with Bits[7:0] Register 0x01E, form a 10-bit number that allows the
user to read back the magnitude of the frequency error at the phase
frequency detector. Bit 3 in Register 0x01F indicates whether the
phase error measurement is in parts per million (ppm) or parts per
billion (ppb).
M1, M2, M3 DIVIDERS (REGISTER 0x020 AND REGISTER 0x022)
Table 51. Bit Descriptions for M1_DIVIDER (Default 0x16)
Bits
[7:5]
[4:3]
Bit Name
Settings
Description
Default Access
RESERVED
M1_DIVIDER
000b When writing to Register 0x020, these bits must be 000b.
000b
10b
W
These bits control the divide ratio for the M1 divider that feeds the
D1 and D2 dividers.
RW
00 Divide by 2.
01 Divide by 2.5.
10 Divide by 3 (default).
11 Divide by 3.5.
2
1
0
M1_LDO_EN
M1_EN
M1 divider enable LDO.
1b
1b
0b
RW
RW
W
0
1
Disabled.
Enabled (default).
M1 divider enable.
Disabled.
0
1
Enabled (default).
M1_DIVIDER_RESET
Setting this (self clearing) bit resets the M1 divider. This bit is live,
meaning IO_UPDATE is not needed for it to take effect.
Table 52. Bit Descriptions for M2_DIVIDER (Default: 0x16)
Bits
[7:5]
[4:3]
Bit Name
Settings
Description
Default Access
RESERVED
M2_DIVIDER
000b When writing to Register 0x021, these bits must be 000b.
000b
10b
W
These bits control the divide ratio for the M2 divider that feeds the
D3 and D4 dividers.
RW
00 Divide by 2.
01 Divide by 2.5.
10 Divide by 3 (default).
11 Divide by 3.5
2
1
0
M2_LDO_EN
M2_EN
M2 divider enable LDO.
1b
1b
0b
RW
RW
W
0
1
Disabled.
Enabled (default).
M2 divider enable.
Disabled.
0
1
Enabled.
M2_DIVIDER_RESET
Setting this (self clearing) bit resets the M2 divider. This bit is live,
meaning IO_UPDATE is not needed for it to take effect.
Rev. 0 | Page 38 of 41
Data Sheet
AD9530
M3 DIVIDER (REGISTER 0x022)
Table 53. Bit Descriptions for M3_DIVIDER (Default: 0x02)
Bits
[7:4]
[3:2]
Bit Name
Settings
Description
Default Access
RESERVED
M3_DIVIDER
0x0 When writing to Register 0x01F, these bits must be 0x0.
These bits control the divide ratio for the M3 divider.
00 Divide by 2 (default).
0x0
00b
W
RW
01 Divide by 2.5.
10 Divide by 3.
11 Divide by 3.5.
1
0
M3_EN
M3 divider enable.
1b
0b
RW
W
0
1
Disabled.
Enabled (default).
M3_DIVIDER_RESET
Setting this (self clearing) bit resets the M3 divider. This bit is live,
meaning IO_UPDATE is not needed for it to take effect.
N DIVIDER (REGISTER 0x023)
Table 54. Bit Descriptions for N_DIVIDER (Default: 0x0A)
Bits
Bit Name
Settings
Description
Default Access
[7:0]
N_DIVIDER
0x01 to PLL feedback divider. These bits control the divide ratio of the PLL
0xFF feedback divider. The divide ratio ranges from ÷1 (by writing 0x01) to
÷255 by writing 0xFF. Writing 0x00 disables the divider.
0x0A
RW
N DIVIDER CONTROL (REGISTER 0x024)
Table 55. Bit Descriptions for N_DIVIDER_CTRL (Default:0x00)
Bits
[7:1]
0
Bit Name
Settings
Description
Default
0000000b
0b
Access
W
RESERVED
0000000b When writing to Register 0x024, these bits must be 0x00.
N_DIVIDER_RESET
Setting this (self clearing) bit resets the N divider (also called
the feedback divider). This bit is live, meaning IO_UPDATE is not
needed for it to take effect.
W
CHARGE PUMP (REGISTER 0x025)
Table 56. Bit Descriptions for CHARGE_PUMP (Default: 0x07)
Bits
[7:6]
[5:0]
Bit Name
Settings
Description
Default Access
RESERVED
CP_CURRENT
00b When writing to Register 0x025, these bits must be 0x0.
00b
W
Charge pump current. Charge pump current, ICP, is equal to: (1 +
CP_CURRENT) × 50 µA. The allowable range is 50 µA to 2.6 mA. Higher
register settings result in ICP = 2.6 mA.
0x07
RW
000000b 50 µA.
000001b 100 µA.
…
000111b 400 µA (default).
…
110010b 2.55 mA.
110011 2.6 mA (maximum).
PHASE FREQUENCY DECTECTOR (REGISTER 0x026)
Table 57. Bit Descriptions for PHASE_FREQUENCY_DETECTOR (Default: 0x01)
Bits
[7:2]
1
Bit Name
Settings
Description
Default
000000b
0b
Access
W
RESERVED
000000b When writing to Register 0x026, these bits must be 0x00.
PFD antibacklash enable.
PFD_EN_ANTIBACKLASH
RW
0
1
Normal antibacklash pulse width (default).
Elongated antibacklash pulse width.
Rev. 0 | Page 39 of 41
AD9530
Data Sheet
Bits
Bit Name
PFD_ENABLE
Settings
Description
Default
Access
0
PFD enable. This bit enables the phase frequency detector.
1b
RW
0
1
Disabled.
Enabled (default).
LOOP FILTER (REGISTER 0x027)
Table 58. Bit Descriptions for LOOP_FILTER (Default: 0x13)
Bits
[7:6]
[5:2]
Bit Name
Settings
Description
Default Access
RESERVED
00b When writing to Register 0x027, these bits must be 00b
Loop filter capacitance select (CIN in Figure 16)
0000 5 pF
00b
0x4
W
LOOP_FILTER_CAP
RW
0001 17.5 pF
0010 30 pF
0011 42.5 pF
0100 55 pF (default)
0101 67.5 pF
0110 80 pF
0111 92.5 pF
1000 105 pF
1001 117.5 pF
1010 130 pF
1011 142.5 pF
1100 155 pF
1101 167.5 pF
1110 180 pF
1111 192.5 pF
1
0
LOOP_FILTER_BIAS_EN
LOOP_FILTER_AMP_EN
Loop filter enable bias
1b
1b
RW
RW
0
1
Disabled
Enabled (default)
Loop filter enable amplifier
Disabled
0
1
Enabled (default)
VCO FREQUENCY (REGISTER 0x028)
Table 59. Bit Descriptions for VCO_READBACK (Default: 0x00)
Bits
[7:5]
[4:0]
Bit Name
Settings
Description
Default Access
RESERVED
Reserved
000b
R
R
VCO_FREQ_AUTOCAL
Read only VCO autocalibrated frequency band. This is a diagnostic bit
and the user normally does not need to access this register.
Varies
USER SCRATCH PAD 2 (REGISTER 0x0FE)
Table 60. Bit Descriptions for USER_SCRATCHPAD2 (Default: 0x00)
Bits Bit Name
Settings
Description
Reset Access
0x00 RW
[7:0] USER_SCRATCHPAD2,
Bits[7:0]
0x00 to This register has no effect on device operation. It is available for serial
0xFF port debugging or register setting revision control. There are two
additional user scratch pad registers at Address 0x00A and Address 0x0FF.
USER SCRATCH PAD 3 (REGISTER 0x0FF)
Table 61. Bit Descriptions for USER_SCRATCHPAD3 (Default: 0x00)
Bits Bit Name
Settings
Description
Reset Access
0x00 RW
[7:0] USER_SCRATCHPAD3,
Bits[7:0]
0x00 to This register has no effect on device operation. It is available for serial port
0xFF debugging or register setting revision control. There are two additional user
scratch pad registers at Address 0x00A and Address 0x0FE.
Rev. 0 | Page 40 of 41
Data Sheet
AD9530
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
0.30
0.25
0.20
PIN 1
INDICATOR
PIN 1
INDICATOR
37
36
48
1
0.50
BSC
*
EXPOSED
PAD
5.70
5.60 SQ
5.50
24
13
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.203 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2
WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION.
Figure 34. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
Package Description
Package Option
AD9530BCPZ
AD9530BCPZ-REEL7
AD9530/PCBZ
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-48-13
CP-48-13
−40°C to +85°C
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14044-0-4/16(0)
Rev. 0 | Page 41 of 41
相关型号：
AD9540BCPZ-REEL7
OTHER CLOCK GENERATOR, QCC48, 7 X 7 MM, LEAD FREE, MO-220VKKD-2, LFCSP-48
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