AD9544BCPZ-REEL7_技术文档

Quad Input, 10-Output, Dual DPLL,

1 pps Synchronizer and Jitter Cleaner

AD9544

Data Sheet

FEATURES

APPLICATIONS

Dual DPLL synchronizes 1 Hz to 750 MHz physical layer

SyncE and GPS synchronization and jitter cleanup

clocks providing frequency translation with jitter cleaning

of noisy references

Optical transport networks (OTN), SDH, and macro and small

cell base stations

Complies with ITU-T G.8262 and Telcordia GR-253

Supports Telcordia GR-1244, ITU-T G.812, G.813, G.823,

G.824, and G.825

OTN mapping/demapping with jitter cleaning

Small base station clocking, including baseband and radio

Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter

cleanup, and phase transient control

Continuous frequency monitoring and reference validation

for frequency deviation as low as 50 ppb

JESD204B support for analog-to-digital converter (ADC) and

digital-to-analog converter (DAC) clocking

Cable infrastructures

Both DPLLs feature a 24-bit fractional divider with 24-bit

programmable modulus

Programmable digital loop filter bandwidth: 10⁻⁴Hz to 1850 Hz

Automatic and manual holdover and reference switchover,

providing zero delay, hitless, or phase buildout operation

Programmable priority-based reference switching with

manual, automatic revertive, and automatic nonrevertive

modes supported

Carrier Ethernet

GENERAL DESCRIPTION

The 10 clock outputs of the AD9544 are synchronized to any

one of up to four input references. The digital phase-locked

loops (DPLLs) reduce timing jitter associated with the external

references. The digitally controlled loop and holdover circuitry

continuously generate a low jitter output signal, even when all

reference inputs fail.

5 pairs of clock output pins with each pair useable as

differential LVDS/HCSL/CML or as 2 single-ended outputs

(1 Hz to 500 MHz)

2 differential or 4 single-ended input references

Crosspoint mux interconnects reference inputs to PLLs

Supports embedded (modulated) input/output clock signals

Fast DPLL locking modes

The AD9544 is available in a 48-lead LFCSP (7 mm × 7 mm)

package and operates over the −40°C to +85°C temperature

range.

Note that throughout this data sheet, multifunction pins, such

as SDO/M5, are referred to either by the entire pin name or by a

single function of the pin, for example, M5, when only that

function is relevant.

Provides internal capability to combine the low phase noise

of a crystal resonator or crystal oscillator with the

frequency stability and accuracy of a TCXO or OCXO

External EEPROM support for autonomous initialization

Single 1.8 V power supply operation with internal regulation

Built in temperature monitor/alarm and temperature

compensation for enhanced zero delay performance

Rev. 0

Document Feedback

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rights of third parties that may result from its use. Specifications subject to change without notice. No

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Tel: 781.329.4700

Technical Support

www.analog.com

AD9544

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

System Clock PLL........................................................................... 30

System Clock Input Frequency Declaration........................... 30

System Clock Source.................................................................. 30

2× Frequency Multiplier............................................................ 31

Prescale Divider.......................................................................... 31

Feedback Divider........................................................................ 31

System Clock PLL Output Frequency ..................................... 31

System Clock PLL Lock Detector............................................. 31

System Clock Stability Timer.................................................... 31

System Clock Input Termination Recommendations ........... 31

Digital PLL (DPLL)........................................................................ 32

Overview ..................................................................................... 32

DPLL Phase/Frequency Lock Detectors ................................. 32

DPLL Loop Controller............................................................... 32

Applications Information.............................................................. 33

Optical Networking Line Card................................................. 33

Small Cell Base Station .............................................................. 34

Initialization Sequence................................................................... 35

Status and Control Pins ................................................................. 38

Multifunction Pins at Reset/Power-Up ................................... 39

Status Functionality.................................................................... 39

Control Functionality ................................................................ 39

Interrupt Request (IRQ)................................................................ 44

IRQ Monitor ............................................................................... 44

IRQ Mask..................................................................................... 44

IRQ Clear..................................................................................... 44

Watchdog Timer ............................................................................. 46

Lock Detectors................................................................................ 47

DPLL Lock Detectors ................................................................ 47

Phase Step Detector........................................................................ 49

Phase Step Limit ......................................................................... 49

Skew Adjustment........................................................................ 50

EEPROM Usage.............................................................................. 51

Overview ..................................................................................... 51

EEPROM Controller General Operation................................ 51

EEPROM Instruction Set.......................................................... 52

Multidevice Support .................................................................. 54

Serial Control Port ......................................................................... 56

SPI/I²C Port Selection................................................................ 56

SPI Serial Port Operation.......................................................... 56

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

Supply Voltage............................................................................... 5

Supply Current.............................................................................. 5

Power Dissipation......................................................................... 5

System Clock Inputs, XOA and XOB......................................... 6

Reference Inputs ........................................................................... 7

Reference Monitors ...................................................................... 8

DPLL Phase Characteristics........................................................ 8

Distribution Clock Outputs ........................................................ 9

Time Duration of Digital Functions ........................................ 10

Digital PLL (DPLL0, DPLL1) Specifications .......................... 10

Digital PLL Lock Detection Specifications ............................. 11

Holdover Specifications............................................................. 11

Analog PLL (APLL0, APLL1) Specifications.......................... 11

Output Channel Divider Specifications .................................. 11

System Clock Compensation Specifications........................... 12

Temperature Sensor Specifications .......................................... 12

Serial Port Specifications........................................................... 12

Logic Input Specifications (RESETB, M0 to M6) .................. 14

Logic Output Specifications (M0 to M6) ................................ 14

Jitter Generation (Random Jitter) ............................................ 14

Phase Noise ................................................................................. 15

Absolute Maximum Ratings.......................................................... 19

Thermal Resistance .................................................................... 19

ESD Caution................................................................................ 19

Pin Configuration and Function Descriptions........................... 20

Typical Performance Characteristics ........................................... 22

Terminology .................................................................................... 26

Theory of Operation ...................................................................... 27

Overview...................................................................................... 27

Reference Input Physical Connections.................................... 27

Input/Output Termination Recommendations.......................... 28

System Clock Inputs................................................................... 28

Reference Clock Inputs.............................................................. 28

Clock Outputs............................................................................. 29

Rev. 0 | Page 2 of 62

Data Sheet

AD9544

I²C Serial Port Operation...........................................................59

Outline Dimensions........................................................................62

Ordering Guide ...........................................................................62

REVISION HISTORY

10/2017—Revision 0: Initial Version

Rev. 0 | Page 3 of 62

AD9544

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

DISTRIBUTION

OUTPUTS

PLL0

OUT0AP,

OUT0AN,

OUT0BP,

OUT0BN,

OUT0CP,

OUT0CN

REFERENCE

INPUTS

DPLL0

APLL0

DPLL NCO

PLL VCO

÷2

÷Q

REFA,

REFAA,

÷R

TDC

INTERNAL ZERO DELAY

REFB,

REFBB

DISTRIBUTION

OUTPUTS

PLL1

DPLL1

DPLL NCO

APLL1

OUT1AP,

OUT1AN,

OUT1BP,

OUT1BN

REFERENCE

MONITORS

÷Q

PLL VCO

INTERNAL ZERO DELAY

REFERENCE

SWITCHING

CONTROL

SYSTEM

CLOCK PLL

SYSTEM

CLOCK

XOA,

XOB

AD9544

DIGITAL

CROSS

POINT

MUX

SYSTEM CLOCK

COMPENSATION

2

STATUS AND

CONTROL PINS

SERIAL PORT (SPI/I C)

AND EEPROM

CONTROLLER

TEMPERATURE

SENSOR

M0 TO M6

SERIAL PORT

APLL VCO FREQUENCY RANGE

APLL0: 2424MHz TO 3232MHz

APLL1: 3232MHz TO 4040MHz

EEPROM

(OPTIONAL)

Figure 1.

Rev. 0 | Page 4 of 62

Data Sheet

AD9544

SPECIFICATIONS

The minimum and maximum values apply for the full range of the supply voltage and operating temperature variations. The typical

values apply for VDD = 1.8 V and T_A= 25°C, unless otherwise noted.

SUPPLY VOLTAGE

Table 1.

Parameter

Min Typ Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

VDDIOA, VDDIOB

VDD

1.71 1.8

3.465

1.89

V

1.8 V, 2.5 V, and 3.3 V operation supported

SUPPLY CURRENT

The maximum supply voltage values given in Table 1 are the basis for the maximum supply current specifications. The typical supply

voltage values given in Table 1 are the basis for the typical supply current specifications. The minimum supply voltage values given in

Table 1 are the basis for the minimum supply current specifications.

Table 2.

Parameter

Min

260

321

Typ

Max

Unit

Test Conditions/Comments

SUPPLY CURRENT FOR TYPICAL

CONFIGURATION

The Typical Configuration specification in Table 3 is the basis for

the values shown in this section

I_VDDIOx

I_VDD

5

8

mA

Aggregate current for all VDDIOx pins (where x = A or B)

Aggregate current for all VDD pins

310

355

SUPPLY CURRENT FOR ALL BLOCKS

RUNNING CONFIGURATION

The All Blocks Running condition in Table 3 is the basis for the

values shown in this section

I_VDDIOx

I_VDD

5

8

mA

Aggregate current for all VDDIOx pins (where x = A or B)

Aggregate current for all VDD pins

390

430

POWER DISSIPATION

The typical values apply for VDD = 1.8 V, and the maximum values apply for VDD = 1.89 V.

Table 3.

Parameter

Min

445

Typ

560

Max Unit

Test Conditions/Comments

POWER DISSIPATION

Typical Configuration

671

mW

System clock = 49.152 MHz crystal; two DPLLs active;

two 19.44 MHz input references in differential mode;

two ac-coupled PLL0 CML output drivers at 245.76 MHz;

and two PLL1 CML output drivers at 156.25 MHz

All Blocks Running

548

700

125

813

System clock = 49.152 MHz crystal; two DPLLs active;

two 19.44 MHz input references in differential mode;

three ac-coupled PLL0 HCSL output drivers at 400 MHz; and

two PLL1 HCSL output drivers at 400 MHz

Full Power-Down

Based on the Typical Configuration specification with the

power down all bit set to Logic 1

Incremental Power Dissipation

Based on the Typical Configuration specification; the values in this

section indicate the change in power due to the indicated

operation relative to the Typical Configuration specification

Complete DPLL/APLL On/Off

200

mW

Change in dissipated power relative to the Typical Configuration

specification; the blocks, powered down, consist of one reference

input, one DPLL, one APLL, two channel dividers, and two

output drivers

Incremental Power Dissipation

Complete DPLL/APLL On/Off

Based on the Typical Configuration specification; the values in

this section indicate the change in power due to the indicated

operation relative to the Typical Configuration specification;

the blocks, powered down, consist of one reference input, one

DPLL, one APLL, two channel dividers, and two output drivers

Rev. 0 | Page 5 of 62

AD9544

Data Sheet

Parameter

Min

Typ

20

Max Unit

Test Conditions/Comments

Input Reference On/Off

Differential (Normal Mode)

Differential (DC-Coupled LVDS)

Single-Ended

mW

f_REF= 19.44 MHz

At 156.25 MHz

21

13

Output Distribution Driver On/Off

15 mA Mode

30

23

15

1

mW

12 mA Mode

7.5 mA Mode

Auxiliary DPLL On/Off

SYSTEM CLOCK INPUTS, XOA AND XOB

Table 4.

Parameter

Min

Typ

Max Unit

Test Conditions/Comments

SYSTEM CLOCK MULTIPLIER

Output Frequency Range

2250

2415 MHz

The frequency range of the internal voltage controlled

oscillator (VCO) places limits on the choice of the system

clock input frequency

Phase Frequency Detector (PFD) Rate

SYSTEM CLOCK REFERENCE INPUT PATH

Input Frequency Range

20

300

MHz

System clock input must be ac-coupled

System Clock Input Doubler

Disabled

20

16

300

150

Support of oven controlled crystal oscillators (OCXOs) <

20 MHz is possible using the auxiliary DPLL for system clock

frequency compensation

Enabled

MHz

V

Self Biased Common-Mode Voltage

0.75

Internally generated

Input Voltage

High

For dc-coupled, single-ended operation

0.9

V

Low

0.5

Differential Input Voltage Sensitivity 250

mV p-p Minimum voltage swing required (as measured with a

differential probe) across the XOA/XOB pins to ensure

switching between logic states; the instantaneous voltage on

either pin must not exceed 1.2 V; accommodate the single-

ended input by ac grounding the complementary input;

800 mV p-p recommended for optimal jitter performance

Slew Rate for Sinusoidal Input

50

V/µs

Minimum input slew rate for device operation; oscillators

with square wave outputs are recommended if not using a

crystal

System Clock Input Divider

(J Divider) Frequency

100

MHz

System Clock Input Doubler

Duty Cycle

Tolerable duty cycle variation on the system clock input

when using the frequency doubler

20 MHz to 150 MHz

16 MHz to 20 MHz

43

47

50

5

57

53

%

Input Resistance

kΩ

QUARTZ CRYSTAL RESONATOR PATH

Resonator Frequency Range

Crystal Motional Resistance

25

60

MHz

Ω

Fundamental mode, AT cut crystal

100

A maximum motional resistance of 50 Ω , and maximum

C_LOADof 8 pF is strongly recommended for crystals >52 MHz

Rev. 0 | Page 6 of 62

Data Sheet

AD9544

REFERENCE INPUTS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL MODE

Differential mode specifications assume ac coupling

of the input signal to the reference input pins

Frequency Range

Sinusoidal Input

LVPECL Input

750

750 × 10⁶

MHz

Hz

Lower limit dependent on input slew rate

1

Lower limit dependent on ac coupling; 1 Hz is

equivalent to 1 pulse per second (pps)

LVDS Input

1

500 × 10⁶

Hz

V/µs

V

Assumes an LVDS minimum of 494 mV p-p differential

amplitude; lower limit dependent on ac coupling

Slew Rate for Sinusoidal input

20

Minimum input slew rate for device operation; jitter

degradation may occur for slew rates < 35 V/µs

Common-Mode Input Voltage

Differential Input Amplitude

0.64

Internally generated self bias voltage

Peak-to-peak differential voltage swing across pins

required to ensure switching between logic levels as

measured with a differential probe; instantaneous

voltage on either pin must not exceed 1.3 V

f_IN< 500 MHz

350

500

2100

100

mV p-p

mV

f_IN= 500 MHz to 750 MHz

Differential Input Voltage Hysteresis

Input Resistance

Input Pulse Width

LVPECL

55

16

kΩ

Equivalent differential input resistance

Applies for dc-coupling to an LVDS source

600

900

ps

LVDS

DC-COUPLED, LVDS-COMPATIBLE

MODE

Frequency Range

1

450 × 10⁶

1.375

Hz

V

Common-Mode Input Voltage

Differential Input Amplitude

1.125

400

1200

mV p-p Differential voltage across pins required to ensure

switching between logic levels; instantaneous

voltage on either pin must not exceed the supply rails

Differential Input Voltage Hysteresis

Input Resistance

55

16

100

mV

kΩ

ns

Input Pulse Width

1

SINGLE-ENDED MODE

Single-ended mode specifications assume dc

coupling of the input signal to the reference input

pins

Frequency Range

1.2 V AC-Coupled

1.2 V and 1.8 V CMOS

1

500 × 10⁶

Hz

Lower limit dependent on ac-coupling

CMOS specifications assume dc coupling of the input

signal to the reference input pins

1.2 V AC-Coupled Common-Mode

Voltage

610

mV

Internally generated self-bias voltage

Input Amplitude (Single-Ended,

AC-Coupled Mode)

360

1200

mV p-p Peak-to-peak single-ended voltage swing;

instantaneous voltage must not exceed 1.3 V

1.2 V and 1.8 V CMOS Input

Voltage

High, V_IH

0.65 × V_REF

1.15 × V_REF

0.35 × V_REF

V

V_REFis determined by operating mode of the CMOS

input receiver, 1.2 V or 1.8 V

Low, V_IL

Input Resistance

DC-Coupled Single-Ended Mode

AC-Coupled Single-Ended Mode

Input Pulse Width

30

15

kΩ

ps

900

Rev. 0 | Page 7 of 62

AD9544

Data Sheet

REFERENCE MONITORS

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REFERENCE MONITORS

Reference Monitor

Loss of Reference

Detection Time

4.9 + 0.13 × t_PFD

µs

t_PFDis the nominal phase detector period, R/f_REF, where R

is the frequency division factor determined by the R

divider, and f_REFis the frequency of the active reference

Frequency Out of

Range Limits

50

1.5 × 10⁷

ppb

Parts per billion (ppb) is defined as Δf/f_REF, where Δf is the

frequency deviation, and f_REFis the reference input

frequency; programmable with the lower bound, subject

to quality of the system clock (or the source of system

clock compensation); 1.5 × 10⁷is equivalent to 1.5%

Validation Timer

0.001

1

1048

sec

ns

Programmable in 1 ms increments

Programmable in 1 ns increments

Excess Jitter Alarm Threshold

65535

DPLL PHASE CHARACTERISTICS

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

MAXIMUM OUTPUT PHASE

PERTURBATION

Assumes a jitter free reference; satisfies Telcordia GR-1244-CORE

requirements; 0 ppm frequency difference between references;

reference switch initiated via register map (see the AD9544 Register

Map Reference Manual) by faulting the active reference input

Phase Refinement Disabled

50 Hz DPLL loop bandwidth; normal phase margin mode; frequency

translation = 19.44 MHz to 155.52 MHz; 49.152 MHz signal generator

used for system clock source

Peak

20

140 ps

Steady State

Phase Buildout Operation

Hitless Operation

Phase Refinement Enabled

18

0

125 ps

ps

50 Hz DPLL loop bandwidth; high phase margin mode; phase

refinement iterations = 4; frequency translation = 19.44 MHz to

155.52 MHz; 49.152 MHz signal generator used for system clock source

Peak

5

40

35

ps

Steady State

Phase Buildout Operation

Hitless Operation

PHASE SLEW LIMITER

4

0

ps

0.001

250

µs/sec See the AN-1420 Application Note, Phase Buildout and Hitless

Switchover with Digital Phase-Locked Loops (DPLLs)

Rev. 0 | Page 8 of 62

Data Sheet

AD9544

DISTRIBUTION CLOCK OUTPUTS

Table 8.

Parameter

Min

Typ

Max

Unit Test Conditions/Comments

DIFFERENTIAL MODE

Output Frequency

All testing is both ac-coupled and dc-coupled

Frequency range determined by driver

functionality; actual frequency synthesis may be

limited by the APLL VCO frequency range

CML

1

500 × 10⁶

Hz

Terminated per Figure 33

Terminated per Figure 32

HCSL

Differential Output Voltage Swing

Voltage between output pins measured with

output driver static; peak-to-peak differential

output amplitude is twice that shown when driver

is toggling and measured using a differential probe

Output Current = 7.5 mA

HCSL

312

257

368

348

402

408

mV

Terminated per Figure 32

CML

Terminated to VDD (nominal 1.8 V) per Figure 33

Output Current = 15 mA

HCSL

631

578

745

729

809

818

mV

Terminated per Figure 32

CML

Terminated to VDD (nominal 1.8 V) per Figure 33

Common-Mode Output Voltage

Output Current = 7.5 mA

HCSL

CML

155

184

201

mV

Terminated per Figure 32

VDD − 208 VDD − 188 VDD − 169 mV

Terminated to VDD (nominal 1.8 V) per Figure 33

(maximum common-mode voltage case occurs at

the minimum amplitude)

Output Current = 15 mA

HCSL

CML

316

372

405

mV

Terminated per Figure 32

VDD − 416 VDD − 371 VDD − 327 mV

Terminated to VDD (nominal 1.8 V) per Figure 33

(maximum common-mode voltage case occurs at

the minimum amplitude)

SINGLE-ENDED MODE

Output Frequency

1

500 × 10⁶

Hz

Frequency range determined by driver

functionality; actual frequency synthesis may be

limited by the APLL VCO frequency range

Output Current = 12 mA

Voltage Swing (Peak-to-Peak)

HCSL Driver Mode

509

456

584

565

634

644

mV

Each output terminated per Figure 37 with R_L= 50 Ω

CML Driver Mode

Each output terminated per Figure 37 with R_L= 50 Ω

connected to VDD (nominal 1.8 V) instead of GND

Voltage Swing Midpoint

HCSL Driver Mode

CML Driver Mode

255

292

317

mV

Each output terminated per Figure 37 with R_L= 50 Ω

VDD − 325 VDD − 291 VDD − 266 mV

Each output terminated per Figure 37 with R_L= 50 Ω

connected to VDD (nominal 1.8 V) instead of GND

Output Current = 15 mA

Voltage Swing (Peak-to-Peak)

HCSL Driver Mode

645

589

734

721

796

815

mV

Each output terminated per Figure 37 with R_L= 50 Ω

CML Driver Mode

Each output terminated per Figure 37 with R_L= 50 Ω

connected to VDD (nominal 1.8 V) instead of GND

Voltage Swing Midpoint

HCSL Driver Mode

CML Driver Mode

322

367

398

mV

Each output terminated per Figure 37 with R_L= 50 Ω

VDD − 411 VDD − 367 VDD − 334

Each output terminated per Figure 37 with R_L= 50 Ω

connected to VDD (nominal 1.8 V) instead of GND

Rev. 0 | Page 9 of 62

AD9544

Data Sheet

TIME DURATION OF DIGITAL FUNCTIONS

Table 9.

Parameter

Min Typ Max Unit

Test Conditions/Comments

TIME DURATION OF DIGITAL

FUNCTIONS

EEPROM to Register Download

Time

10

ms

Using the Typical Configuration from Table 3

Power-On Reset (POR)

25

1

ms

ns

Time from power supplies > 80% to release of internal reset

Mx refers to Pin M0 through Pin M6

Mx Pin to RESETB Rising Edge

Setup Time

Mx Pin to RESETB Rising Edge

Hold Time

2

ns

Multiple Mx Pin Timing Skew

39

14

ns

Applies only to multibit Mx pin functions

RESETB Falling Edge to Mx Pin

High-Z Time

TIME FROM START OF DPLL

ACTIVATION TO ACTIVE PHASE

DETECTOR OUTPUT

Untagged Operation

10

t_PFD

t_PFDis the nominal phase detector period given by R/f_REF, where R is the

frequency division factor determined by the R divider, and f_REFis the

frequency of the active reference

Tagged Operation

Tag

period

Tag period = (tag ratio/f_TAG), where f_TAGis either f_REF(for tagged reference

mode) or f_FEEDBACK(for all other tagged modes); the tag ratio corresponds to

the selection of f_TAG

DIGITAL PLL (DPLL0, DPLL1) SPECIFICATIONS

Table 10.

Parameter

Min

Typ Max

2 × 10⁵

Unit

Test Conditions/Comments

DIGITAL PLL

Digital Phase Detector (DPD)

Input Frequency Range

1

Hz

Loop Filter

Profile 0

Bandwidth

0.0001

1850

Hz

Programmable design parameter; (f_PFD/bandwidth) ≥ 20

Phase Margin

Closed-Loop Peaking

Profile 1

70

Degrees

dB

1.1

Bandwidth

305

0.1

Hz

Programmable design parameter; (f_PFD/bandwidth) ≥ 20

Phase Margin

Closed-Loop Peaking

88.5

Degrees

dB

In accordance with Telcordia GR-253-CORE jitter transfer

specifications

DIGITAL PLL NCO Division Ratio

These specifications cover limitations on the DPLLx frequency

tuning word (FTW0); the AD9544 evaluation software frequency

planning wizard sets these values automatically for the user, and

the AD9544 evaluation software is available for download from

the AD9544 product page; NCO division = 2⁴⁸/FTW0, which takes

the form INT.FRAC, where INT is the integer portion, and FRAC is

the fractional portion

NCO Integer

NCO Fraction

7

13

This is the integer portion of NCO division ratio

This is the fractional portion of NCO division ratio

0.05

0.95

Rev. 0 | Page 10 of 62

Data Sheet

AD9544

DIGITAL PLL LOCK DETECTION SPECIFICATIONS

Table 11.

Parameter

Min

Typ

1

Max

Unit

Test Conditions/Comments

PHASE LOCK DETECTOR

Threshold Programming Range

Threshold Resolution

10

2²⁴− 1 ps

ps

FREQUENCY LOCK DETECTOR

Threshold Programming Range

Threshold Resolution

10

2²⁴− 1 ps

ps

1

PHASE STEP DETECTOR

Threshold Programming Range

Threshold Resolution

100

2³²− 1 ps

ps

Setting this value too low causes false triggers

1

HOLDOVER SPECIFICATIONS

Table 12.

Parameter

Min

Typ

Max

Unit

ppb

Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy

0.01

0.1

AD9544 is configured using Configuration 1 from Table 21;

excludes frequency drift of system clock (SYSCLK) source;

excludes frequency drift of input reference prior to

entering holdover; 160 ms history timer; history holdoff

setting of 8; three holdover history features (bits) are

enabled: delay history until frequency lock bit, delay

history until phase lock bit, and delay holdover history

accumulation until not phase slew limited bit

Relative Frequency Accuracy

Between Channels

Cascaded Operation

0

ppb

268435 sec

History Averaging Window

0.001

ANALOG PLL (APLL0, APLL1) SPECIFICATIONS

Table 13.

Parameter

Min

Typ

Max

Unit

VCO FREQUENCY RANGE

Analog PLL0 (APLL0)

2424

3232

162

3232

4040

350

MHz

Analog PLL1 (APLL1)

MHz

PHASE FREQUENCY DETECTOR (PFD) INPUT FREQUENCY RANGE

LOOP BANDWIDTH

MHz

260

68

kHz

PHASE MARGIN

Degrees

OUTPUT CHANNEL DIVIDER SPECIFICATIONS

Table 14.

Parameter

Min

Typ

Max

Unit

t_VCO

Test Conditions/Comments

t_VCO= 1/(APLLx VCO frequency), where x = 0, 1

OUTPUT PHASE ADJUST STEP SIZE

1

Rev. 0 | Page 11 of 62

AD9544

Data Sheet

SYSTEM CLOCK COMPENSATION SPECIFICATIONS

Table 15.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ppt is parts per trillion (10⁻¹²

)

DIRECT COMPENSATION

Resolution

0.028

ppt

CLOSED-LOOP COMPENSATION (AUXILIARY DPLL)

Phase Detector Frequency

Loop Bandwidth

2

200

2 × 10³

kHz

Hz

%

0.1

Reference Monitor Threshold

5

TEMPERATURE SENSOR SPECIFICATIONS

Table 16.

Parameter

TEMPERATURE

Accuracy

Min

Typ

Max

Unit

Test Conditions/Comments

T_A= −50°C to +110°C

Absolute

5

°C

%

Relative

1.7

Resolution

Conversion Time

REPEATABILITY

DRIFT

0.0078

0.18

0.02

0.1

°C

ms

°C

16-bit (signed) resolution

T_A= 25°C

500 hour stress test at 100°C

SERIAL PORT SPECIFICATIONS

Serial Port Interface (SPI) Mode

Table 17.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CSB

Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

SCLK

VDDIOA − 0.4

V

0.4

V

1

µA

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

SDIO

VDDIOA − 0.4

V

0.4

V

1

µA

As an Input

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

As an Output

VDDIOA − 0.4

V

0.4

0.2

V

1

µA

Output Logic 1 Voltage

Output Logic 0 Voltage

SDO

VDDIOA − 0.2

V

1 mA load current

Output Logic 1 Voltage

Output Logic 0 Voltage

Leakage Current

V

1 mA load current

0.2

1

V

1 mA load current

µA

SDO inactive (high impedance)

Rev. 0 | Page 12 of 62

Data Sheet

AD9544

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TIMING

Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V

SCLK

Clock Rate, 1/t_CLK

50

MHz

ns

Pulse Width High, t_HIGH

Pulse Width Low, t_LOW

SDIO to SCLK Setup, t_DS

SCLK to SDIO Hold, t_DH

SCLK to Valid SDIO and SDO, t_DV

CSB to SCLK Setup, t_S

CSB to SCLK Hold, t_C

CSB Minimum Pulse Width High

5

9

ns

2.2

0

ns

9

ns

1.5

0

ns

1

t_CLK

I²C Mode

Table 18.

Parameter

Min

Typ Max

Unit

Test Conditions/Comments

SDA, SCL (AS INPUTS)

Input Logic 1 Voltage

Input Logic 0 Voltage

Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V

70

% of VDDIOA

V

0.3 ×

VDDIOA

Input Current

−10

1.5

+10

µA

For V_IN= 10% to 90% of VDDIOA

Hysteresis of Schmitt Trigger Inputs

SDA (AS OUTPUT)

% of VDDIOA

Output Logic 0 Voltage

0.2

V

I_OUT= 3 mA

Output Fall Time from V_IHMinimum

to V_ILMaximum

20 + 0.1 × C_B

250

ns

10 pF ≤ C_B≤ 400 pF

TIMING

SCL Clock Rate

400

kHz

µs

Bus Free Time Between a Stop and

Start Condition, t_BUF

1.3

0.6

Repeated Start Condition Setup

Time, t_{SU; STA}

µs

Repeated Hold Time Start

Condition, t_{HD; STA}

After this period, the first clock pulse is

generated

Stop Condition Setup Time, t_{SU; STO}

Low Period of the SCL Clock, t_LOW

High Period of the SCL Clock, t_HIGH

SCL/SDA Rise Time, t_R

0.6

µs

ns

pF

1.3

0.6

20 + 0.1 × C_B

100

300

SCL/SDA Fall Time, t_F

Data Setup Time, t_{SU; DAT}

Data Hold Time, t_{HD; DAT}

100

Capacitive Load for Each Bus Line, C_B

400

Rev. 0 | Page 13 of 62

AD9544

Data Sheet

LOGIC INPUT SPECIFICATIONS (RESETB, M0 TO M6)

Table 19.

Parameter

Min

Typ Max

Unit Test Conditions/Comments

RESETB

Valid for 3.3 V ≥ VDDIOA ≥ 1.8 V; internal 100 kΩ pull-up resistor

Input High Voltage (V_IH)

Input Low Voltage (V_IL)

VDDIOA − 0.4

V

0.4

125

V

Input Current High (I_INH

Input Current Low (I_INL

)

1

µA

)

15

LOGIC INPUTS (M0 to M6)

Valid for 3.3 V ≥ VDDIOx ≥ 1.8 V; VDDIOA applies to the M5 pin and

the M6 pin; VDDIOB applies to the M0, M1, M2, M3, and M4 pins;

the M3 and M4 pins have internal 100 kΩ pull-down resistors

Frequency Range

51

MHz

V

Input High Voltage (V_IH)

Input Low Voltage (V_IL)

Input Current (I_INH, I_INL)

VDDIOx − 0.4

0.4

125

V

µA

LOGIC OUTPUT SPECIFICATIONS (M0 TO M6)

Table 20.

Parameter

Min

Typ Max Unit Test Conditions/Comments

Valid for 3.3 V ≥ VDDIOx ≥ 1.8 V; VDDIOA applies for the M5 and

LOGIC OUTPUTS (M0 to M6)

M6 pins; VDDIOB applies for M0 to M4; normal (default) output

drive current setting for M0 through M6

Frequency Range

26

MHz

Output High Voltage (V_OH)

VDDIOx − 0.6

VDDIOx – 0.2

V

Load current = 10 mA

Load current = 1 mA

Load current = 10 mA

Load current = 1 mA

Output Low Voltage (V_OL)

0.6

0.2

JITTER GENERATION (RANDOM JITTER)

Table 21.

Parameter

Min Typ

Max Unit Test Conditions/Comments

System clock doubler enabled; high phase margin mode enabled;

JITTER GENERATION

there is not a significant jitter difference between driver modes

Channel 0—DPLL0, APLL0

Channel 1 powered down

RMS Jitter (12 kHz to 20 MHz)

Configuration 1—155.52 MHz

223

220

235

fs

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 38.88 MHz, f_VCO

2488.32 MHz, f_OUT= 155.52 MHz, BW_DPLL= 50 Hz, phase buildout

operation

=

Configuration 2—245.76 MHz

Configuration 3—491.52 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 30.72 MHz, f_VCO

2457.6 MHz, f_OUT= 245.76 MHz, BW_DPLL= 50 Hz, internal zero delay

operation

Device configuration: f_SYSCLK= 52 MHz XTAL, f_COMP= 19.2 MHz

temperature compensated crystal oscillator (TCXO), BW_COMP

50 Hz, f_REF= 1 Hz, f_VCO= 2949.12 MHz, f_OUT= 491.52 MHz, BW_DPLL

50 mHz, phase buildout operation

=

Configuration 4—125 MHz

213

217

230

fs

Device configuration: f_SYSCLK= 52 MHz XTAL, f_COMP= 19.2 MHz TCXO,

BW_COMP= 50 Hz, f_REF= 125 MHz, f_VCO= 2500 MHz, f_OUT= 125 MHz,

BW_DPLL= 0.1 Hz, phase buildout operation

Configuration 5—312.5 MHz

Configuration 6—174.7030837 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 25 MHz, f_VCO

2500 MHz, f_OUT= 312.5 MHz, BW_DPLL= 50 Hz, phase buildout

operation

=

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 155.52 MHz, f_VCO

2620.5463 MHz, f_OUT= (155.52 × 255/227) MHz, BW_DPLL= 50 Hz

=

Rev. 0 | Page 14 of 62

Data Sheet

AD9544

Parameter

Min Typ

Max Unit Test Conditions/Comments

Channel 1—DPLL1, APLL1

RMS Jitter (12 kHz to 20 MHz)

Configuration 1—155.52 MHz

Channel 0 powered down

247

280

323

243

266

264

fs

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 38.88 MHz, f_VCO

3265.92 MHz, f_OUT= 155.52 MHz, BW_DPLL= 50 Hz, phase buildout

operation, half divide enabled

=

Configuration 2—245.76 MHz

Configuration 3—491.52 MHz

Configuration 4—125 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 30.72 MHz, f_VCO

3686.4 MHz, f_OUT= 245.76 MHz, BW_DPLL= 50 Hz, half divide enabled,

internal zero delay operation

Device configuration: f_SYSCLK= 52 MHz XTAL, f_COMP= 19.2 MHz TCXO,

BW_COMP= 50 Hz, f_REF= 1 Hz, f_VCO= 3932.16 MHz, f_OUT= 491.52 MHz,

BW_DPLL= 50 mHz, phase buildout operation

Device configuration: f_SYSCLK= 52 MHz XTAL, f_COMP= 19.2 MHz TCXO,

BW_COMP= 50 Hz, f_REF= 125 MHz, f_VCO= 3250 MHz, f_OUT= 125 MHz,

BW_DPLL= 0.1 Hz, phase buildout operation

Configuration 5—312.5 MHz

Configuration 6—174.7030837 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 25 MHz, f_VCO

3750 MHz, f_OUT= 312.5 MHz, BW_DPLL= 50 Hz, phase buildout

operation

=

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 155.52 MHz,

f_VCO= 3319.3586 MHz, f_OUT= (155.52 × 255/227) MHz, BW_DPLL=

50 Hz, phase buildout operation

PHASE NOISE

Table 22.

Parameter

PHASE NOISE

Min Typ

Max Unit

Test Conditions/Comments

System clock doubler enabled; high phase margin mode

enabled; there is not a significant jitter difference between

driver modes

Channel 0—DPLL0, APLL0

Channel 1 powered down

RMS Jitter (12 kHz to 20 MHz)

Configuration 1—155.52 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 38.88 MHz,

f

_VCO= 2488.32 MHz, f_OUT= 155.52 MHz, BW_DPLL= 50 Hz,

phase buildout operation

10 Hz Offset

100 Hz Offset

1 kHz Offset

−81

dBc/Hz

−98

dBc/Hz

−118

−128

−134

−144

−158

−161

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

Configuration 2—245.76 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 30.72 MHz,

f_VCO= 2457.6 MHz, f_OUT= 245.76 MHz, BW_DPLL= 50 Hz, internal

zero delay operation

10 Hz Offset

100 Hz Offset

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

−77

dBc/Hz

−93

−114

−125

−130

−140

−156

−161

Rev. 0 | Page 15 of 62

AD9544

Data Sheet

Parameter

Min Typ

Max Unit

Test Conditions/Comments

Device configuration: f_SYSCLK= 52 MHz XTAL, f_COMP= 19.2 MHz

Configuration 3—491.52 MHz

TCXO, BW_COMP= 50 Hz, f_REF= 1 Hz, f_VCO= 2949.12 MHz, f_OUT

=

491.52 MHz, BW_DPLL= 50 mHz, phase buildout operation

10 Hz Offset

100 Hz Offset

1 kHz Offset

−74

dBc/Hz

−89

dBc/Hz

−108

−119

−123

−134

−152

−159

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

Configuration 4—125 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_COMP= 19.2 MHz

TCXO, BW_COMP= 50 Hz, f_REF= 125 MHz, f_VCO= 2500 MHz,

f

_OUT= 125 MHz, BW_DPLL= 0.1 Hz, phase buildout operation

10 Hz Offset

100 Hz Offset

1 kHz Offset

−84

dBc/Hz

−106

−120

−131

−136

−147

−160

−163

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

Configuration 5—312.5 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 25 MHz,

f_VCO= 2500 MHz, f_OUT= 312.5 MHz, BW_DPLL= 50 Hz, phase

buildout operation

10 Hz Offset

100 Hz Offset

−74

dBc/Hz

−91

1 kHz Offset

−112

−123

−128

−138

−154

−161

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

Configuration 6—174.7030837 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 155.52 MHz,

f

_VCO= 2620.5463 MHz, f_OUT= (155.52 × 255/227) MHz,

BW_DPLL= 50 Hz

10 Hz Offset

100 Hz Offset

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

−82

dBc/Hz

−99

−117

−127

−133

−143

−157

−160

Rev. 0 | Page 16 of 62

Data Sheet

AD9544

Parameter

Min Typ

Max Unit

Test Conditions/Comments

Channel 1—DPLL1, APLL1

RMS Jitter (12 kHz to 20 MHz)

Configuration 1—155.52 MHz

Channel 0 powered down

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 38.88 MHz,

f_VCO= 3265.92 MHz, f_OUT= 155.52 MHz, BW_DPLL= 50 Hz, phase

buildout operation, half divide enabled

10 Hz Offset

100 Hz Offset

1 kHz Offset

−81

dBc/Hz

−98

dBc/Hz

−118

−128

−132

−144

−158

−162

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

Configuration 2—245.76 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 30.72 MHz,

f_VCO= 3686.4 MHz, f_OUT= 245.76 MHz, BW_DPLL= 50 Hz, half

divide enabled; internal zero delay operation

10 Hz Offset

100 Hz Offset

1 kHz Offset

−76

dBc/Hz

−93

−114

−124

−127

−138

−156

−161

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

Configuration 3—491.52 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_COMP= 19.2 MHz

TCXO, BW_COMP= 50 Hz, f_REF= 1 Hz, f_VCO= 3932.16 MHz, f_OUT

=

491.52 MHz, BW_DPLL= 50 mHz, phase buildout operation

10 Hz Offset

100 Hz Offset

1 kHz Offset

−74

dBc/Hz

−90

−108

−118

−120

−131

−150

−160

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

Configuration 4—125 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_COMP= 19.2 MHz

TCXO, BW_COMP= 50 Hz, f_REF= 125 MHz, f_VCO= 3250 MHz,

f_OUT= 125 MHz, BW_DPLL= 0.1 Hz, phase buildout operation

10 Hz Offset

100 Hz Offset

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

−83

dBc/Hz

−106

−120

−131

−135

−145

−160

−163

Rev. 0 | Page 17 of 62

AD9544

Data Sheet

Parameter

Min Typ

Max Unit

Test Conditions/Comments

Configuration 5—312.5 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 25 MHz,

f_VCO= 3750 MHz, f_OUT= 312.5 MHz, BW_DPLL= 50 Hz,

phase buildout operation

10 Hz Offset

100 Hz Offset

−73

dBc/Hz

−91

dBc/Hz

1 kHz Offset

−112

−122

−125

−137

−154

−161

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

Configuration 6—174.7030837 MHz

Device configuration: f_SYSCLK= 52 MHz XTAL, f_REF= 155.52 MHz,

f_VCO= 3319.3586 MHz, f_OUT= (155.52 × 255/227) MHz,

BW_DPLL= 50 Hz

10 Hz Offset

100 Hz Offset

1 kHz Offset

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

Floor

−77

dBc/Hz

−99

−117

−127

−131

−142

−158

−161

Rev. 0 | Page 18 of 62

Data Sheet

AD9544

ABSOLUTE MAXIMUM RATINGS

Table 23.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required.

Parameter

Rating

2 V

1.8 V Supply Voltage (VDD)

Input/Output Supply Voltage

(VDDIOA, VDDIOB)

3.6 V

θ_JAis the junction to ambient thermal resistance, 0.0 m/sec

airflow per JEDEC JESD51-2 (still air).

Input Voltage Range (XOA, XOB,

REFA, REFAA, REFB, REFBB)

−0.5 V to VDD + 0.5 V

θ_JMAis the junction to ambient thermal resistance, 1.0 m/sec

airflow or 2.5 m/sec airflow per JEDEC JESD51-6 (moving air).

Digital Input Voltage Range

SDO/M5, SCLK/SCL, SDIO/SDA,

CSB/M6

−0.5 V to VDDIOA + 0.5 V

θ_JCis the junction to case thermal resistance (die to heat sink)

M0, M1, M2, M3, M4

−0.5 V to VDDIOB + 0.5 V

−65°C to +150°C

per MIL-STD 883, Method 1012.1.

Storage Temperature Range

Operating Temperature Range¹

Values of θ_JAare for package comparison and PCB design

considerations. θ_JAprovides for a first-order approximation

of T_Jper the following equation:

−40°C to +85°C

Lead Temperature (Soldering 10 sec) 300°C

¹See the Thermal Resistance section for additional information.

T_J= T_A+ (θ_JA× PD)

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

where T_Ais the ambient temperature (°C).

Values of θ_JCare for package comparison and PCB design

considerations when an external heat sink is required.

Table 24. Thermal Resistance

1

Package Type

θ_JA

θ_JMA

θ_JC

Unit

CP-48-13^{2, 3}

23.9

19.4, 18.2

1.5

°C/W

¹θ_JMAis 19.4°C/W at 1.0 m/sec airflow and 18.2°C/W at 2.5 m/sec airflow.

²Thermal characteristics derived using a JEDEC51-7 plus JEDEC51-5 2S2P test

board. The exposed pad on the bottom of the package must be soldered to

ground to achieve the specified thermal performance.

³Results are from simulations. The PCB is a JEDEC multilayer type. Thermal

performance for actual applications requires careful inspection of the

conditions in the application to determine if they are similar to those

assumed in these calculations.

ESD CAUTION

Rev. 0 | Page 19 of 62

AD9544

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

36 M3

35 M2

34 VDDIOB

SDO/M5

SCLK/SCL

VDDIOA

SDIO/SDA

CSB/M6

VDD

33

M1

32 M0

31 VDD

AD9544

TOP VIEW

(Not to Scale)

LDO0

LF0

VDD

30

29 LF1

28

LDO1

VDD

27 VDD

10

OUT0AP 11

OUT0AN 12

26

OUT1AN

25 OUT1AP

NOTES

1. EXPOSED PAD. THE EXPOSED PAD IS THE GROUND CONNECTION

ON THE CHIP. THE EXPOSED PAD MUST BE SOLDERED TO THE

ANALOG GROUND OF THE PCB TO ENSURE PROPER

FUNCTIONALITY AND FOR HEAT DISSIPATION, NOISE, AND

MECHANICAL STRENGTH BENEFITS.

2. DNC = DO NOT CONNECT. LEAVE THESE PINS FLOATING.

Figure 2. Pin Configuration

Table 25. Pin Function Descriptions

Input/

Pin No.

Mnemonic Output Pin Type

Description

1

SDO/M5

Output CMOS

Serial Data Output (SDO). This pin is for reading serial data in 4-wire SPI mode.

Changes to the VDDIOA supply voltage affect the V_IHand V_OHvalues for this pin.

Configurable Input/Output (M5).This pin is a status and control pin when the

device is not in 4-wire SPI mode.

2

SCLK/SCL

Input

CMOS

Serial Programming Clock (SCLK) Pin in SPI Mode. Changes to the VDDIOA supply

voltage affect the V_IHand V_OHvalues for this pin.

Serial Clock Pin (SCL) in I²C Mode. Changes to the VDDIOA supply voltage affect the

V_IHand V_OHvalues for this pin.

3

4

VDDIOA

Power

CMOS

Serial Port Power Supply. The valid supply voltage is 1.8 V, 2.5 V, or 3.3 V. The

VDDIOA pin can be connected to the VDD supply bus if 1.8 V operation is desired.

SDIO/SDA

Input/

output

Serial Data Input/Output in SPI Mode (SDIO). Write data to this pin in 4-wire SPI

mode. This pin has no internal pull-up or pull-down resistor. Changes to the VDDIOA

supply voltage affect the V_IHand V_OHvalues for this pin.

Serial Data Pin in I²C Mode (SDA).

5

CSB/M6

VDD

Input/

output

CMOS

Chip Select in SPI Mode (CSB). Active low input. Maintain a Logic 0 level on this pin

when programming the device in SPI mode. This pin has an internal 10 kΩ pull-up

resistor. Changes to the VDDIOA supply voltage affect the V_IHand V_OHvalues for this pin.

Configurable Input/Output (M6). This pin is a status and control pin when the

device is not in SPI mode.

6, 9, 10, 13,

19, 20, 24,

27, 28, 31,

40, 41, 45

Input

Power

1.8 V Power Supply.

7

LDO0

LDO bypass

APLL0 Loop Filter Voltage Regulator. Connect a 0.22 μF capacitor from this pin to

ground. This pin is the ac ground reference for the integrated APLL0 loop filter.

8

LF0

Input/

output

Loop filter

for APLL0

Loop Filter Node for APLL0. Connect a 3.9 nF capacitor from this pin to Pin 7

(LDO0).

11

12

OUT0AP

OUT0AN

Output HCSL, LVDS,

CML, CMOS

PLL0 Output 0A.

Output HCSL, LVDS,

CML, CMOS

PLL0 Complementary Output 0A.

Rev. 0 | Page 20 of 62

Data Sheet

AD9544

Input/

Mnemonic Output Pin Type

Pin No.

Description

14

OUT0BP

Output HCSL, LVDS,

CML, CMOS

PLL0 Output 0B.

15

OUT0BN

Output HCSL, LVDS,

CML, CMOS

PLL0 Complementary Output 0B.

16, 21, 44

17

DNC

No Connect

Do Not Connect. Leave these pins floating.

PLL0 Output 0C.

OUT0CP

Output HCSL, LVDS,

CML, CMOS

18

22

23

25

26

29

30

OUT0CN

OUT1BP

OUT1BN

OUT1AP

OUT1AN

LF1

Output HCSL, LVDS,

CML, CMOS

PLL0 Complementary Output 0C.

PLL1 Output 1B.

Output HCSL, LVDS,

CML, CMOS

Output HCSL, LVDS,

CML, CMOS

PLL1 Complementary Output 1B.

PLL1 Output 1A.

Output HCSL, LVDS,

CML, CMOS

Input/

HCSL, LVDS,

PLL1 Complementary Output 1A.

Output CML, CMOS

Input/

output

Loop filter

for APLL1

Loop Filter Node for APLL1. Connect a 3.9 nF capacitor from this pin to Pin 30 (LDO1).

LDO1

Input

LDO bypass

APLL1 Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from this pin to

ground. This pin is the ac ground reference for the integrated APLL1 loop filter.

32, 33, 35,

36, 37

M0, M1,

M2, M3, M4 output

Input/

CMOS

Configurable Input/Output Pins. These are status and control pins. Changes to the

VDDIOB supply voltage affect the V_IHand V_OHvalues for these pins. M3 and M4 have

internal 100 kΩ pull-down resistors. M0, M1, and M2 do not have internal resistors.

34

38

VDDIOB

REFB

Input

Power

Mx Pin Power Supply. This power supply powers the digital section that controls

the M0 to M4 pins. Valid supply voltages are 1.8 V, 2.5 V, or 3.3 V. The VDDIOB pin

can be connected to the VDD supply bus if 1.8 V operation is desired.

1.8 V single- Reference B Input. This internally biased input is typically ac-coupled; when

ended or

differential

input

configured in this manner, it can accept any differential signal with a single-ended

swing up to the VDD power supply. If dc-coupled, the input can be LVDS or single-

ended 1.8 V CMOS.

39

42

REFBB

XOA

Input

1.8 V single- Reference BB Input or Complementary Reference B Input. If REFB is in differential

ended or

differential

input

mode, the REFB complementary signal is on this pin. No connection is necessary to

this pin if REFB is a single-ended input and REFBB is not used.

Differential

input

System Clock Input. XOA contains internal dc biasing and is ac-coupled with a 0.01 μF

capacitor except when using a crystal. When a crystal is used, connect the crystal

across XOA and XOB. A single-ended CMOS input is also an option, but it can

produce spurious spectral content when the duty cycle is not 50%. When using

XOA as a single-ended input, connect a 0.1 μF capacitor from XOB to ground.

43

46

XOB

Input

Differential

input

Complementary System Clock Input. Complementary signal to XOA. XOB contains

internal dc biasing and is ac-coupled with a 0.1 μF capacitor except when using a

crystal. When a crystal is used, connect the crystal across XOA and XOB.

REFAA

1.8 V single- Reference AA input or Complementary REFA Input. If REFA is in differential mode,

ended or

differential

input

the REFA complementary signal is on this pin. No connection is necessary to this

pin if REFA is a single-ended input and REFAA is not used. If dc-coupled, the input

is single-ended 1.8 V CMOS.

47

REFA

Input

1.8 V single- Reference A Input. This internally biased input is typically ac-coupled; when

ended or

differential

input

configured in this manner, it can accept any differential signal with a single-ended

swing up to the VDD power supply. If dc-coupled, the input can be LVDS or single-

ended 1.8 V CMOS.

48

EP

RESETB

EPAD

1.8 V CMOS

logic

Active Low Chip Reset. This pin has an internal 100 kΩ pull-up resistor. When

asserted, the chip goes into reset. Changes to the VDDIOA supply voltage affect the

V_IHvalues for this pin.

Output Exposed

pad

Exposed Pad. The exposed pad is the ground connection on the chip. The exposed

pad must be soldered to the analog ground of the PCB to ensure proper functionality

and for heat dissipation, noise, and mechanical strength benefits.

Rev. 0 | Page 21 of 62

AD9544

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

–30

–40

INTEGRATED RMS JITTER

(12kHz TO 20MHz): 213fs

–40

–50

(12kHz TO 20MHz): 224fs

f

_OUT= 155.52MHz

f

_OUT= 125.0MHz

–50

PHASE NOISE (dBc/Hz):

–60

10Hz

–81

10Hz

–84

100Hz

1kHz

–98

100Hz

1kHz

–106

–120

–131

–136

–147

–160

–163

–70

–118

–128

–134

–144

–158

–159

–161

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–100

–110

–120

–130

–140

–150

–160

–170

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 3. Absolute Phase Noise (PLL0, Configuration 1, HCSL Mode,

f_REF= 38.88 MHz, f_OUT= 155.52 MHz, f_SYS= 52 MHz Crystal, BW_DPLL= 50 Hz)

Figure 6. Absolute Phase Noise (PLL0, Configuration 4, HCSL Mode,

f_REF= 125 MHz, f_OUT= 125.0 MHz, f_COMP= 19.2 MHz TCXO, f_SYS= 52 MHz Crystal,

BW_DPLL= 0.1 Hz, Phase Buildout Mode)

–30

INTEGRATED RMS JITTER

(12kHz TO 20MHz): 217fs

INTEGRATED RMS JITTER

(12kHz TO 20MHz): 220fs

–40

f

_OUT= 312.5MHz

PHASE NOISE (dBc/Hz):

f

_OUT= 245.76MHz

PHASE NOISE (dBc/Hz):

–50

–60

–50

–60

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

–74

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

–77

–91

–93

–70

–112

–123

–128

–138

–154

–157

–161

–114

–125

–130

–140

–156

–158

–161

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–100

–110

–120

–130

–140

–150

–160

–170

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 7. Absolute Phase Noise (PLL0, Configuration 5, HCSL Mode,

f_REF= 25 MHz, f_OUT= 312.5 MHz, f_SYS= 52 MHz Crystal, BW_DPLL= 50 Hz,

Phase Buildout Mode)

Figure 4. Absolute Phase Noise (PLL0, Configuration 2, HCSL Mode,

f_REF= 30.72 MHz, f_OUT= 245.76 MHz, f_SYS= 52 MHz Crystal, BW_DPLL= 50 Hz)

–30

INTEGRATED RMS JITTER

–40

–50

–40

–50

(12kHz TO 20MHz): 234.5fs

(12kHz TO 20MHz): 230fs

f_OUT= 491.52MHz

PHASE NOISE (dBc/Hz):

f_OUT= 174.7MHz

PHASE NOISE (dBc/Hz):

–60

10Hz

–74

10Hz

–82

100Hz

1kHz

–89

100Hz

1kHz

–99

–70

–108

–119

–123

–134

–152

–155

–159

–117

–127

–133

–143

–157

–158

–160

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–100

–110

–120

–130

–140

–150

–160

–170

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 5. Absolute Phase Noise (PLL0, Configuration 3, HCSL Mode,

f_REF= 1 Hz, f_OUT= 491.52 MHz, f_COMP= 19.2 MHz TCXO, f_SYS= 52 MHz Crystal,

BW_DPLL= 50 Hz)

Figure 8. Absolute Phase Noise (PLL0, Configuration 6, HCSL Mode,

f_REF= 155.52 MHz, f_OUT= 174.7 MHz, f_SYS= 52 MHz Crystal, BW_DPLL= 50 Hz,

Phase Buildout Mode)

Rev. 0 | Page 22 of 62

Data Sheet

AD9544

–30

–40

–30

–40

INTEGRATED RMS JITTER

(12kHz TO 20MHz): 255fs

INTEGRATED RMS JITTER

(12kHz TO 20MHz): 243fs

f

_OUT= 155.52MHz

PHASE NOISE (dBc/Hz):

f

_OUT= 125.0MHz

PHASE NOISE (dBc/Hz):

–50

–60

10Hz

–81

10Hz

–83

100Hz

1kHz

–98

100Hz

1kHz

–106

–120

–131

–135

–145

–160

–163

–70

–118

–128

–132

–143

–158

–160

–162

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–100

–110

–120

–130

–140

–150

–160

–170

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 9. Absolute Phase Noise (PLL1, Configuration 1, HCSL Mode,

f_REF= 38.88 MHz, f_OUT= 155.52 MHz, f_SYS= 52 MHz Crystal, BW_DPLL= 50 Hz)

Figure 12. Absolute Phase Noise (PLL1, Configuration 4, HCSL Mode,

f_REF= 125 MHz, f_OUT= 125 MHz, f_COMP= 19.2 MHz TCXO, f_SYS= 52 MHz

Crystal, BW_DPLL= 0.1 Hz, Phase Buildout Mode)

–30

INTEGRATED RMS JITTER

–40

–50

–40

–50

(12kHz TO 20MHz): 280fs

(12kHz TO 20MHz): 266fs

f

_OUT= 245.76MHz

f_OUT= 312.5MHz

PHASE NOISE (dBc/Hz):

–60

10Hz

–76

10Hz

–73

100Hz

1kHz

–93

100Hz

1kHz

–91

–70

–114

–124

–127

–138

–156

–159

–161

–112

–122

–125

–137

–154

–158

–161

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–100

–110

–120

–130

–140

–150

–160

–170

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 10. Absolute Phase Noise (PLL1, Configuration 2, HCSL Mode,

f_REF= 30.72 MHz, f_OUT= 245.76 MHz, f_SYS= 52 MHz Crystal, 50 Hz DPLL BW)

Figure 13. Absolute Phase Noise (PLL1, Configuration 5, HCSL Mode,

f_REF= 25 MHz, f_OUT= 312.5 MHz, f_SYS= 52 MHz Crystal, BW_DPLL= 50 Hz,

Phase Buildout Mode)

–30

INTEGRATED RMS JITTER

–40

–50

–40

–50

(12kHz TO 20MHz): 322.7fs

(12kHz TO 20MHz): 264fs

f

_OUT= 491.52MHz

f_OUT= 174.7MHz

PHASE NOISE (dBc/Hz):

–60

10Hz

–74

10Hz

–77

100Hz

1kHz

–90

100Hz

1kHz

–99

–70

–108

–118

–120

–131

–150

–154

–160

–117

–127

–131

–142

–158

–159

–161

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

10kHz

100kHz

1MHz

10MHz

>30MHz

FLOOR

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

–100

–110

–120

–130

–140

–150

–160

–170

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 11. Absolute Phase Noise (PLL1, Configuration 3, HCSL Mode,

f_REF= 1 Hz, f_OUT= 491.52 MHz, f_COMP= 19.2 MHz TCXO, f_SYS= 52 MHz Crystal,

50 MHz DPLL BW)

Figure 14. Absolute Phase Noise (PLL1, Configuration 6, HCSL Mode,

f_REF= 155.52 MHz, f_OUT= 174.7 MHz, f_SYS= 52 MHz Crystal, BW_DPLL= 50 Hz,

Phase Buildout Mode)

Rev. 0 | Page 23 of 62

AD9544

Data Sheet

1.0

0.8

800

700

600

500

400

300

200

100

HCSL, 15mA

CML, 15mA

7.5mA MODE

15mA MODE

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

1

2

3

4

5

6

7

8

9

10

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

TIME (Seconds)

TIME (ns)

Figure 15. DC-Coupled, Single-Ended, 1 Hz Output Waveforms Using HCSL

7.5 mA and 15 mA Mode Terminated 50 Ω to GND per Figure 38;

Slew Rate: ~7 V/ns for 15 mA Mode; ~3.5 V/ns for 7.5 mA Mode

Figure 18. 245.76 MHz Output Waveform for 15 mA Driver Settings;

HCSL Drivers Terminated 50 Ω to GND per Figure 32;

CML Drivers Terminated 50 Ω to 1.8 V per Figure 33

1.0

0.8

1.0

HCSL, 15mA

CML, 15mA

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.2

–0.4

–0.6

–0.8

–1.0

–0.8

HCSL, 7.5mA (SLEW RATE ~2.4V/ns)

CML, 7.5mA (SLEW RATE ~2.7V/ns)

–1.0

HCSL, 15mA (SLEW RATE ~5.4V/ns)

CML, 15mA (SLEW RATE ~6V/ns)

–1.2

0

50

100

150

200

250

300

350

400

0

1

2

3

4

5

6

7

8

9

10

TIME (μs)

TIME (ns)

Figure 16. 8 kHz Output Waveforms for Various Driver Settings;

HCSL Drivers Terminated 50 Ω to GND per Figure 32;

CML Drivers Terminated 50 Ω to 1.8 V per Figure 33

Figure 19. 491.52 MHz Output Waveform for15 mA Driver Settings;

HCSL Drivers Terminated 50 Ω to GND per Figure 32;

CML Drivers Terminated 50 Ω to 1.8 V per Figure 33

1.0

2000

1800

1600

1400

1200

1000

800

HCSL, 7.5mA, 10MHz

CML, 7.5mA, 10MHz

HCSL, 15mA, 10MHz

CML, 15mA, 10MHz

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

600

CML, DIFFERENTIAL, 15mA

CML, DIFFERENTIAL, 12.5mA

CML, DIFFERENTIAL, 7.5mA

HCSL, DIFFERENTIAL, 15mA

HCSL, DIFFERENTIAL, 12.5mA

HCSL, DIFFERENTIAL, 7.5mA

400

200

0

20

40

60

80

100 120 140 160 180 200

1

10

100

1k

10k 100k

1M

10M 100M 1G

TIME (ns)

FREQUENCY (Hz)

Figure 17. 10 MHz Output Waveforms for Various Driver Settings;

HCSL Drivers Terminated 50 Ω to GND per Figure 32;

CML Drivers Terminated 50 Ω to 1.8 V per Figure 33

Figure 20. Differential Output Amplitude Waveforms;

HCSL Drivers Terminated 50 Ω to GND per Figure 32;

CML Drivers Terminated 50 Ω to 1.8 V per Figure 33

Rev. 0 | Page 24 of 62

Data Sheet

AD9544

5

0

BW = 10mHz

BW = 100mHz

BW = 1Hz

BW = 10Hz

BW = 100Hz

0

–5

–10

–15

–20

–10

–15

–20

BW = 10mHz

BW = 100mHz

BW = 1Hz

BW = 10Hz

BW = 100Hz

PHASE MARGIN:70°

PEAKING: 1.07dB

ATTENUATION:

PHASE MARGIN:88.5°

PEAKING: <0.1dB

ATTENUATION:

AT LOOP BW: 5.5dB

2× LOOP BW: 18dB/DECADE

100× LOOP BW: 41dB/DECADE

1000× LOOP BW: 60dB/DECADE

–25

–25 AT LOOP BW: 2.5dB

2× LOOP BW: 21dB/

DECADE

100× LOOP BW: 60dB/

DECADE

–30

0.001

–30

0.001

0.01

0.1

1

10

100

1k

0.01

0.1

1

10

100

1000

OFFSET FREQUENCY (Hz)

Figure 22. DPLL Closed-Loop Transfer Function High Phase Margin Loop

Filter Setting

Figure 21. DPLL Closed-Loop Transfer Function Nominal Phase Margin

Loop Filter Setting

Rev. 0 | Page 25 of 62

AD9544

Data Sheet

TERMINOLOGY

Zero Delay

Phase Buildout (PBO) Switchover

Zero delay is seen in an integer-N PLL architecture that establishes

zero (or nearly zero, but constant) phase offset between the final

output signal and the signal appearing at the reference input of

the PLL phase detector. A PLL with zero delay provides minimal

input to output phase offset in the static (steady state) sense.

That is, phase slewing at the output typically occurs any time

the PLL is in the process of phase or frequency acquisition (for

example, when a multiple input PLL switches from one input

reference signal to another).

PBO only applies to PLLs with the ability to switch from

one reference signal to another. PBO is the ability of a PLL to

switch between two reference signals having an arbitrary initial

instantaneous phase offset, whereby the phase of the output

signal remains fixed. This mode of operation implies the ability

of the PLL to absorb the phase difference between the two

reference input signals, the goal being to prevent a phase

disturbance at the output when switching between two

reference signals. Prevention of a phase disturbance at the

output means there is no guarantee of phase alignment between

the input and output signals. Unlike hitless switchover, PBO

places no restriction on the output/input frequency ratio. PBO

output phase transient prevention applies any time the PLL is in

the process of phase or frequency acquisition (that is, it is not

necessarily limited to reference switching).

Hitless Switchover

Hitless switchover applies to PLLs with the ability to switch

from one reference signal to another while maintaining a

constant phase relationship from the active input to output.

Hitless switchover is the ability of a PLL to switch between

reference signals having an arbitrary initial instantaneous

phase offset. In hitless switching, the output signal slews in a

prescribed manner from its initial phase to the new phase, and

the absolute phase relationship from active input to output is

maintained. The reference switching scheme is hitless if the

phase slewing is gradual enough to not cause traffic hits caused

by the output clock phase slewing. A PLL employing hitless

switchover capability requires the output/input frequency ratio

to be an integer greater than or equal to 1. Hitless output phase

transient limitation applies any time the PLL is in the process of

phase or frequency acquisition (that is, it is not necessarily

limited to reference switching).

For more information, see the AN-1420 Application Note, Phase

Buildout and Hitless Switchover with Digital Phase-Locked Loops

(DPLLs).

Rev. 0 | Page 26 of 62

Data Sheet

AD9544

THEORY OF OPERATION

OVERVIEW

The AD9544 has five differential output drivers. Each of the five

output drivers has a dedicated 32-bit programmable Q divider.

Each differential driver operates up to 500 MHz and is configura-

ble as a CML driver with external pull-up resistors, or an HCSL

driver with external pull-down resistors. There are three drive

strengths:

The AD9544 provides clocking outputs that are directly related

in phase and frequency to the selected (active) reference but

with jitter characteristics governed by the system clock, the

DCO, and the analog output PLL (APLL). The AD9544 supports

up to four reference inputs and input frequencies ranging from

1 Hz to 750 MHz. The cores of this device are two DPLLs. Each

DPLL has a programmable digital loop filter that greatly

reduces jitter transferred from the active reference to the output,

and these four DPLLs operate completely independently of each

other. The AD9544 supports both manual and automatic

holdover. While in holdover, the AD9544 continues to provide an

output as long as the system clock is present. The holdover

output frequency is a time average of the output frequency

history prior to the transition to the holdover condition. The

device offers manual and automatic reference switchover

capability if the active reference is degraded or fails completely.

•

The 7.5 mA mode is used for CML and HCSL and

ac-coupled LVDS. When used as an LVDS-compatible

driver, it must be ac-coupled and terminated with a 100 Ω

resistor across the differential pair.

•

The 15 mA mode produces a voltage swing and is compatible

with LVPECL. If LVPECL dc signal levels are required, the

designer must ac couple and rebias the AD9544 output.

The 15 mA mode can also be used with the termination

scheme shown in Figure 34 and Figure 35 to produce an

LVDS signal with the correct LVDS dc bias.

•

The 12 mA mode is halfway in between the two other settings.

The AD9544 includes a system clock multiplier and two DPLLs,

each cascaded with its own APLL.

REFERENCE INPUT PHYSICAL CONNECTIONS

Two pairs of pins (REFA/REFAA and REFB/REFBB) provide

access to the reference clock receivers. The user can reconfigure

each differential pair into two single-ended reference inputs. To

accommodate input signals with slow rising and falling edges,

both the differential and single-ended input receivers employ

hysteresis. Hysteresis also ensures that a disconnected or

floating input does not cause the receiver to oscillate.

The input signal goes first to the DPLL, which performs the

jitter cleaning and most of the frequency translation. Each DPLL

features a 48-bit DCO output that generates a signal in the range

of 162 MHz to 350 MHz.

The DCO output goes to the APLL, which multiplies the signal

up to a range of 2.424 GHz to 3.232 GHz (for Channel 0) or

3.232 GHz to 4.040 GHz (for Channel 1). After division by 2, this

signal is sent to the clock distribution section, which consists of

the 32-bit Q divider and output driver for each output. Channel 0

has six Q dividers and Channel 1 has four Q dividers.

When configured for differential operation, the input receivers

accommodate either ac-coupled or dc-coupled input signals.

If the input receiver is configured for dc-coupled LVDS mode,

the input receivers are capable of accepting dc-coupled LVDS

signals. The receiver is internally dc biased to handle ac-coupled

operation; however, there is no internal 50 Ω or 100 Ω termination.

The XOA and XOB inputs provide the input for the system clock.

These pins accept a reference clock in the 20 MHz to 300 MHz

range or a 25 MHz to 52 MHz crystal connected directly across

the XOA and XOB inputs. The system clock provides the clocks to

the frequency monitors, the DPLLs, and internal logic.

Rev. 0 | Page 27 of 62

AD9544

Data Sheet

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

SYSTEM CLOCK INPUTS

C

TUNE

0.1µF

150Ω

330Ω

XOA

3.3V

CMOS

TCXO

XOA

25MHz TO 60MHz

FUNDAMENTAL

AT-CUT CRYSTAL

AD9544

0.1µF

XOB

C

TUNE

Figure 24. System Clock Input (XOA, XOB) when Using a TCXO/OCXO with

3.3 V CMOS Output

Figure 23. System Clock Input (XOA/XOB) in Crystal Mode

(Each C_TUNEShunt Capacitor Shown Must Equal 2× (C_LOAD− C_STRAY

,

Where Typical C_STRAY= 2 pF to 5 pF)

REFERENCE CLOCK INPUTS

LVDS DRIVER

LEVEL SHIFT

REFx

AD9544

OR

(1.2V COMMON-MODE)

AD9544

1.8V RECEIVER

REFxx

30kΩ

R1

CMOS

DRIVER

REFx

20µA

R2

HI-Z

INPUT

20µA

1.2V

100Ω

20µA

INTERNAL DC THRESHOLD

FOR 1.2V OR 1.8V CMOS

20µA

REFxx

30kΩ

Figure 28. Differential LVDS Input Mode

Figure 25. Single-Ended DC-Coupled Mode, 1.2 V or 1.8 V CMOS

REFx

1.2V

AD9544

OR

DIFFERENTIAL

DRIVER

R

L

AD9544

47kΩ

REFxx

(OPTIONAL)

1.8V RECEIVER

DRIVER

47kΩ

0.1µF

47Ω

0.1µF

REFx

0.6V

R

L

0.1µF

0.6V

REFxx

47Ω

Figure 29. Differential AC-Coupled Mode (R_L= 100 Ω Is Recommended,

Except For HCSL)

Figure 26. Single-Ended AC-Coupled Mode

REFx

1.2V

OR

DIFFERENTIAL DRIVER

AD9544

47kΩ

REFxx

(0.6V COMMON-MODE)

DRIVER

REFx

R

L

0.6V

REFxx

Figure 27. Single-Ended Internal Pull-Up Mode

Figure 30. Differential DC-Coupled Mode

Rev. 0 | Page 28 of 62

Data Sheet

AD9544

CLOCK OUTPUTS

AD9544

OUTxyP

0.1µF

I

50Ω

Q

XY

LVDS OR

LVPECL

RECEIVER

+1.8V

I

100Ω

PLLx

50Ω

Q

XYY

OUTxyN

LVDS: USE 7.5mA DRIVER SETTING.

LVPECL: USE 15mA DRIVER SETTING.

I-SOURCE MODE

Figure 31. LVDS-Compatible Output Swing, AC-Coupled (V p-p ≈ 375 mV per Section for I = 15 mA

AD9544

OUTxyP

56.2Ω 453Ω

I

50Ω

Q

XY

TO HCSL

RECEIVER

1.8V

+1.8V

I

PLLx

56.2Ω 453Ω

OUTxyN

50Ω

Q

XYY

OUTxyN

I-SOURCE MODE

I-SINK MODE

Figure 36. 2.5 V LVPECL or Double Amplitude LVDS-Compatible Boost

Output, 1.5 V p-p, 1.24 V Common-Mode (I = 15 mA)

Figure 32. HCSL Output, V p-p ≈ 750 mV per Section (I = 15 mA)

AD9544

OUTxyP

I

R

50Ω

Q

L

Q

XY

1.2V, 1.5V

OR 1.8V

IN PHASE

OUTPUTS

+1.8V

I

PLLx

R

50Ω

L

I

Q

XYY

OUTxyN

I-SOURCE MODE

I-SINK MODE

Figure 37. Single-Divider, Single-Ended Mode Providing In-Phase Outputs

(Current Source Mode)

Figure 33. CML Output (I = 7.5 mA; I = 15 mA Options for 1.5 V or 1.8 V Supply)

AD9544

OUTxyP

I

R

I

50Ω

Q

L

XY

Q

XY

50Ω

INDEPENDENT

OUTPUTS

1.8V

+1.8V

I

R

L

PLLx

10nF

R

Q

XYY

Q

XYY

OUTxyN

I-SOURCE MODE

I-SINK MODE

Figure 38. Dual-Divider, Single-Ended Mode Providing Independent Outputs

(Current Source Mode); Note that Single-Ended CML Mode Is Also Available

(See Figure 33)

Figure 34. LVDS-Compatible Output, 1.24 V Common-Mode, T Network

(I = 7.5 mA; I = 15 mA with Extra 100 Ω Termination, R_L)

AD9544

OUTxyP

63.4Ω 237Ω

I

Q

XY

1.8V

R

L

PLLx

63.4Ω 237Ω

Q

XYY

OUTxyN

I-SINK MODE

Figure 35. LVDS-Compatible Output, 1.2 V Common-Mode, Thevenin Bias

Network (I = 7.5 mA; 15 mA With Extra 100 Ω Termination, R_L)

Rev. 0 | Page 29 of 62

AD9544

Data Sheet

SYSTEM CLOCK PLL

Note that throughout the System Clock PLL section, unless

otherwise specified, any referenced bits, registers, or bit fields

reside in the system clock (SYSCLK) section of the register map

(Register 0x0200 to Register 0x0209).

Crystal Path

The crystal path supports crystal resonators in the 25 MHz to

60 MHz frequency range. An internal maintaining amplifier

provides the negative resistance required to induce oscillation. The

internal amplifier expects an AT cut, fundamental mode crystal

with a maximum motional resistance of 100 Ω for crystals up to

52 MHz, and 50 Ω for crystals up to 60 MHz. The following

crystals, listed in alphabetical order, may meet these criteria.

The system clock PLL (see Figure 39) comprises an integer-N

frequency synthesizer with a fully integrated loop filter and voltage

controlled oscillator (VCO). The VCO output is the AD9544

system clock with a frequency range of 2250 MHz to 2415 MHz.

The XOA and XOB pins constitute the input to the system clock

PLL to which a user connects a clock source or crystal resonator.

•

AVX/Kyocera CX3225SB

ECS, Inc. ECX-32

Epson/Toyocom TSX-3225

Fox FX3225BS

AD9544

LOCK

DETECTOR

VCO

CALIBRATION

XTAL

2×

XOA

XOB

NDK NX3225SA

PFD,

CHARGE PUMP,

LOOP FILTER

SYSTEM

CLOCK

÷J

1, 2, 4, 8

Siward SX-3225

2250MHz TO

2415MHz

Suntsu SCM10B48-49.152 MHz

DIRECT

÷K

4 TO 255

Analog Devices, Inc., does not guarantee the operation of the

AD9544 with the aforementioned crystals, nor does Analog

Devices endorse one crystal supplier over another. The AD9544

reference design uses a readily available high performance

49.152 MHz crystal with low spurious content.

Figure 39. System Clock PLL Block Diagram

SYSTEM CLOCK INPUT FREQUENCY

DECLARATION

Proper operation of the AD9544 requires the user to declare

the input reference frequency to the system clock PLL. To do

so, program the SYSCLK reference frequency bit field, which

constitutes the nominal frequency of the system clock PLL

input reference. The AD9544 evaluation software frequency

planning wizard calculates this value for the user.

Direct Path

The direct path has a differential receiver with a self bias of

0.6 V dc. Generally, the presence of the bias voltage necessitates

the use of ac coupling between the external source and the XOA

and XOB pins. Furthermore, when using a 3.3 V CMOS oscillator

as the system clock PLL reference source, in addition to ac

coupling, it is important to use a voltage divider to reduce the

3.3 V swing to a maximum of 1.14 V (note that the optimal

voltage swing is 800 mV p-p). The external signal must exhibit a

50% duty cycle for best performance.

SYSTEM CLOCK SOURCE

The XOA and XOB pins serve as the input connection to the

system clock PLL, giving the user access to a crystal path (see

Figure 23) or a direct path (see Figure 24). Path selection is via

the enable maintaining amplifier bit, where a Logic 0 (default)

selects the direct path and Logic 1 selects the crystal path. The

optimal reference source for the system clock input is a crystal

resonator in the 50 MHz range or an ac-coupled square wave

source (single-ended or differential) with 800 mV p-p

amplitude.

The direct path supports low frequency LVPECL, LVDS,

CMOS, or sinusoidal clock sources as a reference to the system

clock PLL. For a sinusoidal source, however, it is best to use a

frequency of 50 MHz or greater. The low slew rate of lower

frequency sinusoids tends to yield nonoptimal noise performance.

Applications requiring low DPLL loop bandwidth require the

improved stability provided by a TCXO or OCXO. Loop

bandwidths below approximately 50 Hz may prevent the PLL

from locking or cause random loss of lock events when using a

less stable PLL reference source.

Although one method to mitigate this problem is to use a high

stability system clock source (such as an OCXO), the AD9544

provides integrated system clock compensation capability,

which lessens the stability requirements on the system clock

while providing the outstanding phase noise of the higher

frequency crystal. To use this feature, connect a 40 MHz to

60 MHz crystal to the XOA/XOB pins (as in Figure 23), and

connect either a TCXO or OCXO to either an unused reference

input or an Mx pin (as shown in Figure 24).

Rev. 0 | Page 30 of 62

Data Sheet

AD9544

2× FREQUENCY MULTIPLIER

SYSTEM CLOCK PLL LOCK DETECTOR

The system clock PLL provides the user with the option of

doubling the reference frequency via the enable SYSCLK

doubler bit. Doubling the input reference frequency potentially

reduces the PLL in-band noise. The reference frequency must be

less than 150 MHz when using the 2× frequency multiplier to

satisfy the 300 MHz maximum PFD rate. Furthermore, the 2×

frequency multiplier requires the reference input signal to have

very near to 50% duty cycle; otherwise, the resulting spurious

content may prevent the system clock PLL from locking.

The system clock PLL features a simple lock detector that

compares the time difference between the reference and

feedback clock edges. The user can check the status of the lock

detector via the SYSCLK locked bit in the status readback

registers (Address 0x3000 to Address 0x300A) of the register

map, where Logic 1 indicates locked and Logic 0 unlocked. The

most common reason the system clock PLL fails to lock is due

to the user employing the 2× frequency multiplier with a

reference input clock that deviates from the 50% duty cycle.

PRESCALE DIVIDER

SYSTEM CLOCK STABILITY TIMER

The system clock PLL includes an input prescale divider

programmable for divide ratios of 1 (default), 2, 4, or 8. The

purpose of the divider is to provide flexible frequency planning

for mitigating potential spurs in the output clock signals of the

AD9544. The user selects the divide ratio via the 2-bit SYSCLK

input divider ratio bit field in Register 0x0201. The corresponding

divide value is 2^J, where J is the decimal value of the 2-bit number

in the SYSCLK input divider ratio bit field.

Because time processing blocks within the AD9544 depend on

the system clock generating a stable frequency, the system clock

PLL provides an indication of its status. The status of the system

clock PLL is available to the user as well as directly to certain

internal time keeping blocks.

At initial power-up, the system clock status is unknown and

reported as being unstable. However, after the user programs

the system clock registers and the system clock PLL VCO

calibrates, the system clock PLL locks shortly thereafter.

For example, given that the SYSCLK input divider ratio bit field is

10 (binary), J = 2 (decimal), yielding a divide ratio of 2^J= 2²= 4.

SYSTEM CLOCK INPUT TERMINATION

RECOMMENDATIONS

FEEDBACK DIVIDER

The output of the system clock PLL constitutes the system clock

frequency, f_S. The system clock frequency depends on the value

of the feedback divider. The feedback divide ratio has a range of

4 to 255, which the user programs via the 8-bit feedback divider

ratio register (the register value is the divide ratio). For example,

a programmed value of 100 (0x64 hexadecimal) yields a divide

ratio of 100.

To connect a crystal resonator to the system clock PLL XOA

and XOB inputs, refer to Figure 23. Be sure to program the

enable maintaining amplifier bit = 1 to select the crystal path.

The 15 pF shunt capacitors shown relate to the C_LOADand C_STRAY

associated with the crystal as follows:

C_SHUNT= 2 × (C_LOAD− C_STRAY

)

For C_LOAD= 10 pF and C_STRAY= 2 pF to 5 pF, the value of C_SHUNT

is approximately 15 pF.

SYSTEM CLOCK PLL OUTPUT FREQUENCY

Calculate the system clock frequency as follows:

To connect a TCXO or OCXO with a 3.3 V output, refer to

Figure 24. Be sure to program the enable maintaining amplifier

bit = 0 to select the direct path.

K

f_S= f_SYSIN

×

J

where:

f_SYSINis the input frequency.

K is the feedback divide ratio.

J is the input divide ratio. J = ½ when using the 2× frequency

multiplier.

The user must choose f_SYSIN, K, and J such that f_Ssatisfies the

VCO range of 2250 MHz to 2415 MHz.

Rev. 0 | Page 31 of 62

AD9544

Data Sheet

DIGITAL PLL (DPLL)

OVERVIEW

DPLL PHASE/FREQUENCY LOCK DETECTORS

Note that throughout this section, unless otherwise specified,

any referenced bits, registers, or bit fields reside in the DPLL

Channel 0 and DPLL Channel 1 sections (Address 0x1000 to

Address 0x102A, and Address 0x1400 to Address 0x142A) of

the register map.

See the Lock Detectors section for details concerning the phase

and frequency detectors of the DPLL.

DPLL LOOP CONTROLLER

The DPLL has several operating modes (including freerun,

holdover, and active). To ensure seamless transition between

modes, the DPLL has a loop controller. The loop controller sets

the appropriate DPLL operating mode based on the prevailing

requirements of automatic reference switching or manual

control settings.

The DPLL is an all-digital implementation of a phase-locked

loop (PLL). Figure 40 shows the fundamental building blocks of

an APLL and a DPLL. An APLL typically relies on a VCO as the

frequency element for generating an output signal, where the

output frequency depends on an applied dc voltage. A DPLL, on

the other hand, uses a numerically controlled oscillator (NCO),

which relies on a digital frequency tuning word (FTW) to

produce the output frequency. A VCO inherently produces a

timing signal because it is, by definition, an oscillator, whereas

the AD9544 NCO requires an external timing source, the system

clock. The fundamental difference between an APLL and a

DPLL is that the VCO in an APLL can tune to any frequency

within its operating bandwidth, whereas the NCO in a DPLL

can only tune to discrete frequencies (by virtue of the FTW).

ANALOG

Switchover

Switchover occurs when the loop controller switches directly

from one input reference to another. The AD9544 handles a

reference switchover by briefly entering holdover mode, loading

the new DPLL parameters, and then immediately recovering.

Holdover

Typically, the holdover state is in effect when all of the input

references are invalid. However, the user can force the holdover

mode even when one or more references are valid by setting the

DPLLx force holdover bit (where x = 0 or 1) in the Operational

Control Channel 0 and Operational Control Channel 1 sections

of the register map to Logic 1. In holdover mode, the output

frequency remains fixed (to the extent of the stability of the

system clock). The accuracy of the AD9544 in holdover mode is

dependent on the device programming and availability of the

tuning word history.

PHASE

FIXED LOOP

ERROR BANDWIDTH VOLTAGE

PHASE

DETECTOR

LOOP

FILTER

VCO

DIVIDER

APLL

Recovery from Holdover

When in holdover and an enabled translation profile becomes

available, the device exits holdover operation. The loop controller

restores the DPLL to closed-loop operation, locks to the selected

reference, and sequences the recovery of all the loop parameters

based on the profile settings for the active reference.

NUMERIC

FREQUENCY

PROGRAMMABLE

LOOP BANDWIDTH

TUNING WORD

NUMERIC

COEFFICIENTS

NUMERIC

PHASE

ERROR

SYSTEM

CLOCK

NCO

If the DPLLx force holdover bit (where x = 0 or 1) in the

Operational Control Channel 0 and Operational Control

Channel 1 sections of the register map is set to Logic 1, the

device does not automatically exit holdover when a valid

translation profile is available. However, automatic recovery can

occur after clearing the DPLL force holdover bit.

DIGITAL

PHASE

DETECTOR

DIGITAL

LOOP

FILTER

DIVIDER

DPLL

Figure 40. APLL vs. DPLL

The DPLLs in the AD9544 have a digital TDC-based phase

detector and a digital loop filter with programmable bandwidth.

The digital loop filter output yields a digital FTW (instead of a

dc voltage, as in the case of an analog PLL) that produces a

corresponding NCO output frequency.

Rev. 0 | Page 32 of 62

Data Sheet

AD9544

APPLICATIONS INFORMATION

OPTICAL NETWORKING LINE CARD

clock. The other DPLL cleans jitter and provides clocking to the

transmitter path.

In this application (shown in Figure 41), the AD9544 is used in

a variety of ways.

Other tasks include frequency translation and jitter cleaning of

the reference clock from the timing card, as well as seamlessly

managing the reference switching from Timing Card 1 to

Timing Card 2.

In a loop timed (WAN) mode, one of the AD9544 DPLLs locks

to the CDR and is used to remove jitter on the receiver path,

sending that clock to the central timing card, as well as the

framer. In some applications, the AD9544 can also perform a

variety of frequency translation tasks, such as multiplying or

dividing by an FEC ratio, and/or removing jitter from a gapped

Given the continually evolving nature of optical line card

protocols and functions, the functions listed in this section are

by no means exhaustive.

LINE CARD

LASER

DIODE

Tx

FRAMER/FEC

SERIALIZER

LDD

FIBER

DISTRIBUTION

PLL0

OUT0AP,

REFERENCE

OUTPUTS

OUT0AN,

OUT0BP,

OUT0BN,

OUT0CP,

OUT0CN

INPUTS

DPLL0

APLL0

FROM TIMING

CARD 1

DPLL NCO

PLL VCO

÷2

÷Q

REFA,

REFAA,

REFB,

FROM TIMING

CARD 2

÷R

TDC

INTERNAL ZERO DELAY

REFBB

DISTRIBUTION

OUTPUTS

PLL1

DPLL1

DPLL NCO

APLL1

OUT1AP,

OUT1AN,

OUT1BP,

OUT1BN

REFERENCE

MONITORS

÷Q

PLL VCO

OPTICAL

MODULE

INTERNAL ZERO DELAY

REFERENCE

SWITCHING

CONTROL

SYSTEM

CLOCK PLL

SYSTEM

CLOCK

XOA,

XOB

AD9544

DIGITAL

CROSS

POINT

MUX

SYSTEM CLOCK

COMPENSATION

2

STATUS AND

CONTROL PINS

SERIAL PORT (SPI/I C)

AND EEPROM

CONTROLLER

TEMPERATURE

SENSOR

M0 TO M6

SERIAL PORT

EEPROM

(OPTIONAL)

POST

AMP

PHOTO

DIODE

Rx

FIBER

FRAMER/FEC

DESERIALIZER CDR

TIA

Figure 41. Optical Line Card Example

Rev. 0 | Page 33 of 62

AD9544

Data Sheet

backhaul). The PLL0 of the AD9544 provides one device clock

and up to four device system reference clocks that can be used

to clock wireless transceivers, such as the AD9371.

SMALL CELL BASE STATION

In this application (shown in Figure 42), the AD9544 provides

all of the synchronization to the baseband unit of a small cell

base station. The built in JESD204B support enables a particu-

larly compact and efficient design.

The PLL1 of the AD9544 clocks the backhaul interface and,

optionally, the CPU interface.

The EEPROM support of the AD9544 allows the AD9544 to

load its configuration automatically at power-up.

The AD9544 can lock to any of the following: GPS, SyncE, or

loop timed (if using SONET/SDH or passive optical network

30.72MHz

61.44MHz

122.88MHz

SYSREF TO

JESD204B SUPPORT

RADIO 1

SYSREF TO

RADIO 2

SYSREF TO

BASEBAND

DISTRIBUTION

RADIO

PLL0

OUT0AP,

OUT0AN,

OUT0BP,

OUT0BN,

OUT0CP,

OUT0CN

REFERENCE

INPUTS

OUTPUTS

1:4

FANOUT

(2 CARDS)

DPLL0

APLL0

30.72MHz

61.44MHz

122.88MHz

245.76MHz

307.2MHz

DPLL NCO

PLL VCO

÷2

÷Q

REFA,

REFAA,

REFB,

INPUT

BASEBAND

PROCESSOR

÷R

TDC

INTERNAL ZERO DELAY

GPS, LOOP TIMED

FROM NETWORK

SyncE

REFBB

EXTERNAL

NETWORK

DISTRIBUTION

OUTPUTS

PLL1

DPLL1

DPLL NCO

APLL1

OUT1AP,

OUT1AN,

OUT1BP,

OUT1BN

REFERENCE

MONITORS

NETWORK

CONNECTION

ETHERNET

10MHz

25MHz

÷Q

SyncE

PLL VCO

PASSIVE OPTICAL NETWORK

SONET/SDH

125MHz

156.25MHz

312.5MHz

INTERNAL ZERO DELAY

REFERENCE

SWITCHING

CONTROL

SYSTEM

CLOCK PLL

SYSTEM

CLOCK

XOA,

XOB

AD9544

DIGITAL

CROSS

POINT

MUX

SYSTEM CLOCK

COMPENSATION

2

STATUS AND

CONTROL PINS

SERIAL PORT (SPI/I C)

AND EEPROM

CONTROLLER

TEMPERATURE

SENSOR

M0 TO M6

SERIAL PORT

EEPROM

(OPTIONAL)

Figure 42. Small Cell Application

Rev. 0 | Page 34 of 62

Data Sheet

AD9544

INITIALIZATION SEQUENCE

Figure 43, Figure 44, and Figure 45 describe the sequence for powering on and programming the AD9544.

START

APPLY VDD

(ALL DOMAINS)

WAIT FOR POWER

SUPPLIES TO

STABILIZE

VDD

NO

SETTLED?

YES

POR: WAIT 60ms

REFERENCE INPUT(S)

CAN BE APPLIED

ANY TIME HEREAFTER

CHIP LEVEL

RESET LOOP

ISSUE A

RST_COUNT =

RST_COUNT + 1

CHIP LEVEL RESET

RST_COUNT = 0

(PIN OR SOFT RESET)

SOFTWARE

WRITE REGISTER

CONTENT FROM

SETUP FILE

GENERATED

AD9544

REGISTER DUMP

WRITE:

REGISTER 0x000F = 0x01

SUBPROCESS:

SYSTEM CLOCK

INITIALIZATION

i = 0

RAISE FLAG FOR

DEBUGGING

NO

WRITE:

YES

REGISTER 0x000F = 0x01

READ:

RST_COUNT > 0

NO

APLLi

ENABLED

REGISTER 0x3000 TO REGISTER 0x3019

REGISTER 0x3100 TO REGISTER 0x310E

REGISTER 0x3200 TO REGISTER 0x320E

YES

SUBPROCESS:

ANALOG PLLi

INITIALIZATION

i = i +1

NO

i > 1

YES

END

Figure 43. Programming Sequence Loop

Rev. 0 | Page 35 of 62

AD9544

Data Sheet

START

APLL CAL REG. LOCK REG. AUTOSYNC REG.

SYNC REG.

0x2101

0x2201

APLL RECALIBRATION

LOOP

0

1

0x2100

0x2200

0x3100

0x3200

0x10DB

0x14DB

CAL_COUNT = 0

VCO

CALIBRATION

OPERATION

WRITE:

CAL REG BIT 1 = 0

NO

WRITE:

REGISTER 0x000F BIT 0 = 1

END

(TO RST_COUNT

CHECK)

YES

CAL_COUNT > 1

WRITE:

CAL REG BIT 1 = 1

WRITE:

REGISTER 0x000F BIT 0 = 1

CAL_COUNT =

CAL_COUNT + 1

APLL LOCK

DETECT POLLING

LOOP

START TIMEOUT CLOCK:

TIME = 0

NO

TIMEOUT CLOCK:

TIME > 50ms

YES

LOCK REG BIT 3 = 1

YES

NO

AUTOSYNC

REGISTERS

BITS[1:0] = 0

YES

MANUAL

DISTRIBUTION

SYNCHRONIZATION

OPERATION

WRITE:

SYNC REG BIT 3 = 1

WRITE:

REGISTER 0x000F BIT 0 = 1

WRITE:

SYNC REG BIT 3 = 0

WRITE:

REGISTER 0x000F BIT 0 = 1

END

Figure 44. System Clock Initialization Subprocess

Rev. 0 | Page 36 of 62

Data Sheet

AD9544

START

APLL CAL REG. LOCK REG. AUTOSYNC REG.

SYNC REG.

0x2101

0x2201

APLL RECALIBRATION

LOOP

0

1

0x2100

0x2200

0x3100

0x3200

0x10DB

0x14DB

CAL_COUNT = 0

VCO

CALIBRATION

OPERATION

WRITE:

CAL REG BIT 1 = 0

NO

WRITE:

REGISTER 0x000F BIT 0 = 1

END

(TO RST_COUNT

CHECK)

YES

CAL_COUNT > 1

WRITE:

CAL REG BIT 1 = 1

WRITE:

REGISTER 0x000F BIT 0 = 1

CAL_COUNT =

CAL_COUNT + 1

APLL LOCK

DETECT POLLING

LOOP

START TIMEOUT CLOCK:

TIME = 0

NO

TIMEOUT CLOCK:

TIME > 50ms

YES

LOCK REG BIT 3 = 1

YES

NO

AUTOSYNC

REGISTERS

BITS[1:0] = 0"

YES

MANUAL

DISTRIBUTION

SYNCHRONIZATION

OPERATION

WRITE:

SYNC REG BIT 3 = 1

WRITE:

REGISTER 0x000F BIT 0 = 1

WRITE:

SYNC REG BIT 3 = 0

WRITE:

REGISTER 0x000F BIT 0 = 1

END

Figure 45. Analog PLL Initialization Subprocess

Rev. 0 | Page 37 of 62

AD9544

Data Sheet

STATUS AND CONTROL PINS

The AD9544 features seven independently configurable digital

CMOS status/control pins (M0 to M6). Configuring an Mx pin

as a status pin causes that pin to be an output. Conversely,

configuring an Mx pin as a control pin causes that pin to be an

input. Register 0x0102 to Register 0x0108 control both the

nature of the pin (either status or control via Bit D7), as well as

the selection of the status source or control destination

associated with the pin via Bits[D6:D0]. During power-up or

reset, the Mx pins temporarily become inputs and only allow the

device to autoconfigure. Figure 46 is a block diagram of the Mx pin

functionality.

switches to the newly programmed pin function, at which time

normal behavior resumes. Note that, when switching from one

input function to another input function on the same pin, the

logic state driven at the input to the pin can change freely

during the interval between writing the new function to the

corresponding register and asserting the input/output update.

When switching the operation of an Mx pin from an input to an

output function, the recommendation is that the external drive

source become high impedance during the interval between

writing the new function and asserting the input/output update.

When switching the operation of an Mx pin from an output to

an input, the recommendation is as follows. First, program the

Mx pin input function to no operation (NOOP) and assert the

input/output update. This configuration avoids input/output

contention on the Mx pin or other undesired behavior because,

prior to the assertion of the input/output update, the device

continues to drive the Mx pin. Following the assertion of the

input/output update, the device releases the Mx pin but ignores

the logic level on the pin due to the programmed NOOP function.

Note that the recommendation is to avoid using a high impedance

source on an Mx pin configured as an input because this may

cause excessive internal current consumption. Second, drive the

Mx pin with Logic 0 or Logic 1 via the desired external source

and program the associated Mx pin register from NOOP to the

desired function.

The Mx pin control logic uses special register write detection

logic to prevent these pins from behaving unpredictably when the

Mx pin function changes, especially when changing mode from

input to output or vice versa.

When an Mx pin functions as an output, it continues operating

according to the prior function, even after the user programs

the corresponding registers. However, assertion of an input/output

update causes the corresponding pins to switch to the new

function according to the newly programmed register contents.

Note that changing from one output function to another output

function on an Mx pin does not require special timing to avoid

input/output contention on the pin.

When an Mx pin functions as an input, programming a particular

Mx pin function register causes all the Mx pin control functions

to latch their values. Assertion of an input/output update

Mx PIN FUNCTION LOGIC

DEVICE

RESET

POWER UP

AUTOCONFIGURATION

I/O

CONTROL

FUNCTION

SELECT

CONTROL

DESTINATIONS

Mx PIN

CONTROL

REGISTERS

I/O UPDATE

STATUS

SOURCE

SELECT

STATUS

SOURCES

Figure 46. Mx Pin Logic

Rev. 0 | Page 38 of 62

Data Sheet

AD9544

MULTIFUNCTION PINS AT RESET/POWER-UP

STATUS FUNCTIONALITY

At power-up or in response to a reset operation, the Mx pins

enter a special operating mode. For a brief interval following a

power-up or reset operation, the Mx pins function only as

inputs (the internal drivers enter a high impedance state during

a power-up/reset operation). During this brief interval, the

device latches the logic levels at the Mx inputs and uses this

information to autoconfigure the device accordingly. The Mx

pins remain high-Z until either an EEPROM operation occurs,

in which case M1 or M2 become an I²C master, or the user (or

EEPROM) programs them to be outputs.

Configuring an Mx pin as a status pin gives the user access to

specific internal device status/IRQ functions in the form of a

hardware pin that produces a logic signal. Each Mx pin has a

corresponding Mx function register. To assign an Mx pin as a

status pin, write a Logic 1 to the Mx output enable bit in the

corresponding Mx pin function register.

To assign a specific status/IRQ function to an Mx pin configured

as a status pin, program the appropriate 7-bit code (see Table 30)

to Bits[D6:D0] of the corresponding Mx function register.

See the Interrupt Request (IRQ) section for details regarding

IRQ functionality.

If the user does not connect external pull-up/pull-down resistors

to the Mx pins, the M3 and M4 pins have internal pull-down

resistors to ensure a predictable start-up configuration. In the

absence of external resistors, the internal pull-down resistors

ensure that the device starts up with the serial port in SPI mode

and without automatically loading data from an external EEPROM

(see Table 26). Although the M0, M1, M2, M5, and M6 pins are

high impedance at startup, connect external 100 kΩ pull-down

or pull-up resistors to these pins to ensure robust operation.

When configured as a status pin, the output mode of an Mx pin

depends on a 2-bit mode code per Table 28. The 2-bit codes reside

in Register 0x0100 through Register 0x0101, where the 2-bit

codes constitute the Mx receiver/driver bit fields. Note that the

Mx receiver/driver bit fields perform a different function when

the Mx pin is a control pin (see the Control Functionality

section).

Table 28. Mx Receiver/Driver Bit Field Codes for Mx Status Pins

The Mx pin start-up conditions are shown in Table 26. M0, M1,

and M2 are excluded from Table 26 because these pins have no

explicit function during a power-up or reset operation.

Code Mode

Description

00

CMOS,

Output is Logic 0 when deasserted and

active high Logic 1 when asserted (default operating

mode).

Table 26. Mx Pin Function at Startup or Reset

01

10

11

CMOS,

active low

Output is Logic 1 when deasserted and

Logic 0 when asserted.

Mx

Startup/Reset

Function

Logic 1

Logic 0

PMOS,

Output is high impedance when deasserted

M3

EEPROM load

function

Load from

EEPROM

Do not load from

EEPROM (default)

open drain and active high when asserted.

NMOS,

Output is high impedance when deasserted

M4

Serial port

function

I²C mode

SPI mode

(default)

open drain and active low when asserted.

M5

M6

I²C address offset See Table 27

See Table 27

The PMOS open-drain mode requires an external pull-down

resistor. The NMOS open-drain mode requires an external pull-up

resistor. Note that the open-drain modes enable the implementa-

tion of wire-OR’e d functionality of multiple Mx status pins

(including Mx status pins across multiple AD9544 devices or other

compatible devices—for example, to implement an IRQ bus).

When the start-up conditions select the serial port to be I²C

mode (that is, M4 is Logic 1 at startup), the M5 and M6 pins

determine the I²C port device address offset per Table 27. Note

that the logic levels in Table 27 only apply during a power-up or

reset operation.

The drive strength of an Mx status pin is programmable via the

corresponding Mx configuration bits (Bits[D6:D0] of the pin

drive strength register). Logic 0 (default) selects normal drive

strength (~6 mA) and Logic 1 selects weak drive strength (~3 mA).

Table 27. I²C Device Address Offset

M6

X¹

0

M5

X¹

0

M4

0

Address Offset

Not applicable

1001000 (0x48)

1001001 (0x49)

1001010 (0x4A)

1001011 (0x4B)

CONTROL FUNCTIONALITY

1

Configuring an Mx pin as a control pin gives the user control of

the specific internal device functions via an external hardware

logic signal. Each Mx pin has a corresponding Mx function register.

To assign an Mx pin as a control pin, write a Logic 0 to the

Mx output enable bit in the corresponding Mx function register.

0

1

0

1

¹X means don’t care.

To assign an Mx control pin to a specific function, program the

appropriate 7-bit code (see Table 30) to Bits[D6:D0] of the

corresponding Mx function register. See the Interrupt Request

(IRQ) section for details regarding IRQ functionality.

Rev. 0 | Page 39 of 62

AD9544

Data Sheet

When configured as an Mx control pin, the logical level applied

to the Mx pin translates to the selected device function. It is also

possible to assign multiple Mx control pins to the same control

function with the multiple pins implementing a Boolean expres-

sion. The Boolean operation associated with an Mx control pin

depends on a 2-bit code per Table 29. The 2-bit codes reside in

Register 0x100 through Register 0x101, where the 2-bit codes

constitute the Mx receiver/driver bit fields. Note that the Mx

receiver/driver bit fields perform a different function when the

Mx pin is a status pin (see the Status Functionality section).

performed using that result and the remaining AND and NOT

AND operations.

Consider a case where M0, M2, M3, and M6 are all assigned to

the input/output update control function; that is, Bits[D6:D0] in

Register 0x0102 through Register 0x0108 = 0x01 (see Table 30). In

addition, M0 is assigned for AND operation, M2 for NOT OR

operation, M3 for NOT AND operation, and M6 for OR operation

(that is, the 2-bit codes in Register 0x0100 and Register 0x0101

according to Table 29). With these settings, the input/output

update function behaves according the following Boolean equation:

Table 29. Mx Receiver/Driver Bit Field Codes for Mx Control

Pins

Input/output update = (!M2 || M6) && M0 && !M3

where:

Code Boolean Description

! is logical NOT. Therefore, an input/output update occurs when

00

AND

Logical AND the associated Mx control pin

with the other Mx control pins assigned to

the same control function.

M0 is Logic 1 and M3 is Logic 0, and either M2 is Logic 0 or M6

is Logic 1.

&& is logical AND.

|| is logical OR.

01

NOT AND Invert the logical state of the associated Mx

control pin and AND it with the other Mx

control pins assigned to the same control

function.

When an Mx control pin acts on a control function individually

(rather than as part of a group, per the previous example), the

Boolean functionality of the codes in Table 29 reduces to two

possibilities. Namely, Code 00 and Code 10 specify a Boolean

true (the Mx pin logic state applies to the corresponding control

function directly), whereas Code 01 and Code 11 specify a

Boolean false (the Mx pin logic state applies to the corresponding

control function with a logical inversion).

10

11

OR

Logical OR the associated Mx control pin with

the other Mx control pins assigned to the

same control function.

NOT OR

Invert the logical state of the associated Mx

control pin and OR it with the other Mx control

pins assigned to the same control function.

The Boolean functionality of aggregated Mx control pins

follows a hierarchy whereby logical OR operations occur before

logical AND operations. The OR and NOT OR operations are

collectively grouped into a single result. A logical AND is then

Regarding the source and destination proxy columns in Table 30,

the &&, || and ! symbols denote the Boolean AND, OR, and

NOT operations, respectively.

Table 30. Mx Pin Status and Control Codes

Bits[D6:D0]

(Hex)

0x00

0x01

0x02

0x03

0x04

Control Function

No operation (NOOP)

IO_UPDATE

Destination Proxy

Not applicable

Status Function

Source Proxy (or Description)

Not applicable

Logic 0, static

Register 0x000F, Bit D0

Register 0x2000, Bit D0

Register 0x2005, Bit D7

Register 0x2000, Bit D3

Logic 1, static

Not applicable

Device power down

Clear watchdog timer

Sync all

Digital core clock

Watchdog timer timeout

Not applicable

SYSCLK calibration in

progress

Register 0x3001, Bit D2

0x05

0x06

0x07

Unassigned

Not applicable

SYSCLK lock detect

SYSCLK stable

Register 0x3001, Bit D0

Register 0x3001, Bit D1

Channel 0 and Channel 1

PLLs locked

Register 0x3001, Bit D4 && Bit D5

0x08

0x09

0x0A

0x0B

0x0C

0x0D

Unassigned

Not applicable

PLL0 locked

Register 0x3001, Bit D4

Register 0x3001, Bit D5

Register 0x3000, Bit D0

Register 0x3000, Bit D1

Register 0x3000, Bit D2 || Bit D3

Register 0x3002, Bit D0

PLL1 locked

EEPROM save in progress

EEPROM load in progress

EEPROM fault detected

Temperature sensor limit

alarm

0x0E

0x0F

0x10

Unassigned

Not applicable

Unassigned

Any IRQ event

Not applicable

Unassigned

Not applicable

Clear all IRQ events

Register 0x2005, Bit D0

The logical OR of all triggered

IRQ events

Rev. 0 | Page 40 of 62

Data Sheet

AD9544

Bits[D6:D0]

(Hex)

Control Function

Destination Proxy

Status Function

Source Proxy (or Description)

0x11

Clear common IRQ

events

Register 0x2005, Bit D1

Common IRQ event

The logical OR of all triggered

common IRQ events

0x12

0x13

Clear PLL0 IRQ events

Register 0x2005, Bit D2

Register 0x2005, Bit D3

PLL0 IRQ event

PLL1 IRQ event

The logical OR of all triggered

PLL0 IRQ events

Clear PLL1 IRQ events

The logical OR of all triggered

PLL1 IRQ events

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

Unassigned

Not applicable

REFA demodulator clock

Unassigned

Not applicable

Register 0x300D, Bit D3

REFAA demodulator clock

Unassigned

REFB demodulator clock

Unassigned

REFBB demodulator clock

Unassigned

REFA reference (R) divider

resync

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

Unassigned

Fault REFA

Not applicable

REFAA R divider resync

REFB R divider resync

REFBB R divider resync

REFA faulted

Register 0x300D, Bit D7

Register 0x300E, Bit D3

Register 0x300E, Bit D7

Register 0x3005, Bit D3

Register 0x3006, Bit D3

Register 0x3007, Bit D3

Register 0x3008, Bit D3

Register 0x3005, Bit D4

Register 0x3006, Bit D4

Register 0x3007, Bit D4

Register 0x3008, Bit D4

Not applicable

Register 0x2003, Bit D0

Register 0x2003, Bit D1

Register 0x2003, Bit D2

Register 0x2003, Bit D3

Not applicable

Fault REFAA

Fault REFB

REFAA faulted

REFB faulted

Fault REFBB

Unassigned

REFBB faulted

REFA valid

Not applicable

REFAA valid

Not applicable

REFB valid

Not applicable

REFBB valid

Timeout REFA

validation

Register 0x2002, Bit D0

(validate REFA if faulted;

otherwise, no action)

REFA active

This function represents a logical

combination of several registers and

bits

0x29

Timeout REFAA

validation

Register 0x2002, Bit D1

(validate REFAA if

faulted; otherwise, no

action)

REFAA active

This function represents a logical

combination of several registers and

bits

0x2A

0x2B

Timeout REFB

validation

Register 0x2002, Bit D2

(validate REFB if faulted;

otherwise, no action)

REFB active

This function represents a logical

combination of several registers and

bits

Timeout REFBB

validation

Register 0x2002, Bit D3

(validate REFBB if

faulted; otherwise, no

action)

REFBB active

This function represents a logical

combination of several registers and

bits

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

Unassigned

Not applicable

Unassigned

Not applicable

Feedback 0 active

Feedback 1 active

DPLL0 phase locked

DPLL0 frequency locked

APLL0 locked

Not applicable

Register 0x3100, Bit D1

Register 0x3100, Bit D2

Register 0x3100, Bit D3

APLL0 calibration in progress Register 0x3100, Bit D4

DPLL0 active

Register 0x3009, Bit D5 || Bit D4 || Bit

D3 || Bit D2 || Bit D1 || Bit D0

Register 0x3101, Bit D0

Register 0x3101, Bit D1

Register 0x3101, Bit D2

0x35

0x36

0x37

Unassigned

Not applicable

DPLL0 freerun

DPLL0 holdover

DPLL0 switching

Rev. 0 | Page 41 of 62

AD9544

Data Sheet

Bits[D6:D0]

(Hex)

Control Function

Destination Proxy

Status Function

Source Proxy (or Description)

0x38

Unassigned

Not applicable

DPLL0 tuning word history

status

Register 0x3102, Bit D0

0x39

Unassigned

Not applicable

DPLL0 tuning word history

updated

Not applicable

0x3A

0x3B

0x3C

Unassigned

Not applicable

DPLL0 frequency clamped

DPLL0 phase slew limited

Register 0x3102, Bit D1

Register 0x3102, Bit D2

Not applicable

PLL0 distribution

synchronized

0x3D

0x3E

0x3F

0x40

Unassigned

Not applicable

Unassigned

Not applicable

Unassigned

Not applicable

DPLL0 phase step detected

DPLL0 fast acquisition active

Not applicable

Unassigned

Not applicable

Register 0x3102, Bit D4

Register 0x3102, Bit D5

PLL0 power-down

Register 0x2100, Bit D0

DPLL0 fast acquisition

complete

0x41

0x42

0x43

0x44

0x45

0x46

0x47

DPLL0 user freerun

DPLL0 user holdover

Register 0x2105, Bit D0

Register 0x2105, Bit D1

Register 0x2107, Bit D1

Register 0x2101, Bit D3

Register 0x2105, Bit D4

Register 0x2105, Bit D5

Register 0x2105, Bit D6

DPLL0 feedback divider

resync

Not applicable

PLL0 distribution phase slew

enable

Register 0x310D, logical OR of

Bits[5:0]

DPLL0 clear tuning

word history

PLL0 distribution

configuration error

Register 0x310E, logical OR of Bits[5:0]

Synchronize PLL0

distribution dividers

Unassigned

Not applicable

DPLL0 translation

profile select, Bit 0

Not applicable

DPLL0 translation

profile select, Bit 1

Not applicable

DPLL0 translation

profile select, Bit 2

Not applicable

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

Unassigned

Mute OUT0A

Mute OUT0AA

Not applicable

Unassigned

Not applicable

Unassigned

Not applicable

Unassigned

Not applicable

Unassigned

Not applicable

Unassigned

Not applicable

Unassigned

Not applicable

Unassigned

Not applicable

Unassigned

Not applicable

Register 0x2102, Bit D2

Register 0x2102, Bit D3

Register 0x2102, Bit D5

DPLL1 phase locked

DPLL1 frequency locked

APLL1 locked

Register 0x3200, Bit D1

Register 0x3200, Bit D2

Register 0x3200, Bit D3

Reset OUT0A/

OUT0AA driver

0x53

0x54

Mute OUT0B

Register 0x2103, Bit D2

Register 0x2103, Bit D3

APLL1 calibration in progress Register 0x3200, Bit D4

Mute OUT0BB

DPLL1 active

Register 0x300A, Bit D5 || Bit D4 || Bit

D3 || Bit D2 || Bit D1 || Bit D0

0x55

Reset OUT0B/

OUT0BB driver

Register 0x2103, Bit D5

DPLL1 freerun

Register 0x3201, Bit D0

0x56

0x57

0x58

Mute OUT0C

Register 0x2104, Bit D2

Register 0x2104, Bit D3

Register 0x2104, Bit D5

DPLL1 holdover

DPLL1 switching

Register 0x3201, Bit D1

Register 0x3201, Bit D2

Register 0x3202, Bit D0

Mute OUT0CC

Reset OUT0C/

OUT0CC driver

DPLL1 tuning word history

status

0x59

0x5A

0x5B

0x5C

Mute OUT0xP/

OUT0xN drivers

Register 0x2101, Bit D1

Register 0x2101, Bit D2

Register 0x2101, Bit D0

Not applicable

DPLL1 tuning word history

updated

Not applicable

Reset OUT0xP/

OUT0xN drivers

DPLL1 frequency clamped

Register 0x3202, Bit D1

Register 0x3202, Bit D2

Not applicable

Channel 0 N-shot

request

DPLL1 phase slew limited

Unassigned

PLL1 distribution

synchronized

Rev. 0 | Page 42 of 62

Data Sheet

AD9544

Bits[D6:D0]

(Hex)

0x5D

0x5E

0x5F

0x60

Control Function

Destination Proxy

Not applicable

Status Function

Source Proxy (or Description)

Unassigned

Not applicable

Unassigned

Not applicable

DPLL1 phase step detected

DPLL1 fast acquisition active

Not applicable

Unassigned

Not applicable

Register 0x3202, Bit D4

Register 0x3202, Bit D5

PLL1 power-down

Register 0x2200, Bit D0

DPLL1 fast acquisition

complete

0x61

0x62

0x63

0x64

0x65

0x66

0x67

DPLL1 force freerun

DPLL1 force holdover

Register 0x2205, Bit D0

Register 0x2205, Bit D1

Register 0x2207, Bit D1

Register 0x2201, Bit D3

Register 0x2205, Bit D4

Register 0x2205, Bit D5

Register 0x2205, Bit D6

DPLL1 feedback divider

resync

Not applicable

PLL1 distribution phase slew

enable OR’ed

Register 0x320D, Logical OR of

Bits[3:0]

DPLL1 clear tuning

word history

PLL1 distribution phase

control error OR’ed

Register 0x320E, Logical OR if Bits[3:0]

Synchronize PLL1

distribution dividers

Unassigned

Not applicable

DPLL1 translation

profile select, Bit 0

Not applicable

DPLL1 translation

profile select, Bit 1

Not applicable

DPLL1 translation

profile select, Bit 2

Not applicable

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

Unassigned

Mute OUT1A

Mute OUT1AA

Not applicable

Unassigned

Not applicable

Register 0x2202, Bit D2

Register 0x2202, Bit D3

Register 0x2202, Bit D5

Reset OUT1A/OUT1AA

driver

0x73

0x74

0x75

Mute OUT1B

Register 0x2203, Bit D2

Register 0x2203, Bit D3

Register 0x2203, Bit D5

Not applicable

Mute OUT1BB

Reset OUT1B/OUT1BB

driver

0x76

0x77

0x78

Mute OUT1xP/OUT1xN

drivers

Register 0x2201, Bit D1

Unassigned

Not applicable

Reset OUT1xP/OUT1xN Register 0x2201, Bit D2

drivers

Unassigned

Channel 1 N-shot

request

Register 0x2201, Bit D0

Timestamp 0 event detected

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

Unassigned

Not applicable

Timestamp 1 event detected

Skew measurement detected Not applicable

Unassigned

Not applicable

Rev. 0 | Page 43 of 62

AD9544

Data Sheet

INTERRUPT REQUEST (IRQ)

The AD9544 monitors certain internal device events potentially

allowing them to trigger an IRQ event. Three groups of registers

(see Figure 47) control the IRQ functionality within the AD9544:

or any IRQ signal in Figure 47). Note that the default state of the

IRQ mask register bits is Logic 0; therefore, the device is not

capable of generating an IRQ event status result until the user

populates the IRQ mask with a Logic 1 to unmask the desired

specific IRQ events. Writing a Logic 1 to an IRQ mask bit may

result in immediate indication of an IRQ status event result if the

corresponding specific device event is already asserted (that is,

the device previously registered the corresponding device event).

•

IRQ monitor registers (Register 0x300B through

Register 0x3019)

•

IRQ mask registers (Register 0x010C through Register 0x011A)

IRQ clear registers (Register 0x2006 through Register 0x2014)

The IRQ logic can indicate an IRQ event status result for any

specific device event(s) via the logical OR of the status of all the

IRQ monitor bits. In addition, the IRQ logic offers IRQ event

status results for particular groups of specific IRQ events,

namely, the PLL0 IRQs, PLL1 IRQs, and common IRQs (see

Figure 47).

IRQ CLEAR

The IRQ clear registers (in the operational controls section of

the register map) comprise a bit for bit correspondence with

the IRQ monitor. Writing a Logic 1 to an IRQ clear bit forces

the corresponding IRQ monitor bit to Logic 0, thereby clearing

that specific IRQ event. Note that the IRQ clear registers are

autoclearing; therefore, after writing a Logic 1 to an IRQ clear bit,

the device automatically restores the IRQ clear bit to Logic 0.

The IRQ event status results remain asserted until the user

clears all of the bits in the IRQ monitor responsible for the IRQ

status result (that is, the entire group of status bits associated

with PLL0 IRQ, PLL1 IRQ, common IRQ, or any IRQ signal

shown in Figure 47).

The PLL0 IRQ group includes all device events associated with

DPLL0 and APLL0. The PLL1 IRQ group includes all device

events associated with DPLL1 and APLL1. The common IRQ

group includes events associated with the system clock, the

watchdog timer, and the EEPROM.

IRQ MONITOR

The IRQ monitor registers (in the general status section of the

register map) maintain a record of specific IRQ events. The

occurrence of a specific device event results in the setting and

latching of the corresponding bit in the IRQ monitor. The

output of the IRQ monitor provides the mechanism for

generating IRQ event status results (see the PLL0 IRQ, PLL1

IRQ, common IRQ, or any IRQ signal shown in Figure 47).

Although it is not recommended, in certain applications, it

may be desirable to clear an entire IRQ group all at one time.

Register 0x2005 provides four bits for clearing IRQ groups.

Bit D0 clears all IRQ monitor bits. Bit D1 clears the common

IRQ bits. Bit D2 clears the PLL0 IRQ bits. Bit D3 clears the

PLL1 IRQ bits.

Alternately, the user can program any of the multifunction pins

as an input for clearing an IRQ group, which allows clearing an

IRQ group with an external logic signal rather than by writing

to Register 0x2005 (see Figure 47).

IRQ MASK

The IRQ mask registers (in the Mx pin status and control section

of the register map) comprise a bit for bit correspondence with

the specific IRQ event bits within the IRQ monitor. Writing a

Logic 1 to a mask bit enables (unmasks) the corresponding

specific device event to the IRQ monitor. A Logic 0 (default)

disables (masks) the corresponding specific device event to the

IRQ monitor. Therefore, a specific IRQ event is the result of a

logical AND of a specific device event and its associated IRQ,

mask bit.

The recommendation for clearing IRQ status events is to first

service the specific IRQ event (as needed) and then clear the

specific IRQ for that particular IRQ event. Clearing IRQ groups

via Register 0x2005 or via an Mx pin requires great care.

Clearing an IRQ group all at one time may result in the

unintentional clearing of one or more asserted IRQ monitor

bits. Clearing asserted IRQ monitor bits eliminates the record of

the associated device events, subsequently erasing any history of

those events having occurred.

The presence of the IRQ mask allows the user to select certain

device events for generating an IRQ event, while ignoring

(masking) all other specific device events from contributing to

an IRQ event status result (PLL0 IRQ, PLL1 IRQ, common IRQ

Rev. 0 | Page 44 of 62

Data Sheet

AD9544

CLEAR ALL IRQS

CLEAR PLL0 IRQS

CLEAR PLL1 IRQS

CLEAR COMMON IRQS

IRQ CLEAR

GROUP/ALL

BITS

PLL0 IRQ

PLL1 IRQ

REGISTER 0x2005

GROUPED

IRQ EVENT

STATUS

COMMON IRQ

GROUPED

IRQ CLEAR

IRQ CLEAR BITS

REGISTER 0x2006 TO

REGISTER 0x2014

IRQ MONITOR BITS

REGISTER 0x300B TO

REGISTER 0x3019

ANY

IRQ

IRQ MASK BITS

REGISTER 0x010C TO

REGISTER 0x011A

1 = ENABLE

0 = MASK (DEFAULT)

GROUPED DEVICE EVENTS

Figure 47. IRQ System Diagram

Rev. 0 | Page 45 of 62

AD9544

Data Sheet

WATCHDOG TIMER

The watchdog timer is a general-purpose programmable timer

capable of triggering a specific IRQ event (see Figure 48). The

timer relies on the system clock, however; therefore, the system

clock must be present and locked for the watchdog timer to be

functional. The bit fields associated with the watchdog timer

reside in the Mx pin status and control function section of the

register map.

or by assigning it directly to an Mx status pin. In the case of an

Mx status pin, the timeout event of the watchdog timer is a

pulse spanning 96 system clock periods (approximately 40 ns).

There are two ways to reset the watchdog timer, thereby preventing

it from indicating a timeout event. The first method is by

writing a Logic 1 to the clear watchdog bit (an autoclearing bit)

in the operational controls section of the register map.

Alternatively, the user can program any of the multifunction

pins as a control pin to reset the watchdog timer, which allows

the user to reset the timer by means of a hardware pin rather

than using the serial port.

The user sets the period of the watchdog timer by programming

the watchdog timer (ms) bit field with a 16-bit timeout value. A

nonzero value sets the timeout period in units of milliseconds,

providing a range of 1 ms to 65.535 sec, whereas a zero value

(0x0000, the default value) disables the timer. The relative accuracy

of the timer is approximately 0.1% with an uncertainty of

0.5 ms. Note that whenever the user writes a 16-bit timeout

value to the watchdog timer, it automatically clears the timer,

ensuring a correct timeout period (per the new value) starting

from the moment of the bit field update.

There are two typical cases for employing the watchdog timer.

Both cases assume that the watchdog timer output appears at

the output of an appropriately configured Mx status pin (the

watchdog timer output for the following case descriptions). The

first case is for an external device (for example, an FPGA or

microcontroller) to monitor the watchdog timer output using it

as a signal to carry out periodic housekeeping functions. The

second case is to have the watchdog timer output connected to

the external device, such that the assertion of the watchdog

output resets the external device. In this way, under normal

operation, the external device repeatedly resets the watchdog

timer by either writing Logic 1 to the clear watchdog bit or by

asserting an Mx control pin configured for clearing the watchdog.

In this way, as long as the external device keeps resetting the

watchdog timer before it times out, the watchdog timer does

not generate an output signal. As such, the watchdog timer does

not reset the external device. However, if the external device

fails to reset the watchdog timer before its timeout period

expires, the watchdog timer eventually times out, resetting the

external device via the appropriately configured Mx status pin.

The watchdog timer (ms) bit field relates to the timeout period

as follows:

Watchdog Timer (ms) = Timeout Period × 10³

To determine the value of the watchdog timer (ms) bit field

necessary for a timeout period of 10 sec,

Watchdog Timer (ms) = Timeout Period × 103

= 10 × 103

= 10,000

= 0x2710 (hexadecimal)

If enabled, the timer runs continuously and generates a timeout

IRQ event when the timeout period expires. The user has access

to the watchdog timer status via its associated IRQ monitor bit

Mx PINS

Mx PIN FUNCTION LOGIC

CLEAR

WATCHDOG

VIA Mx PIN

WATCHDOG

OUTPUT VIA

Mx PIN

CLEAR

WATCHDOG

REGISTER 0x2005,

BIT D7

40ns

CLEAR

TO IRQ EVENT

SOURCE LOGIC

TIMER

1kHz

CLK

OUT

PRESET

TEXT = BIT(S) IN THE REGISTER MAP

16

WATCHDOG

TIMER

(MS)

REGISTER 0x010A TO REGISTER 0x010B

Figure 48. Watchdog Timer

Rev. 0 | Page 46 of 62

Data Sheet

AD9544

LOCK DETECTORS

DPLL LOCK DETECTORS

DPLL Phase Lock Detector

During any given PFD phase error sample, the lock detector

either adds water with the fill bucket or removes water with the

drain bucket (one or the other, but not both). The decision of

whether to add or remove water depends on the threshold level

specified by the user in the 24-bit unsigned Profile x phase lock

threshold bit field. The bit field value is the desired threshold in

picoseconds. Thus, the phase lock threshold extends from 0 ps

to 16.7 µs and represents the phase error at the output of the

PFD. Though the programming range supports 0 ps as a lower

limit, in practice, the minimum value must be greater than 50 ps.

Each DPLL channel (DPLL0 and DPLL1) contains an all digital

phase lock detector. The user controls the threshold sensitivity

and hysteresis of the phase detector via the source profiles.

The phase lock detector provides the user with two status bits in

the status readback PLLx section of the register map. The DPLLx

phase lock bit latches to Logic 1 when the DPLL changes state

from not phase locked to phase locked. The DPLLx phase unlock

bit latches to Logic 1 when the DPLL changes state from phase

locked to not phase locked. The DPLLx phase lock bits are

located in Register 0x3100 and 0x3200, respectively. Because

these bits can change dynamically, it is strongly recommended

that the user set an IRQ for these bits. When using the IRQ

function, it is possible for the IRQ status to indicate Logic 1 for

an IRQ function that was just enabled if that condition is true at

the time the IRQ is enabled. Therefore, the user must clear the

IRQ just enabled via the IRQ map DPLL0 clear (Register 0x200B

to Register 0x200F) section and the IRQ map DPLL1 clear

(Register 0x2010 to Register 0x2014) section of the register map to

obtain visibility of subsequent state transitions of the phase lock

detector.

The phase lock detector compares the absolute value of each

phase error sample at the output of the PFD to the programmed

phase threshold value. If the absolute value of the phase error

sample is less than or equal to the programmed phase threshold

value, the detector control logic adds one fill bucket into the

tub. Otherwise, it removes one drain bucket from the tub. Note

that it is the magnitude, relative to the phase threshold value,

that determines whether to fill or drain the bucket, and not the

polarity of the phase error sample.

An exception to the fill/drain process occurs when the phase

slew limiter is active. When the phase slew limiter is actively in

the limiting process, the lock detector blocks fill events, allowing

only drain events to occur.

The phase lock detector behaves in a manner analogous to

water in a tub (see Figure 49). The total capacity of the tub

is 4096 units, with −2048 denoting empty, 0 denoting the 50%

point, and +2047 denoting full. The tub also has a safeguard to

prevent overflow. Furthermore, the tub has a low water mark

at −1025 and a high water mark at +1024. To change the water

level, the phase lock detector adds water with a fill bucket or

removes water with a drain bucket. To specify the size of the fill

and drain buckets, use the unsigned 8-bit Profile x phase lock fill

rate and Profile x phase lock fill rate bit field (where x is a value

from 0 through 7, corresponding to a particular source profile).

When more filling is taking place than draining, the water level

in the tub eventually rises above the high water mark (+1024),

which causes the lock detector to indicate lock. When more

draining is taking place than filling, the water level in the tub

eventually falls below the low water mark (−1024), which causes

the lock detector to indicate unlock. The ability to specify the

threshold level, fill rate, and drain rate enables the user to tailor

the operation of the lock detector to the statistics of the timing

jitter associated with the input reference signal. Note that, for

debug purposes, the user can make the fill or drain rate zero to

force the lock detector to indicate a lock or unlock state,

respectively.

The water level in the tub is what the lock detector uses to

determine the lock and unlock conditions. When the water level

is below the low water mark (−1025), the lock detector indicates

an unlock condition. Conversely, when the water level is above

the high water mark (+1024), the lock detector indicates a lock

condition. When the water level is between the marks, the lock

detector holds its last condition. Figure 49 shows this concept

with an overlay of an example of the instantaneous water level

(vertical) vs. time (horizontal) and the resulting lock/unlock

states.

Note that whenever the AD9544 enters freerun or holdover

mode, the DPLL phase lock detector indicates an unlocked state.

For more information on how to choose the appropriate phase

lock threshold, fill rate, and drain rate values for a given

application, refer to the AN-1061 Application Note.

DPLL Frequency Lock Detector

The operation of the frequency lock detector is identical to that

of the phase lock detector, with two exceptions:

LOCKED

UNLOCKED

•

The fill or drain decision is based on the period deviation

between the reference of the DPLL and the feedback

signals, instead of the phase error at the output of the PFD.

The frequency lock detector is unaffected by the state of

the phase slew limiter.

2047

1024

LOCK LEVEL

FILL

RATE

DRAIN

RATE

0

•

UNLOCK LEVEL

–1025

–2048

Figure 49. Lock Detector Diagram

Rev. 0 | Page 47 of 62

AD9544

Data Sheet

The frequency lock detector provides the user with two status

bits in the IRQ map DPLLx mask section of the register map. The

DPLLx frequency lock bit (where x is 0 or 1) latches to Logic 1

when the DPLL changes state from not frequency locked to

frequency locked. The DPLLx frequency unlock bit latches to

Logic 1 when the DPLL changes state from frequency locked to

not frequency locked. Because these are latched bits, the user

must clear them via the IRQ map DPLLx clear section of the

register map to obtain visibility of subsequent state transitions

of the frequency lock detector.

Consider a case where it is desirable to set the Profile x

frequency lock threshold bit field to meet the frequency

threshold when the signal from the reference TDC is 80 kHz

and the signal from the feedback TDC is 79.32 kHz (or vice

versa).

Profile x Frequency Lock Threshold = |1/f_REF− 1/f_FB|/10⁻¹²

= |1/80,000 − 1/79,320|/10⁻¹²

= 170,161 (nearest integer)

= 0x0298B1 (hexadecimal)

The frequency lock detector uses the 24-bit unsigned Profile x

frequency lock threshold bit field (where x is a value from 0

through 7, corresponding to a particular source profile),

specified in units of picoseconds. Thus, the frequency threshold

value extends from 0 ps to 16.7 µs and represents the absolute

value of the difference in period between the reference and

feedback signals at the input to the DPLL.

For more information on how to choose the appropriate frequency

lock threshold, fill rate, and drain rate values for a given application,

refer to the AN-1061 Application Note.

Profile x Frequency Lock Threshold = |1/f_REF− 1/f_FB|/10⁻¹²

where:

f_REFis the frequency of the signal at the DPLL PFD reference

input.

f_FBis the frequency of the signal at the DPLL PFD feedback

input.

Rev. 0 | Page 48 of 62

Data Sheet

AD9544

PHASE STEP DETECTOR

PHASE STEP LIMIT

When a phase transient occurs that exceeds the prescribed

value, one or both of the following two events occurs,

depending on the state of the enable step detect reference fault

bit in the operational control Channel 0 and Channel 1 (DPLL0

and DPLL1) sections of the register map:

Although the AD9544 has the ability to switch between multiple

reference inputs, some applications use only one input and handle

reference switching externally (see Figure 50). Unfortunately,

this arrangement forfeits the ability of the AD9544 to mitigate

the output disturbance associated with a reference switchover,

because the reference switchover is not under the control of the

AD9544. However, the AD9544 offers a phase transient threshold

detection feature to help identify when an external reference

switchover occurs and to act accordingly.

•

Logic 0: the DPLL initiates a new acquisition sequence.

Logic 1: the reference monitor is reset.

When the enable step detect reference fault bit is Logic 0

(default), detection of a phase step causes only the first event to

occur. By initializing a new DPLL acquisition sequence, the

DPLL can take advantage of the fast acquisition feature,

assuming it is active, which is especially helpful for very low loop

bandwidth applications. In addition, a new acquisition manages

the impact of the phase step by either building out the phase or

slewing to the new phase in a hitless manner.

SWITCHOVER

CONTROL

AD9544

REFERENCE 1

REFx, REFxx

REFERENCE 2

Figure 50. External Reference Switching

When the enable step detect reference fault bit is Logic 1,

detection of a phase step causes both events to occur. Because

exceeding the phase step threshold in this case implies an

external switch to a new reference, resetting the reference

monitor forces it to establish new reference statics.

Phase transient threshold detection works by monitoring the

output of the DPLL phase detector for phase transients, but in a

manner that is somewhat jitter tolerant. Otherwise, the phase

transient threshold detector is prone to false positives.

To activate the phase transient threshold detection, program the

32-bit unsigned Profile x phase step threshold bit field (where x

is a value from 0 through 7, corresponding to a particular

source profile). The default value is zero, which disables the phase

transient threshold detector. A nonzero value denotes the

desired phase step threshold in units of picoseconds per the

following equation:

The phase transient threshold detector provides the user with a

live status bit in the status readback PLLx section of the register

map, as well as a latched status bit in the IRQ map DPLLx read

section of the register map. The DPLLx phase step detect bit

(where x is 0 or 1) latches to Logic 1 on threshold violation of

the phase transient threshold detector. Because this is a latched

bit, the user must clear it via the IRQ map DPLLx clear section

of the register map to obtain visibility of subsequent threshold

violations detected by the phase step detector.

Phase Step Threshold = Profile x Phase Step Threshold × 10⁻¹²

Note that the phase transient threshold detector is not active

unless the DPLL indicates frequency locked status.

Mitigating Phase Step Limit False Positives

As an example, determine the value of the Profile x phase step

threshold bit field necessary for a 12 ns limit. Solving the

previous equation for the phase step limit yields

When enabled, the phase transient threshold detector operates

continuously, as long as the associated reference is the active

reference for the DPLL (DPLL0 or DPLL1, assuming the DPLL

is frequency locked. As such, any phase disturbance at the input

to the phase detector of the DPLL is subject to violating the

threshold of the phase transient threshold detector. This

violation includes a user induced phase adjustment via the

DPLLx phase offset bit field or the Profile x phase skew bit field.

To mitigate false triggering of the phase transient threshold

detector (when enabled) due to intentional phase adjustments,

the user can employ the phase slew rate limiter DPLL.

Profile x Phase Step Threshold = (12 × 10⁻⁹)/10⁻¹²

= 12,000

= 0x00002EE0 (hexadecimal)

To reduce the likelihood of jitter induced threshold violations,

choose a phase step threshold of at least two times the expected

rms jitter (σ_JITTER) associated with the input reference signal.

Profile x Phase Step Threshold ≥ 2 × σ_JITTER

The following formula relates the maximum phase slew rate

(MPSR) necessary to prevent inadvertent triggering of the

phase transient threshold detector:

As such, in the previous example with Profile x phase step

threshold = 12,000, an input signal with 12 ns rms jitter is likely

to produce false positives because the signal violates the

previously described inequality. To reduce the likelihood of a

false positive, the inequality indicates Profile x phase step

threshold = 24,000 is a better choice. In fact, even with a value

of 24,000, there is still a slight probability of a jitter sample

exceeding 2 × σ_JITTER. As such, scaling σ_JITTERby four to six is an

even better choice.

MPSR = (P + F)/7

where:

P is the phase transient threshold detector limit (in

picoseconds).

F is the frequency (in Hz) at the input of the DPLL phase

detector.

Rev. 0 | Page 49 of 62

AD9544

Data Sheet

Note that this formula ignores other contributors to phase error,

including jitter, frequency offset, and propagation delay variation.

user may have two or more GNSS/GPS sources that have identical

frequency but may exhibit a fixed time offset due to a mismatch

between antenna cable lengths.

If the user has a prior knowledge of the timing of an external

event, such as the switching of the reference input clock source

via an external mux, rather than using the phase transient step

detector, a more robust solution is to invalidate the associated

reference manually. To do so, force a reference fault condition

via the appropriate operational controls bit field. Using this

method imposes the least impact on the steady state operation of

the device. The only steady state impact is that the validation

timer of the associated reference must be set to a duration that

is longer (with suitable margin) than the duration between the

assertion of the force fault condition and the occurrence of the

external event.

To activate the skew adjustment feature, program the 24-bit

signed Profile x phase skew bit field (where x is the profile number,

Profile 0 to Profile 7). The default value is zero, which disables

the skew adjustment feature. A nonzero value enables the skew

adjustment feature and denotes the desired time skew in units

of picoseconds per the following equation:

Time Skew = Profile x Phase Skew × 10⁻¹²

As an example, determine the value of the Profile x phase skew

bit field necessary for a time skew of −35 ns. Solving the

previous equation for the Profile x phase skew yields

Profile x Phase Skew = (−35 × 10⁻⁹)/10⁻¹²

SKEW ADJUSTMENT

= −35,000

Skew adjustment allows the user to associate a fixed phase offset

with a reference input, which, for example, is useful in applications

with redundant global navigation satellite system (GNSS)/

global positioning system (GPS) reference sources. That is, a

= 0xFF7748 (hexadecimal)

Rev. 0 | Page 50 of 62

Data Sheet

AD9544

EEPROM USAGE

OVERVIEW

EEPROM Upload

The AD9544 supports an external, I²C-compatible, EEPROM

with dedicated access. With some restrictions, the AD9544 also

supports multidevice access to a single external EEPROM on a

shared I²C common bus. The AD9544 has an on-chip I²C

master to interface to the EEPROM through the Mx pins.

To store the AD9544 register contents in the EEPROM, the user

must write a Logic 1 to the EEPROM save bit in the EEPROM

section of the register map. The EEPROM save bit does not

require an input/output update. Writing a Logic 1 to this bit

immediately triggers an upload sequence.

The AD9544 has the equivalent of a write protect feature in that

the user must write a Logic 1 to the EEPROM write enable bit

(in the EEPROM section of the register map) prior to requesting an

upload to the EEPROM. Attempting to upload to the EEPROM

without first setting the EEPROM write enable bit results in a

fault indication (that is, the AD9544 asserts the EEPROM fault bit

in the general status section of the register map).

Because the default register settings of the AD9544 do not

define a particular frequency translation, the user must factory

program the EEPROM content before it can be downloaded to

the register map (either automatically or manually). If desired,

the user can store custom device configurations by manually

forcing an upload to the EEPROM via the register map.

EEPROM CONTROLLER GENERAL OPERATION

A prerequisite to an EEPROM upload is the existence of an upload

sequence stored in the 15-byte EEPROM sequence section of

the register map. That is, the user must store a series of upload

instructions (see the EEPROM Instruction Set section) in the

EEPROM sequence section of the register map prior to executing

an EEPROM upload.

EEPROM Controller

The EEPROM controller governs all aspects of communication

with the EEPROM. Because the I²C interface uses a 100 kHz

(normal mode) or 400 kHz (fast mode) communication link,

the controller runs synchronous to an on-chip generated clock

source suitable for use as the I²C serial clock. The on-chip oscillator

enables asynchronously immediately on a request for activation

of the controller. When the oscillator starts, it notifies the

controller of its availability, and the controller activates. After

the requested controller operation is complete, the controller

disables the clock generator and returns to an idle state.

The EEPROM controller performs an upload sequence by reading

the instructions stored in the EEPROM sequence section of the

register map byte by byte and executing them in order. That is,

the data stored in the EEPROM sequence section of the register

map are instructions to the EEPROM controller on what to

store in the EEPROM (including operational commands and

AD9544 register data).

EEPROM Download

An EEPROM download transfers contents from the EEPROM

to the AD9544 programming registers and invokes specific

actions per the instructions stored in the EEPROM (see Table 31).

Automatic downloading is the most common method for

initiating an EEPROM download sequence, which initiates at

power-up of the AD9544, provided Pin M3 is Logic 1 at power-

up (see the Multifunction Pins at Reset/Power-Up section).

Alternatively, instead of cycling power to the AD9544 to initiate an

EEPROM download, the user can force the RESETB pin to

Logic 0, force Pin M3 to Logic 1, and then return the RESETB

pin to Logic 1 and remove the drive source from Pin M3.

Note that the EEPROM controller sets the EEPROM save in

progress bit (in the status readback section of the register map)

to Logic 1 while the upload sequence is in progress as an indication

to the user that the controller is busy.

Because the EEPROM sequence section of the register map is

only 15 bytes, it typically cannot hold enough instructions to

upload a complete set of AD9544 data to the EEPROM. Therefore,

most upload sequences necessitate that the user upload a series

of subsequences. For example, to accomplish a required upload

sequence consisting of 20 bytes of instructions, perform the

following procedure:

The user can also request an EEPROM download on demand

(that is, without resetting or cycling power to the AD9544) by

writing a Logic 1 to the EEPROM load bit in the EEPROM

section of the register map.

1. Write the first 14 instructions to the EEPROM sequence

registers in the EEPROM section of the register map, with

the 15th instruction being a pause instruction (see Table 31).

2. Initiate an EEPROM upload by writing Logic 1 to the

EEPROM save bit. When the EEPROM controller reaches

the pause instruction, it suspends the upload process and

waits for another assertion of the EEPROM save bit.

Note that the load from EEPROM bit does not require an

input/output update. Writing a Logic 1 to this bit immediately

triggers a download sequence.

The EEPROM controller sets the EEPROM load in progress bit

(in the general status section of the register map) to Logic 1

while the download sequence is in progress as an indication to

the user that the controller is busy.

3. While the controller pauses, write the remaining six bytes

of the upload sequence into the EEPROM sequence

registers in the EEPROM section of the register map,

followed by an end of data instruction (see Table 31).

4. Initiate an EEPROM upload by writing Logic 1 to the

EEPROM save bit. When the EEPROM controller reaches

the end of data instruction, it terminates the upload process.

Rev. 0 | Page 51 of 62

AD9544

Data Sheet

The previous procedure is an example of an upload sequence

consisting of two subsequences. Most upload sequences require

more than two subsequences; however, the procedure is the same.

Specifically, partition a long sequence into several subsequences

by using the pause instruction at the end of each subsequence

and the end of data instruction at the end of the final subsequence.

However, even if the test fails, device operation is unaffected

because there was no transfer of data to the AD9544 registers.

EEPROM Header

The EEPROM controller adds a header to stored data that

carries information related to the AD9544, such as

•

Vendor ID

Chip type

EEPROM Checksum

When the EEPROM controller encounters an end of data

instruction (see Table 31) during an upload sequence, it

computes a 32-bit cyclic redundancy check (CRC) checksum

and appends it to the stored data in the EEPROM. Similarly,

when the EEPROM controller executes a download sequence, it

computes a checksum on the fly. At the end of a download

sequence, the EEPROM controller compares the newly

computed checksum to the one stored in the EEPROM. If the

two checksums do not match, the EEPROM controller asserts

the EEPROM CRC error bit in the status readback section of

the register map.

Product ID

Chip revision

At the beginning of an EEPROM download sequence, the

EEPROM controller compares the stored header values to the

values in the corresponding registers of the AD9544. If the

controller detects a mismatch, it asserts the EEPROM fault bit

in the status readback section of the register map and

terminates the download.

EEPROM INSTRUCTION SET

The EEPROM controller relies on a combination of instructions

and data. An instruction consists of a single byte (eight bits).

Some instructions require subsequent bytes of payload data.

That is, some instructions are self contained operations, whereas

others are directions on how to process subsequent payload

data. A summary of the EEPROM controller instructions is

shown in Table 31.

To minimize the possibility of downloading a corrupted

EEPROM data set, the user can execute a checksum test by

asserting the verify EEPROM CRC bit in the EEPROM section

of the register map, which causes the EEPROM controller to

execute a download sequence, but without actually transferring

data to the AD9544 registers. The controller still computes an

on the fly checksum, performs the checksum comparison, and

asserts the EEPROM CRC error bit if the checksums do not

match. Therefore, after the device deasserts the EEPROM load

in progress bit, the user can check the EEPROM CRC fault bit

to determine if the test passed (that is, EEPROM CRC error = 0).

When the controller downloads the EEPROM contents to the

AD9544 registers, it does so in a linear fashion, stepping

through the instructions stored in the EEPROM. However, when

the controller uploads to the EEPROM, the sequence is a nonlinear

combination of various parts of the register map, as well as

computed data that the controller calculates on the fly.

Table 31. EEPROM Controller Instruction Set Summary

Instruction Code

(Hexadecimal)

0x00 to 0x7F

0x80

Response

Comments

Register transfer

Input/output update

Not applicable

Requires a 2-byte register address suffix

Assert input/output update during download

Undefined

0x81 to 0x8F

0x90

Calibrate APLLs

Calibrate the system clock PLL

Calibrate APLL0

Calibrate APLL1

Not applicable

Calibrate the system clock PLL, APLL0, and APLL1 during download

Calibrate only the system clock PLL during download

Calibrate only APLL0 during download

Calibrate only APLL1 during download

Reserved/unused

0x91

0x92

0x93

0x94 to 0x97

0x98

Force freerun

Force DPLL0 and DPLL1 to freerun during download

Force only DPLL0 to freerun during download

Force only DPLL1 to freerun during download

Reserved/unused

0x99

Force DPLL0 freerun

Force DPLL1 freerun

Not applicable

0x9A

0x9B to 0x9F

0xA0

Synchronize outputs

Synchronize Channel 0

Synchronize Channel 1

Not applicable

Synchronize all distribution outputs during download

Synchronize only Channel 0 distribution outputs during download

Synchronize only Channel 1 distribution outputs during download

Reserved/unused

0xA1

0xA2

0xA3 to 0xAF

0xB0

Clear condition

Set condition

Apply Condition 0 and reset the condition map

Apply Condition 1 to Condition 15, respectively

Undefined

0xB1 to 0xBF

0xC0 to 0xFD

0xFE

Not applicable

Pause

Pause the EEPROM upload sequence

0xFF

End of data

Marks the end of the instruction sequence

Rev. 0 | Page 52 of 62

Data Sheet

AD9544

Register Transfer Instructions (0x00 to 0x7F)

Condition Value

Instructions with a hexadecimal value from 0x00 through 0x7F

indicate a register transfer operation. Register transfer instructions

require a 2-byte suffix, which constitutes the starting address of

the AD9544 register targeted for transfer (where the first byte

to follow the data instruction is the most significant byte of the

register address). When the EEPROM controller encounters a

data instruction, it knows to interpret the next two bytes as the

register map target address.

The condition value has a one to one correspondence to the

conditional instruction. Specifically, the condition value is the

value of the conditional instruction minus 0xB0. Therefore,

condition values have a range of 0 to 15. The EEPROM controller

uses condition values in conjunction with the condition map,

while the user uses a condition value to populate the EEPROM

load condition bit field of the register map with a condition ID.

Condition ID

Note that the value of the register transfer instruction encodes

the payload length (number of bytes). That is, the EEPROM

controller knows how many register bytes to transfer to/from

the indicated register by adding 1 to the instruction value. For

example, Data Instruction 0x1A has a decimal value of 26;

therefore, the controller knows to transfer 27 bytes to and from

the target register (that is, one more than the value of the

instruction).

The condition ID is the value stored in the 4-bit EEPROM load

condition bit field in the EEPROM section of the register map.

The EEPROM controller uses the condition ID in conjunction

with the condition map to determine which instructions to

execute or ignore during a download sequence.

Condition Map

The condition map is a table maintained by the EEPROM

controller consisting of a list of condition values. When the

EEPROM controller encounters a conditional instruction

during a download sequence, it determines the corresponding

condition value of the instruction (0 to 15). If the condition

value is nonzero, the EEPROM controller places the condition

value in the condition map. Conversely, if the condition value

is zero, the controller clears the condition map and applies

Condition 0. Condition 0 causes all subsequent instructions to

execute unconditionally (until the controller encounters a new

conditional instruction that causes conditional processing).

Input/Output Update Instruction (0x80)

When the EEPROM controller encounters an input/output

update instruction during an upload sequence, it stores the

instruction in EEPROM. When encountered during a download

sequence, however, the EEPROM controller initiates an

input/output update event (equivalent to the user asserting the

IO_UPDATE bit in the serial port section of the register map).

Device Action Instructions (0x90 to 0xAF)

When the EEPROM controller encounters a device action

instruction during an upload sequence, it stores the instruction

in EEPROM. When encountered during a download sequence,

however, the EEPROM controller executes the specified action

per Table 31.

Conditional Processing

While executing a download sequence, the EEPROM controller

executes or skips instructions depending on the condition ID

and the contents of the condition map (except for the condi-

tional and end of data instructions, which always execute

unconditionally).

Conditional Instructions (0xB0 to 0xBF)

The conditional instructions allow conditional execution of

EEPROM instructions during a download sequence. During an

upload sequence, however, they are stored as is and have no

effect on the upload process.

If the condition map is empty or the condition ID is zero, all

instructions execute unconditionally during download. However,

if the condition ID is nonzero and the condition map contains a

condition value matching the condition ID, the EEPROM

controller executes the subsequent instructions. Alternatively,

if the condition ID is nonzero but the condition map does not

contain a condition value matching the condition ID, the

EEPROM controller skips instructions until it encounters a

conditional instruction with a condition value of zero or a

condition value matching the condition ID.

Conditional processing makes use of four elements:

•

The conditional instruction.

The condition value.

The condition ID.

The condition map.

Conditional Instruction

Note that the condition map allows multiple conditions to exist

at any given moment. This multiconditional processing mecha-

nism enables the user to have one download instruction sequence

with many possible outcomes, depending on the value of the

condition ID and the order in which the controller encounters

conditional instructions. An example of the use of conditional

processing is shown in Table 32.

When the EEPROM controller encounters a conditional

instruction during an upload sequence, it stores the instruction

in the EEPROM. When the EEPROM controller detects a

conditional instruction during a download sequence, it affects

the condition map as well as the outcome of conditional processing.

Rev. 0 | Page 53 of 62

AD9544

Data Sheet

AD9544

Table 32. Example Conditional Processing Sequence

DEVICE 1

SCL SDA M1 M2

DEVICE 2

SCL SDA M1 M2

33 35

Instruction

Operation

2

4

33

2

4

0x00 to 0x7F

A sequence of register transfer instructions

that execute unconditionally

SCL

SDA

EEPROM

0xB1

Apply Condition 1

SCL

SDA

CPU

SCL SDA

0x00 to 0x7F

A sequence of register transfer instructions

that execute only if the condition ID is 1

SCL SDA

0xB2

Apply Condition 2

Apply Condition 3

Figure 51. Level 1 Multidevice Configuration

0xB3

AD9544

DEVICE 1

SCL SDA M1 M2

DEVICE 2

SCL SDA M1 M2

33 35

0x00 to 0x7F

A sequence of register transfer instructions that

execute only if the condition ID is 1, 2, or 3

2

4

33

2

4

0x91

0xB0

0x80

0xFF

Calibrate the system clock PLL

Clear condition map

SDA

SCL

Input/output update

Terminate sequence

SCL SDA

EEPROM

SCL SDA

CPU

Figure 52. Level 2 Multidevice Configuration

Pause Instruction (0xFE)

Multidevice Bus Arbitration

The EEPROM controller only recognizes the pause instruction

during an upload sequence. Upon encountering a pause

instruction, the EEPROM controller enters an idle state, but

preserves the current value of the EEPROM address pointer.

The EEPROM controller implements bus arbitration by

continuously monitoring the SDA and SCL bus signals for start

and stop conditions. The controller can determine whether the

bus is idle or busy. If the bus is busy, the EEPROM controller

delays its pending I²C transfer until a stop condition indicates

that the bus is available.

One use of the pause instruction is for saving multiple, yet

distinct, values of the same AD9544 register, which is useful for

sequencing power-up conditions.

Bus arbitration is essential in cases where two I²C master

devices simultaneously attempt an I²C transfer. For example, if

one I²C master detects that SDA is Logic 0 when it is intended to be

Logic 1, it assumes that another I²C master is active and immedi-

ately terminates its own attempt to transfer data. Similarly, if

one I²C master detects that SCL is Logic 0 prior to entering a

start state, it assumes that another I²C master is active and stalls

its own attempt to drive the bus.

The pause instruction is also useful for executing an upload

sequence requiring more space than is available in the EEPROM

sequence registers in the EEPROM section of the register map

(see the EEPROM Upload section).

End of Data Instruction (0xFF)

When the EEPROM controller encounters an end of data

instruction during an upload sequence, it stores the instruction

in EEPROM along with the computed checksum, clears the

EEPROM address pointer, and then enters an idle state. When

encountered during a download sequence, however, the

EEPROM controller clears the EEPROM address pointer,

verifies the checksum, and then enters an idle state.

In either case, the prevailing I²C master completes its current

transaction before releasing the bus. Because the postponed I²C

master continuously monitors the bus for a stop condition, it

attempts to seize the bus and carry out the postponed transaction

on detection of such a stop condition.

Note that during EEPROM downloads, condition instructions

always execute unconditionally.

The EEPROM controller includes an arbitration timer to optimize

the bus arbitration process. Specifically, when the EEPROM

controller postpones an I²C transfer as a result of detecting bus

contention, it starts the arbitration timer. If the EEPROM controller

fails to detect a stop condition within 255 SCL cycles, it attempts

to force another transaction. If the bus is still busy, the EEPROM

controller restarts the arbitration timer, and the process continues

until the EEPROM controller eventually completes the pending

transaction.

MULTIDEVICE SUPPORT

Multidevice support enables multiple AD9544 devices to share

the contents of a single EEPROM. There are two levels of

multidevice support. Level 1 supports a configuration where

multiple AD9544 devices share a single EEPROM through a

dedicated I²C bus. Level 2 supports a configuration where

multiple AD9544 devices share a single EEPROM connected to

a common I²C bus that includes other I²C master devices.

Figure 51 and Figure 52 show the Level 1 and Level 2

configurations, respectively.

Rev. 0 | Page 54 of 62

Data Sheet

AD9544

Table 33. Template for a Multidevice EEPROM Sequence

Multidevice Configuration Example

Instructions

Comment

Consider two AD9544 devices (Device 1 and Device 2) that

share a single EEPROM, and assume both devices have a

common PLL0 configuration but differing PLL1 configurations.

0x00 to 0x7F

A sequence of register transfer instructions

associated with the PLL0 configuration

common to both devices

A template for an EEPROM sequence that accomplishes this

configuration is shown in Table 33. The sequence relies on

conditional processing to differentiate between Device 1 and

Device 2. Therefore, the user must program the condition ID

of both devices prior to executing an EEPROM download.

Specifically, the user must program the EEPROM load condition

bit field of Device 1 with a condition ID of 1 and Device 2 with

a condition ID of 2.

0xB1

Apply Condition 1

0x00 to 0x7F

A sequence of register transfer instructions

associated with the PLL1 configuration

specific to Device 1

0xB0

Clear the condition map

Apply Condition 2

0xB2

0x00 to 0x7F

A sequence of register transfer instructions

associated with the PLL1 configuration

specific to Device 2

0xB0

0x80

0xFF

Clear the condition map

Input/output update

End of sequence

Rev. 0 | Page 55 of 62

AD9544

Data Sheet

SERIAL CONTROL PORT

The AD9544 serial control port is a flexible, synchronous serial

communications port that provides a convenient interface to

many industry-standard microcontrollers and microprocessors.

The AD9544 serial control port is compatible with most

synchronous transfer formats, including I²C, Motorola SPI, and

Intel SSR protocols. The serial control port allows read/write

access to the AD9544 register map.

The chip select (CSB) pin is an active low control that gates read

and write operations. Assertion (active low) of the CSB pin

initiates a write or read operation to the AD9544 SPI port. The

user can transfer any number of data bytes in a continuous stream.

The register address is automatically incremented or decremented

based on the setting of the address ascension bit (Register 0x00).

The user must deassert the CSB pin following the last byte

transferred, thereby ending the stream mode. This pin is

internally connected to a 10 kΩ pull-up resistor. When CSB is

high, the SDIO and SDO pins enter a high impedance state.

The AD9544 uses the Analog Devices unified SPI protocol (see

the Analog Devices Serial Control Interface Standard). The

unified SPI protocol guarantees that all new Analog Devices

products using the unified protocol have consistent serial port

characteristics. The SPI port configuration is programmable via

Register 0x00.

Implementation Specific Details

The Analog Devices Serial Control Interface Standard provides

a detailed description of the unified SPI protocol and covers

items such as timing, command format, and addressing. The

unified SPI protocol defines the following device specific items:

Unified SPI differs from the SPI port found on older Analog

Devices products, such as the AD9557 and AD9558, in the

following ways:

•

Analog Devices unified SPI protocol revision: 1.0

Chip type: 0x5

•

Unified SPI does not have byte counts. A transfer is

terminated when the CSB pin goes high. The W1 and W0

bits in the traditional SPI become the A12 and A13 bits of

the register address. This is similar to streaming mode in

the traditional SPI.

Product ID: 0x012

Physical layer: 3-wire and 4-wire supported and 1.5 V,

1.8 V, and 2.5 V operation supported

Optional single-byte instruction mode: not supported

Data link: not used

•

The address ascension bit (Register 0x000) controls

whether register addresses are automatically incremented

or decremented regardless of the LSB/MSB first setting. In

traditional SPI, LSB first mode dictated auto-incrementing

and MSB first mode dictated auto-decrementing of the

register address.

Control: not used

Communication Cycle—Instruction Plus Data

The unified SPI protocol consists of a two-part communication

cycle. The first part is a 16-bit instruction word coincident with

the first 16 SCLK rising edges. The second part is the payload,

the bits of which are coincident with SCLK rising edges. The

instruction word provides the AD9544 serial control port with

information regarding the payload. The instruction word

•

The first 16 register addresses of devices that adhere to the

unified serial port have a consistent structure.

SPI/I²C PORT SELECTION

Although the AD9544 supports both the SPI and I²C serial port

protocols, only one is active following power-up (as determined

by the M4 multifunction pin during the start-up sequence). The

only way to change the serial port protocol is to reset (or power

cycle) the device. See Table 27 for the I²C address assignments.

W

includes the R/ bit that indicates the direction of the payload

transfer (that is, a read or write operation). The instruction

word also indicates the starting register address of the first

payload byte.

Write

SPI SERIAL PORT OPERATION

When the instruction word indicates a write operation, the

payload is written into the serial control port buffer of the

AD9544. Data bits are registered on the rising edge of SCLK.

Generally, it does not matter what data is written to blank

registers; however, it is customary to use 0s. Note that the user

must verify that all reserved registers within a specific range

have a default value of 0x00; however, Analog Devices makes

every effort to avoid having reserved registers with nonzero

default values.

Pin Descriptions

The serial clock (SCLK) pin serves as the serial shift clock. This

pin is an input. SCLK synchronizes serial control port read and

write operations. The rising edge SCLK registers write data bits,

and the falling edge registers read data bits. The SCLK pin

supports a maximum clock rate of 50 MHz.

The SPI port supports both 3-wire (bidirectional) and 4-wire

(unidirectional) hardware configurations and both MSB first

and LSB first data formats. Both the hardware configuration

and data format features are programmable. The 3-wire mode

uses the serial data input/output (SDIO) pin for transferring

data in both directions. The 4-wire mode uses the SDIO pin

for transferring data to the AD9544, and the SDO pin for

transferring data from the AD9544.

Most of the serial port registers are buffered; therefore, data

written into buffered registers does not take effect immediately.

To transfer buffered serial control port contents to the registers

that actually control the device requires an additional operation,

an IO_UPDATE operation, implemented in one of two ways.

One is to write a Logic 1 to Register 0x0F, Bit 0 (this bit is an

Rev. 0 | Page 56 of 62

Data Sheet

AD9544

autoclearing bit). The other is to use an external signal via

an appropriately programmed multifunction pin. The user can

change as many register bits as desired before executing an

input/output update. The input/output update operation transfers

the buffer register contents to their active register counterparts.

SPI MSB-/LSB-First Transfers

The AD9544 instruction word and payload can be transferred

MSB first or LSB first. The default for the AD9544 is MSB first.

To invoke LSB first mode, write a Logic 1 to Register 0x00, Bit 6.

Immediately after invoking LSB first mode, subsequent serial

control port operations are LSB first.

Read

If the instruction word indicates a read operation, the next

N × 8 SCLK cycles clock out the data starting from the address

specified in the instruction word, where N is the number of

data bytes to read. Read data appears on the appropriate data

pin (SDIO or SDO) on the falling edge of SCLK. The user must

latch the read data on the rising edge of SCLK. Note that the

internal SPI control logic does not skip over blank registers

during a readback operation.

Address Ascension

If the address ascension bit (Register 0x0000, Bit 5) is Logic 0,

serial control port register addressing decrements from the

specified starting address toward Address 0x0000. If the address

ascension bit (Register 0x0000, Bit 5) is Logic 1, serial control

port register addressing increments from the starting address

toward Address 0x3A3B. Reserved addresses are not skipped

during multibyte input/output operations; therefore, write the

default value to a reserved register and Logic 0s to unmapped

registers. Note that it is more efficient to issue a new write

command than to write the default value to more than two

consecutive reserved (or unmapped) registers.

A readback operation takes data from either the serial control

port buffer registers or the active registers, as determined by

Register 0x01, Bit 5.

SPI Instruction Word (16 Bits)

W

Table 34. Streaming Mode (No Addresses Skipped)

The MSB of the 16-bit instruction word is R/ , which indicates

Address Ascension

Increment

Stop Sequence

whether the ensuing operation is read or write. The next 15 bits

are the register address (A14 to A0), which indicates the starting

register address of the read/write operation (see Table 35). Note

that SPI controller ignores A14, treating it as Logic 0, because

the AD9544 has no register addresses requiring more than a

14-bit address word.

0x0000 … 0x3A3B

0x3A3B … 0x0000

Decrement

Table 35. Serial Control Port, 16-Bit Instruction Word

MSB

LSB

I0

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

R/W

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

CSB

DON'T CARE

SCLK DON'T CARE

DON'T CARE

SDIO

DON'T CARE

R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 53. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data

CSB

SCLK

DON'T CARE

SDIO

SDO

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

DON'T CARE

16-BIT INSTRUCTION HEADER

REGISTER (N) DATA

REGISTER (N – 1) DATA

REGISTER (N – 2) DATA

REGISTER (N – 3) DATA

DON'T

CARE

Figure 54. Serial Control Port Read—MSB First, Address Decrement, Four Bytes of Data

t_DS

t_HIGH

t_S

t_C

t_CLK

t_DH

t_LOW

CSB

SCLK

SDIO

DON'T CARE

R/W

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

D4

D3

D2

D1

D0

DON'T CARE

Figure 55. Timing Diagram for Serial Control Port Write—MSB First

Rev. 0 | Page 57 of 62

AD9544

Data Sheet

CSB

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N – 1

Figure 56. Timing Diagram for Serial Control Port Register Read—MSB First

CSB

SCLK DON'T CARE

DON'T CARE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

DON'T CARE

SDIO

Figure 57. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data

t_S

t_C

CS

t_CLK

t_HIGH

t_LOW

t_DS

SCLK

SDIO

t_DH

BIT N

BIT N + 1

Figure 58. Serial Control Port Timing—Write

Table 36. Serial Control Port Timing

Parameter

Description

t_DS

t_DH

t_CLK

t_S

Setup time between data and the rising edge of SCLK

Hold time between data and the rising edge of SCLK

Period of the clock

Setup time between the CSB falling edge and the SCLK rising edge (start of the communication cycle)

Setup time between the SCLK rising edge and CSB rising edge (end of the communication cycle)

Minimum period that SCLK is in a logic high state

t_C

t_HIGH

t_LOW

t_DV

Minimum period that SCLK is in a logic low state

SCLK to valid SDIO (see Figure 56)

Rev. 0 | Page 58 of 62

Data Sheet

AD9544

Start and stop functionality appears in Figure 60. The start

I²C SERIAL PORT OPERATION

condition is a high to low transition on the SDA line while SCL

is high. The master always generates the start condition to

initialize a data transfer. The stop condition is a low to high

transition on the SDA line while SCL is high. The master always

generates the stop condition to terminate a data transfer. The

SDA line must always transfer eight bits (one byte). Each byte

must be followed by an acknowledge bit; bytes are sent MSB first.

The I²C interface is popular because it requires only two pins

and easily supports multiple devices on the same bus. Its main

disadvantage is its maximum programming speed of 400 kbps.

The AD9544 I²C port supports the 400 kHz fast mode as well as

the 100 kHz standard mode.

To support 1.5 V, 1.8 V, and 2.5 V I²C operation, the AD9544

does not strictly adhere to every requirement in the original I²C

specification. In particular, it does not support specifications such

as slew rate limiting and glitch filtering. Therefore, the AD9544

is I²C compatible, but not necessarily fully I²C compliant.

The acknowledge bit (A) is the ninth bit attached to any 8-bit

data byte. An acknowledge bit is always generated by the

receiver to inform the transmitter that the byte has been

received. Acknowledgement consists of pulling the SDA line

low during the ninth clock pulse after each 8-bit data byte.

The AD9544 I²C port consists of a serial data line (SDA) and

a serial clock line (SCL). In an I²C bus system, the AD9544

connects to the serial bus (data bus SDA and clock bus SCL)

as a slave device; that is, the AD9544 does not generate an I²C

clock. The AD9544 uses direct 16-bit memory addressing rather

than 8-bit memory addressing, which is more common.

A

The nonacknowledge bit ( ) is the ninth bit attached to any

8-bit data byte. A nonacknowledge bit is always generated by

the receiver to inform the transmitter that the byte has not been

received. Nonacknowledgment consists of leaving the SDA line

high during the ninth clock pulse after each 8-bit data byte.

After issuing a nonacknowledge bit, the AD9544 I²C state

machine goes into an idle state.

The AD9544 allows up to four unique slave devices to occupy

the I²C bus via a 7-bit slave address transmitted as part of an I²C

packet. Only the device with a matching slave address responds

to subsequent I²C commands. Table 37 lists the supported

device slave addresses.

Data Transfer Process

The master initiates data transfer by asserting a start condition,

which indicates that a data stream follows. All I²C slave devices

connected to the serial bus respond to the start condition.

I²C Bus Characteristics

A summary of the various I²C abbreviations appears in Table 37.

The master then sends an 8-bit address byte over the SDA line,

Table 37. I²C Bus Abbreviation Definitions

W

consisting of a 7-bit slave address (MSB first) plus a R/ bit.

Abbreviation

Definition

Start

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device (Logic 0

indicates write, and Logic 1 indicates read).

S

Sr

P

Repeated start

Stop

The peripheral whose address corresponds to the transmitted

address responds by sending an acknowledge bit. All other

devices on the bus remain idle while the selected device waits

A

W

R

Acknowledge

Nonacknowledge

Write

W

for data to be read from or written to it. If the R/ bit is Logic 0,

Read

the master (transmitter) writes to the slave device (receiver).

W

If the R/ bit is Logic 1, the master (receiver) reads from the

An example of valid data transfer appears in Figure 59. One

clock pulse is required for each data bit transferred. The data on

the SDA line must be stable during the high period of the clock.

The high or low state of the data line can change only when the

clock signal on the SCL line is low.

slave device (transmitter). The format for these commands

appears in the Data Transfer Format section.

Data is then sent over the serial bus in the format of nine clock

pulses, one data byte (eight bits) from either master (write mode)

or slave (read mode), followed by an acknowledge bit from the

receiving device. The protocol allows a data transfer to consist

of any number of bytes (that is, the payload size is unrestricted).

In write mode, the first two data bytes immediately after the

slave address byte are the internal memory (control registers)

address bytes (the higher address byte first). This addressing

scheme gives a memory address of up to 2¹⁶− 1 = 65,535. The

data bytes after these two memory address bytes are register

data written to or read from the control registers. In read mode,

the data bytes following the slave address byte consist of register

data written to or read from the control registers.

SDA

SCL

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

Figure 59. Valid Bit Transfer

Rev. 0 | Page 59 of 62

AD9544

Data Sheet

When all the data bytes are read or written, stop conditions are

established. In write mode, the master device (transmitter)

asserts a stop condition to end data transfer during the clock

pulse following the acknowledge bit for the last data byte from the

slave device (receiver). In read mode, the master device (receiver)

receives the last data byte from the slave device (transmitter)

but does not pull SDA low during the ninth clock pulse (a

nonacknowledge bit). By receiving the nonacknowledge bit, the

slave device knows that the data transfer is finished and enters

idle mode. The master device then takes the data line low

during the low period before the 10^thclock pulse, and high

during the 10^thclock pulse to assert a stop condition.

A start condition can be used instead of a stop condition.

Furthermore, a start or stop condition can occur at any time,

and partially transferred bytes are discarded.

SDA

SCL

S

P

START CONDITION

STOP CONDITION

Figure 60. Start and Stop Conditions

MSB

SDA

SCL

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

3 TO 7

8

9

3 TO 7

8

9

10

P

1

2

1

2

S

Figure 61. Acknowledge Bit

MSB

SDA

SCL

ACK FROM

SLAVE RECEIVER

ACK FROM

SLAVE RECEIVER

3 TO 7

8

9

3 TO 7

8

9

10

P

1

2

1

2

S

Figure 62. Data Transfer Process (Master Write Mode, 2-Byte Transfer)

SDA

SCL

ACK FROM

NONACK FROM

MASTER RECEIVER

3 TO 7

8

9

3 TO 7

8

9

10

1

2

1

2

S

P

Figure 63. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge From Slave

Rev. 0 | Page 60 of 62

Data Sheet

AD9544

Data Transfer Format

subsequent reads (see Table 39). The receive byte format is used

to read the data byte(s) from RAM starting from the current

address (see Table 40). The read byte format is the combined

format of the send byte and the receive byte (see Table 41).

The write byte format is used to write a register address to the

RAM starting from the specified RAM address (see Table 38).

The send byte format is used to set up the register address for

Table 38. Write Byte Format

S

Slave

W

A

RAM address high byte

A

RAM address low byte

A

RAM

A

RAM

A

RAM

A

P

address

Data 0

Data 1

Data 2

Table 39. Send Byte Format

Slave address

S

W

A

RAM address high byte

RAM Data 0

A

RAM address low byte

A

P

Table 40. Receive Byte Format

Slave address

S

R

A

RAM Data 1

A

RAM Data 2

A

Table 41. Read Byte Format

S

Slave

address

W

A

RAM address

high byte

A

RAM address

low byte

A

Sr Slave

address

R

A

RAM

Data 0

A

RAM

Data 1

A

RAM

Data 2

A

P

I²C Serial Port Timing

SDA

t_LOW

t_R

t_{SU; DAT}

t_BUF

t_{HD; STA}

t_R

t_F

t_SP

t_F

SCL

t_{SU; STA}

t_{SU; STO}

t_{HD; STA}

t_HIGH

t_{HD; DAT}

S

Sr

P

S

Figure 64. I²C Serial Port Timing

Table 42. I²C Timing Definitions

Parameter

f_SCL

Description

Serial clock

t_BUF

Bus free time between stop and start conditions

Repeated hold time start condition

Repeated start condition setup time

Stop condition setup time

t_{HD; STA}

t_{SU; STA}

t_{SU; STO}

t_{HD; DAT}

t_{SU; DAT}

t_LOW

Data hold time

Data setup time

SCL clock low period

t_HIGH

SCL clock high period

t_R

Minimum/maximum receive SCL and SDA rise time

Minimum/maximum receive SCL and SDA fall time

t_F

t_SP

Pulse width of voltage spikes that must be suppressed by the input filter

Rev. 0 | Page 61 of 62

AD9544

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

7.10

0.30

0.25

0.18

7.00 SQ

6.90

PIN 1

INDICATOR

PIN 1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

37

36

48

1

0.50

BSC

5.70

EXPOSED

PAD

5.60 SQ

5.50

24

13

0.50

0.40

0.30

0.20 MIN

BOTTOM VIEW

5.50 REF

TOP VIEW

END VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4.

Figure 65. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.75 mm Package Height

(CP-48-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-48-13

AD9544BCPZ

AD9544BCPZ-REEL7

AD9544/PCBZ

−40°C to +85°C

48-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

CP-48-13

¹Z = RoHS Compliant Part.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D16391-0-10/17(0)

Rev. 0 | Page 62 of 62


型号：	AD9544BCPZ-REEL7
厂家：	ADI
描述：	Quad Input, 10-Output, Dual DPLL, 1 pps Synchronizer and Jitter Cleaner
文件：	总62页 (文件大小：1207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9544BCPZ-REEL7 [ADI]

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