AD9561 [ADI]
Pulse Width Modulator; 脉宽调制器
| 型号： | AD9561 |
| 厂家： | 
ADI |
| 描述： | Pulse Width Modulator |
| 文件： | 总8页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Pulse Width Modulator
AD9561
FUNCTIONAL BLOCK DIAGRAM
FEATURES
60 MHz Pulse Rate
8-Bit Resolution
AD9561
Center, Left or Right Justify
Low Power: 700 mW typical
Minimum Pulse Width: <5 ns
Maximum PW: 100 % Full-scale
RAMP
INTERNAL
TIMING
OUTPUT
LOGIC
CLOCK
RAMP
REF
CAL
OUT
APPLICATIONS
Laser Printers
Digital Copiers
Color Copiers
R
SET
CAL
DAC
PWM
OUT
CAL IN
8-BIT
DATA
L
A
T
C
H
L
DAC
CAL
OUT
A
T
C
H
SEM/DEM
LEM/TEM
RETRACE
GENERAL DESCRIPTION
Additionally, input data setup and hold time are symmetrical at
2 ns each, simplifying interface to the system bus.
The AD9561 is a second generation high speed, digitally
programmable pulse width modulator (PWM). Output pulse
width is proportional to an 8-bit DATA input value. Two
additional control inputs determine if the pulse is placed at the
beginning, middle or end of the clock period. Pulse width and
placement can be changed every clock cycle up to 60 MHz.
Finally, chip design and pinout are optimized to decrease
sensitivity of analog circuits to digital coupling. (See layout
section for detailed recommendations for optimum results.)
Inputs are TTL or CMOS compatible, and outputs are CMOS
compatible. The AD9561JR is packaged in a 28-lead plastic
SOIC. It is rated over the commercial temperature range, 0°C
to +70°C.
Pulse width modulation is a well proven method for controlling
gray scale and resolution enhancement in scanning laser print
engines. Modulating pulse width provides the most cost
effective method for continuous tone reproduction and resolu-
tion enhancement in low-to-moderate cost scanning electro-
photographic systems.
HIGHLIGHTS
1. 60 MHz native printer clock rate.
2. Single +5 V power supply.
3. On-chip Autocalibration.
The AD9561 uses precision analog circuits to control dot size
so that near-photographic quality images are practical without
the high frequency clock signals required by all digital approaches.
4. Pulse placement flexibility.
5. High resolution: 256 pulse widths.
The AD9561 has improved features and performance over its
predecessor, the AD9560. An improved ramp topology enables
control of pulse width through 100% of the dot clock period as
opposed to 95% for the AD9560. This enables smooth transi-
tion across dot boundaries for line screen applications.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1996
(+V = +5 V; RSET = 715 ⍀, CLOCK = 20 MHz unless otherwise noted)
AD9561–SPECIFICATIONS
S
AD9561JR
Parameter
Temp
Min
Typ
Max
Units
RESOLUTION
8
Bits
ACCURACY (@ 20 MHz)
Differential Nonlinearity
Integral Linearity1
+25°C
+25°C
+25°C
±0.5
±1.5
±0.75
±2
±4
LSB
LSB
LSB
Odd/Even Pulse Mismatch2
DIGITAL INPUTS
Logic “1” Voltage
Full
2.0
V
Logic “0” Voltage
Full
0.8
V
Input Current
Input Capacitance
Data Setup Time
Data Hold Time
Minimum Clock Pulse Width (HIGH)
Full
+25°C
Full
Full
Full
±1
µA
pF
ns
ns
ns
5
2.0
2.0
0.3
0.3
6
DYNAMIC PERFORMANCE
Maximum Trigger Rate
Full
+25°C
Full
Full
Full
Full
Full
Full
60
12
MHz
ns
ps/°C
ns
% Clock
ns
ns
3
Minimum Propagation Delay (tPD
Minimum Propagation Delay TC
Output Pulse Width @ Code 254
Output Pulse Width @ Code 255
Output Rise Time5, 6
)
20
60
5
100
1.8
1.8
6
28
3
3
Output Fall Time5, 6
RETRACE Propagation Delay
ns
PWM OUTPUT
Logic “1” Voltage5, 6
Logic “0” Voltage5, 6
Full
Full
4.6
4.6
V
V
0.4
0.4
CAL OUT
Logic “1” Voltage
Logic “0” Voltage
Full
Full
V
V
POWER SUPPLY7
Positive Supply Current (+5.0 V)
Power Dissipation
Full
Full
Full
Full
140
700
70
170
850
85
mA
mW
mA
mW
Power Reduce Current
Power Reduce Dissipation
Power Supply Rejection Ratio
350
425
Propagation Delay Sensitivity (TEM)8
+25°C
1.5
ns/V
NOTES
1Best Fit between codes 25 and 230. INL is very layout sensitive.
2Due to linearity mismatch in dual ramps.
3Measured from rising edge of clock to transition of Codes 0 to 255.
4Minimum pulse width (at 20 MHz) limited by rise time. Pulse width for Code 25 will be greater when CLOCK < 20 MHz.
5Output load = 10 pF and 2 mA source/sink.
6Load conditions to test output drive capability. Linearity will degrade with either capacitive or current loading. Best linearity obtained driving a single CMOS input.
7All performance specifications valid when supply maintained at +5 V, ±5%.
8Tested from +4.75 V to +5.25 V.
Specification subject to change without notice.
REV. 0
–2–
AD9561
ABSOLUTE MAXIMUM RATINGS1
PIN CONFIGURATION
Positive Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Digital Input Voltage Range . . . . . . . . . . . . . . . –0.5 V to VDD
Minimum RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Ω
Digital Output Current (Sourcing)2 . . . . . . . . . . . . . . . 10 mA
Digital Output Current (Sinking)2 . . . . . . . . . . . . . . . . 10 mA
Operating Temperature Range3 . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Lead Soldering Temperature (10 sec)4 . . . . . . . . . . . .+300°C
D2
28
27
26
25
24
23
22
1
2
3
4
D3
D1
D4
D5
D0 (LSB)
D6
SEM/DEM
D7(MSB)
5
6
LEM/TEM
V
CLOCK
DD
NOTES
V
1Absolute maximum ratings are limiting values, to be applied individually, and
beyond which serviceability may be impaired. Functional operation under any of
these conditions is not necessarily implied.
7
GND
DD
AD9561
TOP VIEW
(Not to Scale)
8
GND
21 OUT
2CAL OUT should drive a single TTL or CMOS input.
9
V
DD
20
19
GND
3Typical Thermal Impedance:
V
GND
10
11
12
13
DD
28-lead SOIC (plastic) θJA = 71.4 °C/W; θJC = 23°C/W.
4When soldering surface mount packages in vapor phase equipment, temperature
should not exceed 220°C for more than one minute.
18 RETRACE
CAL OUT
PWR REDUCE
GND
17
16
15
CAL START
V
DD
R
GND
14
SET
ORDERING GUIDE
Temperature Package
Range Description
Package
Option
PIN DESCRIPTIONS
Model
Pin
Name
Description
AD9561JR
0°C to +70°C 28-Lead SOIC R-28
AD9561JR-REEL* 0°C to +70°C 28-Lead SOIC R-28
1–5
6
7
D3–D7
CLOCK
VDD
Digital Data Bits, D7 Is MSB
Clock Input
+5 V Supply
*Tape and Reel ordered in multiples of 1000 ICs.
8
GND
Ground Return
9
VDD
+5 V Supply
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
Ground Return
CAL OUT
POWER REDUCE
GND
RSET
GND
Calibration Complete Output
Place AD9561 in Sleep Mode
Ground Return
Ramp Current Set Resistor
Ground Return
VDD
+5 V Supply
CAL START
RETRACE
VDD
GND
OUT
GND
VDD
LEM/TEM
Initiates Calibration Cycle
Force Output High
+5 V Supply
Ground Return
Modulated Pulse Out
Ground Return
+5 V Supply
Controls Leading (1) or
Trailing (0) Edge Modulation
25
SEM/DEM
Controls Single (1) or Dual (0)
Edge Modulation
26–28 D0–D2
Digital Data Bits, D0 is LSB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9561 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD9561
N
N+1
N+1
CLOCK
DATA
CONTROL
FF, XX
00, XX
C0, 10
C0, 0X
C0, 0X
80, 0X
40, 0X
00, XX
C0, 0X
E0, 11
FF, XX
0%
DNC
75%
TEM
75%
DEM
75%
DEM
50%
DEM
25%
DEM
0%
DNC
75%
DEM
87%
LEM
100%
DNC
PULSE
N+1
OUTPUT
PULSE N
Figure 1. Pulse Pattern Example
THEORY OF OPERATION
General
LEADING EDGE
MODULATION
The AD9561 is a mixed signal IC designed to provide high-
speed pulse width modulation in laser printers and copiers. It
uses high performance analog circuits to achieve high resolution
pulse control without requiring the excessively high clock rates
of an all digital solution.
TRAILING EDGE
MODULATION
Because of the sensitivity of analog circuits to digital crosstalk,
PCB layout is critical for achieving optimum results. Please read the
layout section at the end of this data sheet and follow suggestions
completely for best performance.
DUAL EDGE
MODULATION
The AD9561 was designed to facilitate either higher effective
resolution or photo-realistic image reproduction on low cost
laser print platforms. Its 8-bit pulse width resolution and pulse
positioning capabilities combine to offer the highest level of gray
shading and resolution enhancement flexibility available. It
also includes an autocalibration circuit to minimize external
components, and eliminates an extra burden on the system
microprocessor.
Figure 2. Modulation Modes
Pulse positioning within the CLOCK period is defined by the
following table:
Table I. Truth Table
SEM/DEM
LEM/TEM
Alignment
The Functional Block Diagram illustrates the analog content,
comprising ramp generators, DACs and comparators that
generate a series of pulses. These pulses are combined in the
output logic to form PWM OUT pulses whose width is propor-
tional to the 8-bit DATA and whose position is determined by
the SEM/DEM and LEM/TEM inputs.
1
1
0
1
0
X
LEM
TEM
DEM
Single-Edge Modulation offers two options in which one edge is
modulated while the other remains fixed relative to the CLOCK.
For Leading-Edge Modulation, the rising edge of the pulse is
delayed from the leading edge of the CLOCK proportional to
DATA, and the falling edge remains fixed at the end of the
CLOCK period. This may also be called “right-hand justified.”
The AD9561 employs a proprietary ramp topology that
eliminates the loss of dynamic range at the ends of the ramp.
The Functional Block Diagram is shown for illustration purposes
only and does not represent the actual implementation.
Modulation Modes
Similarly, Trailing-Edge Modulation has the rising edge fixed
on the beginning of the CLOCK period and the falling edge
delayed proportional to DATA. This can be called “left-hand
justified.”
Positioning the width controlled pulses at the beginning, middle
or end of the CLOCK period, as shown in Figure 2, adds
significantly to the flexibility of the AD9561. This is accom-
plished through control bit SEM/DEM and LEM/TEM. These
acronyms represent Single-Edge Modulation/Dual-Edge
Modulation and Leading-Edge Modulation/Trailing-Edge
Modulation. SEM/DEM and LEM/TEM are collectively
identified as CONTROL.
Dual-Edge Modulation is often called “center justified” because
the delay of both edges varies relative to the CLOCK. With
increasing values for DATA, pulse width increases with its
center remaining constant proportional to the CLOCK.
Like DATA, modulation control inputs SEM/DEM, and
LEM/TEM can be updated at the CLOCK rate up to 60 MHz.
REV. 0
–4–
AD9561
where F is the CLOCK frequency in Hz. The resistor value
determined by the equation will generate a current near center-
range of the autocalibration circuit.
Pulse Pattern Example
Figure 1 at the top of the previous page illustrates the PWM
OUT of the AD9561 with various DATA and CONTROL
inputs. The DATA format is Binary. In the Pulse Pattern
Example, the Hexadecimal format is used, i.e., FFH represents
decimal 255.
Autocalibration
The AD9561 should be calibrated when power is applied to the
system or after a power reduce cycle.
The top line shows the CLOCK; the second shows DATA and
CONTROL inputs, which are latched on the rising edge of
CLOCK. The third line shows the resulting pulse.
CAL START
1µs MIN
The AD9561 DATA and CONTROL inputs are double
latched. The OUTPUT pulse labeled “Pulse N” results from
DATA and CONTROL values latched in by the first CLOCK,
illustrating the one CLOCK period timing delay.
tAC
CAL OUT
The CONTROL value number for pulse one is shown as xx.
This means the value is not important because a 100% pulse
will be output for any CONTROL value for DATA value 255 or
FFH. Likewise, OUTPUT Pulse N is noted as 100% DNC (do
not care), also noting that CONTROL value is unimportant.
Figure 4. Autocalibration Timing
Autocalibration is initiated by applying a pulse of 1 µs minimum
duration to Pin 17, CAL START. The CLOCK pulse should be
applied continuously during calibration. As Figure 4 shows, the
initial state of CAL OUT is not known.
The fourth DATA/CONTROL value is C0/0X. This indicates
that the level for LEM/TEM is unimportant when SEM/DEM is
logic Level “0”.
During the CAL IN pulse, all internal logic is initialized for
calibration and proper synchronization once calibration is
complete; the falling edge of CAL IN initiates the Auto-CAL
cycle.
Selecting RSET
Because the AD9561 must provide full range coverage of the
CLOCK pulse period, the ramp time must be matched to the
CLOCK period. All components for the ramp generators, except
Auto-CAL is not affected by the code applied to the DATA or
CONTROL inputs. However, to assure that no pulses are
generated during calibration, it is suggested that all digital
inputs be held at Logic “0.”
RSET, are integrated in the AD9561.
RSET, is selected by the user to set the ramp time close to the
CLOCK period. The ramps are generated by constant current
sources charging on-chip capacitors.
On the falling edge of CAL IN, the ramp’s slope is set as slow as
possible for the current RSET. Figure 4 shows the RAMP slope
increasing as autocalibration adds small incremental currents,
until it crosses the internal REF LO before the end of the
CLOCK period.
RSET can be chosen in the range from 226 Ω for 60 MHz
operation to 16.5 kΩ for 1 MHz. Because the absolute value of
the on-chip capacitor can vary by ±20%, the autocalibration
circuit is included to fine tune the matching of the ramp time to
the CLOCK period.
END OF CLOCK CYCLE
RAMP
100
10
1
REF LO
TIME
RAMP
0
1
R
10
20
Figure 5. Autocalibration Conceptual
– kΩ
SET
The calibration current is incremented on each 32nd CLOCK
pulse until the full-scale ramp time is equal to the period of the
CLOCK. Cal Complete is detected and CAL OUT goes high
when the ramp crosses REF LO before it is reset by the next
CLOCK. With a maximum of 64 incremental increases, the
maximum autocalibration time, tAC, can be calculated by the
Figure 3. RSET Values vs. CLOCK Frequency
Figure 3 shows approximate values for RSET over the operating
frequency range. The following equation should be used to
determine RSET
:
30.2068 ×109
equation:
R =
F1.04414
32×64
tAC
=
FC
FC = CLOCK frequency in Hertz
where:
–5–
REV. 0
AD9561
This yields the maximum time from the trailing edge of CAL IN
to the rising edge of CAL OUT. As an example, the maximum
time required for auto-calibration for a system with clock frequency
of 20 MHz is 102.4 ms plus the width of the CAL IN pulse.
An ideal transfer would give 0% (or 0 ns) pulse width for a Code 0.
As the code is incremented in steps of one, the pulse width would
increase by 0.39% until it reached 100% for Code 255.
When operating at high clock rates, several of the most narrow
pulses do not reach valid logic Level “1” because of finite rise
time. For example, at 20 MHz, a 1.95% pulse (code 5 or 05H)
would have an expected pulse width of 1 ns. Because the rise
time is typically 1.5 ns, this pulse will not reach a full output
level. Therefore, depending on the clock rate, the lowest set of
codes produces a series of triangle waves increasing in width
and amplitude until a pulse of approximately 3 ns–5 ns reaches
a proper logic level. Thus, the transfer is flat until about
3 ns–5 ns pulse width (number of codes varies as a function of
CLOCK frequency).
Power Reduce
The POWER REDUCE function permits the user to power
down all nonessential circuits when the printer is not active.
Applying a Logic “0” to POWER REDUCE decreases the
power supply requirement by approximately half.
APPLICATIONS
DATA Timing
Input DATA to the AD9561 is double latched. As a result of the
internal timing, the OUTPUT is delayed more than one clock
period from its corresponding DATA word. Figure 6 illustrates
timing of DATA and CONTROL inputs relative to the CLOCK.
Because of the new ramp topology in the AD9561, the transfer
function extends slightly greater than 100% (typically 102%) of
the clock period. This has the effect of creating smooth transitions
at the CLOCK period boundaries instead of the discontinuities
produced by the AD9560.
CLOCK
SETUP
HOLD
tCLOCK
DATA
CONTROL
tCLOCK
tCLOCK
tCLOCK
tPD
Figure 6. DATA and CONTROL Timing
The DATA and CONTROL inputs to the AD9561 are stan-
dard master-slave latches. Inputs are latched in on the rising
edge of the CLOCK with 2 ns Set-Up time and 2 ns Hold time.
This is a design improvement over the AD9560 meant to
simplify interfacing the AD9561 to digital processing circuits.
LEM
(RIGHT JUSTIFIED)
TEM
(LEFT JUSTIFIED)
DEM
(CENTER JUSTIFIED)
Figure 8. Dot Clock Period Transitions
A propagation delay exists between the CLOCK and OUTPUT
pulses. The minimum propagation delay can be observed when
alternating between codes 0 (00H hexadecimal) and 255 (FFH
hexadecimal). This delay is due in part to normal circuit
propagation; the remainder is due to time required to imple-
ment the proprietary ramp function. OUTPUT pulse transi-
tions will typically occur 22 ns after the rising edge of CLOCK.
It may vary from 10 ns–35 ns over temperature.
As shown in Figure 8, a Leading Edge Modulated pulse followed
by a Trailing Edge Modulated pulse will stay high from the rising
edge of the first pulse to the falling edge of the second. This is
due to Code 255 being designed to be typically 102% of the
CLOCK period. (Dashed lines indicate where transitions
would occur if the code for the following or preceding period
were 0.) Likewise, no gap occurs for maximum width Trailing
Edge Modulation to max pulse width for Dual Edge Modula-
tion. Because the ending and starting characteristics of all
modes are symmetrical, any combination of pulses that ends at
the boundary of the first period and starts at the boundary of
the second period will produce a continuous pulse across the
boundary.
Transfer Function
Output pulse width increases with increasing DATA values. As
the heavy line of Figure 7 shows, the transfer function of the
AD9561 is slightly nonideal.
100
80
60
40
20
0
For the purposes of printing text, or any time absolute white or
black is required, 0 is decoded and a 100% LOW is output in
the next CLOCK cycle. Similarly, 255 is detected and the next
pulse is 100% HIGH.
Retrace
The RETRACE function permits driving the output to a
constant Logic High. For laser printer applications, applying a
logic “1” to RETRACE holds the laser on during the retrace
period so end of scan can be detected. Returning it to Logic
Low gives control back to the input data bits D0–D7.
0
128
25
255
CODE
Figure 7. Pulse Width Transfer Function
REV. 0
–6–
AD9561
Grounding and Bypassing
To reiterate the key layout considerations, high speed
Because the AD9561 uses analog circuits to achieve its superb
gray scale resolution, caution must be exercised when incorpo-
rating it into the mostly digital controller card for a printer.
Achieving the accuracy designed into the AD9561 requires that
interference due to improper grounding, power supply noise and
digital coupling be minimized by following good layout practices.
It is strongly urged that all following recommendations be
followed.
digital traces should not be located near the RSET pin or
under the center of the IC body.
A final interface consideration relates to rise/fall time of
the high speed signals. Some logic families have rise and
fall times as fast as 2 V/ns. This can result in on-chip
parasitic coupling of these signals into the analog section.
The undesirable effect can be eliminated by inserting
series resistors in the DATA, SEM/DEM and LEM/
TEM connections. These resistors, in conjunction with the
capacitance of the input pin and bond pad, will form a low
pass filter to limit slew rate of the signals. The value of
these resistors should be chosen based on trading off slower
rise and fall time to possible interference to set up and hold
times for faster clock rates.
Factory characterization proves that a single ground plane
dedicated to the AD9561 is most effective. This is atypical of
many mixed signal circuits that use separate analog and digital
grounds. Due to the operating speed of the AD9561, separate
grounds result in erratic performance, which is eliminated by
using a single isolated ground plane. This is because the DATA
“low” value can be different from the ground value of the
AD9561. All pins on the AD9561 labeled GROUND should
be connected to the single dedicated ground plane. For best
results, it is suggested that this plane be in the first interior layer
under the IC. To assure logic level compatibility from the drive
circuits to the AD9561, a single connection to the board’s main
ground is necessary.
Power supply noise can also disrupt the linear circuits of
the AD9561. Since switching power supplies are becoming
the norm in most systems, caution should be exercised to
minimize switching noise reaching the AD9561. The IC is
designed for maximum power supply rejection. However,
frequency content of switching supply noise often exceeds
the frequency range of highest rejection. The preferred
method would be to use a linear regulator from a higher
supply voltage. If this is not practical, insert a ferrite bead
in series with the supply connection. If possible, a VDD
plane or a substantial width trace should connect VDD to
Pin 7 first and then connect to each of the other VDD pins
with wide traces. Thorough decoupling will complete a low
pass filter for the supply.
The connection between the dedicated ground plane and the
board’s main ground should be parallel to the path of the digital
signals interfacing to the AD9561. High frequency return current
seeks the path most parallel to the signal current. Whenever a
parallel path does not exist, ground bounce results.
CLOCK, DATA and CONTROL signal traces should run
from the drive logic to the AD9561 in a group parallel to the
connection between the system ground and the AD9561
ground. Using more than one signal plane will permit these
traces to be as close to the ground interconnection as possible.
This results in lowest impedance ground return and minimum
ground interference due to digital switching.
All VDD connections should be connected together. 0.1 µF
chip capacitors should be connected as closely as possible
to each VDD pin to the dedicated ground plane. Laboratory
results indicate that performance is maximized when these
chip capacitors are mounted on the same side of the PC
card as the AD9561. If mounting chip components on the
same side as the AD9561 is not a preferred manufacturing
method, due consideration is encouraged to make an excep-
tion, at least in the case of RSET and as many decoupling
capacitors as practical. Additionally, a 10 µF tantalum
capacitor should decouple the supply on the AD9561 side
of the regulator or ferrite bead, also to the dedicated
ground plane.
Attention to subtle layout characteristics can yield significant
improvement in performance of high speed mixed signal ICs.
The AD9561 pinouts were chosen for maximum isolation of
sensitive pins such as RSET. The Pin 1 end of the IC should be
oriented toward the source of the high speed digital inputs.
This will help assure that these signal runs are short, with
essentially the same length, thus having equal propagation
delays. Most importantly, it will facilitate orienting traces to
minimize coupling.
For a recommended layout, see the AD9561/PCB data
sheet. A copy can be obtained by calling Applications
Support at 1-800-ANALOGD.
High speed digital traces including DATA, CLOCK, SEM/
DEM, LEM/TEM and the OUTPUT should not pass under the
body of the IC. The CLOCK, in particular, should enter
perpendicular to the IC.
For best results, the OUTPUT trace should exit perpendicular
to the IC and pass through a via to a signal layer under the
ground plane. This trace or any resistor or other component
of the output circuit should not be parallel to RSET as electro-
magnetic coupling can occur, causing the ramp current reference
to be noisy and linearity to deteriorate.
Optimally, RSET should be a chip resistor located on the same
side of the board as the AD9561. It should be located close to
Pin 14, without being close to the other IC pins. RSET should
be on the top of the board with the AD9561 with no vias to add
stray reactance and additional coupling paths.
REV. 0
–7–
AD9561
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SOIC
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45°
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
–8–
REV. 0
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