AD9613-170EBZ_技术文档

12-Bit, 170 MSPS/210 MSPS/250 MSPS,

1.8 V Dual Analog-to-Digital Converter (ADC)

AD9613

Data Sheet

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

DRVDD

SNR = 69.6 dBFS at 185 MHz f_INand 250 MSPS

SFDR = 86 dBc at 185 MHz f_INand 250 MSPS

−149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS A_INand

250 MSPS

Total power consumption: 770 mW at 250 MSPS

1.8 V supply voltages

VIN+A

PIPELINE

12-BIT

ADC

12

D0±

.

VIN–A

VCM

PARALLEL

DDR LVDS

AND

AD9613

VIN+B

PIPELINE

12-BIT

ADC

12

D11±

DRIVERS

LVDS (ANSI-644 levels) outputs

VIN–B

Integer 1-to-8 input clock divider (625 MHz maximum input)

Sample rates of up to 250 MSPS

IF sampling frequencies of up to 400 MHz

Internal ADC voltage reference

Flexible analog input range

1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)

ADC clock duty cycle stabilizer

DCO±

OR±

REFERENCE

1 TO 8

CLOCK

DIVIDER

SERIAL PORT

OEB

PDWN

SCLK SDIO

CSB

CLK+

CLK– SYNC

95 dB channel isolation/crosstalk

Serial port control

NOTES

1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A

AND CHANNEL B LVDS OUTPUT DATA.

Energy-saving power-down modes

Figure 1.

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers (3G)

TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Ultrasound equipment

Broadband data applications

GENERAL DESCRIPTION

The AD9613 is a dual 12-bit, analog-to-digital converter (ADC)

with sampling speeds of up to 250 MSPS. The AD9613 is designed

to support communications applications where low cost, small

size, wide bandwidth, and versatility are desired.

Programming for setup and control is accomplished using a

3-wire SPI-compatible serial interface.

The AD9613 is available in a 64-lead LFCSP and is specified

over the industrial temperature range of −40°C to +85°C. This

product is protected by a U.S. patent.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of user-

selectable input ranges. An integrated voltage reference eases design

considerations. A duty cycle stabilizer (DCS) is provided to

compensate for variations in the ADC clock duty cycle,

PRODUCT HIGHLIGHTS

1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.

2. Fast overrange and threshold detect.

3. Proprietary differential input maintains excellent SNR

performance for input frequencies of up to 400 MHz.

4. SYNC input allows synchronization of multiple devices.

5. 3-pin, 1.8 V SPI port for register programming and register

readback.

allowing the converters to maintain excellent performance.

The ADC output data is routed directly to the two external 12-bit

LVDS output ports and formatted as either interleaved or channel

multiplexed.

6. Pin compatibility with the AD9643, allowing a simple

migration up to 14 bits, and with the AD6649 and the AD6643.

Flexible power-down options allow significant power savings,

when desired.

Rev. C

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rightsof third parties that may result fromits use. Specifications subject to change without notice. No

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Trademarks andregisteredtrademarks are the property of their respective owners.

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Technical Support

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AD9613

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Analog Input Considerations ................................................... 23

Voltage Reference ....................................................................... 25

Clock Input Considerations...................................................... 25

Power Dissipation and Standby Mode .................................... 27

Digital Outputs ........................................................................... 27

ADC Overrange (OR)................................................................ 27

Channel/Chip Synchronization.................................................... 28

Serial Port Interface (SPI).............................................................. 29

Configuration Using the SPI..................................................... 29

Hardware Interface..................................................................... 29

SPI Accessible Features.............................................................. 30

Memory Map .................................................................................. 31

Reading the Memory Map Register Table............................... 31

Memory Map Register Table..................................................... 32

Memory Map Register Description ......................................... 34

Applications Information .............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

ADC DC Specifications............................................................... 3

ADC AC Specifications ............................................................... 4

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 11

Thermal Characteristics ............................................................ 11

ESD Caution................................................................................ 11

Pin Configurations and Function Descriptions ......................... 12

Typical Performance Characteristics ........................................... 16

Equivalent Circuits ......................................................................... 22

Theory of Operation ...................................................................... 23

ADC Architecture ...................................................................... 23

Changes to Figure 5 and Pin 7 and Pin 8 Descriptions............. 14

Changes to Pin 42 and Pin 43, Output Enable Bar and Power-

Down Pin Type, and Pin 47 Descriptions................................... 15

Changes to Typical Performance Characteristics Conditions.. 16

Changes to Fiugre 43...................................................................... 22

Added ADC Overrange (OR) Section......................................... 27

Changes to Channel/Chip Synchronization Section ................. 28

Changes to Reading the Memory Map Register Table

Section and Transfer Register Map Section ................................ 31

Changes to Register 0x02, Bits[5:4].............................................. 32

Changes to Register 0x16, Bit 5 .................................................... 33

Added Register 0x3A ..................................................................... 34

Deleted Register 0x59 .................................................................... 34

Changes to Bit 0—Master Sync Buffer Enable Section ............. 34

Deleted SYNC Pin Control (Register 0x59) Section.................. 34

REVISION HISTORY

1/13—Rev. B to Rev. C

Changes to Features...........................................................................1

Changes to Table 1.............................................................................3

Changes to Table 2 ............................................................................5

Change to Logic Inputs (SDIO) Paramter, Table 3........................6

Changes to Table 4.............................................................................8

Change to Reading the Memory Map Register Table Section........31

Changes to Table 14.........................................................................33

Change to Memory Map Register Description Section..............34

Updated Outline Dimensions........................................................36

9/11—Rev. A to Rev. B

Changes to Figure 1.......................................................................... 1

Changes to Temperature Drift Parameters ................................... 3

Changes Output Offset Voltage (V_OS), ANSI Mode Typ

5/11—Rev. 0 to Rev. A

Parameter and Output Offset Voltage (V_OS), Reduced Swing

Mode Parameter................................................................................ 7

Changes DCO to Data Skew (t_SKEW) Parameters .......................... 8

Changes to Output Enable Bar and Power-Down Pin Type

and Pin 47 Description .................................................................. 13

Changes to Table 2, AD9613-170: Worst Second or Third

Harmonic and Worst Other (Harmonic or Spur) Max Values

and Spurious Free Dynamic Range Min Value .............................4

4/11—Revision 0: Initial Version

Rev. C | Page 2 of 36

Data Sheet

AD9613

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, DCS enabled,

unless otherwise noted.

Table 1.

AD9613-170

Temp Min Typ Max

AD9613-210

Min Typ Max

AD9613-250

Min Typ Max

Parameter

Unit

RESOLUTION

Full

12

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Full

25°C

Full

25°C

Guaranteed

±10

Guaranteed

±10

+3/−5

±0.5

±10

±±

±0.5

mV

+2/−6

±0.5

%FSR

LSB

Differential Nonlinearity (DNL)

±0.25

±0.20

±0.25

±0.28

Integral Nonlinearity (INL)¹

±0.5

±0.6

±0.8

MATCHING CHARACTERISTIC

Offset Error

Gain Error

Full

±13

±2.5

±13

+3.5/−2

±13

mV

+3.5/−2.5 %FSR

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

±5

±70

±5

±80

±5

±100

ppm/°C

LSB rms

INPUT-REFERRED NOISE

VREF = 1.75 V

25°C

0.39

ANALOG INPUT

Input Span

Full

1.75

2.5

20

1.75

2.5

20

1.75

2.5

20

V p-p

pF

kΩ

V

Input Capacitance²

Input Resistance³

Input Common-Mode Voltage

POWER SUPPLIES

Supply Voltage

AVDD

0.9

Full

1.7

1.8

1.9

1.7

1.8

1.9

1.7

1.8

1.9

V

DRVDD

Supply Current

1

I_AVDD

Full

230

1±2

250

160

2±1

159

265

185

252

176

275

210

mA

1

I_DRVDD

POWER CONSUMPTION

Sine Wave Input¹(DRVDD = 1.8 V)

Standby Power^±

Full

670

90

10

738

720

90

10

810

770

90

10

873

mW

Power-Down Power

¹Measured with a low input frequency, full-scale sine wave.

²Input capacitance refers to the effective capacitance between one differential input pin and its complement.

³Input resistance refers to the effective resistance between one differential input pin and its complement.

^±Standby power is measured with a dc input and the CLK± pin inactive (that is, set to AVDD or AGND).

Rev. C | Page 3 of 36

AD9613

Data Sheet

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full scale input range, unless

otherwise noted.

Table 2.

AD9613-170

AD9613-210

AD9613-250

Parameter¹

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

SIGNAL-TO-NOISE-RATIO (SNR)

f_IN= 30 MHz

f_IN= 90 MHz

25°C

Full

25°C

Full

70.1

70.0

70.1

70.0

69.8

dBFS

69.3

69.2

f_IN= 1±0 MHz

f_IN= 185 MHz

69.8

69.5

69.8

69.5

69.6

69.2

67.8

f_IN= 220 MHz

25°C

69.±

69.3

69.0

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

f_IN= 30 MHz

f_IN= 90 MHz

25°C

Full

25°C

Full

69.1

69.0

69.1

69.0

68.8

dBFS

68.2

68

f_IN= 1±0 MHz

f_IN= 185 MHz

68.8

68.5

68.8

68.5

68.6

68.2

66.5

68.±

68.3

68.0

f_IN= 220 MHz

25°C

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 30 MHz

f_IN= 90 MHz

f_IN= 1±0 MHz

f_IN= 185 MHz

25°C

11.2

11.1

11.2

11.1

11.0

11.2

11.1

11.0

Bits

f_IN= 220 MHz

WORST SECOND OR THIRD HARMONIC

f_IN= 30 MHz

f_IN= 90 MHz

25°C

Full

25°C

Full

dBc

−9±

−92

−9±

−90

−89

−78

−80

f_IN= 1±0 MHz

f_IN= 185 MHz

−87

−89

−88

−83

−86

−80

25°C

f_IN= 220 MHz

−80

−83

−85

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 30 MHz

f_IN= 90 MHz

25°C

Full

25°C

Full

dBc

9±

92

90

92

89

78

80

f_IN= 1±0 MHz

f_IN= 185 MHz

87

89

88

83

86

80

25°C

f_IN= 220 MHz

83

85

WORST OTHER (HARMONIC OR SPUR)

f_IN= 30 MHz

f_IN= 90 MHz

25°C

Full

25°C

Full

dBc

−97

−96

−95

−93

−92

−78

−80

f_IN= 1±0 MHz

f_IN= 185 MHz

−97

−91

−97

−96

−91

−80

25°C

f_IN= 220 MHz

−93

−9±

−89

Rev. C | Page ± of 36

Data Sheet

AD9613

AD9613-170

AD9613-210

AD9613-250

Parameter¹

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

TWO-TONE SFDR

25°C

dBc

f_IN= 18±.12 MHz (−7 dBFS),

187.12 MHz (−7 dBFS)

88

CROSSTALK²

95

Full

dB

FULL POWER BANDWIDTH³

25°C

1000

MHz

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

²Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.

³Full power bandwidth is the bandwidth of operation where typical ADC performance can be achieved.

Rev. C | Page 5 of 36

AD9613

Data Sheet

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled,

unless otherwise noted.

Table 3.

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

High Level Input Current

Low Level Input Current

Input Capacitance

Full

0.9

3.6

V

V p-p

V

0.3

AGND

0.9

AVDD

1.±

V

Full

10

−22

22

−10

µA

pF

kΩ

±

8

10

12

Input Resistance

SYNC INPUT

Logic Compliance

Internal Bias

CMOS/LVDS

0.9

Full

V

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

AGND

1.2

AGND

−5

AVDD

0.6

V

+5

µA

pF

kΩ

−5

1

16

Input Resistance

12

20

LOGIC INPUT (CSB)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

0

−5

2.1

0.6

+5

V

µA

kΩ

pF

−80

+±5

26

2

Input Capacitance

LOGIC INPUT (SCLK)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

0

±5

−5

2.1

0.6

70

V

µA

kΩ

pF

+5

26

2

Input Capacitance

LOGIC INPUTS (SDIO)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.22

0

±5

−5

2.1

0.6

70

V

µA

kΩ

pF

+5

26

5

Input Capacitance

Rev. C | Page 6 of 36

Data Sheet

AD9613

Parameter

Temp

Min

Typ

Max

Unit

LOGIC INPUTS (OEB, PDWN)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Input Capacitance

Full

1.22

0

±5

−5

2.1

0.6

70

V

µA

kΩ

pF

+5

26

5

DIGITAL OUTPUTS

LVDS Data and OR Outputs

Differential Output Voltage (V_OD), ANSI Mode

Output Offset Voltage (V_OS), ANSI Mode

Differential Output Voltage (V_OD), Reduced Swing Mode

Output Offset Voltage (V_OS), Reduced Swing Mode

Full

250

1.15

150

1.15

350

1.22

200

1.22

±50

1.35

280

1.35

mV

V

mV

V

¹Pull up.

²Pull down.

Rev. C | Page 7 of 36

AD9613

Data Sheet

SWITCHING SPECIFICATIONS

Table 4.

AD9613-170

AD9613-210

AD9613-250

Parameter

Temp Min Typ Max Min

Typ Max Min Typ Max Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Conversion Rate¹

Full

625

170

625

210

625

250

MHz

MSPS

ns

±0

5.8

±0

±.8

±0

±

CLK Period, Divide-by-1 Mode (t_CLK

)

CLK Pulse Width High (t_CH

)

Divide-by-1 Mode, DCS Enabled

Divide-by-1 Mode, DCS Disabled

Divide-by-2 Mode Through Divide-by-8 Mode

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

DATA OUTPUT PARAMETERS

LVDS Mode

Full

2.61 2.9

2.76 2.9

0.8

3.19

3.05

2.16

2.28

0.8

2.±

2.6±

2.52

1.8

1.9

0.8

2.0

2.2

2.1

ns

1.0

0.1

1.0

0.1

1.0

0.1

ps rms

Data Propagation Delay (t_PD

DCO Propagation Delay (t_DCO

)

Full

6.0

6.7

0.7

10

1.0

0.1

10

6.0

6.7

0.7

10

1.0

0.1

10

6.0

6.7

0.7

10

1.0

0.1

10

ns

Cycles

ns

ps rms

µs

)

DCO to Data Skew (t_SKEW

Pipeline Delay (Latency)

Aperture Delay (t_A)

)

0.±

1.0

0.±

1.0

0.±

1.0

Aperture Uncertainty (Jitter, t_J)

Wake-Up Time (from Standby)

Wake-Up Time (from Power Down)

Out-of-Range Recovery Time

250

3

250

3

Cycles

¹Conversion rate is the clock rate after the divider.

Rev. C | Page 8 of 36

Data Sheet

AD9613

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min Typ Max Unit

SYNC TIMING REQUIREMENTS

See Figure 3 for timing details

t_SSYNC

t_HSYNC

SYNC to the rising edge of CLK setup time

SYNC to the rising edge of CLK hold time

See Figure 58 for SPI timing diagram

0.3

0.±

ns

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Time required for the SDIO pin to switch from an input to an output

relative to the SCLK falling edge (not shown in Figure 58)

2

±0

2

10

ns

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an input

relative to the SCLK rising edge (not shown in Figure 58)

10

ns

Rev. C | Page 9 of 36

AD9613

Data Sheet

Timing Diagrams

t_A

N – 1

N + 4

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCO–

DCO+

t_SKEW

t_PD

PARALLEL INTERLEAVED

D0±

(LSB)

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

CH B

N – 8

CH A

N – 7

CH B

N – 7

CH A

N – 6

.

CHANNEL A AND

.

CHANNEL B

D11±

(MSB)

CH A

N – 10

CH B

N – 10

CH A

N – 9

CH B

N – 9

CH A

N – 8

CH B

N – 8

CH A

N – 7

CH B

N – 7

CH A

N – 6

CHANNEL MULTIPLEXED

(EVEN/ODD) MODE

D0±/D1±

(LSB)

CH A0

N – 10

CH A1

N – 10

CH A0

N – 9

CH A1

N – 9

CH A0

N – 8

CH A1

N – 8

CH A0

N – 7

CH A1

N – 7

CH A0

N – 6

.

CHANNEL A

D10±/D11±

CH A10 CH A11

CH A10 CH A11 CH A10 CH A11

CH A10 CH A11 CH A10

(MSB)

N – 10

N – 9

N – 8

N – 7

N – 6

CHANNEL MULTIPLEXED

(EVEN/ODD) MODE

D0±/D1±

(LSB)

CH B0

N – 10

CH B1

N – 10

CH B0

N – 9

CH B1

N – 9

CH B0

N – 8

CH B1

N – 8

CH B0

N – 7

CH B1

N – 7

CH B0

N – 6

.

CHANNEL B

D10±/D11±

CH B10 CH B11

N – 10 N – 10

CH B10 CH B11 CH B10 CH B11

N – 9 N – 9 N – 8 N – 8

CH B10 CH B11 CH B10

N – 7 N – 7 N – 6

(MSB)

Figure 2. Interleaved LVDS Mode Data Output Timing

CLK+

SYNC

t_SSYNC

t_HSYNC

Figure 3. SYNC Timing Inputs

Rev. C | Page 10 of 36

Data Sheet

AD9613

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the

printed circuit board (PCB) increases the reliability of the

solder joints, maximizing the thermal capability of the package.

Parameter

Rating

Electrical

AVDD to AGND

DRVDD to AGND

−0.3 V to +2.0 V

VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V

Typical θ_JAis specified for a 4-layer PCB with solid ground

plane. As shown in Figure 40, airflow increases heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes reduces the θ_JA.

CLK+, CLK− to AGND

SYNC to AGND

VCM to AGND

−0.3 V to AVDD + 0.2 V

−0.3 V to DRVDD + 0.3 V

CSB to AGND

SCLK to AGND

SDIO to AGND

OEB to AGND

PDWN to AGND

OR+/OR− to AGND

Table 7. Thermal Resistance

Airflow

Velocity

(m/sec)

1, 2

1, 3

1, 4

Package Type

θ_JA

θ_JC

θ_JB

10.±

Unit

°C/W

6±-Lead LFCSP

9 mm × 9 mm

(CP-6±-±)

0

26.8 1.1±

21.6

D0−/D0+ Through D11−/D11+ to

AGND

1.0

DCO+/DCO− to AGND

Environmental

−0.3 V to DRVDD + 0.3 V

2.0

20.2

¹Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³Per MIL-Std 883, Method 1012.1.

Operating Temperature Range

(Ambient)

Maximum Junction Temperature

Under Bias

−±0°C to +85°C

150°C

^±Per JEDEC JESD51-8 (still air).

Storage Temperature Range

(Ambient)

−65°C to +125°C

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. C | Page 11 of 36

AD9613

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

CLK+

CLK–

SYNC

DNC

1

2

3

4

5

6

7

8

9

48 PDWN

47 OEB

46 CSB

45 SCLK

44 SDIO

43 OR+

AD9613

PARALLEL LVDS

TOP VIEW

42 OR–

41 D11+ (MSB)

40 D11– (MSB)

39 D10+

38 D10–

37 DRVDD

36 D9+

(Not to Scale)

DRVDD 10

DNC 11

DNC 12

D0– (LSB) 13

D0+ (LSB) 14

D1– 15

35 D9–

34 D8+

D1+ 16

33 D8–

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE

MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 4. Pin Configuration (Top View) for the LFCSP Interleaved Parallel LVDS Mode

Table 8. Pin Function Descriptions for the LFCSP Interleaved Parallel LVDS Mode

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

0

AGND,

Exposed Paddle

Ground

Analog Ground. The exposed thermal paddle on the bottom of the

package provides the analog ground for the part. This exposed paddle

must be connected to ground for proper operation.

4 to 9, 11, 12, 55, 56, 58

DNC

Do not connect. Do not connect to these pins.

Digital Output Driver Supply (1.8 V Nominal).

Analog Power Supply (1.8 V Nominal).

10, 19, 28, 37

DRVDD

AVDD

Supply

49, 50, 53, 54, 59, 60, 63, 64

ADC Analog

1

2

51

52

57

CLK+

CLK−

VIN+A

VIN−A

VCM

Input

Output

ADC Clock Input—True.

ADC Clock Input—Complement.

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Common-Mode Level Bias Output for Analog Inputs. This pin should

be decoupled to ground using a 0.1 μF capacitor.

61

62

VIN−B

VIN+B

Input

Differential Analog Input Pin (−) for Channel B.

Differential Analog Input Pin (+) for Channel B.

Digital Input

3

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Rev. C | Page 12 of 36

Data Sheet

AD9613

Pin No.

Mnemonic

Type

Description

Digital Outputs

1±

13

16

15

18

17

21

20

23

22

27

26

30

29

32

31

3±

33

36

35

39

38

±1

±0

±3

D0+ (LSB)

D0− (LSB)

D1+

D1−

D2+

D2−

D3+

D3−

D±+

D±−

D5+

D5−

D6+

D6−

D7+

D7−

D8+

Output

Channel A/Channel B LVDS Output Data 0—True.

Channel A/Channel B LVDS Output Data 0—Complement.

Channel A/Channel B LVDS Output Data 1—True.

Channel A/Channel B LVDS Output Data 1—Complement.

Channel A/Channel B LVDS Output Data 2—True.

Channel A/Channel B LVDS Output Data 2—Complement.

Channel A/Channel B LVDS Output Data 3—True.

Channel A/Channel B LVDS Output Data 3—Complement.

Channel A/Channel B LVDS Output Data ±—True.

Channel A/Channel B LVDS Output Data ±—Complement.

Channel A/Channel B LVDS Output Data 5—True.

Channel A/Channel B LVDS Output Data 5—Complement.

Channel A/Channel B LVDS Output Data 6—True.

Channel A/Channel B LVDS Output Data 6—Complement.

Channel A/Channel B LVDS Output Data 7—True.

Channel A/Channel B LVDS Output Data 7—Complement.

Channel A/Channel B LVDS Output Data 8—True.

Channel A/Channel B LVDS Output Data 8—Complement.

Channel A/Channel B LVDS Output Data 9—True.

Channel A/Channel B LVDS Output Data 9—Complement.

Channel A/Channel B LVDS Output Data 10—True.

D8−

D9+

D9−

D10+

D10−

D11+ (MSB)

D11− (MSB)

OR+

OR−

DCO+

DCO−

Channel A/Channel B LVDS Output Data 10—Complement.

Channel A/Channel B LVDS Output Data 11—True.

Channel A/Channel B LVDS Output Data 11—Complement.

Channel A/Channel B LVDS Overrange—True.

Channel A/Channel B LVDS Overrange—Complement.

Channel A/Channel B LVDS Data Clock Output—True.

Channel A/Channel B LVDS Data Clock Output—Complement.

±2

25

2±

SPI Control

±5

±±

SCLK

SDIO

CSB

Input

SPI Serial Clock.

Input/Output SPI Serial Data I/O.

Input

±6

SPI Chip Select (Active Low).

Output Enable Bar and

Power-Down

±7

±8

OEB

PDWN

Input/Output Output Enable Bar Input (Active Low).

Input/Output Power-Down Input (Active High). Operation depends upon SPI mode;

this input can be configured as power-down or standby. For further

description, refer to Table 1±.

Rev. C | Page 13 of 36

AD9613

Data Sheet

PIN 1

INDICATOR

CLK+

CLK–

SYNC

DNC

1

2

3

4

5

6

7

8

9

48 PDWN

47 OEB

46 CSB

45 SCLK

44 SDIO

43 ORA+

42 ORA–

41 A D10+/D11+ (MSB)

40 A D10–/D11– (MSB)

39 A D8+/D9+

38 A D8–/D9–

37 DRVDD

36 A D6+/D7+

35 A D6–/D7–

34 A D4+/D5+

33 A D4–/D5–

DNC

AD9613

CHANNEL

MULTIPLEXED

(EVEN/ODD)

LVDS

ORB–

ORB+

DNC

DRVDD 10

B D0–/D1– (LSB) 11

B D0+/D1+ (LSB) 12

B D2–/D3– 13

TOP VIEW

(Not to Scale)

B D2+/D3+ 14

B D4–/D5– 15

B D4+/D5+ 16

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PADDLE ON THE BOTTOM OF THE PACKAGE PROVIDES THE

ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO

GROUND FOR PROPER OPERATION.

Figure 5. Pin Configuration (Top View) for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode

Table 9. Pin Function Descriptions for the LFCSP Channel Multiplexed (Even/Odd) LVDS Mode

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

10, 19, 28, 37

DRVDD

AVDD

DNC

Supply

Digital Output Driver Supply (1.8 V Nominal).

Analog Power Supply (1.8 V Nominal).

49, 50, 53, 54, 59, 60, 63, 64

4 to 9, 26, 27, 55, 56, 58

0

Do Not Connect. Do not connect to these pins.

AGND, Exposed

Paddle

Ground

The exposed thermal paddle on the bottom of the package provides

the analog ground for the part. This exposed paddle must be connected

to ground for proper operation.

ADC Analog

51

52

62

61

57

VIN+A

VIN−A

VIN+B

VIN−B

VCM

Input

Output

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Differential Analog Input Pin (+) for Channel B.

Differential Analog Input Pin (−) for Channel B.

Common-Mode Level Bias Output for Analog Inputs. This pin should be

decoupled to ground using a 0.1 μF capacitor.

1

2

CLK+

CLK−

Input

ADC Clock Input—True.

ADC Clock Input—Complement.

Digital Input

3

SYNC

Input

Digital Synchronization Pin. Slave mode only.

Digital Outputs

7

ORB+

ORB−

Output

Channel B LVDS Overrange Output—True. The overrange indication is

valid on the rising edge of the DCO.

Channel B LVDS Overrange Output—Complement. The overrange

indication is valid on the rising edge of the DCO.

6

Rev. C | Page 14 of 36

Data Sheet

AD9613

Pin No.

11

12

13

1±

15

16

17

18

20

21

22

23

29

30

31

32

33

3±

35

36

38

39

±0

±1

±3

Mnemonic

B D0−/D1− (LSB)

B D0+/D1+ (LSB)

B D2−/D3−

B D2+/D3+

B D±−/D5−

B D±+/D5+

B D6−/D7−

B D6+/D7+

B D8−/D9−

B D8+/D9+

B D10−/D11−

B D10+/D11+

Type

Description

Output

Channel B LVDS Output Data 1/Data 0—Complement.

Channel B LVDS Output Data 1/Data 0—True.

Channel B LVDS Output Data 3/Data 2—Complement.

Channel B LVDS Output Data 3/Data 2—True.

Channel B LVDS Output Data 5/Data ±—Complement.

Channel B LVDS Output Data 5/Data ±—True.

Channel B LVDS Output Data 7/Data 6—Complement.

Channel B LVDS Output Data 7/Data 6—True.

Channel B LVDS Output Data 9/Data 8—Complement.

Channel B LVDS Output Data 9/Data 8—True.

Channel B LVDS Output Data 11/Data 10—Complement.

Channel B LVDS Output Data 11/Data 10—True.

Channel A LVDS Output Data 1/Data 0—Complement.

Channel A LVDS Output Data 1/Data 0—True.

Channel A LVDS Output Data 3/Data 2—Complement.

Channel A LVDS Output Data 3/Data 2—True.

Channel A LVDS Output Data 5/Data ±—Complement.

Channel A LVDS Output Data 5/Data ±—True.

Channel A LVDS Output Data 7/Data 6—Complement.

Channel A LVDS Output Data 7/Data 6—True.

Channel A LVDS Output Data 9/Data 8—Complement.

Channel A LVDS Output Data 9/Data 8—True.

Channel A LVDS Output Data 11/Data 10—Complement.

Channel A LVDS Output Data 11/Data 10—True.

A D0−/D1− (LSB) Output

A D0+/D1+ (LSB) Output

A D2−/D3−

A D2+/D3+

A D±−/D5−

A D±+/D5+

A D6−/D7−

A D6+/D7+

A D8−/D9−

A D8+/D9+

A D10−/D11−

A D10+/D11+

ORA+

Output

Channel A LVDS Overrange Output—True. The overrange indication is

valid on the rising edge of the DCO.

±2

ORA−

Output

Channel A LVDS Overrange Output—Complement. The overrange

indication is valid on the rising edge of the DCO.

25

2±

DCO+

DCO−

Output

Channel A/Channel B LVDS Data Clock Output—True.

Channel A/Channel B LVDS Data Clock Output—Complement.

SPI Control

±5

±±

±6

SCLK

SDIO

CSB

Input

SPI Serial Clock.

Input/Output SPI Serial Data I/O.

Input

SPI Chip Select (Active Low).

Output Enable Bar and

Power-Down

±7

±8

OEB

PDWN

Input

Output Enable Bar Input (Active Low).

Power-Down Input (Active High). Operation depends upon SPI mode;

this input can be configured as power-down or standby. For further

description, refer to Table 1±.

Rev. C | Page 15 of 36

AD9613

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN =

−1.0 dBFS, 32k sample, T_A= 25°C, unless otherwise noted.

0

–20

–40

–60

120

170MSPS

90.1MHz @ –1dBFS

SNR = 69.7dB (70.7dBFS)

SFDR = 88dBc

SFDR (dBFS)

SNR (dBFS)

100

80

60

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

SFDR (dBc)

40

20

0

SNR (dBc)

–140

0

10

20

30

40

50

60

70

80

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 6. AD9613-170 Single-Tone FFT with f_IN= 90.1 MHz

Figure 9. AD9613-170 Single-Tone SNR/SFDR vs.

Input Amplitude (A_IN) with f_IN= 90.1 MHz

0

100

170MSPS

185.1MHz @ –1dBFS

SNR = 68.9dB (69.9dBFS)

SFDR = 80dBc

SFDR (dBc)

95

90

–20

–40

–60

85

80

75

70

65

60

THIRD HARMONIC

–80

–100

–120

SNR (dBFS)

–140

0

10

20

30

40

50

60

70

80

60 90 120 150 180 210 240 270 300 330 360 390

FREQUENCY (MHz)

Figure 7. AD9613-170 Single-Tone FFT with f_IN= 185.1 MHz

Figure 10. AD9613-170 Single-Tone SNR/SFDR vs. Input Frequency (f_IN)

0

170MSPS

305.1MHz @ –1dBFS

SNR = 67dB (68dBFS)

–20

SFDR = 79dBc

SFDR (dBc)

–40

SECOND HARMONIC

–60

IMD3 (dBc)

THIRD HARMONIC

–60

–80

–100

SFDR (dBFS)

–100

–120

–140

IMD3 (dBFS)

–120

–90.0

0

10

20

30

40

50

60

70

80

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 8. AD9613-170 Single-Tone FFT with f_IN= 305.1 MHz

Figure 11. AD9613-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

_IN1= 89.12, f_IN2= 92.12 MHz, f_S= 170 MSPS

f

Rev. C | Page 16 of 36

Data Sheet

AD9613

100

0

–20

–40

–60

–80

95

90

85

80

SFDR (dBc)

IMD3 (dBc)

SNR, CHANNEL B

SFDR, CHANNEL B

SNR, CHANNEL A

SFDR, CHANNEL A

75

70

65

SFDR (dBFS)

IMD3 (dBFS)

–100

–120

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

40 50 60 70 80 90 100 110 120 130 140 150 160 170

INPUT AMPLITUDE (dBFS)

SAMPLE RATE (MSPS)

Figure 12. AD9613-170 Two-Tone SFDR/IMD3 vs.

Input Amplitude (A_IN) with f_IN1= 184.12, f_IN2= 187.12 MHz, f_S= 170 MSPS

Figure 15. AD9613-170 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 90 MHz

0

16,000

170MSPS

89.12MHz @ –7dBFS

92.12MHz @ –7dBFS

0.38LSB rms

16,384 TOTAL HITS

14,000

–20

SFDR = 87dBc (94dBFS)

12,000

–40

10,000

8000

6000

4000

–60

–80

–100

–120

2000

0

–140

0

10

20

30

40

50

60

70

80

N – 1

N

N + 1

FREQUENCY (MHz)

OUTPUT CODE

Figure 13. AD9613-170 Two-Tone FFT with f_IN1= 89.12, f_IN2= 92.12 MHz,

f_S= 170 MSPS

Figure 16. AD9613-170 Grounded Input Histogram

0

–20

–40

–60

170MSPS

184.12MHz @ –7dBFS

187.12MHz @ –7dBFS

SFDR = 84dBc (91dBFS)

210MSPS

90.1MHz @ –1dBFS

SNR = 69.5dB (70.5dBFS)

SFDR = 88dBc

–20

–40

–60

THIRD HARMONIC

–80

–100

–120

–80

–100

–120

–140

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

90

100

FREQUENCY (MHz)

Figure 14. AD9613-170 Two-Tone FFT with f_IN1= 184.12, f_IN2= 187.12 MHz,

f_S= 170 MSPS

Figure 17. AD9613-210 Single-Tone FFT with f_IN= 90.1 MHz

Rev. C | Page 17 of 36

AD9613

Data Sheet

0

–20

–40

–60

100

95

210MSPS

185.1MHz @ –1dBFS

SNR = 68.5dB (69.5dBFS)

SFDR = 88dBc

SFDR (dBc)

90

85

80

75

70

65

60

THIRD HARMONIC

–80

–100

–120

SNR (dBFS)

–140

0

10

20

30

40

50

60

70

80

90

100

60 90 120 150 180 210 240 270 300 330 360 390

FREQUENCY (MHz)

Figure 18. AD9613-210 Single-Tone FFT with f_IN= 185.1 MHz

Figure 21. AD9613-210 Single-Tone SNR/SFDR vs. Input Frequency (f_IN

)

0

210MSPS

305.1MHz @ –1dBFS

SNR = 66.5dB (67.5dBFS)

–20

SFDR = 75dBc

SFDR (dBc)

–40

THIRD HARMONIC

–60

IMD3 (dBc)

–60

SECOND HARMONIC

–80

–100

–120

–140

SFDR (dBFS)

–100

IMD3 (dBFS)

–120

–90.0

0

10

20

30

40

50

60

70

80

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

90

100

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 19. AD9613-210 Single-Tone FFT with f_IN= 305.1 MHz

Figure 22. AD9613-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

f

_IN1= 89.12 , f_IN2= 92.12 MHz, f_S= 210 MSPS

120

0

–20

–40

–60

–80

SFDR (dBFS)

100

SFDR (dBc)

IMD3 (dBc)

80

SNR (dBFS)

60

SFDR (dBc)

40

SNR (dBc)

SFDR (dBFS)

IMD3 (dBFS)

–100

–120

20

0

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

INPUT AMPLITUDE (dBFS)

0

INPUT AMPLITUDE (dBFS)

Figure 20. AD9613-210 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN) with

Figure 23. AD9613-210 Two-Tone SFDR/IMD3 vs.

Input Amplitude (A_IN) with f_IN1= 184.12, f_IN2= 187.12 MHz, f_S= 210 MSPS

f

_IN= 90.1 MHz

Rev. C | Page 18 of 36

Data Sheet

AD9613

14,000

12,000

10,000

8000

0

210MSPS

0.437LSB rms

16,384 TOTAL HITS

89.12MHz @ –7dBFS

92.12MHz @ –7dBFS

SFDR = 90dBc (97dBFS)

–20

–40

–60

6000

–80

–100

–120

4000

2000

0

–140

0

10

20

30

40

50

60

70

80

N – 2 N – 1

N

N + 1

90

100

FREQUENCY (MHz)

OUTPUT CODE

Figure 27. AD9613-210 Grounded Input Histogram

Figure 24. AD9613-210 Two-Tone FFT with f_IN1= 89.12, f_IN2= 92.12 MHz,

f_S= 210 MSPS

0

–20

–40

–60

0

250MSPS

210MSPS

184.12MHz @ –7dBFS

187.12MHz @ –7dBFS

SFDR = 88dBc (95dBFS)

90.1MHz @ –1dBFS

SNR = 68.9dB (69.9dBFS)

SFDR = 88dBc

–20

–40

SECOND HARMONIC

THIRD HARMONIC

–60

–80

–100

–120

–80

–100

–120

–140

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

0

10

20

30

40

50

60

70

80

90

100

FREQUENCY (MHz)

Figure 28. AD9613-250 Single-Tone FFT with f_IN= 90.1 MHz

Figure 25. AD9613-210 Two-Tone FFT with f_IN1= 184.12, f_IN2= 187.12 MHz,

f_S= 210 MSPS

0

100

250MSPS

185.1MHz @ –1dBFS

SNR = 68.1dB (69.1dBFS)

–20

95

SFDR = 85dBc

–40

90

–60

85

THIRD HARMONIC

SNR, CHANNEL B

SECOND HARMONIC

SFDR, CHANNEL B

SNR, CHANNEL A

80

–80

SFDR, CHANNEL A

–100

75

–120

–140

70

65

40

60

80

100

120

140

160

180

200

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

SAMPLE RATE (MSPS)

Figure 26. AD9613-210 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 90 MHz

Figure 29. AD9613-250 Single-Tone FFT with f_IN= 185.1 MHz

Rev. C | Page 19 of 36

AD9613

Data Sheet

0

–20

–40

–60

0

–20

–40

–60

–80

250MSPS

305.1MHz @ –1dBFS

SNR = 66.5dB (67.5dBFS)

SFDR = 83dBc

SFDR (dBc)

IMD3 (dBc)

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

SFDR (dBFS)

IMD3 (dBFS)

–100

–120

–140

0

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 30. AD9613-250 Single-Tone FFT with f_IN= 305.1 MHz

Figure 33. AD9613-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

f

_IN1= 89.12, f_IN2= 92.12 MHz, f_S= 250 MSPS

120

0

–20

–40

–60

–80

SFDR (dBFS)

100

SFDR (dBc)

IMD3 (dBc)

80

SNR (dBFS)

60

SFDR (dBc)

40

SFDR (dBFS)

IMD3 (dBFS)

SNR (dBc)

20

–100

–120

0

–90.0

–78.5

–67.0

–55.5

–44.0

–32.5

–21.0

–7.0

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

INPUT AMPLITUDE (dBFS)

Figure 34. AD9613-250 Two-Tone SFDR/IMD3 vs.

Input Amplitude (A_IN) with f_IN1= 184.12, f_IN2= 187.12 MHz, f_S= 250 MSPS

Figure 31. AD9613-250 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN) with

f

_IN= 90.1 MHz

0

100

95

250MSPS

89.12MHz @ –7dBFS

92.12MHz @ –7dBFS

–20

SFDR = 86dBc (93dBFS)

SFDR (dBc)

90

85

80

75

70

65

60

–40

–60

–80

–100

–120

SNR (dBFS)

–140

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

60

80 100 120 140 160 180 200 220 240 260

FREQUENCY (MHz)

Figure 35. AD9613-250 Two-Tone FFT with f_IN1= 89.12, f_IN2= 92.12 MHz,

f_S= 250 MSPS

Figure 32. AD9613-250 Single-Tone SNR/SFDR vs. Input Frequency (f_IN

)

Rev. C | Page 20 of 36

Data Sheet

AD9613

16,000

14,000

12,000

0

250MSPS

184.12MHz @ –7dBFS

187.12MHz @ –7dBFS

SFDR = 86dBc (93dBFS)

0.39LSB rms

16,384 TOTAL HITS

–20

–40

–60

10,000

8000

6000

4000

–80

–100

–120

2000

0

–140

N – 1

N

N + 1

0

10 20 30 40 50 60 70 80 90 100 110 120

FREQUENCY (MHz)

OUTPUT CODE

Figure 38. AD9613-250 Grounded Input Histogram

Figure 36. AD9613-250 Two-Tone FFT with f_IN1= 184.12, f_IN2= 187.12 MHz,

f_S= 250 MSPS

100

95

90

85

SNR, CHANNEL B

SFDR, CHANNEL B

SNR, CHANNEL A

80

SFDR, CHANNEL A

75

70

65

40

60

80 100 120 140 160 180 200 220 240

SAMPLE RATE (MSPS)

Figure 37. AD9613-250 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 90.1 MHz

Rev. C | Page 21 of 36

AD9613

Data Sheet

EQUIVALENT CIRCUITS

AVDD

350Ω

26kΩ

SCLK

OR

PDWN

OR OEB

VIN

Figure 39. Equivalent Analog Input Circuit

Figure 43. Equivalent SCLK, PDWN, or OEB Input Circuit

AVDD

26kΩ

350Ω

0.9V

CSB

15kΩ

CLK+

CLK–

Figure 40. Equivalent Clock lnput Circuit

Figure 44. Equivalent CSB Input Circuit

DRVDD

AVDD

V+

V–

DATAOUT–

V–

DATAOUT+

V+

SYNC

0.9V

16kΩ

0.9V

Figure 41. Equivalent LVDS Output Circuit

Figure 45. Equivalent SYNC Input Circuit

DRVDD

350Ω

SDIO

26kΩ

Figure 42. Equivalent SDIO Circuit

.

Rev. C | Page 22 of 36

Data Sheet

AD9613

THEORY OF OPERATION

A small resistor in series with each input can help reduce the

The AD9613 has two analog input channels, two filter channels,

and two digital output channels. The intermediate frequency (IF)

input signal passes through several stages before appearing at the

output port(s) as a filtered, and optionally, decimated digital signal.

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC input; therefore,

the precise values are dependent on the application.

The dual ADC design can be used for diversity reception of signals,

where the ADCs operate identically on the same carrier but from

two separate antennae. The ADCs can also be operated with

independent analog inputs. The user can sample frequencies

from dc to 300 MHz using appropriate low-pass or band-pass

filtering at the ADC inputs with little loss in ADC performance.

Operation to 400 MHz analog input is permitted but occurs at

the expense of increased ADC noise and distortion.

In intermediate frequency (IF) undersampling applications, the

shunt capacitors should be reduced. In combination with the

driving source impedance, the shunt capacitors limit the input

bandwidth. Refer to the AN-742 Application Note, Frequency

Domain Response of Switched-Capacitor ADCs; the AN-827

Application Note, A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs; and the Analog Dialogue article,

“Transformer-Coupled Front-End for Wideband A/D Converters,”

for more information on this subject.

Synchronization capability is provided to allow synchronized

timing between multiple devices.

BIAS

Programming and control of the AD9613 are accomplished

using a 3-pin, SPI-compatible serial interface.

S

C

FB

S

ADC ARCHITECTURE

VIN+

VIN–

The AD9613 architecture consists of a dual front-end sample-

and-hold circuit, followed by a pipelined, switched-capacitor

ADC. The quantized outputs from each stage are combined into

a final 12-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate on a new input

sample and the remaining stages to operate on the preceding

samples. Sampling occurs on the rising edge of the clock.

C

PAR1

PAR2

H

S

C

S

C

FB

C

PAR1

PAR2

S

BIAS

Figure 46. Switched-Capacitor Input

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The MDAC magnifies the difference between the

reconstructed DAC output and the flash input for the next stage

in the pipeline. One bit of redundancy is used in each stage to

facilitate digital correction of flash errors. The last stage simply

consists of a flash ADC.

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched, and the inputs should be

differentially balanced.

Input Common Mode

The analog inputs of the AD9613 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that V_CM= 0.5 × AVDD (or

0.9 V) is recommended for optimum performance. An on-board

common-mode voltage reference is included in the design and

is available from the VCM pin. Using the VCM output to set the

input common mode is recommended. Optimum performance

is achieved when the common-mode voltage of the analog input

is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM

pin must be decoupled to ground by a 0.1 µF capacitor, as described

in the Applications Information section. Place this decoupling

capacitor close to the pin to minimize the series resistance and

inductance between the part and this capacitor.

The input stage of each channel contains a differential sampling

circuit that can be ac- or dc-coupled in differential or single-ended

modes. The output staging block aligns the data, corrects errors,

and passes the data to the output buffers. The output buffers are

powered from a separate supply, allowing digital output noise to be

separated from the analog core. During power-down, the output

buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9613 is a differential switched-capacitor

circuit that has been designed for optimum performance while

processing a differential input signal.

The clock signal alternatively switches the input between sample

mode and hold mode (see the configuration shown in Figure 46).

When the input is switched into sample mode, the signal source

must be capable of charging the sampling capacitors and settling

within 1/2 clock cycle.

Rev. C | Page 23 of 36

AD9613

Data Sheet

Differential Input Configurations

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz. Excessive signal power can also cause

core saturation, which leads to distortion.

Optimum performance is achieved while driving the AD9613

in a differential input configuration. For baseband applications, the

AD8138, ADA4937-2, ADA4938-2, and ADA4930-2 differential

drivers provide excellent performance and a flexible interface to

the ADC.

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9613. For applications where

SNR is a key parameter, differential double balun coupling is

the recommended input configuration (see Figure 49). In this

configuration, the input is ac-coupled, and the CML is provided

to each input through a 33 Ω resistor. These resistors compensate

for losses in the input baluns to provide a 50 Ω impedance to

the driver.

The output common-mode voltage of the ADA4930-2 is easily

set with the VCM pin of the AD9613 (see Figure 47), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

15pF

200Ω

33Ω

5pF

15Ω

90Ω

VIN–

VIN+

AVDD

76.8Ω

VIN

In the double balun and transformer configurations, the value

of the input capacitors and resistors is dependent on the input

frequency and source impedance. Based on these parameters,

the value of the input resistors and capacitors may need to be

adjusted or some components may need to be removed. Table 10

displays recommended values to set the RC network for different

input frequency ranges. However, these values are dependent

on the input signal and bandwidth and should be used only as

a starting guide. Note that the values given in Table 10 are for

each R1, R2, C2, and R3 component shown in Figure 48 and

Figure 49.

ADC

ADA4930-2

0.1µF

33Ω

15pF

15Ω

VCM

120Ω

200Ω

33Ω

0.1µF

Figure 47. Differential Input Configuration Using the ADA4938-2

For baseband applications where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 48. To bias the

analog input, the VCM voltage can be connected to the center

tap of the secondary winding of the transformer.

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use an amplifier with variable

gain. The AD8375 or AD8376 digital variable gain amplifier

(DVGAs) provides good performance for driving the AD9613.

Figure 50 shows an example of the AD8376 driving the AD9613

through a band-pass antialiasing filter.

C2

R3

R2

VIN+

R1

2V p-p

49.9Ω

C1

R1

ADC

R2

VCM

VIN–

33Ω

R3

0.1µF

C2

Figure 48. Differential Transformer-Coupled Configuration

Table 10. Example RC Network

Frequency Range (MHz)

0 to 100

R1 Series (Ω)

C1 Differential (pF)

R2 Series (Ω)

C2 Shunt (pF)

R3 Shunt (Ω)

±9.9

33

15

8.2

3.9

0

15

8.2

100 to 300

C2

R3

0.1µF

R1

R2

VIN+

2V p-p

33Ω

P

S

P

C1

R1

ADC

A

0.1µF

33Ω

0.1µF

VCM

VIN–

33Ω

R3

0.1µF

C2

Figure 49. Differential Double Balun Input Configuration

Rev. C | Page 2± of 36

Data Sheet

AD9613

1000pF 180nH 220nH

1µH

165Ω

VPOS

15pF

AD9613

AD8376

5.1pF 3.9pF

301Ω

VCM

1nF

2.5kΩ║2pF

165Ω

1nF

1µH

68nH

180nH 220nH

1000pF

NOTES

1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS

WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).

2. FILTER VALUES SHOWN FOR A 20MHz BANDWIDTH FILTER

CENTERED AT 140MHz.

Figure 50. Differential Input Configuration Using the AD8376 (Filter Values Shown for a 20 MHz Bandwidth Filter Centered at 140 MHz)

the clock from feeding through to other portions of the AD9613,

while preserving the fast rise and fall times of the signal, which are

critical to low jitter performance.

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9613.

The full-scale input range can be adjusted by varying the reference

voltage via SPI. The input span of the ADC tracks reference

voltage changes linearly.

®

Mini-Circuits

ADT1-1WT, 1:1Z

ADC

390pF

XFMR

CLOCK

INPUT

CLOCK INPUT CONSIDERATIONS

CLK+

CLK–

100Ω

50Ω

For optimum performance, the AD9613 sample clock inputs,

CLK+ and CLK−, should be clocked with a differential signal. The

signal is typically ac-coupled into the CLK+ and CLK− pins via

a transformer or via capacitors. These pins are biased internally

(see Figure 51) and require no external bias. If the inputs are

floated, the CLK− pin is pulled low to prevent spurious clocking.

AVDD

390pF

SCHOTTKY

DIODES: HSMS2822

Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz)

25Ω

ADC

390pF

CLOCK

INPUT

CLK+

0.9V

CLK–

SCHOTTKY

DIODES:

HSMS2822

25Ω

CLK+

CLK–

Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)

4pF

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins, as shown in Figure 54. The AD9510, AD9511, AD9512,

AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,

AD9522, AD9523, AD9524, and ADCLK905/ADCLK907/

ADCLK925 clock drivers offer excellent jitter performance.

Figure 51. Simplified Equivalent Clock Input Circuit

Clock Input Options

The AD9613 has a very flexible clock input structure. Clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter

is of the most concern, as described in the Jitter Considerations

section.

ADC

0.1µF

CLOCK

INPUT

CLK+

AD95xx

100Ω

Figure 52 and Figure 53 show two preferable methods for clocking

the AD9613 (at clock rates of up to 625 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using an RF balun or RF transformer.

PECL DRIVER

0.1µF

CLOCK

INPUT

CLK–

240Ω

50kΩ

Figure 54. Differential PECL Sample Clock (Up to 625 MHz)

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 625 MHz, and the RF transformer is

recommended for clock frequencies from 10 MHz to 200 MHz.

The back-to-back Schottky diodes across the transformer secondary

limit clock excursions into the AD9613 to approximately 0.8 V p-p

differential. This limit helps prevent the large voltage swings of

Rev. C | Page 25 of 36

AD9613

Data Sheet

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 55. The AD9510,

AD9511, AD9512, AD9513, AD9514, AD9515, AD9516, AD9517,

AD9518, AD9520, AD9522, AD9523, and AD9524 clock drivers

offer excellent jitter performance.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input frequency

(f_IN) due to jitter (t_J) can be calculated by

SNR_HF= −10 log[(2π × f_IN× t_JRMS)²+ 10 ^{(/SNR /10)}

]

LF

In the equation, the rms aperture jitter represents the root-

mean-square of all jitter sources, which include the clock input,

the analog input signal, and the ADC aperture jitter specification.

IF undersampling applications are particularly sensitive to jitter,

as shown in Figure 56.

ADC

CLK+

0.1µF

CLOCK

INPUT

AD95xx

LVDS DRIVER

100Ω

0.1µF

CLOCK

INPUT

CLK–

50kΩ

80

Figure 55. Differential LVDS Sample Clock (Up to 625 MHz)

75

70

65

Input Clock Divider

The AD9613 contains an input clock divider with the ability to

divide the input clock by integer values between 1 and 8. The

duty cycle stabilizer (DCS) is enabled by default on power-up.

The AD9613 clock divider can be synchronized using the external

SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock

divider to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

causes the clock divider to reset to its initial state. This synchro-

nization feature allows multiple parts to have their clock dividers

aligned to guarantee simultaneous input sampling.

60

55

50

0.05ps

0.2ps

0.5ps

1ps

1.5ps

MEASURED

1

10

100

1000

INPUT FREQUENCY (MHz)

Figure 56. AD9613-250 SNR vs. Input Frequency and Jitter

Clock Duty Cycle

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9613.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, may be sensitive to

clock duty cycle. Commonly, a 5% tolerance is required on the

clock duty cycle to maintain dynamic performance characteristics.

The AD9613 contains a duty-cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows the user to

provide a wide range of clock input duty cycles without affecting

the performance of the AD9613.

Refer to the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance, and the AN-756 Application Note,

Sample Systems and the Effects of Clock Phase Noise and Jitter,

for more information about jitter performance as it relates to

ADCs.

Jitter on the rising edge of the input clock is still of paramount

concern and is not reduced by the duty cycle stabilizer. The

duty cycle control loop does not function for clock rates less

than 40 MHz nominally. The loop has a time constant associated

with it that must be considered when the clock rate can change

dynamically. A wait time of 1.5 µs to 5 µs is required after a

dynamic clock frequency increase or decrease before the DCS

loop is relocked to the input signal. During the period that the

loop is not locked, the DCS loop is bypassed, and internal

device timing is dependent on the duty cycle of the input clock

signal. In such applications, it may be appropriate to disable the

duty cycle stabilizer. In all other applications, enabling the DCS

circuit is recommended to maximize ac performance.

Rev. C | Page 26 of 36

Data Sheet

AD9613

POWER DISSIPATION AND STANDBY MODE

DIGITAL OUTPUTS

As shown in Figure 57, the power dissipated by the AD9613 is

proportional to its sample rate. The data in Figure 57 was taken

using the same operating conditions as those used for the Typical

Performance Characteristics section.

The AD9613 output drivers can be configured for either ANSI

LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.

As detailed in Application Note AN-877, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI

control.

0.8

0.5

0.4

0.3

0.2

0.7

0.6

0.5

0.4

0.3

TOTAL POWER

Digital Output Enable Function (OEB)

The AD9613 has a flexible three-state ability for the digital output

pins. The three-state mode is enabled using the OEB pin or

through the SPI interface. If the OEB pin is low, the output data

drivers are enabled. If the OEB pin is high, the output data drivers

are placed in a high impedance state. This OEB function is not

intended for rapid access to the data bus. Note that OEB is

referenced to the digital output driver supply (DRVDD) and

should not exceed that supply voltage.

I

AVDD

I

DRVDD

0.2

0.1

0

0.1

0

When using the SPI interface, the data outputs of each channel

can be independently three-stated by using the output enable bar

bit (Bit 4) in Register 0x14. Because the output data is interleaved,

if only one of the two channels is disabled, the output data of

the remaining channel is repeated in both the rising and falling

output clock cycles.

40

60

80 100 120 140 160 180 200 220 240

ENCODE FREQUENCY (MSPS)

Figure 57. AD9613-250 Power and Current vs. Sample Rate

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9613 is placed in power-down mode.

In this state, the ADC typically dissipates 10 mW. During power-

down, the output drivers are placed in a high impedance state.

Asserting the PDWN pin low returns the AD9613 to its normal

operating mode. Note that PDWN is referenced to the digital

output driver supply (DRVDD) and should not exceed that

supply voltage.

Timing

The AD9613 provides latched data with a pipeline delay of 10 input

sample clock cycles. Data outputs are available one propagation

delay (t_PD) after the rising edge of the clock signal.

Minimize the length of the output data lines and loads placed

on them to reduce transients within the AD9613. These

transients can degrade converter dynamic performance.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, wake-up time is related to the

time spent in power-down mode, and shorter power-down

cycles result in proportionally shorter wake-up times.

The lowest typical conversion rate of the AD9613 is 40 MSPS. At

clock rates below 40 MSPS, dynamic performance can degrade.

Data Clock Output (DCO)

The AD9613 also provides data clock output (DCO) intended for

capturing the data in an external register. Figure 2 shows a timing

diagram of the AD9613 output modes.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map Register

Description section and the AN-877 Application Note,

ADC OVERRANGE (OR)

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipeline and, therefore, is

subject to a latency of 10 ADC clock. An overrange at the input is

indicated by this bit 10 clock cycles after it.

Interfacing to High Speed ADCs via SPI, for additional details.

Table 11. Output Data Format

VIN+ − VIN−,

Input Span = 1.75 V p-p (V)

Input (V)

Offset Binary Output Mode

0000 0000 0000

1000 0000 0000

1111 1111 1111

Twos Complement Mode (Default)

1000 0000 0000

0000 0000 0000

0111 1111 1111

OR

1

0

VIN+ − VIN–

Less than –0.875

–0.875

0

+0.875

Greater than +0.875

1111 1111 1111

0111 1111 1111

1

Rev. C | Page 27 of 36

AD9613

Data Sheet

CHANNEL/CHIP SYNCHRONIZATION

The AD9613 has a SYNC input that allows the user flexible

synchronization options for synchronizing the internal blocks.

The sync feature is useful for guaranteeing synchronized operation

across multiple ADCs. The input clock divider can be synchronized

using the SYNC input. The divider can be enabled to synchronize

on a single occurrence of the SYNC signal or on every occurrence

by setting the appropriate bits in Register 0x3A.

The SYNC input is internally synchronized to the sample clock.

However, to ensure that there is no timing uncertainty between

multiple parts, the SYNC input signal should be synchronized

to the input clock signal. The SYNC input should be driven

using a single-ended CMOS type signal.

Rev. C | Page 28 of 36

Data Sheet

AD9613

SERIAL PORT INTERFACE (SPI)

The AD9613 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. The SPI gives the user added

flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that can

be further divided into fields. These fields are documented in the

Memory Map section. For detailed operational information, see

the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI.

All data is composed of 8-bit words. The first bit of each individual

byte of serial data indicates whether a read or write command is

issued. This allows the serial data input/output (SDIO) pin to

change direction from an input to an output.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an output

at the appropriate point in the serial frame.

CONFIGURATION USING THE SPI

Data can be sent in MSB-first mode or in LSB-first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

Three pins define the SPI of this ADC: the SCLK pin, the SDIO

pin, and the CSB pin (see Table 12). The SCLK (serial clock) pin

is used to synchronize the read and write data presented from/to

the ADC. The SDIO (serial data input/output) pin is a dual-

purpose pin that allows data to be sent and read from the internal

ADC memory map registers. The CSB (chip select bar) pin is an

active-low control that enables or disables the read and write cycles.

HARDWARE INTERFACE

The pins described in Table 12 comprise the physical interface

between the user programming device and the serial port of the

AD9613. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

Table 12. Serial Port Interface Pins

Function

SCLK Serial Clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial Data Input/Output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note,

CSB

Chip Select Bar. An active-low control that gates the read

and write cycles.

Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 58 and

Table 5.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used for

other devices, it may be necessary to provide buffers between this

bus and the AD9613 to prevent these signals from transitioning

at the converter inputs during critical sampling periods.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes

to allow for additional external timing. When CSB is tied high,

SPI functions are placed in a high impedance mode. This mode

turns on any SPI pin secondary functions.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase and its length is determined

by the W0 and W1 bits.

Rev. C | Page 29 of 36

AD9613

Data Sheet

SPI ACCESSIBLE FEATURES

Table 13 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9613 part-specific features are described in the

Memory Map Register Description section.

Table 13. Features Accessible Using the SPI

Feature Name

Description

Mode

Clock

Offset

Test I/O

Output Mode

Output Phase

Output Delay

VREF

Allows the user to set either power-down mode or standby mode

Allows the user to access the DCS via the SPI

Allows the user to digitally adjust the converter offset

Allows the user to set test modes to have known data on output bits

Allows the user to set up outputs

Allows the user to set the output clock polarity

Allows the user to vary the DCO delay

Allows the user to set the reference voltage

Allows the user to enable the synchronization features

Digital Processing

t_HIGH

t_DS

t_CLK

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 58. Serial Port Interface Timing Diagram

Rev. C | Page 30 of 36

Data Sheet

AD9613

MEMORY MAP

Logic Levels

READING THE MEMORY MAP REGISTER TABLE

An explanation of logic level terminology follows:

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into four sections: the chip

configuration registers (Address 0x00 to Address 0x02); the

channel index and transfer registers (Address 0x05 and

Address 0xFF); and the ADC functions registers, including

setup, control, and test (Address 0x08 to Address 0x3A).

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

The memory map register table (see Table 14) documents the

default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x14, the output

mode register, has a hexadecimal default value of 0x05. This

means that Bit 0 = 1 and Bit 2 = 1, and the remaining bits are

0s. This setting is the default output format value, which is twos

complement. For more information on this function and others,

see the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. This document details the functions controlled by

Register 0x00 to Register 0x20. The remaining register, Register

0x3A, is documented in the Memory Map Register Description

section.

Address 0x08 to Address 0x20 and Address 0x3A are shadowed.

Writes to these addresses do not affect part operation until a

transfer command is issued by writing 0x01 to Address 0xFF,

setting the transfer bit. This allows these registers to be updated

internally and simultaneously when the transfer bit is set. The

internal update takes place when the transfer bit is set and the

bit autoclears.

Channel Specific Registers

Some channel setup functions, such as the signal monitor

thresholds, can be programmed to a different value for each

channel. In these cases, channel address locations are internally

duplicated for each channel. These registers and bits are designated

in Table 14 as local. These local registers and bits can be accessed

by setting the appropriate Channel A or Channel B bits in Register

0x05. If both bits are set, the subsequent write affects the registers

of both channels. In a read cycle, only Channel A or Channel B

should be set to read one of the two registers. If both bits are set

during an SPI read cycle, the part returns the value for Channel A.

Registers and bits designated as global in Table 14 affect the entire

part and the channel features for which independent settings are

not allowed between channels. The settings in Register 0x05 do

not affect the global registers and bits.

Open and Reserved Locations

All address and bit locations that are not included in Table 14

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), this address location should

not be written.

Default Values

After the AD9613 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table (see Table 14).

Rev. C | Page 31 of 36

AD9613

Data Sheet

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 14 are not currently supported for this device.

Table 14. Memory Map Registers

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

0x00

SPI port

0

LSB first

Soft reset

1

Soft reset

LSB first

0

0x18

The nibbles

are mirrored

so that LSB-

first mode

or MSB-first

mode

configuration

(global)¹

registers

correctly,

regardless

of shift

mode

0x01

0x02

Chip ID

(global)

8-bit chip ID[7:0] (AD9613 = 0x83)

(default)

0x83

Read only

Chip grade

(global)

Open

Speed grade ID

00 = 250 MSPS

Open

Speed

grade ID

used to

differentiate

devices;

read only

01 = 210 MSPS

11 = 170 MSPS

Channel Index and Transfer Registers

0x05

Channel index Open

(global)

Open

ADC B

(default)

ADC A

(default)

0x03

Bits are set

to

determine

which

device on

the chip

receives the

next write

command;

applies to

local

registers

only

0xFF

Transfer

(global)

Open

Transfer

0x00

Synchron-

ously

transfers

data from

the master

shift register

to the slave

ADC Functions

0x08

Power modes

(local)

External

power-

down pin

function

(local)

0 = power-

down

1 = standby

Open

Internal power-down mode

(local)

00 = normal operation

01 = full power-down

10 = standby

Determines

various

generic

modes of

chip

operation

11 = reserved

0x09

0x0B

Global clock

(global)

Open

Duty cycle

stabilizer

(default)

0x01

0x00

Clock divide

(global)

Input clock divider phase adjust

000 = no delay

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by ±

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

Clock divide

values other

than 000

auto-

matically

cause the

duty cycle

stabilizer to

become

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = ± input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

active

Rev. C | Page 32 of 36

Data Sheet

AD9613

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x0D

Test mode

(local)

User test

mode

control

Open

Reset PN

long gen

Reset PN

short gen

Output test mode

0000 = off (default)

0001 = midscale short

0010 = positive FS

0011 = negative FS

0x00

When this

register is

set, the test

data is

placed on

the output

pins in

0 =

continuou

s/repeat

pattern

1 = single

pattern,

then 0s

0100 = alternating checkerboard

0101 = PN long sequence

0110 = PN short sequence

0111 = one/zero word toggle

1000 = user test mode

place of

normal data

1001 to 1110 = unused

1111 = ramp output

0x10

0x1±

Offset adjust

(local)

Open

Offset adjust in LSBs from +31 to −32

(twos complement format)

0x00

0x05

Output mode

Open

Output

enable bar

(local)

Open

Output invert

(local)

1 = normal

(default)

Output format

00 = offset binary

01 = twos complement

(default)

Configures

the outputs

and the

format of

the data

0 = inverted

10 = gray code

11 = reserved

(local)

0x15

Output Adjust

(Global)

Open

LVDS output drive current adjust

0000 = 3.72 mA output drive current

0001 = 3.5 mA output drive current (default)

0010 = 3.30 mA output drive current

0011 = 2.96 mA output drive current

0100 = 2.82 mA output drive current

0101 = 2.57 mA output drive current

0110 = 2.27 mA output drive current

0x01

0111 = 2.0 mA output drive current (reduced range)

1000 – 1111 = reserved

0x16

Clock phase

control

(global)

Invert

DCO clock

Open

0x00

Odd/Even

Mode

Output

Enable

0 =

disabled

1 =

enabled

0x17

0x18

DCO output

delay (global)

Enable

DCO

clock

Open

DCO clock delay

[delay = (3100 ps × register value/31 +100)]

00000 = 100 ps

0x00

delay

00001 = 200 ps

00010 = 300 ps

…

11110 = 3100 ps

11111 = 3200 ps

Input span

select (global)

Open

Full-scale input voltage selection

01111 = 2.087 V p-p

…

00001 = 1.772 V p-p

00000 = 1.75 V p-p (default)

11111 = 1.727 V p-p

…

Full-scale

input

adjustment

in 0.022 V

steps

10000 = 1.383 V p-p

0x19

0x1A

0x1B

0x1C

0x1D

User Test

Pattern 1 LSB

(global)

User Test Pattern 1[7:0]

User Test Pattern 1[15:8]

User Test Pattern 2[7:0]

User Test Pattern 2[15:8]

User Test Pattern 3[7:0]

0x00

User Test

Pattern 1 MSB

(global)

User Test

Pattern 2 LSB

(global)

User Test

Pattern 2 MSB

(global)

0x00

User Test

Pattern 3 LSB

(global)

Rev. C | Page 33 of 36

AD9613

Data Sheet

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x1E

0x1F

0x3A

User Test

Pattern 3 MSB

(global)

User Test Pattern 3[15:8]

0x00

User Test

Pattern ± LSB

(global)

User Test Pattern ±[7:0]

0x00

Sync control

(global)

Open

Clock

divider

sync

Master sync

buffer enable

divider

next sync

only

enable

¹The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00.

it receives and to ignore the rest. The clock divider sync enable

bit (Address 0x3A, Bit 1) resets after it syncs.

MEMORY MAP REGISTER DESCRIPTION

For more information on functions controlled in Register 0x00

to Register 0x20, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

Sync Control (Register 0x3A)

Bits[7:3]—Reserved

Bit 0—Master Sync Buffer Enable

Bit 2—Clock Divider Next Sync Only

Bit 0 must be set high to enable any of the sync functions. If

the sync capability is not used, this bit should remain low to

conserve power.

If the master sync buffer enable bit (Address 0x3A, Bit 0) and

the clock divider sync enable bit (Address 0x3A, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse that

Rev. C | Page 3± of 36

Data Sheet

AD9613

APPLICATIONS INFORMATION

DESIGN GUIDELINES

To maximize the coverage and adhesion between the ADC

and the PCB, a silkscreen should be overlaid to partition the

continuous plane on the PCB into several uniform sections.

This provides several tie points between the ADC and the PCB

during the reflow process. Using one continuous plane with no

partitions guarantees only one tie point between the ADC and

the PCB. See the evaluation board for a PCB layout example.

For detailed information about the packaging and PCB layout

of chip-scale packages, refer to the AN-772 Application Note, A

Design and Manufacturing Guide for the Lead Frame Chip Scale

Package (LFCSP).

Before starting system-level design and layout of the AD9613,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9613, it is recommended

that two separate 1.8 V supplies be used: one supply should be

used for analog (AVDD), and a separate supply should be used

for the digital outputs (DRVDD). The designer can employ

several different decoupling capacitors to cover both high and

low frequencies. These capacitors should be located close to the

point of entry at the PC board level and close to the pins of the

part with minimal trace length.

VCM

The VCM pin should be decoupled to ground with a 0.1 µF

capacitor, as shown in Figure 48. For optimal channel-to-channel

isolation, a 33 Ω resistor should be included between the AD9613

VCM pin and the Channel A analog input network connection,

as well as between the AD9613 VCM pin and the Channel B

analog input network connection.

A single PCB ground plane should be sufficient when using the

AD9613. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

SPI Port

Exposed Paddle Thermal Heat Slug Recommendations

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9613 to keep these signals from transitioning at the converter

input pins during critical sampling periods.

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. A continuous, exposed

(no solder mask) copper plane on the PCB should mate to the

AD9613 exposed paddle, Pin 0.

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged with

nonconductive epoxy.

Rev. C | Page 35 of 36

AD9613

Data Sheet

OUTLINE DIMENSIONS

9.10

9.00 SQ

8.90

0.30

0.25

0.18

0.60 MAX

0.60

MAX

PIN 1

INDICATOR

1

49

48

64

PIN 1

INDICATOR

8.85

8.75 SQ

8.65

0.50

BSC

EXPOSED

PAD

6.35

6.20 SQ

6.05

0.50

0.40

0.30

33

32

16

17

0.25 MIN

BOTTOM VIEW

7.50 REF

TOP VIEW

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SEATING

PLANE

0.20 REF

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-6±-±

AD9613BCPZ-170

AD9613BCPZ-210

AD9613BCPZ-250

AD9613BCPZRL7-170

AD9613BCPZRL7-210

AD9613BCPZRL7-250

AD9613-170EBZ

AD9613-210EBZ

AD9613-250EBZ

−±0°C to +85°C

6±-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 170 MSPS

6±-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 210 MSPS

6±-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 MSPS

6±-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 170 MSPS

6±-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 210 MSPS

6±-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 MSPS

Evaluation Board with AD9613, 170 MSPS

CP-6±-±

Evaluation Board with AD9613, 210 MSPS

Evaluation Board with AD9613, 250 MSPS

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D09637-0-1/13(C)

Rev. C | Page 36 of 36


型号：	AD9613-170EBZ
厂家：	ADI
描述：	12-Bit, 170 MSPS/210 MSPS/250 MSPS,1.8 V Dual Analog-to-Digital Converter (ADC) 12位， 170 MSPS / 210 MSPS / 250 MSPS ， 1.8 V双通道模拟数字转换器（ ADC ）转换器
文件：	总36页 (文件大小：1074K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9613-170EBZ [ADI]

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AD9613BCPZRL7-210

AD9613BCPZRL7-250

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