AD9631_03 [ADI]
Ultralow Distortion, Wide Bandwidth Voltage Feedback Op Amps; 超低失真，宽带电压反馈运算放大器
| 型号： | AD9631_03 |
| 厂家： | 
ADI |
| 描述： | Ultralow Distortion, Wide Bandwidth Voltage Feedback Op Amps |
| 文件： | 总20页 (文件大小：637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Distortion, Wide Bandwidth
Voltage Feedback Op Amps
a
AD9631/AD9632
FEATURES
Wide Bandwidth
AD9631, G = +1
PIN CONFIGURATION
8-Lead PDIP (N)
and SOIC (R) Packages
AD9632, G = +2
Small Signal
320 MHz
250 MHz
Large Signal (4 V p-p)
175 MHz
AD9631/
1
2
3
4
8
7
6
5
NC
+V
NC
–INPUT
+INPUT
AD9632
S
OUTPUT
NC
–V
S
TOP VIEW
180 MHz
NC = NO CONNECT
Ultralow Distortion (SFDR), Low Noise
–113 dBc Typ @ 1 MHz
–95 dBc Typ @ 5 MHz
–72 dBc Typ @ 20 MHz
46 dBm Third Order Intercept @ 25 MHz
7.0 nV/÷Hz Spectral Noise Density
High Speed
Slew Rate 1300 V/ꢀs
A proprietary design architecture has produced an amplifier
that combines many of the best characteristics of both current
feedback and voltage feedback amplifiers. The AD9631 and
AD9632 exhibit exceptionally fast and accurate pulse response
(16 ns to 0.01%) as well as extremely wide small signal and large
signal bandwidth and ultralow distortion. The AD9631 achieves
–72 dBc at 20 MHz, and 320 MHz small signal and 175 MHz
large signal bandwidths.
Settling 16 ns to 0.01%, 2 V Step
ꢁ3 V to ꢁ5 V Supply Operation
17 mA Supply Current
These characteristics position the AD9631/AD9632 ideally for
driving flash as well as high resolution ADCs. Additionally, the
balanced high impedance inputs of the voltage feedback archi-
tecture allow maximum flexibility when designing active filters.
APPLICATIONS
ADC Input Driver
Differential Amplifiers
IF/RF Amplifiers
Pulse Amplifiers
The AD9631/AD9632 are offered in the industrial (–40ꢂC to
+85ꢂC) temperature range. They are available in PDIP and SOIC.
Professional Video
–30
DAC Current to Voltage
Baseband and Video Communications
Pin Diode Receivers
V
= ꢁ5V
S
R
V
= 500ꢃ
= 2V p-p
L
O
–50
–70
Active Filters/Integrators/Log Amps
GENERAL DESCRIPTION
–90
The AD9631 and AD9632 are very high speed and wide band-
width amplifiers. They are an improved performance alternative
to the AD9621 and AD9622. The AD9631 is unity gain stable.
The AD9632 is stable at gains of 2 or greater. Using a voltage
feedback architecture, the AD9631/AD9632’s exceptional settling
time, bandwidth, and low distortion meet the requirements of
many applications that previously depended on current feedback
amplifiers. Its classical op amp structure works much more
predictably in many designs.
SECOND HARMONIC
–110
THIRD HARMONIC
–130
10k
100k
1M
10M
100M
FREQUENCY – Hz
Figure 1. AD9631 Harmonic Distortion vs.
Frequency, G = +1
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9631/AD9632–SPECIFICATIONS
(؎VS = ؎5 V; RLOAD = 100 ⍀; AV = 1 (AD9631); AV = 2 (AD9632), unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
AD9631A
AD9632A
Parameter
Conditions
Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
Bandwidth (–3 dB)
Small Signal
V
OUT Յ 0.4 V p-p
220 320
150 175
180 250
155 180
MHz
MHz
Large Signal1
VOUT = 4 V p-p
Bandwidth for 0.1 dB Flatness
VOUT = 300 mV p-p
AD9631, RF = 140 W;
AD9632, RF = 425 W
VOUT = 4 V Step
VOUT = 0.5 V Step
VOUT = 4 V Step
130
130
MHz
Slew Rate, Average ±
Rise/Fall Time
1000 1300
1200 1500
V/ms
ns
ns
1.2
2.5
1.4
2.1
Settling Time
To 0.1%
To 0.01%
VOUT = 2 V Step
VOUT = 2 V Step
11
16
11
16
ns
ns
HARMONIC/NOISE PERFORMANCE
Second Harmonic Distortion
2 V p-p; 20 MHz, RL = 100 W
RL = 500 W
–64 –57
–54 –47
dBc
dBc
dBc
dBc
dBm
dB
nV/÷Hz
pA/÷Hz
–72 –65
–76 –69
–81 –74
46
18
7.0
–72 –65
–74 –67
–81 –74
41
14
4.3
Third Harmonic Distortion
2 V p-p; 20 MHz, RL = 100 W
RL = 500 W
Third Order Intercept
Noise Figure
Input Voltage Noise
Input Current Noise
Average Equivalent Integrated
Input Noise Voltage
Differential Gain Error (3.58 MHz)
Differential Phase Error (3.58 MHz)
Phase Nonlinearity
25 MHz
RS = 50 W
1 MHz to 200 MHz
1 MHz to 200 MHz
2.5
2.0
0.1 MHz to 200 MHz
RL = 150 W
RL = 150 W
DC to 100 MHz
100
60
mV rms
%
0.03 0.06
0.02 0.04
1.1
0.02 0.04
0.02 0.04 Degree
1.1
Degree
DC PERFORMANCE2 RL = 150 W
Input Offset Voltage3 ,
3
10
13
2
5
8
mV
mV
mV/؇C
mA
TMIN–TMAX
Offset Voltage Drift
Input Bias Current
±10
2
±10
2
7
10
3
7
10
3
TMIN–TMAX
mA
Input Offset Current
0.1
0.1
mA
TMIN–TMAX
5
5
mA
Common-Mode Rejection Ratio
Open-Loop Gain
VCM = ±2.5 V
VOUT = ±2.5 V
TMIN–TMAX
70
46
40
90
52
70
46
40
90
52
dB
dB
dB
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
500
1.2
±3.4
500
1.2
±3.4
kW
pF
V
Input Common-Mode Voltage Range
OUTPUT CHARACTERISTICS
Output Voltage Range, RL = 150 W
Output Current
Output Resistance
Short Circuit Current
±3.2 ±3.9
±3.2 ±3.9
V
70
70
mA
W
mA
0.3
240
0.3
240
POWER SUPPLY
Operating Range
Quiescent Current
±3.0 ±5.0 ±6.0 ±3.0 ±5.0 ±6.0
V
17
18
21
16
17
20
mA
mA
dB
TMIN–TMAX
TMIN–TMAX
Power Supply Rejection Ratio
50
60
56
66
NOTES
1See Absolute Maximum Ratings and Theory of Operation sections of this data sheet.
2Measured at AV = 50.
3Measured with respect to the inverting input.
Specifications subject to change without notice.
–2–
REV. C
AD9631/AD9632
MAXIMUM POWER DISSIPATION
ABSOLUTE MAXIMUM RATINGS1
The maximum power that can be safely dissipated by these
devices is limited by the associated rise in junction temperature.
The maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately 150؇C. Exceeding this limit temporarily
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junc-
tion temperature of 175؇C for an extended period can result in
device failure.
Supply Voltage (+VS to –VS) . . . . . . . . . . . . . . . . . . . . . 12.6 V
Voltage Swing ¥ Bandwidth Product . . . . . . . . . . . 550 V-MHz
Internal Power Dissipation2
Plastic Package (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . 0.9 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . ±1.2 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range N, R . . . . . . . . . –65؇C to +125؇C
Operating Temperature Range (A Grade) . . . . –40؇C to +85؇C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300؇C
While the AD9631 and AD9632 are internally short circuit
protected, this may not be sufficient to guarantee that the maxi-
mum junction temperature (150؇C) is not exceeded under all
conditions. To ensure proper operation, it is necessary to observe
the maximum power derating curves.
NOTES
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Specification is for device in free air:
2.0
T
= +150 C
J
8-LEAD PDIP PACKAGE
8-Lead PDIP Package: qJA = 90∞C/W
1.5
1.0
8-Lead SOIC Package: qJA = 140∞C/W
METALLIZATION PHOTO
Dimensions shown in inches and (millimeters)
Connect Substrate to –VS
8-LEAD SOIC PACKAGE
+V
7
S
–IN
2
0.5
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
AMBIENTTEMPERATURE – ؇C
0.046
(1.17)
6
OUT
Figure 2. Maximum Power Dissipation
vs. Temperature
ORDERING GUIDE
Temperature
Range
Package
Description Option
Package
Model
3
+IN
4
–V
AD9631
S
AD9631AN
AD9631AR
AD9631AR-REEL –40∞C to +85∞C SOIC
AD9631AR-REEL7 –40∞C to +85∞C SOIC
–40∞C to +85∞C PDIP
–40∞C to +85∞C SOIC
N-8
R-8
R-8
R-8
0.050 (1.27)
+V
S
7
–IN
2
AD9631CHIPS
AD9632AN
AD9632AR
AD9632AR-REEL –40∞C to +85∞C SOIC
AD9632AR-REEL7 –40∞C to +85∞C SOIC
Die
–40∞C to +85∞C PDIP
–40∞C to +85∞C SOIC
N-8
R-8
R-8
R-8
0.046
(1.17)
6
OUT
3
+IN
4
–V
AD9632
S
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9631/AD9632 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. C
–3–
AD9631/AD9632–Typical Performance Characteristics
R
R
F
F
10ꢀF
10ꢀF
+V
+V
S
S
PULSE
GENERATOR
0.1ꢀF
0.1ꢀF
T
/T = 350ps
F
R
267ꢃ
PULSE
V
IN
GENERATOR
R
T
V
V
AD9631
AD9631
OUT
T
/T = 350ps
F
OUT
R
49.9ꢃ
130ꢃ
V
IN
R
= 100ꢃ
R
= 100ꢃ
0.1ꢀF
0.1ꢀF
L
L
R
T
100ꢃ
49.9ꢃ
10ꢀF
10ꢀF
–V
–V
S
S
TPC 1. AD9631 Noninverting Configuration, G = +1
TPC 4. AD9631 Inverting Configuration, G = –1
5ns
5ns
1V
1V
TPC 2. AD9631 Large Signal Transient Response;
TPC 5. AD9631 Large Signal Transient Response;
VO = 4 V p-p, G = +1, RF = 250 W
VO = 4 V p-p, G = –1, RF = RIN = 267 W
5ns
5ns
100mV
100mV
TPC 3. AD9631 Small Signal Transient Response;
TPC 6. AD9631 Small Signal Transient Response;
VO = 400 mV p-p, G = +1, RF = 140 W
VO = 400 mV p-p, G = –1, RF = RIN = 267 W
–4–
REV. C
AD9631/AD9632
R
R
F
F
10ꢀF
10ꢀF
+V
+V
S
S
PULSE
PULSE
GENERATOR
GENERATOR
0.1ꢀF
0.1ꢀF
T
/T = 350ps
F
R
T
/T = 350ps
F
R
R
R
IN
IN
V
IN
R
49.9ꢃ
T
V
V
AD9632
AD9632
OUT
OUT
130ꢃ
V
IN
R
= 100ꢃ
R
= 100ꢃ
0.1ꢀF
0.1ꢀF
L
L
R
49.9ꢃ
T
100ꢃ
10ꢀF
10ꢀF
–V
–V
S
S
TPC 7. AD9632 Noninverting Configuration, G = +2
TPC 10. AD9632 Inverting Configuration, G = –1
5ns
5ns
1V
1V
TPC 11. AD9632 Large Signal Transient Response;
VO = 4 V p-p, G = –1, RF = RIN = 422 W, RT = 56.2 W
TPC 8. AD9632 Large Signal Transient Response;
VO = 4 V p-p, G = +2, RF = RIN = 422 W
5ns
100mV
5ns
100mV
TPC 12. AD9632 Small Signal Transient Response;
VO = 400 mV p-p, G = –1, RF = RIN = 267 W, RT = 61.9 W
TPC 9. AD9632 Small Signal Transient Response;
VO = 400 mV p-p, G = +2, RF = RIN = 274 W
REV. C
–5–
AD9631/AD9632
1
R
F
V
R
= ꢁ5V
= 100ꢃ
S
R
150ꢃ
F
0
450
400
350
300
250
L
GAIN = +1
R
200ꢃ
V
= ꢁ5V
= 100ꢃ
= 300mV p-p
F
–1
–2
–3
S
R
V
L
R
50ꢃ
F
AD9631
O
130ꢃ
R
L
R
F
100ꢃ
N PACKAGE
–4
–5
–6
–7
–8
–9
R PACKAGE
10M
100M
20
40
60
80 100 120 140 160 180 200 220 240
1M
1G
VALUE OF FEEDBACK RESISTOR (R ) –ꢃ
FREQUENCY – Hz
F
TPC 13. AD9631 Small Signal Frequency
Response, G = +1
TPC 16. AD9631 Small Signal –3 dB Bandwidth vs. RF
0.1
1
R
F
R
F
0
–0.1
–0.2
–0.3
250ꢃ
150ꢃ
0
V
R
= ꢁ5V
= 100ꢃ
V
R
V
= ꢁ5V
= 100ꢃ
= 4V p-p
S
S
–1
–2
–3
R
F
140ꢃ
L
L
R
= 50ꢃTO 250ꢃ
BY 50ꢃ
G = +1
= 300mV p-p
F
O
V
O
R
F
100ꢃ
R
120ꢃ
F
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–4
–5
–6
–7
–8
–9
1M
10M
FREQUENCY – Hz
100M
500M
1M
10M
FREQUENCY – Hz
100M
500M
TPC 14. AD9631 0.1 dB Flatness, N Package
(for R Package Add 20 W to RF)
TPC 17. AD9631 Large Signal Frequency
Response, G = +1
90
80
70
60
50
40
100
80
1
0
–1
–2
–3
60
V
R
= ꢁ5V
= 100ꢃ
= 300mV p-p
S
PHASE
L
40
V
O
20
0
R
267ꢃ
F
–4
–5
–6
–7
–8
–9
–20
30
20
GAIN
–40
–60
10
–80
0
–100
–120
–10
–20
10k
100k
1M
FREQUENCY – Hz
100M
1G
10M
1M
10M
100M
1G
FREQUENCY – Hz
TPC 15. AD9631 Open-Loop Gain and
Phase Margin vs. Frequency, RL = 100 W
TPC 18. AD9631 Small Signal Frequency
Response, G = –1
–6–
REV. C
AD9631/AD9632
0.10
0.05
–30
–50
–70
V
R
= ꢁ5V
= 500ꢃ
S
L
G = +1
= 2V p-p
0.00
V
O
–0.05
–0.10
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
0.10
0.05
–90
–110
–130
SECOND
HARMONIC
0.00
THIRD
HARMONIC
–0.05
–0.10
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
10k
100k
1M
10M
100M
FREQUENCY – Hz
TPC 19. AD9631 Harmonic Distortion vs.
TPC 22. AD9631 Differential Gain and Phase
Frequency, RL = 500 W
Error, G = +2, RL = 150 W
–30
–50
–70
0.3
V
R
= ꢁ5V
= 100ꢃ
S
L
0.2
0.1
G = +1
= 2V p-p
V
O
SECOND
HARMONIC
0.0
–0.1
–0.2
–0.3
–90
–110
–130
THIRD
HARMONIC
10k
100k
1M
10M
100M
0
10
20
30
40
50
60
70
80
FREQUENCY – Hz
SETTLINGTIME – ns
TPC 20. AD9631 Harmonic Distortion vs.
TPC 23. AD9631 Short-Term Settling Time,
Frequency, RL = 100 W
2 V Step, RL = 100 W
60
0.3
0.2
0.1
55
50
45
40
35
30
25
20
0.0
–0.1
–0.2
10
20
30
40
50 60 70 80 90 100
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY – MHz
SETTLINGTIME – ꢀs
TPC 21. AD9631 Third Order Intercept vs. Frequency
TPC 24. AD9631 Long-Term Settling Time,
2 V Step, RL = 100 W
REV. C
–7–
AD9631/AD9632
7
R
V
R
= ꢁ5V
= 100ꢃ
F
S
350
300
250
200
150
6
325ꢃ
L
R
425ꢃ
GAIN = +2
F
V
= ꢁ5V
= 100ꢃ
= 300mV p-p
5
4
3
S
R
125ꢃ
F
R
V
L
R
225ꢃ
F
N PACKAGE
O
2
1
R
F
R
IN
R PACKAGE
0
AD9632
100ꢃ
R
L
–1
–2
–3
49.9ꢃ
150 200
100
250 300 350 400 450 500 550
VALUE OF R , R –ꢃ
10M
100M
1M
1G
F
IN
FREQUENCY – Hz
TPC 25. AD9632 Small Signal Frequency
Response, G = +2
TPC 28. AD9632 Small Signal –3 dB Bandwidth
vs. RF, RIN
0.1
0
7
R
F
6
5
4
3
525ꢃ
V
= ꢁ5V
V
R
= ꢁ5V
= 100ꢃ
S
–0.1
–0.2
–0.3
S
R
275ꢃ
F
R
V
= 100ꢃ
= 4V p-p
L
L
G = +2
= 300mV p-p
R
O
F
R
= 125ꢃ TO 525ꢃ
BY 100ꢃ
F
V
O
325ꢃ
R
F
375ꢃ
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
2
1
R
F
425ꢃ
0
–1
–2
–3
1M
10M
100M
1M
10M
FREQUENCY – Hz
100M
500M
FREQUENCY – Hz
TPC 26. AD9632 0.1 dB Flatness, N Package
(for R Package Add 20 W to RF)
TPC 29. AD9632 Large Signal Frequency
Response, G = +2
65
60
1
0
100
55
50
45
40
35
30
25
20
15
10
5
V
= ꢁ5V
S
–1
–2
–3
R
V
= 100ꢃ
= 300mV p-p
50
L
PHASE
O
0
R , R
IN
–50
F
–4
–5
–6
–7
–8
–9
267ꢃ
GAIN
–100
–150
–200
–250
0
–5
–10
–15
10k
100k
1M
FREQUENCY – Hz
100M
1G
10M
1M
10M
100M
1G
FREQUENCY – Hz
TPC 27. AD9632 Open-Loop Gain and Phase
Margin vs. Frequency, RL = 100 W
TPC 30. AD9632 Small Signal Frequency
Response, G = –1
–8–
REV. C
AD9631/AD9632
–30
–50
–70
0.04
0.02
V
R
= ꢁ5V
= 500ꢃ
S
L
G = +2
= 2V p-p
0.00
V
O
–0.02
–0.04
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
SECOND
HARMONIC
0.04
0.02
–90
–110
–130
THIRD
HARMONIC
0.00
–0.02
–0.04
1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH 9TH 10TH 11TH
10k
100k
1M
10M
100M
FREQUENCY – Hz
TPC 34. AD9632 Differential Gain and Phase
Error G = +2, RL = 150 W
TPC 31. AD9632 Harmonic Distortion vs.
Frequency, RL = 500 W
0.2
0.1
–30
–50
–70
V
R
= ꢁ5V
= 100ꢃ
S
L
G = +2
= 2V p-p
V
O
SECOND
HARMONIC
0.0
–0.1
–0.2
–0.3
–90
–110
–130
THIRD
HARMONIC
0
10
20
30
40
50
60
70
80
10k
100k
1M
FREQUENCY – Hz
10M
100M
SETTLINGTIME – ns
TPC 32. AD9632 Harmonic Distortion vs.
TPC 35. AD9632 Short-Term Settling Time,
Frequency, RL = 100 W
2 V Step, RL = 100 W
50
0.3
0.2
0.1
45
40
35
30
25
20
15
10
0.0
–0.1
–0.2
10
20
30
40
50 60 70 80 90 100
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY – MHz
SETTLINGTIME – ꢀs
TPC 33. AD9632 Third Order Intercept vs. Frequency
TPC 36. AD9632 Long-Term Settling Time,
2 V Step, RL = 100 W
REV. C
–9–
AD9631/AD9632
24
17
15
V
= ꢁ5V
V = ꢁ5V
S
21
S
18
15
12
9
13
11
9
7
6
5
3
3
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 37. AD9631 Noise vs. Frequency
TPC 40. AD9632 Noise vs. Frequency
80
80
75
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
70
65
60
55
50
45
40
35
30
25
20
15
10
5
–PSRR
+PSRR
–PSRR
+PSRR
0
0
10k
100k
1M
FREQUENCY – Hz
100M
1G
10k
100k
1M
FREQUENCY – Hz
100M
1G
10M
10M
TPC 38. AD9631 PSRR vs. Frequency
TPC 41. AD9632 PSRR vs. Frequency
100
90
80
70
60
50
40
30
20
100
90
80
70
60
50
40
30
20
V
ꢄV
R
= ꢁ5V
V = ꢁ5V
S
S
= 1V
ꢄV
= 1V
CM
CM
= 100ꢃ
R = 100ꢃ
L
L
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
FREQUENCY – Hz
FREQUENCY – Hz
TPC 39. AD9631 CMRR vs. Frequency
TPC 42. AD9632 CMRR vs. Frequency
–10–
REV. C
AD9631/AD9632
1000
100
10
1350
1250
1150
1050
950
V
= ꢁ5V
S
GAIN = +1
+A
OL
AD9632
–A
OL
850
1
750
650
0.1
550
+A
OL
AD9631
40
450
–A
OL
0.01
10k
350
100k
1M
10M
100M
–60 –40 –20
0
20
60
80
100 120 140
FREQUENCY – Hz
JUNCTIONTEMPERATURE – ꢂC
TPC 43. AD9631 Output Resistance vs. Frequency
TPC 46. Open-Loop Gain vs. Temperature
76
1000
V
= ꢁ5V
S
74
72
70
68
66
64
62
60
58
56
–PSRR
GAIN = +1
AD9632
100
10
+PSRR
–PSRR
AD9632
AD9631
1
0.1
+PSRR
40
AD9631
0.01
10k
–60 –40 –20
0
20
60
80
100 120 140
100k
1M
10M
100M
JUNCTIONTEMPERATURE – ꢂC
FREQUENCY – Hz
TPC 44. AD9632 Output Resistance vs. Frequency
TPC 47. PSRR vs. Temperature
4.1
98
V
= ꢁ5V
S
+V
OUT
4.0
3.9
3.8
3.7
3.6
3.5
3.4
3.3
96
94
92
90
88
86
–V
OUT
R
= 150ꢃ
L
R
= 50ꢃ
L
+V
OUT
–V
OUT
–CMRR
+CMRR
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
JUNCTIONTEMPERATURE – ꢂC
JUNCTIONTEMPERATURE – ꢂC
TPC 45. AD9631/AD9632 Output Swing vs. Temperature
TPC 48. AD9631/AD9632 CMRR vs. Temperature
REV. C
–11–
AD9631/AD9632
21
20
19
18
17
16
15
250
240
230
220
210
200
190
AD9631
AD9631
ꢁ6V
SINK
SOURCE
AD9632
AD9631
ꢁ6V
ꢁ5V
SINK
AD9632
AD9632
ꢁ5V
SOURCE
80 100 120 140
14
180
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
JUNCTIONTEMPERATURE – ꢂC
JUNCTIONTEMPERATURE – ꢂC
TPC 49. Supply Current vs. Temperature
TPC 52. Short Circuit Current vs. Temperature
–1.0
2.0
1.5
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
AD9632
+I
–I
1.0
0.5
B
V
V
= ꢁ5V
= ꢁ6V
B
S
AD9632
AD9631
0.0
S
–0.5
–1.0
–1.5
–2.0
–I
B
V
= ꢁ5V
= ꢁ6V
AD9631
S
S
+I
V
B
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
JUNCTIONTEMPERATURE – ꢂC
JUNCTIONTEMPERATURE – ꢂC
TPC 50. Input Offset Voltage vs. Temperature
TPC 53. Input Bias Current vs. Temperature
220
180
100
100
3WAFER LOTS
COUNT = 573
3WAFER LOTS
COUNT = 1373
200
180
160
140
120
90
80
70
60
50
90
80
70
60
50
160
CUMULATIVE
CUMULATIVE
140
120
100
80
100
80
40
30
20
10
0
40
30
20
10
0
FREQ. DIST
60
FREQ. DIST
60
40
40
20
20
0
0
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
INPUT OFFSETVOLTAGE – mV
INPUT OFFSETVOLTAGE – mV
TPC 51. AD9631 Input Offset Voltage Distribution
TPC 54. AD9632 Input Offset Voltage Distribution
–12–
REV. C
AD9631/AD9632
THEORY OF OPERATION
General
When the AD9631 is used in the transimpedance (I to V) mode,
such as in photodiode detection, the value of RF and diode capaci-
tance (CI) are usually known. Generally, the value of RF selected
will be in the kW range, and a shunt capacitor (CF) across RF will
be required to maintain good amplifier stability. The value of
CF required to maintain optimal flatness (<1 dB peaking) and
settling time can be estimated as
The AD9631 and AD9632 are wide bandwidth, voltage feedback
amplifiers. Since their open-loop frequency response follows the
conventional 6 dB/octave roll-off, their gain bandwidth product
is basically constant. Increasing their closed-loop gain results in
a corresponding decrease in small signal bandwidth. This can
be observed by noting the bandwidth specification between the
AD9631 (gain of +1) and AD9632 (gain of +2). The AD9631/
AD9632 typically maintain 65 degrees of phase margin. This
high margin minimizes the effects of signal and noise peaking.
1
2
]
CF @ 2ꢀ C R – 1 / ꢀ 2RF
2
(
)
O
I
F
O
[
where wO is equal to the unity gain bandwidth product of the
amplifier in rad/sec, and CI is the equivalent total input
capacitance at the inverting input. Typically wO = 800 ꢅ 106
rad/sec (see TPC 15).
Feedback Resistor Choice
The value of the feedback resistor is critical for optimum perfor-
mance on the AD9631 (gain of +1) and less critical as the gain
increases. Therefore, this section is specifically targeted at the
AD9631.
As an example, choosing RF = 10 kW and CI = 5 pF requires CF
to be 1.1 pF (Note: CI includes both source and parasitic circuit
capacitance). The bandwidth of the amplifier can be estimated
using the CF calculated as
At minimum stable gain (+1), the AD9631 provides optimum
dynamic performance with RF = 140 W. This resistor acts as a
parasitic suppressor only against damped RF oscillations that
can occur due to lead (input, feedback) inductance and parasitic
capacitance. This value of RF provides the best combination of
wide bandwidth, low parasitic peaking, and fast settling time.
1.6
2ꢂRFCF
f3dꢁ
@
R
F
In fact, for the same reasons, a 100 W–130 W resistor should be
placed in series with the positive input for other AD9631 noninver-
ting and all AD9631 inverting configurations. The correct
connection is shown in Figures 3 and 4.
C
F
I
I
C
I
AD9631
V
OUT
+V
S
R
F
10ꢀF
G = 1 +
R
G
Figure 5. Transimpedance Configuration
0.1ꢀF
100ꢃ–130ꢃ
V
IN
R
For general voltage gain applications, the amplifier bandwidth
can be closely estimated as
IN
R
TERM
AD9631/
AD9632
V
OUT
R
F
ꢀO
f3dB
@
2ꢂ 1 + R /R
(
)
0.1ꢀF
F
G
R
G
This estimation loses accuracy for gains of +2/–1 or lower due
to the amplifier’s damping factor. For these “low gain” cases,
the bandwidth will actually extend beyond the calculated value
(see TPCs 13 and 25).
10ꢀF
–V
S
Figure 3. Noninverting Operation
As a general rule, capacitor CF will not be required if
+V
S
R
R
10ꢀF
F
NG
4ꢀO
G = –
R
RG ¥C £
(
)
F
I
G
0.1ꢀF
100ꢃ–130ꢃ
where NG is the noise gain (1 + RF/RG) of the circuit. For most
voltage gain applications, this should be the case.
R
IN
AD9631/
AD9632
V
OUT
R
F
R
G
V
IN
0.1ꢀF
R
TERM
10ꢀF
–V
S
Figure 4. Inverting Operation
REV. C
–13–
AD9631/AD9632
Pulse Response
40
30
20
10
Unlike a traditional voltage feedback amplifier, where the slew
speed is dictated by its front end dc quiescent current and
gain bandwidth product, the AD9631 and AD9632 provide
“on-demand” current that increases proportionally to the input
“step” signal amplitude. This results in slew rates (1300 V/ms)
comparable to wideband current feedback designs. This, combined
with relatively low input noise current (2.0 pA/÷Hz), gives the
AD9631 and AD9632 the best attributes of both voltage and
current feedback amplifiers.
Large Signal Performance
The outstanding large signal operation of the AD9631 and AD9632
is due to a unique, proprietary design architecture. In order to
maintain this level of performance, the maximum 550 V-MHz
product must be observed (e.g., @ 100 MHz, VO £ 5.5 V p-p).
0
5
10
15
20
25
C
– pF
L
Power Supply Bypassing
Figure 7. Recommended RSERIES vs. Capacitive Load
Adequate power supply bypassing can be critical when optimizing
the performance of a high frequency circuit. Inductance in the
power supply leads can form resonant circuits that produce
peaking in the amplifier’s response. In addition, if large current
transients must be delivered to the load, then bypass capacitors
(typically greater than 1 mF) will be required to provide the best
settling time and lowest distortion. A parallel combination of at
least 4.7 mF, and between 0.1 mF and 0.01 mF, is recommended.
Some brands of electrolytic capacitors will require a small series
damping resistor ª4.7 W for optimum results.
APPLICATIONS
The AD9631 and AD9632 are voltage feedback amplifiers well
suited for applications such as photodetectors, active filters, and
log amplifiers. The devices’ wide bandwidth (320 MHz), phase
margin (65ꢂ), low current noise (2.0 pA/÷Hz), and slew rate
(1300 V/ms) give higher performance capabilities to these appli-
cations over previous voltage feedback designs.
With a settling time of 16 ns to 0.01% and 11 ns to 0.1%, the
devices are an excellent choice for DAC I/V conversion. The same
characteristics along with low harmonic distortion make them
a good choice for ADC buffering/amplification. With superb
linearity at relatively high signal frequencies, the AD9631 and
AD9632 are ideal drivers for ADCs up to 12 bits.
Driving Capacitive Loads
The AD9631 and AD9632 were designed primarily to drive
nonreactive loads. If driving loads with a capacitive component is
desired, the best frequency response is obtained by the addition of
a small series resistance as shown in Figure 6. The accompany-
ing graph shows the optimum value for RSERIES versus capacitive
load. It is worth noting that the frequency response of the circuit
when driving large capacitive loads will be dominated by the
passive roll-off of RSERIES and CL.
Operation as a Video Line Driver
The AD9631 and AD9632 have been designed to offer outstand-
ing performance as video line drivers. The important specifications
of differential gain (0.02%) and differential phase (0.02ꢂ) meet
the most exacting HDTV demands for driving video loads.
R
F
274ꢃ
274ꢃ
10ꢀF
+V
S
R
SERIES
R
R
IN
AD9631/
AD9632
0.1ꢀF
R
L
IN
C
L
75ꢃ
CABLE
1kꢃ
75ꢃ
AD9631/
AD9632
75ꢃ
CABLE
V
OUT
75ꢃ
0.1ꢀF
10ꢀF
V
IN
Figure 6. Driving Capacitive Loads
75ꢃ
–V
S
Figure 8. Video Line Driver
–14–
REV. C
AD9631/AD9632
Active Filters
Choose
The wide bandwidth and low distortion of the AD9631 and
AD9632 are ideal for the realization of higher bandwidth active
filters. These characteristics, while being more common in
many current feedback op amps, are offered in the AD9631 and
AD9632 in a voltage feedback configuration. Many active filter
configurations are not realizable with current feedback amplifiers.
FO = Cutoff Frequency = 20 MHz
a = Damping Ratio = 1/Q = 2
–R4
R1
H = Absolute Value of Circuit Gain =
= 1
Then
k = 2ꢂ FO C1
A multiple feedback active filter requires a voltage feedback
amplifier and is more demanding of op amp performance than
other active filter configurations, such as the Sallen-Key. In
general, the amplifier should have a bandwidth that is at least
10 times the bandwidth of the filter if problems due to phase shift
of the amplifier are to be avoided.
4C1(H + 1)
C2 =
R1 =
R3 =
ꢃ2
ꢃ
2HK
ꢃ
Figure 9 is an example of a 20 MHz low-pass multiple feedback
active filter using an AD9632.
2K (H + 1)
R4 = H (R1)
+5V
A/D Converter Driver
10ꢀF
C1
50pF
R4
154ꢃ
As A/D converters move toward higher speeds with higher resolu-
tions, there becomes a need for high performance drivers that
will not degrade the analog signal to the converter. It is desirable
from a system’s standpoint that the A/D be the element in the
signal chain that ultimately limits overall distortion. This places
new demands on the amplifiers that are used to drive fast, high
resolution A/Ds.
0.1ꢀF
R1
154ꢃ
R3
78.7ꢃ
V
IN
C2
100pF
V
AD9632
OUT
100ꢃ
0.1ꢀF
10ꢀF
With high bandwidth, low distortion, and fast settling time, the
AD9631 and AD9632 make high performance A/D drivers for
advanced converters. Figure 10 is an example of an AD9631 used
as an input driver for an AD872, a 12-bit, 10 MSPS A/D converter.
–5V
Figure 9. Active Filter Circuit
+5V DIGITAL
10ꢃ
+5V ANALOG
7
DV
DD
0.1ꢀF
0.1ꢀF
6
DGND
+5V DIGITAL
4
5
+5V ANALOG
140ꢃ
AV
DD
22
23
0.1ꢀF
DV
DD
AGND
10ꢀF
DGND
CLOCK INPUT
21
20
CLK
OTR
0.1ꢀF
AD872
49.9ꢃ
19
18
17
16
15
14
13
12
11
10
9
1
2
MSB
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
V
AD9631
INA
130ꢃ
ANALOG
IN
0.1ꢀF
V
INB
27
REF GND
10ꢀF
DIGITAL OUTPUT
0.1ꢀF
1ꢀF
28
26
–5V ANALOG
REF IN
REF OUT
8
AGND
AV
SS
AV
SS
3
25
0.1ꢀF
0.1ꢀF
–5V ANALOG
Figure 10. AD9631 Used as Driver for an AD872, a 12-Bit, 10 MSPS A/D Converter
REV. C
–15–
AD9631/AD9632
Layout Considerations
large (0.47 mF–10 mF) tantalum electrolytic capacitor should be
connected in parallel, though not necessarily so close, to supply
current for fast, large signal changes at the output.
The specified high speed performance of the AD9631 and AD9632
requires careful attention to board layout and component
selection. Proper RF design techniques and low-pass parasitic
component selection are mandatory.
The feedback resistor should be located close to the inverting input
pin in order to keep the stray capacitance at this node to a mini-
mum. Capacitance variations of less than 1 pF at the inverting
input will significantly affect high speed performance.
The PCB should have a ground plane covering all unused portions
of the component side of the board to provide a low impedance
path. The ground plane should be removed from the area near
the input pins to reduce stray capacitance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50 W or 75 W and be properly termi-
nated at each end.
Chip capacitors should be used for supply bypassing (see
Figure 10). One end should be connected to the ground plane,
and the other within 1/8 inch of each power pin. An additional
–16–
REV. C
AD9631/AD9632
OUTLINE DIMENSIONS
8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
0.375 (9.53)
0.365 (9.27)
0.355 (9.02)
8
1
5
0.295 (7.49)
0.285 (7.24)
0.275 (6.98)
4
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015
(0.38)
MIN
0.180
(4.57)
MAX
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MO-095AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
ꢅ 45ꢂ
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8ꢂ
0.51 (0.0201)
0.31 (0.0122)
0ꢂ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. C
–17–
AD9631/AD9632
Revision History
Location
Page
7/03—Data Sheet changed from REV. B to REV. C.
Deleted Evaluation Boards information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Deleted military CERDIP version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Change to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Change to TPC 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Change to TPC 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Change to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1/03—Data Sheet changed from REV. A to REV. B.
Deleted DIP (N) Inverter, SOIC (R) Inverter, and DIP (N) Noninverter Evaluation Boards in Figures 12–14 . . . . . . . . . . . . . . . 17
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
–18–
REV. C
–19–
–20–
相关型号：
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