AD9644CCPZRL7-80_技术文档

14-Bit, 80 MSPS/155 MSPS, 1.8 V Dual

Serial Output Analog-to-Digital Converter (ADC)

Data Sheet

AD9644

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

AGND

DRVDD

DRGND

JESD204A coded serial digital outputs

SNR = 73.7 dBFS at 70 MHz and 80 MSPS

SNR = 71.7 dBFS at 70 MHz and 155 MSPS

SFDR = 92 dBc at 70 MHz and 80 MSPS

SFDR = 92 dBc at 70 MHz and 155 MSPS

Low power: 423 mW at 80 MSPS, 567 mW at 155 MSPS

1.8 V supply operation

AD9644

DOUT+A

DOUT–A

VIN+A

14

PIPELINE

14-BIT ADC

DSYNC+A

DSYNC–A

VIN–A

VCMA

DOUT+B

DOUT–B

14

VIN+B

VIN–B

VCMB

PIPELINE

14-BIT ADC

Integer 1-to-8 input clock divider

IF sampling frequencies to 250 MHz

DSYNC+B

DSYNC–B

−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS

−150.3 dBFS/Hz input noise at 180 MHz and 155 MSPS

Programmable internal ADC voltage reference

Flexible analog input range: 1.4 V p-p to 2.1 V p-p

ADC clock duty cycle stabilizer

REFERENCE

PLL

SERIAL PORT

1 TO 8

CLOCK

DIVIDER

PDWN

(SPI)

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

SCLK SDIO CSB

CLK+ CLK– SYNC

Figure 1. 48-Lead 7 mm × 7 mm LFCSP

APPLICATIONS

Communications

PRODUCT HIGHLIGHTS

Diversity radio systems

1. An on-chip PLL allows users to provide a single ADC

sampling clock; the PLL multiplies the ADC sampling

clock to produce the corresponding JESD204A data rate

clock.

2. The configurable JESD204A output block supports up to

1.6 Gbps per channel data rate when using a dedicated

data link per ADC or 3.2 Gbps data rate when using a

single shared data link for both ADCs.

3. Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 250 MHz.

4. Operation from a single 1.8 V power supply.

5. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding),

controlling the clock DCS, power-down, test modes,

voltage reference mode, and serial output configuration.

Multimode digital receivers (3G and 4G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

No license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registeredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9644

Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Voltage Reference ...................................................................... 22

Clock Input Considerations ..................................................... 22

Channel/Chip Synchronization ............................................... 24

Power Dissipation and Standby Mode.................................... 24

Digital Outputs........................................................................... 24

Built-In Self-Test (BIST) and Output Test ................................. 29

Built-In Self-Test (BIST) ........................................................... 29

Output Test Modes.................................................................... 29

Serial Port Interface (SPI) ............................................................. 31

Configuration Using the SPI .................................................... 31

Hardware Interface .................................................................... 32

SPI Accessible Features ............................................................. 32

Memory Map .................................................................................. 33

Reading the Memory Map Register Table.............................. 33

Memory Map Register Table.................................................... 34

Memory Map Register Descriptions ....................................... 38

Applications Information ............................................................. 42

Design Guidelines ...................................................................... 42

Outline Dimensions....................................................................... 43

Ordering Guide .......................................................................... 43

Applications ...................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights........................................................................... 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications .................................................................................... 4

ADC DC Specifications............................................................... 4

ADC AC Specifications ............................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications.............................................................. 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings ......................................................... 10

Thermal Characteristics ................................................................ 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions .......................... 11

Typical Performance Characteristics........................................... 13

Equivalent Circuits......................................................................... 19

Theory of Operation ...................................................................... 20

ADC Architecture ...................................................................... 20

Analog Input Considerations ................................................... 20

REVISION HISTORY

9/2020—Rev. C to Rev. D

4/2011—Rev. 0 to Rev. A

Changed CP-48-8 to CP-48-9......................................Throughout

Updated Outline Dimensions....................................................... 43

Changes to Ordering Guide.......................................................... 43

Added Model -155 ........................................................ Throughout

Changes to Features Section and Figure 1.....................................1

Changes to General Description Section .......................................3

Changes to Table 1............................................................................4

Changes to Table 2............................................................................5

Changes to Table 4............................................................................8

Additions to TPC Introductory Statement................................. 13

Changes to Speed Grade ID Bits in Table 17 ............................. 31

Changes to Ordering Guide.......................................................... 40

1/2012—Rev. B to Rev. C

Change to General Description Section........................................ 3

6/2011—Rev. A to Rev. B

Added Figure 23 to Figure 40; Renumbered Sequentially........ 16

Changes to Clock Input Considerations Section....................... 22

Added Figure 61 ............................................................................. 24

Changes to Digital Outputs and Timing Section....................... 27

Added Figure 69 ............................................................................. 28

Changes to Output Test Modes Section...................................... 29

Changes to SPI Accessible Features Section............................... 32

6/2010—Revision 0: Initial Version

Rev. D | Page 2 of 44

Data Sheet

AD9644

GENERAL DESCRIPTION

The AD9644 is a dual, 14-bit, analog-to-digital converter (ADC)

with a high speed serial output interface and sampling speeds

of either 80 MSPS or 155 MSPS.

By default, the ADC output data is routed directly to the two

external JESD204A serial output ports. These outputs are at CML

voltage levels. Two modes are supported such that output

coded data is either sent through one data link or two. (L = 1; F

= 4 or

L = 2; F = 2). Independent synchronization inputs (DSYNC)

are provided for each channel.

The AD9644 is designed to support communications appli-

cations where high performance, combined with low cost, small

size, and versatility, is desired. The JESD204A high speed serial

interface reduces board routing requirements and lowers pin count

requirements for the receiving device.

Flexible power-down options allow significant power savings,

when desired.

The dual ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth differential sample-and-hold

analog input amplifiers that support a variety of user-selectable

input ranges. An integrated voltage reference eases design consid-

erations. A duty cycle stabilizer is provided to compensate for

variations in the ADC clock duty cycle, allowing the converters

to maintain excellent performance.

Programming for setup and control is accomplished using a 3-wire

SPI-compatible serial interface.

The AD9644 is available in a 48-lead LFCSP and is specified over

the industrial temperature range of −40°C to +85°C.

This product is protected by a U.S. patent.

Rev. D | Page 3 of 44

AD9644

Data Sheet

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS diﬀerential input, DCS enabled,

unless otherwise noted.

Table 1.

AD9644-80

Typ

AD9644-155

Typ

Parameter

Temperature Min

Max

Min

Max

Unit

RESOLUTION

Full

14

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Full

±5°C

Full

±5°C

Guaranteed

±±

−±.5

Guaranteed

±±.±

−1.5

±1ꢀ

+1

±ꢀ.55

±11

+4

±ꢀ.55

mV

% FSR

LSB

−7

−6

Differential Nonlinearity (DNL)¹

±ꢀ.3

±ꢀ.5

±ꢀ.3

Integral Nonlinearity (INL)¹

±1.1

±1.±5

±ꢀ.55

LSB

MATCHING CHARACTERISTIC

Offset Error

Gain Error

Full

−7

−1.5

+1.5

+ꢀ.6

+1ꢀ

+±.75

−6

−3.1

+1.5

+ꢀ.75

+9

+5

mV

% FSR

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

±5°C

±±

±35

ꢀ.7

±±

±144

ꢀ.7

ppm/°C

LSB rms

INPUT REFERRED NOISE

ANALOG INPUT

Input Span

Input Capacitance^±

Input Resistance

VCM OUTPUT LEVEL

POWER SUPPLIES

Supply Voltage

AVDD

Full

1.383

ꢀ.88

1.75

7

±ꢀ

±.ꢀ87

ꢀ.9±

1.383

ꢀ.87

1.75

5

±ꢀ

±.ꢀ87

ꢀ.93

V p-p

pF

kΩ

V

ꢀ.9

Full

1.7

1.8

1.9

1.7

1.8

1.9

V

DRVDD

Supply Current

IAVDD¹

IDRVDD¹

Full

175

6ꢀ

19ꢀ

67

±±6

89

±4±

97

mA

POWER CONSUMPTION

Sine Wave Input1

Standby Power³

Power-Down Power

Full

4±3

85

15

46ꢀ

±7

567

168

18

61ꢀ

±7

mW

¹Measured with a low input frequency, full-scale sine wave.

^±Input capacitance refers to the effective capacitance between one differential input pin and AGND.

³Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

Rev. D | Page 4 of 44

Data Sheet

AD9644

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS diﬀerential input, DCS enabled,

unless otherwise noted.

Table 2.

AD9644-80

Typ

AD9644-155

Parameter¹

Temperature

Min

Max

Min

Typ

Max

Unit

SIGNAL-TO-NOISE-RATIO (SNR)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

73.8

73.7

7±.6

71.9

71.7

71.4

dBFS

f_IN= 18ꢀ MHz

71.8

7ꢀ.ꢀ

AD9644BCPZ-8ꢀ

AD9644CCPZ-8ꢀ

AD9644BCPZ-155

f_IN= ±±ꢀ MHz

Full

69.8

±5°C

7±.ꢀ

71.ꢀ

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

7±.7

7±.6

71.5

7ꢀ.8

7ꢀ.7

7ꢀ.3

dBFS

f_IN= 18ꢀ MHz

7ꢀ.4

68.6

AD9644BCPZ-8ꢀ

AD9644CCPZ-8ꢀ

AD9644BCPZ-155

f_IN= ±±ꢀ MHz

Full

68.7

±5°C

71.1

69.9

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

f_IN= 18ꢀ MHz

f_IN= ±±ꢀ MHz

±5°C

11.8

11.6

11.5

11.4

11.3

Bits

WORST SECOND OR THIRD HARMONIC

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

−94

−9±

−87

−94

−9±

dBc

f_IN= 18ꢀ MHz

−8ꢀ

−73

AD9644BCPZ-8ꢀ

AD9644CCPZ-8ꢀ

AD9644BCPZ-155

f_IN= ±±ꢀ MHz

Full

−8ꢀ

±5°C

−85

−9ꢀ

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

94

9±

87

94

9±

dBc

f_IN= 18ꢀ MHz

8ꢀ

73

AD9644BCPZ-8ꢀ

AD9644CCPZ-8ꢀ

AD9644BCPZ-155

f_IN= ±±ꢀ MHz

Full

8ꢀ

±5°C

85

9ꢀ

WORST OTHER (HARMONIC OR SPUR)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

−98

−96

−97

−95

dBc

f_IN= 18ꢀ MHz

−9ꢀ

−87

AD9644BCPZ-8ꢀ

AD9644CCPZ-8ꢀ

AD9644BCPZ-155

f_IN= ±±ꢀ MHz

Full

−89

±5°C

−95

−94

Rev. D | Page 5 of 44

AD9644

Data Sheet

AD9644-80

Typ

AD9644-155

Parameter¹

Temperature

Min

Max

Min

Typ

Max

Unit

TWO-TONE SFDR

f_IN= +3ꢀ MHz (−7 dBFS ), +33 MHz (−7 dBFS )

f_IN= +169 MHz (−7 dBFS ), +17± MHz (−7 dBFS )

CROSSTALK^±

±5°C

Full

93

89

9ꢀ

89

dBc

dB

−1ꢀ5

78ꢀ

−1ꢀ5

78ꢀ

ANALOG INPUT BANDWIDTH³

±5°C

MHz

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

^±Crosstalk is measured at 1ꢀꢀ MHz with −1.ꢀ dBFS on one channel and no input on the alternate channel.

³Analog input bandwidth specifies the −3 dB input BW of the AD9644 input. The usable full-scale BW of the part with good performance is ±5ꢀ MHz.

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS diﬀerential input, and DCS enabled,

unless otherwise noted.

Table 3.

AD9644-80/AD9644-155

Parameter

Temperature

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

ꢀ.9

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

High Level Input Current

Low Level Input Current

Input Capacitance

Full

V

ꢀ.3

AGND

ꢀ.9

−1ꢀꢀ

3.6

AVDD

1.4

V p-p

V

+1ꢀꢀ

μA

pF

kΩ

4

1ꢀ

Input Resistance

8

1±

SYNC INPUT

Logic Compliance

Internal Bias

CMOS

ꢀ.9

Full

V

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

AGND

1.±

AGND

−1ꢀꢀ

AVDD

ꢀ.6

V

+1ꢀꢀ

μA

pF

kΩ

1

16

Input Resistance

1±

±ꢀ

DSYNC INPUT

Logic Compliance

Internal Bias

CMOS/LVDS

ꢀ.9

Full

V

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

AGND

1.±

AGND

−1ꢀꢀ

AVDD

ꢀ.6

V

+1ꢀꢀ

μA

pF

kΩ

1

16

Input Resistance

1±

±ꢀ

Rev. D | Page 6 of 44

Data Sheet

AD9644

AD9644-80/AD9644-155

Parameter

LOGIC INPUT (CSB)¹

Temperature

Min

Typ

Max

Unit

Logic Compliance

CMOS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.±±

ꢀ

−1ꢀ

4ꢀ

±.1

ꢀ.6

+1ꢀ

13±

V

μA

kΩ

pF

±6

±

Input Capacitance

LOGIC INPUT (SCLK, PDWN)^±

Logic Compliance

CMOS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current (VIN = 1.8 V)

Low Level Input Current

Input Resistance

Full

1.±±

ꢀ

−9±

−1ꢀ

±.1

ꢀ.6

−135

+1ꢀ

V

μA

kΩ

pF

±6

±

Input Capacitance

LOGIC INPUT/OUTPUT (SDIO)¹

Logic Compliance

CMOS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.±±

ꢀ

−1ꢀ

38

±.1

ꢀ.6

+1ꢀ

1±8

V

μA

kΩ

pF

±6

5

Input Capacitance

DIGITAL OUTPUTS

Logic Compliance

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Full

CML

ꢀ.8

DRVDD/±

ꢀ.6

ꢀ.75

1.1

1.ꢀ5

V

¹Pull up.

^±Pull down.

Rev. D | Page 7 of 44

AD9644

Data Sheet

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS diﬀerential input, and DCS enabled,

unless otherwise noted.

Table 4.

AD9644-80

Typ

AD9644-155

Typ

Parameter

Temperature Min

Max Min

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Full

64ꢀ

8ꢀ

64ꢀ

155

MHz

MSPS

ns

Conversion Rate¹

4ꢀ

1±.5

4ꢀ

6.45

CLK Period—Divide-by-1 Mode (t_CLK

)

CLK Pulse Width High (t_CH)

Divide-by-1 Mode, DCS Enabled

Divide-by-1 Mode, DCS Disabled

Divide-by-± Mode Through Divide-by-8

Mode

Full

3.75

5.95

ꢀ.8

6.±5

8.75

6.55

1.935

3.ꢀ65

ꢀ.8

3.±±5

4.515 ns

3.385 ns

ns

Aperture Delay (t_A)

Full

ꢀ.78

ꢀ.1±5

ꢀ.78

ꢀ.1±5

ns

ps rms

Aperture Uncertainty (Jitter, t_J)

DATA OUTPUT PARAMETERS

Data Output Period or UI (Unit Interval)

Data Output Duty Cycle

Data Valid Time

PLL Lock Time (t_LOCK

Wake Up Time (Standby)

Wake Up Time (Power-Down)^±

Pipeline Delay (Latency)

Full

1/(±ꢀ × f_CLK

)

1/(±ꢀ × f_CLK

)

Seconds

%

UI

μs

ms

5ꢀ

ꢀ.78

4

±5°C

Full

5ꢀ

ꢀ.74

4

5

±.5

)

5

±.5

±3

±4

±3

±4

CLK

cycles

Data Rate per Channel (NRZ)

Deterministic Jitter

Random Jitter at 1.6 Gbps

Random Jitter at 3.± Gbps

Output Rise/Fall Time

±5°C

1.6

4ꢀ

9.5

5.±

5ꢀ

3.1

4ꢀ

Gbps

ps

ps rms

ps

5.±

5ꢀ

TERMINATION CHARACTERISTICS

Differential Termination Resistance

OUT-OF-RANGE RECOVERY TIME

±5°C

1ꢀꢀ

±

1ꢀꢀ

±

Ω

CLK

cycles

¹Conversion rate is the clock rate after the divider.

^±Wake-up time is defined as the time required to return to normal operation from power-down mode.

Rev. D | Page 8 of 44

Data Sheet

AD9644

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Limit

SYNC TIMING REQUIREMENTS

t_SSYNC

t_HSYNC

SYNC to rising edge of CLK+ setup time

SYNC to rising edge of CLK+ hold time

ꢀ.3ꢀ ns typ

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

± ns min

4ꢀ ns min

± ns min

1ꢀ ns min

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge

1ꢀ ns min

Timing Diagrams

SAMPLE

N

N – 23

ANALOG

N – 22

N + 1

INPUT

N – 21

SIGNAL

N – 1

N – 20

CLK–

CLK+

CLK–

CLK+

DOUT+

DOUT–

SAMPLE N – 23

ENCODED INTO 2

8b/10b SYMBOLS

SAMPLE N – 22

ENCODED INTO 2

8b/10b SYMBOLS

SAMPLE N – 21

ENCODED INTO 2

8b/10b SYMBOLS

Figure 2. Data Output Timing

CLK+

SYNC

t_SSYNC

t_HSYNC

Figure 3. SYNC Input Timing Requirements

Rev. D | Page 9 of 44

AD9644

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the PCB

increases the reliability of the solder joints and maximizes the

thermal capability of the package.

Parameter

Rating

ELECTRICAL

AVDD to AGND

DRVDD to AGND

−ꢀ.3 V to +±.ꢀ V

−ꢀ.3 V to +±.ꢀV

VIN+A/VIN+B, VIN−A/VIN−B to AGND −ꢀ.3 V to AVDD + ꢀ.± V

Table 7. Thermal Resistance

CLK+, CLK− to AGND

SYNC to AGND

VCMA, VCMB to AGND

CSB to AGND

SCLK to AGND

SDIO to AGND

PDWN to AGND

DOUT+A, DOUTꢀ−A, DOUTꢀ+B,

DOUT−B to AGND

−ꢀ.3 V to AVDD + ꢀ.± V

−ꢀ.3 V to DRVDD + ꢀ.± V

Airflow

Velocity

(m/sec)

1, 2

1, 3

1, 4

Package Type

θ_JA

±5

±±

±ꢀ

θ_JC

θ_JB

Unit

°C/W

48-Lead LFCSP

7 mm × 7 mm

(CP-48-9)

ꢀ

±

14

1.ꢀ

±.5

¹Per JEDEC 51-7, plus JEDEC ±5-5 ±S±P test board.

^±Per JEDEC JESD51-± (still air) or JEDEC JESD51-6 (moving air).

³Per MIL-STD 883, Method 1ꢀ1±.1.

⁴Per JEDEC JESD51-8 (still air).

DSYNC+A, DSYNC−A, DSYNC+B,

DSYNC−B to AGND

−ꢀ.3 V to DRVDD + ꢀ.± V

Typical θ_JAis specified for a 4-layer PCB with a solid ground

plane. As shown Table 7, airflow improves heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes, reduces θ_JA.

ENVIRONMENTAL

Operating Temperature Range

(Ambient)

Maximum Junction Temperature

Under Bias

−4ꢀ°C to +85°C

15ꢀ°C

Storage Temperature Range

(Ambient)

−65°C to +15ꢀ°C

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. D | Page 1ꢀ of 44

Data Sheet

AD9644

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

36 VCMA

DNC

34 DNC

VCMB

AVDD

DNC

35

4

5

6

7

8

9

10

11

12

AVDD

CLK+

CLK–

AVDD

SYNC

AVDD

DRGND

DRVDD

DNC

33 PDWN

AD9644

TOP

VIEW

32

31

30

29

DNC

CSB

SCLK

SDIO

(Not to Scale)

28 DRVDD

27 DRVDD

26

DRGND

25 DNC

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD

MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 4. LFCSP Pin Configuration (Top View)

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

11, 15, ±±, ±7, ±8

±, 4, 7, 9, 37, 38, 41,

4±, 43, 44, 47, 48

DRVDD

AVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

Analog Power Supply (1.8 V Nominal).

3, 1±, ±5, 3±, 34, 35

1ꢀ, 16, ±1, ±6

DNC

DRGND

Do Not Connect.

Digital Driver Supply Ground.

Driver

Ground

ꢀ

AGND,

Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog

ground for the part. This exposed pad must be connected to ground for

proper operation.

ADC Analog

4ꢀ

39

45

46

36

1

5

6

VIN+A

VIN−A

VIN+B

VIN−B

VCMA

VCMB

CLK+

Input

Output

Input

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Differential Analog Input Pin (+) for Channel B.

Differential Analog Input Pin (−) for Channel B.

Common-Mode Level Bias Output for Channel A Analog Input.

Common-Mode Level Bias Output for Channel B Analog Input.

ADC Clock Input—True.

CLK−

ADC Clock Input—Complement.

Digital Input

8

±4

SYNC

DSYNC+A

Input

Input Clock Divider Synchronization Pin.

Active Low JESD±ꢀ4A LVDS Channel A SYNC Input—True/JESD±ꢀ4A CMOS

Channel A SYNC Input.

±3

14

DSYNC−A

DSYNC+B

Input

Active Low JESD±ꢀ4A LVDS Channel A SYNC Input—Complement.

Active Low JESD±ꢀ4A LVDS Channel B SYNC Input—True/JESD±ꢀ4A CMOS

Channel A SYNC Input.

13

DSYNC−B

Input

Active Low JESD±ꢀ4A LVDS Channel B SYNC Input—Complement.

Rev. D | Page 11 of 44

AD9644

Data Sheet

Pin No.

Mnemonic

Type

Description

Digital Outputs

±ꢀ

19

18

17

DOUT+A

DOUT−A

DOUT+B

DOUT−B

Output

Channel A CML Output Data—True.

Channel A CML Output Data—Complement.

Channel B CML Output Data—True.

Channel B CML Output Data—Complement.

SPI Control

3ꢀ

±9

31

SCLK

SDIO

CSB

Input

SPI Serial Clock.

Input/Output SPI Serial Data Input/Output.

Input

SPI Chip Select (Active Low).

ADC Configuration

33

PDWN

Power-Down Input. Using the SPI interface, this input can be configured as

power-down or standby.

Rev. D | Page 1± of 44

Data Sheet

AD9644

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, DCS enabled, 1.75 V p-p differential input, VIN = −1.0 dBFS, and 32k sample,

T_A= 25°C, unless otherwise noted.

0

–20

0

80MSPS

10.1MHz @ –1dBFS

SNR = 73.0dB (74.0dBFS)

SFDR = 95dBc

140.3MHz @ –1dBFS

SNR = 72.2dB (73.2dBFS)

SFDR = 94.0dBc

–20

–40

–60

–80

THIRD HARMONIC

–100

–120

–140

–100

–120

–140

0

10

20

30

40

0

10

20

FREQUENCY (MHz)

30

40

FREQUENCY (MHz)

Figure 5. AD9644-80 Single-Tone FFT with f_IN= 10.1 MHz

Figure 8. AD9644-80 Single-Tone FFT with f_IN= 140.1 MHz

0

80MSPS

30.1MHz @ –1dBFS

SNR = 72.7dB (73.7dBFS)

SFDR = 94dBc

180.1MHz @ –1dBFS

SNR = 71.6dB (72.6dBFS)

SFDR = 93dBc

–20

–40

–20

–40

–60

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–140

–100

–120

–140

0

10

20

FREQUENCY (MHz)

30

0

10

20

FREQUENCY (MHz)

30

40

Figure 6. AD9644-80 Single-Tone FFT with f_IN= 30.1 MHz

Figure 9. AD9644-80 Single-Tone FFT with f_IN= 180.1 MHz

0

80MSPS

70.1MHz @ –1dBFS

SNR = 72.5dB (73.5dBFS)

SFDR = 94.0dBc

220.1MHz @ –1dBFS

SNR = 71.1dB (72.1dBFS)

SFDR = 92dBc

–20

–40

–20

–40

–60

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–140

–100

–120

–140

0

10

20

FREQUENCY (MHz)

30

0

10

20

FREQUENCY (MHz)

30

40

Figure 7. AD9644-80 Single-Tone FFT with f_IN= 70.1 MHz

Figure 10. AD9644-80 Single-Tone FFT with f_IN= 220.1 MHz

Rev. D | Page 13 of 44

AD9644

Data Sheet

100

95

90

85

80

75

70

65

120

100

80

60

40

20

0

SNR @ –40°C

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

0

50

100

150

200

250

INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 14. AD9644-80 Single-Tone SNR/SFDR vs. Input Frequency (f_IN) and

Temperature with 2.0 V p-p Full-Scale, f_S= 80 MSPS

Figure 11. AD9644-80 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

with f_IN= 10.1 MHz, f_S= 80 MSPS

0

120

100

80

–20

–40

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

–60

–80

SFDR (dBc)

IMD3 (dBc)

SFDR (dBFS)

IMD3 (dBFS)

60

40

20

–100

–120

0

–90

–78

–66

–54

–42

–30

–18

–6

INPUT AMPLITUDE (dBFS)

Figure 12. AD9644-80 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

Figure 15. AD9644-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

with f_IN= 180 MHz, f_S= 80 MSPS

with f_IN1= 29.9 MHz, f_IN2= 32.9 MHz, f_S= 80 MSPS

100

95

0

–20

–40

90

SNR @ –40°C

SFDR @ –40°C

85

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

–60

–80

SFDR (dBc)

IMD3 (dBc)

SFDR (dBFS)

IMD3 (dBFS)

80

75

70

65

–100

–120

0

50

100

150

200

250

–90

–78

–66

–54

–42

–30

–18

–6

INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 13. AD9644-80 Single-Tone SNR/SFDR vs. Input Frequency (f_IN) and

Temperature with 1.75 V p-p Full-Scale, f_S= 80 MSPS

Figure 16. AD9644-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

with f_IN1= 169.1 MHz, f_IN2= 172.1 MHz, f_S= 80 MSPS

Rev. D | Page 14 of 44

Data Sheet

AD9644

0

14,000

12,000

10,000

8000

80MSPS

29.9MHz @ –7dBFS

32.9MHz @ –7dBFS

SFDR = 94.4dBc (101.4dBFS)

–20

–40

–60

6000

–80

4000

–100

–120

–140

2000

0

10

20

FREQUENCY (MHz)

30

40

N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4

OUTPUT CODE

Figure 17. AD9644-80 Two-Tone FFT with f_IN1= 29.9 MHz and f_IN2= 32.9 MHz

Figure 20. AD9644-80 Grounded Input Histogram

0

1.0

0.8

80MSPS

169.1MHz @ –7dBFS

–20

–40

172.1MHz @ –7dBFS

SFDR = 91.9dBc (98.9dBFS)

0.6

0.4

0.2

–60

0

–80

–0.2

–0.4

–0.6

–0.8

–1.0

–100

–120

–140

0

10

20

FREQUENCY (MHz)

30

40

0

200

400

600

800

1000 1200 1400 1600

OUTPUT CODE

Figure 18. AD9644-80 Two-Tone FFT with f_IN1= 169.1 MHz and

f_IN2= 172.1 MHz

Figure 21. AD9644-80 INL with f_IN= 30.3 MHz

100

0.50

0.25

0

95

90

85

80

75

70

SNR CHANNEL B

SFDR CHANNEL B

SNR CHANNEL A

SFDR CHANNEL A

–0.25

–0.50

45

50

55

60

65

70

75

80

0

2000 4000 6000 8000 10,000 12,000 14,000 16,000

OUTPUT CODE

SAMPLE RATE (MSPS)

Figure 19. AD9644-80 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 70. MHz

Figure 22. AD9644-80 DNL with f_IN= 30.3 MHz

Rev. D | Page 15 of 44

AD9644

Data Sheet

0

–20

–40

–60

0

–20

–40

–60

155MSPS

10.1MHz @ –1dBFS

SNR = 70.9dB (71.9dBFS)

SFDR = 94dBc

140.1MHz @ –1dBFS

SNR = 70.5dB (71.5dBFS)

SFDR = 92dBc

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–80

–100

–120

–140

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

Figure 23. AD9644-155 Single-Tone FFT with f_IN= 10.1 MHz

Figure 26. AD9644-155 Single-Tone FFT with f_IN= 140.1 MHz

0

155MSPS

30.1MHz @ –1dBFS

SNR = 70.8dB (71.8dBFS)

SFDR = 93dBc

180.1MHz @ –1dBFS

SNR = 70.4dB (71.4dBFS)

SFDR = 92dBc

–20

–40

–60

–40

–60

THIRD

HARMONIC

THIRD HARMONIC

SECOND

HARMONIC

–80

–100

–120

–140

–80

–100

–120

–140

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

Figure 24. AD9644-155 Single-Tone FFT with f_IN= 30.1 MHz

Figure 27. AD9644-155 Single-Tone FFT with f_IN= 180.1 MHz

0

155MSPS

70.1MHz @ –1dBFS

SNR = 70.7dB (71.7dBFS)

SFDR = 92dBc

220.1MHz @ –1dBFS

SNR = 70.0dB (71.0dBFS)

SFDR = 90dBc

–20

–40

–60

–40

–60

THIRD HARMONIC

–80

–100

–120

–140

–80

–100

–120

–140

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

Figure 25. AD9644-155 Single-Tone FFT with f_IN= 70.1 MHz

Figure 28. AD9644-155 Single-Tone FFT with f_IN= 220.1 MHz

Rev. D | Page 16 of 44

Data Sheet

AD9644

120

100

80

60

40

20

0

100

95

SNR @ –40°C

SFDR (dBFS)

SNR (dBFS)

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

90

85

SFDR (dBc)

80

75

70

65

SNR (dBc)

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

50

100

150

200

250

300

INPUT AMPLITUDE (dBFS)

INPUT FREQUENCY (MHz)

Figure 29. AD9644-155 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

Figure 32. AD9644-155 Single-Tone SNR/SFDR vs. Input Frequency (f_IN) and

Temperature with 2.0 V p-p Full-Scale, f_S= 80 MSPS

with f_IN= 10.1 MHz, f_S= 80 MSPS

120

0

–20

–40

SFDR (dBFS)

100

80

SNR (dBFS)

SFDR (dBc)

60

–60

SFDR (dBc)

IMD3 (dBc)

40

–80

SNR (dBc)

20

–100

SFDR (dBFS)

IMD3 (dBFS)

0

–90

–120

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

–78

–66

–54

–42

–30

–18

–6

INPUT AMPLITUDE (dBFS)

Figure 30. AD9644-155 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN

)

Figure 33. AD9644-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

with f_IN= 180 MHz, f_S= 80 MSPS

with f_IN1= 29.9 MHz, f_IN2= 32.9 MHz, f_S= 80 MSPS

100

95

0

–20

–40

90

SNR @ –40°C

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

85

SFDR (dBc)

–60

IMD3 (dBc)

80

75

70

65

–80

SFDR (dBFS)

IMD3 (dBFS)

–100

–120

–90

–78

–66

–54

–42

–30

–18

–6

0

50

100

150

200

250

300

INPUT AMPLITUDE (dBFS)

INPUT FREQUENCY (MHz)

Figure 34. AD9644-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN

)

Figure 31. AD9644-155 Single-Tone SNR/SFDR vs. Input Frequency (f_IN) and

Temperature with 1.75 V p-p Full-Scale, f_S= 80 MSPS

with f_IN1= 169.1 MHz, f_IN2= 172.1 MHz, f_S= 80 MSPS

Rev. D | Page 17 of 44

AD9644

Data Sheet

0

–20

–40

–60

4000

3500

155MSPS

29.9MHz @ –7dBFS

32.9MHz @ –7dBFS

SFDR = 89.8dBc (96.8dBFS)

3000

2500

2000

1500

–80

–100

–120

1000

500

0

–140

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

N – 5 N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4 N + 5

OUTPUT CODE

Figure 35. AD9644-155 Two-Tone FFT with f_IN1= 29.9 MHz and f_IN2= 32.9 MHz

Figure 38. AD9644-155 Grounded Input Histogram

0

1

0.8

155MSPS

169.1MHz @ –7dBFS

–20

–40

–60

172.1MHz @ –7dBFS

SFDR = 89.1dBc (96.1dBFS)

0.6

0.4

0.2

0

–80

–100

–120

–140

–0.2

–0.4

–0.6

–0.8

–1

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

0

2000 4000 6000

8000 10000 12000 14000 16000

OUTPUT CODE

Figure 36. AD9644-155 Two-Tone FFT with f_IN1= 169.1 MHz and

f_IN2= 172.1 MHz

Figure 39. AD9644-155 INL with f_IN= 30.3 MHz

100

0.5

0.25

0

95

90

85

SNR, CHANNEL B

SFDR, CHANNEL B

SNR, CHANNEL A

80

SFDR, CHANNEL A

–0.25

–0.5

75

70

50

65

80

95

110

125

140

155

0

2000 4000 6000

8000 10000 12000 14000 16000

SAMPLE RATE (MSPS)

OUTPUT CODE

Figure 37. AD9644-155 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 70. MHz

Figure 40. AD9644-155 DNL with f_IN= 30.3 MHz

Rev. D | Page 18 of 44

Data Sheet

AD9644

EQUIVALENT CIRCUITS

AVDD

350Ω

30kΩ

SCLK

OR

PDWN

VIN

Figure 41. Equivalent Analog Input Circuit

Figure 45. Equivalent SCLK or PDWN Input Circuit

AVDD

30kΩ

350Ω

0.9V

CSB

15kΩ

CLK+

CLK–

Figure 42. Equivalent Clock Input Circuit

Figure 46. Equivalent CSB Input Circuit

DRVDD

AVDD

4mA

R

TERM

V

DOUT±A/B

DSYNC±A/B

OR SYNC

CM

0.9V

16kΩ

0.9V

Figure 43. Digital CML Output

Figure 47. Equivalent SYNC and DSYNC Input Circuit

DRVDD

350Ω

30kΩ

SDIO

Figure 44. Equivalent SDIO Circuit

Rev. D | Page 19 of 44

AD9644

Data Sheet

THEORY OF OPERATION

A small resistor in series with each input can help reduce the

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC input; therefore,

the precise values are dependent on the application.

The AD9644 dual-core analog-to-digital converter (ADC) can

be used for diversity reception of signals, in which the ADCs are

operating identically on the same carrier but from two separate

antennae. The ADCs can also be operated with independent

analog inputs. The user can sample any f_S/2 frequency segment

from dc to 250 MHz, using appropriate low-pass or band-pass

filtering at the ADC inputs with little loss in ADC performance.

In intermediate frequency (IF) undersampling applications, any

shunt capacitors or series resistors should be reduced since the

input sample capacitor is unbuffered. In combination with the

driving source impedance, the shunt capacitors limit the input

bandwidth. Refer to the AN-742 Application Note, Frequency

Domain Response of Switched-Capacitor ADCs; the AN-827

Application Note, A Resonant Approach to Interfacing Amplifiers

to Switched-Capacitor ADCs; and the Analog Dialog article,

“Transformer-Coupled Front-End for Wideband A/D

Converters,” for more information on this subject (refer to

www.analog.com).

In nondiversity applications, the AD9644 can be used as a base-

band or direct downconversion receiver, in which one ADC is

used for I input data, and the other is used for Q input data.

Synchronization capability is provided to allow synchronized

timing between multiple devices.

Programming and control of the AD9644 are accomplished

using a 3-wire SPI-compatible serial interface.

ADC ARCHITECTURE

The AD9644 architecture consists of a dual front-end sample-

and-hold circuit, followed by a pipelined, switched-capacitor

ADC. The quantized outputs from each stage are combined into

a final 14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate on a new input

sample and the remaining stages to operate on the preceding

samples. Sampling occurs on the rising edge of the clock.

BIAS

S

C

FB

C

S

VIN+

VIN–

C

PAR1

C

PAR2

H

S

C

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The MDAC magnifies the difference between the

recon-structed DAC output and the flash input for the next

stage in the pipeline. One bit of redundancy is used in each stage

to facilitate digital correction of flash errors. The last stage simply

consists of a flash ADC.

S

C

FB

C

PAR1

PAR2

S

BIAS

Figure 48. Switched-Capacitor Input

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched, and the inputs should be

differentially balanced.

The input stage of each channel contains a differential sampling

circuit that can be ac- or dc-coupled in differential or single-

ended modes. The output staging block aligns the data, corrects

errors, and passes the data to the output buffers. The output buffers

are powered from a separate supply, allowing digital output noise

to be separated from the analog core. During power-down, the

output buffers go into a high impedance state.

Input Common Mode

The analog inputs of the AD9644 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that VCM = 0.5 × AVDD (or

0.9 V) is recommended for optimum performance. An on-

board common-mode voltage reference is included in the

design and is available from the VCMA and VCMB pins. Using

the VCMA and VCMB outputs to set the input common mode

is recommended. Optimum performance is achieved when the

common-mode voltage of the analog input is set by the VCMA

and VCMB pin voltages (typically 0.5 × AVDD). The VCMA

and VCMB pins must be decoupled to ground by a 0.1 μF

capacitor. This decoupling capacitor should be placed close

to the pin to minimize the series resistance and inductance

between the part and this capacitor.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9644 is a differential switched-

capacitor circuit that has been designed for optimum performance

while processing a differential input signal.

The clock signal alternatively switches the input between sample

mode and hold mode (see Figure 48). When the input is switched

into sample mode, the signal source must be capable of charging

the sample capacitors and settling within ½ of a clock cycle.

Rev. D | Page ±ꢀ of 44

Data Sheet

AD9644

The signal characteristics must be considered when selecting

Differential Input Configurations

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can also

cause core saturation, which leads to distortion.

Optimum performance is achieved while driving the AD9644 in a

differential input configuration. For baseband applications, the

AD8138, ADA4937-2, and ADA4938-2 differential drivers provide

excellent performance and a flexible interface to the ADC.

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9644. For applications in

which SNR is a key parameter, differential double balun coupling

is the recommended input configuration (see Figure 51). In this

configuration, the input is ac-coupled and the VCM is provided

to each input through a 33 Ω resistor. These resistors compensate

for losses in the input baluns to provide a 50 Ω impedance to

the driver.

The output common-mode voltage of the ADA4938-2 is easily

set with the VCM pin of the AD9644 (see Figure 49), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

15pF

200Ω

33Ω

5pF

15Ω

90Ω

VIN–

VIN+

AVDD

ADC

VCM

76.8Ω

VIN

In the double balun and transformer configurations, the value of

the input capacitors and resistors is dependent on the input fre-

quency and source impedance. Based on these parameters the

value of the input resistors and capacitors may need to be

adjusted or some components may need to be removed. Table 9

displays recommended values to set the RC network for different

input frequency ranges. However, these values are dependent

on the input signal and bandwidth and should be used only as a

starting guide. Note that the values given in Table 9 are for each

R1, R2, C2, and R3 component shown in Figure 50 and Figure 51.

ADA4938-2

0.1µF

33Ω

15pF

15Ω

120Ω

200Ω

Figure 49. Differential Input Configuration Using the ADA4938-2

For baseband applications in which SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 50. To bias the

analog input, the VCM voltage can be connected to the center

tap of the secondary winding of the transformer.

Table 9. Example RC Network

C2

Frequency

Range

(MHz)

R1

Series

(Ω)

C1

R2

Series

(Ω)

C2

Shunt

(pF)

R3

Shunt

(Ω)

R3

Differential

(pF)

R2

VIN+

R1

ꢀ to 1ꢀꢀ

33

15

8.±

3.9

ꢀ

8.±

49.9

2V p-p

49.9Ω

C1

R1

ADC

VCM

1ꢀꢀ to ±5ꢀ

Open

R2

VIN–

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use the AD8376 variable gain

amplifier. An example drive circuit including a band-pass filter

is shown in Figure 52. See the AD8376 data sheet for more

information.

0.1µF

R3

C2

Figure 50. Differential Transformer-Coupled Configuration

C2

R3

0.1µF

R1

R2

VIN+

VIN–

2V p-p

33Ω

P

S

P

C1

R1

ADC

A

0.1µF

VCM

R3

C2

Figure 51. Differential Double Balun Input Configuration

Rev. D | Page ±1 of 44

AD9644

Data Sheet

1000pF 180nH 220nH

1µH

165Ω

VPOS

15pF

VCM

1nF

AD8376

5.1pF 3.9pF

165Ω

301Ω

1nF

1µH

68nH

AD9644

180nH 220nH

1000pF

NOTES

1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS

WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).

Figure 52. Differential Input Configuration Using the AD8376 (Filter Values Shown Are for a 20 MHz Bandwidth Filter Centered at 140 MHz)

secondary limit clock excursions into the AD9644 to

approximately 0.8 V p-p differential.

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9644.

The input full scale range can be adjusted through the SPI port by

adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be

used to change the full scale between 1.383 V p-p and 2.087 V p-p

in 0.022 V steps, as shown in Table 17.

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9644 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

CLOCK INPUT CONSIDERATIONS

®

Mini-Circuits

ADC

ADT1-1WT, 1:1Z

For optimum performance, the AD9644 sample clock inputs,

CLK+ and CLK−, should be clocked with a diﬀerential signal.

The signal is typically ac-coupled into the CLK+ and CLK− pins by

means of a transformer or a passive component configuration.

These pins are biased internally (see Figure 53) and require no

external bias. If the inputs are floated, the CLK− pin is pulled low

to prevent inadvertent clocking.

0.1µF

50Ω

0.1µF

XFMR

CLOCK

INPUT

CLK+

CLK–

100Ω

0.1µF

SCHOTTKY

DIODES:

HSMS2822

0.1µF

Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz)

AVDD

ADC

0.9V

1nF

50Ω

1nF

0.1µF

CLOCK

INPUT

CLK+

CLK–

CLK+

CLK–

2pF

SCHOTTKY

DIODES:

HSMS2822

Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz)

Figure 53. Equivalent Clock Input Circuit

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 56. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/AD9520

/AD9522 clock drivers offer excellent jitter performance.

Clock Input Options

The AD9644 has a very flexible clock input structure. Clock input

can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless

of the type of signal being used, clock source jitter is of the most

concern, as described in the Jitter Considerations section. The

minimum conversion rate of the AD9644 is 40 MSPS. At clock

rates below 40 MSPS, dynamic performance of the AD9644 can

degrade.

0.1µF

CLOCK

INPUT

CLK+

ADC

AD95xx

PECL DRIVER

100Ω

0.1µF

50kΩ

0.1µF

Figure 54 and Figure 55 show two preferred methods for clocking

the AD9644 (at clock rates up to 640 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using either an RF balun or an RF transformer.

CLOCK

INPUT

CLK–

240Ω

50kΩ

Figure 56. Differential PECL Sample Clock (Up to 640 MHz)

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 640 MHz, and the RF transformer is

recommended for clock frequencies from 40 MHz to 200 MHz.

The back-to-back Schottky diodes across the transformer/balun

Rev. D | Page ±± of 44

Data Sheet

AD9644

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 57. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/

AD9518/AD9520/AD9522 clock drivers offer excellent jitter

performance.

Jitter in the rising edge of the input is still of paramount concern

and is not easily reduced by the internal stabilization circuit. The

loop has a time constant associated with it that must be considered

in applications in which the clock rate can change dynamically.

A wait time of 1.5 μs to 5 μs is required after a dynamic clock

frequency increase or decrease before the DCS loop is relocked to

the input signal. During the time period that the loop is not

locked, the DCS loop is bypassed, and internal device timing is

dependent on the duty cycle of the input clock signal. In such

applications, it may be appropriate to disable the duty cycle

stabilizer. In all other applications, enabling the DCS circuit is

recommended to maximize ac performance.

0.1µF

CLOCK

INPUT

CLK+

ADC

AD95xx

LVDS DRIVER

100Ω

0.1µF

50kΩ

CLOCK

INPUT

CLK–

50kΩ

Figure 57. Differential LVDS Sample Clock (Up to 640 MHz)

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. For inputs near full scale, the degradation in

SNR from the low frequency SNR (SNR_LF) at a given input

frequency (f_INPUT) due to jitter (t_JRMS) can be calculated by

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended CMOS signal. In such applica-

tions, the CLK+ pin should be driven directly from a CMOS gate,

and the CLK− pin should be bypassed to ground with a 0.1 ꢀF

capacitor (see Figure 58).

SNR_HF= −10 log[(2π × f_INPUT× t_JRMS)²+ 10 ^{(SNR /10)}

]

LF

V

In the equation, the rms aperture jitter represents the clock

input jitter specification. IF undersampling applications are

particularly sensitive to jitter, as illustrated in Figure 59. The

measured curve in Figure 59 was taken using an ADC clock source

with approxi-mately 65 fs of jitter, which combines with the 125 fs

of jitter inherent in the AD9644 to produce the result shown.

75

CC

OPTIONAL

100Ω

0.1µF

1kΩ

AD95xx

CMOS DRIVER

CLOCK

INPUT

CLK+

ADC

1

50Ω

CLK–

0.1µF

1

50Ω RESISTOR IS OPTIONAL.

Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

70

Input Clock Divider

The AD9644 contains an input clock divider with the ability to

divide the input clock by integer values between 1 and 8. For

divide ratios other than 1 the duty cycle stabilizer is automatically

enabled.

0.05ps

0.2ps

0.5ps

1ps

1.5ps

65

60

55

50

MEASURED

The AD9644 clock divider can be synchronized using the external

SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock

divider to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

causes the clock divider to reset to its initial state. This synchro-

nization feature allows multiple parts to have their clock dividers

aligned to guarantee simultaneous input sampling.

1

10

100

1000

INPUT FREQUENCY (MHz)

Figure 59. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases in

which aperture jitter may affect the dynamic range of the AD9644.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. The AD9644 requires a tight

tolerance on the clock duty cycle to maintain dynamic

performance characteristics.

The AD9644 contains a duty cycle stabilizer (DCS) that retimes

the nonsampling (falling) edge, providing an internal clock signal

with a nominal 50% duty cycle. This allows the user to provide

a wide range of clock input duty cycles without affecting the

perfor-mance of the AD9644. Noise and distortion

performance are nearly flat for a wide range of duty cycles with

the DCS enabled.

Refer to the AN-501 Application Note and the AN-756

Application Note (visit www.analog.com) for more information

about jitter performance as it relates to ADCs.

Rev. D | Page ±3 of 44

AD9644

Data Sheet

By asserting PDWN (either through the SPI port or by asserting

the PDWN pin high), the AD9644 is placed in power-down mode.

In this state, the ADC typically dissipates 15 mW. During power-

down, the output drivers are placed in a high impedance state.

Asserting the PDWN pin low returns the AD9644 to its normal

operating mode.

CHANNEL/CHIP SYNCHRONIZATION

The AD9644 has a SYNC input that offers the user flexible

synchronization options for synchronizing the clock divider.

The clock divider sync feature is useful for guaranteeing synchro-

nized sample clocks across multiple ADCs. The input clock

divider can be enabled to synchronize on a single occurrence of

the SYNC signal or on every occurrence.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

clock, and JESD204A outputs . Internal capacitors are discharged

when entering power-down mode and then must be recharged

when returning to normal operation.

The SYNC input is internally synchronized to the sample clock;

however, to ensure that there is no timing uncertainty between

multiple parts, the SYNC input signal should be externally syn-

chronized to the input clock signal, meeting the setup and hold

times shown in Table 5. The SYNC input should be driven

using a single-ended CMOS-type signal.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered and

the JESD204A outputs running when faster wake-up times are

required.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 60 and Figure 61, the power dissipated by

the AD9644 varies with its sample rate (AD9644-80 shown).

DIGITAL OUTPUTS

JESD204A Transmit Top Level Description

The data in Figure 60 and Figure 61 was taken in JESD204A

serial output mode, using the same operating conditions as those

used for the Typical Performance Characteristics.

The AD9644 digital output complies with the JEDEC Standard

No. 204A (JESD204A), which describes a serial interface for

data converters. JESD204A uses 8B/10B encoding as well as

optional scrambling. K28.5 and K28.7 comma symbols are used

for frame synchronization and the K28.3 control symbol is used

for lane synchronization. The receiver is required to lock onto

the serial data stream and recover the clock with the use of a

PLL. For details on the output interface, users are encouraged

to refer to the JESD204A standard.

0.5

0.4

0.3

0.2

0.1

0

0.25

0.20

0.15

0.10

0.05

0

TOTAL POWER

IAVDD

The JESD204A transmit block is used to multiplex data from

the two analog-to-digital converters onto two independent

JESD204A Links. Each JESD204A Link is considered a separate

instance of the JESD204A specification, has an independent

DSYNC signal, and contains one or more lanes. Note that the

JESD204 specification only allows one lane per link, while the

JESD204A specification adds multilane support through an

alignment procedure.

IDRVDD

40

50

60

70

80

ENCODE FREQUENCY (MSPS)

Figure 60. AD9644-80 Power and Current vs. Encode Frequency with f_IN

10.1 MHz

=

Each JESD204A Link is described according to the following

nomenclature:

0.60

0.50

0.40

0.30

0.20

0.10

0

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

TOTAL POWER



S = samples transmitted/single converter/frame cycle

M = number of converters/converter device (link)

L = number of lanes/converter device (link)

N = converter resolution

N’ = total number of bits per sample

CF = number of control words/frame clock

cycle/converter device (link)

I

AVDD

I

DRVDD



CS = number of control bits/conversion sample

K = number of frames per multiframe

HD = high density mode

F = octets/frame

C = control bit (overrange, overflow, underflow)

T = tail bit

80

90

100

110

120

130

140

150

ENCODE FREQUENCY (MSPS)

Figure 61. AD9644-155 Power and Current vs. Encode Frequency

with f_IN= 10.1 MHz

SCR = scrambler enable/disable

FCHK = checksum

Rev. D | Page ±4 of 44

Data Sheet

AD9644

Figure 62 shows a simplified block diagram of the AD9644

JESD204A links. The two links each have a primary and a

secondary converter input and lane output. By default, the

primary Input 0 of Link A is ADC Converter A and its primary

lane Output 0 is sent on output Lane A. The primary Input 0 of

Link B is ADC Converter B and its primary lane Output 0 is

sent on output Lane B. Muxes throughout the design are used

to enable secondary inputs/outputs and swap lane outputs for

other configurations. The JESD204A block for AD9644 is

designed to support the configurations described in Table 10

via a quick configuration register at Address 0x5E accessible via

the SPI bus.

AD9644, the 14-bit converter word is broken into two octets.

Bit 13 through Bit 6 are in the first octet. The second octet

contains Bit 5 through Bit 0 and two tail bits. The MSB of the tail

bits can also be used to indicate an out-of-range condition. The

tail bits are configured using the JESD204A link control

Register 1, Address 0x60, Bit 6.

The two resulting octets are optionally scrambled and encoded

into their corresponding 10-bit code. The scrambling function

is controlled by the JESD204A scrambling and lane configuration

register, Address 0x06E, Bit 7. Figure 63 shows how the 14-bit

data is taken from the ADC, the tail bits are added, the two

octets are scrambled, and how the octets are encoded into two

10-bit symbols. Figure 63 illustrates the default data format.

In addition to the default mode, the user can program the AD9644

to output both ADC channels on a single lane (F = 4). This mode

allows use of a single high speed data lane, which simplifies board

layout and connector requirements. In Figure 64 the ADC A

output is represented by Word 0 and the ADC B output by Word

1. The third output mode utilizes a single link to support both

channels. In single link mode, the DSYNCA pin is used to support

both outputs. This mode is useful for optimal alignment between

the output channels.

The scrambler uses a self-synchronizing polynomial-based

algorithm defined by the equation 1 + x¹⁴+ x¹⁵. The descrambler

in the receiver should be a self-synchronizing version of the

scrambler polynomial. Figure 65 shows the corresponding

receiver data path.

Refer to JEDEC Standard No. 204A-April 2008, Section 5.1, for

complete transport layer and data format details and Section

5.2 for a complete explanation of scrambling and descrambling.

The 8B/10B encoding works by taking eight bits of data (an octet)

and encoding them into a 10-bit symbol. By default in the

AD9644

DUAL ADC

LINK A

~SYNC

CONVERTER A

INPUT

CONVERTER A

SAMPLE

LANE 0

LANE 1

LANE 0

PRIMARY

LANE

A

B

LANE A

CONVERTER A

CONVERTER

INPUT [0]

OUTPUT [0]

JESD204A LINK A

(M = 0, 1, 2; L = 0, 1, 2)

SECONDARY

CONVERTER

INPUT [1]

SECONDARY

LANE

OUTPUT [1]

LANE

MUX

(SPI

REGISTER

0x5F)

A

B

SECONDARY

CONVERTER

INPUT [1]

SECONDARY

LANE

OUTPUT [1]

JESD204A LINK B

(M = 0, 1, 2; L = 0, 1, 2)

CONVERTER B

INPUT

LANE B

PRIMARY

CONVERTER

INPUT [0]

PRIMARY

LANE

OUTPUT [0]

CONVERTER B

SAMPLE

LINK B

~SYNC

Figure 62. AD9644 Transmit Link Simplified Block Diagram

Rev. D | Page ±5 of 44

AD9644

Data Sheet

Table 10. AD9644 JESD204A Typical Configurations

AD9644 Configuration

JESK204A Link A Settings

M = 1; L = 1; S = 1; F = ±

N’ = 16; CF = ꢀ

JESD204A Link B Settings

M = 1; L = 1; S = 1; F = ±

N’ = 16; CF = ꢀ

Comments

Maximum sample rate = 8ꢀ MSPS or 155 MSPS

Two Converters

Two JESD±ꢀ4A Links

One Lane Per Link

CS = ꢀ, 1, ±; K = N/A

SCR = ꢀ, 1; HD = ꢀ

M = ±; L = ±; S = 1; F = ±

N’ = 16

CS = ꢀ, 1, ±; K = N/A

SCR = ꢀ, 1; HD = ꢀ

Disabled

Maximum sample rate = 8ꢀ MSPS or 155 MSPS

Required for applications needing two aligned

samples (I/Q applications)

Two Converters

One JESD±ꢀ4A Link

Two Lanes Per Link

CF = ꢀ; CS = ꢀ, 1, ±

K = 16; SCR = ꢀ, 1;

HD = ꢀ

M = ±; L = 1; S = 1; F = 4

N’ = 16

Disabled

Maximum sample rate = 8ꢀ MSPS

Two Converters

One JESD±ꢀ4A Link

One Lane Per Link

CF = ꢀ; CS = ꢀ, 1, ±

K = 8; SCR = ꢀ, 1; HD = ꢀ

DATA

FROM

ADC

FRAME

ASSEMBLER

(ADD TAIL BITS)

OPTIONAL

8B/10B

ENCODER

TO

RECEIVER

SCRAMBLER

14

15

1 + x + x

Figure 63. AD9644 ADC Output Data Path

WORD 0[13:6]

SYMBOL 0[9:0]

FRAME 0

FRAME 1

WORD 0[5:0],TAIL BITS[1:0]

WORD 1[13:6]

SYMBOL 1[9:0]

SYMBOL 2[9:0]

SYMBOL 3[9:0]

TIME

WORD 1[5:0], TAIL BITS[1:0]

Figure 64. AD9644 14-Bit Data Transmission with Tail Bits

OPTIONAL

8B/10B

DECODER

FRAME

ALIGNMENT

DATA

OUT

FROM

TRANSMITTER

DESCRAMBLER

14 15

1 + x + x

Figure 65. Required Receiver Data Path

Initial Frame Synchronization

The DSYNC input can be driven either from a differential

LVDS source or by using a single-ended CMOS driver circuit.

The DSYNC input default to LVDS mode but can be set to

CMOS mode by setting Bit 4 in SPI Address 0x61. If it is driven

differentially from an LVDS source, then an external 100 Ω

termination resistor should be provided. If the DSYNC input is

driven single-ended then the CMOS signal should be connected

to the DSYNC+ signal and the DSYNC− signal should be left

disconnected.

The serial interface must synchronize to the frame boundaries

before data can be properly decoded. The JESD204A standard

has a synchronization routine to identify the frame boundary.

When the DSYNC pin is taken low for at least two clock cycles,

the AD9644 enters the code group synchronization mode. The

AD9644 transmits the K28.5 comma symbol until the receiver

achieves synchronization. The receiver should then deassert the

sync signal (take DSYNC high) and the AD9644 begins the initial

lane alignment sequence (when enabled through Bits[3:2] of

Address 0x60) and subsequently begins transmitting sample

data. The first non-K28.5 symbol corresponds to the first octet

in a frame.

Rev. D | Page ±6 of 44

Data Sheet

AD9644

Table 11. AD9644 JESD204A Frame Alignment Monitoring and Correction Replacement Characters

Last Octet in

Multiframe

Scrambling Lane Synchronization Character to be Replaced

Replacement Character

K±8.7 (ꢀxFC)

K±8.3 (ꢀx7C)

Off

On

Off

On

Off

Last octet in frame repeated from previous frame

Last octet in frame equals D±8.7 (ꢀxFC)

Last octet in frame equals D±8.3 (ꢀx7C)

Last octet in frame equals D±8.7 (ꢀx7C)

No

Yes

Not applicable K±8.7 (ꢀxFC)

No

Yes

K±8.7 (ꢀxFC)

K±8.3 (ꢀx7C)

Not applicable K±8.7 (ꢀxFC)

common mode of the digital output automatically biases itself

to half the supply of the receiver (that is, the common-mode

voltage is 0.9 V for a receiver supply of 1.8 V) if dc-coupled

connecting is used (see Figure 67). For receiver logic that is not

within the bounds of the DRVDD supply, an ac-coupled

connection should be used. Simply place a 0.1 μF capacitor on

each output pin and derive a 100 Ω differential termination

close to the receiver side.

Frame and Lane Alignment Monitoring and Correction

Frame alignment monitoring and correction is part of the

JESD204A specification. The 14-bit word requires two octets to

transmit all the data. The two octets (MSB and LSB), where

F = 2, make up a frame. During normal operating conditions

frame alignment is monitored via alignment characters, which

are inserted under certain conditions at the end of a frame.

Table 11 summarizes the conditions for character insertion

along with the expected characters under the various operation

modes. If lane synchronization is enabled, the replacement

character value depends on whether the octet is at the end of a

frame or at the end of a multiframe.

If there is no far-end receiver termination or if there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than six inches and that the differential output traces be

close together and at equal lengths.

Based on the operating mode, the receiver can ensure that it is

still synchronized to the frame boundary by correctly receiving

the replacement characters.

V

RXCM

100Ω

DIFFERENTIAL

DRVDD

Digital Outputs and Timing

TRACE PAIR

0.1µF

DOUT+x

DOUT–x

The AD9644 has differential digital outputs that power up

by default. The driver current is derived on chip and sets the

output current at each output equal to a nominal 4 mA. Each

output presents a 100 Ω dynamic internal termination to

reduce unwanted reflections.

RECEIVER

= Rx V

100Ω

OR

V

OUTPUT SWING = 400mV p-p

CM

A 100 Ω differential termination resistor should be placed at

each receiver input to result in a nominal 400 mV peak-to-peak

swing at the receiver (see Figure 66). Alternatively, single-

ended 50 Ω termina-tion can be used. When single-ended

termination is used, the termination voltage should be

DRVDD/2; otherwise, ac coupling capacitors can be used to

terminate to any single-ended voltage.

Figure 66. AC-Coupled Digital Output Termination Example

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

DOUT+x

RECEIVER

100Ω

DOUT–x

V

= DRVDD/2

OUTPUT SWING = 400mV p-p

The AD9644 digital outputs can interface with custom ASICs

and FPGA receivers, providing superior switching performance

in noisy environments. Single point-to-point network topologies

are recommended with a single differential 100 Ω termination

resistor placed as close to the receiver logic as possible. The

CM

Figure 67. DC-Coupled Digital Output Termination Example

Rev. D | Page ±7 of 44

AD9644

Data Sheet

WIDTH@BER1: BATHTUB

HEIGHT1: EYE DIAGRAM

PERIOD1: HISTOGRAM

0

10

1

4

3

25,000

20,000

15,000

10,000

5000

–

+

–2

–4

–6

–8

10

400

200

0

–200

–400

–10

–12

–14

10

0.781

EYE: TRANSITION BITS

OFFSET: –0.004

ULS: 8000; 639999, TOTAL: 8000; 639999

0

–600 –400 –200

0

200 400 600

610 615 620 625 630 635

TIME (ps)

–0.5

0

0.5

TIME (ps)

ULS

Figure 68. AD9644-80 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations

WIDTH@BER1: BATHTUB

HEIGHT1: EYE DIAGRAM

PERIOD1: HISTOGRAM

0

10

1

4

3

500

400

300

50,000

45,000

40,000

–

–2

–4

–6

–8

10

200

100

0

35,000

30,000

25,000

20,000

15,000

10,000

–100

–200

–300

–10

–12

–14

10

0.742

–400

–500

EYE: TRANSITION BITS

OFFSET: –0.004

ULS: 8000; 124,0001, TOTAL: 8000; 124,0001

5000

0

–300 –200 –100

0

100 200 300

305 310 315 320 325 330 335

TIME (ps)

–0.5

0

0.5

TIME (ps)

ULS

Figure 69. AD9644-155 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations

Figure 68 and Figure 69 shows an example of the digital output

(default) data eye and a time interval error (TIE) jitter histogram.

Table 12. Digital Output Coding

Digital Output

Twos Complement

([D13:D0])

(VIN+ ) − (VIN− ),

Input Span = 1.75 V p-p (V)

Additional SPI options allow the user to further increase the

output driver voltage swing of all four outputs to drive longer

trace lengths (see Address 0x15 in Table 17). Even though this

produces sharper rise and fall times on the data edges and is

less prone to bit errors, the power dissipation of the DRVDD

supply increases when this option is used. See the Memory Map

section for more details.

Code

8191

ꢀ

+ꢀ.875

ꢀ.ꢀꢀ

ꢀ1 1111 1111 1111

ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

11 1111 1111 1111

1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

−1

−ꢀ.ꢀꢀꢀ1ꢀ7

−819± −ꢀ.875

The lowest typical clock rate is 40 MSPS. For clock rates slower

than 60 MSPS, the user should set Bit 3 to 0 in the serial control

register (Address 0x21 in Table 17). This option sets the PLL

loop bandwidth to use clock rates between 40 MSPS and

60 MSPS.

The format of the output data is twos complement by default.

Table 12 provides an example of this output coding format.

To change the output data format to offset binary or gray code,

see the Memory Map section (Address 0x14 in Table 17).

Setting Bit 2 in the output mode register (Address 0x14) allows

the user to invert the digital samples from their nominal state.

As shown in Figure 64, the MSB is transmitted first in the data

output serial stream.

Rev. D | Page ±8 of 44

Data Sheet

AD9644

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9644 includes built-in test features designed to enable

verification of the integrity of each channel as well as facilitate

board level debugging. A BIST (built-in self-test) feature is

included that verifies the integrity of the digital datapath of the

AD9644. Various output test options are also provided to place

predictable values on the outputs of the AD9644.

For more information, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

There are nine digital output test pattern options available that

can be initiated through the SPI (see Table 14 for the output bit

sequencing options). This feature is useful when validating

receiver capture and timing. Some test patterns have two serial

sequential words and can be alternated in various ways,

BUILT-IN SELF-TEST (BIST)

depending on the test pattern selected. Note that some patterns

do not adhere to the data format select option. In addition,

custom user-defined test patterns can be assigned in the user

pattern registers (Address 0x19 through Address 0x20).

The BIST is a thorough test of the digital portion of the selected

AD9644 signal path. When enabled, the test runs from an internal

pseudorandom noise (PN) source through the digital datapath

starting at the ADC block output. The BIST sequence runs for

512 cycles and stops. The BIST signature value for Channel A

and/or Channel B is placed in Register 0x24 and Register 0x25.

The outputs are not disconnected during this test, so the PN

sequence can be observed as it runs. The PN sequence can be

continued from its last value or reset from the beginning, based

on the value programmed in Register 0x0E, Bit 2. The BIST

signature result varies based on the channel configuration.

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 2⁹− 1 (511) bits. A description

of the PN sequence short and how it is generated can be found

in Section 5.1 of the ITU-T O.150 (05/96) recommendation.

The only difference is that the starting value must be a specific

value instead of all 1s (see Table 13 for the initial values).

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 2²³− 1 (8,388,607) bits. A

description of the PN sequence long and how it is generated

can be found in Section 5.6 of the ITU-T O.150 (05/96)

standard. The only differences are that the starting value must be

a specific value instead of all 1s (see Table 13 for the initial

values) and that the AD9644 inverts the bit stream with relation

to the ITU-T standard.

OUTPUT TEST MODES

Digital Test patterns can be inserted at various points along the

signal path within the AD9644 as shown in Figure 70. The

ability to inject these signals at several locations facilitates

debugging of the JESD204A serial communication link.

The Register 0x0D allows test signals generated at the output of

the ADC core to be fed directly into the input of the serial Link.

The output test options available from Register 0x0D are shown

in Table 17. When an output test mode is enabled, the analog

section of the ADC is disconnected from the digital back end

blocks and the test pattern is run through the output formatting

block. Some of the test patterns are subject to output formatting,

and some are not. The seed value for the PN sequence tests can

be forced if the PN reset bits are used to hold the generator in reset

mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can

be performed with or without an analog signal (if present, the

analog signal is ignored), but they do require an encode clock.

Table 13. PN Sequence

Initial

Value

First Three Output Samples

(MSB First)

Sequence

PN Sequence Short

PN Sequence Long

ꢀxꢀꢀ9±

ꢀx3AFF

ꢀx1±5B, ꢀx3C9A, ꢀx±66ꢀ

ꢀx3FD7, ꢀxꢀꢀꢀ±, ꢀx36Eꢀ

The Register 0x62 allows patterns similar to those described in

Table 14 to be input at different points along the data path.

This allows the user to provide predictable output data on the

serial link without it having been manipulated by the internal

formatting logic. Refer to Table 17 for additional information

on the test modes available in Register 0x62.

Rev. D | Page ±9 of 44

AD9644

Data Sheet

Table 14. Flexible Output Test Modes from SPI Register 0x0D

Digital Output Word 1

(Default Twos Complement

Format)

Digital Output Word 2

(Default Twos Complement

Format)

Output Test Mode

Bit Sequence

Subject to Data

Format Select

Pattern Name

ꢀꢀꢀꢀ

ꢀꢀꢀ1

ꢀꢀ1ꢀ

ꢀꢀ11

ꢀ1ꢀꢀ

ꢀ1ꢀ1

ꢀ11ꢀ

ꢀ111

1ꢀꢀꢀ

Off (default)

Midscale short

Not applicable

Same

Yes

No

Yes

No

ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ1 1111 1111 1111

1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ

Not applicable

1111 1111 1111

User data from Register ꢀx19 to

Register ꢀx±ꢀ

+Full-scale short

−Full-scale short

Checkerboard

PN sequence long

PN sequence short

One-/zero-word toggle

User test mode

Same

ꢀ1 ꢀ1ꢀ1 ꢀ1ꢀ1 ꢀ1ꢀ1

Not applicable

ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

User data from Register ꢀx19 to

Register ꢀx±ꢀ

Yes

1ꢀꢀ1 to 111ꢀ

1111

Not used

Ramp output

Not applicable

N

Not applicable

N + 1

No

JESD204A TEST PATTERNS

10-BIT

SPI REGISTER 0x62 BITS 5:4 =

01 AND BITS 2:0 ≠ 000

ADC TEST PATTERNS

14-BIT

SPI REGISTER 0x0D

BITS 3:0 ≠ 0000

JESD204A TEST PATTERNS

16-BIT

SPI REGISTER 0x62 BITS 5:4 =

00 AND BITS 2:0 ≠ 000

SERALIZER

OUTPUT

FRAME

CONSTRUCTION

SCRAMBLER

(OPTIONAL)

8-BIT/10-BIT

ENCODER

JESD204A

SAMPLE

CONSTRUCTION

ADC CORE

FRAMER

TAIL BITS

Figure 70. Block Diagram Showing Digital Test Modes

Rev. D | Page 3ꢀ of 44

Data Sheet

AD9644

SERIAL PORT INTERFACE (SPI)

The AD9644 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

gives the user added flexibility and customization, depending on

the application. Addresses are accessed via the serial port and can

be written to or read from via the port. Memory is organized into

bytes that can be further divided into fields, which are documented

in the Memory Map section. For detailed operational

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

The falling edge of the CSB, in conjunction with the rising edge

of the SCLK, determines the start of the framing. An example

of the serial timing and its definitions can be found in Figure 71

and Table 5.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high,

SPI functions are placed in high impedance mode.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK pin, the SDIO

pin, and the CSB pin (see Table 15). The SCLK (a serial clock)

is used to synchronize the read and write data presented from

and to the ADC. The SDIO (serial data input/output) is a dual-

purpose pin that allows data to be sent to and read from the

internal ADC memory map registers. The CSB (chip select bar)

is an active-low control that enables or disables the read and

write cycles.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. The first bit of the first byte in

a multibyte serial data transfer frame indicates whether a read

command or a write command is issued. If the instruction is a

readback operation, performing a readback causes the serial

data input/output (SDIO) pin to change direction from an input

to an output at the appropriate point in the serial frame.

Table 15. Serial Port Interface Pins

Function

SCLK Serial Clock. The serial shift clock input is used to

synchronize serial interface reads and writes.

SDIO Serial Data Input/Output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

All data is composed of 8-bit words. Data can be sent in MSB-

first mode or in LSB-first mode. MSB first is the default on

power-up and can be changed via the SPI port configuration

register. For more information about this and other features,

see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI.

CSB

Chip Select Bar. An active-low control that gates the read

and write cycles.

t_HIGH

t_DS

t_CLK

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 71. Serial Port Interface Timing Diagram

Rev. D | Page 31 of 44

AD9644

Data Sheet

HARDWARE INTERFACE

SPI ACCESSIBLE FEATURES

The pins described in Table 15 comprise the physical interface

between the user programming device and the serial port of the

AD9644. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

Table 16 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9644 part-specific features are described in detail

in the Memory Map Register Descriptions section.

Table 16. Features Accessible Using the SPI

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note, Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit.

Feature Name

Description

Mode

Allows the user to set either power-down mode

or standby mode

Clock

Allows the user to access the DCS, set the

clock divider, set the clock divider phase, and

enable the sync

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used for

other devices, it may be necessary to provide buffers between

this bus and the AD9644 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

Offset

Allows the user to digitally adjust the

converter offset

Test I/O

Full Scale

JESD±ꢀ4A

Allows the user to set test modes to have

known data on output bits

Allows the user to set the input full scale

voltage

Allows user to configure the JESD±ꢀ4A output

Rev. D | Page 3± of 44

Data Sheet

AD9644

MEMORY MAP

Logic Levels

READING THE MEMORY MAP REGISTER TABLE

An explanation of logic level terminology follows:

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into four sections: the chip

configuration registers (Address 0x00 to Address 0x02); the

channel index and transfer registers (Address 0x05 and

Address 0xFF); the ADC functions registers, including setup,

control, and test (Address 0x08 to Address 0x3A); and the

JESD204A configuration registers (Address 0x5E to Address 0x79).



“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”



“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 through Address 0x79 are shadowed. Writes to

these addresses do not affect part operation until a transfer

command is issued by writing 0x01 to Address 0xFF, setting the

transfer bit. This allows these registers to be updated internally

and simultaneously when the transfer bit is set. The internal

update takes place when the transfer bit is set, and the bit

autoclears.

The memory map register table (see Table 17) lists the default

hexadecimal value for each hexadecimal address shown. The

column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x18, the input

span select register, has a hexadecimal default value of 0x00. This

means that Bit 0 through Bit 4 = 0, and the remaining bits are 0s.

This setting is the default reference selection setting. The default

value uses a 1.75 V p-p reference. For more information on this

function and others, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI. This application note details the

functions con-trolled by Register 0x00 to Register 0xFF.

Channel-Specific Registers

Some channel setup functions, such as the channel output

mode, can be programmed differently for each ADC or link

channel. In these cases, channel address locations are internally

duplicated for each channel. These registers and bits are

designated in Table 17 as local. These local registers and bits

can be accessed by setting the appropriate Channel A/Link A or

Channel B/Link B bits in Register 0x05.

Open Locations

All address and bit locations that are not included in Table 17

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is open

(for example, Address 0x18). If the entire address location is

open (for example, Address 0x13), this address location should not

be written.

If both bits are set in register 0x05, the subsequent write affects

the registers of both channels/links. In a SPI read cycle, only

Channel A/Link A or Channel B/Link B should be set to read

one of the two registers. If both bits are set during an SPI read

cycle, the part returns the value for Channel A/Link A. Registers

and bits designated as global in Table 17 affect the entire part or

the channel features for which independent settings are not

allowed between channels. The settings in Register 0x05 do not

affect the global registers and bits.

Default Values

After the AD9644 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 17.

Rev. D | Page 33 of 44

AD9644

Data Sheet

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 17 are not currently supported for this device.

Table 17. Memory Map Registers

Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Default/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

ꢀxꢀꢀ

SPI port

configuration

(global)¹

ꢀ

LSB first

Soft reset

1

Soft reset

LSB first

ꢀ

ꢀx18

Nibbles are

mirrored so

that LSB-first

or MSB-first

mode is set

correctly,

regardless of

shift mode.

To control

this register,

all channel

index bits in

Register

ꢀxꢀ5 must

be set.

ꢀxꢀ1

ꢀxꢀ±

Chip ID

(global)

8-bit chip ID[7:ꢀ]

(AD9644 = ꢀx7E)

(default)

ꢀx7E

Read only

Chip grade

(global)

Open

Speed grade ID

Open

Speed grade

ID

differentiates

devices;

ꢀꢀ = 8ꢀ MSPS

1ꢀ = 155 MSPS

read only

Channel Index and Transfer Registers

ꢀxꢀ5

Channel index Open

(global)

Open

ADC B and ADC A and

Link B

(default)

ꢀxꢀ3

Bits set to

determine

which

Link A

(default)

device on

the chip

receives

next write

command;

local

registers

only

ꢀxFF

Transfer

(global)

Open

Transfer

ꢀxꢀꢀ

Synchro-

nously

transfers

data from

master shift

register to

slave

ADC Functions

ꢀxꢀ8

Power modes

(local)

Open

External power-

down pin

function (local)

ꢀ = power-

down

Open

Internal power-down mode

(local)

ꢀꢀ = normal operation

ꢀ1 = full power-down

1ꢀ = standby

ꢀxꢀꢀ

ꢀxꢀ1

Determines

various

generic

modes of

chip

operation

1 = standby

11 = reserved

ꢀxꢀ9

Global clock

(global)

Open

Duty cycle

stabilizer

(default)

ꢀxꢀA

ꢀxꢀB

PLL status

(global)

PLL

Locked

Open

ꢀxꢀꢀ

Read Only

Clock divide

(global)

Open

Input clock divider phase adjust

ꢀꢀꢀ = no delay

Clock divide ratio

ꢀꢀꢀ = divide by 1

ꢀꢀ1 = divide by ±

ꢀ1ꢀ = divide by 3

ꢀ11 = divide by 4

1ꢀꢀ = divide by 5

1ꢀ1 = divide by 6

11ꢀ = divide by 7

111 = divide by 8

Clock divide

values other

than ꢀꢀꢀ

automatically

causes duty

cycle

stabilizer to

become

active

ꢀꢀ1 = 1 input clock cycle

ꢀ1ꢀ = ± input clock cycles

ꢀ11 = 3 input clock cycles

1ꢀꢀ = 4 input clock cycles

1ꢀ1 = 5 input clock cycles

11ꢀ = 6 input clock cycles

111 = 7 input clock cycles

Rev. D | Page 34 of 44

Data Sheet

AD9644

Default

Value

(Hex)

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Default/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ꢀxꢀD

Test mode

(local)

User test

mode

control

Open

Reset PN long

generator

Reset

PN

short

generat

or

Output test mode

ꢀꢀꢀꢀ = off (default)

ꢀꢀꢀ1 = midscale short

ꢀꢀ1ꢀ = positive FS

ꢀꢀ11 = negative FS

ꢀxꢀꢀ

When this

register is

set, test data

is used in

place of

normal ADC

data

ꢀ =

continuo

us/repeat

pattern

1 = single

pattern

ꢀ1ꢀꢀ = alternating checkerboard

ꢀ1ꢀ1 = PN long sequence

ꢀ11ꢀ = PN short sequence

ꢀ111 = one/zero word toggle

1ꢀꢀꢀ = user test mode

1ꢀꢀ1 to 111ꢀ = unused

1111 = ramp output

ꢀxꢀE

ꢀx1ꢀ

ꢀx14

BIST enable

(global)

Open

Reset BIST

sequence

Open

BIST enable

ꢀxꢀꢀ

ꢀxꢀ1

Offset adjust

(local)

Offset adjust in LSBs from +31 to −3±

(twos complement format)

Output mode

Output

disable

(local)

Open

Output

invert

(local)

Output format

ꢀꢀ = offset binary

ꢀ1 = twos complement

(default)

Configures

outputs and

the format

of the data

1ꢀ = gray code

11 = offset binary

(local)

ꢀx15

ꢀx18

Output adjust

(global)

Open

Output drive level

adjust

11 = 3±ꢀ mV

ꢀꢀ = 4ꢀꢀ mV

1ꢀ = 44ꢀ mV

ꢀ1 = 5ꢀꢀ mV

ꢀxꢀꢀ

Input span

select

(global)

Full-scale input voltage selection

ꢀ1111 = ±.ꢀ87 V p-p

…

Full-scale

input

adjustment

in ꢀ.ꢀ±± V

steps

ꢀꢀꢀꢀ1 = 1.77± V p-p

ꢀꢀꢀꢀꢀ = 1.75 V p-p (default)

11111 = 1.7±7 V p-p

…

1ꢀꢀꢀꢀ = 1.383 V p-p

ꢀx19

ꢀx1A

ꢀx1B

ꢀx1C

ꢀx1D

ꢀx1E

ꢀx1F

ꢀx±ꢀ

ꢀx±1

User Test

Pattern 1 LSB

(global)

User Test Pattern 1 [7:ꢀ]

User Test Pattern 1 [15:8]

User Test Pattern ± [7:ꢀ]

User Test Pattern ± [15:8]

User Test Pattern 3 [7:ꢀ]

User Test Pattern 3 [15:8]

User Test Pattern 4 [7:ꢀ]

User Test Pattern 4 [15:8]

ꢀxꢀꢀ

User Test

Pattern 1 MSB

(global)

User Test

Pattern ± LSB

(global)

User Test

Pattern ± MSB

(global)

User Test

Pattern 3 LSB

(global)

User Test

Pattern 3 MSB

(global)

User Test

Pattern 4 LSB

(global)

User Test

Pattern 4 MSB

(global)

PLL Control

(global)

Open

PLL Low

encode

rate

Open

Bit 3 must be

enabled if

ADC clock

enable

rate is less

than 6ꢀ MSPS

Rev. D | Page 35 of 44

AD9644

Data Sheet

Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Default/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ꢀx±4

ꢀx±5

ꢀx3A

BIST signature

LSB (local)

BIST signature[7:ꢀ]

ꢀxꢀꢀ

Read only

BIST signature

MSB (local)

BIST signature[15:8]

Read only

Sync control

(global)

Open

Clock

divider

sync

Master sync

buffer

enable

divider

next sync

only

enable

JESD±ꢀ4A Configuration Registers

ꢀx5E

JESD±ꢀ4A

quick

configure

Open

ꢀꢀꢀ = default—configuration

determined by other registers

ꢀꢀ1 = two converters using two links

with one lane per link

ꢀ1ꢀ = two converters using one link with

two lanes per link

ꢀxꢀꢀ

Changes

settings of

Address

ꢀx5F to

Address

ꢀx6ꢀ and

Address

ꢀx6E to

Address

ꢀx7±

(global)

ꢀ11 = two converters using one link and

a single lane

1ꢀꢀ to 111: reserved

(self

clearing)

ꢀx5F

JESD±ꢀ4A

lane

assignment

Open

JESD±ꢀ4A serial lane control

ꢀꢀꢀꢀ = one lane per link. Link A: Lane ꢀ sent on Lane A,

Link B: Lane ꢀ Sent on Lane B

ꢀxꢀꢀ

(global)

ꢀꢀꢀ1 = one lane per link. Link A: Lane ꢀ sent on Lane B,

Link B: Lane ꢀ Sent on Lane A.

ꢀꢀ1ꢀ = two lanes per link. Link A: Lane ꢀ, Lane 1 sent on

Lane A, Lane B. Link B disabled.

ꢀꢀ11 = two lanes per link. Link A: Lane ꢀ, Lane 1 sent on

Lane B, Lane A. Link B disabled.

ꢀ1ꢀꢀ = two lanes per link. Link B: Lane ꢀ, Lane 1 sent on

Lane A, Lane B. Link A disabled.

ꢀ1ꢀ1 = two lanes per link. Link B: Lane ꢀ, 1 sent on

Lane B, Lane A. Link A disabled.

ꢀ11ꢀ to 1111: reserved

ꢀx6ꢀ

ꢀx61

ꢀx6±

JESD±ꢀ4A

Link Control

Register 1

(local)

Open

Serial

tail bit

enable

Serial test

sample enable

Serial

lane

synchro

nization

enable

Serial lane alignment

sequence mode

ꢀꢀ = disabled

ꢀ1 = enabled

1ꢀ = reserved

11 = always on test

mode

Frame

Serial

ꢀxꢀꢀ

alignment

character

insertion

disable

transmit link

powered

down

JESD±ꢀ4A

Link Control

Register ±

(local)

Local DSYNC mode

ꢀꢀ = individual mode

ꢀ1 = global mode

1ꢀ = DSYNC active

mode

DSYNC pin

input inverted

CMOS

DSYNC

input

ꢀ =

LVDS

1 =

Open

Bypass

8b/1ꢀb

encoding

Invert

transmit

bits

Mirror serial

output bits

11 = DSYNC pin

disabled

CMOS

JESD±ꢀ4A

Link Control

Register 3

(local)

Disable

CHKSUM

Open

Link test generation input

selection

Open

Link test generation mode

ꢀꢀꢀ = normal operation

ꢀꢀ = 16-bit data injected at

sample input to the link

ꢀ1 = 1ꢀ-bit data injected at

output of 8b/1ꢀb encoder

1ꢀ = reserved

ꢀꢀ1 = alternating checker board

ꢀ1ꢀ = 1/ꢀ word toggle

ꢀ11 = PN sequence—long

1ꢀꢀ = PN sequence—short

1ꢀ1 = user test pattern data continuous

11ꢀ = user test pattern data single

111 = ramp output

11 = reserved

ꢀx63

ꢀx64

JESD±ꢀ4A

Link Control

Register 4

(local)

Initial lane assignment sequence repeat count

ꢀxꢀꢀ

JESD±ꢀ4A

device

JESD±ꢀ4A serial device identification (DID) number

identification

number (DID)

(local)

Rev. D | Page 36 of 44

Data Sheet

AD9644

Default

Value

(Hex)

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Default/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ꢀx65

JESD±ꢀ4A

bank

Open

JESD±ꢀ4A serial bank identification number (BID)

ꢀxꢀꢀ

identification

number (BID)

(local)

ꢀx66

JESD±ꢀ4A

lane

identification

number (LID)

for Lane ꢀ

(local)

Open

JESD±ꢀ4A serial lane identification (LID) number for Lane ꢀ

JESD±ꢀ4A serial lane identification (LID) number for Lane 1

ꢀxꢀꢀ

ꢀx67

ꢀx6E

JESD±ꢀ4A

lane

identification

number (LID)

for Lane 1

(local)

Open

ꢀxꢀ1

ꢀx8ꢀ

JESD±ꢀ4A

scrambler

Enable

serial

Open

Lane control

(global)

(SCR) and lane scrambler

ꢀ = one lane

per link (L = 1)

1 = two lanes

per link (L = ±)

(L)

mode

(SCR)

(local)

configuration

register

ꢀx6F

ꢀx7ꢀ

ꢀx71

JESD±ꢀ4A

number of

octets per

frame (F)

(global)

JESD±ꢀ4A number of octets per frame (F)—these bits are calculated based on the equation: F = M × (± ÷ L)

ꢀxꢀ1

ꢀxꢀF

ꢀxꢀꢀ

Read only

JESD±ꢀ4A

number of

frames per

multiframe (K)

(local)

Open

JESD±ꢀ4A number of frames per multiframe (K)

JESD±ꢀ4A

number of

converters per

link (M)

Open

Number of

converters

per link (M)

ꢀ = link

(global)

connected

to one ADC

(M = 1)

1 = link

connected

to two ADCs

(M = ±)

ꢀx7±

JESD ±ꢀ4A

ADC

resolution (N)

and control

bits per

Number of control bits Open

per sample (CS)

ꢀꢀ = no control bits

(CS = ꢀ)

ꢀ1 = one control bit

(CS = 1)

Converter resolution (N) (read only)

ꢀx4D

sample (CS)

(local)

1ꢀ = two control bits

(CS = ±)

11 = unused

ꢀx73

ꢀx74

JESD±ꢀ4A

total bits per

sample (N’)

(global)

Open

Total bits per sample (N’) (read only)

ꢀxꢀF

ꢀxꢀꢀ

Read only

JESD±ꢀ4A

samples per

converter (S)

frame cycle

(global)

Open

Samples per converter (S) frame cycle (read only)

Always 1 for the AD9644

ꢀx75

JESD±ꢀ4A HD

and CF

Enable

high

Open

Number of control words per frame clock cycle per Link (CF) –

always ꢀ for the AD9644 (read only)

ꢀxꢀꢀ

Read only

configuration

(global)

density

format

(HD = ꢀ,

read only)

Rev. D | Page 37 of 44

AD9644

Data Sheet

Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Default/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ꢀx76

ꢀx77

ꢀx78

JESD±ꢀ4A

serial reserved

Field 1 (RES1)

Serial Reserved Field 1 (RES1) – these registers are available for customer use

Serial Reserved Field ± (RES±) – these registers are available for customer use

Serial checksum value for Lane ꢀ (FCHK)

ꢀxꢀꢀ

JESD±ꢀ4A

serial reserved

Field ± (RES±)

JESD±ꢀ4A

checksum

value (FCHK)

for Lane ꢀ

(local)

Read only

ꢀx79

JESD±ꢀ4A

checksum

value (FCHK)

for lane 1

(local)

Serial checksum value for Lane 1 (FCHK)

ꢀxꢀꢀ

¹The channel index register at Address ꢀxꢀ5 should be set to ꢀxꢀ3 (default) when writing to Address ꢀxꢀꢀ.

000: default—configuration determined by other registers

MEMORY MAP REGISTER DESCRIPTIONS

001: two converters using two links with one lane per link

(maximum sample rate = 80 MHz or 155 MHz) Each link

configuration:

For additional information about functions controlled in

Register 0x00 to Register 0x25, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

M = 1; N’ = 16; CF = 0; K = 16; S = 1; F = 2; L = 1; HD = 0;

Sync Control (Register 0x3A)

Bits[7:3]—Open

010 = two converters using one link with two lanes per link

(Maximum sample rate = 80 MHz or 155 MHz). Each link

configuration:

Bit 2—Clock Divider Next Sync Only

If the master sync buffer enable bit (Address 0x3A, Bit 0) and

the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit

2 allows the clock divider to sync to the first sync pulse it receives

and to ignore the rest. The clock divider sync enable bit (Address

0x3A, Bit 1) resets after it syncs.

M = 2; N’ = 16; CF = 0; K = 16; S = 1; F = 2; L = 2; HD = 0;

uses DSYNCA pin for synchronization. Setting this mode sets

Address 0x5F = 0x02 and sets Address 0x60 = 0x14 for Link A

and sets Address 0x60 = 0x01 for Link B.

011 = two converters using one link and a single lane (maxi-

mum sample rate = 78.125 MHz). Each link configuration: M = 2;

N’ = 16; CF = 0; K = 8;S = 1; F = 4; L = 1; HD = 0; uses DSYNCA

pin for synchronization and DOUTA for output signals.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal is

enabled when Bit 1 is high and Bit 0 is high. This is continuous

sync mode.

100 to 111: reserved.

Bit 0—Master Sync Buffer Enable

JESD204A Lane Assignment (Register 0x5F)

Bits[7:4]—Reserved

Bit 0 must be high to enable any of the sync functions. If the

sync capability is not used this bit should remain low to

conserve power.

Bits[3:0]—JESD204A Serial Lane Control

These bits set the lane usage. See Figure 62.

JESD204A Quick Configure (Register 0x5E)

Bits[7:3]—Reserved

0000: one lane per link. Link A: Lane 0 sent on Lane A,

Link B: Lane 0 sent on Lane B.

Bits[2:0]—Register Quick Configuration

0001: one lane per link. Link A: Lane 0 sent on Lane B,

Link B: Lane 0 sent on Lane A.

Writes to Bits[2:0] of this register configure the part for the

most popular modes of operation for the JESD204A link. The

intent of this register is to simplify the part setup for typical

serial link operation modes. Writing values other than 0x0 to

this register causes registers throughout the JESD204A memory

map to be updated. Once these registers have been written the

affected JESD204A configuration register reads back with their

new values and can be updated. These bits are self clearing and

always read back as 0b000.

0010: two lanes per link. Link A: Lane 0, one sent on Lane A,

Link B disabled.

0011: two lanes per link. Link A: Lane 0, one sent on Lane B,

Lane A. Link B disabled.

0100: two lanes per link. Link B: Lane 0, one sent on Lane A,

Lane B. Link A disabled.

0101: two lanes per link. Link B: Lane 0, one sent on Lane B,

Lane A. Link A disabled.

0110 to 1111: reserved for future use.

Rev. D | Page 38 of 44

Data Sheet

AD9644

JESD204A Link Control Register 1 (Register 0x60)

Bit 7—Reserved

Bit 3—Open

Bit 2—Bypass 8b/10b Encoding

Bit 6—Serial Tail Bit Enable

If this bit is set the 8b/10b encoding is bypassed and the most

significant bits are set to 0.

If this bit is set, the unused tail bits are padded with a pseudo

random number sequence from a 31-bit LFSR (see JESD204A

5.1.4).

Bit 1—Invert Transmit Bits

Setting this bit inverts the 10 serial output bits. This effectively

inverts the output signals.

Bit 5—Serial Test Sample Enable

If this bit is set, JESD204A test samples are enabled—transport

layer test sample sequence (as specified in JESD204A section

5.1.6.2) is sent on all link lanes.

Bit 0—Mirror Serial Output Bits

Setting this bit reverses the order of the 10b outputs.

JESD204A Link Control Register 3 (Register 0x62)

Bit 4—Serial Lane Synchronization Enable

Bit 7—Disable CHKSUM

If this bit is set, lane synchronization is enabled. Both sides

perform lane sync. Frame alignment character insertion uses

either /K28.3/ or /K28.7/ control characters (see JESD204A

5.3.3.4).

Setting this bit high disables the CHKSUM configuration

parameter (for testing purposes only).

Bit 6—Open

Bits[3:2]—Serial Lane Alignment Sequence Mode

00: initial lane alignment sequence disabled.

01: initial lane alignment sequence enabled.

10: reserved.

Bits[5:4]—Link Test Generation Input Selection

00: 16-bit test generation data injected at sample input to

the link.

01: 10-bit test generation data injected at output of 8b/10b

encoder (at input to PHY).

11: initial lane alignment sequence always on test mode—

JESD204A data link layer test mode where repeated lane alignment

sequence is sent on all lanes.

10: reserved.

11: reserved.

Bit 1—Frame Alignment Character Insertion Disable

Bit 3—Open

Bits[2:0]—Link Test Generation Mode

000: normal operation (test mode disabled).

001: alternating checker board.

010: 1/0 word toggle.

If Bit 1 is set, the frame alignment character insertion is

disabled per JESD204A section 5.3.3.4.

Bit 0—Serial Transmit Link Powered Down

If Bit 0 is set high, the serial transmit link is held in reset with

its clock gated off. The JESD204A transmitter should be

powered down when changing any of the link configuration

bits.

011: PN sequence—long.

100: PN sequence—short.

101: continuous/repeat user test mode—most significant bits

from user pattern (1, 2, 3, 4) placed on the output for 1 clock

cycle and then repeat. (output user pattern 1, 2, 3, 4, 1, 2, 3, 4, 1,

2, 3, 4…).

JESD204A Link Control Register 2 (Register 0x61)

Bits[7:6]—Local DSYNC Mode

00: individual/separate mode. Each link is controlled by a

separate DSYNC pin that independently controls code group

synchronization.

110: single user test mode—most significant bits from user

pattern (1, 2, 3, 4) placed on the output for 1 clock cycle and

then output all zeros. (output user pattern 1, 2, 3, 4, then output

all zeros).

01: global mode. Any DSYNC signal causes the link to begin

code group synchronization.

10: sync active mode. DSYNC signal is active—force code group

synchronization.

111: ramp output.

JESD204A Link Control Register 4 (Register 0x63)

11: DSYNC pin disabled.

Bits[7:0]—Initial Lane Alignment Sequence Repeat Count

Bit 5—DSYNC Pin Input Inverted

If this bit is set, the DSYNC pin of the link is inverted (active high).

Bit 4—CMOS DSYNC Input

Specifies the number of times the initial lane alignment

sequence (ILAS) is repeated. If 0 is programmed the ILAS does

not repeat. If 1 is programmed the ILAS repeat one time and so

on. See Register 0x60, Bits[3:2] to enable the ILAS and for a test

mode to continuously enable the initial lane alignment

sequence.

0: LVDS differential pair DSYNC input (default)

1: CMOS single ended DSYNC input

Rev. D | Page 39 of 44

AD9644

Data Sheet

JESD204A Device Identification Number (DID)

(Register 0x64)

JESD204A Number of Converters Per Link (M)

(Register 0x71)

Bits[7:0]—Serial Device Identification (DID) Number

Bits[7:1]—Reserved

JESD204A Bank Identification Number (BID)

(Register 0x65)

Bit 0—Number of Converters per Link per Device (M).

0: link connected to one ADC. Only primary input used (M = 1).

Bits[7:4]—Open

1: link connected to two ADCs. Primary and secondary inputs

used (M = 2).

Bits[3:0]—Serial Bank Identification (DID) Number

JESD204A Lane Identification Number (LID) for Lane 0

(Register 0x66)

JESD204A ADC Resolution (N) and Control Bits Per

Sample (CS) (Register 0x72)

Bits[7:5]—Open

Bits[7:6]—Number of Control Bits per Sample (CS)

Bits[4:0]—Serial Lane Identification (LID) Number for

Lane 0.

00: no control bits sent per sample (CS = 0).

01: one control bits sent per sample—overrange bit enabled.

(CS = 1).

JESD204A Lane Identification Number (LID) for Lane 1

(Register 0x67)

10: two control bits sent per sample—overflow/underflow bits

enabled (CS = 2).

Bits[7:5]—Open

Bits[4:0]—Serial Lane Identification (LID) Number for

Lane 1.

11: unused.

Bit 5—Open

JESD204A Scrambler (SCR) and Lane Configuration

Registers (Register 0x6E)

Bits[4:0]—Converter Resolution (N)

Bit 7—Enable Serial Scrambler Mode

Setting this bit high enables the scrambler (SCR = 1).

Bits[6:1]—Open

Read only bits showing the converter resolution (reads back 13

(0xD) for 14-bit resolution).

JESD204A Total Bits Per Sample (N’) (Register 0x73)

Bits[7:5]—Open

Bit[0]—Serial Lane Control.

00000: one lane per link (L = 1).

00001: two lanes per link (L = 2).

00010: 11111—reserved.

Bits[4:0]—Total Number of Bits per Sample (N’)

Read only bits showing the total number of bits per sample—1

(reads back 15 (0xF) for 16 bits per sample).

JESD204A Samples Per Converter (S) Frame Cycle

(Register 0x74)

JESD204A Number of Octets Per Frame (F)

(Register 0x6F—Read Only)

Bits[7:5]—Open

Bits[7:0]—Number of Octets per Frame (F)

Bits[4:0]—Samples per Converter Frame Cycle (S)

The readback from this register is calculated from the following

equation: F = (M × 2)/L

Read only bits showing the number of samples per converter

frame cycle −1 (reads back 0 (0x0) for 1 sample per converter

frame).

Valid values for F for the AD9644 are:

F = 2, with M = 1 and L = 1

F = 4, with M = 2 and L = 1

F = 2, with M = 2 and L = 2

JESD204A HD and CF Configuration (Register 0x75)

Bit 7—Enable High Density Format (Read Only)

Read only bit—always 0 in the AD9644.

JESD204A Number of Frames Per Multiframe

(Register 0x70)

Bits[6:5]—Reserved

Bits[4:0]—Number of Control Words per Frame Clock

Cycle per Link (CF)

Bits[7:5]—Reserved

Bits[4:0]—Number of Frames per Multiframe (K).

Read only bits—reads back 0x0 for the AD9644.

Rev. D | Page 4ꢀ of 44

Data Sheet

AD9644

JESD204A Serial Reserved Field 1 (Register 0x76)

JESD204A Serial Checksum Value for Lane 0

(Register 0x78)

Bits[7:0]—Serial Reserved Field 1 (RES1)

Bits[7:0]—Serial Checksum Value for Lane 0

This read/write register is available for customer use.

This read only register is automatically calculated for each lane.

Sum (all link configuration parameters for Lane 0) mode 256.

JESD204A Serial Reserved Field 2 (Register 0x77)

Bits[7:0]—Serial Reserved Field 2 (RES2)

JESD204A Serial Checksum Value for Lane 1

(Register 0x79)

This read/write register is available for customer use.

Bits[7:0]—Serial Checksum Value for Lane 1

This read only register is automatically calculated for each lane.

Sum (all link configuration parameters for Lane 1) mode 256.

Rev. D | Page 41 of 44

AD9644

Data Sheet

APPLICATIONS INFORMATION

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged to

prevent solder wicking through the vias, which can compromise

the connection.

DESIGN GUIDELINES

Before starting design and layout of the AD9644 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements that are needed for certain pins.

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the

Power and Ground Recommendations

When connecting power to the AD9644, it is recommended

that two separate 1.8 V supplies be used. Use one supply for

analog (AVDD); use a separate supply for the digital outputs

(DRVDD). For both AVDD and DRVDD several different

decoupling capa-citors should be used to cover both high and

low frequencies. Place these capacitors close to the point of entry

at the PCB level and close to the pins of the part, with minimal

trace length.

continuous plane on the PCB into several uniform sections.

This provides several tie points between the ADC and the PCB

during the reflow process. Using one continuous plane with no

partitions guarantees only one tie point between the ADC and the

PCB. For detailed information about packaging and PCB layout

of chip scale packages, see the AN-772 Application Note, A

Design and Manufacturing Guide for the Lead Frame Chip Scale

Package (LFCSP), at www.analog.com.

A single PCB ground plane should be sufficient when using the

AD9644. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

VCMA and VCMB

The VCMA and VCMB pins should be decoupled to ground

with a 0.1 ꢀF capacitor, as shown in Figure 50.

SPI Port

Exposed Paddle Thermal Heat Slug Recommendations

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9644 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. A continuous, exposed

(no solder mask) copper plane on the PCB should mate to the

AD9644 exposed paddle, Pin 0.

Rev. D | Page 4± of 44

Data Sheet

AD9644

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

7.10

0.30

0.23

0.18

7.00 SQ

6.90

PIN 1

INDICATOR

AREA

PIN 1

INDICATOR AR EA

(SEE DETAIL A)

O

P TIONS

37

36

48

1

0.50

BSC

5.65

EXPOSED

PAD

5.50 SQ

5.35

24

13

0.45

0.40

0.35

0.20 MIN

BOTTOM VIEW

5.50 REF

TOP VIEW

END VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WKKD

Figure 72. 48-Lead Lead Frame Chip Scale Package [LFCSP]

7 mm × 7 mm Body and 0.75 mm Package Height

(CP-48-9)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

AD9644BCPZ-8ꢀ

AD9644BCPZRL7-8ꢀ

AD9644CCPZ-8ꢀ

AD9644CCPZRL7-8ꢀ

AD9644BCPZ-155

AD9644BCPZRL7-155

AD9644-8ꢀKITZ

AD9644-155KITZ

−4ꢀ°C to +85°C

48-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

CP-48-9

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. D | Page 43 of 44

AD9644

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D09180-9/20(D)

Rev. D | Page 44 of 44


型号：	AD9644CCPZRL7-80
厂家：	ADI
描述：	14-Bit, 80 MSPS/155 MSPS, 1.8V Dual, Serial Output A/D Converter 转换器
文件：	总44页 (文件大小：1886K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9644CCPZRL7-80 [ADI]

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