AD9649BCPZ-40_技术文档

14-Bit, 20/40/65/80 MSPS,

1.8 V Analog-to-Digital Converter

AD9649

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

GND

SDIO SCLK CSB

DRVDD

1.8 V analog supply operation

1.8 V to 3.3 V output supply

SNR

74.3 dBFS at 9.7 MHz input

71.5 dBFS at 200 MHz input

SFDR

93 dBc at 9.7 MHz input

80 dBc at 200 MHz input

Low power

45 mW at 20 MSPS

RBIAS

VCM

SPI

OR

PROGRAMMING DATA

D13 (MSB)

VIN+

VIN–

ADC

CORE

D0 (LSB)

DCO

VREF

SENSE

AD9649

REF

SELECT

87 mW at 80 MSPS

Differential input with 700 MHz bandwidth

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = 0.35 LSB

MODE

DIVIDE BY

1, 2, 4

CONTROLS

CLK+ CLK–

PDWN DFS MODE

Serial port control options

Offset binary, gray code, or twos complement data format

Integer 1, 2, or 4 input clock divider

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out (DCO) with programmable clock and data

alignment

Figure 1.

PRODUCT HIGHLIGHTS

1. The AD9649 operates from a single 1.8 V analog power

supply and features a separate digital output driver supply

to accommodate 1.8 V to 3.3 V logic families.

2. The patented sample-and-hold circuit maintains excellent

performance for input frequencies up to 200 MHz and is

designed for low cost, low power, and ease of use.

3. A standard serial port interface (SPI) supports various

product features and functions, such as data output format-

ting, internal clock divider, power-down, DCO, data output

(D13 to D0) timing and offset adjustments, and voltage

reference modes.

4. The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP

that is pin compatible with the AD9629 12-bit ADC and

the AD9609 10-bit ADC, enabling a simple migration path

between 10-bit and 14-bit converters sampling from 20 MSPS

to 80 MSPS.

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers

GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA

Smart antenna systems

Battery-powered instruments

Handheld scope meters

Portable medical imaging

Ultrasound

Radar/LIDAR

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9649

TABLE OF CONTENTS

Features .............................................................................................. 1

Voltage Reference ....................................................................... 19

Clock Input Considerations...................................................... 20

Power Dissipation and Standby Mode .................................... 21

Digital Outputs ........................................................................... 22

Timing ......................................................................................... 22

Built-In Self-Test (BIST) and Output Test .................................. 23

Built-In Self-Test (BIST)............................................................ 23

Output Test Modes..................................................................... 23

Serial Port Interface (SPI).............................................................. 24

Configuration Using the SPI..................................................... 24

Hardware Interface..................................................................... 25

Configuration Without the SPI ................................................ 25

SPI Accessible Features.............................................................. 25

Memory Map .................................................................................. 26

Reading the Memory Map Register Table............................... 26

Open Locations .......................................................................... 26

Default Values............................................................................. 26

Memory Map Register Table..................................................... 27

Memory Map Register Descriptions........................................ 29

Applications Information.............................................................. 30

Design Guidelines ...................................................................... 30

Outline Dimensions....................................................................... 31

Ordering Guide .......................................................................... 31

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

DC Specifications ......................................................................... 4

AC Specifications.......................................................................... 5

Digital Specifications ................................................................... 6

Switching Specifications .............................................................. 7

Timing Specifications .................................................................. 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

AD9649-80 .................................................................................. 11

AD9649-65 .................................................................................. 13

AD9649-40 .................................................................................. 14

AD9649-20 .................................................................................. 15

Equivalent Circuits......................................................................... 16

Theory of Operation ...................................................................... 17

Analog Input Considerations.................................................... 17

REVISION HISTORY

10/09—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD9649

GENERAL DESCRIPTION

deterministic and pseudorandom patterns, along with custom

user-defined test patterns entered via the serial port interface (SPI).

The AD9649 is a monolithic, single channel 1.8 V supply, 14-bit,

20/40/65/80 MSPS analog-to-digital converter (ADC). It features

a high performance sample-and-hold circuit and an on-chip volt-

age reference.

A differential clock input with optional 1, 2, or 4 divide ratios

controls all internal conversion cycles.

The product uses multistage differential pipeline architecture

with output error correction logic to provide 14-bit accuracy at

80 MSPS data rates and to guarantee no missing codes over the

full operating temperature range.

The digital output data is presented in offset binary, gray code, or

twos complement format. A data output clock (DCO) is provided

to ensure proper latch timing with receiving logic. Both 1.8 V and

3.3 V CMOS levels are supported.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

The AD9649 is available in a 32-lead RoHS-compliant LFCSP and

is specified over the industrial temperature range (−40°C to

+85°C).

Rev. 0 | Page 3 of 32

AD9649

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 1.

AD9649-20/AD9649-40

Temp Min Typ Max

AD9649-65

AD9649-80

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

Full

14

Bits

ACCURACY

No Missing Codes

Offset Error

Full

25°C

Full

25°C

Guaranteed

−0.40 +0.05

−1.5

+0.50

−0.40 +0.05 +0.50 −0.40 +0.05 +0.50 % FSR

Gain Error¹

−1.5

0.3

−1.5

0.35

% FSR

0.ꢀ5 LSB

LSB

1.ꢁ5 LSB

LSB

Differential Nonlinearity (DNL)²

0.50

+0.55

1.30

0.25

0.50

2

Integral Nonlinearity (INL)²

1.30

0.50

0.ꢀ0

2

TEMPERATURE DRIFT

Offset Error

Full

2

ppm/°C

INTERNAL VOLTAGE REFERENCE

Output Voltage (1 V Mode)

Load Regulation Error at 1.0 mA

INPUT-REFERRED NOISE

VREF = 1.0 V

Full

0.984 0.99ꢀ

2

1.008

0.984 0.99ꢀ 1.008 0.984 0.99ꢀ 1.008

V

mV

2

25°C

0.98

LSB rms

ANALOG INPUT

Input Span, VREF = 1.0 V

Input Capacitance³

Input Common-Mode Voltage

Input Common-Mode Range

REFERENCE INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

AVDD

DRVDD

Full

2

ꢀ

0.9

2

ꢀ

0.9

2

ꢀ

0.9

V p-p

pF

V

0.5

1.3

0.5

1.3

0.5

1.3

V

ꢁ.5

1.8

ꢁ.5

1.8

kΩ

Full

1.ꢁ

1.8

1.9

3.ꢀ

1.ꢁ

1.9

3.ꢀ

1.ꢁ

1.9

3.ꢀ

V

Supply Current

IAVDD²

Full

25.0/31.3 2ꢁ.3/33.ꢁ

1.ꢀ/2.9

3.0/5.3

41.0

4.ꢁ

8.4

44.0

4ꢁ.0

5.ꢀ

10.2

50.0

mA

IDRVDD²(1.8 V)

IDRVDD²(3.3 V)

POWER CONSUMPTION

DC Input

Sine Wave Input²(DRVDD = 1.8 V)

Sine Wave Input²(DRVDD = 3.3 V)

Standby Power⁴

Full

45.2/5ꢁ.2

4ꢁ.9/ꢀ1.ꢀ 51.8/ꢀ5.8

54.9/ꢁ3.8

34/34

ꢁ5.2

82.3

101.5

34

8ꢀ.8

94.ꢁ

118.3

34

mW

8ꢁ.5

100

Power-Down Power

0.5

¹Measured with 1.0 V external reference.

²Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.

³Input capacitance refers to the effective capacitance between one differential input pin and ground.

⁴Standby power is measured with a dc input and the CLK+, CLK− active.

Rev. 0 | Page 4 of 32

AD9649

AC SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 2.

AD9649-20/AD9649-40

AD9649-65

Min Typ Max Min Typ

AD9649-80

Parameter¹

Temp Min

Typ

Max

Max Unit

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 9.ꢁ MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

25°C

ꢁ4.ꢁ

ꢁ4.4

ꢁ4.5

ꢁ4.3

ꢁ4.1

dBFS

ꢁ3.1

ꢁ3.0

ꢁ3.ꢀ

ꢁ3.5

f_IN= ꢁ0 MHz

ꢁ3.ꢁ

ꢁ1.5

ꢁ3.ꢁ

ꢁ1.5

ꢁ3.ꢀ

ꢁ1.5

ꢁ2.ꢁ

ꢁ2.ꢀ

f_IN= 200 MHz

SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)

f_IN= 9.ꢁ MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

ꢁ4.ꢀ

ꢁ4.3

ꢁ4.4

ꢁ4.2

ꢁ4.1

ꢁ4.0

dBFS

f_IN= ꢁ0 MHz

ꢁ3.ꢀ

ꢁ0.0

ꢁ3.ꢀ

ꢁ0.0

ꢁ3.5

ꢁ0.0

f_IN= 200 MHz

25°C

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 9.ꢁ MHz

f_IN= 30.5 MHz

f_IN= ꢁ0 MHz

f_IN= 200 MHz

25°C

12.0

11.9

11.3

12.0

11.9

11.3

12.0

11.9

11.3

Bits

WORST SECOND OR THIRD HARMONIC

f_IN= 9.ꢁ MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

−95

−93

dBc

−82

−83

f_IN= ꢁ0 MHz

−94

−80

−94

−80

−92

−80

−82

f_IN= 200 MHz

25°C

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 9.ꢁ MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

95

94

95

94

93

dBc

82

83

f_IN= ꢁ0 MHz

93

80

93

80

92

80

82

f_IN= 200 MHz

25°C

WORST OTHER (HARMONIC OR SPUR)

f_IN= 9.ꢁ MHz

f_IN= 30.5 MHz

25°C

Full

25°C

Full

−100

dBc

−90

f_IN= ꢁ0 MHz

−100

−95

−100

−95

−100

−95

−90

f_IN= 200 MHz

25°C

TWO-TONE SFDR

f_IN= 30.5 MHz (−ꢁ dBFS), 32.5 MHz (−ꢁ dBFS)

ANALOG INPUT BANDWIDTH

25°C

90

dBc

ꢁ00

MHz

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

Rev. 0 | Page 5 of 32

AD9649

DIGITAL SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 3.

AD9649-20/AD9649-40/AD9649-65/AD9649-80

Parameter

Temp

Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

0.9

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

High Level Input Current

Low Level Input Current

Input Resistance

Full

V

0.2

GND − 0.3

−10

8

3.6

AVDD + 0.2

+10

12

V p-p

V

μA

kΩ

pF

10

4

Input Capacitance

LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN)¹

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−50

−10

DRVDD + 0.3

0.8

−75

+10

V

μA

kΩ

pF

30

2

Input Capacitance

LOGIC INPUTS (CSB)²

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

0

−10

40

DRVDD + 0.3

0.8

+10

135

V

μA

kΩ

pF

26

2

Input Capacitance

DIGITAL OUTPUTS

DRVDD = 3.3 V

High Level Output Voltage (I_OH)

I_OH= 50 μA

I_OH= 0.5 mA

Full

3.29

3.25

V

Low Level Output Voltage (I_OL)

I_OL= 1.6 mA

I_OL= 50 μA

Full

0.2

0.05

V

DRVDD = 1.8 V

High Level Output Voltage (I_OH)

I_OH= 50 μA

I_OH= 0.5 mA

Full

1.79

1.75

V

Low Level Output Voltage (I_OL)

I_OL= 1.6 mA

I_OL= 50 μA

Full

0.2

0.05

V

¹Internal 30 kΩ pull-down.

²Internal 30 kΩ pull-up.

Rev. 0 | Page 6 of 32

AD9649

SWITCHING SPECIFICATIONS

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty

cycle clock, unless otherwise noted.

Table 4.

AD9649-20/AD9649-40

AD9649-65

AD9649-80

Max Min Typ Max Unit

Parameter

Temp Min

Typ

Max

Min

Typ

CLOCK INPUT PARAMETERS

Input Clock Rate

Conversion Rate¹

Full

80/1ꢀ0

20/40

2ꢀ0

ꢀ5

320

80

MHz

MSPS

ns

3

12.5

50/25

CLK Period, Divide-by-1 Mode (t_CLK

)

15.38

CLK Pulse Width High (t_CH

Aperture Delay (t_A)

Aperture Uncertainty (Jitter, t_J)

DATA OUTPUT PARAMETERS

)

25.0/12.5

1.0

0.1

ꢁ.ꢀ9

1.0

0.1

ꢀ.25

1.0

0.1

ns

ps rms

Full

Data Propagation Delay (t_PD

DCO Propagation Delay (t_DCO

DCO to Data Skew (t_SKEW

Pipeline Delay (Latency)

Wake-Up Time²

Standby

)

Full

3

0.1

8

350

ꢀ00/400

2

3

ns

Cycles

μs

)

0.1

8

350

300

2

0.1

8

350

2ꢀ0

2

ns

OUT-OF-RANGE RECOVERY TIME

Cycles

¹Conversion rate is the clock rate after the CLK divider.

²Wake-up time is dependent on the value of the decoupling capacitors.

N – 1

N + 4

t_A

N + 5

N

N + 3

VIN

N + 1

N + 2

t_CH

t_CLK

CLK+

CLK–

t_DCO

DCO

t_SKEW

N – 8

DATA

N – 7

N – 6

N – 5

N – 4

t_PD

Figure 2. CMOS Output Data Timing

Rev. 0 | Page ꢁ of 32

AD9649

TIMING SPECIFICATIONS

Table 5.

Parameter

Conditions

Min

Typ

Max

Unit

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an

output relative to the SCLK falling edge

2

40

2

10

ns

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge

10

ns

Rev. 0 | Page 8 of 32

AD9649

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

Parameter

Rating

The exposed paddle is the only ground connection for the chip

and must be soldered to the analog ground plane of the user’s

PCB. Soldering the exposed paddle to the user’s board also

increases the reliability of the solder joints and maximizes the

thermal capability of the package.

AVDD to AGND¹

−0.3 V to +2.0 V

−0.3 V to +3.9 V

DRVDD to AGND¹

VIN+, VIN− to AGND¹

CLK+, CLK− to AGND¹

VREF to AGND¹

−0.3 V to AVDD + 0.2 V

−0.3 V to DRVDD + 0.3 V

−40°C to +85°C

Table 7. Thermal Resistance

SENSE to AGND¹

VCM to AGND¹

Airflow

Package

Type

Velocity

(m/sec)

RBIAS to AGND¹

1, 2

1, 3

1, 4

1,2

θ_JA

θ_JC

3.1

θ_JB

20.ꢁ

Ψ_JT

0.3

0.5

0.8

Unit

°C/W

CSB to AGND¹

32-Lead LFCSP

5 mm × 5 mm

0

1.0

2.5

3ꢁ.1

32.4

29.1

SCLK/DFS to AGND¹

SDIO/PDWN to AGND¹

MODE/OR to AGND¹

D0 through D13 to AGND¹

DCO to AGND¹

¹Per JEDEC 51-ꢁ, plus JEDEC 51-5 2S2P test board.

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-ꢀ (moving air).

³Per MIL-Std 883, Method 1012.1.

⁴Per JEDEC JESD51-8 (still air).

Operating Temperature Range (Ambient)

Maximum Junction Temperature Under Bias

Storage Temperature Range (Ambient)

150°C

−ꢀ5°C to +150°C

Typical θ_JAis specified for a 4-layer PCB with a solid ground

plane. As shown in Table 7, airflow improves heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes, reduces the θ_JA.

¹AGND refers to the analog ground of the customer’s PCB.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. 0 | Page 9 of 32

AD9649

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK+

CLK–

AVDD

1

2

3

4

5

6

7

8

24 AVDD

23 MODE/OR

22 DCO

21 D13 (MSB)

20 D12

19 D11

18 D10

17 D9

PIN 1

INDICATOR

CSB

AD9649

TOP VIEW

SCLK/DFS

SDIO/PDWN

D0 (LSB)

D1

(Not to Scale)

NOTES

1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE ANALOG GROUND

PLANE OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND MAXIMIZE

THE HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.

Figure 3. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

0 (EP)

GND

Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog

ground of the customer’s PCB to ensure proper functionality and maximize the heat dissipation, noise,

and mechanical strength benefits.

1, 2

3, 24, 29, 32

CLK+, CLK−

AVDD

Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.

1.8 V Supply Pin for the ADC CORE Domain.

4

5

CSB

SCLK/DFS

SPI Chip Select. Active low enable, 30 kΩ internal pull-up.

SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.

Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.

DFS high = twos complement output; DFS low = offset binary output.

ꢀ

SDIO/PDWN

SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.

Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down.

See Table 14 for details.

ꢁ to 12, 14 to 21 D0 (LSB) to

D13 (MSB)

ADC Digital Outputs.

13

22

23

DRVDD

DCO

MODE/OR

1.8 V to 3.3 V Supply Pin for Output Driver Domain.

Data Clock Digital Output.

Chip Mode Select Input in SPI Mode (MODE).

Out-of-Range Digital Output in SPI Mode or in Non-SPI Mode (OR).

Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).

Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).

Chip power-down (SPI Register 0x08, Bits[ꢁ:5] = 100).

Chip stand-by (SPI Register 0x08, Bits[ꢁ:5] = 101).

Normal operation, output disabled (SPI Register 0x08, Bits[ꢁ:5] = 110).

Normal operation, output enabled (SPI Register 0x08, Bits[ꢁ:5] = 111).

In non-SPI mode, the pin operates only as an out-of-range (OR) digital output.

1.0 V Voltage Reference Input/Output. See Table 10.

25

VREF

2ꢀ

2ꢁ

28

30, 31

SENSE

VCM

RBIAS

Reference Mode Selection. See Table 10.

Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.

Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.

ADC Analog Inputs.

VIN−, VIN+

Rev. 0 | Page 10 of 32

AD9649

TYPICAL PERFORMANCE CHARACTERISTICS

AD9649-80

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle

clock, unless otherwise noted.

0

80MSPS

30.5MHz @ –1dBFS

SNR = 73.2dB (74.2dBFS)

SFDR = 93.6dBc

9.7MHz @ –1dBFS

SNR = 73.4dB (74.4dBFS)

SFDR = 94.4dBc

–15

–30

–15

–30

–45

–60

–75

–90

3

2

5

2

4

6

5

6

4

–105

–120

–105

–120

4

8

12

16

20

24

28

32

36

4

8

12

16

20

24

28

32

36

FREQUENCY (MHz)

Figure 4. AD9649-80 Single-Tone FFT with f_IN= 9.7 MHz

Figure 7. AD9649-80 Single-Tone FFT with f_IN= 30.5 MHz

0

80MSPS

200MHz @ –1dBFS

SNR = 70.5dB (71.5dBFS)

SFDR = 80.2dBc

80MSPS

70.3MHz @ –1dBFS

SNR = 72.1dB (73.1dBFS)

SFDR = 93.5dBc

–15

–30

–15

–30

–45

–60

–45

–60

–75

–90

–75

–90

2

3

2

3

4

6

5

–105

–120

6

4

5

–105

–120

4

8

12

16

20

24

28

32

36

4

8

12

16

20

24

28

32

36

FREQUENCY (MHz)

Figure 5. AD9649-80 Single-Tone FFT with f_IN= 70.3 MHz

Figure 8. AD9649-80 Single-Tone FFT with f_IN= 200 MHz

0

80MSPS

30.5MHz @ –7dBFS

32.5MHz @ –7dBFS

–15

–20

SFDR = 89.5dBc (96.5dBFS)

–30

–45

–60

SFDR (dBc)

–40

–60

IMD3 (dBc)

–75

–90

–80

–100

–120

2F1 + F2

2F2 + F1

SFDR (dBFS)

IMD3 (dBFS)

F2 – F1

2F1 – F2

2F2 – F1

F1 + F2

–105

–120

–90

–78

–66

–54

–42

–30

–18

–6

4

8

12

16

20

24

28

32

36

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 6. AD9649-80 Two-Tone FFT with f_IN1= 30.5 MHz and f_IN2= 32.5 MHz

Figure 9. AD9649-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)

with f_IN1= 30.5 MHz and f_IN2= 32.5 MHz

Rev. 0 | Page 11 of 32

AD9649

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle

clock, unless otherwise noted.

120

100

80

100

90

80

70

60

50

40

30

20

10

0

SFDR (dBc)

SFDRFS

SNR (dBFS)

SNRFS

60

SFDR

40

20

0

SNR

–90

–80

–60

–40

–20

0

50

100

150

200

INPUT AMPLITUDE (dBFS)

INPUT FREQUENCY (MHz)

Figure 13. AD9649-80 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

Figure 10. AD9649-80 SNR/SFDR vs. Input Frequency (AIN)

with 2 V p-p Full Scale

450,000

400,000

350,000

120

SFDR (dBc)

SNR (dBFS)

100

300,000

250,000

200,000

150,000

100,000

50,000

0

80

60

40

20

0

N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4

10

20

30

40

50

60

70

80

OUTPUT CODE

SAMPLE RATE (MSPS)

Figure 14. AD9649-80 Grounded Input Histogram

Figure 11. AD9649-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz

2.0

1.5

0.5

0.4

0.3

0.2

1.0

0.5

0.1

0

–0.1

–0.5

–1.0

–1.5

–2.0

–0.2

–0.3

–0.4

–0.5

0

2048

4096

6144

8192 10,240 12,288 14,336 16,384

0

2048

4096

6144

8192 10,240 12,288 14,336 16,384

OUTPUT CODE

Figure 12. AD9649-80 DNL Error with f_IN= 9.7 MHz

Figure 15. AD9649-80 INL with f_IN= 9.7 MHz

Rev. 0 | Page 12 of 32

AD9649

AD9649-65

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle

clock, unless otherwise noted.

0

–15

–30

–45

–60

–75

–90

–105

120

100

80

65MSPS

9.7MHz @ –1dBFS

SNR = 73.5dB (74.5dBFS)

SFDR = 97.7dBc

SFDRFS

SNRFS

60

SFDR

40

20

0

SNR

3

2

5

6

4

–120

3

6

9

12

15

18

21

24

27

30

–90 –80

–60

–40

–20

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 16. AD9649-65 Single-Tone FFT with f_IN= 9.7 MHz

Figure 19.AD9649-65 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

100

0

65MSPS

70.3MHz @ –1dBFS

SNR = 72.6dB (73.6dBFS)

SFDR = 94.1dBc

90

SFDR (dBc)

–15

80

–30

70

SNR (dBFS)

–45

–60

60

50

40

30

20

10

0

–75

–90

2

4

3

5

6

–105

–120

0

50

100

150

200

3

6

9

12

15

18

21

24

27

30

INPUT FREQUENCY (MHz)

FREQUENCY (MHz)

Figure 20. AD9649-65 SNR/SFDR vs. Input Frequency (AIN)

with 2 V p-p Full Scale

Figure 17. AD9649-65 Single-Tone FFT with f_IN= 70.3 MHz

0

65MSPS

30.5MHz @ –1dBFS

SNR = 73.3dB (74.3dBFS)

SFDR = 99.3dBc

–15

–30

–45

–60

–75

–90

3

2

5

–105

–120

6

4

3

6

9

12

15

18

21

24

27

30

FREQUENCY (MHz)

Figure 18. AD9649-65 Single-Tone FFT with f_IN= 30.5 MHz

Rev. 0 | Page 13 of 32

AD9649

AD9649-40

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle

clock, unless otherwise noted.

120

100

80

0

–15

–30

–45

40MSPS

9.7MHz @ –1dBFS

SNR = 73.5dB (74.5dBFS)

SFDR = 95.4dBc

SFDRFS

SNRFS

–60

–75

–90

60

SFDR

40

20

0

SNR

2

4

5

3

6

–105

–120

2

4

6

8

10

12

14

16

18

–90 –80

–60

–40

–20

0

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 21. AD9649-40 Single-Tone FFT with f_IN= 9.7 MHz

Figure 23. AD9649-40 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

0

40MSPS

30.5MHz @ –1dBFS

SNR = 73.2dB (74.2dBFS)

SFDR = 95.7dBc

–15

–30

–45

–60

–75

–90

4

3

2

5

–105

–120

6

2

4

6

8

10

12

14

16

18

FREQUENCY (MHz)

Figure 22. AD9649-40 Single-Tone FFT with f_IN= 30.5 MHz

Rev. 0 | Page 14 of 32

AD9649

AD9649-20

AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty cycle

clock, unless otherwise noted.

0

–15

–30

120

20MSPS

9.7MHz @ –1dBFS

SNR = 73.5dBFS (74.5dBFS)

SFDR = 97.2dBc

SFDR (dBFS)

SNR (dBFS)

100

80

–45

–60

60

SFDR (dBc)

–75

–90

40

SNR (dBc)

4

3

5

2

6

–105

–120

20

0

950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50

FREQUENCY (MHz)

–100 –90 –80 –70 –60 –50 –40 –30 –20 –10

0

INPUT AMPLITUDE (dBFS)

Figure 24. AD9649-20 Single-Tone FFT with f_IN= 9.7 MHz

Figure 26. AD9649-20 SNR/SFDR vs. Input Amplitude (AIN) with f_IN= 9.7 MHz

0

20MSPS

30.5MHz @ –1dBFS

SNR = 73.2dB (74.2dBFS)

SFDR = 98.1dBc

–15

–30

–45

–60

–75

–90

3

2

4

6

5

–105

–120

950k 1.90 2.85 3.80 4.75 5.70 6.65 7.60 8.55 9.50

FREQUENCY (MHz)

Figure 25. AD9649-20 Single-Tone FFT with f_IN= 30.5 MHz

Rev. 0 | Page 15 of 32

AD9649

EQUIVALENT CIRCUITS

DRVDD

AVDD

VIN±

Figure 31. Equivalent D0 to D13 and OR Digital Output Circuit

Figure 27. Equivalent Analog Input Circuit

DRVDD

AVDD

SCLK/DFS,

350Ω

MODE,

375Ω

SDIO/PDWN

VREF

30kΩ

7.5kΩ

Figure 32. Equivalent SCLK/DFS, MODE and SDIO/PDWN Input Circuit

Figure 28. Equivalent VREF Circuit

AVDD

DRVDD

AVDD

30kΩ

375Ω

350Ω

SENSE

CSB

Figure 29. Equivalent SENSE Circuit

Figure 33. Equivalent CSB Input Circuit

5Ω

CLK+

15kΩ

0.9V

AVDD

15kΩ

5Ω

CLK–

375Ω

RBIAS

AND VCM

Figure 30. Equivalent Clock Input Circuit

Figure 34. Equivalent RBIAS, VCM Circuit

Rev. 0 | Page 16 of 32

AD9649

THEORY OF OPERATION

high IF frequencies. Either a shunt capacitor or two single-ended

capacitors can be placed on the inputs to provide a matching pas-

sive network. This ultimately creates a low-pass filter at the input

to limit unwanted broadband noise. See the AN-742 Application

Note, the AN-827 Application Note, and the Analog Dialogue

article, “Transformer-Coupled Front-End for Wideband A/D

Converters” (Volume 39, April 2005) for more information. In

general, the precise values depend on the application.

The AD9649 architecture consists of a multistage, pipelined ADC.

Each stage provides sufficient overlap to correct for flash errors in

the preceding stage. The quantized outputs from each stage are

combined into a final 14-bit result in the digital correction logic.

The pipelined architecture permits the first stage to operate with

a new input sample, whereas the remaining stages operate with pre-

ceding samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and an interstage residue amplifier (for example, a multiplying

digital-to-analog converter (MDAC)). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage consists of a flash ADC.

Input Common Mode

The analog inputs of the AD9649 are not internally dc-biased.

Therefore, in ac-coupled applications, the user must provide an

external dc bias. Setting the device so that VCM = AVDD/2

is recommended for optimum performance, but the device can

function over a wider range with reasonable performance, as

shown in Figure 36 and Figure 37.

100

The output staging block aligns the data, corrects errors, and

passes the data to the CMOS output buffers. The output buffers

are powered from a separate (DRVDD) supply, allowing adjust-

ment of the output voltage swing. During power-down, the output

buffers go into a high impedance state.

SFDR (dBc)

90

80

SNR (dBFS)

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9649 is a differential switched-

capacitor circuit designed for processing differential input

signals. This circuit can support a wide common-mode range

while maintaining excellent performance. By using an input

common-mode voltage of midsupply, users can minimize

signal-dependent errors and achieve optimum performance.

70

60

50

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

INPUT COMMON-MODE VOLTAGE (V)

Figure 36. SNR/SFDR vs. Input Common-Mode Voltage,

f_IN= 32.1 MHz, f_S= 80 MSPS

H

C_PAR

100

90

H

VIN+

C_SAMPLE

SFDR (dBc)

SNR (dBFS)

S

C_SAMPLE

VIN–

H

C_PAR

80

H

70

60

50

Figure 35. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 35). When the input

circuit is switched to sample mode, the signal source must be

capable of charging the sample capacitors and settling within one-

half of a clock cycle. A small resistor in series with each input

can help reduce the peak transient current injected from the output

stage of the driving source. In addition, low Q inductors or ferrite

beads can be placed on each leg of the input to reduce high differ-

ential capacitance at the analog inputs and, therefore, achieve the

maximum bandwidth of the ADC. Such use of low Q inductors or

ferrite beads is required when driving the converter front end at

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

INPUT COMMON-MODE VOLTAGE (V)

Figure 37. SNR/SFDR vs. Input Common-Mode Voltage,

f_IN= 10.3 MHz, f_S= 20 MSPS

An on-board, common-mode voltage reference is included in

the design and is available from the VCM pin. The VCM pin

must be decoupled to ground by a 0.1 μF capacitor, as described

in the Applications Information section.

Rev. 0 | Page 1ꢁ of 32

AD9649

Differential Input Configurations

the true SNR performance of the AD9649. For applications above

~10 MHz where SNR is a key parameter, differential double balun

coupling is the recommended input configuration (see Figure 41).

Optimum performance is achieved while driving the AD9649

in a differential input configuration. For baseband applications,

the AD8138, ADA4937-2, and ADA4938-2 differential drivers

provide excellent performance and a flexible interface to the ADC.

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use the AD8352 differential driver.

An example is shown in Figure 42. See the AD8352 data sheet

for more information.

The output common-mode voltage of the ADA4938-2 is easily

set with the VCM pin of the AD9649 (see Figure 38), and the

driver can be configured in a Sallen-Key filter topology to

provide band limiting of the input signal.

In any configuration, the value of Shunt Capacitor C is dependent

on the input frequency and source impedance and may need to

be reduced or removed. Table 9 displays the suggested values to set

the RC network. However, these values are dependent on the

input signal and should be used only as a starting guide.

200Ω

33Ω

VIN–

VIN

76.8Ω

AVDD

90Ω

10pF

ADC

ADA4938-2

33Ω

0.1µF

120Ω

VCM

Table 9. Example RC Network

VIN+

200Ω

R Series

Frequency Range (MHz)

0 to ꢁ0

ꢁ0 to 200

(Ω Each)

C Differential (pF)

Figure 38. Differential Input Configuration Using the ADA4938-2

33

125

22

Open

For baseband applications below ~10 MHz where SNR is a key

parameter, differential transformer coupling is the recommended

input configuration. An example is shown in Figure 39. To bias

the analog input, the VCM voltage can be connected to the

center tap of the secondary winding of the transformer.

Single-Ended Input Configuration

A single-ended input can provide adequate performance in cost-

sensitive applications. In this configuration, SFDR and distortion

performance degrade due to the large input common-mode swing.

If the source impedances on each input are matched, there should

be little effect on SNR performance. Figure 40 shows a typical

single-ended input configuration.

VIN+

R

2V p-p

49.9Ω

C

ADC

R

VCM

VIN–

10µF

AVDD

0.1µF

1kΩ

R

Figure 39. Differential Transformer-Coupled Configuration

VIN+

1V p-p

0.1µF

49.9Ω

1kΩ

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can also

cause core saturation, which leads to distortion.

AVDD

ADC

C

1kΩ

R

VIN–

10µF

0.1µF

1kΩ

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

Figure 40. Single-Ended Input Configuration

0.1µF

R

0.1µF

VIN+

2V p-p

25Ω

P

A

S

P

C

ADC

0.1µF

VCM

VIN–

Figure 41. Differential Double Balun Input Configuration

V

CC

0.1µF

0Ω

0.1µF

16

1

8, 13

11

0.1µF

ANALOG INPUT

R

VIN+

VIN–

2

200Ω

C

ADC

AD8352

10

R

G

C

D

3

4

5

200Ω

VCM

14

0.1µF

ANALOG INPUT

0Ω

0.1µF

Figure 42. Differential Input Configuration Using the AD8352

Rev. 0 | Page 18 of 32

AD9649

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9649. The VREF can be configured using either the internal

1.0 V reference or an externally applied 1.0 V reference voltage.

The various reference modes are summarized in the sections

that follow. The Reference Decoupling section describes the

best practices PCB layout of the reference.

INTERNAL VREF = 0.996V

Internal Reference Connection

A comparator within the AD9649 detects the potential at the

SENSE pin and configures the reference into two possible modes,

which are summarized in Table 10. If SENSE is grounded, the

reference amplifier switch is connected to the internal resistor

divider (see Figure 43), setting VREF to 1.0 V.

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

LOAD CURRENT (mA)

Figure 44. VREF Accuracy vs. Load Current

VIN+

VIN–

4

3

2

ADC

CORE

VREF ERROR (mV)

1

0

VREF

–1

–2

–3

–4

–5

–6

1.0µF

0.1µF

SELECT

LOGIC

SENSE

0.5V

ADC

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

Figure 43. Internal Reference Configuration

Figure 45. Typical VREF Drift

If the internal reference of the AD9649 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 44 shows

how the internal reference voltage is affected by loading.

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 28). The internal buffer generates the

positive and negative full-scale references for the ADC core.

Therefore, the external reference must be limited to a maximum

of 1.0 V.

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 45 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

Table 10. Reference Configuration Summary

Selected Mode

SENSE Voltage (V) Resulting VREF (V)

Resulting Differential Span (V p-p)

Fixed Internal Reference

Fixed External Reference

AGND to 0.2

AVDD

1.0 internal

1.0 applied to external VREF pin

2.0

Rev. 0 | Page 19 of 32

AD9649

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9649 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9649 sample clock inputs,

CLK+ and CLK−, with a differential signal. The signal is typi-

cally ac-coupled into the CLK+ and CLK− pins via a transformer

or capacitors. These pins are biased internally (see Figure 46) and

require no external bias.

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 49. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers offer

excellent jitter performance.

AVDD

0.9V

CLK+

CLK–

0.1µF

CLOCK

INPUT

CLK+

2pF

AD951x

PECL DRIVER

100Ω

ADC

0.1µF

CLOCK

INPUT

CLK–

240Ω

50kΩ

Figure 46. Equivalent Clock Input Circuit

Clock Input Options

Figure 49. Differential PECL Sample Clock (Up to 4× Rated Sample Rate)

The AD9649 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of great concern, as described in the Jitter Considerations section.

A third option is to ac couple a differential LVDS signal to the

sample clock input pins as shown in Figure 50. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

Figure 47 and Figure 48 show two preferred methods for clock-

ing the AD9649. The CLK inputs support up to 4× the rated sample

rate when using the internal clock divider feature. A low jitter clock

source is converted from a single-ended signal to a differential

signal using either an RF transformer or an RF balun.

0.1µF

CLOCK

INPUT

CLK+

AD951x

LVDS DRIVER

100Ω

ADC

0.1µF

CLOCK

INPUT

CLK–

®

50kΩ

Mini-Circuits

ADT1-1WT, 1:1 Z

0.1µF

XFMR

Figure 50. Differential LVDS Sample Clock (Up to 4× Rated Sample Rate)

CLOCK

INPUT

CLK+

100Ω

50Ω

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 ꢀF capacitor (see

Figure 51).

ADC

0.1µF

CLK–

SCHOTTKY

DIODES:

HSMS2822

0.1µF

Figure 47. Transformer-Coupled Differential Clock (3 MHz to 200 MHz)

V

CC

OPTIONAL

100Ω

0.1µF

1

0.1µF

1kΩ

AD951x

CMOS DRIVER

1nF

50Ω

1nF

0.1µF

CLOCK

INPUT

CLK+

CLOCK

INPUT

CLK+

50Ω

ADC

CLK–

SCHOTTKY

DIODES:

0.1µF

HSMS2822

1

50Ω RESISTOR IS OPTIONAL.

Figure 48. Balun-Coupled Differential Clock (Up to 4× Rated Sample Rate)

Figure 51. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

The RF balun configuration is recommended for clock frequen-

cies between 80 MHz and 320 MHz, and the RF transformer is

recommended for clock frequencies from 3 MHz to 200 MHz.

The back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9649 to ~0.8 V p-p

differential.

Input Clock Divider

The AD9649 contains an input clock divider with the ability

to divide the input clock by integer values of 1, 2, or 4.

Rev. 0 | Page 20 of 32

AD9649

Clock Duty Cycle

supplies for clock drivers separate from the ADC output driver

supplies. Low jitter, crystal-controlled oscillators make the best

clock sources. If the clock is generated from another type of source

(by gating, dividing, or another method), it should be retimed by

the original clock at the last step.

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals and, as a result, may be sensitive

to clock duty cycle. Commonly, a 50% duty cycle clock with 5%

tolerance is required to maintain optimum dynamic performance,

as shown in Figure 52.

For more information, see the AN-501 Application Note and the

AN-756 Application Note, which are available on www.analog.com.

Jitter on the rising edge of the clock input can also impact dynamic

performance and should be minimized, as discussed in the Jitter

Considerations section of this datasheet.

80

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 54, the analog core power dissipated by the

AD9649 is proportional to its sample rate. The digital power dis-

sipation of the CMOS outputs are determined primarily by the

strength of the digital drivers and the load on each output bit.

75

70

The maximum DRVDD current (I_DRVDD) can be calculated as

65

60

55

50

45

40

I

_DRVDD= V_DRVDD× C_LOAD× f_CLK× N

where N is the number of output bits (15, in the case of the

AD9649).

This maximum current occurs when every output bit switches

on every clock cycle, that is, a full-scale square wave at the Nyquist

frequency of f_CLK/2. In practice, the DRVDD current is estab-

lished by the average number of output bits that are switching,

which is determined by the sample rate and the characteristics

of the analog input signal.

10

20

30

40

50

60

70

80

POSITIVE DUTY CYCLE (%)

Figure 52. SNR vs. Clock Duty Cycle

Reducing the capacitive load presented to the output drivers can

minimize digital power consumption. The data in Figure 54 was

taken using the same operating conditions as those used for the

Typical Performance Characteristics, with a 5 pF load on each

output driver.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR from the low fre-

quency SNR (SNR_LF) at a given input frequency (f_INPUT) due to

jitter (t_JRMS) can be calculated by

85

SNR_HF= −10 log[(2π × f_INPUT× t_JRMS)²+ 10 ^{(−SNR /10)}

]

LF

80

75

In the previous equation, the rms aperture jitter represents the

clock input jitter specification. IF undersampling applications

are particularly sensitive to jitter, as illustrated in Figure 53.

80

AD9649-80

70

65

AD9649-65

60

55

75

70

65

0.05ps

50

AD9649-40

45

0.2ps

40

AD9649-20

35

10

20

30

40

50

60

70

80

60

55

50

0.5ps

CLOCK RATE (MSPS)

Figure 54. Analog Core Power vs. Clock Rate

1.0ps

1.5ps

In SPI mode, the AD9649 can be placed in power-down mode

directly via the SPI port or by using the programmable external

MODE pin. In non-SPI mode, power-down is achieved by assert-

ing the PDWN pin high. In this state, the ADC typically dissipates

500 μW. During power-down, the output drivers are placed in a

high impedance state. Asserting the PDWN pin (or the MODE pin

in SPI mode) low returns the AD9649 to normal operating mode.

Note that PDWN is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

2.0ps

2.5ps

3.0ps

45

1

10

100

1k

FREQUENCY (MHz)

Figure 53. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases in

which aperture jitter may affect the dynamic range of the AD9649.

To avoid modulating the clock signal with digital noise, keep power

Rev. 0 | Page 21 of 32

AD9649

Low power dissipation in power-down mode is achieved by shut-

ting down the reference, reference buffer, biasing networks, and

clock. Internal capacitors are discharged when entering power-

down mode and then must be recharged when returning to normal

operation. As a result, wake-up time is related to the time spent

in power-down mode, and shorter power-down cycles result in

proportionally shorter wake-up times.

Digital Output Enable Function (OEB)

When using the SPI interface, the data outputs and DCO can be

independently three-stated by using the programmable external

MODE pin. The OEB function of the MODE pin is enabled via

Bits[6:5] of Register 0x08.

If the MODE pin is configured to operate in traditional OEB mode

and the MODE pin is low, the output data drivers and DCOs are

enabled. If the MODE pin is high, the output data drivers and

DCOs are placed in a high impedance state. This OEB function

is not intended for rapid access to the data bus. Note that the

MODE pin is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows

the user to keep the internal reference circuitry powered when

faster wake-up times are required. See the Memory Map section for

more details.

DIGITAL OUTPUTS

TIMING

The AD9649 output drivers can be configured to interface with

1.8 V to 3.3 V CMOS logic families. Output data can also be multi-

plexed onto a single output bus to reduce the total number of traces

required.

The AD9649 provides latched data with a pipeline delay of eight

clock cycles. Data outputs are available one propagation delay (t_PD)

after the rising edge of the clock signal.

Minimize the length of the output data lines and loads placed on

them to reduce transients within the AD9649. These transients may

degrade converter dynamic performance.

The CMOS output drivers are sized to provide sufficient output

current to drive a wide variety of logic families. However, large

drive currents tend to cause current glitches on the supplies and

may affect converter performance.

The lowest typical conversion rate of the AD9649 is 3 MSPS.

At clock rates below 3 MSPS, dynamic performance may degrade.

Applications requiring the ADC to drive large capacitive loads

or large fanouts may require external buffers or latches.

Data Clock Output (DCO)

The AD9649 provides a data clock output (DCO) signal that is

intended for capturing the data in an external register. The CMOS

data outputs are valid on the rising edge of DCO, unless the DCO

clock polarity has been changed via the SPI. See Figure 2 for a

graphical timing description.

The output data format can be selected to be either offset binary

or twos complement by setting the SCLK/DFS pin when operating

in the external pin mode (see Table 11).

As detailed in the AN-877 Application Note, Interfacing to High

Speed ADCs via SPI, the data format can be selected for offset

binary, twos complement, or gray code when using the SPI control.

Table 11. SCLK/DFS and SDIO/PDWN Mode Selection

(External Pin Mode)

Voltage at Pin SCLK/DFS

SDIO/PDWN

GND

Offset binary (default) Normal operation

(default)

DRVDD

Twos complement

Outputs disabled

Table 12. Output Data Format

Input (V)

Condition (V)

Offset Binary Output Mode

Twos Complement Mode

10 0000 0000 0000

00 0000 0000 0000

01 1111 1111 1111

OR

1

0

VIN+ − VIN−

< −VREF − 0.5 LSB

= −VREF

= 0

= +VREF − 1.0 LSB

> +VREF − 0.5 LSB

00 0000 0000 0000

10 0000 0000 0000

11 1111 1111 1111

1

Rev. 0 | Page 22 of 32

AD9649

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9649 includes a built-in test feature designed to enable

verification of the integrity of each channel, as well as facilitate

board-level debugging. Also included is a built-in self-test (BIST)

feature that verifies the integrity of the digital datapath of the

AD9649. Various output test options are also provided to place

predictable values on the outputs of the AD9649.

runs the BIST, enabling Bit 0 (BIST enable) of Register 0x0E

and resetting the PN sequence generator, Bit 2 (BIST init) of

Register 0x0E. Upon completion of the BIST, Bit 0 of Register 0x24

is automatically cleared. The PN sequence can be continued from

its last value by writing a 0 in Bit 2 of Register 0x0E. However, if the

PN sequence is not reset, the signature calculation does not equal

the predetermined value at the end of the test. The user must

then rely on verifying the output data.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD9649 signal path. Perform the BIST test after a reset to ensure

that the part is in a known state. During the BIST test, data from

an internal pseudorandom noise (PN) source is driven through

the digital datapath of both channels, starting at the ADC block

output. At the datapath output, CRC logic calculates a signature

from the data. The BIST sequence runs for 512 cycles and then

stops. When the BIST sequence is complete, the BIST compares

the signature results with a predetermined value. If the signatures

match, the BIST sets Bit 0 of Register 0x24, signifying that the

test passed. If the BIST test failed, Bit 0 of Register 0x24 is cleared.

The outputs are connected during this test so that the PN sequence

can be observed as it runs. Writing the value 0x05 to Register 0x0E

OUTPUT TEST MODES

The output test options are described in Table 16 at Address 0x0D.

When an output test mode is enabled, the analog section of the

ADC is disconnected from the digital back end blocks and the

test pattern is run through the output formatting block. Some of

the test patterns are subject to output formatting, and some are

not. The PN generators from the PN sequence tests can be reset

by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be per-

formed with or without an analog signal (if present, the analog

signal is ignored), but they do require an encode clock. For more

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

Rev. 0 | Page 23 of 32

AD9649

SERIAL PORT INTERFACE (SPI)

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 55 and

Table 5.

The AD9649 SPI allows the user to configure the converter for

specific functions or operations through a structured register space

provided inside the ADC. The SPI gives the user added flexibility

and customization, depending on the application. Addresses are

accessed via the serial port and can be written to or read from via

the port. Memory is organized into bytes that can be further

divided into fields, which are documented in the Memory Map

section. For detailed operational information, see the AN-877

Application Note, Interfacing to High Speed ADCs via SPI.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode. This mode turns

on any SPI pin secondary functions.

CONFIGURATION USING THE SPI

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits, as shown in Figure 55.

Three pins define the SPI of this ADC: the SCLK (SCLK/DFS,

the SDIO (SDIO/PDWN), and the CSB (see Table 13). The SCLK

(a serial clock) is used to synchronize the read and write data

presented from and to the ADC. The SDIO (serial data input/

output) is a dual-purpose pin that allows data to be sent and

read from the internal ADC memory map registers. The CSB

(chip select bar) is an active-low control that enables or disables

the read and write cycles.

All data is composed of 8-bit words. The first bit of the first byte in

a multibyte serial data transfer frame indicates whether a read com-

mand or a write command is issued. This allows the serial data

input/output (SDIO) pin to change direction from an input to

an output at the appropriate point in the serial frame.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an output

at the appropriate point in the serial frame.

Table 13. Serial Port Interface Pins

Function

SCLK Serial clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

Data can be sent in MSB-first mode or in LSB-first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

CSB

Chip select bar. An active-low control that gates the read

and write cycles.

t_HIGH

t_DS

t_CLK

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 55. Serial Port Interface Timing Diagram

Rev. 0 | Page 24 of 32

AD9649

In this mode, connect the CSB chip select to DRVDD, which

disables the serial port interface.

HARDWARE INTERFACE

The pins described in Table 13 constitute the physical interface

between the programming device of the user and the serial port

of the AD9649. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

Table 14. Mode Selection

External

SDIO/PDWN DRVDD

AGND (default)

DRVDD

AGND (default)

Voltage

Configuration

Chip power-down mode

Normal operation (default)

Twos complement enabled

Offset binary enabled

SCLK/DFS

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. For detailed information about one

method for SPI configuration, refer to the AN-812 Application

Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.

SPI ACCESSIBLE FEATURES

Table 15 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9649 part-specific features are described in detail

in Table 16.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used for

other devices, it may be necessary to provide buffers between this

bus and the AD9649 to prevent these signals from transitioning

at the converter inputs during critical sampling periods.

Table 15. Features Accessible Using the SPI

Feature

Description

Modes

Allows the user to set either power-down mode or

standby mode

The SDIO/PDWN and SCLK/DFS pins serve a dual function when

the SPI interface is not being used. When the pins are strapped

to DRVDD or ground during device power-on, they are associated

with a specific function. The Digital Outputs section describes

the strappable functions supported on the AD9649.

Offset Adjust Allows the user to digitally adjust the converter

offset

Test Mode

Allows the user to set test modes to have known

data on output bits

Output Mode Allows the user to set up outputs

CONFIGURATION WITHOUT THE SPI

Output Phase Allows the user to set the output clock polarity

Output Delay Allows the user to vary the DCO delay

In applications that do not interface to the SPI control registers,

the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone

CMOS-compatible control pins. When the device is powered up, it

is assumed that the user intends to use the pins as static control

lines for the power-down and output data format feature control.

Rev. 0 | Page 25 of 32

AD9649

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

DEFAULT VALUES

Each row in the memory map register table (see Table 16) contains

eight bit locations. The memory map is roughly divided into four

sections: the chip configuration registers (Address 0x00 to

Address 0x02); the device transfer registers (Address 0xFF); the

program registers, including setup, control, and test (Address 0x08

to Address 0x2A); and the digital feature control registers

(Address 0x101).

After the AD9649 is reset, critical registers are loaded with default

values. The default values for the registers are given in the memory

map register table (see Table 16).

Logic Levels

An explanation of logic level terminology follows:

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

Table 16 documents the default hexadecimal value for each

hexadecimal address shown. The column with the heading Bit 7

(MSB) is the start of the default hexadecimal value given. For

example, Address 0x2A, the OR/MODE select register, has a hexa-

decimal default value of 0x01. This means that in Address 0x2A,

Bits[7:1] = 0, and Bit 0 = 1. This setting is the default OR/MODE

setting. The default value results in the programmable external

MODE/OR pin (Pin 23) functioning as an out-of-range digital

output. For more information on this function and others, see the

AN-877 Application Note, Interfacing to High Speed ADCs via SPI.

This document details the functions controlled by Register 0x00

to Register 0xFF. The remaining register, Register 0x101, is docu-

mented in the Memory Map Register Descriptions section that

follows Table 16.

•

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 to Address 0x18 are shadowed. Writes to these

addresses do not affect part operation until a transfer command

is issued by writing 0x01 to Address 0xFF, setting the transfer bit.

This allows these registers to be updated internally and simulta-

neously when the transfer bit is set. The internal update takes

place when the transfer bit is set, and then the bit autoclears.

OPEN LOCATIONS

All address and bit locations that are not included in the SPI map

are not currently supported for this device. Unused bits of a valid

address location should be written with 0s. Writing to these loca-

tions is required only when part of an address location is open

(for example, Address 0x2A). If the entire address location is

open, it is omitted from the SPI map (for example, Address 0x13)

and should not be written.

Rev. 0 | Page 2ꢀ of 32

AD9649

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 16 are not currently supported for this device.

Table 16.

Def.

Value

Default

Notes/

Addr.

(MSB)

Bit 7

(LSB)

Bit 0

(Hex) Register Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(Hex)

Comments

Chip configuration registers

0x00

SPI port

configuration

0

LSB first

Soft

reset

1

Soft

reset

LSB first

0

0x18

The nibbles are

mirrored so that

LSB or MSB first

mode registers

correctly, regard-

less of shift

mode.

0x01

0x02

Chip ID

8-bit chip ID, Bits[ꢁ:0]

AD9ꢀ49 = 0xꢀF

Read

only

Unique chip ID

used to differen-

tiate devices;

read only.

Chip grade

Open

Speed grade ID, Bits[ꢀ:4]

(identify device variants of chip ID)

20 MSPS = 000

Open

Read

only

Unique speed

grade ID used to

differentiate

devices; read

only.

40 MSPS = 001

ꢀ5 MSPS = 010

80 MSPS = 011

Device transfer registers

0xFF Transfer

Open

Transfer

0x00

Synchronously

transfers data

from the master

shift register to

the slave.

Program registers

0x08

Modes

External

Pin 23

MODE

input

External Pin 23

00 = chip run

01 = full power-down

10 = standby

11 = chip wide

digital reset

Determines

function when high

00 = full power-down

01 = standby

10 = normal mode,

output disabled

11 = normal mode,

output enabled

various generic

modes of chip

operation.

enable

0x0B

0x0D

Clock divide

Test mode

Open

Clock divider, Bits[2:0]

Clock divide ratio

000 = divide-by-1

001 = divide-by-2

011 = divide-by-4

0x00

The divide ratio

is the value + 1.

User test mode

00 = single

01 = alternate

10 = single once

11 = alternate once

Reset PN Reset PN

long gen short

gen

Output test mode, Bits[3:0] (local)

0000 = off (default)

When set, the

test data is

placed on the

output pins in

place of normal

data.

0001 = midscale short

0010 = positive FS

0011 = negative FS

0100 = alternating checkerboard

0101 = PN 23 sequence

0110 = PN 9 sequence

0111 = 1/0 word toggle

1000 = user input

1001 = 1/0 bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

0x0E

0x10

BIST enable

Offset adjust

Open

BIST init

Open

BIST

enable

0x00

When Bit 0 is set,

the built-in self-

test function is

initiated.

8-bit device offset adjustment, Bits[ꢁ:0] (local)

Device offset

trim.

Offset adjust in LSBs from +12ꢁ to −128 (twos complement format)

Rev. 0 | Page 2ꢁ of 32

AD9649

Def.

Value

Default

Notes/

Addr.

(MSB)

Bit 7

(LSB)

Bit 0

(Hex) Register Name

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(Hex)

Comments

0x14

Output mode

00 = 3.3 V CMOS

10 = 1.8 V CMOS

Open

Output

disable

Open

Output

invert

00 = offset binary

01 = twos

complement

10 = gray code

11 = offset binary

0x00

0x22

Configures the

outputs and the

format of the

data.

0x15

Output adjust

3.3 V DCO

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

1.8 V DCO

3.3 V data

1.8 V data

Determines

CMOS output

drive strength

properties.

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes

(default)

drive strength

00 = 1 stripe

(default)

01 = 2 stripes

10 = 3 stripes

11 = 4 stripes

drive strength

00 = 1 stripe

01 = 2 stripes

10 = 3 stripes

(default)

11 = 4 stripes

0x1ꢀ

Output phase

DCO

Open

Input clock phase adjust,

Bits[2:0]

(Value is number of input clock

cycles of phase delay)

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = ꢀ input clock cycles

111 = ꢁ input clock cycles

0x00

On devices that

use global clock

divide, deter-

mines which

output

polarity

0 =

normal

1 = inv

phase of the

divider output is

used to supply

the output clock;

internal latching

is unaffected.

0x1ꢁ

Output delay

Enable

DCO

delay

Open

Enable

data

delay

Open

DCO/data delay, Bits[2:0]

000 = 0.5ꢀ ns

001 = 1.12 ns

010 = 1.ꢀ8 ns

011 = 2.24 ns

100 = 2.80 ns

101 = 3.3ꢀ ns

110 = 3.92 ns

111 = 4.48 ns

0x00

Sets the fine

output delay of

the output clock

but does not

change internal

timing.

0x19

0x1A

0x1B

0x1C

0x24

USER_PATT1_LSB

USER_PATT1_MSB

USER_PATT2_LSB

USER_PATT2_MSB

BIST signature LSB

Bꢁ

Bꢀ

B5

B4

B3

B2

B1

B9

B1

B9

B0

B8

B0

B8

0x00

User-defined

Pattern 1 LSB.

B15

Bꢁ

B14

Bꢀ

B13

B5

B12

B4

B11

B3

B10

B2

User-defined

Pattern 1 MSB.

User-defined

Pattern 2 LSB.

B15

B14

B13

B12

B11

B10

User-defined

Pattern 2 MSB.

BIST signature, Bits[ꢁ:0]

Least significant

byte of BIST sig-

nature, read only.

0x2A

OR/MODE select

Open

0 =

0x01

Selects I/O

MODE

1 = OR

(default)

functionality in

conjunction with

Address 0x08 for

MODE (input) or

OR (output) on

External Pin 23.

Digital feature control register

0x101 USR2

1

Enable

GCLK

detect

Run

GCLK

Disable

SDIO

pull-

0x88

Enables internal

oscillator for

clock rates of

<5 MHz.

down

Rev. 0 | Page 28 of 32

AD9649

Bit 2—Run GCLK

MEMORY MAP REGISTER DESCRIPTIONS

Bit 2 enables the GCLK oscillator. For some applications with

encode rates below 10 MSPS, it may be preferable to set this bit

high to supersede the GCLK detector.

For additional information about functions controlled in

Register 0x00 to Register 0xFF, see the AN-877 Application

Note, Interfacing to High Speed ADCs via SPI.

Bit 0—Disable SDIO Pull-Down

USR2 (Register 0x101)

Bit 0 can be set high to disable the internal 30 kꢁ pull-down on

the SDIO pin, which can be used to limit the loading when many

devices are connected to the SPI bus.

Bit 3—Enable GCLK Detect

Normally set high, Bit 3 enables a circuit that detects encode

rates below ~5 MSPS. When a low encode rate is detected, an

internal oscillator, GCLK, is enabled, ensuring the proper oper-

ation of several circuits. If set low, the detector is disabled.

Rev. 0 | Page 29 of 32

AD9649

APPLICATIONS INFORMATION

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), at www.analog.com.

DESIGN GUIDELINES

Before starting the design and layout of the AD9649 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements needed for certain pins.

Power and Ground Recommendations

When connecting power to the AD9649, it is strongly recom-

mended that two separate supplies be used. Use one 1.8 V supply

for analog (AVDD); use a separate 1.8 V to 3.3 V supply for the

digital output supply (DRVDD). If a common 1.8 V AVDD and

DRVDD supply must be used, the AVDD and DRVDD domains

must be isolated with a ferrite bead or filter choke and separate

decoupling capacitors. Several different decoupling capacitors can

be used to cover both high and low frequencies. Locate these

capacitors close to the point of entry at the PCB level and close

to the pins of the part, with minimal trace length.

Encode Clock

For optimum dynamic performance, use a low jitter encode

clock source with a 50% duty cycle ( 5%) to clock the AD9649.

VCM

The VCM pin should be decoupled to ground with a 0.1 ꢀF

capacitor, as shown in Figure 39.

A single PCB ground plane should be sufficient when using the

AD9649. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

RBIAS

The AD9649 requires that a 10 kΩ resistor be placed between

the RBIAS pin and ground. This resistor sets the master current

reference of the ADC core and should have at least a 1% tolerance.

Exposed Paddle Thermal Heat Sink Recommendations

Reference Decoupling

The exposed paddle (Pin 0) is the only ground connection for

the AD9649; therefore, it must be connected to analog ground

(AGND) on the customer’s PCB. To achieve the best electrical

and thermal performance, mate an exposed (no solder mask)

continuous copper plane on the PCB to the AD9649 exposed

paddle, Pin 0.

Externally decouple the VREF pin to ground with a low ESR,

1.0 ꢀF capacitor in parallel with a low ESR, 0.1 ꢀF ceramic

capacitor.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9649 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. Fill or plug these vias with nonconduc-

tive epoxy.

Rev. 0 | Page 30 of 32

AD9649

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

EXPOSED

PAD

(BOTTOM VIEW)

3.65

3.50 SQ

3.35

TOP

VIEW

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

0.80 MAX

0.65 TYP

3.50 REF

12° MAX

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 56. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-4)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

–40°C to +85°C

Package Description

Package Option

CP-32-4

AD9ꢀ49BCPZ-80^{1, 2}

AD9ꢀ49BCPZRLꢁ-80^{1, 2}

AD9ꢀ49BCPZ-ꢀ5^{1, 2}

AD9ꢀ49BCPZRLꢁ-ꢀ5^{1, 2}

AD9ꢀ49BCPZ-40^{1, 2}

AD9ꢀ49BCPZRLꢁ-40^{1, 2}

AD9ꢀ49BCPZ-20^{1, 2}

AD9ꢀ49BCPZRLꢁ-20^{1, 2}

AD9ꢀ49-80EBZ¹

32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Evaluation Board

AD9ꢀ49-ꢀ5EBZ¹

Evaluation Board

AD9ꢀ49-40EBZ¹

AD9ꢀ49-20EBZ¹

¹Z = RoHS Compliant Part.

²The exposed paddle (Pin 0) is the only GND connection on the chip and must be connected to the PCB AGND.

Rev. 0 | Page 31 of 32

AD9649

NOTES

registered trademarks are the property of their respective owners.

D08539-0-10/09(0)

Rev. 0 | Page 32 of 32


型号：	AD9649BCPZ-40
厂家：	ADI
描述：	14-Bit, 20/40/65/80 MSPS 1.8 V Analog-to-Digital Converter 14位20/40/65/80 MSPS， 1.8 V模拟数字转换器转换器模数转换器 PC
文件：	总32页 (文件大小：1285K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9649BCPZ-40 [ADI]

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AD9649BCPZRL7-65

AD9649BCPZRL7-80

AD9649_17

AD9650

AD9650-105EBZ

AD9650-25EBZ

AD9650-65EBZ

AD9650-80EBZ