AD9665 [ADI]
4-Channel, LVDS, Dual-Output, Laser Diode Driver with Oscillator; 4通道， LVDS ，双路输出，激光二极管驱动器与振荡器
| 型号： | AD9665 |
| 厂家： | 
ADI |
| 描述： | 4-Channel, LVDS, Dual-Output, Laser Diode Driver with Oscillator |
| 文件： | 总17页 (文件大小：447K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4-Channel, LVDS, Dual-Output,
Laser Diode Driver with Oscillator
AD9665
FUNCTIONAL BLOCK DIAGRAM
FEATURES
W3SET
W3DIS
W3DISN
Dual, current-controlled output current sources with 4 input
channels
WRITE
CHANNEL 3
TTL-selectable output
W2SET
W2DIS
W2DISN
Stable on-chip oscillators with independent frequency and
amplitude control
WRITE
OUTPUT A
OUTPUT B
ENABLE
LD1
LD2
CHANNEL 2
TTL- or LVDS-selectable write channel enables negative logic
Independent TTL oscillator enables positive logic
170 mA minimum output current for the read channel
510 mA minimum output current for Write Channel 1
330 mA minimum output current for Write Channel 2
165 mA minimum output current for Write Channel 3
950 mA typical total output current
W1SET
W1DIS
W1DISN
WRITE
CHANNEL 1
RSET
RDIS
READ CHANNEL
OSCILLATOR
Typical rise time/fall time of 0.8 ns
Low power consumption
OSCEN
Single 5 V power supply ( 10%)
INS OUTSEL
F
F
A
A
ADJ2
ADJ1
ADJ2
ADJ1
Figure 1. 4-Channel, LVDS, Laser Driver Block Diagram
APPLICATIONS
DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM
supercombo drives
Magneto-optical (MO) drives
Laser diode current switching
1
2
3
4
5
6
7
8
24
23
W3DISN
W3DIS*
GND
INS
V
DD
22
21
GENERAL DESCRIPTION
LD1
LD1
GND
LD2
LD2
AD9665
GND
The AD9665 is a laser diode driver for high performance CD-RW
and DVD recordable drives. It includes four channels for four
different optical power levels: the read channel generates a
continuous output power level, whereas Channel 1, Channel 2,
and Channel 3 can be used as write channels that can be
controlled with an LVDS or TTL interface. The WxDIS and
LFCSP
20
19
18
17
W2DISN
W2DIS*
W1DISN
W1DIS*
5mm
(Not to Scale)
× 5mm
V
DD
RDIS
pins are active low logic. The OSCEN pin is controlled by
*TTL ACTIVE LOW
NOTES
an active high TTL signal. All active channels are summed at
the output where Write Channel 1 can contribute at least
325 mA output current, and Write Channel 2 and Write
Channel 3 can contribute at least 250 mA and 150 mA,
respectively. The level of the output current is set by an
external resistor, which converts this voltage into a current
at the WxSET pin.
1. THE EXPOSED PAD SHOULD BE CONNECTED TO GROUND.
Figure 2. 4-Channel, LVDS, Laser Driver Pin Configuration
An on-chip oscillator is provided to allow output current
modulation and to reduce laser-mode hopping. Four external
resistors permit the setting of two distinct values for the
frequency and swing of the oscillator. The oscillator can output
up to 100 mA p-p of current (push-pull oscillator) with a
frequency range of 200 MHz to 500 MHz.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
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Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
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Last content update 08/25/2013 11:00 pm
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4-Channel, LVDS, Dual-Output, Laser Diode Driver with Oscillator
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AD9665
TABLE OF CONTENTS
Features .............................................................................................. 1
Board Layout..................................................................................9
Temperature Considerations .......................................................9
Shutdown Supply Current Variation ....................................... 11
Evaluation Board ............................................................................ 12
Schematic..................................................................................... 12
Operation......................................................................................... 13
Pin Descriptions ......................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Logic Table......................................................................................... 8
Applications....................................................................................... 9
REVISION HISTORY
8/10—Revision E: Initial Version
Rev. E | Page 2 of 16
AD9665
SPECIFICATIONS
RDIS
At 25°C, VDD = 5 V, ENABLE = 1, OSCEN = 0, FADJ = 6.81 kΩ, AADJ = 5.76 kΩ, VOUT = 2.5 V, IOUT = 50 mA (Read),
unless otherwise specified.
= 0,
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
LASER AMPLIFIER
Output Current Read Channel
Output is sourcing, IIN = 2 mA
Output is sourcing, VOUT = 3.5 V, IIN = 2 mA
Output is sourcing, IIN = 2 mA
Output is sourcing, VOUT = 3.5 V, IIN = 2 mA
Output is sourcing, IIN = 2 mA
Output is sourcing, VOUT = 3.5 V, IIN = 2 mA
Output is sourcing, IIN = 2 mA
Output is sourcing, VOUT = 3.5 V, IIN = 2 mA
All channels sourcing, IIN = 1.45 mA
All channels sourcing, VOUT = 3.5 V, IIN = 1.45 mA
Read channel or Write Channel 31
Write Channel 12 or Write Channel 23
Write Channel 1, VOUT = 3.5 V, IIN = 2 mA4
Read channel1
170
150
510
450
330
290
165
145
875
775
−1.5
−1.0
−15
85
190
170
540
480
360
320
185
165
950
850
0.4
mA
mA
Output Current Write Channel 1
Output Current Write Channel 2
Output Current Write Channel 3
Total Output Current (See Figure 11)
Output Current Linearity Error
mA
mA
mA
mA
mA
mA
mA
mA
+1.5
+1.0
%
0.2
%
−9
%
Best-Fit Current Gain
Best-Fit Current Offset
105
300
200
100
−2
115
335
225
110
+4
mA/mA
mA/mA
mA/mA
mA/mA
mA
Write Channel 12
Write Channel 23
Write Channel 31
Read channel or Write Channel 31
Write Channel 12
265
165
80
−7
−17
−11
140
−3
+11
+8
mA
Write Channel 23
−1
mA
IIN Input Impedance (RIN), All Channels
IOUT Current Output Noise
RIN to GND, IOUT = 0 mA
200
100
3.5
260
Ω
f = 300 MHz
pA/√Hz
%/V
%/V
IOUT Supply Sensitivity, (PSRR) Read Mode
IOUT Supply Sensitivity, (PSRR) Write Mode
VDD = 5 V 10%
IOUT = 100 mA, 50 mA read channel,
3.5
50 mA any write channel, VDD = 5 V 10%
IOUT Temperature Sensitivity, Read Mode
IOUT Temperature Sensitivity, Write Mode
175
150
390
350
ppm/°C
ppm/°C
ppm/°C
ppm/°C
IOUT = 100 mA (50 mA read channel, 50 mA Write Channel 1)
IOUT = 100 mA (50 mA read channel, 50 mA Write Channel 2)
IOUT = 100 mA (50 mA read channel, 50 mA Write Channel 3)
LASER AMPLIFIER AC SPECIFICATIONS
Write Rise Time
IOUT = 50 mA (read channel), 150 mA (Write Channel 1)5
IOUT = 65 mA (read channel), 375 mA (Write Channel 1),
0.75
0.8
0.95
1.3
ns
ns
V
DD = 5 V, VOUT = 3.5 V6
IOUT = 50 mA (read channel), 100 mA (Write Channel 2)5
IOUT = 50 mA (read channel), 50 mA (Write Channel 3)5
IOUT = 50 mA (read channel), 150 mA (Write Channel 1)7
IOUT = 65 mA (read channel), 375 mA (Write Channel 1),
0.6
0.8
ns
ns
ns
ns
0.55
0.55
0.4
0.75
0.75
0.6
Write Fall Time
V
DD = 5 V, VOUT = 3.5 V8
IOUT = 50 mA (read channel), 100 mA (Write Channel 2)7
IOUT = 50 mA (read channel), 50 mA (Write Channel 3)7
Logic at 50% of final value to IOUT at 50% of final value
Logic at 50% of final value to IOUT at 50% of final value
ENABLE 50% H-L to IOUT at 50% of final value
0.55
0.45
5.2
6.3
3.8
5.5
3
0.75
0.65
ns
ns
ns
ns
ns
ns
ns
IOUT ON Propagation Delay (LVDS Mode)
IOUT OFF Propagation Delay (LVDS Mode)
Disable Time
Enable Time
ENABLE 50% L-H to IOUT at 50% of final value
Output Switching Time
OUTSEL 50% to IOUT at 50% of final value
OSCILLATOR SPECIFICATIONS
Oscillator Frequency
OSCEN = 1
280
315
50
340
MHz
Oscillator Amplitude
OSCEN = 1
mA p-p
μA p-p/°C
kHz/°C
Oscillator Temperature Coefficient
Oscillator amplitude, OSCEN = 1
Oscillator frequency, OSCEN = 1
60
195
Rev. E | Page 3 of 16
AD9665
Parameter
Conditions
Min
Typ
2
Max
Unit
ns
Disable Time Oscillator
Enable Time Oscillator
LOGIC SPECIFICATIONS
INS = 1 (LVDS Mode)
Minimum Differential Input Voltage
Maximum Differential Input Voltage
Valid Input Voltage
OSCEN 50% H-L to IOUT at 50% of final value, OSCEN = 1
OSCEN 50% L-H to IOUT at 50% of final value, OSCEN = 1
4
ns
Magnitude
100
0
mV
mV
V
Magnitude
600
2.4
Relative to GND
OUTEN
Logic HI Threshold
Temperature stabilized
Temperature stabilized
2.0
V
V
Logic LO Threshold
SUPPLY CURRENT9
0.8
W1DIS10
W2DIS10
W3DIS10
ENABLE
OSCEN
RDIS
INS = 1 (LVDS Mode)
Power Down
0
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
8.6
26
46
54
mA
mA
mA
mA
Inputs Disabled, Read Enabled
Inputs Disabled, Oscillator Enabled
Read Mode, Oscillator Enabled11
IOUT = 50 mA
Write Mode11
1
0
1
0
0
0
49
mA
IOUT = 150 mA (50 mA Write
Channel 1, Write Channel 2,
Write Channel 3)
INS = 0 (TTL Mode)
Power-Down
0
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
9.5
23
43
51
mA
mA
mA
mA
Inputs Disabled, Read Enabled
Inputs Disabled, Oscillator Enabled
Read Mode, Oscillator Enabled11
IOUT = 50 mA
Write Mode11
1
0
1
0
0
0
43
mA
IOUT = 150 mA (50 mA Write
Channel 1, Write Channel 2,
Write Channel 3)
OPERATING CONDITIONS
Supply Voltage Range
4.5
5.5
V
Operating Temperature Range
−25
+85
°C
1 Output linearity, offset current, and gain are calculated using the best-fit method at 30 mA, 60 mA, and 90 mA. The transfer function is IOUT = (IIN × GAIN) + IOS
.
2 Output linearity, offset current, and gain are calculated using the best-fit method at 90 mA, 120 mA, and 150 mA. The transfer function is IOUT = (IIN × GAIN) + IOS
.
3 Output linearity, offset current, and gain are calculated using the best-fit method at 60 mA, 90 mA, and 120 mA. The transfer function is IOUT = (IIN × GAIN) + IOS
.
4
Output linearity is calculated using the best-fit method, which is calculated at 90 mA, 120 mA, and 150 mA, extrapolated to IIN = 2 mA.
5 Measured electrically from 10% to 90% of final value. Sharp Diode—GH06550B2B (see Figure 14).
6 Measured electrically from 10% to 90% of final value. Mitsubishi Diode—ML101J26. RL = 0.66 Ω (see Figure 14).
7 Measured electrically from 90% to 10% of final value. Sharp Diode—GH06550B2B (see Figure 14).
8 Measured electrically from 90% to 10% of final value. Mitsubishi Diode—ML101J26. RL = 0.66 Ω (see Figure 14).
9 See the Shutdown Supply Current Variation section for more information.
10 WxDIS = 0 means channel is off regardless of mode: TTL or LVDS (see Table 3). WxDIS = 1 means channel is on regardless of mode: TTL or LVDS (see Table 3).
11 The value specified does not include the output current.
Rev. E | Page 4 of 16
AD9665
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Range
Supply Voltage (+VDD)
Pins 10, 11, 17, 23, 32
6 V
Input Pins
Pins 12, 13, 14, 15
2.2 mA
Pins 1, 2, 5, 6, 7, 8, 9, 16, 24, 29, 30
Internal Power Dissipation1
5 mm × 5 mm, 32-Lead, Pad-Up LFCSP
Operating Temperature Range
Storage Temperature Range
−0.8 V to +VDD
2 W
ESD CAUTION
−25°C to +85°C
−65°C to +150°C
1 Power dissipation is specified on semistandard 4-layer board.
Rev. E | Page 5 of 16
AD9665
TYPICAL PERFORMANCE CHARACTERISTICS
700
200
175
150
125
100
75
A
= 5.76kΩ
F
= 6.81kΩ
ADJ
ADJ
600
500
400
300
200
100
0
READ (50mA)
READ (50mA) AND WRITE 3 (50mA)
READ (50mA) AND WRITE 2 (50mA)
READ (50mA) AND WRITE 1 (50mA)
50
25
0
0
2
4
6
8
10
12
14
0
2
4
6
8
10
RESISTANCE (kΩ)
ADJUST
12
14
F
RESISTANCE (kΩ)
A
ADJ
Figure 3. Oscillator Frequency vs. FADJ
Figure 6. Oscillator Amplitude vs. AADJ
70
60
50
40
30
20
10
0
70
65
60
55
50
45
40
35
30
A
= 5.76kΩ
A
F
= 5.76kΩ
= 6.81kΩ
ADJ
ADJ
ADJ
(50mA)
READ
(50mA)
(50mA)
READ
AND WRITE 3
(50mA)
(50mA)
READ
AND WRITE 2
(50mA)
READ
AND WRITE 1
(50mA)
200
250
300
350
400
450
500
550
600
0
10
20
30
I
40
50
60
70
80
90
100
FREQUENCY (MHz)
CURRENT (mA DC)
OUT
Figure 4. Oscillator Amplitude vs. Frequency
Figure 7. Oscillator Amplitude vs. IOUT-DC
–20
–30
–40
–50
–60
–70
–80
2.5
SECOND HARMONIC
THIRD HARMONIC
2.0
1.5
1.0
0.5
0
OUT 2
FOURTH HARMONIC
OUT 1
FIFTH HARMONIC
0.1
1
10
100
1000
100
200
300
400
500
600
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. IOUT Current Noise
Figure 8. Oscillator Distortion vs. Frequency
Rev. E | Page 6 of 16
AD9665
60
55
50
45
40
35
30
330
325
320
315
310
305
300
WRITE 3
READ
WRITE 1
WRITE 2
A
F
= 5.76kΩ
= 6.81kΩ
A
F
= 5.76kΩ
= 6.81kΩ
ADJ
ADJ
ADJ
ADJ
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Oscillator Amplitude vs. Temperature
Figure 12. Oscillator Frequency vs. Temperature
1250
1000
750
500
250
0
1250
1000
750
500
250
0
V
V
= 5V
V
V
= 5V
DD
DD
= 2.5V
= 3.5V
OUT
OUT
TEMPERATURE = 25°C
TEMPERATURE = 25°C
TOTAL I
OUT
TOTAL I
OUT
WRITE 1
WRITE 1
READ
WRITE 2
WRITE 2
READ
WRITE 3
1.8
WRITE 3
1.8 2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
INPUT CURRENT (mA)
INPUT CURRENT (mA)
Figure 10. Output Current vs. Input Current for Each Channel, VOUT = 2.5 V
Figure 13. Output Current vs. Input Current for Each Channel, VOUT = 3.5 V
1000
AD9665
V
= 5V
DD
TEMPERATURE = 25°C
V
= 2V
OUT
READ
4.32kΩ 200Ω
INS
V
= 2.5V
OUT
800
600
400
200
0
+5V
V
_RD
IN
WR1
4.32kΩ 200Ω
V
= 3V
OUT
V
V
V
_WR1
_WR2
_WR3
IN
IN
IN
I
_1
OUT
WR2
4.32kΩ 200Ω
50Ω
SCOPE
LD_1
V
= 3.5V
OUT
R
WR3
4.32kΩ 200Ω
S
R
L
R
46.4Ω
TERM
3.4Ω
50Ω
RD ENABLE
W1_P
W1_N
I
_2
OUT
I
= I
= I
= I
= I
IN
IN_RD
IN_WR1
IN_WR2
IN_WR3
1.8
50Ω
SCOPE
R
WR1 ENABLE
LD_2
T
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.0
100Ω
INPUT CURRENT FOR EACH CHANNEL (mA)
R
S
R
L
R
46.4Ω
TERM
3.4Ω
50Ω
Figure 11. Total IOUT vs. IIN
W2_P
R
100Ω
T
WR2 ENABLE
WR3 ENABLE
W2_N
W3_P
R
T
100Ω
OUTSEL
+5V
W3_N
Figure 14. Electrical LVDS Pulse Response Schematic
Rev. E | Page 7 of 16
AD9665
LOGIC TABLE
Table 3.
ENABLE OUTSEL OSCEN
INS
RDIS
W1DIS
W1DISN
W2DIS
W2DISN
W3DIS
W3DISN
OSC
LD1
LD2
L
H
H
x
L
L
x
L
x
x
x
x
x
x
x
x
x
OFF
OFF
L
L
L
L
H
H
x
x
H
H
x
x
H
H
x
x
OFF
ON
OFF
OFF
I
× 100mA/mA
RSET
I
I
× 100mA/mA +
RSET
H
(F
+ A
)
OSC ADJ2
ADJ2
I
×
W1SET
300mA/mA +
(F + A
H
H
H
L
L
L
H
H
H
L
L
L
H
H
H
L
H
H
x
x
x
H
L
x
x
x
H
H
L
x
x
x
ON
ON
ON
OFF
OFF
OFF
I
)
OSC ADJ2 ADJ2
I
I
× 200mA/mA +
W2SET
I
(F
+ A )
OSC ADJ2
ADJ2
× 100mA/mA +
W3SET
I
(F
+ A
)
H
OSC ADJ2
ADJ2
I
(F
OSC ADJ2
+ A
)
ADJ2
H
H
L
L
H
L
L
H
L
H
H
x
H
H
x
H
H
x
ON
OFF
OFF
(NOT RECOMMENDED)
H
L
L
L
OFF
I
× 100mA/mA
RSET
I
I
× 100mA/mA +
RSET
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
L
L
L
H
H
H
L
L
L
ON
ON
ON
ON
OFF
OFF
OFF
OFF
(F
+ A
)
OSC ADJ2
ADJ2
I
×
W1SET
300mA/mA +
(F + A
I
)
OSC ADJ2 ADJ2
I
I
× 200mA/mA +
W2SET
I
(F
+ A )
H
H
H
L
L
OSC ADJ2
ADJ2
× 100mA/mA +
W3SET
I
(F
+ A
)
L
H
H
OSC ADJ2
ADJ2
I
(F
OSC ADJ2
+ A
)
ADJ2
H
H
L
H
L
H
L
H
L
H
H
x
x
H
H
x
x
H
H
x
x
ON
OFF
(NOT RECOMMENDED)
H
OFF
I
× 100mA/mA
OFF
RSET
I
I
× 100mA/mA +
RSET
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
H
H
L
x
x
x
x
H
H
L
x
x
x
x
H
H
H
L
x
x
x
x
ON
ON
ON
ON
OFF
OFF
OFF
OFF
(F
+ A )
OSC ADJ1
ADJ1
I
× 300mA/mA +
W1SET
I
(F
+ A )
OSC ADJ1
ADJ1
I
I
× 200mA/mA +
W2SET
I
(F
+ A )
H
H
OSC ADJ1
ADJ1
× 100mA/mA +
W3SET
I
(F
+ A
)
H
OSC ADJ1
ADJ1
I
(F
OSC ADJ1
+ A
)
ADJ1
H
H
H
H
H
L
L
H
L
H
H
x
H
H
x
H
H
x
ON
OFF
OFF
(NOT RECOMMENDED)
H
L
L
L
OFF
I
× 100mA/mA
RSET
I
I
× 100mA/mA +
RSET
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
L
H
H
L
L
L
H
H
H
L
L
L
ON
ON
ON
(F
+ A
)
OFF
OFF
OFF
OSC ADJ1
ADJ1
I
I
I
× 300mA/mA +
W1SET
I
(F
+ A )
OSC ADJ1
ADJ1
× 200mA/mA +
W2SET
I
(F
+ A )
H
H
H
L
OSC ADJ1
ADJ1
× 100mA/mA +
W3SET
I
(F
+ A
)
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
ON
ON
OFF
OFF
OSC ADJ1
ADJ1
I
(F
OSC ADJ1
+ A
)
ADJ1
H
H
L
H
(NOT RECOMMENDED)
OUTSEL
INS
OSCEN
TTL
H = LD1 OUTPUT
L = LD2 OUTPUT
H = LVDS
L = TTL
H = OSCILLATOR ON
L = OSCILLATOR OFF
USE LVDS + INPUT
Rev. E | Page 8 of 16
AD9665
APPLICATIONS
The AD9665 uses the current at one or more of its four inputs,
RSET, W1SET, W2SET, and W3SET, and generates an output
current proportional to the sum of the input currents. The read
channel has a typical gain of 105 mA/mA, Write Channel 1 has
a typical gain of 300 mA/mA, Write Channel 2 has a typical
gain of 200 mA/mA, and Write Channel 3 has a typical gain of
100 mA/mA. The input impedance of all the channels is
typically 200 Ω. In most cases, a voltage output DAC can be
used to drive these channels. In this case, a series resistance
should be placed between each of the DAC channels and the
respective input on the AD9665. These resistances should be
selected to scale the desired maximum output current for each
channel with an appropriate voltage from the DAC without
excessively loading it.
Add this to the ~2 V of operating voltage that is required for the
laser diode, and voltage headroom can become a problem if
operating on a 5 V supply. Because the di/dt term seems to be a
system requirement, L is the only contributor that can be
changed when trying to reduce the voltage drop. Decreasing the
inductance of the FPC can be done by either making the trace
wider or by making it shorter. Because the distance from the
laser diode driver (LDD) to the laser diode is fixed, using a
wider trace is the only option. This can be accomplished by
changing from a single-layer FPC design to a double-layer FPC
design. This additional layer allows the full width of the FPC
from the LDD to the laser diode to be used for the drive
current, while the bottom layer can be used entirely for the
return path (see Figure 15).
BOARD LAYOUT
Due to the fast rise and fall time (<1 ns) required for the
operation of high speed drives, trace lengths carrying high
VIA
speed signals, such as
, W1DIS, W2DIS, and W3DIS, and
RDIS
I
DIODE
I
DIODE
I
DIODE
I
DIODE
the output current should be kept as short as possible to
minimize series inductance. A decoupling capacitor should be
located near each VDD pin, and the ground return for the
cathode of the laser diode should be kept as short as possible.
LASER
DIODE
TOP
TRACE
An S11 measurement of a piece of flexible printed circuit board
(FPC) can show the inductance associated with that section of
the FPC. In Table 4, an S11 measurement of two different pieces
of a 19 mm (0.75 in) FPC was taken. The first piece is a single
layer of an FPC with 0.5 ounce copper and 25.4 micron (1 mil)
thick Kapton® and coverlay. The second piece is an FPC with
2 layers of 0.5 ounce copper and 25.4 micron (1 mil) thick
Kapton and coverlay.
BOTTOM
TRACE
SINGLE-LAYER
FPC
DOUBLE-LAYER
FPC
Figure 15. Single-Layer and Double-Layer Flexible Printed Circuit Boards
TEMPERATURE CONSIDERATIONS
The AD9665 is available in a 32-lead LFCSP with an exposed
heat pad on top of the package. Using a 4-layer JEDEC standard
test board, the θJA of this package was determined without any
external heat sink attached to the exposed pad. This board is
made of FR4, is 1.60 mm thick, and consists of four copper
layers. The two internal layers are solid copper (1 oz/in2 or
0.35 mm thick). The two surface layers (containing the
component and back side traces) use 2 oz/in2 (0.70 mm thick)
of copper. This method of construction yields a θJA for the
AD9665 of approximately 110°C/W. An integrated circuit
dissipating 500 mW and packaged in an LFCSP, while operating
in an ambient environment of 85°C, would have an internal
junction temperature of approximately 140°C.
Table 4. Inductance of FPC
S11
L, nH @ 10 MHz
L, nH @ 300 MHz
Single-layer FPC
Double-layer FPC
8.8
4.3
8.5
4.2
As indicated by the measurement results, using two layers of
copper in an FPC can reduce inductance by over 50%. Using the
basic circuit equation
di
V = L
dt
85°C + 0.5 W × 110°C/W = 140°C
it can be seen that increasing the amplitude of a current step
increases the voltage drop across the inductor. For example, on
the single-layer FPC, a 200 mA pulse with a rise time of 1 ns
generates a voltage drop of 1.86 V, assuming an additional
0.5 nH of inductance due to the laser diode itself. Increase this
current to 250 mA, and the voltage drop is greater than 2.3 V.
This junction temperature is within the maximum
recommended operating junction temperature of 150°C. This
can be improved by attaching an external heat sink to the exposed
heat pad of the package. Of course, this is not a realistic method for
mounting a laser diode driver in an optical storage device.
In an actual application, the laser diode driver would most
likely be mounted to a flexible circuit board. The θJA of a system
is highly dependent on the board layout, material, and heat
sink. The user must consider these conditions carefully.
Rev. E | Page 9 of 16
AD9665
Some of the circuitry of the AD9665 can be used to monitor the
internal junction temperature.
While the power to the AD9665 is disconnected, the AD9665
should be allowed to reach thermal equilibrium (at the desired
ambient temperature). With all channels turned off such that
The AD9665 uses a combination of diodes and transistors to
protect it from electrostatic discharge (ESD). All input pins have
a diode between them and ground, with the anode connected to
ground and the cathode connected to the particular input pin.
The base-emitter junction of a PNP transistor is used for ESD
protection for each pin to VDD. The collector is electrically
connected to the substrate of the die (see Figure 16). The base-
emitter junction of this transistor can be used to monitor the
internal die temperature of the IC.
I
OUT = 0 mA, measure V1 as shown in Figure 16 (note the
polarity).
The second point of the 2-point measurement is obtained when
the AD9665 is operated under load, for example, while driving
a laser. Before taking the measurement, the AD9665 must be
allowed adequate time to reach a thermal equilibrium.
As seen in Figure 16, the AD9665 has a finite parasitic
resistance (RS) between VDD (Pin 17) and the base of the PNP
transistor. This resistance is typically 120 mΩ. Because the goal
of the experiment is to measure ΔVBE of the transistor, the
voltage drop across this resistance must be taken into account to
get an accurate representation of the actual ΔVBE. This voltage
drop varies depending on the output current of the AD9665
operating under load. Therefore, the actual supply current (IDD)
must be measured for each measurement.
Using a 10 V source at the enable pin to forward-bias the base-
emitter junction and a 1 MΩ resistor to limit the current, a
2-point measurement can be used to calculate the junction
temperature of the IC. Because the enable pin (ENABLE) needs
to be high for normal operation, the AD9665 can be operated
normally with the 10 V applied through the 1 MΩ resistor.
For this experiment, V1 and V2 were measured between the
ENABLE pin (Pin 16) and the closest VDD pin (Pin 17).
VDROP = IDD × RS
AD9665
So the resulting ΔVBE can be found as
I
DD
ΔVBE = (V2 + VDROP2) − (V1 + VDROP1
)
V
R
S
DD
5V
–
For increasing temperature, this result should be negative.
V1, V2
+
I
From ΔVBE, the final junction temperature is determined by
BE
1MΩ
ENABLE
ΔVBE
TJ =TA +
10V
GND
−1.9 mV/°C
From the resulting temperature rise in addition to the measured
power dissipation, the thermal resistance from the junction to
ambient can be calculated as
Figure 16. Junction Temperature Measurement Circuit
The most important aspect of measuring junction temperature
on the AD9665 is that only one variable in the system is
changed at a time. In this case, the only variable is the amount
of power being dissipated by the AD9665. Therefore, the
ambient temperature should be held constant. For example, to
measure the junction temperature of the AD9665 while
operating at 60°C ambient, the ambient temperature must be
held constant for both the initial measurement, V1, and the
final measurement, V2. This is true because of the relationship
between temperature and VBE. For the process with which the
AD9665 is fabricated, the change in VBE (ΔVBE) is related to the
die temperature by −1.9 mV/°C (note the negative coefficient).
Therefore, die temperature is directly related to ambient
temperature and the power dissipated.
PD = VDD × IDD − VLOAD × ILOAD
TJ −TA
θJA
=
PD
Rev. E | Page 10 of 16
AD9665
SHUTDOWN SUPPLY CURRENT VARIATION
The AD9665 defaults to TTL input mode when the ENABLE
pin is tied low (ENABLE = 0), regardless of the position of the
INS pin. Because of this, there can be additional supply current
due to the applied voltage on the read, write, or OSCEN enable
pins, the cause of which is an inverter located on the TTL input
ENABLE pins (see Figure 17).
Voltages close to GND or VDD are not sufficient to turn on
both transistors. However, as voltages vary from these extremes,
significant current can flow. Figure 18 shows how the power-
down current varies with voltage applied on the read, write, or
OSCEN enable pins.
Therefore, to ensure the lowest possible shutdown current,
the read, write, and OSCEN voltages should be tied to either
0 V or 5 V.
+V
DD
16
CHIP DISABLED
INPUT
OUTPUT
12
VALID
TTL LOW
VALID
TTL HIGH
8
4
0
GND
Figure 17. Inverter Circuit
NONVALID
TTL REGION
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TTL VOLTAGE ON READ AND WRITE CHANNELS (V)
Figure 18. Read and Write TTL Enable Voltage vs. Supply Current
Rev. E | Page 11 of 16
AD9665
EVALUATION BOARD
SCHEMATIC
OUTSEL
OSCEN
W10
VD
V
R20
W1
DD
R22
DNI
DNI
R15
R16
R17
R18
VDD
6.81kΩ 6.81kΩ 5.76kΩ 5.76kΩ
+
C6
0.1µF
C13
10µF
SHORT, WIDE,
AND CLOSE
W3DISN
VDNEG
W3DIS
VDNEG
W2DISN
VDNEG
W2DIS
VDNEG
W1DISN
VDNEG
W1DIS
VDNEG
32 31 30 29 28 27 26 25
W2
W3
W4
W5
W6
W7
VD
R1
VDPOS
D1
100Ω
R6
DNI
W11
LD1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
W3DISN
INS
VDD
R4
46.4Ω
C7
DNI
R5
3.1Ω
W3DIS
GND
V
DD
+
C9
C14
10µF
VDPOS
VDPOS
LD1
0.1µF
GND
LD1
GND
LD2
LD2
AD9665
R2
100Ω
W2DISN
W2DIS
W1DISN
W1DIS
SHORT, WIDE,
AND CLOSE
D2
V
DD
R7
DNI
C8
0.1µF
LD2
VDPOS
VDPOS
C10
DNI
R9
46.4Ω
R8
3.1Ω
9
10 11 12 13 14 15 16
R3
100Ω
ENBL
VDPOS
VDD
W9
VDNEG VDPOS
VDNEG VDPOS
5V
RDIS
R10
0Ω
R11
4.3kΩ
R12
4.3kΩ
R13
R14
4.3kΩ
R21
DNI
4.3kΩ
VDD
R19
DNI
W8
VD
+
C12
10µF
C18
0.1µF
C17
0.1µF
C11
0.1µF
C1
0.1µF
C2
DNI
C3
DNI
C4
DNI
C5
DNI
VDD
W3SET W2SET W1SET
RSET
Figure 19. AD9665ACPZ-32 Evaluation Board Schematic
Rev. E | Page 12 of 16
AD9665
OPERATION
WxDISN RDIS
, ENABLE, INS,
OUTSEL, and OSCEN, can be driven with pulsed sources or
can be set to a steady state level with jumpers. For steady state
The logic signals, WxDIS,
,
PIN DESCRIPTIONS
Table 5.
Pin No. Mnemonic Description
WxDISN
operation, the logic levels for the WxDIS and
pins are
1
W3DISN
Negative enable for Write Channel 3
(LVDS mode only)
Positive enable for Write Channel 3
(LVDS mode), enable (TTL mode)
set with voltages applied to the VDPOS and VDNEG pins on
the evaluation board. For LVDS mode (INS = 1), VDPOS and
VDNEG should be at a level greater than 50 mV and less than
2.45 V (0.050 V < VDPOS < 2.45 V and 0.05 V < VDNEG < 2.45 V),
with the differential voltage greater than 100 mV and less than
600 mV. For TTL operation (INS = 0), VDPOS should be
greater than 2.5 V and VDNEG should be less than 0.8 V. Under
TTL operation, it may be convenient to put VDPOS at 5 V and
VDNEG at 0 V. The pin labeled 5 V is the logic level for INS
and OUTSEL.
2
W3DIS
3, 4
5
GND
W2DISN
GND
Negative enable for Write Channel 2
(LVDS mode only)
Positive enable for Write Channel 2
(LVDS mode), enable (TTL mode)
Negative enable for Write Channel 1
(LVDS mode only)
Positive enable for Write Channel 1
(LVDS mode), enable (TTL mode)
6
7
8
W2DIS
W1DISN
W1DIS
The VDD pins are connected together in the IC and can be
connected to the same external supply. Although they are all
connected internally, there must be a direct connection to each
of these pins through their vector pins externally, which are also
labeled VDD.
9
RDIS
VDD
Enable for R Channel (TTL only)
10
5 V supply and dc logic level
RDIS
for
5 V supply and dc logic level
RDIS
and ENABLE
11
VDD
A jumper set to the right side of a 3-lead connection applies the
VDPOS voltage to the applicable pin on the IC. A jumper set to
the left side of a 3-lead connection applies the VDNEG voltage.
for
and ENABLE
12
13
14
15
16
17
W3SET
W2SET
W1SET
RSET
ENABLE
VDD
Input for Write Channel 3 (RIN = 200 Ω)
Input for Write Channel 2 (RIN = 200 Ω)
Input for Write Channel 1 (RIN = 200 Ω)
Input for Read Channel (RIN = 200 Ω)
Chip enable—active high
Output stage supply, 5 V
Output 2
GND
Output 1
Evaluation boards are shipped with 100 Ω termination resistors
across the LVDS inputs and without 50 Ω resistors on the other
logic traces. Resistors R5 and R8 can be connected between ground
and the cathodes of Diode 1 and Diode 2, respectively. To monitor
diode current with an oscilloscope, a 3.1 Ω resistor can be placed in
each of these positions. The series 46.4 Ω resistors at R4 and R9
present a 50 Ω impedance to measurement equipment. This results
in the oscilloscope displaying the diode current with a conversion
factor of 1.558 mV/mA. If this capability is not desired, 0 Ω
resistors can be installed in the R5 and R8 positions.
18, 19
20
21, 22
23
LD2
GND
LD1
VDD
Output stage supply, 5 V
24
INS
Logic mode select (0 = TTL, 1 = LVDS)
Amplitude resistor set for Oscillator 2
Amplitude resistor set for Oscillator 1
Frequency resistor set for Oscillator 2
Frequency resistor set for Oscillator 1
Output select (0 = LD2, 1 = LD1)
Oscillator enable—active high
No connection
25
26
27
AADJ2
AADJ1
FADJ2
28
FADJ1
29
30
31
OUTSEL
OSCEN
N/C
32
VDD
5 V supply and dc logic level for OSCEN
N/A
EPAD
The exposed pad should be connected
to ground.
Rev. E | Page 13 of 16
AD9665
OUTLINE DIMENSIONS
0.30
0.23
0.18
0.60 MAX
5.00
BSC SQ
0.60 MAX
25
24
32
1
0.45
BSC
4.75
BSC SQ
0.50
BSC
2.85
2.70 SQ
2.55
*
PIN 1
INDICATOR
EXPOSED
PAD
17
16
8
9
0.50
0.40
0.30
0.20
MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
SEATING
PLANE
0.05
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220 WITH EXCEPTION TO PADDLE ORIENTATION.
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION
SECTION OF THIS DATA SHEET.
Figure 20. 32-Lead Pad-Up, Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−25°C to +85°C
−25°C to +85°C
Package Description
Package Option
CP-32-1
CP-32-1
AD9665ACPZ-REEL
AD9665ACPZ-REEL7
32-Lead, Pad-Up, Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead, Pad-Up, Lead Frame Chip Scale Package [LFCSP_VQ]
1 Z = RoHS Compliant Part.
Rev. E | Page 14 of 16
AD9665
NOTES
Rev. E | Page 15 of 16
AD9665
NOTES
© 2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05269-0-8/10(E)
Rev. E | Page 16 of 16
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