AD96687TQ [ADI]
Ultrafast Comparators; 超高速比较器
| 型号： | AD96687TQ |
| 厂家： | 
ADI |
| 描述： | Ultrafast Comparators |
| 文件： | 总6页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Ultrafast Comparators
AD96685/AD96687
FEATURES
AD 96685 FUNCTIO NAL BLO CK D IAGRAM
Fast: 2.5 ns Propagation Delay
Low Pow er: 118 m W per Com parator
Packages: DIP, TO-100, SOIC, PLCC
Pow er Supplies: +5 V, –5.2 V
Logic Com patibility: ECL
MIL-STD-883 Versions Available
50 ps Delay Dispersion
APPLICATIONS
AD 96687 FUNCTIO NAL BLO CK D IAGRAM
High Speed Triggers
High Speed Line Receivers
Threshold Detectors
Window Com parators
Peak Detectors
GENERAL D ESCRIP TIO N
families. T he outputs provide sufficient drive current to directly
drive transmission lines terminated in 50 Ω to –2 V. A level sen-
sitive latch input is included which permits tracking, track-hold,
or sample-hold modes of operation.
T he AD96685 and AD96687 are ultrafast voltage comparators.
T he AD96685 is a single comparator with 2.5 ns propagation
delay; the AD96687 is an equally fast dual comparator. Both
devices feature 50 ps propagation delay dispersion which is a
particularly important characteristic of high speed comparators.
It is a measure of the difference in propagation delay under dif-
fering overdrive conditions.
T he AD96685 and AD96687 are available in both industrial,
–25°C to +85°C, and military temperature ranges. Industrial
range devices are available in 16-pin DIP, SOIC, and 20-lead
PLCC; additionally, the AD96685 is available in a 10-pin,
T O-100 metal can.
A fast, high precision differential input stage permits consistent
propagation delay with a wide variety of signals in the common-
mode range from –2.5 V to +5 V. Outputs are complementary
digital signals fully compatible with ECL 10 K and 10 KH logic
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD96685/AD96687–SPECIFICATIONS
ABSO LUTE MAXIMUM RATINGS1
EXP LANATIO N O F TEST LEVELS
T est Level
Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . +6.5 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . –6.5 V
Input Voltage Range2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Latch Enable Voltage . . . . . . . . . . . . . . . . . . . . . . . . –VS to 0 V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating T emperature Range3
AD96685/87/BH/BQ/BP/BR . . . . . . . . . . . . –25°C to +85°C
AD96685/87/T Q . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . . . –55°C to +150°C
Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Lead Soldering T emperature (10 sec) . . . . . . . . . . . . . +300°C
I
– 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V
– Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C; 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
ELECTRICAL CHARACTERISTICS (Positive Supply Voltage = +5.0 V; Negative Supply Voltage = –5.2 V, unless otherwise noted)
Industrial Tem p. Range –25؇C to +85؇C
Military Tem p. Range –55؇C to +125؇C
Test AD 96685BH /BQ/BP /BR AD 96687BQ/BP /BR
AD 96685TQ
AD 96687TQ
P aram eter
Tem p Level Min
Typ
Max
Min Typ Max
Min Typ Max
Min Typ Max
Units
INPUT CHARACT ERIST ICS
Input Offset Voltage4
+25°C
Full
Full
+25°C
Full
+25°C
Full
+25°C
+25°C
Full
I
1
2
3
1
2
3
1
2
3
1
2
3
mV
mV
µV/°C
µA
µA
µA
µA
kΩ
pF
V
dB
VI
V
I
VI
I
VI
V
V
VI
VI
Input Offset Drift
Input Bias Current
20
7
20
7
20
7
20
7
10
13
1.0
1.2
10
13
1.0
1.2
10
16
1.0
1.2
10
16
1.0
1.2
Input Offset Current
0.1
0.1
0.1
0.1
Input Resistance
Input Capacitance
Input Voltage Ranges
Common-Mode Rejection Ratio
200
2
200
2
200
2
200
2
–2.5
80
+5.0
–2.5
80
+5.0
–2.5
80
+5.0
–2.5
80
+5.0
Full
90
90
90
90
ENABLE INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Full
Full
Full
Full
VI
VI
VI
VI
–1.1
–1.1
–1.1
–1.1
V
V
µA
µA
–1.5
40
5
–1.5
40
5
–1.5
40
5
–1.5
40
5
DIGIT AL OUT PUT S6
Logic “1” Voltage
Logic “0” Voltage
Full
Full
VI
VI
–1.1
–1.1
–1.1
–1.1
V
V
–1.5
–1.5
–1.5
–1.5
SWIT CHING PERFORMANCES
Propagation Delays7
Input to Output HIGH
Input to Output LOW
Latch Enable to Output HIGH
Latch Enable to Output LOW
Dispersions8
+25°C IV
+25°C IV
+25°C IV
+25°C IV
2.5
2.5
2.5
2.5
50
3.5
3.5
3.5
3.5
2.5
2.5
2.5
2.5
50
3.5
3.5
3.5
3.5
2.5
2.5
2.5
2.5
50
3.5
3.5
3.5
3.5
2.5
2.5
2.5
2.5
50
3.5
3.5
3.5
3.5
ns
ns
ns
ns
ps
+25°C
V
Latch Enable
Minimum Pulse Width
Minimum Setup T ime
Minimum Hold T ime
+25°C IV
+25°C IV
+25°C IV
2.0
0.5
0.5
3.0
1.0
1.0
2.0
0.5
0.5
3.0
1.0
1.0
2.0
0.5
0.5
3.0
1.0
1.0
2.0
0.5
0.5
3.0
1.0
1.0
ns
ns
ns
POWER SUPPLY9
Positive Supply Current (+5.0 V)
Negative Supply Current (–5.2 V) Full
Power Supply Rejection Ratio10
Full
VI
VI
VI
8
15
70
9
18
15
31
70
18
36
8
15
70
9
18
15
31
70
18
36
mA
mA
dB
Full
60
60
60
60
4RS = 100 Ω.
NOT ES
1Absolute maximum ratings are limiting values, may be applied individually, and beyond which serviceability
of the circuit may be impaired. Functional operation under any of these conditions is not necessarily implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2Under no circumstances should the input voltages exceed the supply voltages .
3T ypical thermal impedances . . .
5Input Voltage Range can be extended to –3.3 V if –VS = –6.0 V.
6Outputs terminated through 50 Ω to –2.0 V.
7Propagation delays measured with 100 mV pulse (10 mV overdrive), to
50% transition point of the output.
8Change in propagation Delay from 100 mV to 1 V input overdrive.
9Supply voltages should remain stable within ±5% for normal operation.
10Measured at ±5% of +VS and –VS.
AD96685 Metal Can
AD96685 Ceramic
AD96685 SOIC
AD96685 PLCC
AD96687 Ceramic
AD96687 SOIC
θJA = 172°C/W; θJC = 52°C/W
JA = 115°C/W; θJC = 57°C/W
θJA = 170°C/W; θJC = 60°C/W
JA = 88°C/W; θJC = 45°C/W
θJA = 115°C/W; θJC = 57°C/W
JA = 92°C/W; θJC = 47°C/W
θJA = 81°C/W; θJC = 45°C/W
θ
Specifications subject to change without notice.
θ
θ
AD96687 PLCC
–2–
REV. C
AD96685/AD96687
FUNCTIO NAL D ESCRIP TIO N
P in Nam e
D escription
Positive supply terminal, nominally +5.0 V.
+VS
NONINVERT ING INPUT
Noninverting analog input of the differential input stage. T he NONINVERT ING INPUT must be
driven in conjunction with the INVERT ING INPUT .
INVERT ING INPUT
LAT CH ENABLE
Inverting analog input of the differential input stage. T he INVERT ING INPUT must be driven in
conjunction with the NONINVERT ING INPUT .
In the “compare” mode (logic HIGH), the output will track changes at the input of the compara-
tor. In the “latch” mode (logic LOW), the output will reflect the input state just prior to the
comparator being placed in the “latch” mode. LATCH ENABLE must be driven in conjunction
with LAT CH ENABLE for the AD96687.
LATCH ENABLE
In the “compare” mode (logic LOW), the output will track changes at the input of the comparator.
In the “latch” mode (logic HIGH), the output will reflect the input state just prior to the compara-
tor being placed in the “latch” mode. LAT CH ENABLE must be driven in conjunction with
LATCH ENABLE for the AD96687.
–VS
Q
Negative supply terminal, nominally –5.2 V.
One of two complementary outputs. Q will be at logic HIGH if the analog voltage at the
NONINVERT ING INPUT is greater than the analog voltage at the INVERT ING INPUT (pro-
vided the comparator is in the “compare” mode). See LAT CH ENABLE and LAT CH ENABLE
(AD96687 only) for additional information.
Q
One of two complementary outputs. Q will be at logic LOW if the analog voltage at the
NONINVERT ING INPUT is greater than the analog voltage at the INVERT ING INPUT
(provided the comparator is in the “compare” mode). See LAT CH ENABLE and LAT CH EN-
ABLE (AD96687 only) for additional information.
GROUND 1
GROUND 2
One of two grounds, but primarily associated with the digital ground. Both grounds should be con-
nected together near the comparator.
One of two grounds, but primarily associated with the analog ground. Both grounds should be con-
nected together near the comparator.
P IN D ESIGNATIO NS
AD 96685BQ /TQ /BR
AD 96687BQ /TQ /BR
NC = NO CONNECT
AD 96685BP
AD 96685BH
AD 96687BP
NC = NO CONNECT
NC = NO CONNECT
REV. C
–3–
AD96685/AD96687
SYSTEM TIMING D IAGRAM
tS
– Minimum Setup T ime
tH
– Minimum Hold T ime
– Input to Output Delay
tPD
tPD(E) – LAT CH ENABLE to Output Delay
tPW(E) – Minimum LAT CH ENABLE Pulse Width
VOS
VOD
– Input Offset Voltage
– Overdrive Voltage
D IE LAYO UT AND MECH ANICAL INFO RMATIO N
Die Dimensions (AD96685) . . . . . . . . 44 ϫ 50 ϫ 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ϫ 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic
Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding
or 1 mil, Gold, Gold Ball Bonding
Die Dimensions (AD96687) . . . . . . . . 77 ϫ 60 ϫ 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ϫ 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic
Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding
or 1 mil, Gold, Gold Ball Bonding
REV. C
–4–
AD96685/AD96687
O RD ERING GUID E
Tem perature
P ackage
Model
Type
Range
D escription
O ptions
AD96685BH
AD96685BP
AD96685BQ
AD96685BR
AD96685BP-REEL
AD96685T Q
AD96687BP
AD96687BQ
AD96687BR
Single
Single
Single
Single
Single
Single
Dual
Dual
Dual
Dual
Dual
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
10-Pin Can, Industrial
20-Pin PLCC, Industrial
16-Pin DIP, Industrial
H-10A
P-20A
Q-16
R-16A
P-20A
Q-16
P-20A
Q-16
R-16A
R-16A
Q-16
16-Pin SOIC, Industrial
20-Pin PLCC, Industrial
16-Pin DIP, Extended T emperature
20-Pin PLCC, Industrial
16-Pin DIP, Industrial
16-Pin SOIC, Industrial
16-Pin SOIC, Industrial
16-Pin DIP, Extended T emperature
AD96687BR-REEL
AD96687T Q
AP P LICATIO NS INFO RMATIO N
T he AD96685/87 have been specifically designed to reduce
propagation delay dispersion over an input overdrive range of
100 mV to 1 V. Propagation delay dispersion is the change in
propagation delay which results from a change in the degree of
overdrive (how far the switching point is exceeded by the input).
T he overall result is a higher degree of timing accuracy since the
AD96685/87 is far less sensitive to input variations than most
comparator designs.
T he AD96685/87 comparators are very high speed devices.
Consequently, high speed design techniques must be employed
to achieve the best performance. T he most critical aspect of any
AD96685/87 design is the use of a low impedance ground
plane.
Another area of particular importance is power supply
decoupling. Normally, both power supply connections should
be separately decoupled to ground through 0.1 µF ceramic and
0.001 µF mica capacitors. T he basic design of comparator cir-
cuits makes the negative supply somewhat more sensitive to
variations. As a result more attention should be placed on insur-
ing a “clean” negative supply.
Typical Applications
H IGH SP EED SAMP LING CIRCUIT
T he LAT CH ENABLE input is active LOW (latched). If the
latching function is not used, the LAT CH ENABLE input
should be grounded (ground is an ECL logic HIGH). T he
LATCH ENABLE input of the AD96687 should be tied to
–2.0 V or left “floating,” to disable the latching function. An
alternate use of the LAT CH ENABLE input is as a hysteresis
control input. By varying the voltage at the LAT CH ENABLE
input for the AD96685 and the differential voltage between both
latch inputs for the AD96687, small variations in the hysteresis
can be achieved.
Occasionally, one of the two comparator stages within the
AD96687 will not be used. T he inputs of the unused compara-
tor should not be allowed to “float.” T he high internal gain may
cause the output to oscillate (possibly affecting the other com-
parator which is being used) unless the output is forced into a
fixed state. T his is easily accomplished by insuring that the two
inputs are at least one diode drop apart, while also grounding
the LAT CH ENABLE input.
H IGH SP EED WIND O W CO MP ARATO R
T he best performance will be achieved with the use of proper
ECL terminations. T he open-emitter outputs of the
AD96685/87 are designed to be terminated through 50 Ω resis-
tors to –2.0 V, or any other equivalent ECL termination. If high
speed ECL signals must be routed more than a few centimeters,
MicroStrip or StripLine techniques may be required to insure
proper transition times and prevent output ringing.
REV. C
–5–
AD96685/AD96687
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-P in Cer am ic D IP
16-P in SO IC
20-P in P LCC
20-P in LCC
10-P in TO -100 Metal Can
REV. C
–6–
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