AD9680_技术文档

14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS

JESD204B, Dual Analog-to-Digital Converter

Data Sheet

AD9680

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD

SPIVDD

JESD204B (Subclass 1) coded serial digital outputs

1.65 W total power per channel at 1 GSPS (default settings)

SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz

SNR at 1 GSPS = 65.3 dBFS at 340 MHz (A_IN= −1.0 dBFS),

60.5 dBFS at 1 GHz (A_IN= −1.0 dBFS)

ENOB = 10.8 bits at 10 MHz

(1.25V) (2.5V) (3.3V)

(1.25V)

(1.25V) (1.25V) (1.8V TO 3.3V)

BUFFER

VIN+A

VIN–A

ADC

14

CORE

DDC

FD_A

SERDOUT0±

4

SIGNAL

MONITOR

SERDOUT1±

SERDOUT2±

SERDOUT3±

DNL = 0.5 LSB

FD_B

14

DDC

INL = 2.5 LSB

VIN+B

VIN–B

ADC

CORE

Noise density = −154 dBFS/Hz at 1 GSPS

1.25 V, 2.5 V, and 3.3 V dc supply operation

No missing codes

BUFFER

CONTROL

REGISTERS

V_1P0

FAST

DETECT

Internal ADC voltage reference

Flexible input range: 1.46 V p-p to 1.94 V p-p

AD9680-1250: 1.58 V p-p nominal

SIGNAL

MONITOR

SYNCINB±

SYSREF±

JESD204B

SUBCLASS 1

CONTROL

CLOCK

GENERATION

AD9680-1000 and AD9680-820: 1.70 V p-p nominal

AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)

Programmable termination impedance

400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

2 GHz usable analog input full power bandwidth

95 dB channel isolation/crosstalk

CLK+

CLK–

÷2

÷4

÷8

SPI CONTROL

PDWN/

STBY

AD9680

AGND DRGND DGND SDIO SCLK CSB

Figure 1.

Amplitude detect bits for efficient AGC implementation

2 integrated wideband digital processors per channel

12-bit NCO, up to 4 half-band filters

Differential clock input

Integer clock divide by 1, 2, 4, or 8

Flexible JESD204B lane configurations

Small signal dither

PRODUCT HIGHLIGHTS

1. Wide full power bandwidth supports IF sampling of signals

up to 2 GHz.

2. Buffered inputs with programmable input termination eases

filter design and implementation.

3. Four integrated wideband decimation filters and numerically

controlled oscillator (NCO) blocks supporting multiband

receivers.

APPLICATIONS

4. Flexible serial port interface (SPI) controls various product

features and functions to meet specific system requirements.

5. Programmable fast overrange detection.

6. 9 mm × 9 mm, 64-lead LFCSP.

Communications

Diversity multiband, multimode digital receivers

3G/4G, TD-SCDMA, W-CDMA, GSM, LTE

General-purpose software radios

Ultrawideband satellite receivers

Instrumentation

Radars

Signals intelligence (SIGINT)

DOCSIS 3.0 CMTS upstream receive paths

HFC digital reverse path receivers

Rev. C

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AD9680* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

REFERENCE MATERIALS

Informational

• JESD204 Serial Interface

Press

EVALUATION KITS

• AD-FMCDAQ2-EBZ Evaluation Board

• Analog Devices Introduces High-Performance RF ICs for

Multi-band Base Stations and Microwave Point-to-Point

Radios

• AD9680/AD9234/AD9690 Evaluation Board

• ADA4961 & AD9680 Analog Signal Chain Evaluation and

AD9528 Converter Synchronization

• Analog Devices Unveils New Class of Data Converters That

Set 14-bit, GSPS Performance Standard

Technical Articles

DOCUMENTATION

• Clocking Wideband GSPS JESD204B ADCs

• Digital Signal Process in IF RF Data Converters

Application Notes

• AN-835: Understanding High Speed ADC Testing and

Evaluation

• MS-2660: Understanding Spurious-Free Dynamic Range in

Wideband GSPS ADCs

Data Sheet

• MS-2672: JESD204B Subclasses - Part 1: An Introduction to

JESD204B Subclasses and Deterministic Latency

• AD9680: 14-Bit, 1 GSPS/820 MSPS/500 MSPS JESD204B,

Dual Analog-to-Digital Converter Data Sheet

• MS-2677: JESD204B Subclasses - Part 2: Subclass 1 vs.

Subclass 2 System Considerations

TOOLS AND SIMULATIONS

• AD9680 Delphi Models

• Visual Analog

• MS-2708: GSPS Data Converters to the Rescue for

Electronics Surveillance and Warfare Systems

• MS-2714: Understanding Layers in the JESD204B

• AD9680 / AD6674 IBIS Model

• AD9680 AMI Model

Specificaton: A High Speed ADC Perspective, Part 1

• MS-2735: Maximizing the Dynamic Range of Software-

Defined Radio

• AD9680 S-Parameters

• Powering GSPS or RF Sampling ADCs: Switcher vs LDO

DESIGN RESOURCES

• AD9680 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

DISCUSSIONS

View all AD9680 EngineerZone Discussions.

SAMPLE AND BUY

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TECHNICAL SUPPORT

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number.

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AD9680

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Frequency Translation ................................................................... 54

General Description................................................................... 54

DDC NCO Plus Mixer Loss and SFDR................................... 55

Numerically Controlled Oscillator .......................................... 55

FIR Filters ........................................................................................ 57

General Description................................................................... 57

Half-Band Filters ........................................................................ 58

DDC Gain Stage ......................................................................... 60

DDC Complex to Real Conversion ......................................... 60

DDC Example Configurations ................................................. 61

Digital Outputs ............................................................................... 64

Introduction to the JESD204B Interface ................................. 64

JESD204B Overview .................................................................. 64

Functional Overview ................................................................. 65

JESD204B Link Establishment ................................................. 65

Physical Layer (Driver) Outputs .............................................. 67

JESD204B Tx Converter Mapping ........................................... 69

Configuring the JESD204B Link.............................................. 71

Multichip Synchronization............................................................ 74

SYSREF Setup/Hold Window Monitor................................. 76

Test Modes....................................................................................... 78

ADC Test Modes ........................................................................ 78

JESD204B Block Test Modes .................................................... 79

Serial Port Interface........................................................................ 81

Configuration Using the SPI..................................................... 81

Hardware Interface..................................................................... 81

SPI Accessible Features.............................................................. 81

Memory Map .................................................................................. 82

Reading the Memory Map Register Table............................... 82

Memory Map Register Table..................................................... 83

Applications Information .............................................................. 96

Power Supply Recommendations............................................. 96

Exposed Pad Thermal Heat Slug Recommendations............ 96

AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60).............. 96

Outline Dimensions....................................................................... 97

Ordering Guide .......................................................................... 97

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 3

General Description......................................................................... 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

AC Specifications.......................................................................... 6

Digital Specifications ................................................................... 8

Switching Specifications .............................................................. 9

Timing Specifications ................................................................ 10

Absolute Maximum Ratings.......................................................... 12

Thermal Characteristics ............................................................ 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Typical Performance Characteristics ........................................... 15

AD9680-1250.............................................................................. 15

AD9680-1000.............................................................................. 19

AD9680-820................................................................................ 24

AD9680-500................................................................................ 29

Equivalent Circuits ......................................................................... 33

Theory of Operation ...................................................................... 35

ADC Architecture ...................................................................... 35

Analog Input Considerations.................................................... 35

Voltage Reference ....................................................................... 41

Clock Input Considerations ...................................................... 42

ADC Overrange and Fast Detect.................................................. 44

ADC Overrange.......................................................................... 44

Fast Threshold Detection (FD_A and FD_B) ........................ 44

Signal Monitor ................................................................................ 45

SPORT Over JESD204B............................................................. 46

Digital Downconverter (DDC)..................................................... 48

DDC I/Q Input Selection .......................................................... 48

DDC I/Q Output Selection ....................................................... 48

DDC General Description ........................................................ 48

Rev. C | Page 2 of 97

Data Sheet

AD9680

REVISION HISTORY

Changes to Specifications Section and Table 1 .............................5

Changes to AC Specifications Section and Table 2.......................6

Changes to Digital Specifications Section .....................................8

Changes to Switching Specifications Section and Table 4 ...........9

Changes to Table 6, Thermal Characteristics Section, and

Table 7...............................................................................................11

Change to Digital Inputs Description, Table 8............................13

Added AD9680-1000 Section, Figure 10, and Figure 11;

Renumbered Sequentially ..............................................................14

Changes to Figure 6 to Figure 9 ....................................................14

Added Figure 12 to Figure 14........................................................15

Changes to Figure 15 to Figure 17 ................................................15

Changes to Figure 18 to Figure 21 ................................................16

Changes to Figure 25 and Figure 29 .............................................17

Changes to Figure 30 ......................................................................18

Deleted Figure 35, Figure 36, and Figure 38................................19

Added AD9680-500 Section and Figure 31 to Figure 54 .............19

Changes to Analog Input Considerations Section and

11/15—Rev. B to Rev. C

Added AD9680-1250......................................................... Universal

Changes to Features Section ............................................................1

Change to General Description Section.........................................4

Changes to Table 1 ............................................................................5

Changes to Table 2 ............................................................................6

Changes to Table 4 ............................................................................9

Changes to Table 5 ..........................................................................10

Changes to Figure 4.........................................................................11

Changes to Pin 14 Description, Table 8 .......................................14

Added AD9680-1250 Section and Figure 6 to Figure 29;

Renumbered Sequentially ..............................................................15

Changes to Figure 113 ....................................................................34

Changes to Analog Input Considerations Section......................35

Changes to Table 9 ..........................................................................36

Changes to Input Buffer Control Registers (0x018, 0x019,

0x01A, 0x935, 0x934, 0x11A) Section..........................................37

Added Figure 118 to Figure 120....................................................37

Changes to Table 10 ........................................................................40

Changes to Table 17 ........................................................................57

Changes to ADC Test Modes Section...........................................78

Changes to Table 36 ........................................................................83

Changes to Ordering Guide...........................................................97

Differential Input Configurations Section...................................25

Added Input Buffer Control Registers (0x018, 0x019, 0x01A,

0x935, 0x934, 0x11A) Section, Figure 66, Figure 68, and Table 9;

Renumbered Sequentially ..............................................................26

Changes to Analog Input Buffer Controls and SFDR

Optimization Section and Figure 67 ............................................26

Added Figure 69 to Figure 72........................................................27

Added Figure 73 to Figure 75........................................................28

Changes to Table 10 ........................................................................28

Added Input Clock Divider ½ Period Delay Adjust Section and

Clock Fine Delay Adjust Section...................................................30

Changes to Figure 83 and Temperature Diode Section .............31

Added Signal Monitor Section and Figure 86 to Figure 89.......33

Changes to Table 11 ........................................................................39

Changes to Table 12 to Table 14....................................................40

Changes to Table 16 ........................................................................41

Deleted Figure 65 and Figure 66 ...................................................45

Changes to Table 17 ........................................................................45

Changes to Table 19 to Table 20....................................................46

Changes to Table 22 ........................................................................47

Changes to Table 23 ........................................................................49

Changes to JESD204B Link Establishment Section ...................53

Added Figure 105 to Figure 110....................................................56

Changes to Example 1: Full Bandwidth Mode Section..............60

Added Multichip Synchronization Section, Figure 115 to

3/15—Rev. A to Rev. B

Added AD9680-820 ........................................................... Universal

Changes to Features Section ............................................................1

Changes to Table 1 ............................................................................5

Changes to Table 2 ............................................................................6

Changes to Table 3 ............................................................................8

Changes to Table 4 ............................................................................9

Added Figure 14; Renumbered Sequentially...............................15

Added AD9680-820 Section and Figure 31 Through Figure 36 ...19

Added Figure 37 Through Figure 42 ............................................20

Added Figure 43 Through Figure 48 ............................................21

Added Figure 49 Through Figure 54 ............................................22

Added Figure 55 ..............................................................................23

Changes to Figure 69 and Figure 70 .............................................26

Changes to Input Buffer Control Registers (0x018, 0x019, 0x01A,

0x935, 0x934, 0x11A) Section, Table 9, and Figure 93....................31

Added Figure 99 Through Figure 100..........................................33

Changes to Table 10 ........................................................................34

Changes to Clock Jitter Considerations Section .........................37

Added Figure 112 ............................................................................37

Changes to Digital Downconverter (DDC) Section...................42

Changes to Table 17 ........................................................................51

Changes to Table 36 ........................................................................77

Changes to Ordering Guide...........................................................91

Figure 117, and Table 28.................................................................62

Added Test Modes Section and Table 29 to Table 33 .................66

Changes to Reading the Memory Map Register Table Section.......70

Changes to Table 36 ........................................................................71

Changes to Power Supply Recommendations Section,

Figure 118, and Exposed Pad Thermal Heat Slug

Recommendations Section ............................................................83

12/14—Rev. 0 to Rev. A

Changes to Ordering Guide...........................................................84

Added AD9680-500 ........................................................... Universal

Changes to Features Section and Figure 1 .....................................1

Changes to General Description Section.......................................4

5/14—Revision 0: Initial Version

Rev. C | Page 3 of 97

AD9680

Data Sheet

GENERAL DESCRIPTION

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/

500 MSPS analog-to-digital converter (ADC). The device has

an on-chip buffer and sample-and-hold circuit designed for low

power, small size, and ease of use. This device is designed for

sampling wide bandwidth analog signals of up to 2 GHz. The

AD9680 is optimized for wide input bandwidth, high sampling

rate, excellent linearity, and low power in a small package.

function in the communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect output bits of the ADC. If the input

signal level exceeds the programmable threshold, the fast detect

indicator goes high. Because this threshold indicator has low

latency, the user can quickly turn down the system gain to avoid

an overrange condition at the ADC input.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations.

Users can configure the Subclass 1 JESD204B-based high speed

serialized output in a variety of one-, two-, or four-lane

configurations, depending on the DDC configuration and the

acceptable lane rate of the receiving logic device. Multiple device

synchronization is supported through the SYSREF and

SYNCINB input pins.

The analog input and clock signals are differential inputs. Each

ADC data output is internally connected to two digital down-

converters (DDCs). Each DDC consists of up to five cascaded

signal processing stages: a 12-bit frequency translator (NCO),

and four half-band decimation filters. The DDCs are bypassed

by default.

The AD9680 has flexible power-down options that allow

significant power savings when desired. All of these features can

be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.

The AD9680 is available in a Pb-free, 64-lead LFCSP and is

specified over the −40°C to +85°C industrial temperature range.

This product is protected by a U.S. patent.

In addition to the DDC blocks, the AD9680 has several

functions that simplify the automatic gain control (AGC)

Rev. C | Page 4 of 97

Data Sheet

AD9680

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified

maximum sampling rate for each speed grade, A_IN= −1.0 dBFS, clock divider = 2, default SPI settings, T_A= 25°C, unless otherwise noted.

Table 1.

AD9680-500

AD9680-820

AD9680-1000

AD9680-1250

Parameter

Temp Min Typ Max Min Typ

Max Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

ACCURACY

Full

14

Bits

No Missing Codes

Offset Error

Offset Matching

Gain Error

Gain Matching

Differential Nonlinearity

(DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Full

Guaranteed

0

−0.3

0

1

+0.3 −0.3

0.3

+6

5.1

0

1

+0.3 −0.31

0.23

+6

5.5

0

+0.31 −0.31

0.23

+0.31 % FSR

0

1

0.3

+6

4.5

% FSR

LSB

−6

0

1

+6

4.5

−6

−0.6

−4.5

0.5 +0.7 −0.7

0.5 +0.8 −0.7

0.5

2.5

+0.8

−0.8

−6

0.5 +0.8

Full

2.5 +5.0 −3.3

2.5 +4.3 −5.7

+6.9

3

+6

LSB

Full

−3

25

−10

54

−12

13.8

−15

92

ppm/°C

Gain Error

INTERNAL VOLTAGE

REFERENCE

Voltage

Full

1.0

V

INPUT-REFERRED NOISE

V_REF= 1.0 V

25°C

2.06

2.46

2.63

3.45

LSB rms

ANALOG INPUTS

Differential Input Voltage

Range (Programmable)

Common-Mode Voltage

(V_CM)

Differential Input

Capacitance¹

Analog Input Full Power

Bandwidth

Full

1.46 2.06 2.06 1.46 1.70 1.94 1.46

1.70

2.05

1.5

2

1.94

1.46

1.58

2.05

1.5

2

1.94

V p-p

V

25°C

2.05

1.5

2

2.05

1.5

2

pF

GHz

POWER SUPPLY

AVDD1

AVDD2

AVDD3

AVDD1_SR

DVDD

DRVDD

SPIVDD

I_AVDD1

Full

25°C

Full

1.22 1.25 1.28 1.22 1.25 1.28 1.22

2.44 2.50 2.56 2.44 2.50 2.56 2.44

1.25

2.50

3.3

1.25

1.8

685

595

125

16

208

200

N/A³

5

1.28

2.56

3.4

1.28

3.4

720

680

142

18

269

225

1.22

2.44

3.2

1.22

1.7

1.25

2.50

3.3

1.25

1.8

785

675

125

17

250

220

N/A³

5

1.28

2.56

3.4

1.28

3.4

880

780

142

20

325

300

V

mA

3.2

3.3

3.4

3.2

3.3

3.4

3.2

1.22 1.25 1.28 1.22 1.25 1.28 1.22

1.7

1.8

3.4

1.7

1.8

3.4

1.7

435 467

395 463

605

490

125

15

660

545

140

18

I_AVDD2

I_AVDD3

87

15

101

22

I_{AVDD1_SR}

2

I_DVDD

145 152

190 237

140

205

200

N/A³

5

246

240

1

I_DRVDD

I_DRVDD(L = 2 Mode)

I_SPIVDD

5

6

Rev. C | Page 5 of 97

AD9680

Data Sheet

AD9680-500

Temp Min Typ Max Min Typ

AD9680-820

Max Min

AD9680-1000

AD9680-1250

Parameter

Typ

Max

Min

Typ

Max

Unit

POWER CONSUMPTION

Total Power Dissipation

(Including Output

Drivers)²

Total Power Dissipation

(L = 2 Mode)

Full

2.2

2.1

2.9

3.3

3.7

W

25°C

N/A³

W

Power-Down Dissipation

Standby⁴

Full

700

1.2

820

1.3

835

1.4

1030

1.66

mW

W

¹All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used.

²Default mode. No DDCs used. L = 4, M = 2, F = 1.

³N/A means not applicable. At the maximum sample rate, it is not applicable to use L = 2 mode on the JESD204B output interface because this exceeds the maximum

lane rate of 12.5 Gbps. L = 2 mode is supported when the equation ((M × N΄ × (10/8) × f_OUT)/L) results in a line rate that is ≤12.5 Gbps. f_OUTis the output sample rate and

is denoted by f_S/DCM, where DCM is the decimation ratio.

⁴Can be controlled by the SPI.

AC SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified

maximum sampling rate for each speed grade, A_IN= −1.0 dBFS, clock divider = 2, default SPI settings, T_A= 25°C, unless otherwise noted.

Table 2.

AD9680-500

Temp Min Typ Max Min Typ

AD9680-820

AD9680-1000

AD9680-1250

Max Unit

Parameter¹

Max Min Typ

ANALOG INPUT FULL SCALE Full

2.06

1.7

1.58

V p-p

NOISE DENSITY²

Full

−153

−154

−151.5

dBFS/Hz

SIGNAL-TO-NOISE RATIO

(SNR)³

f_IN= 10 MHz

25°C

Full

69.2

67.8 69.0

68.6

67.2

65.6 67.0

66.5

67.2

65.1 66.6

65.3

63.6

61.5 63.2

dBFS

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

25°C

62.8

62.2

61.1

59.2

55.5

68.0

64.4

63.8

60.5

65.1

64.0

63.4

59.7

64.0

61.5

60.5

57.0

SNR AND DISTORTION RATIO

(SINAD)³

f_IN= 10 MHz

25°C

Full

69.0

67.6 68.8

68.4

67.1

65.2 66.8

66.3

67.1

65.0 66.4

65.2

63.5

61.4 62.8

62.6

dBFS

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

25°C

67.9

64.2

63.6

60.3

64.7

63.5

62.7

58.7

63.8

62.1

61.1

56.0

61.8

60.8

58.2

51.5

EFFECTIVE NUMBER OF BITS

(ENOB)

f_IN= 10 MHz

25°C

Full

11.2

10.9 11.1

11.1

10.9

10.5 10.8

10.7

10.8

10.5 10.7

10.5

10.3

Bits

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

9.9

10.1

10.0

9.8

9.4

8.3

25°C

11.0

10.4

10.3

9.7

10.5

10.3

10.1

9.5

10.3

10.0

9.8

9.0

Rev. C | Page 6 of 97

Data Sheet

AD9680

AD9680-500

Temp Min Typ Max Min Typ

AD9680-820

AD9680-1000

AD9680-1250

Parameter¹

Max Min Typ

Max Unit

SPURIOUS-FREE DYNAMIC

RANGE (SFDR)³

f_IN= 10 MHz

25°C

Full

83

88

83

81

80

75

70

91

83

81

78

74

70

88

85

82

80

68

84

77

78

76

77

71

61

dBFS

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

80

75

74

25°C

WORST HARMONIC,

SECOND OR THIRD³

f_IN= 10 MHz

25°C

Full

−83

−88

−83

−81

−80

−75

−70

−91

−83

−81

−78

−74

−70

−88

−85

−82

−80

−68

−84

dBFS

−74 dBFS

dBFS

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

−80

−75

−77

−78

−76

−77

−71

−61

25°C

dBFS

WORST OTHER, EXCLUDING

SECOND OR THIRD

HARMONIC³

f_IN= 10 MHz

25°C

Full

−95

−93

−88

−89

−84

−97

−93

−91

−90

−83

−84

−74

−95

−94

−88

−86

−81

−82

−75

−87

−79

−81

−79

−77

−69

dBFS

−74 dBFS

dBFS

f_IN= 170 MHz

f_IN= 340 MHz

f_IN= 450 MHz

f_IN= 765 MHz

f_IN= 985 MHz

f_IN= 1950 MHz

−82

−80

−81

25°C

dBFS

TWO-TONE

INTERMODULATION

DISTORTION (IMD),

A

_IN1AND A_IN2= −7 dBFS

f_IN1= 185 MHz,

_IN2= 188 MHz

f_IN1= 338 MHz,

f_IN2= 341 MHz

CROSSTALK⁵

FULL POWER BANDWIDTH⁶25°C

25°C

−88

−90

−87

−88

−82

dBFS

f

−78⁴

95

2

95

2

95

2

95

2

dB

GHz

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

²Noise density is measured at a low analog input frequency (30 MHz).

³See Table 10 for the recommended settings for full-scale voltage and buffer current settings.

⁴Measurement taken with 449 MHz and 452 MHz inputs for two-tone.

⁵Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel.

⁶Measured with the circuit shown in Figure 115.

Rev. C | Page 7 of 97

AD9680

Data Sheet

DIGITAL SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified

maximum sampling rate for each speed grade, A_IN= −1.0 dBFS, clock divider = 2, default SPI settings, T_A= 25°C, unless otherwise noted.

Table 3.

Parameter

Temperature Min

Typ

Max

1800

2.5

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

LVDS/LVPECL

Full

600

1200

0.85

35

mV p-p

V

kΩ

pF

SYSREF INPUTS (SYSREF+, SYSREF−)

Logic Compliance

Full

LVDS/LVPECL

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance (Differential)

LOGIC INPUTS (SDI, SCLK, CSB, PDWN/STBY)

Logic Compliance

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

400

0.6

1200

0.85

35

1800

2.0

mV p-p

V

kΩ

pF

2.5

Full

CMOS

0.8 × SPIVDD

0

V

0.5

V

30

kΩ

LOGIC OUTPUT (SDIO)

Logic Compliance

Full

CMOS

Logic 1 Voltage (I_OH= 800 µA)

Logic 0 Voltage (I_OL= 50 µA)

SYNCIN INPUT (SYNCINB+/SYNCINB−)

Logic Compliance

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

0.8 × SPIVDD

0

V

0.5

Full

LVDS/LVPECL/CMOS

400

0.6

1200

0.85

35

1800

2.0

mV p-p

V

kΩ

pF

2.5

0.5

770

LOGIC OUTPUTS (FD_A, FD_B)

Logic Compliance

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Full

CMOS

0.8 × SPIVDD

0

V

kΩ

30

DIGITAL OUTPUTS (SERDOUTx , x = 0 TO 3)

Logic Compliance

Differential Output Voltage

Full

CML

360

mV p-p

Output Common-Mode Voltage (V_CM

AC-Coupled

)

25°C

Full

0

1.8

+100

V

Short-Circuit Current (I_DSHORT

Differential Return Loss (RL_DIFF

Common-Mode Return Loss (RL_CM

Differential Termination Impedance

)

−100

8

6

mA

dB

Ω

1

)

1

)

80

100

120

¹Differential and common-mode return loss are measured from 100 MHz to 0.75 × baud rate.

Rev. C | Page 8 of 97

Data Sheet

AD9680

SWITCHING SPECIFICATIONS

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified

maximum sampling rate for each speed grade, A_IN= −1.0 dBFS, default SPI settings, T_A= 25°C, unless otherwise noted.

Table 4.

AD9680-500

Temp Min Typ Max Min

AD9680-820

AD9680-1000

AD9680-1250

Typ Max Unit

Parameter

CLOCK

Typ

Max Min Typ Max Min

Clock Rate (at

Full

0.3

4

0.3

4

0.3

4

0.3

4

GHz

CLK+/CLK− Pins)

Maximum Sample Rate¹

Minimum Sample Rate²

Clock Pulse Width High

Clock Pulse Width Low

OUTPUT PARAMETERS

Unit Interval (UI)³

Full

500

300

1000

820

300

609.7

1000

300

500

1250

300

400

MSPS

ps

Full

25°C

80

24

200

32

80

24

121.95

32

80

24

100

32

80

24

80

32

ps

Rise Time (t_R) (20% to

80% into 100 Ω Load)

Fall Time (t_F) (20% to 80% 25°C

into 100 Ω Load)

24

32

24

32

24

32

24

32

ps

PLL Lock Time

25°C

2

5

2

ms

Data Rate per Channel

3.125

12.5 3.125 8.2

12.5 3.125 10

12.5 3.1215 12.5 12.5 Gbps

(NRZ)⁴

LATENCY⁵

Pipeline Latency

Full

55

1

55

1

Clock

cycles

Clock

cycles

Fast Detect Latency

28

4

28

4

Wake-Up Time⁶

Standby

Power-Down

APERTURE

25°C

1

ms

4

Aperture Delay (t_A)

Aperture Uncertainty

(Jitter, t_J)

Full

530

55

530

55

530

55

530

55

ps

f_Srms

Out-of-Range Recovery

Time

Full

1

Clock

cycles

¹The maximum sample rate is the clock rate after the divider.

²The minimum sample rate operates at 300 MSPS with L = 2 or L = 1.

³Baud rate = 1/UI. A subset of this range can be supported.

⁴Default L = 4. This number can be changed based on the sample rate and decimation ratio.

⁵No DDCs used. L = 4, M = 2, F = 1.

⁶Wake-up time is defined as the time required to return to normal operation from power-down mode.

Rev. C | Page 9 of 97

AD9680

Data Sheet

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLK+ to SYSREF+ TIMING REQUIREMENTS

See Figure 3

t_{SU_SR}

t_{H_SR}

Device clock to SYSREF+ setup time

Device clock to SYSREF+ hold time

See Figure 4

117

−96

ps

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_ACCESS

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

Minimum period that SCLK must be in a logic high state

Minimum period that SCLK must be in a logic low state

2

40

2

ns

10

Maximum time delay between falling edge of SCLK and output

data valid for a read operation

6

10

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an

input relative to the SCLK rising edge (not shown in Figure 4)

10

ns

Timing Diagrams

APERTURE

DELAY

SAMPLE N

N + 1

ANALOG

N – 54

INPUT

SIGNAL

N – 55

N – 53

N – 1

N – 52

N – 51

CLK–

CLK+

CLK–

CLK+

SERDOUT0–

SERDOUT0+

A

B

C

D

E

F

G

H

I

J

A

B

C

D

E

F

G

H

I

J

A

B

C

D

E

F

G

H

I

J

CONVERTER0 MSB

CONVERTER0 LSB

CONVERTER1 MSB

CONVERTER1 LSB

SERDOUT1–

SERDOUT1+

H

A

J

SERDOUT2–

SERDOUT2+

SERDOUT3–

SERDOUT3+

SAMPLE N – 55

SAMPLE N – 54

SAMPLE N – 53

ENCODED INTO 1

8-BIT/10-BIT SYMBOL

Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1)

Rev. C | Page 10 of 97

Data Sheet

AD9680

CLK–

CLK+

t_{SU_SR}

t_{H_SR}

SYSREF–

SYSREF+

Figure 3. SYSREF Setup and Hold Timing

t_DS

t_HIGH

t_CLK

t_ACCESS

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

DON’T CARE

R/W

SDIO DON’T CARE

A14

A13

A12

A11

A10

A9

A8

A7

D7

D6

D3

D2

D1

D0

Figure 4. Serial Port Interface Timing Diagram

Rev. C | Page 11 of 97

AD9680

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

Typical θ_JA, θ_JB, and θ_JCare specified vs. the number of printed

circuit board (PCB) layers in different airflow velocities (in m/sec).

Airflow increases heat dissipation effectively reducing θ_JAand

θ_JB. In addition, metal in direct contact with the package leads

and exposed pad from metal traces, through holes, ground, and

power planes, reduces θ_JA. Thermal performance for actual

applications requires careful inspection of the conditions in

an application. The use of appropriate thermal management

techniques is recommended to ensure that the maximum junction

temperature does not exceed the limits shown in Table 6.

Parameter

Rating

Electrical

AVDD1 to AGND

AVDD1_SR to AGND

AVDD2 to AGND

AVDD3 to AGND

1.32 V

2.75 V

3.63 V

1.32 V

3.63 V

−0.3 V to +0.3 V

3.2 V

−0.3 V to SPIVDD + 0.3 V

−40°C to +85°C

−40°C to +115°C

DVDD to DGND

DRVDD to DRGND

SPIVDD to AGND

AGND to DRGND

VIN x to AGND

SCLK, SDIO, CSB to AGND

PDWN/STBY to AGND

Operating Temperature Range

Junction Temperature Range

Table 7. Thermal Resistance Values

Airflow

Velocity

(m/sec)

PCB Type

θ_JA

Ψ_JB

θ_{JC_TOP}θ_{JC_BOT}Unit

JEDEC

2s2p Board

0.0

1.0

2.5

17.8^{1, 2}6.3^{1, 3}4.7^{1, 4}

15.6^{1, 2}5.9^{1, 3}N/A⁵

15.0^{1, 2}5.7^{1, 3}N/A⁵

1.2^{1, 4}

°C/W

Storage Temperature Range (Ambient) −65°C to +150°C

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

¹Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³Per JEDEC JESD51-8 (still air).

⁴Per MIL-STD 883, Method 1012.1.

⁵N/A means not applicable.

ESD CAUTION

Rev. C | Page 12 of 97

Data Sheet

AD9680

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD1

AVDD2

AVDD3

VIN–A

VIN+A

AVDD3

AVDD2

1

2

3

4

5

6

7

8

9

48 AVDD1

47 AVDD1

46 AVDD2

45 AVDD3

44 VIN–B

43 VIN+B

42 AVDD3

41 AVDD2

40 AVDD2

39 AVDD2

38 SPIVDD

37 CSB

AD9680

TOP VIEW

(Not to Scale)

AVDD2 10

AVDD2 11

V_1P0 12

SPIVDD 13

PDWN/STBY 14

DVDD 15

36 SCLK

35 SDIO

34 DVDD

33 DGND

DGND 16

NOTES

1. EXPOSED PAD. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE

PACKAGE PROVIDES THE GROUND REFENCE FOR AVDDx. THIS EXPOSED

PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 5. Pin Configuration (Top View)

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

Power Supplies

0

EPAD

Ground

Exposed Pad. The exposed thermal pad on the bottom of the

package provides the ground reference for AVDDx. This

exposed pad must be connected to ground for proper

operation.

1, 2, 47, 48, 49, 52, 55, 61, 64 AVDD1

Supply

Analog Power Supply (1.25 V Nominal).

Analog Power Supply (2.5 V Nominal).

3, 8, 9, 10, 11, 39, 40, 41,

46, 50, 51, 62, 63

AVDD2

4, 7, 42, 45

13, 38

15, 34

16, 33

18, 31

19, 30

56, 60

57

AVDD3

SPIVDD

DVDD

Supply

Ground

Supply

Ground

Supply

Analog Power Supply (3.3 V Nominal).

Digital Power Supply for SPI (1.8 V to 3.3 V).

Digital Power Supply (1.25 V Nominal).

Ground Reference for DVDD.

Ground Reference for DRVDD.

Digital Driver Power Supply (1.25 V Nominal).

Ground Reference for SYSREF .

DGND

DRGND

DRVDD

AGND¹

AVDD1_SR¹

Analog Power Supply for SYSREF (1.25 V Nominal).

Analog

5, 6

12

VIN−A, VIN+A

V_1P0

Input

Input/DNC

ADC A Analog Input Complement/True.

1.0 V Reference Voltage Input/Do Not Connect. This pin is

configurable through the SPI as a no connect or an input. Do

not connect this pin if using the internal reference. Requires a

1.0 V reference voltage input if using an external voltage

reference source.

44, 43

53, 54

VIN−B, VIN+B

CLK+, CLK−

Input

ADC B Analog Input Complement/True.

Clock Input True/Complement.

CMOS Outputs

17, 32

FD_A, FD_B

Output

Fast Detect Outputs for Channel A and Channel B.

Rev. C | Page 13 of 97

AD9680

Data Sheet

Pin No.

Digital Inputs

20, 21

Mnemonic

Type

Description

SYNCINB−, SYNCINB+

SYSREF+, SYSREF−

Input

Active Low JESD204B LVDS Sync Input True/Complement.

Active High JESD204B LVDS System Reference Input

True/Complement.

58, 59

Data Outputs

22, 23

24, 25

26, 27

28, 29

SERDOUT0−, SERDOUT0+ Output

SERDOUT1−, SERDOUT1+ Output

SERDOUT2−, SERDOUT2+ Output

SERDOUT3−, SERDOUT3+ Output

Lane 0 Output Data Complement/True.

Lane 1 Output Data Complement/True.

Lane 2 Output Data Complement/True.

Lane 3 Output Data Complement/True.

Device Under Test (DUT)

Controls

14

PDWN/STBY

Input

Power-Down Input (Active High). The operation of this pin

depends on the SPI mode and can be configured as power-

down or standby. Requires an external 10 kΩ pull-down resistor.

35

36

37

SDIO

SCLK

CSB

Input/Output SPI Serial Data Input/Output.

Input

SPI Serial Clock.

SPI Chip Select (Active Low).

¹To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, see the Applications

Information section.

Rev. C | Page 14 of 97

Data Sheet

AD9680

TYPICAL PERFORMANCE CHARACTERISTICS

AD9680-1250

AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.58 V p-p

full-scale differential input, A_IN= −1.0 dBFS, default SPI settings, clock divider = 2, T_A= 25°C, 128k FFT sample, unless otherwise noted.

See Table 10 for recommended settings.

A

= –1dBFS

A

= –1dBFS

IN

–10

–30

–10

–30

SNR = 64dBFS

ENOB = 10.3 BITS

SFDR = 82dBFS

SNR = 62.5dBFS

ENOB = 9.9 BITS

SFDR = 70dBFS

BUFFER CURRENT = 3.5×

–50

–70

–90

–110

–130

–110

–130

0

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

0

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

Figure 6. Single-Tone FFT with f_IN= 10.3 MHz

Figure 9. Single-Tone FFT with f_IN= 450.3 MHz

A

= –1dBFS

A

= –1dBFS

IN

SNR = 60.9dBFS

ENOB = 9.8 BITS

SFDR = 74dBFS

IN

–10

–30

–10

–30

SNR = 63.4dBFS

ENOB = 10.2 BITS

SFDR = 79dBFS

BUFFER CURRENT = 3.5×

BUFFER CURRENT = 5.5×

–50

–70

–90

–110

–130

–110

–130

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

Figure 7. Single-Tone FFT with f_IN= 170.3 MHz

Figure 10. Single-Tone FFT with f_IN= 765.3 MHz

0

–20

A

= –1dBFS

SNR = 62.8dBFS

ENOB = 10.1 BITS

SFDR = 76dBFS

BUFFER CURRENT = 3.5×

A

= –1dBFS

IN

–10

–30

SNR = 59.7dBFS

ENOB = 9.6 BITS

SFDR = 74dBFS

BUFFER CURRENT = 5.5×

–40

–50

–60

–70

–80

–90

–100

–120

–110

–130

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

Figure 8. Single-Tone FFT with f_IN= 340.3 MHz

Figure 11. Single-Tone FFT with f_IN= 985.3 MHz

Rev. C | Page 15 of 97

AD9680

Data Sheet

0

85

80

75

70

65

60

A

= –1dBFS

IN

SNR = 58.5dBFS

ENOB = 9.3 BITS

SFDR = 68dBFS

BUFFER CURRENT = 5.5×

–20

SFDR

–40

–60

–80

–100

SNR

–120

0

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260

SAMPLE RATE (MHz)

Figure 12. Single-Tone FFT with f_IN= 1205.3 MHz

Figure 15. SNR/SFDR vs. f_S, f_IN= 170.3 MHz; Buffer Control 1 (0x018) = 3.5×

85

0

3.5× SNR (dBFS)

3.5× SFDR (dBFS)

4.5× SNR (dBFS)

A

= –1dBFS

IN

SNR = 56.6dBFS

ENOB = 9.0 BITS

SFDR = 67dBFS

BUFFER CURRENT = 7.5×

–20

–40

4.5× SFDR (dBFS)

80

75

70

65

60

–60

–80

–100

–120

10.3 147.3 212.3 290.3 355.3 433.3 511.3 589.3 667.3

0

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

INPUT FREQUENCY (MHz)

Figure 13. Single-Tone FFT with f_IN= 1602.3 MHz

Figure 16. SNR/SFDR vs. f_IN; f_IN< 700 MHz;

Buffer Control 1 (0x018) = 3.5× and 4.5×

0

–20

80

A

= –1dBFS

SNR 6.5×

SFDR 6.5×

IN

SNR = 55.4dBFS

ENOB = 8.8 BITS

SFDR = 63dBFS

75

70

65

60

55

BUFFER CURRENT = 8.5×

–40

–60

–80

–100

–120

0

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

628.3 706.6 784.3 862.3 940.3 1018.3 1096.3 1174.3 1252.3

INPUT FREQUENCY (MHz)

Figure 17. SNR/SFDR vs. f_IN; 650 MHz < f_IN< 1.3 GHz;

Buffer Control 1 (0x018) = 6.5×

Figure 14. Single-Tone FFT with f_IN= 1954.3 MHz

Rev. C | Page 16 of 97

Data Sheet

AD9680

80

0

–20

SNR 8.5×

SFDR 8.5×

IMD3 (dBc)

IMD3 (dBFS)

SFDR (dBFS)

SFDR (dBc)

75

70

65

60

55

50

–40

–60

–80

–100

–120

1252.3 1356.3 1460.3 1564.3 1668.3 177.23 1876.3 1980.3

–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6

INPUT AMPLITUDE (dBFS)

0

INPUT FREQUENCY (MHz)

Figure 18. SNR/SFDR vs. f_IN; 1.3 GHz < f_IN< 2GHz;

Buffer Control 1 (0x018) = 8.5×

Figure 21. Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

_IN1= 184 MHz and f_IN2= 187 MHz

f

0

A

AND A

= –7dBFS

IN2

IN1

IMD3 (dBc)

SFDR = 82dBFS

IMD2 = 84dBFS

IMD3 = 82dBFS

BUFFER CURRENT = 3.5×

IMD3 (dBFS)

SFDR (dBFS)

SFDR (dBc)

–20

–40

–60

–80

–100

–120

–140

–100

–120

–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6

0

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 19. Two-Tone FFT; f_IN1= 184 MHz, f_IN2= 187 MHz

Figure 22. Two-Tone IMD3/SFDR vs. Input Amplitude (A_IN) with

_IN1= 449 MHz and f_IN2= 452 MHz

f

0

–20

120

100

80

A

AND A

= –7dBFS

IN2

IN1

SFDR = 78dBFS

IMD2 = 78dBFS

IMD3 = 78dBFS

BUFFER CURRENT = 5.5×

–40

60

40

–60

20

–80

0

SNR (dBFS)

SNR (dBc)

SFDR (dBc)

SFDR (dBFS)

–100

–120

–20

–40

–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6

INPUT AMPLITUDE (dBFS)

0

78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000

FREQUENCY (MHz)

Figure 20. Two-Tone FFT; f_IN1= 449 MHz, f_IN2= 452 MHz

Figure 23. SNR/SFDR vs. Analog Input Level, f_IN= 170.3 MHz

Rev. C | Page 17 of 97

AD9680

Data Sheet

85

80

75

70

65

60

55

1200000

1000000

800000

600000

400000

200000

0

3.45 LSB rms

SFDR

SNR

–48 –38 –28 –18 –8

2

12 22 32 42 52 62 72 82 92 102 112

TEMPERATURE (°C)

CODE

Figure 24. SNR/SFDR vs. Temperature, f_IN= 170.3 MHz

Figure 27. Input-Referred Noise Histogram

4

3

4.00

3.95

3.90

3.85

3.80

3.75

3.70

3.65

3.60

3.55

2

1

0

–1

–2

–3

–4

0

2000

4000

6000

8000 10000 12000 14000 16000

–48 –38 –28 –18 –8

2

12 22 32 42 52 62 72 82

OUTPUT CODE

TEMPERATURE (°C)

Figure 25. INL, f_IN= 10.3 MHz

Figure 28. Power Dissipation vs. Temperature

0.4

0.3

4.0

3.9

3.8

3.7

3.6

3.5

3.4

3.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

0

2000

4000

6000

8000 10000 12000 14000 16000

1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260

OUTPUT CODE

SAMPLE RATE (MHz)

Figure 26. DNL, f_IN= 15 MHz

Figure 29. Power Dissipation vs. f_S

Rev. C | Page 18 of 97

Data Sheet

AD9680

AD9680-1000

AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.7 V p-p

full-scale differential input, A_IN= −1.0 dBFS, default SPI settings, clock divider = 2, T_A= 25°C, 128k FFT sample, unless otherwise noted.

See Table 10 for recommended settings.

A

= –1dBFS

A

= –1dBFS

IN

–10

–30

–10

–30

SNR = 67.2dBFS

ENOB = 10.8 BITS

SFDR = 88dBFS

SNR = 64.0dBFS

ENOB = 10.3 BITS

SFDR = 82dBFS

BUFFER CONTROL 1 = 1.5×

BUFFER CONTROL 1 = 3.0×

–50

–70

–90

–110

–130

–110

–130

0

100

200

300

400

500

0

100

200

300

400

500

FREQUENCY (MHz)

Figure 30. Single-Tone FFT with f_IN= 10.3 MHz

Figure 33. Single-Tone FFT with f_IN= 450.3 MHz

0

–20

A

= –1dBFS

IN

A

= –1dBFS

SNR = 61.5dBFS

ENOB = 10.1 BITS

SFDR = 82dBFS

BUFFER CONTROL 1 = 6.0×

IN

–10

–30

SNR = 66.6dBFS

ENOB = 10.7 BITS

SFDR = 85dBFS

BUFFER CONTROL 1 = 3.0×

–40

–50

–60

–70

–80

–90

–100

–120

–110

–130

100

200

300

400

500

100

200

300

400

500

FREQUENCY (MHz)

Figure 31. Single-Tone FFT with f_IN= 170.3 MHz

Figure 34. Single-Tone FFT with f_IN= 765.3 MHz

0

A

= –1dBFS

A

= –1dBFS

SNR = 65.3dBFS

ENOB = 10.5 BITS

SFDR = 85dBFS

BUFFER CONTROL 1 = 3.0×

IN

–10

–30

SNR = 60.5dBFS

ENOB = 9.9 BITS

SFDR = 80dBFS

–20

–40

BUFFER CONTROL 1 = 6.0×

–50

–60

–70

–80

–90

–100

–120

–110

–130

100

200

300

400

500

100

200

300

400

500

FREQUENCY (MHz)

Figure 35. Single-Tone FFT with f_IN= 985.3 MHz

Figure 32. Single-Tone FFT with f_IN= 340.3 MHz

Rev. C | Page 19 of 97

AD9680

Data Sheet

0

90

85

80

75

70

65

60

A

= –1dBFS

IN

SNR = 59.8BFS

ENOB = 9.6 BITS

SFDR = 79dBFS

BUFFER CONTROL 1 = 8.0×

–20

–40

SFDR (dBFS)

–60

–80

SNR (dBFS)

–100

–120

0

100

200

300

400

500

700

750

800

850

900

950

1000

1050

1100

FREQUENCY (MHz)

SAMPLE RATE (MHz)

Figure 39. SNR/SFDR vs. f_S, f_IN= 170.3 MHz; Buffer Control 1 (0x018) = 3.0×

Figure 36. Single-Tone FFT with f_IN= 1293.3 MHz

90

85

80

75

70

65

0

–20

A

= –1dBFS

IN

SNR = 57.7dBFS

ENOB = 9.2 BITS

SFDR = 70dBFS

BUFFER CONTROL 1 = 8.0×

–40

–60

–80

60

1.5× SFDR (dBFS)

1.5× SNR (dBFS)

3.0× SFDR (dBFS)

3.0× SNR (dBFS)

–100

–120

55

50

10.3 63.3 100.3 170.3 225.3 302.3 341.3 403.3 453.3 502.3

0

100

200

300

400

500

ANALOG INPUT FREQUENCY (MHz)

FREQUENCY (MHz)

Figure 40. SNR/SFDR vs. f_IN; f_IN< 500 MHz;

Buffer Control 1 (0x018) = 1.5× and 3.0×

Figure 37. Single-Tone FFT with f_IN= 1725.3 MHz

100

90

80

70

60

0

–20

A

= –1dBFS

IN

SNR = 57.0dBFS

ENOB = 9.1 BITS

SFDR = 69dBFS

BUFFER CURRENT = 6.0×

–40

–60

–80

–100

–120

4.0× SFDR

4.0× SNRFS

6.0× SFDR

6.0× SNRFS

50

476.8 554.4 593.2 670.8 748.4 826.0 903.6

ANALOG INPUT FREQUENCY (MHz)

981.2

0

100

200

300

400

500

FREQUENCY (MHz)

Figure 41. SNR/SFDR vs. f_IN; 500 MHz < f_IN< 1 GHz;

Buffer Control 1 (0x018) = 4.0× and 6.0×

Figure 38. Single-Tone FFT with f_IN= 1950.3 MHz

Rev. C | Page 20 of 97

Data Sheet

AD9680

100

90

80

70

60

50

0

–20

A

AND A

= –7dBFS

IN2

IN1

SFDR = 88dBFS

IMD2 = 93dBFS

IMD3 = 88dBFS

BUFFER CONTROL 1 = 4.5×

–40

–60

SFDR

SNR

–80

–100

–120

0

100

200

300

400

500

978.5

1065.0 1142.4 1220.0 1297.3 1374.8 1452.2

ANALOG INPUT FREQUENCY (MHz)

FREQUENCY (MHz)

Figure 45. Two-Tone FFT; f_IN1= 338 MHz, f_IN2= 341 MHz

Figure 42. SNR/SFDR vs. f_IN; 1 GHz < f_IN< 1.5 GHz;

Buffer Control 1 (0x018) = 6.0×

100

20

SFDR (dBc)

SFDR (dBFS)

IMD3 (dBc)

0

IMD3 (dBFS)

90

–20

–40

80

70

–60

SFDR

SNR

–80

–100

–120

–140

60

50

1513.3

1607.4

1701.6

1795.6

1889.7

–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6

ANALOG INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 46. Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

Figure 43. SNR/SFDR vs. f_IN; 1.5 GHz < f_IN< 2 GHz;

Buffer Control 1 (0x018) = 7.5×

f

_IN1= 184 MHz and f_IN2= 187 MHz

20

0

–20

SFDR (dBc)

SFDR (dBFS)

IMD3 (dBc)

A

AND A

= –7dBFS

IN2

IN1

SFDR = 87dBFS

IMD2 = 93dBFS

IMD3 (dBFS)

IMD3 = 87dBFS

BUFFER CONTROL 1 = 3.0×

–20

–40

–60

–80

–100

–120

–140

–40

–60

–80

–100

–120

0

100

200

300

400

500

–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 47. Two-Tone IMD3/SFDR vs. Input Amplitude (A_IN) with

Figure 44. Two-Tone FFT; f_IN1= 184 MHz, f_IN2= 187 MHz

f

_IN1= 338 MHz and f_IN2= 341 MHz

Rev. C | Page 21 of 97

AD9680

Data Sheet

110

100

90

3

2

80

70

1

60

50

0

40

30

–1

–2

–3

20

10

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

0

–10

–20

0

2000

4000

6000

8000 10000 12000 14000 16000

–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6

0

OUTPUT CODE

INPUT AMPLITUDE (dBFS)

Figure 50. INL, f_IN= 10.3 MHz

Figure 48. SNR/SFDR vs. Analog Input Level, f_IN= 170.3 MHz

0.6

0.4

100

90

SFDR

0.2

80

0

70

SNR

–0.2

–0.4

–0.6

60

50

–50 –40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

0

2000

4000

6000

8000 10000 12000 14000 16000

TEMPERATURE (°C)

OUTPUT CODE

Figure 51. DNL, f_IN= 15 MHz

Figure 49. SNR/SFDR vs. Temperature, f_IN= 170.3 MHz

Rev. C | Page 22 of 97

Data Sheet

AD9680

3.40

3.35

3.30

3.25

3.20

3.15

3.10

3.05

3.00

2.95

2.90

25000

L = 4, M = 2, F = 1

2.63 LSB rms

20000

15000

10000

5000

0

700

750

800

850

900

950

1000

1050

1100

N – 6 N – 5 N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4 N + 5 N + 6

SAMPLE RATE (MHz)

CODE

Figure 52. Input-Referred Noise Histogram

Figure 54. Power Dissipation vs. f_S

3.40

3.35

3.30

3.25

3.20

3.15

L = 4

M = 2

F = 1

–50 –40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90

TEMPERATURE (°C)

Figure 53. Power Dissipation vs. Temperature

Rev. C | Page 23 of 97

AD9680

Data Sheet

AD9680-820

AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.7 V p-p

full-scale differential input, A_IN= −1.0 dBFS, default SPI settings, clock divider = 2, T_A= 25°C, 128k FFT sample, unless otherwise noted.

See Table 10 for recommended settings.

0

A

= –1dBFS

A

= –1dBFS

IN

SNR = 67.2dBFS

SNR = 65.1dBFS

–20

ENOB = 10.5 BITS

SFDR = 79dBFS

–20

ENOB = 10.9BITS

SFDR = 89dBFS

BUFFER CONTROL 1 = 6.5×

BUFFER CONTROL 1 = 1.5×

–40

–60

–80

–100

–120

–100

–120

0

82

164

246

328

410

0

82

164

246

328

410

FREQUENCY (MHz)

Figure 55. Single-Tone FFT with f_IN= 10.3 MHz

Figure 58. Single-Tone FFT with f_IN= 450.3 MHz

0

–20

0

–20

A

= –1dBFS

A

= –1dBFS

IN

SNR = 67.0dBFS

ENOB = 10.8 BITS

SFDR = 83dBFS

SNR = 64.0dBFS

ENOB = 10.3 BITS

SFDR = 79dBFS

BUFFER CONTROL 1 = 2.0×

BUFFER CONTROL 1 = 6.5×

–40

–60

–80

–100

–120

–100

–120

0

82

164

246

328

410

0

82

164

246

328

FREQUENCY (MHz)

Figure 56. Single-Tone FFT with f_IN= 170.3 MHz

Figure 59. Single-Tone FFT with f_IN= 765.3 MHz

0

–20

0

–20

A

= –1dBFS

SNR = 66.5dBFS

ENOB = 10.7 BITS

SFDR = 86dBFS

BUFFER CONTROL 1 = 3.0×

A

= –1dBFS

IN

SNR = 63.4dBFS

ENOB = 10.1 BITS

SFDR = 74dBFS

BUFFER CONTROL 1 = 8.5×

–40

–60

–80

–100

–120

–100

–120

0

82

164

246

328

410

0

82

164

246

328

FREQUENCY (MHz)

Figure 57. Single-Tone FFT with f_IN= 340.3 MHz

Figure 60. Single-Tone FFT with f_IN= 985.3 MHz

Rev. C | Page 24 of 97

Data Sheet

AD9680

0

90

85

80

75

70

65

60

55

50

A

= –1dBFS

IN

SNR = 62.0dBFS

ENOB = 9.9 BITS

SFDR = 76dBFS

BUFFER CONTROL 1 = 6.5×

–20

–40

SFDR

SNR

–60

–80

–100

–120

500

550

600

650

700

750

800

850

900

0

82

164

246

328

410

SAMPLE RATE (MHz)

FREQUENCY (MHz)

Figure 61. Single-Tone FFT with f_IN= 1205.3 MHz

Figure 64. SNR/SFDR vs. f_S, f_IN= 170.3 MHz;

Buffer Control 1 (0x018) = 3.0×

0

–20

95

90

85

80

75

70

65

60

55

50

A

= –1dBFS

IN

SNR = 60.5dBFS

ENOB = 9.5 BITS

SFDR = 68dBFS

BUFFER CONTROL 1 = 7.5×

–40

–60

–80

–100

–120

SFDR (3.0×)

SNR (3.0×)

0

82

164

246

328

410

FREQUENCY (MHz)

ANALOG INPUT FREQUENCY (MHz)

Figure 65. SNR/SFDR vs. f_IN; f_IN< 450 MHz;

Buffer Control 1 (0x018) = 3.0×

Figure 62. Single-Tone FFT with f_IN= 1720.3 MHz

85

0

–20

A

= –1dBFS

IN

SNR = 59.7dBFS

ENOB = 9.5 BITS

SFDR = 69dBFS

BUFFER CONTROL 1 = 8.5×

80

75

70

65

60

55

–40

–60

–80

–100

–120

SFDR (6.5×)

SNR (6.5×)

50

450.3

480.3

510.3

515.3

610.3

766.3

810.3

985.3

0

82

164

246

328

410

ANALOG INPUT FREQUENCY (MHz)

FREQUENCY (MHz)

Figure 66. SNR/SFDR vs. f_IN; 450 MHz < f_IN< 1 GHz;

Buffer Control 1 (0x018) = 6.5×

Figure 63. Single-Tone FFT with f_IN= 1950.3 MHz

Rev. C | Page 25 of 97

AD9680

Data Sheet

0

–20

80

75

70

65

60

55

50

AIN1 AND AIN2 = –7dBFS

SFDR = 87dBFS

IMD2 = 92dBFS

IMD3 = 87dBFS

BUFFER CURRENT = 3.0×

–40

–60

–80

–100

–120

SFDR (6.5×)

SNR (6.5×)

0

82

164

246

328

410

985.3 1022.3

1110.3

1205.3

1315.3

1420.3

1510.3

FREQUENCY (MHz)

ANALOG INPUT FREQUENCY (MHz)

Figure 67. SNR/SFDR vs. f_IN; 1 GHz < f_IN< 1.5 GHz;

Buffer Control 1 (0x018) = 6.5×

Figure 70. Two-Tone FFT; f_IN1= 338 MHz, f_IN2= 341 MHz

75

70

65

60

55

0

IMD3 (dBc)

IMD3 (dBFS)

SFDR (dBc)

SFDR (dBFS)

–20

–40

–60

–80

–100

–120

SFDR (8.5×)

SNR (8.5×)

50

1510.3

1600.3

1720.3

1810.3

1920.3

1950.3

–87 –81 –75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9

INPUT AMPLITUDE (dBFS)

ANALOG INPUT FREQUENCY (MHz)

Figure 68. SNR/SFDR vs. f_IN; 1.5 GHz < f_IN< 2 GHz;

Buffer Control 1 (0x018) = 8.5×

Figure 71. Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

_IN1= 184 MHz and f_IN2= 187 MHz

f

0

–20

0

AIN1 AND AIN2 = –7dBFS

SFDR = 90dBFS

IMD2 = 90dBFS

IMD3 = 91dBFS

BUFFER CURRENT = 3.0×

IMD3 (dBc)

IMD3 (dBFS)

SFDR (dBc)

SFDR (dBFS)

–20

–40

–60

–80

–100

–120

0

–87 –81 –75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9

INPUT AMPLITUDE (dBFS)

82

164

246

328

410

FREQUENCY (MHz)

Figure 72. Two-Tone IMD3/SFDR vs. Input Amplitude (A_IN) with

_IN1= 338 MHz and f_IN2= 341 MHz

Figure 69. Two-Tone FFT; f_IN1= 184 MHz, f_IN2= 187 MHz

f

Rev. C | Page 26 of 97

Data Sheet

AD9680

120

105

90

2.5

2.0

1.5

75

1.0

60

0.5

45

0

30

–0.5

–1.0

–1.5

–2.0

15

SNR (dBc)

0

SNR (dBFS)

SFDR (dBc)

SFDR (dBFS)

–15

–30

0

2000

4000

6000

8000 10000 12000 14000 16000

OUTPUT CODE

INPUT AMPLITUDE (dBFS)

Figure 73. SNR/SFDR vs. Analog Input Level, f_IN= 170.3 MHz

Figure 75. INL, f_IN= 10.3 MHz

90

0.25

0.20

SNR (dBFS)

SFDR (dBFS)

85

80

75

70

65

60

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–45

–30

–15

–5

5

15

25

45

65

85

0

2000

4000

6000

8000 10000 12000 14000 16000

TEMPERATURE (°C)

OUTPUT CODE

Figure 76. DNL, f_IN= 15 MHz

Figure 74. SNR/SFDR vs. Temperature, f_IN= 170.3 MHz

Rev. C | Page 27 of 97

AD9680

Data Sheet

3.1

3.0

2.9

2.8

2.7

2.6

2.5

1600000

1400000

1200000

1000000

800000

600000

400000

200000

0

2.46 LSB rms

CODE

SAMPLE RATE (MHz)

Figure 79. Power Dissipation vs. f_S; L = 4, M = 2, F = 1 for f_S≥ 625 MSPS and

L = 2, M = 2, F = 2 for f_S< 625 MSPS (Default SPI)

Figure 77. Input-Referred Noise Histogram

2.90

2.88

2.86

2.84

2.82

2.80

2.78

2.76

–45

–30

–15

–5

5

15

25

45

65

85

TEMPERATURE (°C)

Figure 78. Power Dissipation vs. Temperature

Rev. C | Page 28 of 97

Data Sheet

AD9680

AD9680-500

AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 2.06 V p-p

full-scale differential input, A_IN= −1.0 dBFS, default SPI settings, clock divider = 2, T_A= 25°C, 128k FFT sample, unless otherwise noted.

See Table 10 for recommended settings.

0

A

= −1dBFS

A

= −1dBFS

IN

SNR = 68.9dBFS

SNR = 67.8dBFS

ENOB = 10.9 BITS

SFDR = 83dBFS

ENOB = 10.8 BITS

SFDR = 83dBFS

–20

BUFFER CONTROL 1 = 4.5×

BUFFER CONTROL 1 = 2.0×

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

Figure 83. Single-Tone FFT with f_IN= 450.3 MHz

Figure 80. Single-Tone FFT with f_IN= 10.3 MHz

0

A

= −1dBFS

IN

A

= −1dBFS

IN

SNR = 68.9dBFS

SNR = 64.7dBFS

ENOB = 11 BITS

–20

–40

–20

–40

ENOB = 10.4 BITS

SFDR = 80dBFS

SFDR = 88dBFS

BUFFER CONTROL 1 = 2.0×

BUFFER CONTROL 1 = 5.0×

–60

–80

–100

–120

–140

–100

–120

–140

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

Figure 81. Single-Tone FFT with f_IN= 170.3 MHz

Figure 84. Single-Tone FFT with f_IN= 765.3 MHz

0

–20

0

A

= −1dBFS

IN

A

= −1dBFS

IN

SNR = 68.5dBFS

SNR = 64.0dBFS

ENOB = 10.9 BITS

SFDR = 83dBFS

–20

–40

ENOB = 10.3 BITS

SFDR = 76dBFS

BUFFER CONTROL 1 = 4.5×

BUFFER CONTROL 1 = 5.0×

–40

–60

–80

–100

–120

–140

–100

–120

–140

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

Figure 82. Single-Tone FFT with f_IN= 340.3 MHz

Figure 85. Single-Tone FFT with f_IN= 985.3 MHz

Rev. C | Page 29 of 97

AD9680

Data Sheet

95

90

85

80

75

70

65

60

0

A

= −1dBFS

IN

SNR = 63.0dBFS

–20

ENOB = 10.0 BITS

SFDR = 69dBFS

BUFFER CONTROL 1 = 8.0×

SFDR

–40

–60

–80

SNR

–100

–120

–140

0

300 320 340 360 380 400 420 440 460 480 500 530 550

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

SAMPLE FREQUENCY (MHz)

Figure 86. Single-Tone FFT with f_IN= 1310.3 MHz

Figure 89. SNR/SFDR vs. f_S, f_IN= 170.3 MHz; Buffer Control 1 = 2.0×

100

0

–20

A

= −1dBFS

IN

SNR = 61.5dBFS

ENOB = 9.8 BITS

SFDR = 69dBFS

90

80

70

BUFFER CONTROL 1 = 8.0×

–40

–60

–80

–100

–120

–140

60

2.0× SNR

2.0× SFDR

4.5× SNR

4.5× SFDR

50

10.3

95.3 150.3 180.3 240.3 301.3 340.7 390.3 450.3

ANALOG INPUT FREQUENCY (MHz)

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

Figure 87. Single-Tone FFT with f_IN= 1710.3 MHz

Figure 90. SNR/SFDR vs. f_IN; f_IN< 500 MHz;

Buffer Control 1 (0x018) = 2.0× and 4.5×

0

–20

100

90

80

70

60

50

A

= −1dBFS

IN

SNR = 60.8dBFS

ENOB = 9.6 BITS

SFDR = 68dBFS

BUFFER CONTROL 1 = 8.0×

–40

–60

–80

–100

–120

–140

4.0× SNR

4.0× SFDR

8.0× SNR

8.0× SFDR

450.3 480.3 510.3 515.3 610.3 765.3 810.3 985.3 1010.3

0

25

50

75

100 125 150 175 200 225 250

FREQUENCY (MHz)

ANALOG INPUT FREQUENCY (MHz)

Figure 91. SNR/SFDR vs. f_IN; 500 MHz < f_IN< 1 GHz;

Buffer Control 1 (0x018) = 4.0× and 8.0×

Figure 88. Single-Tone FFT with f_IN= 1950.3 MHz

Rev. C | Page 30 of 97

Data Sheet

AD9680

80

0

–20

7.0× SNR

SFDR (dBc)

7.0× SFDR

8.0× SNR

SFDR (dBFS)

IMD3 (dBc)

8.0× SFDR

75

70

65

60

55

IMD3 (dBFS)

–40

–60

–80

–100

–120

50

1010.3

–90

–84

–78

–72

–66

–60 –54 –48 –42 –36 –30 –24 –18 –12

1205.3

1410.3

1600.3

1810.3

1950.3

ANALOG INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 92. SNR/SFDR vs. f_IN; 1 GHz < f_IN< 2 GHz;

Buffer Control 1 (0x018) = 7.0× and 8.0×

Figure 95. Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

_IN1= 184 MHz and f_IN2= 187 MHz

f

0

A

AND A

= –7dBFS

IN2

SFDR (dBc)

SFDR (dBFS)

IMD3 (dBc)

IN1

SFDR = 88dBFS

IMD2 = 94dBFS

–20

–40

–20

IMD3 (dBFS)

IMD3 = 88dBFS

BUFFER CONTROL 1 = 2.0×

–40

–60

–80

–100

–120

–100

–120

–90

–81

–72

–63

–54

–45

–36

–27

–18

–9

0

50

100

150

200

250

FREQUENCY (MHz)

AMPLITUDE (dBFS)

Figure 93. Two-Tone FFT; f_IN1= 184 MHz, f_IN2= 187 MHz

Figure 96. Two-Tone IMD3/SFDR vs. Input Amplitude (A_IN) with

_IN1= 338 MHz and f_IN2= 341 MHz

f

0

–20

–40

–60

–80

110

100

90

A

AND A

= –7dBFS

IN2

IN1

SFDR = 88dBFS

IMD2 = 88dBFS

IMD3 = 89dBFS

BUFFER CONTROL 1 = 4.5×

80

70

60

50

40

30

20

10

–100

SFDR (dBFS)

SNR (dBFS)

SFDR (dBc)

SNR (dBc)

0

–10

–120

–20

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

50

100

150

200

250

FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 94. Two-Tone FFT; f_IN1= 338 MHz, f_IN2= 341 MHz

Figure 97. SNR/SFDR vs. Analog Input Level, f_IN= 170.3 MHz

Rev. C | Page 31 of 97

AD9680

Data Sheet

95

90

85

80

75

70

900000

800000

700000

600000

500000

400000

300000

200000

100000

0

2.06 LSB RMS

SFDR

SNR

65

–40

–15

10

35

60

85

TEMPERATURE (°C)

OUTPUT CODE

Figure 98. SNR/SFDR vs. Temperature, f_IN= 170.3 MHz

Figure 101. Input-Referred Noise Histogram

2.32

2.30

2.28

2.26

2.24

2.22

2.20

3.0

2.5

L = 4

M = 2

F = 1

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

0

2000

4000

6000

8000 10000 12000 14000 16000

–45

–35

–5

15

25

45

65

85

TEMPERATURE (°C)

OUTPUT CODE

Figure 99. INL, f_IN= 10.3 MHz

Figure 102. Power Dissipation vs. Temperature

0.8

0.6

2.37

2.32

2.27

2.22

2.17

2.12

2.07

2.02

1.97

1.92

1.87

L = 4, M = 2, F = 1

L = 2, M = 2, F = 2

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

0

2000

4000

6000

8000 10000 12000 14000 16000

300 320 340 360 380 400 420 440 460 480 500 520 540

OUTPUT CODE

SAMPLE RATE (MHz)

Figure 103. Power Dissipation vs. f_S

Figure 100. DNL, f_IN= 15 MHz

Rev. C | Page 32 of 97

Data Sheet

AD9680

EQUIVALENT CIRCUITS

AVDD3

VIN+x

AVDD3

3pF 1.5pF

EMPHASIS/SWING

CONTROL (SPI)

400Ω

V

CM

BUFFER

10pF

DRVDD

AVDD3

DATA+

DATA–

SERDOUTx+

x = 0, 1, 2, 3

DRGND

DRVDD

VIN–x

OUTPUT

DRIVER

A

IN

SERDOUTx–

x = 0, 1, 2, 3

3pF 1.5pF

CONTROL

(SPI)

DRGND

Figure 104. Analog Inputs

Figure 107. Digital Outputs

DVDD

1kΩ

SYNCINB+

AVDD1

25Ω

20kΩ

CLK+

CLK–

DGND

DVDD

LEVEL

V

= 0.85V

TRANSLATOR

CM

20kΩ

AVDD1

V

CM

1kΩ

25Ω

SYNCINB–

SYNCINB± PIN

CONTROL (SPI)

20kΩ

DGND

V

= 0.85V

CM

Figure 105. Clock Inputs

Figure 108. SYNCINB Inputs

AVDD1_SR

1kΩ

SYSREF+

SPIVDD

ESD

PROTECTED

20kΩ

SPIVDD

LEVEL

V

= 0.85V

1kΩ

TRANSLATOR

CM

SCLK

AVDD1_SR

20kΩ

30kΩ

1kΩ

ESD

PROTECTED

SYSREF–

Figure 106. SYSREF Inputs

Figure 109. SCLK Input

Rev. C | Page 33 of 97

AD9680

Data Sheet

SPIVDD

ESD

PROTECTED

ESD

PROTECTED

30kΩ

1kΩ

PDWN/

STBY

CSB

ESD

PROTECTED

ESD

PROTECTED

PDWN

CONTROL (SPI)

Figure 110. CSB Input

Figure 113. PDWN/STBY Input

SPIVDD

AVDD2

ESD

PROTECTED

SDO

SPIVDD

SDI

1kΩ

V_1P0

SDIO

30kΩ

ESD

PROTECTED

ESD

PROTECTED

V_1P0 PIN

CONTROL (SPI)

Figure 111. SDIO Input

Figure 114. V_1P0 Input/Output

SPIVDD

ESD

PROTECTED

FD

JESD LMFC

JESD SYNC~

FD_A/FD_B

TEMPERATURE DIODE

(FD_A ONLY)

ESD

PROTECTED

FD_x PIN CONTROL (SPI)

Figure 112. FD_A/FD_B Outputs

Rev. C | Page 34 of 97

Data Sheet

AD9680

THEORY OF OPERATION

The AD9680 has two analog input channels and four JESD204B

output lane pairs. The ADC is designed to sample wide bandwidth

analog signals of up to 2 GHz. The AD9680 is optimized for wide

input bandwidth, high sampling rate, excellent linearity, and

low power in a small package.

into sample mode, the signal source must be capable of charging

the sample capacitors and settling within one-half of a clock cycle.

A small resistor, in series with each input, can help reduce the peak

transient current injected from the output stage of the driving

source. In addition, low Q inductors or ferrite beads can be placed

on each leg of the input to reduce high differential capacitance at

the analog inputs and, thus, achieve the maximum bandwidth of

the ADC. Such use of low Q inductors or ferrite beads is required

when driving the converter front end at high IF frequencies.

Either a differential capacitor or two single-ended capacitors

can be placed on the inputs to provide a matching passive network.

This ultimately creates a low-pass filter at the input, which limits

unwanted broadband noise. For more information, refer to the

AN-742 Application Note, the AN-827 Application Note, and

the Analog Dialogue article “Transformer-Coupled Front-End

for Wideband A/D Converters” (Volume 39, April 2005). In

general, the precise values depend on the application.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations.

The AD9680 has several functions that simplify the AGC

function in a communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect output bits of the ADC. If the input

signal level exceeds the programmable threshold, the fast detect

indicator goes high. Because this threshold indicator has low

latency, the user can quickly turn down the system gain to avoid

an overrange condition at the ADC input.

For best dynamic performance, the source impedances driving

VIN+x and VIN−x must be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates a differential reference that defines the span of the

ADC core.

The Subclass 1 JESD204B-based high speed serialized output data

lanes can be configured in one-lane (L = 1), two-lane (L = 2),

and four-lane (L = 4) configurations, depending on the sample

rate and the decimation ratio. Multiple device synchronization

is supported through the SYSREF and SYNCINB input pins.

Maximum SNR performance is achieved by setting the ADC

to the largest span in a differential configuration. In the case

of the AD9680, the available span is programmable through

the SPI port from 1.46 V p-p to 2.06 V p-p differential, with

1.58 V p-p differential being the default for the AD9680-1250,

1.70 V p-p differential being the default for the AD9680-1000

and AD9680-820, and 2.06 V p-p differential being the default

for the AD9680-500.

ADC ARCHITECTURE

The architecture of the AD9680 consists of an input buffered

pipelined ADC. The input buffer is designed to provide a

termination impedance to the analog input signal. This

termination impedance can be changed using the SPI to meet

the termination needs of the driver/amplifier. The default

termination value is set to 400 Ω. The equivalent circuit diagram of

the analog input termination is shown in Figure 104. The input

buffer is optimized for high linearity, low noise, and low power.

Differential Input Configurations

There are several ways to drive the AD9680, either actively or

passively. However, optimum performance is achieved by

driving the analog input differentially.

The input buffer provides a linear high input impedance (for

ease of drive) and reduces kickback from the ADC. The buffer

is optimized for high linearity, low noise, and low power. The

quantized outputs from each stage are combined into a final

14-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample; at the same time, the remaining stages operate with the

preceding samples. Sampling occurs on the rising edge of the clock.

For applications where SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration (see Figure 115 and Table 9) because the noise

performance of most amplifiers is not adequate to achieve the

true performance of the AD9680.

For low to midrange frequencies, a double balun or double

transformer network (see Figure 115 and Table 9) is recom-

mended for optimum performance of the AD9680. For higher

frequencies in the second or third Nyquist zones, it is better

to remove some of the front-end passive components to ensure

wideband operation (see Figure 115 and Table 9).

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9680 is a differential buffer. The

internal common-mode voltage of the buffer is 2.05 V. The

clock signal alternately switches the input circuit between

sample mode and hold mode. When the input circuit is switched

Rev. C | Page 35 of 97

AD9680

Data Sheet

0.1µF

R2

R3

R1

C1

C2

ADC

BALUN

0.1µF

R2

0.1µF

C1

NOTES

1. SEE TABLE 9 FOR COMPONENT VALUES.

Figure 115. Differential Transformer-Coupled Configuration for AD9680

Table 9. Differential Transformer-Coupled Input Configuration Component Values

Device

Frequency Range

Transformer

R1 (Ω)

R2 (Ω)

50

R3 (Ω)

10

0

C1 (pF)

C2 (pF)

AD9680-500

DC to 250 MHz

250 MHz to 2 GHz

DC to 410 MHz

410 MHz to 2 GHz

DC to 500 MHz

500 MHz to 2 GHz

DC to 625 MHz

ETC1-1-13

BAL-0006/BAL-0006SMG

ETC1-1-13

BAL-0006/BAL-0006SMG

ETC1-1-13/BAL-0006SMG

BAL-0006/BAL-0006SMG

BAL-0006SMG

10

4

2

AD9680-820

AD9680-1000

AD9680-1250

10

50

4

2

25

4

2

Open

4

Open

2

Open

10

50

15

0

625 MHz to 2 GHz

BAL-0006SMG

Input Common Mode

Input Buffer Control Registers (0x018, 0x019, 0x01A,

0x935, 0x934, 0x11A)

The analog inputs of the AD9680 are internally biased to the

common mode as shown in Figure 116. The common-mode

buffer has a limited range in that the performance suffers greatly

if the common-mode voltage drops by more than 100 mV.

Therefore, in dc-coupled applications, set the common-mode

voltage to 2.05 V, 100 mV to ensure proper ADC operation.

The full-scale voltage setting must be at a 1.7 V p-p differential

if running in a dc-coupled application.

The input buffer has many registers that set the bias currents and

other settings for operation at different frequencies. These bias

currents and settings can be changed to suit the input frequency

range of operation. Register 0x018 controls the buffer bias current

to help with the kickback from the ADC core. This setting can be

scaled from a low setting of 1.0× to a high setting of 8.5×. The

default setting is 3.0× for the AD9680-1000 and AD9680-820,

and 2.0× for the AD9680-500. These settings are sufficient for

operation in the first Nyquist zone for the products. When the

input buffer current in Register 0x018 is set, the amount of

current required by the AVDD3 supply changes. This relationship

is shown in Figure 117. For a complete list of buffer current

settings, see Table 36.

Analog Input Buffer Controls and SFDR Optimization

The AD9680 input buffer offers flexible controls for the analog

inputs, such as input termination, buffer current, and input full-

scale adjustment. All the available controls are shown in Figure 116.

AVDD3

300

VIN+x

250

AD9680-1250,

AD9680-1000,

AND

AVDD3

3pF 1.5pF

AD9680-820

200

400Ω

V

CM

BUFFER

AD9680-500

10pF

150

AVDD3

100

VIN–x

AIN CONTROL

SPI REGISTERS

(0x008, 0x015,

0x016, 0x018,

0x019, 0x01A,

0x11A, 0x934,

0x935)

3pF 1.5pF

50

1.5×

2.5×

3.5×

4.5×

5.5×

6.5×

7.5×

8.5×

BUFFER CONTROL 1 SETTING

Figure 117. I_AVDD3vs. Buffer Control 1 Setting in Register 0x018

Figure 116. Analog Input Controls

The 0x019, 0x01A, 0x11A, and 0x935 registers offer secondary

bias controls for the input buffer for frequencies >500 MHz.

Register 0x934 can be used to reduce input capacitance to achieve

wider signal bandwidth but may result in slightly lower linearity

Using the 0x018, 0x019, 0x01A, 0x11A, 0x934, and 0x935 registers,

the buffer behavior on each channel can be adjusted to optimize the

SFDR over various input frequencies and bandwidths of interest.

Rev. C | Page 36 of 97

Data Sheet

AD9680

76

74

72

70

68

66

64

62

60

58

and noise performance. These register settings do not impact the

AVDD3 power as much as Register 0x018 does. For frequencies

<500 MHz, it is recommended to use the default settings for

these registers. Table 10 shows the recommended values for the

buffer current control registers for various speed grades.

Register 0x11A is used when sampling in higher Nyquist zones

(>500 MHz for the AD9680-1000). This setting enables the ADC

sampling network to optimize the sampling and settling times

internal to the ADC for high frequency operation. For frequencies

greater than 500 MHz, it is recommended to operate the ADC core

at a 1.46 V full-scale setting irrespective of the speed grade. This

setting offers better SFDR without any significant penalty in SNR.

650MHz

750MHz

850MHz

1304.3 1408.3 1512.3 1616.3 1720.3 1824.3 1928.3

INPUT FREQUENCY (MHz)

Figure 118, Figure 119, and Figure 120 show the SFDR vs.

analog input frequency for various buffer settings for the

AD9680-1250. The recommended settings shown in Table 10

were used to take the data while changing the contents of

Register 0x018 only.

Figure 120. Buffer Current Sweeps, AD9680-1250 (SFDR vs. I_BUFF);

1300 MHz < f_IN< 2000 MHz; Front-End Network Shown in Figure 115

Figure 121, Figure 122, and Figure 123 show the SFDR vs.

analog input frequency for various buffer settings for the

AD9680-1000. The recommended settings shown in Table 10

were used to take the data while changing the contents of

Register 0x018 only.

85

250MHz

350MHz

450MHz

550MHz

80

75

70

65

60

90

85

80

75

70

65

60

10.3 147.3 212.3 290.3 355.3 433.3 511.3 589.3 667.3

INPUT FREQUENCY (MHz)

1.5×

3.0×

4.5×

55

50

Figure 118. Buffer Current Sweeps, AD9680-1250 (SFDR vs. I_BUFF);

f_IN< 500 MHz; Front-End Network Shown in Figure 115

10

60

110 160 210 260 310 360 410 460

ANALOG INPUT FREQUENCY (MHz)

80

75

70

65

Figure 121. Buffer Current Sweeps, AD9680-1000 (SFDR vs. I_BUFF);

f_IN< 500 MHz; Front-End Network Shown in Figure 115

85

4.0×

5.0×

6.0×

80

75

70

65

60

55

50

45

40

60

350MHz

450MHz

550MHz

650MHz

55

602.3 680.3 758.3 836.3 914.3 992.3 1070.3 1148.3 1226.3

INPUT FREQUENCY (MHz)

Figure 119. Buffer Current Sweeps, AD9680-1250 (SFDR vs. I_BUFF);

600 MHz < f_IN< 1300 MHz; Front-End Network Shown in Figure 115

503.4

677.6

851.9

1026.2

1200.5

1374.8

ANALOG INPUT FREQUENCY (MHz)

Figure 122. Buffer Current Sweeps, AD9680-1000 (SFDR vs. I_BUFF);

500 MHz < f_IN< 1500 MHz; Front-End Network Shown in Figure 115

Rev. C | Page 37 of 97

AD9680

Data Sheet

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

4.5×

5.5×

6.5×

7.5×

8.5×

1.5×

2.0×

3.0×

4.5×

40

1513.4

1607.4

1701.5

1795.6

1889.8

ANALOG INPUT FREQUENCY (MHz)

Figure 123. Buffer Current Sweeps, AD9680-1000 (SFDR vs. I_BUFF);

1500 MHz < f_IN< 2000 MHz; Front-End Network Shown in Figure 115

ANALOG INPUT FREQUENCY (MHz)

Figure 125. Buffer Current Sweeps, AD9680-820 (SFDR vs. I_BUFF);

f_IN< 500 MHz; Front-End Network Shown in Figure 115

In certain high frequency applications, the SFDR can be improved

by reducing the full-scale setting, as shown in Table 10. At high

frequencies, the performance of the ADC core is limited by jitter.

The SFDR can be improved by backing off of the full scale level.

Figure 124 shows the SFDR and SNR vs. full-scale input level at

different high frequencies for the AD9680-1000.

85

80

75

70

65

80

75

70

65

60

55

80

75

70

65

60

55

1.65GHz

1.52GHz

1.76GHz

1.95GHz

1.9GHz

3.5×

4.5×

5.5×

6.5×

60

55

7.5×

50

1.52GHz

1.65GHz

1.76GHz

1.9GHz

ANALOG INPUT FREQUENCY (MHz)

Figure 126. Buffer Current Sweeps, AD9680-820 (SFDR vs. I_BUFF);

500 MHz < f_IN< 1000 MHz; Front-End Network Shown in Figure 115

1.95GHz

80

–3

–2

–1

INPUT LEVEL (dBFS)

6.5×

7.5×

8.5×

75

Figure 124. SNR/SFDR vs. Analog Input Level vs. Input Frequencies, AD9680-1000

Figure 125, Figure 126, and Figure 127 show the SFDR vs.

analog input frequency for various buffer settings for the

AD9680-820. The recommended settings shown in Table 10

were used to take the data while changing the contents of

Register 0x018 only.

70

65

60

55

50

ANALOG INPUT FREQUENCY (MHz)

Figure 127. Buffer Current Sweeps, AD9680-820 (SFDR vs. I_BUFF);

1000 MHz < f_IN< 2000 MHz; Front-End Network Shown in Figure 115

Rev. C | Page 38 of 97

Data Sheet

AD9680

95

90

85

80

75

70

65

Figure 128, Figure 129, and Figure 130 show the SFDR vs.

analog input frequency for various buffer settings for the

AD9680-500. The recommended settings shown in Table 10

were used to take the data while changing the contents of

Register 0x018 only.

4.0×

5.0×

6.0×

7.0×

8.0×

100

90

80

70

60

450.3

480.3

510.3

515.3

610.3

765.3

810.3

985.3

ANALOG INPUT FREQUENCY (MHz)

50

Figure 129. Buffer Current Sweeps, AD9680-500 (SFDR vs. I_BUFF);

450 MHz < f_IN< 1000 MHz; Front-End Network Shown in Figure 115

1.0×

40

1.5×

2.0×

3.0×

4.5×

80

75

70

65

60

55

50

30

10.3

95.3 150.3 180.3 240.3 301.3 340.7 390.3 450.3

ANALOG INPUT FREQUENCY (MHz)

Figure 128. Buffer Current Sweeps, AD9680-500 (SFDR vs. I_BUFF);

f_IN< 500 MHz; Front-End Network Shown in Figure 115 Buffer Control 1

(0x018) = 1.0×, 1.5×, 2.0×, 3.0×, or 4.5×

4.0×

5.0×

45

6.0×

7.0×

8.0×

40

1010.3

1205.3

1410.3

1600.3

1810.3

1950.3

ANALOG INPUT FREQUENCY (MHz)

Figure 130. Buffer Current Sweeps, AD9680-500 (SFDR vs. I_BUFF);

1 GHz < f_IN< 2 GHz; Front-End Network Shown in Figure 115

Rev. C | Page 39 of 97

AD9680

Data Sheet

Table 10. Recommended Register Settings for SFDR Optimization at Different Input Frequencies

Buffer

Control 2

Buffer

Control 3

Buffer

Control 4

Buffer

Control 1

(0x018)—

Buffer

Control 5

(0x935)—

Low

Input

Full-

Scale

Input

Full-Scale

Range

(0x019)— (0x01A)— (0x11A)—

Buffer

Bias

Buffer

Bias

High

Frequency

Input

Current

Frequency

Control

Termination

Capacitance

(0x934)

Setting

(0x025)

(0x030)

(0x016)¹

Product

Frequency

Control

Setting

AD9680-

500

DC to

250 MHz

250 MHz to 0x70

500 MHz (4.5×)

500 MHz to 0x80

1 GHz

1 GHz to

2 GHz

0x20

(2.0×)

0x60

0x0A

0x00 (off)

0x20 (on)

0x00 (off)

N/A³

0x04 (on)

0x00 (off)

0x04 (on)

0x00 (off)

0x04 (on)

0x00 (off)

0x04 (on)

0x00 (off)

0x0C

(2.06 V p-p)

0x0C

(2.06 V p-p)

0x08

(1.46 V p-p)

0x08

(1.46 V p-p)

0x04

0x18

0x14

0x18

0x0C/0x1C/…

0x0E/0x1E/…

0x1F

(Setting 3) (Setting 3)

0x60 0x0A

(Setting 3) (Setting 3)

0x40 0x08

(Setting 1) (Setting 1)

0x40 0x08

(Setting 1) (Setting 1)

0x40 0x09

(Setting 1) (Setting 2)

0x40 0x09

(Setting 1) (Setting 2)

0x40 0x08

(Setting 1) (Setting 1)

0x40 0x08

(Setting 1) (Setting 1)

0x50 0x09

(Setting 2) (Setting 2)

0x50 0x09

(Setting 2) (Setting 2)

0x60 0x09

(Setting 3) (Setting 2)

0x70 0x09

(Setting 4) (Setting 2)

0x50 0x09

(Setting 2) (Setting 2)

0x50 0x09

(Setting 2) (Setting 2)

0x1F

0x1F or 0x00²

0x1F or 0x00¹

0x1F

(5.0×)

0xF0

(8.5×)

AD9680-

820

DC to

200 MHz

DC to

410 MHz

500 MHz to 0x80

1 GHz

1 GHz to

2 GHz

0x10

(1.5×)

0x40

(3.0×)

0x0A

(1.70 V p-p)

0x0A

(1.70 V p-p)

0x08

(1.46 V p-p)

0x08

(1.46 V p-p)

0x1F

0x1F or 0x00²

0x1F or 0x00¹

0x1F

(5.0×)

0xF0

(8.5×)

AD9680-

1000

DC to

150 MHz

0x10

(1.5×)

0x0A

(1.70 V p-p)

DC to

500 MHz

0x40

(3.0×)

0x0A

(1.70 V p-p)

0x1F

500 MHz to 0xA0

1 GHz

0x08

(1.46 V p-p)

0x1F or 0x00¹

0x1F

(6.0×)

1 GHz to

2 GHz

0xD0

(7.5×)

0x08

(1.46 V p-p)

AD9680-

1250

DC to

625 MHz

0x50

(3.5×)

0xA0

(6.0×)

0x0A

(1.58 V p-p)

0x08

(1.46 V p-p)

>625 MHz

0x1F or 0x00¹

¹The input termination can be changed to accommodate the application with little or no impact to ac performance.

²The input capacitance can be set to 1.5 pF to achieve wider input bandwidth but results in slightly lower ac performance.

³N/A means not applicable.

Rev. C | Page 40 of 97

Data Sheet

AD9680

Absolute Maximum Input Swing

the reference voltage. For more information on adjusting the

full-scale level of the AD9680, refer to the Memory Map Register

Table section.

The absolute maximum input swing allowed at the inputs of the

AD9680 is 4.3 V p-p differential. Signals operating near or at

this level can cause permanent damage to the ADC.

The use of an external reference may be necessary, in some

applications, to enhance the gain accuracy of the ADC or to

improve thermal drift characteristics. Figure 132 shows the

typical drift characteristics of the internal 1.0 V reference.

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9680. This internal 1.0 V reference is used to set the full-

scale input range of the ADC. The full-scale input range can

be adjusted via the ADC Function Register 0x025. For more

information on adjusting the input swing, see Table 36. Figure 131

shows the block diagram of the internal 1.0 V reference controls.

1.0010

1.0009

1.0008

1.0007

1.0006

1.0005

1.0004

1.0003

1.0002

1.0001

1.0000

0.9999

0.9998

VIN+A/

VIN+B

VIN–A/

VIN–B

ADC

INTERNAL

V_1P0

GENERATOR

CORE

FULL-SCALE

VOLTAGE

ADJUST

INPUT FULL-SCALE

RANGE ADJUST

SPI REGISTER

(0x025, 0x02,

AND 0x024)

–50

0

25

90

V_1P0

TEMPERATURE (°C)

Figure 132. Typical V_1P0 Drift

V_1P0 PIN

CONTROL SPI

REGISTER

The external reference must be a stable 1.0 V reference. The

ADR130 is a good option for providing the 1.0 V reference.

Figure 133 shows how the ADR130 can be used to provide the

external 1.0 V reference to the AD9680. The grayed out areas

show unused blocks within the AD9680 while using the

ADR130 to provide the external reference.

(0x025, 0x02,

AND 0x024)

Figure 131. Internal Reference Configuration and Controls

The SPI Register 0x024 enables the user to either use this internal

1.0 V reference, or to provide an external 1.0 V reference. When

using an external voltage reference, provide a 1.0 V reference.

The full-scale adjustment is made using the SPI, irrespective of

INTERNAL

V_1P0

GENERATOR

FULL-SCALE

VOLTAGE

ADJUST

ADR130

1

2

3

6

5

4

NC

GND SET

V_1P0

0.1µF

INPUT

V

OUT

IN

0.1µF

FULL-SCALE

CONTROL

Figure 133. External Reference Using ADR130

Rev. C | Page 41 of 97

AD9680

Data Sheet

Input Clock Divider

CLOCK INPUT CONSIDERATIONS

The AD9680 contains an input clock divider with the ability to

divide the Nyquist input clock by 1, 2, 4, and 8. The divider

ratios can be selected using Register 0x10B. This is shown in

Figure 137.

For optimum performance, drive the AD9680 sample clock

inputs (CLK+ and CLK−) with a differential signal. This signal

is typically ac-coupled to the CLK+ and CLK− pins via a

transformer or clock drivers. These pins are biased internally

and require no additional biasing.

The maximum frequency at the CLK inputs is 4 GHz. This is

the limit of the divider. In applications where the clock input is

a multiple of the sample clock, care must be taken to program

the appropriate divider ratio into the clock divider before applying

the clock signal. This ensures that the current transients during

device startup are controlled.

Figure 134 shows a preferred method for clocking the AD9680.

The low jitter clock source is converted from a single-ended

signal to a differential signal using an RF transformer.

0.1µF

1:1Z

CLK+

ADC

CLK–

CLOCK

INPUT

CLK+

100Ω

50Ω

CLK–

÷2

÷4

÷8

0.1µF

Figure 134. Transformer-Coupled Differential Clock

Another option is to ac couple a differential CML or LVDS

REG 0x10B

signal to the sample clock input pins, as shown in Figure 135

and Figure 136.

Figure 137. Clock Divider Circuit

The AD9680 clock divider can be synchronized using the

external SYSREF input. A valid SYSREF causes the clock

divider to reset to a programmable state. This synchronization

feature allows multiple devices to have their clock dividers

aligned to guarantee simultaneous input sampling. See the

Multichip Synchronization section for more information.

3.3V

71Ω

33Ω

10pF

33Ω

0.1µF

Z0 = 50Ω

CLK+

ADC

CLK–

0.1µF

Input Clock Divider ½ Period Delay Adjust

Z0 = 50Ω

Figure 135. Differential CML Sample Clock

The input clock divider inside the AD9680 provides phase delay

in increments of ½ the input clock cycle. Register 0x10C can be

programmed to enable this delay independently for each channel.

Changing this register does not affect the stability of the

JESD204B link.

0.1µF

100Ω

0.1µF

CLOCK INPUT

CLK+

LVDS

CLK+

ADC

DRIVER

CLK–

Clock Fine Delay Adjust

1

50Ω

The AD9680 sampling edge instant can be adjusted by writing to

Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117

enables the feature, and Bits[7:0] of Register 0x118 set the value

of the delay. This value can be programmed individually for

each channel. The clock delay can be adjusted from −151.7 ps

to +150 ps in ~1.7 ps increments. The clock delay adjust takes

effect immediately when it is enabled via SPI writes. Enabling

the clock fine delay adjust in Register 0x117 causes a datapath

reset. However, the contents of Register 0x118 can be changed

without affecting the stability of the JESD204B link.

1

50Ω RESISTORS ARE OPTIONAL.

Figure 136. Differential LVDS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. In applications where the clock duty cycle cannot

be guaranteed to be 50%, a higher multiple frequency clock can be

supplied to the device. The AD9680 can be clocked at 2 GHz with

the internal clock divider set to 2. The output of the divider offers

a 50% duty cycle, high slew rate (fast edge) clock signal to the

internal ADC. See the Memory Map section for more details on

using this feature.

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR at a given input

frequency (f_A) due only to aperture jitter (t_J) can be calculated by

SNR = 20 × log 10 (2 × π × f_A× t_J)

In this equation, the rms aperture jitter represents the root

mean square of all jitter sources, including the clock input,

analog input signal, and ADC aperture jitter specifications.

Rev. C | Page 42 of 97

Data Sheet

AD9680

IF undersampling applications are particularly sensitive to jitter

(see Figure 138).

Power-Down/Standby Mode

The AD9680 has a PDWN/STBY pin that can be used to

configure the device in power-down or standby mode. The

default operation is PDWN. The PDWN/STBY pin is a logic

high pin. When in power-down mode, the JESD204B link is

disrupted. The power-down option can also be set via

Register 0x03F and Register 0x040.

130

12.5f_S

120

110

100

90

25f_S

50f_S

100f_S

200f_S

400f_S

800f_S

In standby mode, the JESD204B link is not disrupted and

transmits zeros for all converter samples. This can be changed

using Register 0x571, Bit 7 to select /K/ characters.

80

70

60

Temperature Diode

50

The AD9680 contains a diode-based temperature sensor for

measuring the temperature of the die. This diode can output a

voltage and serve as a coarse temperature sensor to monitor the

internal die temperature.

40

30

10

100

1000

10000

ANALOG INPUT FREQUENCY (MHz)

Figure 138. Ideal SNR vs. Input Frequency and Jitter

The temperature diode voltage can be output to the FD_A pin

using the SPI. Use Register 0x028, Bit 0 to enable or disable the

diode. Register 0x028 is a local register. Channel A must be

selected in the device index register (0x008) to enable the

temperature diode readout. Configure the FD_A pin to output

the diode voltage by programming Register 0x040[2:0]. See

Table 36 for more information.

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9680. Separate

power supplies for clock drivers from the ADC output driver

supplies to avoid modulating the clock signal with digital noise.

If the clock is generated from another type of source (by gating,

dividing, or other methods), retime the clock by the original clock

at the last step. Refer to the AN-501 Application Note and the

AN-756 Application Note for more in-depth information about

jitter performance as it relates to ADCs.

The voltage response of the temperature diode (SPIVDD =

1.8 V) is shown in Figure 140.

0.90

Figure 139 shows the estimated SNR of the AD9680-1000 across

input frequency for different clock induced jitter values. The

SNR can be estimated by using the following equation:

0.85

0.80

0.75

0.70

0.65

0.60

−SNR





_^

−SNR

10

JITTER









ADC



10





SNR (dBFS) =10log 10

+10^













70

65

60

–55 –45 –35 –25 –15 –5

5

15 25 35 45 55 65 75 85 95 105 115 125

TEMPERATURE (°C)

Figure 140. Temperature Diode Voltage vs. Temperature

25f

50f

75f

100f

125f

150f

175f

200f

55

50

45

s

10

100

1K

10K

INPUT FREQUENCY (MHz)

Figure 139. Estimated SNR Degradation for the AD9680-1000 vs.

Input Frequency and RMS Jitter

Rev. C | Page 43 of 97

AD9680

Data Sheet

ADC OVERRANGE AND FAST DETECT

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped.

The standard overrange bit in the JESD204B outputs provides

information on the state of the analog input that is of limited

usefulness. Therefore, it is helpful to have a programmable

threshold below full scale that allows time to reduce the gain

before the clip actually occurs. In addition, because input

signals can have significant slew rates, the latency of this

function is of major concern. Highly pipelined converters can

have significant latency. The AD9680 contains fast detect

circuitry for individual channels to monitor the threshold and

assert the FD_A and FD_B pins.

The operation of the upper threshold and lower threshold

registers, along with the dwell time registers, is shown in

Figure 141.

The FD indicator is asserted if the input magnitude exceeds the

value programmed in the fast detect upper threshold registers,

located at Register 0x247 and Register 0x248. The selected

threshold register is compared with the signal magnitude at the

output of the ADC. The fast upper threshold detection has a

latency of 28 clock cycles (maximum). The approximate upper

threshold magnitude is defined by

Upper Threshold Magnitude (dBFS)

= 20 log (Threshold Magnitude/2¹³)

ADC OVERRANGE

The FD indicators are not cleared until the signal drops below

the lower threshold for the programmed dwell time. The lower

threshold is programmed in the fast detect lower threshold

registers, located at Register 0x249 and Register 0x24A. The fast

detect lower threshold register is a 13-bit register that is compared

with the signal magnitude at the output of the ADC. This

comparison is subject to the ADC pipeline latency, but is

accurate in terms of converter resolution. The lower threshold

magnitude is defined by

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange indicator can

be embedded within the JESD204B link as a control bit (when

CSB > 0). The latency of this overrange indicator matches the

sample latency.

The AD9680 also records any overrange condition in any of the

eight virtual converters. For more information on the virtual

converters, refer to Figure 146. The overrange status of each virtual

converter is registered as a sticky bit in Register 0x563. The

contents of Register 0x563 can be cleared using Register 0x562,

by toggling the bits corresponding to the virtual converter to set

and reset position.

Lower Threshold Magnitude (dBFS)

= 20 log (Threshold Magnitude/2¹³)

For example, to set an upper threshold of −6 dBFS, write 0xFFF

to Register 0x247 and Register 0x248. To set a lower threshold

of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A.

FAST THRESHOLD DETECTION (FD_A AND FD_B)

The FD bit is immediately set whenever the absolute value of

the input signal exceeds the programmable upper threshold

level. The FD bit is only cleared when the absolute value of the

input signal drops below the lower threshold level for greater

than the programmable dwell time. This feature provides

hysteresis and prevents the FD bit from excessively toggling.

The dwell time can be programmed from 1 to 65,535 sample

clock cycles by placing the desired value in the fast detect dwell

time registers, located at Register 0x24B and Register 0x24C.

See the Memory Map section (Register 0x040, and Register 0x245

to Register 0x24C in Table 36) for more details.

UPPER THRESHOLD

DWELL TIME

TIMER RESET BY

RISE ABOVE

LOWER

THRESHOLD

LOWER THRESHOLD

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE

LOWER THRESHOLD

DWELL TIME

FD_A OR FD_B

Figure 141. Threshold Settings for FD_A and FD_B Signals

Rev. C | Page 44 of 97

Data Sheet

AD9680

SIGNAL MONITOR

The signal monitor block provides additional information about

the signal being digitized by the ADC. The signal monitor

computes the peak magnitude of the digitized signal. This

information can be used to drive an AGC loop to optimize the

range of the ADC in the presence of real-world signals.

converter output samples. The peak magnitude can be derived

by using the following equation:

Peak Magnitude (dBFS) = 20log(Peak Detector Value/2¹³)

The magnitude of the input port signal is monitored over a

programmable time period, which is determined by the signal

monitor period register (SMPR). The peak detector function is

enabled by setting Bit 1 of Register 0x270 in the signal monitor

control register. The 24-bit SMPR must be programmed before

activating this mode.

The results of the signal monitor block can be obtained either

by reading back the internal values from the SPI port or by

embedding the signal monitoring information into the

JESD204B interface as special control bits. A global, 24-bit

programmable period controls the duration of the

measurement. Figure 142 shows the simplified block diagram

of the signal monitor block.

After enabling peak detection mode, the value in the SMPR is

loaded into a monitor period timer, which decrements at the

decimated clock rate. The magnitude of the input signal is

compared with the value in the internal magnitude storage

register (not accessible to the user), and the greater of the two

is updated as the current peak level. The initial value of the

magnitude storage register is set to the current ADC input signal

magnitude. This comparison continues until the monitor period

timer reaches a count of 1.

SIGNAL MONITOR

FROM

MEMORY

MAP

PERIOD REGISTER

(SMPR)

DOWN

COUNTER

IS

COUNT = 1?

0x271, 0x272, 0x273

LOAD

CLEAR

LOAD

MAGNITUDE

STORAGE

REGISTER

SIGNAL

MONITOR

HOLDING

REGISTER

TO SPORT OVER

JESD204B AND

MEMORY MAP

FROM

INPUT

LOAD

When the monitor period timer reaches a count of 1, the 13-bit

peak level value is transferred to the signal monitor holding

register, which can be read through the memory map or output

through the SPORT over the JESD204B interface. The monitor

period timer is reloaded with the value in the SMPR, and the

countdown restarts. In addition, the magnitude of the first

input sample is updated in the magnitude storage register, and

the comparison and update procedure, as explained previously,

continues.

COMPARE

A > B

Figure 142. Signal Monitor Block

The peak detector captures the largest signal within the

observation period. The detector only observes the magnitude

of the signal. The resolution of the peak detector is a 13-bit

value, and the observation period is 24 bits and represents

Rev. C | Page 45 of 97

AD9680

Data Sheet

is to be inserted (CS = 1), only the most significant control bit is

used (see Example Configuration 1 and Example Configuration 2

in Figure 143). To select the SPORT over JESD204B option,

program Register 0x559, Register 0x55A, and Register 0x58F.

See Table 36 for more information on setting these bits.

SPORT OVER JESD204B

The signal monitor data can also be serialized and sent over the

JESD204B interface as control bits. These control bits must be

deserialized from the samples to reconstruct the statistical data.

The signal control monitor function is enabled by setting Bits[1:0]

of Register 0x279 and Bit 1 of Register 0x27A. Figure 143 shows

two different example configurations for the signal monitor

control bit locations inside the JESD204B samples. A maximum

of three control bits can be inserted into the JESD204B samples;

however, only one control bit is required for the signal monitor.

Control bits are inserted from MSB to LSB. If only one control bit

Figure 144 shows the 25-bit frame data that encapsulates the

peak detector value. The frame data is transmitted MSB first

with five 5-bit subframes. Each subframe contains a start bit

that can be used by a receiver to validate the deserialized data.

Figure 145 shows the SPORT over JESD204B signal monitor

data with a monitor period timer set to 80 samples.

16-BIT JESD204B SAMPLE SIZE (N' = 16)

1-BIT

CONTROL

BIT

15-BIT CONVERTER RESOLUTION (N = 15)

(CS = 1)

EXAMPLE

CONFIGURATION 1

(N' = 16, N = 15, CS = 1)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CTRL

[BIT 2]

X

S[14] S[13] S[12] S[11] S[10]

S[9]

X

S[8]

X

S[7]

X

S[6]

X

S[5]

X

S[4]

X

S[3]

X

S[2]

X

S[1]

X

S[0]

X

SERIALIZED SIGNAL MONITOR

FRAME DATA

16-BIT JESD204B SAMPLE SIZE (N' = 16)

14-BIT CONVERTER RESOLUTION (N = 14)

1

CONTROL

BIT

(CS = 1)

1 TAIL

BIT

EXAMPLE

CONFIGURATION 2

(N' = 16, N = 14, CS = 1)

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

CTRL

[BIT 2]

X

S[13] S[12] S[11] S[10]

S[9]

X

S[8]

X

S[7]

X

S[6]

X

S[5]

X

S[4]

X

S[3]

X

S[2]

X

S[1]

X

S[0]

X

TAIL

X

SERIALIZED SIGNAL MONITOR

FRAME DATA

Figure 143. Signal Monitor Control Bit Locations

5-BIT SUB-FRAMES

5-BIT IDLE

IDLE IDLE IDLE IDLE IDLE

SUB-FRAME

1

(OPTIONAL)

5-BIT IDENTIFIER START ID[3]

ID[2]

0

ID[1]

0

ID[0]

1

0

SUB-FRAME

5-BIT DATA

MSB

START

0

P[12]

P[11]

P[7]

P[10]

P[6]

P[9]

P5]

SUB-FRAME

25-BIT

FRAME

5-BIT DATA

SUB-FRAME

START

0

P[8]

P[4]

P[0]

5-BIT DATA

SUB-FRAME

START

0

P[3]

0

P[2]

0

P1]

0

5-BIT DATA

LSB

SUB-FRAME

START

0

P[] = PEAK MAGNITUDE VALUE

Figure 144. SPORT over JESD204B Signal Monitor Frame Data

Rev. C | Page 46 of 97

Data Sheet

AD9680

SMPR = 80 SAMPLES (0x271 = 0x50; 0x272 = 0x00; 0x273 = 0x00)

80 SAMPLE PERIOD

PAYLOAD #3

25-BIT FRAME (N)

DATA

MSB

DATA

LSB

IDENT.

DATA DATA

IDLE

80 SAMPLE PERIOD

PAYLOAD #3

25-BIT FRAME (N + 1)

DATA

LSB

DATA DATA

MSB

IDLE

80 SAMPLE PERIOD

PAYLOAD #3

25-BIT FRAME (N + 2)

DATA

LSB

DATA DATA

MSB

IDLE

Figure 145. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples

Rev. C | Page 47 of 97

AD9680

Data Sheet

DIGITAL DOWNCONVERTER (DDC)

The AD9680 includes four digital downconverters (DDC 0 to

DDC 3) that provide filtering and reduce the output data rate.

This digital processing section includes an NCO, a half-band

decimating filter, an FIR filter, a gain stage, and a complex-real

conversion stage. Each of these processing blocks has control lines

that allow it to be independently enabled and disabled to provide

the desired processing function. The digital downconverter can

be configured to output either real data or complex output data.

The Chip Q ignore bit (Bit 5) in the chip application mode

register (Register 0x200) controls the chip output muxing of all

the DDC channels. When all DDC channels use real outputs,

this bit must be set high to ignore all DDC Q output ports.

When any of the DDC channels are set to use complex I/Q

outputs, the user must clear this bit to use both DDC Output

Port I and DDC Output Port Q. For more information, see

Figure 154.

The DDCs output a 16-bit stream. To enable this operation, the

converter number of bits, N, is set to a default value of 16, even

though the analog core only outputs 14 bits. In full bandwidth

operation, the ADC outputs are the 14-bit word followed by

two zeros, unless the tail bits are enabled.

DDC GENERAL DESCRIPTION

The four DDC blocks are used to extract a portion of the full

digital spectrum captured by the ADC(s). They are intended for

IF sampling or oversampled baseband radios requiring wide

bandwidth input signals.

DDC I/Q INPUT SELECTION

Each DDC block contains the following signal processing stages.

The AD9680 has two ADC channels and four DDC channels.

Each DDC channel has two input ports that can be paired to

support both real or complex inputs through the I/Q crossbar

mux. For real signals, both DDC input ports must select the

same ADC channel (for example, DDC Input Port I = ADC

Channel A, and Input Port Q = ADC Channel A). For complex

signals, each DDC input port must select different ADC

channels (for example, DDC Input Port I = ADC Channel A,

and Input Port Q = ADC Channel B).

Frequency Translation Stage (Optional)

The frequency translation stage consists of a 12-bit complex NCO

and quadrature mixers that can be used for frequency translation

of both real or complex input signals. This stage shifts a portion

of the available digital spectrum down to baseband.

Filtering Stage

After shifting down to baseband, the filtering stage decimates

the frequency spectrum using a chain of up to four half-band

low-pass filters for rate conversion. The decimation process

lowers the output data rate, which in turn reduces the output

interface rate.

The inputs to each DDC are controlled by the DDC input

selection registers (Register 0x311, Register 0x331, Register 0x351,

and Register 0x371). See Table 36 for information on how to

configure the DDCs.

Gain Stage (Optional)

Due to losses associated with mixing a real input signal down to

baseband, the gain stage compensates by adding an additional

0 dB or 6 dB of gain.

DDC I/Q OUTPUT SELECTION

Each DDC channel has two output ports that can be paired to

support both real or complex outputs. For real output signals,

only the DDC Output Port I is used (the DDC Output Port Q is

invalid). For complex I/Q output signals, both DDC Output

Port I and DDC Output Port Q are used.

Complex to Real Conversion Stage (Optional)

When real outputs are necessary, the complex to real conversion

stage converts the complex outputs back to real by performing

an f_S/4 mixing operation plus a filter to remove the complex

component of the signal.

The I/Q outputs to each DDC channel are controlled by the

DDC complex to real enable bit (Bit 3) in the DDC control

registers (Register 0x310, Register 0x330, Register 0x350, and

Register 0x370).

Figure 146 shows the detailed block diagram of the DDCs

implemented in the AD9680.

Rev. C | Page 48 of 97

Data Sheet

AD9680

DDC 0

DDC 1

DDC 2

DDC 3

REAL/I

I

REAL/I

CONVERTER 0

NCO

+

MIXER

(OPTIONAL)

REAL/Q

Q

Q CONVERTER 1

ADC

REAL/I

SYSREF±

I

SAMPLING

AT f_S

REAL/I

CONVERTER 2

NCO

+

MIXER

(OPTIONAL)

REAL/Q

Q

Q CONVERTER 3

SYSREF±

I

REAL/I

CONVERTER 4

NCO

+

MIXER

(OPTIONAL)

REAL/Q

Q

Q CONVERTER 5

ADC

SAMPLING

AT f_S

REAL/I

SYSREF±

I

REAL/I

CONVERTER 6

NCO

+

MIXER

(OPTIONAL)

REAL/Q

Q

Q CONVERTER 7

SYSREF±

SYSREF

SYNCHRONIZATION

CONTROL CIRCUITS

Figure 146. DDC Detailed Block Diagram

Figure 147 shows an example usage of one of the four DDC

blocks with a real input signal and four half-band filters (HB4,

HB3, HB2, and HB1). It shows both complex (decimate by 16)

and real (decimate by 8) output options.

the chip decimation ratio sample rate. Whenever the NCO

frequency is set or changed, the DDC soft reset must be issued.

If the DDC soft reset is not issued, the output may potentially

show amplitude variations.

When DDCs have different decimation ratios, the chip

decimation ratio (Register 0x201) must be set to the lowest

decimation ratio of all the DDC blocks. In this scenario,

samples of higher decimation ratio DDCs are repeated to match

Table 11, Table 12, Table 13, Table 14, and Table 15 show the

DDC samples when the chip decimation ratio is set to 1, 2, 4, 8,

or 16, respectively.

Rev. C | Page 49 of 97

AD9680

Data Sheet

ADC

SAMPLING

AT f_S

ADC

REAL

REAL INPUT—SAMPLED AT f_S

BANDWIDTH OF

INTEREST

BANDWIDTH OF

INTEREST IMAGE

–

f_S/32

DC

–f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

FREQUENCY TRANSLATION STAGE (OPTIONAL)

I

DIGITAL MIXER + NCO FORf_S/3 TUNING, THE FREQUENCY

TUNING WORD = ROUND ((f_S/3)/f_S× 4096) = +1365 (0x555)

NCO TUNES CENTER OF

BANDWIDTH OF INTEREST

TO BASEBAND

cos(ωt)

REAL

12-BIT

NCO

90°

0°

–sin(ωt)

Q

BANDWIDTH OF

INTEREST IMAGE

(–6dB LOSS DUE TO

NCO + MIXER)

DIGITAL FILTER

RESPONSE

BANDWIDTH OF INTEREST

(–6dB LOSS DUE TO

NCO + MIXER)

–

f_S/32

DC

–

f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

FILTERING STAGE

4 DIGITAL HALF-BAND FILTERS

(HB4 + HB3 + HB2 + HB1)

HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

HALF-

BAND

I

FILTER

2

HB4 FIR

HB3 FIR

HB2 FIR

HB1 FIR

HALF-

BAND

FILTER

HALF-

BAND

FILTER

HALF-

BAND

FILTER

HALF-

BAND

FILTER

Q

2

6dB GAIN TO

COMPENSATE FOR

NCO + MIXER LOSS

COMPLEX (I/Q) OUTPUTS

GAIN STAGE (OPTIONAL)

0dB OR 6dB GAIN

DECIMATE BY 16

DIGITAL FILTER

RESPONSE

I

2

+6dB

GAIN STAGE (OPTIONAL)

0dB OR 6dB GAIN

Q

2

+6dB

–

f_S/32

–

f_S/32

DC

COMPLEX TO REAL

DC

–

f_S/8

–

f_S/16

f_S/8

–

f_S/16

CONVERSION STAGE (OPTIONAL)

DOWNSAMPLE BY 2

f_S/4 MIXING + COMPLEX FILTER TO REMOVE Q

I

+6dB

REAL (I) OUTPUTS

DECIMATE BY 8

COMPLEX

TO

REAL

REAL/I

Q

6dB GAIN TO

COMPENSATE FOR

NCO + MIXER LOSS

–

f_S/32

DC

–

f_S/8

–

f_S/16

f_S/8

Figure 147. DDC Theory of Operation Example (Real Input—Decimate by 16)

Rev. C | Page 50 of 97

Data Sheet

AD9680

Table 11. DDC Samples, Chip Decimation Ratio = 1

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR +

HB3 FIR +

HB2 FIR +

HB1 FIR

HB3 FIR +

HB2 FIR +

HB1 FIR

HB3 FIR +

HB2 FIR +

HB1 FIR

HB3 FIR +

HB2 FIR +

HB1 FIR

HB2 FIR +

HB1 FIR

HB2 FIR +

HB1 FIR

(DCM¹= 1)

(DCM¹= 2)

(DCM¹= 4)

(DCM¹= 8)

(DCM¹= 2)

(DCM¹= 4)

(DCM¹= 8)

(DCM¹= 16)

N

N + 1

N + 2

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 1

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 8

N + 9

N + 8

N + 9

N + 10

N + 11

N + 10

N + 11

N + 12

N + 13

N + 12

N + 13

N + 14

N + 15

N + 14

N + 15

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 1

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 8

N + 9

N + 8

N + 9

N + 10

N + 11

N + 10

N + 11

N + 12

N + 13

N + 12

N + 13

N + 14

N + 15

N + 14

N + 15

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 6

N + 7

N + 6

N + 7

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 6

N + 7

N + 6

N + 7

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 16

N + 17

N + 18

N + 19

N + 20

N + 21

N + 22

N + 23

N + 24

N + 25

N + 26

N + 27

N + 28

N + 29

N + 30

N + 31

N + 1

¹DCM means decimation.

Rev. C | Page 51 of 97

AD9680

Data Sheet

Table 12. DDC Samples, Chip Decimation Ratio = 2

Real (I) Output (Complex to Real Enabled)

HB4 FIR +

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR +

HB3 FIR +

HB2 FIR +

HB1 FIR

HB3 FIR +

HB2 FIR +

HB1 FIR

HB3 FIR +

HB2 FIR +

HB1 FIR

HB3 FIR +

HB2 FIR +

HB1 FIR

HB2 FIR +

HB1 FIR

HB2 FIR +

HB1 FIR

(DCM¹= 2)

(DCM¹= 4)

(DCM¹= 8)

(DCM¹= 2)

(DCM¹= 4)

(DCM¹= 8)

(DCM¹= 16)

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 1

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 4

N + 5

N + 4

N + 5

N + 6

N + 7

N + 6

N + 7

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 1

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 2

N + 3

N + 1

N

N + 1

N

N + 1

N

N + 1

N

N + 1

¹DCM means decimation.

Table 13. DDC Samples, Chip Decimation Ratio = 4

Real (I) Output (Complex to Real Enabled)

HB4 FIR + HB3 FIR +

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR + HB3 FIR +

HB2 FIR + HB1 FIR

(DCM¹= 16)

HB3 FIR + HB2 FIR +

HB2 FIR + HB1 FIR

(DCM¹= 4)

HB3 FIR + HB2 FIR +

HB1 FIR (DCM¹= 8)

HB1 FIR (DCM¹= 4)

(DCM¹= 8)

N

N + 1

N

N + 1

N

N + 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 1

N + 2

N + 3

N + 2

N + 3

N + 1

N + 2

N + 3

N + 2

N + 3

N + 1

N

N + 1

N

N + 1

¹DCM means decimation.

Table 14. DDC Samples, Chip Decimation Ratio = 8

Real (I) Output (Complex to Real Enabled)

Complex (I/Q) Outputs (Complex to Real Disabled)

HB3 FIR + HB2 FIR + HB1 FIR

HB4 FIR + HB3 FIR + HB2 FIR +

HB1 FIR (DCM¹= 16)

N

HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM¹= 8)

(DCM¹= 8)

N

N + 1

N

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 1

N + 2

N + 3

N + 2

N + 3

¹DCM means decimation.

Rev. C | Page 52 of 97

Data Sheet

AD9680

Table 15. DDC Samples, Chip Decimation Ratio = 16

Real (I) Output (Complex to Real Enabled)

HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM¹= 16)

Not applicable

Complex (I/Q) Outputs (Complex to Real Disabled)

HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM¹= 16)

N

Not applicable

N + 1

N + 2

N + 3

¹DCM means decimation.

If the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs decimate by 4), and DDC 1 is

set to use HB4 + HB3 + HB2 + HB1 filters (real outputs decimate by 8), then DDC 1 repeats its output data two times for every one

DDC 0 output. The resulting output samples are shown in Table 16.

Table 16. DDC Output Samples when Chip DCM¹= 4, DDC 0 DCM¹= 4 (Complex), and DDC 1 DCM¹= 8 (Real)

DDC 0

DDC 1

DDC Input Samples

N

Output Port I

Output Port Q

Output Port I

Output Port Q

Not applicable

I0 [N]

Q0 [N]

I1 [N]

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

I0 [N + 1]

I0 [N + 2]

I0 [N + 3]

Q0 [N + 1]

Q0 [N + 2]

Q0 [N + 3]

I1 [N + 1]

I1 [N]

Not applicable

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

I1 [N + 1]

¹DCM means decimation.

Rev. C | Page 53 of 97

AD9680

Data Sheet

FREQUENCY TRANSLATION

Variable IF Mode

FREQUENCY TRANSLATION GENERAL DESCRIPTION

NCO and mixers are enabled. NCO output frequency can be

used to digitally tune the IF frequency.

Frequency translation is accomplished by using a 12-bit

complex NCO along with a digital quadrature mixer. The

frequency translation translates either a real or complex input

signal from an intermediate frequency (IF) to a baseband

complex digital output (carrier frequency = 0 Hz).

0 Hz IF (ZIF) Mode

Mixers are bypassed and the NCO is disabled.

f_S/4 Hz IF Mode

The frequency translation stage of each DDC can be controlled

individually and supports four different IF modes using Bits[5:4] of

the DDC control registers (Register 0x310, Register 0x330,

Register 0x350, and Register 0x370). These IF modes are

Mixers and NCO are enabled in special down mixing by f_S/4

mode to save power.

Test Mode

Input samples are forced to 0.999 to positive full scale. NCO is

enabled. This test mode allows the NCOs to directly drive the

decimation filters.

•

Variable IF mode

0 Hz IF (ZIF) mode

f_S/4 Hz IF mode

Test mode

Figure 148 and Figure 149 show examples of the frequency

translation stage for both real and complex inputs.

NCO FREQUENCY TUNING WORD (FTW) SELECTION

12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096

I

cos(ωt)

ADC

SAMPLING

AT f_S

ADC + DIGITAL MIXER + NCO

REAL INPUT—SAMPLED AT f_S

REAL

12-BIT

NCO

90°

0°

COMPLEX

–sin(ωt)

Q

BANDWIDTH OF

INTEREST

BANDWIDTH OF

INTEREST IMAGE

–

f_S/32

DC

–f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

–6dB LOSS DUE TO

NCO + MIXER

12-BIT NCO FTW =

ROUND ((f_S/3)/f_S× 4096) = +1365 (0x555)

POSITIVE FTW VALUES

–f_S/32

f_S/32

DC

12-BIT NCO FTW =

ROUND ((f_S/3)/f_S× 4096) = –1365 (0xAAB)

NEGATIVE FTW VALUES

–f_S/32

f_S/32

DC

Figure 148. DDC NCO Frequency Tuning Word Selection—Real Inputs

Rev. C | Page 54 of 97

Data Sheet

AD9680

NCO FREQUENCY TUNING WORD (FTW) SELECTION

12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096

QUADRATURE MIXER

ADC

SAMPLING

AT f_S

I

+

I

–

I

Q

QUADRATURE ANALOG MIXER +

Q

2 ADCs + QUADRATURE DIGITAL

MIXER + NCO

12-BIT

NCO

REAL

90°

PHASE

90°

0°

COMPLEX

Q

COMPLEX INPUT—SAMPLED AT f_S

I

+

ADC

SAMPLING

AT f_S

Q

+

BANDWIDTH OF

INTEREST

IMAGE DUE TO

ANALOG I/Q

MISMATCH

–

f_S/32

f_S/16

–f_S/2

–f_S/3

–

f_S/4

–

f_S/8

–

f_S/16

f_S/8

f_S/4

f_S/3

f_S/2

DC

12-BIT NCO FTW =

ROUND ((f_S/3)/f_S× 4096) = +1365 (0x555)

POSITIVE FTW VALUES

–f_S/32

f_S/32

DC

Figure 149. DDC NCO Frequency Tuning Word Selection—Complex Inputs

Setting Up the NCO FTW and POW

DDC NCO PLUS MIXER LOSS AND SFDR

The NCO frequency value is given by the 12-bit twos

complement number entered in the NCO FTW. Frequencies

between −f_S/2 and f_S/2 (f_S/2 excluded) are represented using the

following frequency words:

When mixing a real input signal down to baseband, 6 dB of loss

is introduced in the signal due to filtering of the negative image.

An additional 0.05 dB of loss is introduced by the NCO. The

total loss of a real input signal mixed down to baseband is 6.05 dB.

For this reason, it is recommended that the user compensate for

this loss by enabling the additional 6 dB of gain in the gain stage

of the DDC to recenter the dynamic range of the signal within

the full scale of the output bits.

•

0x800 represents a frequency of –f_S/2.

0x000 represents dc (frequency is 0 Hz).

0x7FF represents a frequency of +f_S/2 – f_S/2¹².

The NCO frequency tuning word can be calculated using the

following equation:

When mixing a complex input signal down to baseband, the

maximum value each I/Q sample can reach is 1.414 × full scale

after it passes through the complex mixer. To avoid overrange

of the I/Q samples and to keep the data bitwidths aligned with

real mixing, 3.06 dB of loss (0.707 × full scale) is introduced in

the mixer for complex signals. An additional 0.05 dB of loss is

introduced by the NCO. The total loss of a complex input signal

mixed down to baseband is −3.11 dB.









Mod( f_C, f_S)

12



NCO _ FTW = round 2



f_S



where:

NCO_FTW is a 12-bit twos complement number representing

the NC O F T W.

f_Sis the AD9680 sampling frequency (clock rate) in Hz.

f_Cis the desired carrier frequency in Hz.

Mod( ) is a remainder function. For example, Mod(110,100) =

10, and for negative numbers, Mod(–32, 10) = –2.

round( ) is a rounding function. For example, round(3.6) = 4,

and for negative numbers, round(–3.4)= –3.

The worst case spurious signal from the NCO is greater than

102 dBc SFDR for all output frequencies.

NUMERICALLY CONTROLLED OSCILLATOR

The AD9680 has a 12-bit NCO for each DDC that enables the

frequency translation process. The NCO allows the input

spectrum to be tuned to dc, where it can be effectively filtered

by the subsequent filter blocks to prevent aliasing. The NCO

can be set up by providing a frequency tuning word (FTW) and

a phase offset word (POW).

Note that this equation applies to the aliasing of signals in the

digital domain (that is, aliasing introduced when digitizing

analog signals).

Rev. C | Page 55 of 97

AD9680

Data Sheet

For example, if the ADC sampling frequency (f_S) is 1250 MSPS

and the carrier frequency (f_C) is 416.667 MHz,

Two methods can be used to synchronize multiple PAWs within

the chip:

•

Using the SPI. The DDC NCO soft reset bit in the DDC

synchronization control register (Register 0x300, Bit 4)

can be used to reset all the PAWs in the chip. This is

accomplished by toggling the DDC NCO soft reset bit.

This method can only be used to synchronize DDC

channels within the same AD9680 chip.

Using the SYSREF pin. When the SYSREF pin is enabled

in the SYSREF control registers (Register 0x120 and

Register 0x121), and the DDC synchronization is enabled

in Bits[1:0] in the DDC synchronization control register

(Register 0x300), any subsequent SYSREF event resets all

the PAWs in the chip. This method can be used to synchronize

DDC channels within the same AD9680 chip, or DDC

channels within separate AD9680 chips.

Mod(416.667,1250











NCO _ FTW = round 2¹²

=1365 MHz



1250

This, in turn, converts to 0x555 in the 12-bit twos complement

representation for NCO_FTW. The actual carrier frequency can

be calculated based on the following equation:

NCO _ FTW × f_S

•

f_C− actual =

= 416.56 MHz

2¹²

A 12-bit POW is available for each NCO to create a known phase

relationship between multiple AD9680 chips or individual DDC

channels inside one AD9680.

The following procedure must be followed to update the FTW

and/or POW registers to ensure proper operation of the NCO:

•

Write to the FTW registers for all the DDCs.

Write to the POW registers for all the DDCs.

Synchronize the NCOs either through the DDC soft reset

bit accessible through the SPI, or through the assertion of

the SYSREF pin.

Mixer

The NCO is accompanied by a mixer, whose operation is

similar to an analog quadrature mixer. The mixer performs the

downconversion of input signals (real or complex) by using the

NCO frequency as a local oscillator. For real input signals, this

mixer performs a real mixer operation (with two multipliers).

For complex input signals, the mixer performs a complex mixer

operation (with four multipliers and two adders). The mixer

adjusts its operation based on the input signal (real or complex)

provided to each individual channel. The selection of real or

complex inputs can be controlled individually for each DDC

block by using Bit 7 of the DDC control register (Register 0x310,

Register 0x330, Register 0x350, and Register 0x370).

Note that the NCOs must be synchronized either through SPI

or through the SYSREF pin after all writes to the FTW or POW

registers have completed. This synchronization is necessary to

ensure the proper operation of the NCO.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW)

that determines the instantaneous phase of the NCO. The initial

reset value of each PAW is determined by the POW described

in the Setting Up the NCO FTW and POW section. The phase

increment value of each PAW is determined by the FTW.

Rev. C | Page 56 of 97

Data Sheet

AD9680

FIR FILTERS

Table 17 shows the different bandwidth options by including

FIR FILTERS GENERAL DESCRIPTION

different half-band filters. In all cases, the DDC filtering stage of

the AD9680 provides less than −0.001 dB of pass-band ripple

and >100 dB of stop-band alias rejection.

There are four sets of decimate-by-2, low-pass, half-band, finite

impulse response (FIR) filters (HB1 FIR, HB2 FIR, HB3 FIR,

and HB4 FIR, shown in Figure 146). These filters follow the

frequency translation stage. After the carrier of interest is tuned

down to dc (carrier frequency = 0 Hz), these filters efficiently lower

the sample rate while providing sufficient alias rejection from

unwanted adjacent carriers around the bandwidth of interest.

Table 18 shows the amount of stop-band alias rejection for

multiple pass-band ripple/cutoff points. The decimation ratio

of the filtering stage of each DDC can be controlled individually

through Bits[1:0] of the DDC control registers (0x310, 0x330,

0x350, and 0x370).

HB1 FIR is always enabled and cannot be bypassed. The HB2,

HB3, and HB4 FIR filters are optional and can be bypassed for

higher output sample rates.

Table 17. DDC Filter Characteristics

Real Output

Output

Sample

Decimation Rate

Complex (I/Q) Output

ADC

Output

Sample

Decimation Rate

Alias

Protected

Bandwidth Improvement Ripple

(MHz)

Pass-

Band

Sample Half Band

Rate

(MSPS) Selection

Ideal SNR

Alias

Rejection

(dB)

Filter

Ratio

(MSPS) Ratio

(MSPS)

(dB)¹

(dB)

1250

HB1

1

1250

625

2

625 (I) +

625 (Q)

481.25

1

<−0.001

>100

HB1 + HB2

2

4

8

1

2

4

8

1

2

4

8

1

2

4

8

4

312.5 (I) +

312.5 (Q)

240.62

120.31

60.15

385.0

192.5

96.3

4

HB1 + HB2 +

HB3

312.5

156.25

1000

500

8

156.25 (I) +

156.25 (Q)

7

HB1 + HB2 +

HB3 + HB4

16

2

78.125 (I) +

78.125 (Q)

10

1

1000

HB1

500 (I) +

500 (Q)

250 (I) +

250 (Q)

125 (I) +

125 (Q)

62.5 (I) +

62.5 (Q)

HB1 + HB2

4

HB1 + HB2 +

HB3

HB1 + HB2 +

HB3 + HB4

250

8

7

125

16

2

48.1

10

1

820

HB1

820

410 (I) +

410 (Q)

205 (I) +

205 (Q)

102.5 (I) +

102.5 (Q)

51.25 (I) +

51.25 (Q)

315.7

157.8

78.9

HB1 + HB2

410

4

HB1 + HB2 +

HB3

HB1 + HB2 +

HB3 + HB4

205

8

7

102.5

500

16

2

39.4

10

1

500

HB1

250 (I) +

250 (Q)

125 (I) +

125 (Q)

62.5 (I) +

62.5 (Q)

31.25 (I) +

31.25 (Q)

192.5

96.3

HB1 + HB2

250

4

HB1 + HB2 +

HB3

HB1 + HB2 +

HB3 + HB4

125

8

48.1

7

62.5

16

24.1

10

¹Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(f_S/2)).

Rev. C | Page 57 of 97

AD9680

Data Sheet

Table 18. DDC Filter Alias Rejection

Alias

Pass-Band Ripple/

Alias Protected Bandwidth for

Real (I) Outputs¹

Alias Protected Bandwidth for

Rejection (dB) Cutoff Point (dB)

Complex (I/Q) Outputs¹

<77% × f_OUT

>100

90

85

63.3

25

19.3

10.7

<−0.001

<−0.006

−0.5

<38.5% × f_OUT

<38.7% × f_OUT

<38.9% × f_OUT

<40% × f_OUT

44.4% × f_OUT

45.6% × f_OUT

48% × f_OUT

<77.4% × f_OUT

<77.8% × f_OUT

<80% × f_OUT

88.8% × f_OUT

91.2% × f_OUT

−1.0

−3.0

96% × f_OUT

¹f_OUTis the ADC input sample rate f_S/DDC decimation ratio.

HB3 Filter

HALF-BAND FILTERS

The second decimate-by-2, half-band, low-pass, FIR filter (HB3)

uses an 11-tap, symmetrical, fixed coefficient filter implementation,

optimized for low power consumption. The HB3 filter is only used

when complex outputs (decimate by 8 or 16) or real outputs

(decimate by 4 or 8) are enabled; otherwise, the filter is bypassed.

Table 20 and Figure 151 show the coefficients and response of

the HB3 filter.

The AD9680 offers four half-band filters to enable digital signal

processing of the ADC converted data. These half-band filters

are bypassable and can be individually selected.

HB4 Filter

The first decimate-by-2, half-band, low-pass FIR filter (HB4) uses

an 11-tap, symmetrical, fixed-coefficient filter implementation,

optimized for low power consumption. The HB4 filter is only used

when complex outputs (decimate by 16) or real outputs (decimate

by 8) are enabled; otherwise, the filter is bypassed. Table 19 and

Figure 150 show the coefficients and response of the HB4 filter.

Table 20. HB3 Filter Coefficients

HB3 Coefficient

Number

Normalized

Coefficient

Decimal Coefficient

(18-Bit)

C1, C11

C2, C10

C3, C9

C4, C8

C5, C7

C6

0.006554

0

−0.050819

0

0.294266

0.500000

859

0

−6661

0

38,570

65,536

Table 19. HB4 Filter Coefficients

HB4 Coefficient

Number

Normalized

Coefficient

Decimal Coefficient

(15-Bit)

C1, C11

C2, C10

C3, C9

C4, C8

C5, C7

C6

0.006042

0

−0.049316

0

0.293273

0.500000

99

0

−808

0

4805

8192

0

–20

–40

0

–20

–60

–80

–40

–100

–120

–60

–80

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

NORMALIZED FREQUENCY (× π RAD/SAMPLE)

–100

–120

Figure 151. HB3 Filter Response

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

NORMALIZED FREQUENCY (× π RAD/SAMPLE)

Figure 150. HB4 Filter Response

Rev. C | Page 58 of 97

Data Sheet

AD9680

HB2 Filter

0

–20

The third decimate-by-2, half-band, low-pass FIR filter (HB2)

uses a 19-tap, symmetrical, fixed coefficient filter implementation

that is optimized for low power consumption. The HB2 filter is

only used when complex outputs (decimate by 4, 8, or 16) or

real outputs (decimate by 2, 4, or 8) are enabled; otherwise, the

filter is bypassed.

–40

–60

–80

Table 21 and Figure 152 show the coefficients and response of

the HB2 filter.

–100

–120

Table 21. HB2 Filter Coefficients

HB2 Coefficient

Number

Normalized

Coefficient

Decimal Coefficient

(19-Bit)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

NORMALIZED FREQUENCY (× π RAD/SAMPLE)

C1, C19

C2, C18

C3, C17

C4, C16

C5, C15

C6, C14

C7, C13

C8, C12

C9, C11

C10

0.000614

0

−0.005066

0

0.022179

0

−0.073517

0

0.305786

0.500000

161

0

−1328

0

5814

0

−19,272

0

80,160

131,072

Figure 153. HB1 Filter Response

Table 22. HB1 Filter Coefficients

HB1 Coefficient

Number

Normalized

Coefficient

Decimal Coefficient

(21-Bit)

C1, C55

C2, C54

C3, C53

C4, C52

C5, C51

C6, C50

C7, C49

C8, C48

C9, C47

C10, C46

C11, C45

C12, C44

C13, C43

C14, C42

C15, C41

C16, C40

C17, C39

C18, C38

C19, C37

C20, C36

C21, C35

C22, C34

C23, C33

C24, C32

C25, C31

C26, C30

C27, C29

C28

−0.000023

−24

0

0.000097

102

0

−0.000288

−302

0

–20

0.000696

730

0

−0.0014725

−1544

0

–40

0.002827

2964

0

–60

−0.005039

−5284

0

–80

0.008491

8903

–100

–120

0

−0.013717

−14,383

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.021591

0

22,640

0

NORMALIZED FREQUENCY (× π RAD/SAMPLE)

Figure 152. HB2 Filter Response

−0.033833

0

−35,476

0

HB1 Filter

0.054806

0

57,468

0

The fourth and final decimate-by-2, half-band, low-pass FIR

filter (HB1) uses a 55-tap, symmetrical, fixed coefficient filter

implementation, optimized for low power consumption. The

HB1 filter is always enabled and cannot be bypassed. Table 22

and Figure 153 show the coefficients and response of the HB1

filter.

−0.100557

0

−105,442

0

0.316421

0.500000

331,792

524,288

Rev. C | Page 59 of 97

AD9680

Data Sheet

DDC GAIN STAGE

DDC COMPLEX TO REAL CONVERSION

Each DDC contains an independently controlled gain stage.

The gain is selectable as either 0 dB or 6 dB. When mixing a real

input signal down to baseband, it is recommended that the user

enable the 6 dB of gain to recenter the dynamic range of the

signal within the full scale of the output bits.

Each DDC contains an independently controlled complex to

real conversion block. The complex to real conversion block

reuses the last filter (HB1 FIR) in the filtering stage, along with

an f_S/4 complex mixer to upconvert the signal.

After up converting the signal, the Q portion of the complex

mixer is no longer needed and is dropped.

When mixing a complex input signal down to baseband, the

mixer has already recentered the dynamic range of the signal

within the full scale of the output bits and no additional gain is

necessary. However, the optional 6 dB gain can be used to

compensate for low signal strengths. The downsample by 2

portion of the HB1 FIR filter is bypassed when using the

complex to real conversion stage (see Figure 154).

Figure 154 shows a simplified block diagram of the complex to

real conversion.

HB1 FIR

GAIN STAGE

COMPLEX TO

REAL ENABLE

LOW-PASS

FILTER

I

0dB

OR

I

0

2

I/REAL

6dB

1

COMPLEX TO REAL CONVERSION

0dB

OR

6dB

cos(ωt)

+

90°

REAL

f_S/4

0°

–

sin(ωt)

0dB

OR

6dB

Q

LOW-PASS

FILTER

Q

0dB

OR

6dB

Q

2

HB1 FIR

Figure 154. Complex to Real Conversion Block

Rev. C | Page 60 of 97

Data Sheet

AD9680

DDC EXAMPLE CONFIGURATIONS

Table 23 describes the register settings for multiple DDC example configurations.

Table 23. DDC Example Configurations

Chip

DDC

No. of Virtual

Application Decimation Input

Output

Type

Bandwidth Converters

Layer

Ratio

Type

per DDC¹

Required

Register Settings²

One DDC

2

Complex Complex 38.5% × f_S

2

Register 0x200 = 0x01 (one DDC; I/Q selected)

Register 0x201 = 0x01 (chip decimate by 2)

Register 0x310 = 0x83 (complex mixer; 0 dB gain; variable IF;

complex outputs; HB1 filter)

Register 0x311 = 0x04 (DDC I input = ADC Channel A;

DDC Q input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Two DDCs

4

Complex Complex 19.25% × f_S

4

2

Register 0x200 = 0x02 (two DDCs; I/Q selected)

Register 0x201 = 0x02 (chip decimate by 4)

Register 0x310, Register 0x330 = 0x80 (complex mixer; 0 dB

gain; variable IF; complex outputs; HB2 + HB1 filters)

Register 0x311, Register 0x331 = 0x04 (DDC I input =

ADC Channel A; DDC Q input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Register 0x334, Register 0x335, Register 0x340, Register 0x341 =

FTW and POW set as required by application for DDC 1

Complex Real

9.63% × f_S

Register 0x200 = 0x22 (two DDCs; I only selected)

Register 0x201 = 0x02 (chip decimate by 4)

Register 0x310, Register 0x330 = 0x89 (complex mixer; 0 dB

gain; variable IF; real output; HB3 + HB2 + HB1 filters)

Register 0x311, Register 0x331 = 0x04 (DDC I Input = ADC

Channel A; DDC Q Input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Register 0x334, Register 0x335, Register 0x340, Register 0x341 =

FTW and POW set as required by application for DDC 1

Real

9.63% × f_S

Register 0x200 = 0x22 (two DDCs; I only selected)

Register 0x201 = 0x02 (chip decimate by 4)

Register 0x310, Register 0x330 = 0x49 (real mixer; 6 dB gain;

variable IF; real output; HB3 + HB2 + HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;

DDC 0 Q input = ADC Channel A)

Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B;

DDC 1 Q input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Register 0x334, Register 0x335, Register 0x340, Register 0x341 =

FTW and POW set as required by application for DDC 1

Two DDCs

4

Real

Complex 19.25% × f_S

4

Register 0x200 = 0x02 (two DDCs; I/Q selected)

Register 0x201 = 0x02 (chip decimate by 4)

Register 0x310, Register 0x330 = 0x40 (real mixer; 6 dB gain;

variable IF; complex output; HB2 + HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;

DDC 0 Q input = ADC Channel A)

Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B;

DDC 1 Q input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Register 0x334, Register 0x335, Register 0x340, Register 0x341 =

FTW and POW set as required by application for DDC 1

Rev. C | Page 61 of 97

AD9680

Data Sheet

Chip

DDC

Output

Type

No. of Virtual

Bandwidth Converters

Application Decimation Input

Layer

Ratio

Type

per DDC¹

Required

Register Settings²

Two DDCs

8

Real

4.81% × f_S

2

Register 0x200 = 0x22 (two DDCs; I only selected)

Register 0x201 = 0x03 (chip decimate by 8)

Register 0x310, Register 0x330 = 0x4A (real mixer; 6 dB gain;

variable IF; real output; HB4 + HB3 + HB2 + HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;

DDC 0 Q input = ADC Channel A)

Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B;

DDC 1 Q input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Register 0x334, Register 0x335, Register 0x340, Register 0x341 =

FTW and POW set as required by application for DDC 1

Four DDCs

8

Real

Complex 9.63% × f_S

8

Register 0x200 = 0x03 (four DDCs; I/Q selected)

Register 0x201 = 0x03 (chip decimate by 8)

Register 0x310, Register 0x330, Register 0x350, Register 0x370 =

0x41 (real mixer; 6 dB gain; variable IF; complex output;

HB3+HB2+HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;

DDC 0 Q input = ADC Channel A)

Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A;

DDC 1 Q input = ADC Channel A)

Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B;

DDC 2 Q input = ADC Channel B)

Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B;

DDC 3 Q input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Register 0x334, Register 0x335, Register 0x340, Register 0x341 =

FTW and POW set as required by application for DDC 1

Register 0x354, Register 0x355, Register 0x360, Register 0x361 =

FTW and POW set as required by application for DDC 2

Register 0x374, Register 0x375, Register 0x380, Register 0x381 =

FTW and POW set as required by application for DDC 3

Four DDCs

8

Real

4.81% × f_S

4

Register 0x200 = 0x23 (four DDCs; I only selected)

Register 0x201 = 0x03 (chip decimate by 8)

Register 0x310, Register 0x330, Register 0x350, Register 0x370 =

0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 +

HB3 + HB2 + HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;

DDC 0 Q input = ADC Channel A)

Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A;

DDC 1 Q input = ADC Channel A)

Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B;

DDC 2 Q input = ADC Channel B)

Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B;

DDC 3 Q input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Register 0x334, Register 0x335, Register 0x340, Register 0x341 =

FTW and POW set as required by application for DDC 1

Register 0x354, Register 0x355, Register 0x360, Register 0x361 =

FTW and POW set as required by application for DDC 2

Register 0x374, Register 0x375, Register 0x380, Register 0x381 =

FTW and POW set as required by application for DDC 3

Rev. C | Page 62 of 97

Data Sheet

AD9680

Chip

DDC

Output

Type

No. of Virtual

Bandwidth Converters

Application Decimation Input

Layer

Ratio

Type

per DDC¹

Required

Register Settings²

Four DDCs

16

Real

Complex 4.81% × f_S

8

Register 0x200 = 0x03 (four DDCs; I/Q selected)

Register 0x201 = 0x04 (chip decimate by 16)

Register 0x310, Register 0x330, Register 0x350, Register 0x370 =

0x42 (real mixer; 6 dB gain; variable IF; complex output;

HB4 + HB3 + HB2 + HB1 filters)

Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;

DDC 0 Q input = ADC Channel A)

Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A;

DDC 1 Q input = ADC Channel A)

Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B;

DDC 2 Q input = ADC Channel B)

Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B;

DDC 3 Q input = ADC Channel B)

Register 0x314, Register 0x315, Register 0x320, Register 0x321 =

FTW and POW set as required by application for DDC 0

Register 0x334, Register 0x335, Register 0x340, Register 0x341 =

FTW and POW set as required by application for DDC 1

Register 0x354, Register 0x355, Register 0x360, Register 0x361 =

FTW and POW set as required by application for DDC 2

Register 0x374, Register 0x375, Register 0x380, Register 0x381 =

FTW and POW set as required by application for DDC 3

¹f_Sis the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection.

²The NCOs must be synchronized either through the SPI or through the SYSREF pin after all writes to the FTW or POW registers have completed, to ensure the proper

operation of the NCO. See the NCO Synchronization section for more information.

Rev. C | Page 63 of 97

AD9680

Data Sheet

DIGITAL OUTPUTS

•

K is the number of frames per multiframe

INTRODUCTION TO THE JESD204B INTERFACE

(AD9680 value = 4, 8, 12, 16, 20, 24, 28, or 32 )

S is the samples transmitted/single converter/frame cycle

(AD9680 value = set automatically based on L, M, F, and N΄)

HD is the high density mode (AD9680 = set automatically

based on L, M, F, and N΄)

The AD9680 digital outputs are designed to the JEDEC standard

JESD204B, serial interface for data converters. JESD204B is a

protocol to link the AD9680 to a digital processing device over

a serial interface with lane rates of up to 12.5 Gbps. The benefits

of the JESD204B interface over LVDS include a reduction in

required board area for data interface routing, and an ability to

enable smaller packages for converter and logic devices.

CF is the number of control words/frame clock cycle/

converter device (AD9680 value = 0)

Figure 155 shows a simplified block diagram of the AD9680

JESD204B link. By default, the AD9680 is configured to use

two converters and four lanes. Converter A data is output to

SERDOUT0 and/or SERDOUT1 , and Converter B is output

to SERDOUT2 and/or SERDOUT3 . The AD9680 allows

other configurations such as combining the outputs of both

converters onto a single lane, or changing the mapping of the

A and B digital output paths. These modes are set up via a quick

configuration register in the SPI register map, along with

additional customizable options.

JESD204B OVERVIEW

The JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8-bit/10-bit encoding as

well as optional scrambling to form serial output data. Lane

synchronization is supported through the use of special control

characters during the initial establishment of the link. Additional

control characters are embedded in the data stream to maintain

synchronization thereafter. A JESD204B receiver is required to

complete the serial link. For additional details on the JESD204B

interface, refer to the JESD204B standard.

By default in the AD9680, the 14-bit converter word from each

converter is broken into two octets (eight bits of data). Bit 13

(MSB) through Bit 6 are in the first octet. The second octet

contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits

can be configured as zeros or a pseudorandom number

sequence. The tail bits can also be replaced with control bits

indicating overrange, SYSREF , or fast detect output.

The AD9680 JESD204B data transmit block maps up to two

physical ADCs or up to eight virtual converters (when DDCs

are enabled) over a link. A link can be configured to use one,

two, or four JESD204B lanes. The JESD204B specification refers

to a number of parameters to define the link, and these parameters

must match between the JESD204B transmitter (the AD9680

output) and the JESD204B receiver (the logic device input).

The two resulting octets can be scrambled. Scrambling is

optional; however, it is recommended to avoid spectral peaks

when transmitting similar digital data patterns. The scrambler

uses a self-synchronizing, polynomial-based algorithm defined

by the equation 1 + x

a self-synchronizing version of the scrambler polynomial.

The JESD204B link is described according to the following

parameters:

•

L is the number of lanes/converter device (lanes/link)

(AD9680 value = 1, 2, or 4)

¹⁴+ x¹⁵. The descrambler in the receiver is

•

M is the number of converters/converter device (virtual

converters/link) (AD9680 value = 1, 2, 4, or 8)

F is the octets/frame (AD9680 value = 1, 2, 4, 8, or 16)

N΄ is the number of bits per sample (JESD204B word size)

(AD9680 value = 8 or 16)

The two octets are then encoded with an 8-bit/10-bit encoder.

The 8-bit/10-bit encoder works by taking eight bits of data (an

octet) and encoding them into a 10-bit symbol. Figure 156

shows how the 14-bit data is taken from the ADC, how the tail

bits are added, how the two octets are scrambled, and how the

octets are encoded into two 10-bit symbols. Figure 156 illustrates

the default data format.

•

N is the converter resolution (AD9680 value = 7 to 16)

CS is the number of control bits/sample

(AD9680 value = 0, 1, 2, or 3)

CONVERTER 0

CONVERTER A

ADC

A

INPUT

SERDOUT0–,

SERDOUT0+

MUX/

FORMAT

(SPI

REG 0x561,

REG 0x564)

JESD204B LINK

LANE MUX

AND MAPPING

(SPI

REG 0x5B0,

REG 0x5B2,

REG 0x5B3,

REG 0x5B5,

REG 0x5B6)

CONTROL

(L.M.F)

SERDOUT1–,

SERDOUT1+

(SPI REG 0x570)

SERDOUT2–,

SERDOUT2+

CONVERTER B

INPUT

ADC

B

SERDOUT3–,

SERDOUT3+

CONVERTER 1

SYSREF±

SYNCINB±

Figure 155. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00)

Rev. C | Page 64 of 97

Data Sheet

AD9680

JESD204B

INTERFACE

TEST PATTERN

(REG 0x573,

REG 0x551 TO

REG 0x558)

JESD204B DATA

LINK LAYER TEST

PATTERNS

JESD204B

LONG TRANSPORT

TEST PATTERN

REG 0x571[5]

REG 0x574[2:0]

SERDOUT0±

SERDOUT1±

SERIALIZER

ADC TEST PATTERNS

SCRAMBLER

1 + x + x

(OPTIONAL)

FRAME

CONSTRUCTION

(RE0x550,

8-BIT/10-BIT

ENCODER

14

15

REG 0x551 TO

REG 0x558)

a

b

i

j

a

b

i j

JESD204B SAMPLE

CONSTRUCTION

MSB A13

SYMBOL0

SYMBOL1

a

b

c

d

e

f

g

h

i

j

A12

A11

A10

A9

MSB S7 S7

MSB A13 A5

A12 A4

A11 A3

A10 A2

A9 A1

ADC

S6 S6

S5 S5

A8

TAIL BITS

0x571[6]

A7

S4 S4

A6

S3 S3

A5

S2 S2

A8 A0

A4

S1 S1

A7 C2

A3

LSB S0 S0

LSB A6

T

A2

A1

SB A0

L

C2

C1

C0

CONTROL BITS

Figure 156. ADC Output Data Path Showing Data Framing

TRANSPORT

LAYER

DATA LINK

LAYER

PHYSICAL

LAYER

PROCESSED

ALIGNMENT

CHARACTER

GENERATION

SAMPLE

FRAME

8-BIT/10-BIT

ENCODER

CROSSBAR

MUX

SAMPLES

SCRAMBLER

SERIALIZER

Tx

OUTPUT

CONSTRUCTION CONSTRUCTION

FROM ADC

SYSREF±

SYNCINB±

Figure 157. Data Flow

Physical Layer

FUNCTIONAL OVERVIEW

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. In this layer, parallel data is converted into

one, two, or four lanes of high speed differential serial data.

The block diagram in Figure 157 shows the flow of data through

the JESD204B hardware from the sample input to the physical

output. The processing can be divided into layers that are

derived from the open source initiative (OSI) model widely

used to describe the abstraction layers of communications

systems. These layers are the transport layer, data link layer,

and physical layer (serializer and output driver).

JESD204B LINK ESTABLISHMENT

The AD9680 JESD204B transmitter (Tx) interface operates in

Subclass 1 as defined in the JEDEC Standard 204B (July 2011

specification). The link establishment process is divided into the

following steps: code group synchronization and SYNCINB ,

initial lane alignment sequence, and user data and error correction.

Transport Layer

The transport layer handles packing the data (consisting of

samples and optional control bits) into JESD204B frames that

are mapped to 8-bit octets. These octets are sent to the data link

layer. The transport layer mapping is controlled by rules derived

from the link parameters. Tail bits are added to fill gaps where

required. The following equation can be used to determine the

number of tail bits within a sample (JESD204B word):

Code Group Synchronization (CGS) and SYNCINB

The CGS is the process by which the JESD204B receiver finds

the boundaries between the 10-bit symbols in the stream of

data. During the CGS phase, the JESD204B transmit block

transmits /K28.5/ characters. The receiver must locate /K28.5/

characters in its input data stream using clock and data recovery

(CDR) techniques.

T = N΄ – N – CS

Data Link Layer

The receiver issues a synchronization request by asserting the

SYNCINB pin of the AD9680 low. The JESD204B Tx then begins

sending /K/ characters. Once the receiver has synchronized, it waits

for the correct reception of at least four consecutive /K/ symbols. It

then deasserts SYNCINB . The AD9680 then transmits an ILAS

on the following local multiframe clock (LMFC) boundary.

The data link layer is responsible for the low level functions

of passing data across the link. These include optionally

scrambling the data, inserting control characters for multichip

synchronization/lane alignment/monitoring, and encoding

8-bit octets into 10-bit symbols. The data link layer is also

responsible for sending the initial lane alignment sequence

(ILAS), which contains the link configuration data used by the

receiver to verify the settings in the transport layer.

For more information on the code group synchronization

phase, refer to the JEDEC Standard JESD204B, July 2011,

Section 5.3.3.1.

Rev. C | Page 65 of 97

AD9680

Data Sheet

The SYNCINB pin operation can also be controlled by the

SPI. The SYNCINB signal is a differential dc-coupled LVDS

mode signal by default, but it can also be driven single-ended.

For more information on configuring the SYNCINB pin

operation, refer to Register 0x572.

User Data and Error Detection

After the initial lane alignment sequence is complete, the user

data is sent. Normally, within a frame, all characters are considered

user data. However, to monitor the frame clock and multiframe

clock synchronization, there is a mechanism for replacing

characters with /F/ or /A/ alignment characters when the data

meets certain conditions. These conditions are different for

unscrambled and scrambled data. The scrambling operation is

enabled by default, but it can be disabled using the SPI.

The SYNCINB pins can also be configured to run in CMOS

(single-ended) mode, by setting Bit[4] in Register 0x572. When

running SYNCINB in CMOS mode, connect the CMOS

SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20

(SYNCINB−) floating.

For scrambled data, any 0xFC character at the end of a frame

is replaced by an /F/, and any 0x7C character at the end of a

multiframe is replaced with an /A/. The JESD204B receiver (Rx)

checks for /F/ and /A/ characters in the received data stream

and verifies that they only occur in the expected locations. If an

unexpected /F/ or /A/ character is found, the receiver handles

the situation by using dynamic realignment or asserting the

SYNCINB signal for more than four frames to initiate a

resynchronization. For unscrambled data, if the final character

of two subsequent frames is equal, the second character is

replaced with an /F/ if it is at the end of a frame, and an /A/ if

it is at the end of a multiframe.

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and begins on the next

LMFC boundary. The ILAS consists of four multiframes, with

an /R/ character marking the beginning and an /A/ character

marking the end. The ILAS begins by sending an /R/ character

followed by 0 to 255 ramp data for one multiframe. On the

second multiframe, the link configuration data is sent, starting

with the third character. The second character is a /Q/ character

to confirm that the link configuration data will follow. All

undefined data slots are filled with ramp data. The ILAS

sequence is never scrambled.

Insertion of alignment characters can be modified using SPI.

The frame alignment character insertion (FACI) is enabled by

default. More information on the link controls is available in the

Memory Map section, Register 0x571.

The ILAS sequence construction is shown in Figure 158. The

four multiframes include the following:

•

Multiframe 1. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

8-Bit/10-Bit Encoder

•

Multiframe 2. Begins with an /R/ character followed by a

/Q/ character (/K28.4/), followed by link configuration

parameters over 14 configuration octets (see Table 24) and

ends with an /A/ character. Many of the parameter values

are of the value – 1 notation.

The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols

and inserts control characters into the stream when needed.

The control characters used in JESD204B are shown in Table 24.

The 8-bit/10-bit encoding ensures that the signal is dc balanced by

using the same number of ones and zeros across multiple symbols.

•

Multiframe 3. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

Multiframe 4. Begins with an /R/ character (/K28.0/) and

ends with an /A/ character (/K28.3/).

The 8-bit/10-bit interface has options that can be controlled via

the SPI. These operations include bypass and invert. These options

are troubleshooting tools for the verification of the digital front

end (DFE). See the Memory Map section, Register 0x572[2:1]

for information on configuring the 8-bit/10-bit encoder.

K

R

D

A

R

Q

C

D

A

R

D

A

R

D

D A D

END OF

MULTIFRAME

START OF

ILAS

START OF LINK

CONFIGURATION DATA

START OF

USER DATA

Figure 158. Initial Lane Alignment Sequence

Rev. C | Page 66 of 97

Data Sheet

AD9680

Table 24. AD9680 Control Characters used in JESD204B

10-Bit Value,

RD¹= −1

10-Bit Value,

RD¹= +1

Abbreviation

Control Symbol

/K28.0/

/K28.3/

/K28.4/

/K28.5/

8-Bit Value

000 11100

011 11100

100 11100

101 11100

111 11100

Description

/R/

/A/

/Q/

/K/

/F/

001111 0100

001111 0011

001111 0100

001111 1010

001111 1000

110000 1011

110000 1100

110000 1101

110000 0101

110000 0111

Start of multiframe

Lane alignment

Start of link configuration data

Group synchronization

Frame alignment

/K28.7/

¹RD means running disparity.

If there is no far-end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid such

timing errors, it is recommended that the trace length be less

than six inches, and that the differential output traces be close

together and at equal lengths.

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing, and Controls

The AD9680 physical layer consists of drivers that are defined in

the JEDEC Standard JESD204B, July 2011. The differential digital

outputs are powered up by default. The drivers use a dynamic

100 Ω internal termination to reduce unwanted reflections.

Figure 161 to Figure 166 show an example of the digital output

data eye, time interval error (TIE) jitter histogram, and bathtub

curve for one AD9680 lane running at 10 Gbps and 6 Gbps,

respectively. The format of the output data is twos complement

by default. To change the output data format, see the Memory Map

section (Register 0x561 in Table 36).

Place a 100 Ω differential termination resistor at each receiver

input to result in a nominal 300 mV p-p swing at the receiver

(see Figure 159). Alternatively, single-ended 50 Ω termination

can be used. When single-ended termination is used, the

termination voltage is DRVDD/2. Otherwise, 0.1 µF ac coupling

capacitors can be used to terminate to any single-ended voltage.

De-Emphasis

De-emphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss does not

meet the JESD204B specification. Use the de-emphasis feature

only when the receiver is unable to recover the clock due to

excessive insertion loss. Under normal conditions, it is disabled

to conserve power. Additionally, enabling and setting too high a

de-emphasis value on a short link can cause the receiver eye

diagram to fail. Use the de-emphasis setting with caution

because it can increase electromagnetic interference (EMI). See

the Memory Map section (Register 0x5C1 to Register 0x5C5 in

Table 36) for more details.

V

RXCM

50Ω

DRVDD

100Ω

DIFFERENTIAL

TRACE PAIR

0.1µF

SERDOUTx+

RECEIVER

100Ω

OR

SERDOUTx–

OUTPUT SWING = 300mV p-p

V

= V

RXCM

CM

Figure 159. AC-Coupled Digital Output Termination Example

Phase-Locked Loop

The AD9680 digital outputs can interface with custom ASICs

and FPGA receivers, providing superior switching performance

in noisy environments. Single point-to-point network topologies

are recommended with a single differential 100 Ω termination

resistor placed as close to the receiver inputs as possible. The

common mode of the digital output automatically biases itself

to half the DRVDD supply of 1.2 V (V_CM= 0.6 V). See Figure 160

for dc coupling the outputs to the receiver logic.

The phase-locked loop (PLL) is used to generate the serializer

clock, which operates at the JESD204B lane rate. The status of

the PLL lock can be checked in the PLL locked status bit

(Register 0x56F, Bit 7). This read only bit lets the user know if

the PLL has achieved a lock for the specific setup. The JESD204B

lane rate control, Bit 4 of Register 0x56E, must be set to

correspond with the lane rate.

DRVDD

100Ω

DIFFERENTIAL

TRACE PAIR

SERDOUTx+

RECEIVER

100Ω

SERDOUTx–

OUTPUT SWING = 300mV p-p

V

= DRVDD/2

CM

Figure 160. DC-Coupled Digital Output Termination Example

Rev. C | Page 67 of 97

AD9680

Data Sheet

400

300

200

100

0

400

300

200

100

0

Tx EYE

MASK

Tx EYE

MASK

–100

–200

–300

–400

–100

–200

–300

–400

–100 –80 –60 –40 –20

0

20

40

60

80

–150

–100

–50

0

50

100

150

TIME (ps)

Figure 161. Digital Outputs Data Eye, External 100 Ω Terminations

at 10 Gbps

Figure 164. Digital Outputs Data Eye, External 100 Ω Terminations

at 6 Gbps

8000

7000

6000

4000

3000

2000

1000

0

12000

10000

8000

6000

4000

2000

0

1

2

–4

–2

0

2

4

6

–4

–3

–2

–1

0

3

4

TIME (ps)

Figure 162. Digital Outputs Histogram, External 100 Ω Terminations

at 10 Gbps

Figure 165. Digital Outputs Histogram, External 100 Ω Terminations

at 6 Gbps

1

–2

1

–2

1

–4

1

–4

1

–6

1

–6

1

–8

1

–8

1

–10

1

–10

1

–12

1

–12

1

–14

1

–14

1

–16

1

–16

1

–0.5 –0.4 –0.3 –0.2 –0.1

0

0.1

0.2

0.3

0.4

0.5

–0.5 –0.4 –0.3 –0.2 –0.1

0

0.1

0.2

0.3

0.4

0.5

UI

Figure 163. Digital Outputs Bathtub Curve, External 100 Ω Terminations

at 10 Gbps

Figure 166. Digital Outputs Bathtub Curve, External 100 Ω Terminations

at 6 Gbps

Rev. C | Page 68 of 97

Data Sheet

AD9680

Figure 167 shows a block diagram of the two scenarios

described for I/Q transport layer mapping.

JESD204B TX CONVERTER MAPPING

To support the different chip operating modes, the AD9680

design treats each sample stream (real or I/Q) as originating

from separate virtual converters. The I/Q samples are always

mapped in pairs with the I samples mapped to the first virtual

converter and the Q samples mapped to the second virtual

converter. With this transport layer mapping, the number of

virtual converters are the same whether

The JESD204B Tx block for AD9680 supports up to four DDC

blocks. Each DDC block outputs either two sample streams (I/Q)

for the complex data components (real + imaginary), or one

sample stream for real (I) data. The JESD204B interface can be

configured to use up to eight virtual converters depending on the

DDC configuration. Figure 168 shows the virtual converters and

their relationship to the DDC outputs when complex outputs

are used. Table 25 shows the virtual converter mapping for each

chip operating mode when channel swapping is disabled.

•

A single real converter is used along with a digital

downconverter block producing I/Q outputs, or

An analog downconversion is used with two real

converters producing I/Q outputs.

•

DIGITAL DOWNCONVERSION

M = 2

I

CONVERTER 0

DIGITAL

DOWN

CONVERSION

JESD204B

Tx

REAL

L LANES

ADC

Q

CONVERTER 1

I/Q ANALOG MIXING

M = 2

I

CONVERTER 0

I

ADC

REAL

90°

PHASE

JESD204B

Tx

L LANES

Σ

Q

CONVERTER 1

ADC

Figure 167. I/Q Transport Layer Mapping

DDC 0

ADC A

SAMPLING

AT f_S

REAL/I

CONVERTER 0

Q

I

REAL/Q

Q

CONVERTER 1

DDC 1

DDC 2

DDC 3

REAL/I

CONVERTER 2

Q

I

REAL/Q

Q

I/Q

CROSSBAR

MUX

CONVERTER 3

OUTPUT

INTERFACE

REAL/I

CONVERTER 4

Q

I

REAL/Q

Q

CONVERTER 5

ADC B

SAMPLING

AT f_S

REAL/I

CONVERTER 6

Q

REAL/Q

I

REAL/Q

Q

CONVERTER 7

Figure 168. DDCs and Virtual Converter Mapping

Rev. C | Page 69 of 97

AD9680

Data Sheet

Table 25. Virtual Converter Mapping

Number of Chip

Virtual Converter Mapping

Virtual

Converters Mode (0x200, Ignore

Supported Bits[1:0]) (0x200, Bit 5)

Full bandwidth Real or

Operating

Chip Q

0

1

2

3

4

5

6

7

1 to 2

ADC A

ADC B

Unused

DDC 3 Q

mode (0x0)

complex

(0x0)

samples samples

1

2

4

8

One DDC

mode

(0x1)

Real (I only)

(0x1)

DDC 0 I

Unused

samples

One DDC

mode

(0x1)

Complex (I/Q) DDC 0 I

(0x0)

DDC 0 Q Unused

samples samples

Two DDC

mode

(0x2)

Real (I only)

(0x1)

DDC 0 I

DDC 1 I

Unused

samples samples

Two DDC

mode

(0x2)

Complex (I/Q) DDC 0 I

(0x0)

DDC 0 Q DDC 1 I

samples samples samples samples

DDC 1 Q Unused

Four DDC

mode

(0x3)

Real (I only)

(0x1)

DDC 0 I

DDC 1 I

DDC 2 I

DDC 3 I

Unused

samples samples samples samples

Four DDC

mode

Complex (I/Q) DDC 0 I

(0x0)

DDC 0 Q DDC 1 I

DDC 1 Q DDC 2 I

DDC 2 Q DDC 3 I

samples samples samples samples samples samples samples samples

(0x3)

Rev. C | Page 70 of 97

Data Sheet

AD9680

The decimation ratio (DCM) is the parameter programmed in

Register 0x201.

CONFIGURING THE JESD204B LINK

The AD9680 has one JESD204B link. The device offers an easy

way to set up the JESD204B link through the JESD04B quick

configuration register (Register 0x570). The serial outputs

(SERDOUT0 to SERDOUT3 ) are considered to be part of

one JESD204B link. The basic parameters that determine the

link setup are

The following steps can be used to configure the output:

1. Power down the link.

2. Select quick configuration options.

3. Configure detailed options.

4. Set output lane mapping (optional).

5. Set additional driver configuration options (optional).

6. Power up the link.

•

Number of lanes per link (L)

Number of converters per link (M)

Number of octets per frame (F)

If the lane line rate calculated is less than 6.25 Gbps, select

the low line rate option by programming a value of 0x10 to

Register 0x56E.

If the internal DDCs are used for on-chip digital processing, M

represents the number of virtual converters. The virtual converter

mapping setup is shown in Figure 168.

Table 26 and Table 27 show the JESD204B output configurations

supported for both N΄ = 16 and N΄ = 8 for a given number of

virtual converters. Take care to ensure that the serial line rate

for a given configuration is within the supported range of

3.125 Gbps to 12.5 Gbps.

The maximum lane rate allowed by the JESD204B specification

is 12.5 Gbps. The lane line rate is related to the JESD204B

parameters using the following equation:

10

8

L











M ×N'×

× f

OUT



Lane Line Rate =

f_{ADC _CLOCK}

Decimation Ratio

where

f_OUT

=

Table 26. JESD204B Output Configurations for N΄ = 16

Number of Virtual

JESD204B Transport Layer Settings²

Converters

Supported

(Same Value as M) (0x570)

JESD204B Quick

Configuration

JESD204B Serial

Line Rate¹

L

1

2

4

1

2

4

1

2

4

1

2

4

M

1

2

4

8

F

2

1

2

1

2

4

2

1

2

8

4

2

16

8

4

S

1

2

4

1

2

1

HD

0

1

0

1

N

N΄ CS

K³

1

0x01

0x40

0x41

0x80

0x81

0x0A

0x49

0x88

0x89

0x13

0x52

0x91

0x1C

0x5B

0x9A

20 × f_OUT

10 × f_OUT

5 × f_OUT

8 to 16

16 0 to 3

Only valid K

values that

are divisible

by 4 are

supported

5 × f_OUT

0

2

40 × f_OUT

20 × f_OUT

10 × f_OUT

80 × f_OUT

40 × f_OUT

20 × f_OUT

160 × f_OUT

80 × f_OUT

40 × f_OUT

0

1

0

4

8

0

¹f_OUT= output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥3125 Mbps and ≤12,500 Mbps; when the serial line rate is

≤12.5 Gbps and ≥ 6.25 Gbps, the low line rate mode must be disabled (set Bit 4 to 0x0 in 0x56E). When the serial line rate is <6.25 Gbps and ≥3.125 Gbps, the low line

rate mode must be enabled (set Bit 4 to 0x1 in 0x56E).

²JESD204B transport layer descriptions are as described in the JESD204B Overview section.

³For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.

Rev. C | Page 71 of 97

AD9680

Data Sheet

Table 27. JESD204B Output Configurations for N΄ = 8

Number of Virtual

JESD204B Quick

JESD204B Transport Layer Settings²

Converters Supported Configuration

(Same Value as M)

(0x570)

0x00

0x01

0x40

0x41

0x42

0x80

0x81

0x09

0x48

0x49

0x88

0x89

0x8A

Serial Line Rate¹

10 × f_OUT

5 × f_OUT

L

1

2

4

1

2

4

M

1

2

F

1

2

1

2

4

1

2

1

2

1

2

4

S

1

2

4

8

4

8

1

2

4

8

HD

0

N

N΄

8

CS

0 to 1 Only valid K

K³

1

7 to 8

values which

are divisible

by 4 are

0 to 1

0

5 × f_OUT

0

supported

5 × f_OUT

0

2.5 × f_OUT

20 × f_OUT

10 × f_OUT

5 × f_OUT

0

2

0

5 × f_OUT

0

5 × f_OUT

0

¹f_OUT= output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥3125 Mbps and ≤12,500 Mbps; when the serial line rate is

≤12.5 Gbps and ≥6.25 Gbps, the low line rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial line rate is <6.25 Gbps and ≥3.125 Gbps, the

low line rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E).

²JESD204B transport layer descriptions are as described in the JESD204B Overview section.

³For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.

CMOS

See the Example 1: Full Bandwidth Mode section and the

Example 2: ADC with DDC Option (Two ADCs Plus Four

DDCs) section for two examples describing which JESD204B

FAST

DETECTION

transport layer settings are valid for a given chip mode.

L

14-BIT

AT

1Gbps

REAL/I

JESD204B

LANES

AT UP TO

12.5Gbps

Example 1: Full Bandwidth Mode

CONVERTER 0

CONVERTER 1

JESD204B

TRANSMIT

INTERFACE

Chip application mode = full bandwidth mode (see Figure 169).

14-BIT

AT

1Gbps

REAL/Q

•

Two 14-bit converters at 1000 MSPS

Full bandwidth application layer mode

No decimation

FAST

DETECTION

JESD204B output configuration is as follows:

CMOS

•

Two virtual converters required (see Table 26)

Output sample rate (f_OUT) = 1000/1 = 1000 MSPS

Figure 169. Full Bandwidth Mode

Example 2: ADC with DDC Option (Two ADCs Plus Four

DDCs)

JESD204B supported output configurations (see Table 26)

include:

Chip application mode = four-DDC mode. (see Figure 170).

•

N΄ = 16 bits

N = 14 bits

•

Two 14-bit converters at 1 GSPS

Four DDC application layer mode with complex outputs

(I/Q)

Chip decimation ratio = 16

DDC decimation ratio = 16 (see Table 15).

L = 4, M = 2, and F = 1, or L = 4, M = 2, and F = 2 (quick

configuration = 0x88 or 0x89)

CS = 0 to 2

K = 32

Output serial line rate = 10 Gbps per lane, low line rate

mode disabled

•

JESD204B output configuration is as follows:

•

Virtual converters required = 8 (see Table 26)

Output sample rate (f_OUT) = 1000/16 = 62.5 MSPS

Rev. C | Page 72 of 97

Data Sheet

AD9680

JESD204B supported output configurations (see Table 26):

For L = 1, low line rate mode is disabled. For L = 2, low line

rate mode is enabled.

•

N΄ = 16 bits

N = 14 bits

Example 2 shows the flexibility in the digital and lane

configurations for the AD9680. The sample rate is 1 GSPS;

however, the outputs are all combined in either one or two

lanes, depending on the I/O speed capability of the receiving

device.

L = 1, M = 8, and F = 16, or L = 2, M = 8, and F = 8 (quick

configuration = 0x1C or 0x5B)

•

CS = 0 to 1

K = 32

Output serial line rate = 10 Gbps per lane (L = 1) or 5 Gbps

per lane (L = 2)

I

ADC A

SAMPLING

AT f_S

REAL

CONVERTER 0

Q

CONVERTER 1

REAL/I

DDC 0

DDC 1

DDC 2

DDC 3

L

I

JESD204B

LANES

CONVERTER 2

Q

CONVERTER 3

REAL/Q

AT UP TO

12.5Gbps

L JESD204B

LANES UP TO

12.5Gbps

I/Q

CROSSBAR

MUX

I

CONVERTER 4

Q

CONVERTER 5

REAL/I

ADC B

SAMPLING

AT f_S

I

REAL

REAL/Q

CONVERTER 6

Q

CONVERTER 7

SYSREF

SYNCHRONIZATION

CONTROL CIRCUITS

Figure 170. Two ADC Plus Four DDC Mode

Rev. C | Page 73 of 97

AD9680

Data Sheet

MULTICHIP SYNCHRONIZATION

The AD9680 has a SYSREF input that provides flexible options

for synchronizing the internal blocks. The SYSREF input is a

source synchronous system reference signal that enables multichip

synchronization. The input clock divider, DDCs, signal monitor

block, and JESD204B link can be synchronized using the SYSREF

input. For the highest level of timing accuracy, SYSREF must

meet setup and hold requirements relative to the CLK input.

supports several features that aid users in meeting the

requirements set out for capturing a SYSREF signal. The

SYSREF sample event can be defined as either a synchronous

low to high transition, or a synchronous high to low transition.

Additionally, the AD9680 allows the SYSREF signal to be sampled

using either the rising edge or falling edge of the CLK input.

The AD9680 also has the ability to ignore a programmable

number (up to 16) of SYSREF events. The SYSREF control

options can be selected using Register 0x120 and Register 0x121.

The flowchart in Figure 171 describes the internal mechanism

for multichip synchronization in the AD9680. The AD9680

Rev. C | Page 74 of 97

Data Sheet

AD9680

START

INCREMENT

SYSREF± IGNORE

COUNTER

NO

SYSREF±

IGNORE

COUNTER

EXPIRED?

(0x121)

UPDATE

SETUP/HOLD

DETECTOR STATUS

(0x128)

RESET

SYSREF± IGNORE

COUNTER

SYSREF±

ENABLED?

(0x120)

NO

YES

SYSREF±

ASSERTED?

YES

INPUT

CLOCK

DIVIDER

AUTO ADJUST

ENABLED?

(0x10D)

INCREMENT

SYSREF±

COUNTER

(0x12A)

CLOCK

DIVIDER

> 1?

ALIGN CLOCK

DIVIDER

PHASE TO

SYSREF

YES

DIVIDER

ALIGNMENT

REQUIRED?

(0x10B)

NO

TIMESTAMP

MODE

SYSREF±

TIMESTAMP

DELAY

SYSREF±

YES

CONTROL BITS?

(0x559, 0x55A,

0x58F)

INSERTED

IN JESD204B

CONTROL BITS

SYNCHRONIZATION

MODE?

(0x123)

(0x1FF)

NO

RAMP

TEST

SYSREF± RESETS

RAMP TEST

MODE

YES

MODE

NORMAL

MODE

BACK TO START

ENABLED?

(0x550)

GENERATOR

NO

ALIGN PHASE

JESD204B

LMFC

ALIGNMENT

REQUIRED?

SEND INVALID

NORMAL

OF ALL

YES

SYNC~

ASSERTED

8-BIT/10-BIT

CHARACTERS

(ALL 0's)

SEND K28.5

CHARACTERS

JESD204B

INTERNAL CLOCKS

(INCLUDING LMFC)

TO SYSREF±

INITIALIZATION

NO

SIGNAL

MONITOR

ALIGNMENT

ENABLED?

(0x26F)

DDC NCO

ALIGN DDC

NCO PHASE

ACCUMULATOR

ALIGN SIGNAL

YES

ALIGNMENT

ENABLED?

(0x300)

MONITOR

BACK TO START

COUNTERS

NO

Figure 171. Multichip Synchronization

Rev. C | Page 75 of 97

AD9680

Data Sheet

Figure 172 and Figure 173 show the setup and hold status values

for different phases of SYSREF . The setup detector returns the

status of the SYSREF signal before the CLK edge, and the

hold detector returns the status of the SYSREF signal after the

CLK edge. Register 0x128 stores the status of SYSREF and

lets the user know if the SYSREF signal is captured by the ADC.

SYSREF SETUP/HOLD WINDOW MONITOR

To ensure a valid SYSREF signal capture, the AD9680 has a

SYSREF setup/hold window monitor. This feature allows the

system designer to determine the location of the SYSREF signals

relative to the CLK signals by reading back the amount of

setup/hold margin on the interface through the memory map.

0xF

0xE

0xD

0xC

0xB

0xA

0x9

REG 0x128[3:0]

0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

CLK±

INPUT

SYSREF±

INPUT

VALID

FLIP-FLOP

HOLD (MIN)

FLIP-FLOP

SETUP (MIN)

FLIP-FLOP

HOLD (MIN)

Figure 172. SYSREF Setup Detector

Rev. C | Page 76 of 97

Data Sheet

AD9680

0xF

0xE

0xD

0xC

0xB

0xA

0x9

REG 0x128[7:4] 0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

CLK±

INPUT

SYSREF±

INPUT

VALID

FLIP-FLOP

SETUP (MIN)

FLIP-FLOP

HOLD (MIN)

FLIP-FLOP

HOLD (MIN)

Figure 173. SYSREF Hold Detector

Table 28 shows the description of the contents of Register 0x128 and how to interpret them.

Table 28. SYSREF Setup/Hold Monitor, Register 0x128

Register 0x128[7:4]

Hold Status

Register 0x128[3:0]

Setup Status

Description

0x0

0x0 to 0x8

0x8

0x0 to 0x7

0x8

0x9 to 0xF

0x0

Possible setup error. The smaller this number, the smaller the setup margin.

No setup or hold error (best hold margin).

No setup or hold error (best setup and hold margin).

No setup or hold error (best setup margin).

0x8

0x9 to 0xF

0x0

Possible hold error. The larger this number, the smaller the hold margin.

Possible setup or hold error.

Rev. C | Page 77 of 97

AD9680

Data Sheet

TEST MODES

If the application mode is set to select a DDC mode of

ADC TEST MODES

operation, the test modes must be enabled for each DDC

enabled. The test patterns can be enabled via Bit 2 and Bit 0 of

Register 0x327, Register 0x347, and Register 0x367, depending

on which DDC(s) are selected. The (I) data uses the test

patterns selected for Channel A, and the (Q) data uses the test

patterns selected for Channel B. For DDC3 only, the (I) data

uses the test patterns from Channel A, and the (Q) data does

not output test patterns. Bit 0 of Register 0x387 selects the

Channel A test patterns to be used for the (I) data. For more

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

The AD9680 has various test options that aid in the system level

implementation. The AD9680 has ADC test modes that are

available in Register 0x550. These test modes are described in

Table 29. When an output test mode is enabled, the analog section

of the ADC is disconnected from the digital back-end blocks,

and the test pattern is run through the output formatting block.

Some of the test patterns are subject to output formatting, and

some are not. The PN generators from the PN sequence tests

can be reset by setting Bit 4 or Bit 5 of Register 0x550. These

tests can be performed with or without an analog signal (if

present, the analog signal is ignored); however, they do require

an encode clock.

Table 29. ADC Test Modes¹

Output Test Mode

Bit Sequence

Default/

Seed Value

Pattern Name

Off (default)

Expression

Sample (N, N + 1, N + 2, …)

0000

N/A

0001

0010

0011

0100

0101

0110

0111

1000

Midscale short

+Full-scale short

−Full-scale short

Checkerboard

PN sequence long

PN sequence short

One-/zero-word toggle

User input

00 0000 0000 0000

01 1111 1111 1111

10 0000 0000 0000

10 1010 1010 1010

X²³+ X¹⁸+ 1

N/A

0x3AFF

0x0092

N/A

0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555

0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6

0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697

0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000

X⁹+ X⁵+ 1

11 1111 1111 1111

Register 0x551 to

Register 0x558

N/A

User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2],

User Pattern 1[15:2] … for repeat mode

User Pattern 1[15:2], User Pattern 2[15:2],

User Pattern 3[15:2], User Pattern 4[15:2],

0x0000 … for single mode

1111

Ramp Output

(X) % 2¹⁴

N/A

(X) % 2¹⁴, (X +1) % 2¹⁴, (X +2) % 2¹⁴, (X +3) % 2¹⁴

¹N/A means not applicable.

Rev. C | Page 78 of 97

Data Sheet

AD9680

These tests are shown in Register 0x571[5]. The test pattern is

equivalent to the raw samples from the ADC.

JESD204B BLOCK TEST MODES

In addition to the ADC pipeline test modes, the AD9680 also has

flexible test modes in the JESD204B block. These test modes are

listed in Register 0x573 and Register 0x574. These test patterns

can be injected at various points along the output data path. These

test injection points are shown in Figure 156. Table 30 describes

the various test modes available in the JESD204B block. For the

AD9680, a transition from test modes (Register 0x573 ≠ 0x00)

to normal mode (Register 0x573 = 0x00) requires an SPI soft

reset. This is done by writing 0x81 to Register 0x00 (self cleared).

Interface Test Modes

The interface test modes are described in Register 0x573, Bits[3:0].

These test modes are also explained in Table 30. The interface tests

can be injected at various points along the data. See Figure 156

for more information on the test injection points. Register 0x573,

Bits[5:4] show where these tests are injected.

Table 31, Table 32, and Table 33 show examples of some of the

test modes when injected at the JESD sample input, PHY 10-bit

input, and scrambler 8-bit input. UP in the tables represent the

user pattern control bits from the customer register map.

Transport Layer Sample Test Mode

The transport layer samples are implemented in the AD9680 as

defined by Section 5.1.6.3 in the JEDEC JESD204B Specification.

Table 30. JESD204B Interface Test Modes

Output Test Mode

Bit Sequence

Pattern Name

Expression

Default

0000

Off (default)

Not applicable

0001

0010

0011

0100

0101

0110

0111

1000

Alternating checker board

1/0 word toggle

0x5555, 0xAAAA, 0x5555, …

0x0000, 0xFFFF, 0x0000, …

X³¹+ X²⁸+ 1

Not applicable

0x0003AFFF

0x003AFF

0x03AF

0x092

0x07

Ramp size depends on test injection point

User Pattern 1 to User Pattern 4, then repeat

User Pattern 1 to User Pattern 4, then zeros

31-bit PN sequence

23-bit PN sequence

15-bit PN sequence

9-bit PN sequence

7-bit PN sequence

Ramp output

X²³+ X¹⁸+ 1

X¹⁵+ X¹⁴+ 1

X⁹+ X⁵+ 1

X⁷+ X⁶+ 1

(X) % 2¹⁶

1110

1111

Continuous/repeat user test

Single user test

Register 0x551 to Register 0x558

Table 31. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x573[5:4] = 'b00)

Frame

Number

Converter

Number

Sample

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

PN9

PN23

User Repeat

UP1[15:0]

UP2[15:0]

UP3[15:0]

User Single

UP1[15:0]

UP2[15:0]

UP3[15:0]

UP4[15:0]

0x0000

0

1

2

3

4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0x5555

0xAAAA

0x5555

0xAAAA

0x5555

0x0000

0xFFFF

0x0000

0xFFFF

0x0000

(X) % 2¹⁶

0x496F

0xC9A9

0x980C

0x651A

0x5FD1

0xFF5C

0x0029

0xB80A

0x3D72 UP4[15:0]

0x9B26

(X) % 2¹⁶

(X +1) % 2¹⁶

(X +2) % 2¹⁶

(X +3) % 2¹⁶

(X +4) % 2¹⁶

UP1[15:0]

0x0000

Rev. C | Page 79 of 97

AD9680

Data Sheet

Table 32. Physical Layer 10-bit Input (Register 0x573[5:4] = 'b01)

10-Bit Symbol

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

(X) % 2¹⁰

PN9

PN23

0x3FD

0x1C0

0x00A

0x1B8

0x028

0x3D7

0x0A6

0x326

0x10F

0x3FD

0x31E

0x008

User Repeat

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

User Single

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

0x000

0

1

2

3

4

5

6

7

8

9

10

11

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x125

0x2FC

0x26A

0x198

0x031

0x251

0x297

0x3D1

0x18E

0x2CB

0x0F1

0x3DD

(X + 1) % 2¹⁰

(X + 2) % 2¹⁰

(X + 3) % 2¹⁰

(X + 4) % 2¹⁰

(X + 5) % 2¹⁰

(X + 6) % 2¹⁰

(X + 7) % 2¹⁰

(X + 8) % 2¹⁰

(X + 9) % 2¹⁰

(X + 10) % 2¹⁰

(X + 11) % 2¹⁰

0x000

Table 33. Scrambler 8-bit Input (Register 0x573[5:4] = 'b10)

8-Bit Octet

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

(X) % 2⁸

PN9

PN23

User Repeat

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

User Single

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

0x00

0

1

2

3

4

5

6

7

8

9

10

11

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x49

0x6F

0xC9

0xA9

0x98

0x0C

0x65

0x1A

0x5F

0xD1

0x63

0xAC

0xFF

0x5C

0x00

0x29

0xB8

0x0A

0x3D

0x72

0x9B

0x26

0x43

0xFF

(X + 1) % 2⁸

(X + 2) % 2⁸

(X + 3) % 2⁸

(X + 4) % 2⁸

(X + 5) % 2⁸

(X + 6) % 2⁸

(X + 7) % 2⁸

(X + 8) % 2⁸

(X + 9) % 2⁸

(X + 10) % 2⁸

(X + 11) % 2⁸

0x00

Data Link Layer Test Modes

Test patterns inserted at this point are useful for verifying the

functionality of the data link layer. When the data link layer

test modes are enabled, disable SYNCINB by writing 0xC0

to Register 0x572.

The data link layer test modes are implemented in the AD9680

as defined by section 5.3.3.8.2 in the JEDEC JESD204B

Specification. These tests are shown in Register 0x574 Bits[2:0].

Rev. C | Page 80 of 97

Data Sheet

AD9680

SERIAL PORT INTERFACE

The AD9680 SPI allows the user to configure the converter for

specific functions or operations through a structured register

space provided inside the ADC. The SPI gives the user added

flexibility and customization, depending on the application.

Addresses are accessed via the serial port and can be written to

or read from via the port. Memory is organized into bytes that

can be further divided into fields. These fields are documented

in the Memory Map section. For detailed operational information,

see the Serial Control Interface Standard (Rev. 1.0).

command is issued, which allows the SDIO pin to change

direction from an input to an output.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. If the instruction is a

readback operation, performing a readback causes the SDIO pin

to change direction from an input to an output at the appropriate

point in the serial frame.

CONFIGURATION USING THE SPI

Data can be sent in MSB first mode or in LSB first mode. MSB

first is the default on power-up and can be changed via the SPI

port configuration register. For more information about this

and other features, see the Serial Control Interface Standard

(Rev. 1.0).

Three pins define the SPI of the AD9680 ADC: the SCLK pin,

the SDIO pin, and the CSB pin (see Table 34). The SCLK (serial

clock) pin is used to synchronize the read and write data

presented from/to the ADC. The SDIO (serial data input/output)

pin is a dual-purpose pin that allows data to be sent and read

from the internal ADC memory map registers. The CSB (chip

select bar) pin is an active low control that enables or disables

the read and write cycles.

HARDWARE INTERFACE

The pins described in Table 34 comprise the physical interface

between the user programming device and the serial port of the

AD9680. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

Table 34. Serial Port Interface Pins

Function

SCLK Serial clock. The serial shift clock input that is used to

synchronize serial interface, reads, and writes.

SDIO Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note,

Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.

CSB

Chip select bar. An active low control that gates the read

and write cycles.

Do not activate the SPI port during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is

used for other devices, it may be necessary to provide buffers

between this bus and the AD9680 to prevent these signals from

transitioning at the converter inputs during critical sampling

periods.

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the

serial timing and its definitions can be found in Figure 4 and

Table 5.

Other modes involving the CSB pin are available. The CSB pin

can be held low indefinitely, which permanently enables the

device; this is called streaming. The CSB can stall high between

bytes to allow additional external timing. When CSB is tied

high, SPI functions are placed in a high impedance mode. This

mode turns on any SPI pin secondary functions.

SPI ACCESSIBLE FEATURES

Table 35 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the Serial Control Interface Standard (Rev. 1.0). The AD9680

device-specific features are described in the Memory Map section.

All data is composed of 8-bit words. The first bit of each

individual byte of serial data indicates whether a read or write

Table 35. Features Accessible Using the SPI

Feature Name

Description

Mode

Clock

Allows the user to set either power-down mode or standby mode.

Allows the user to access the clock divider via the SPI.

DDC

Allows the user to set up decimation filters for different applications.

Allows the user to set test modes to have known data on output bits.

Allows the user to set up outputs.

Test Input/Output

Output Mode

SERDES Output Setup

Allows the user to vary SERDES settings such as swing and emphasis.

Rev. C | Page 81 of 97

AD9680

Data Sheet

MEMORY MAP

Logic Levels

An explanation of logic level terminology follows:

READING THE MEMORY MAP REGISTER TABLE

Each row in the memory map register table has eight bit

locations. The memory map is divided into four sections: the

Analog Devices SPI registers (Register 0x000 to Register 0x00D),

the analog input buffer control registers, the ADC function

registers, the DDC function registers, and the digital outputs

and test modes registers.

•

“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

X denotes a don’t care bit.

Table 36 (see the Memory Map Register Table section) documents

the default hexadecimal value for each hexadecimal address shown.

The column with the heading Bit 7 (MSB) is the start of the

default hexadecimal value given. For example, Address 0x561,

the output mode register, has a hexadecimal default value of

0x01, which means that Bit 0 = 1, and the remaining bits are 0s.

This setting is the default output format value, which is twos

complement. For more information on this function and others,

see Table 36.

Channel-Specific Registers

Some channel setup functions, such as the input termination

(Register 0x016), can be programmed to a different value for

each channel. In these cases, channel address locations are

internally duplicated for each channel. These registers and bits

are designated in Table 36 as local. These local registers and bits

can be accessed by setting the appropriate Channel A or Channel B

bits in Register 0x008. If both bits are set, the subsequent write

affects the registers of both channels. In a read cycle, set only

Channel A or Channel B to read one of the two registers. If both

bits are set during an SPI read cycle, the device returns the value

for Channel A. Registers and bits designated as global in Table 36

affect the entire device and the channel features for which

independent settings are not allowed between channels. The

settings in Register 0x005 do not affect the global registers and bits.

Open and Reserved Locations

All address and bit locations that are not included in Table 36

are not currently supported for this device. Write unused bits of

a valid address location with 0s unless the default value is set

otherwise. Writing to these locations is required only when part

of an address location is unassigned (for example, Address 0x561).

If the entire address location is open (for example, Address 0x13),

do not write to this address location.

SPI Soft Reset

After issuing a soft reset by programming 0x81 to Register 0x000,

the AD9680 requires 5 ms to recover. When programming the

AD9680 for application setup, ensure that an adequate delay is

programmed into the firmware after asserting the soft reset and

before starting the device setup.

Default Values

After the AD9680 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 36.

Rev. C | Page 82 of 97

Data Sheet

AD9680

MEMORY MAP REGISTER TABLE

All address locations that are not included in Table 36 are not currently supported for this device and should not be written.

Table 36. Memory Map Registers

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

Analog Devices SPI Registers

0x000

INTERFACE_

CONFIG_A

Soft reset

(self

clearing)

LSB first

0 = MSB

1 = LSB

Address

ascension

0

Address

ascension

LSB first

0 = MSB

1 = LSB

Soft reset

(self

clearing)

0x00

0x001

INTERFACE_

CONFIG_B

Single

instruction

0

Datapath

soft reset

(self

0

clearing)

0x002

DEVICE_

CONFIG

(local)

0

00 = normal operation

10 = standby

11 = power-down

0x00

0x003

0x004

0x005

0x006

CHIP_TYPE

011 = high speed ADC

0x03

0xC5

0x00

Read

only

CHIP_ID

(low byte)

1

0

1

0

X

1

0

X

0

1

0

Read

only

CHIP_ID

(high byte)

Read

only

CHIP_

GRADE

1100 = 1250 MSPS

1010 = 1000 MSPS

1000 = 820 MSPS

0101 = 500 MSPS

X

Read

only

0x008

0x00A

0x00B

0x00C

Device index

Scratch pad

SPI revision

0

1

0

1

0

1

Channel B

Channel A

0x0

0

1

0

1

0

0x00

0x01

0x56

Vendor ID

(low byte)

Read

only

0x00D

Vendor ID

(high byte)

0

1

0

0x04

0x00

Read

only

Analog Input Buffer Control Registers

0x015

Analog input

(local)

0

Input

disable

0 =

normal

operation

1 = input

disabled

0x016

Input

termination

(local)

Analog input differential termination

0000 = 400 Ω (default)

0001 = 200 Ω

1110 = AD9680-1250 and AD9680-1000

1100 = AD9680-820 and AD9680-500

0x0E for

AD9680-

1250 and

AD9680-

1000;

0010 = 100 Ω

0110 = 50 Ω

0x0C for

AD9680-

820 and

AD9680-

500

0x934

Input

capacitance

(local)

0

0x1F = 3 pF to GND (default)

0x00 = 1.5 pF to GND

0x1F

Rev. C | Page 83 of 97

AD9680

Data Sheet

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x018

Buffer

Control 1

(local)

0000 = 1.0× buffer current

0001 = 1.5× buffer current

0010 = 2.0× buffer current (default for AD9680-500)

0011 = 2.5× buffer current

0100 = 3.0× buffer current (default for AD9680-1000

and AD9680-820)

0

0x50 for

AD9680-

1250;

0x40 for

AD9680-

1000

0101 = 3.5× buffer current (default for AD9680-1250)

…

and

AD9680-

820;

1111 = 8.5× buffer current

0x20 for

AD9680-

500

0x019

Buffer

Control 2

(local)

0100 = Setting 1 (default for AD9680-820)

0101 = Setting 2 (default for AD9680-1250 and

AD9680-1000)

0110 = Setting 3 (default for AD9680-500)

0111 = Setting 4

0

0x50 for

AD9680-

1250 and

AD9680-

1000;

0x40 for

AD9680-

820;

0x60 for

AD9680-

500

0x01A

Buffer

Control 3

(local)

0

1000 = Setting 1

1001 = Setting 2 (default for AD9680-1250,

AD9680-1000 and AD9680-820)

0x09 for

AD9680-

1250,

1010 = Setting 3 (default for AD9680-500)

AD9680-

1000

and

AD9680-

820;

0x0A for

AD9680-

500

0x11A

0x935

0x025

Buffer

Control 4

(local)

0

High

0

frequency

setting

0 = off

(default)

1 = on

Buffer

Control 5

(local)

0

Low

frequency

operation

0 = off

1 = on

(default)

Input full-

scale range

(local)

0

Full-scale adjust

0000 = 1.94 V

1000 = 1.46 V

0x09 for

AD9680-

1250;

0x0A for

AD9680-

1000

V p-p

differ-

ential;

use in

conjunc-

tion with

Reg.

1001 = 1.58 V (default for AD9680-1250)

1010 = 1.70 V (default for AD9680-1000 and

AD9680-820)

1011 = 1.82 V

and

1100 = 2.06 V (default for AD9680-500)

AD9680-

820;

0x030

0x0C for

AD9680-

500

0x030

Input full-

scale control

(local)

0

Full-scale control

0

Used in

conjunc-

tion with

Reg.

See Table 10 for recommended settings

for different frequency bands;

default values:

AD9680-1250, AD9680-1000 = 110

AD9680-820 = 101

0x025

AD9680-500 = 001

AD9680-500 = 110 (for <1.82 V)

Rev. C | Page 84 of 97

Data Sheet

AD9680

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

ADC Function Registers

0x024

V_1P0

control

0

1.0 V

0x00

reference

select

0 =

internal

1 =

external

0x028

Temperature

diode

0

Diode

selection

0 =

no diode

selected

1 =

0x00

Used in

conjunc-

tion with

Reg.

0x040

temper-

ature

diode

selected

0x03F

0x040

PDWN/

STBY pin

control (local) enabled

0 = PDWN/

STBY

0

0x00

0x3F

Used in

conjunc-

tion with

Reg.

1 =

disabled

0x040

Chip pin

control

PDWN/STBY function

00 = power down

01 = standby

Fast Detect B (FD_B)

000 = Fast Detect B output

Fast Detect A (FD_A)

000 = Fast Detect A output

001 = JESD204B LMFC output

010 = JESD204B internal SYNC~ output

111 = disabled

10 = disabled

010 = JESD204B internal SYNC~ output

011 = temperature diode

111 = disabled

0x10B

0x10C

Clock divider

0

000 = divide by 1

001 = divide by 2

011 = divide by 4

111 = divide by 8

0x00

Clock divider

phase (local)

0

Independently controls Channel A and Channel B clock

divider phase offset

0000 = 0 input clock cycles delayed

0001 = ½ input clock cycles delayed

0010 = 1 input clock cycles delayed

0011 = 1½ input clock cycles delayed

0100 = 2 input clock cycles delayed

0101 = 2½ input clock cycles delayed

…

1111 = 7½ input clock cycles delayed

Clock divider negative

skew window

00 = no negative skew

01 = 1 device clock of

negative skew

Clock divider positive

skew window

00 = no positive skew

01 = 1 device clock of

positive skew

0x00

Clock

divider

must be

>1

0x10D

Clock divider

and SYSREF

control

Clock

0

divider

auto phase

adjust

0 =

disabled

1 =

10 = 2 device clocks of

negative skew

positive skew

enabled

11 = 3 device clocks of

negative skew

11 = 3 device clocks of

positive skew

0x117

Clock delay

control

0

Clock fine

delay

adjust

enable

0 =

disabled

1 =

0x00

Enabling

the clock

fine delay

adjust

causes a

datapath

reset

enabled

Rev. C | Page 85 of 97

AD9680

Data Sheet

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x118

Clock fine

delay (local)

Clock Fine Delay Adjust[7:0],

twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps

0x00

Used in

con-

≤ −88 = −151.7 ps skew

−87 = −150 ps skew

…

junction

with Reg.

0x0117

0 = 0 ps skew

…

≥ +87 = +150 ps skew

0x11C

0x120

Clock status

0

0 = no

input

clock

detected

1 = input

clock

Read

only

detected

SYSREF

Control 1

SYSREF

flag reset

0 =

normal

opera-

tion

1 = flags

held in

reset

SYSREF

transition

select

0 = low to

high

1 = high to

low

CLK

edge

select

0 = rising

SYSREF mode select

00 = disabled

01 = continuous

10 = N shot

0

0x00

1 = falling

0x121

0x123

SYSREF

Control 2

0

SYSREF N-shot ignore counter select

0000 = next SYSREF only

0001 = ignore the first SYSREF transition

0010 = ignore the first two SYSREF transitions

…

0x00

Mode

select

(Reg

0x120,

Bits [2:1])

must be

N-shot

1111 = ignore the first 16 SYSREF transitions

SYSREF

timestamp

delay control

SYSREF timestamp delay, Bits[6:0]

Ignored

when

Reg.

0x00 = no delay

0x01 = 1 clock delay

…

0x01FF

0x7F = 127 clocks delay

= 0x00

0x128

0x129

SYSREF

Status 1

SYSREF hold status, Register 0x128[7:4],

refer to Table 28

SYSREF setup status, Register 0x128[3:0],

Read

only

refer to Table 28

SYSREF and

clock divider

status

0

Clock divider phase when SYSREF was captured

0000 = in-phase

Read

only

0001 = SYSREF is ½ cycle delayed from clock

0010 = SYSREF is 1 cycle delayed from clock

0011 = 1½ input clock cycles delayed

0100 = 2 input clock cycles delayed

0101 = 2½ input clock cycles delayed

…

1111 = 7½ input clock cycles delayed

0x12A

0x1FF

SYSREF

counter

SYSREF counter, Bits[7:0] increments when a SYSREF is captured

Read

only

Chip sync

mode

Synchronization mode

00 = normal

0x00

01 = timestamp

0x200

0x201

0x228

Chip

application

mode

0

Chip Q

ignore

0 = normal

(I/Q)

1 = ignore

(I only)

0

Chip operating mode

00 = full bandwidth mode

01 = DDC 0 on

10 = DDC 0 and DDC 1 on

11 = DDC 0, DDC 1,

0x00

DDC 2, and DDC 3 on

Chip

decimation

ratio

0

Chip decimation ratio select

000 = full sample rate (decimate = 1)

0x00

001 = decimate by 2

010 = decimate by 4

011 = decimate by 8

100 = decimate by 16

Customer

offset

Offset adjust in LSBs from +127 to −128 (twos complement format)

Rev. C | Page 86 of 97

Data Sheet

AD9680

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x245

Fast detect

(FD) control

(local)

0

Force

FD_A/

FD_B pins; pins if force

0 = normal pins is true,

Force value of

FD_A/FD_B

0

Enable

fast detect

output

0x00

function;

1 = force

to value

this value is

output on FD

pins

0x247

0x248

0x249

0x24A

0x24B

0x24C

0x26F

FD upper

threshold

LSB (local)

Fast detect upper threshold, Bits[7:0]

0x00

FD upper

threshold

MSB (local)

0

Fast detect upper threshold, Bits[12:8]

FD lower

threshold

LSB (local)

Fast detect lower threshold, Bits[7:0]

FD lower

threshold

MSB (local)

0

Fast detect lower threshold, Bits[12:8]

FD dwell

time LSB

(local)

Fast detect dwell time, Bits[7:0]

FD dwell

time MSB

(local)

Fast detect dwell time, Bits[15:8]

Signal

monitor

synchroniza-

tion control

0

Synchronization mode

00 = disabled

Refer to

the

Signal

Monitor

section

01 = continuous

11 = one shot

0x270

Signal

0

Peak

0

0x00

monitor

control (local)

detector

0 =

disabled

1 =

enabled

0x271

0x272

0x273

0x274

Signal

Monitor

Period

Register 0

(local)

Signal monitor period, Bits[7:0]

Signal monitor period, Bits[15:8]

Signal monitor period, Bits[23:16]

0x80

0x00

0x01

In deci-

mated

output

clock

cycles

Signal

Monitor

Period

Register 1

(local)

In deci-

mated

output

clock

cycles

Signal

Monitor

Period

Register 2

(local)

In deci-

mated

output

clock

cycles

Signal

0

Result

update

1 =

0

Result

selection

0 =

reserved

1 = peak

detector

monitor

result control

(local)

update

results

(self clear)

0x275

Signal

Monitor

Result

Signal monitor result, Bits[7:0]

When Register 0x0274[0] = 1, Result Bits[19:7] = Peak Detector Absolute Value[12:0]; Result Bits[6:0] = 0

Read

only

Updated

based on

Reg.

Register 0

(local)

0x274[4]

Rev. C | Page 87 of 97

AD9680

Data Sheet

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x276

0x277

0x278

0x279

0x27A

Signal

Monitor

Result

Register 1

(local)

Signal monitor result, Bits[15:8]

Read

only

Updated

based on

Reg.

0x274[4]

Signal

Monitor

Result

Register 1

(local)

0

Signal monitor result, Bits[19:16]

Read

only

Updated

based on

Reg.

0x274[4]

Signal

monitor

period

counter

result (local)

Period count result, Bits[7:0]

Read

only

Updated

based on

Reg.

0x274[4]

Signal

monitor

SPORT over

JESD204B

control (local)

0

00 = disabled

11 = enable

0x00

SPORT over

JESD204B

input

Peak

0

detector

0 =

selection

(local)

disabled

1 =

enabled

DDC Function Registers (See the Digital Downconverter (DDC) Section)

0x300

DDC

0

DDC NCO

soft reset

0 = normal

operation

1 = reset

0

Synchronization mode

(triggered by SYSREF )

00 = disabled

synchro-

nization

control

01 = continuous

11 = one shot

IF (intermediate

Complex

to real

enable

0 =

0

Decimation rate select

(complex to real

disabled)

11 = decimate by 2

00 = decimate by 4

01 = decimate by 8

10 = decimate by 16

(complex to real

enabled)

0x00

0x310

DDC 0

control

Mixer

select

0 = real

mixer

1 =

complex

mixer

Gain

select

0 = 0 dB

gain

1 = 6 dB

gain

frequency) mode

00 = variable IF mode

(mixers and NCO

enabled)

01 = 0 Hz IF mode (mixer 1 =

bypassed, NCO disabled) enabled

10 = f_S/4 Hz IF mode (f_s/4

downmixing mode)

disabled

11 = test mode (mixer

inputs forced to +f_S,

11 = decimate by 1

00 = decimate by 2

01 = decimate by 4

10 = decimate by 8

NCO enabled)

0x311

DDC 0 input

selection

0

Q input

select

0 = Ch A

1 = Ch B

0

I input

select

0 = Ch A

1 = Ch B

0x00

Refer to

the DDC

section

0x314

0x315

DDC 0

frequency

LSB

DDC 0 NCO frequency value, Bits[7:0]

twos complement

0x00

DDC 0

frequency

MSB

X

DDC 0 NCO frequency value, Bits[11:8]

twos complement

0x320

0x321

DDC 0 phase

LSB

DDC 0 NCO phase value, Bits[7:0]

twos complement

0x00

DDC 0 phase

MSB

X

DDC 0 NCO phase value, Bits[11:8]

twos complement

Rev. C | Page 88 of 97

Data Sheet

AD9680

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

DDC 0

output test

mode

selection

0

Q output

test mode

enable

0 = disabled

1 = enabled

from

0

I output

test mode

enable

0 =

disabled

1 =

0x00

Refer to

the DDC

section

0x327

Channel B

enabled

from

Channel A

IF (intermediate

Complex

to real

enable

0 =

0

Decimation rate select

(complex to real

disabled)

11 = decimate by 2

00 = decimate by 4

01 = decimate by 8

10 = decimate by 16

(complex to real

enabled)

0x00

0x330

DDC 1

control

Mixer

select

0 = real

mixer

1 =

Gain

select

0 = 0 dB

gain

1 = 6 dB

gain

frequency) mode

00 = variable IF mode

(mixers and NCO

enabled)

01 = 0 Hz IF mode (mixer 1 =

bypassed, NCO disabled) enabled

10 = f_ADC/4 Hz IF mode

(f_ADC/4 downmixing

disabled

complex

mixer

mode)

11 = decimate by 1

00 = decimate by 2

01 = decimate by 4

10 = decimate by 8

11 = test mode (mixer

inputs forced to +f_S,

NCO enabled)

0x331

DDC 1 input

selection

0

Q input

select

0 = Ch A

1 = Ch B

0

I input

select

0 = Ch A

1 = Ch B

0x05

Refer to

the DDC

section

0x334

0x335

DDC 1

frequency

LSB

DDC 1 NCO frequency value, Bits[7:0]

twos complement

0x00

DDC 1

frequency

MSB

X

DDC 1 NCO frequency value, Bits[11:8]

twos complement

0x340

0x341

0x347

DDC 1 phase

LSB

DDC 1 NCO phase value, Bits[7:0]

twos complement

0x00

DDC 1 phase

MSB

X

0

X

0

X

0

X

DDC 1 NCO phase value, Bits[11:8]

twos complement

Q output

0

DDC 1

output test

mode

0

I output

test mode

enable

0 =

disabled

1 =

Refer to

the DDC

section

test mode

enable

0 = disabled

1 = enabled

from Ch B

selection

enabled

from Ch A

IF mode

00 = variable IF mode

(mixers and NCO

enabled)

01 = 0 Hz IF mode (mixer disabled

bypassed, NCO disabled) 1 =

10 = f_ADC/4 Hz IF mode

(f_ADC/4 downmixing

mode)

Complex

to real

enable

0 =

0

Decimation rate select

(complex to real

disabled)

11 = decimate by 2

00 = decimate by 4

01 = decimate by 8

10 = decimate by 16

(complex to real

enabled)

0x00

0x350

DDC 2

control

Mixer

select

0 = real

mixer

1 =

Gain

select

0 = 0 dB

gain

1 = 6 dB

gain

complex

mixer

enabled

11 = test mode (mixer

inputs forced to +f_S,

NCO enabled)

11 = decimate by 1

00 = decimate by 2

01 = decimate by 4

10 = decimate by 8

0x351

DDC 2 input

selection

0

Q input

select

0 = Ch A

0

I input

select

0 = Ch A

0x00

Refer to

the DDC

section

1 = Ch B

0x354

0x355

DDC 2

frequency

LSB

DDC 2 NCO frequency value, Bits[7:0]

twos complement

0x00

DDC2

frequency

X

DDC 2 NCO frequency value, Bits[11:8]

twos complement

MSB

Rev. C | Page 89 of 97

AD9680

Data Sheet

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x360

0x361

0x367

DDC 2 phase

LSB

DDC 2 NCO phase value, Bits[7:0]

twos complement

0x00

DDC 2 phase

MSB

X

0

X

0

X

0

X

DDC 2 NCO phase value, Bits[11:8]

twos complement

DDC 2

output test

mode

0

Q output

test mode

enable

0

I output

test mode

enable

0 =

disabled

1 =

Refer to

the DDC

section

selection

0 = disabled

1 = enabled

from Ch B

enabled

from Ch A

IF mode

Complex

to real

enable

0 =

0

Decimation rate select

(complex to real

disabled)

11 = decimate by 2

00 = decimate by 4

01 = decimate by 8

10 = decimate by 16

(complex to real

enabled)

0x00

0x370

DDC 3

control

Mixer

select

0 = real

mixer

1 =

Gain

select

0 = 0 db

gain

1 = 6 db

gain

00 = variable IF mode

(mixers and NCO

enabled)

01 = 0 Hz IF mode(mixer

bypassed, NCO disabled) 1 =

10 = f_ADC/4 Hz IF mode

(f_ADC/4 downmixing

mode)

disabled

complex

mixer

enabled

11 = test mode (mixer

inputs forced to +f_S,

NCO enabled)

11 = decimate by 1

00 = decimate by 2

01 = decimate by 4

10 = decimate by 8

0x371

DDC 3 input

selection

0

Q input

select

0 = Ch A

0

I input

select

0 = Ch A

0x05

Refer to

the DDC

section

1 = Ch B

0x374

0x375

DDC 3

frequency

LSB

DDC 3 NCO frequency value, Bits[7:0]

twos complement

0x00

DDC 3

frequency

MSB

X

DDC 3 NCO frequency value, Bits[11:8]

twos complement

0x380

0x381

0x387

DDC3 phase

LSB

DDC 3 NCO phase value, Bits[7:0]

twos complement

0x00

DDC 3 phase

MSB

X

0

X

0

X

0

X

DDC 3 NCO phase value, Bits[11:8]

twos complement

DDC 3

output test

mode

0

I output

test mode

enable

0 =

Refer to

the DDC

section

selection

disabled

1 =

enabled

from Ch A

Digital Outputs and Test Modes

Reset PN

long gen

0 = long

PN enable

1 = long

PN reset

Reset PN

short gen

0 = short

PN enable

1 = short

PN reset

Test mode selection

0000 = off, normal operation

0001 = midscale short

0010 = positive full scale

0011 = negative full scale

0100 = alternating checker board

0101 = PN sequence, long

0110 = PN sequence, short

0111 = 1/0 word toggle

0x00

0x550

ADC test

modes

(local)

User

0

pattern

selection

0 = conti-

nuous

repeat

1 = single

pattern

1000 = the user pattern test mode (used with

Register 0x0550, Bit 7 and User Pattern 1 to

User Pattern 4 registers)

1111 = ramp output

0x551

User Pattern

1 LSB

0

0x00

Used

with Reg.

0x550

and Reg.

0x573

Rev. C | Page 90 of 97

Data Sheet

AD9680

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x552

0x553

0x554

0x555

0x556

0x557

0x558

0x559

User Pattern

1 MSB

0

0x00

Used

with Reg.

0x550

and Reg.

0x573

User Pattern

2 LSB

0

Used

with Reg.

0x550

and Reg.

0x573

User Pattern

2 MSB

Used

with Reg.

0x550

and Reg.

0x573

User Pattern

3 LSB

Used

with Reg.

0x550

and Reg.

0x573

User Pattern

3 MSB

Used

with Reg.

0x550

and Reg.

0x573

User Pattern

4 LSB

Used

with Reg.

0x550

and Reg.

0x573

User Pattern

4 MSB

Used

with Reg.

0x550

and Reg.

0x573

Output Mode

Control 1

Converter Control Bit 1 selection

000 = tie low (1’b0)

Converter Control Bit 0 selection

000 = tie low (1’b0)

001 = overrange bit

011 = fast detect (FD) bit

101 = SYSREF

Only used when CS (Register 0x58F)

= 2 or 3

Only used when CS (Register 0x58F) = 3

0x55A

Output Mode

Control 2

0

Converter Control Bit 2 selection

000 = tie low (1’b0)

0x01

001 = overrange bit

011 = fast detect (FD) bit

101 = SYSREF

Used when CS (Register 0x58F) = 1, 2, or 3

0x561

0x562

Output

mode

0

Sample

invert

0 = normal

1 = sample

invert

Data format select

00 = offset binary

01 = twos complement

0x01

0x00

Output

Virtual

overrange

(OR) clear

Converter 7 Converter Converter 5 Converter 4 Converter

Converter 2

OR

0 = OR bit

enabled

1 = OR bit

cleared

Converter 1 Converter

OR

6 OR

0 = OR bit 0 = OR bit

enabled enabled

1 = OR bit 1 = OR bit

OR

3 OR

OR

0 OR

0 = OR bit

enabled

1 = OR bit

cleared

0 = OR bit

enabled

1 = OR bit

cleared

0 = OR bit

enabled

1 = OR bit

cleared

0 = OR bit

enabled

1 = OR bit

cleared

0 = OR bit

enabled

1 = OR bit

cleared

Virtual

Converter 2

OR

Virtual

Converter 1 Converter

OR

Virtual

0x00

Read

only

0x563

Output OR

status

Virtual

Converter 7 Converter Converter 5 Converter 4 Converter

OR

6 OR

OR

3 OR

0 OR

0 = no OR

1 = OR

occurred

0 = no

OR

1 = OR

0 = no OR

1 = OR

occurred

0 = no OR

1 = OR

occurred

0 = no OR

1 = OR

occurred

0 = no OR

1 = OR

occurred

0 = no OR

1 = OR

occurred

0 = no OR

1 = OR

occurred

Rev. C | Page 91 of 97

AD9680

Data Sheet

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x564

Output

channel

select

0

Converter

channel

swap

0x00

0 =

normal

channel

ordering

1 =

channel

swap

enabled

0x00 for

AD9680-

1250,

AD9680-

1000 and

AD9680-

820;

0x10 for

AD9680-

500

0x56E

JESD204B

lane rate

control

0

0 = serial

lane rate

≥6.25 Gbps

and

≤12.5 Gbps

1 = serial

lane rate

must be ≥

3.125 Gbps

and

0

≤6.25 Gbps

0x56F

0x570

JESD204B

PLL lock

status

PLL lock

0 = not

locked

0

0x00

Read

only

1 = locked

JESD204B

quick config-

uration

JESD204B quick configuration

L = number of lanes = 2^{Register 0x570, Bits[7:6]}

M = number of converters = 2^{Register 0x570, Bits[5:3]}

F = number of octets/frame = 2 ^{Register 0x570, Bits[2:0]}

0x88 for

AD9680-

1250,

Refer to

Table 26

and

AD9680- Table 27

1000 and

AD9680-

820;

0x49 for

AD9680-

500

Long

Lane synch-

ronization

0 = disable

FACI uses

/K28.7/

1 = enable

FACI uses

/K28.3/ and

/K28.7/

ILAS sequence mode

00 = ILAS disabled

01 = ILAS enabled

11 = ILAS always on test

mode

FACI

0 =

enabled

1 =

disabled

Link

0x14

0x571

JESD204B

Link Mode

Control 1

Standby

mode

0 = all

converter

outputs 0

1 = CGS

(/K28.5/)

Tail bit

(t) PN

0 =

disable

1 =

enable

T = N΄ −

N − CS

transport

layer test

0 =

disable

1 =

control

0 = active

1 = power

down

enable

SYNCINB

pin type

0 =

differential

1 = CMOS

0

8-bit/10-bit

bypass

0 = normal

8-/10-bit

bit invert

0 =

normal

1 = invert

the abcd

efghij

0

0x00

0x572

0x573

JESD204B

Link Mode

Control 2

SYNCINB pin control

00 = normal

10 = ignore SYNCINB

(force CGS)

11 = ignore SYNCINB

(force ILAS/user data)

SYNCINB

pin invert

0 = active

low

1 = active

high

1 = bypass

symbols

JESD204B

Link Mode

Control 3

CHKSUM mode

00 = sum of all 8-bit link

config registers

01 = sum of individual

link config fields

10 = checksum set to

zero

Test injection point

00 = N΄ sample input

01 = 10-bit data at

8-bit/10-bit output

(for PHY testing)

10 = 8-bit data at

scrambler input

JESD204B test mode patterns

0000 = normal operation (test mode disabled)

0001 = alternating checker board

0010 = 1/0 word toggle

0011 = 31-bit PN sequence—X³¹+ X²⁸+ 1

0100 = 23-bit PN sequence—X²³+ X¹⁸+ 1

0101 = 15-bit PN sequence—X¹⁵+ X¹⁴+ 1

0110 = 9-bit PN sequence—X⁹+ X⁵+ 1

0111 = 7-bit PN sequence—X⁷+ X⁶+ 1

1000 = ramp output

1110 = continuous/repeat user test

1111 = single user test

Rev. C | Page 92 of 97

Data Sheet

AD9680

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x574

JESD204B

Link Mode

Control 4

ILAS delay

0

Link layer test mode

000 = normal operation (link layer test

mode disabled)

001 = continuous sequence of /D21.5/

characters

0x00

0000 = transmit ILAS on first LMFC after SYNCINB

deasserted

0001 = transmit ILAS on second LMFC after

SYNCINB deasserted

…

100 = modified RPAT test sequence

101 = JSPAT test sequence

110 = JTSPAT test sequence

1111 = transmit ILAS on 16^thLMFC after SYNCINB

deasserted

0x578

0x580

0x581

0x583

0x584

0x585

0x586

0x58B

JESD204B

LMFC offset

0

LMFC phase offset value[4:0]

JESD204B Tx DID value[7:0]

0

0x00

0x01

0x03

0x8X

JESD204B

DID config

JESD204B

BID config

0

JESD204B Tx BID value, Bits[3:0]

JESD204B LID

Config 1

Lane 0 LID value, Bits[4:0]

Lane 1 LID value, Bits[4:0]

Lane 2 LID value, Bits[4:0]

Lane 3 LID value, Bits[4:0]

0

JESD204B LID

Config 2

JESD204B LID

Config 3

JESD204B LID

Config 4

JESD204B

parameters

SCR/L

JESD204B

scrambling

(SCR)

0

JESD204B lanes (L)

00 = 1 lane

01 = 2 lanes

0 =

11 = 4 lanes

disabled

1 =

Read only, see

Register 0x570

enabled

0x58C

JESD204B F

config

Number of octets per frame, F = Register 0x58C[7:0] + 1

0x88

0x1F

Read

only,

see Reg.

0x570

0x58D

0x58E

JESD204B K

config

0

Number of frames per multiframe, K = Register 0x58D[4:0] + 1

Only values where (F × K) mod 4 = 0 are supported

See Reg.

0x570

JESD204B M

config

Number of Converters per Link[7:0]

0x00 = link connected to one virtual converter (M = 1)

0x01 = link connected to two virtual converters (M = 2)

Read

only

0x03 = link connected to four virtual converters (M = 4)

0x07 = link connected to eight virtual converters (M = 8)

ADC converter resolution (N)

0x0F

0x58F

JESD204B

CS/N config

Number of control bits

(CS) per sample

00 = no control bits

(CS = 0)

01 = 1 control bit (CS =

1); Control Bit 2 only

10 = 2 control bits

(CS = 2); Control Bit 2

and 1 only

0

0x06 = 7-bit resolution

0x07 = 8-bit resolution

0x08 = 9-bit resolution

0x09 = 10-bit resolution

0x0A = 11-bit resolution

0x0B = 12-bit resolution

0x0C = 13-bit resolution

0x0D = 14-bit resolution

0x0E = 15-bit resolution

0x0F = 16-bit resolution

11 = 3 control bits

(CS = 3); all control bits

(2, 1, 0)

0x590

JESD204B N’

config

0

Subclass

support

(Subclass V)

0 =

ADC number of bits per sample (N’)

0x7 = 8 bits

0x2F

0xF = 16 bits

Subclass 0

(no deter-

ministic

latency)

1 =

Subclass 1

0x591

JESD204B S

config

0

1

Samples per converter frame cycle (S)

S value = Register 0x591[4:0] + 1

0x20

Read

only

Rev. C | Page 93 of 97

AD9680

Data Sheet

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x592

JESD204B HD HD value

0

Control words per frame clock cycle per link (CF)

CF value = Register 0x592, Bits[4:0]

0x80

Read

only

and CF

0 =

config

disabled

1 =

enabled

0x5A0

0x5A1

0x5A2

0x5A3

0x5B0

JESD204B

CHKSUM 0

CHKSUM value for SERDOUT0 , Bits[7:0]

CHKSUM value for SERDOUT1 , Bits[7:0]

CHKSUM value for SERDOUT2 , Bits[7:0]

CHKSUM value for SERDOUT3 , Bits[7:0]

0x81

0x82

0x84

0xAA

Read

only

JESD204B

CHKSUM 1

Read

only

JESD204B

CHKSUM 2

Read

only

JESD204B

CHKSUM 3

Read

only

JESD204B

lane power-

down

1

SERD-

OUT3

0 = on

1 = off

1

SERD-

OUT2

0 = on

1 = off

1

SERD-

OUT1

0 = on

1 = off

1

SERD-

OUT0

0 = on

1 = off

0x5B2

0x5B3

0x5B5

0x5B6

0x5BF

JESD204B

lane

SERDOUT0

assign

X

0

X

0

SERDOUT0 lane assignment

000 = Logical Lane 0

001 = Logical Lane 1

010 = Logical Lane 2

011 = Logical Lane 3

0x00

0x11

0x22

0x33

0x05

JESD204B

lane

SERDOUT1

assign

X

0

X

0

SERDOUT1 lane assignment

000 = Logical Lane 0

001 = Logical Lane 1

010 = Logical Lane 2

011 = Logical Lane 3

JESD204B

lane

SERDOUT2

assign

SERDOUT2 lane assignment

000 = Logical Lane 0

001 = Logical Lane 1

010 = Logical Lane 2

011 = Logical Lane 3

JESD204B

lane

SERDOUT3

SERDOUT3 lane assignment

000 = Logical Lane 0

001 = Logical Lane 1

010 = Logical Lane 2

011 = Logical Lane 3

assign

JESD

Swing voltage

serializer

drive adjust

0000 = 237.5 mV

0001 = 250 mV

0010 = 262.5 mV

0011 = 275 mV

0100 = 287.5 mV

0101 = 300 mV (default)

0110 = 312.5 mV

0111 = 325 mV

1000 = 337.5 mV

1001 = 350 mV

1010 = 362.5 mV

1011 = 375 mV

1100 = 387.5 mV

1101 = 400 mV

1110 = 412.5 mV

1111 = 425 mV

SERDOUT1

0 = disable

1 = enable

0

SERD-

OUT0

0 = disable

1 = enable

0x00

0x5C1

De-emphasis

select

0

SERD-

OUT3

0 =

0

SERD-

OUT2

0 =

0

disable

1 =

enable

1 =

enable

Rev. C | Page 94 of 97

Data Sheet

AD9680

Reg

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB) Default

Notes

0x5C2

0x5C3

0x5C4

0x5C5

De-emphasis

setting for

SERDOUT0

0

SERDOUT0 de-emphasis settings

0000 = 0 dB

0x00

0001 = 0.3 dB

0010 = 0.8 dB

0011 = 1.4 dB

0100 = 2.2 dB

0101 = 3.0 dB

0110 = 4.0 dB

0111 = 5.0 dB

De-emphasis

setting for

SERDOUT1

0

SERDOUT1 de-emphasis settings

0000 = 0 dB

0x00

0001 = 0.3 dB

0010 = 0.8 dB

0011 = 1.4 dB

0100 = 2.2 dB

0101 = 3.0 dB

0110 = 4.0 dB

0111 = 5.0 dB

De-emphasis

setting for

SERDOUT2

SERDOUT2 de-emphasis settings

0000 = 0 dB

0001 = 0.3 dB

0010 = 0.8 dB

0011 = 1.4 dB

0100 = 2.2 dB

0101 = 3.0 dB

0110 = 4.0 dB

0111 = 5.0 dB

De-emphasis

setting for

SERDOUT3 de-emphasis settings

0000 = 0 dB

SERDOUT3

0001 = 0.3 dB

0010 = 0.8 dB

0011 = 1.4 dB

0100 = 2.2 dB

0101 = 3.0 dB

0110 = 4.0 dB

0111 = 5.0 dB

Rev. C | Page 95 of 97

AD9680

Data Sheet

APPLICATIONS INFORMATION

plane must have several vias to achieve the lowest possible

POWER SUPPLY RECOMMENDATIONS

resistive thermal path for heat dissipation to flow through the

bottom of the PCB. These vias must be solder filled or plugged.

The number of vias and the fill determine the resulting θ_JA

measured on the board.

The AD9680 must be powered by the following seven supplies:

AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR =

1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.80 V.

For applications requiring an optimal high power efficiency and

low noise performance, it is recommended that the ADP2164

and ADP2370 switching regulators be used to convert the 3.3 V,

5.0 V, or 12 V input rails to an intermediate rail (1.8 V and 3.8 V).

These intermediate rails are then postregulated by very low

noise, low dropout (LDO) regulators (ADP1741, ADM7172,

and ADP125). Figure 174 shows the recommended power

supply scheme for the AD9680.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen on the PCB into several uniform sections. This

provides several tie points between the ADC and PCB during

the reflow process, whereas using one continuous plane with no

partitions only guarantees one tie point. See Figure 175 for a

PCB layout example. For detailed information on packaging

and the PCB layout of chip scale packages, see the AN-772

Application Note, A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP).

AVDD1

1.25V

ADP1741

1.8V

AVDD1_SR

1.25V

DVDD

1.25V

ADP1741

ADP125

DRVDD

1.25V

SPIVDD

(1.8V OR 3.3V)

3.6V

3.3V

AVDD3

3.3V

ADM7172

OR

AVDD2

2.5V

ADP1741

Figure 174. High Efficiency, Low Noise Power Solution for the AD9680

It is not necessary to split all of these power domains in all cases.

The recommended solution shown in Figure 174 provides the

lowest noise, highest efficiency power delivery system for the

AD9680. If only one 1.25 V supply is available, route to AVDD1

first and then tap it off and isolate it with a ferrite bead or a filter

choke, preceded by decoupling capacitors for AVDD1_SR, DVDD,

and DRVDD, in that order. This is shown as the optional path

in Figure 174. The user can employ several different decoupling

capacitors to cover both high and low frequencies. These capacitors

must be located close to the point of entry at the PCB level and

close to the devices, with minimal trace lengths.

Figure 175. Recommended PCB Layout of Exposed Pad for the AD9680

AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60)

AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) can be

used to provide a separate power supply node to the SYSREF

circuits of AD9680. If running in Subclass 1, the AD9680 can

support periodic one-shot or gapped signals. To minimize the

coupling of this supply into the AVDD1 supply node, adequate

supply bypassing is needed.

EXPOSED PAD THERMAL HEAT SLUG

RECOMMENDATIONS

The exposed pad on the underside of the ADC must be connected

to AGND to achieve the best electrical and thermal performance

of the AD9680. Connect an exposed continuous copper plane

on the PCB to the AD9680 exposed pad, Pin 0. The copper

Rev. C | Page 96 of 97

Data Sheet

AD9680

OUTLINE DIMENSIONS

9.10

9.00 SQ

8.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

49

64

1

48

0.50

BSC

EXPOSED

PAD

7.70

7.60 SQ

7.50

33

16

32

17

0.45

0.40

0.35

0.20 MIN

TOP VIEW

BOTTOM VIEW

7.50 REF

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WMMD

Figure 176. 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-15)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +85°C

Package Description²

Package Option

CP-64-15

AD9680BCPZ-1250

AD9680BCPZ-1000

AD9680BCPZ-820

AD9680BCPZ-500

AD9680BCPZRL7-1250

AD9680BCPZRL7-1000

AD9680BCPZRL7-820

AD9680BCPZRL7-500

AD9680-1250EBZ

AD9680-1000EBZ

AD9680-LF1000EBZ

AD9680-820EBZ

64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Evaluation Board for AD9680-1250

−40°C to +85°C

Evaluation Board for AD9680-1000

Evaluation Board for AD9680-1000 with 1 GHz Bandwidth

Evaluation Board for AD9680-820

AD9680-LF820EBZ

AD9680-500EBZ

Evaluation Board for AD9680-820 with 1 GHz Bandwidth

Evaluation Board for AD9680-500

AD9680-LF500EBZ

Evaluation Board for AD9680-500 with 1 GHz Bandwidth

¹Z = RoHS Compliant Part.

²The AD9680-1250EBZ, AD9680-1000EBZ, AD9680-820EBA, and AD9680-500EBZ evaluation boards are optimized for full analog input frequency range of 2 GHz.

registered trademarks are the property of their respective owners.

D11752-0-11/15(C)

Rev. C | Page 97 of 97


型号：	AD9680
厂家：	ADI
描述：	Dual Analog-to-Digital Converter
文件：	总99页 (文件大小：3113K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9680 [ADI]

相关型号：

AD9680-1000EBZ

AD9680-1250EBZ

AD9680-500EBZ

AD9680-820EBZ

AD9680-LF1000EBZ

AD9680-LF500EBZ

AD9680-LF820EBZ

AD9680BCPZ-1000

AD9680BCPZ-1250

AD9680BCPZ-500

AD9680BCPZ-820

AD9680BCPZRL7-1000