AD9699BBPZRL-3000_技术文档

Data Sheet

AD9699

14-Bit, 3 GSPS, JESD204B, Single Analog-to-Digital Converter

► 4 integrated digital downconverters

► 48-bit NCO

► 4 cascaded half-band filters

► Phase coherent NCO switching

► Up to 4 channels available

FEATURES

► JESD204B (Subclass 1) coded serial digital outputs

► Support for lane rates up to 16 Gbps per lane

► 2 W total power at 3 GSPS (default settings)

► Performance at −2 dBFS amplitude, 2.6 GHz input

► SFDR = 70 dBFS

► SNR = 57.2 dBFS

► Performance at −9 dBFS amplitude, 2.6 GHz input

► SFDR = 78 dBFS

► Serial port control

► Integer clock with divide by 2 and divide by 4 options

► Flexible JESD204B lane configurations

► On-chip dither

► SNR = 59.5 dBFS

APPLICATIONS

► Integrated input buffer

► Noise density = −152 dBFS/Hz

► 0.975 V, 1.9 V, and 2.5 V dc supply operation

► 9 GHz analog input full power bandwidth (−3 dB)

► Amplitude detect bits for efficient AGC implementation

► Diversity multiband and multimode digital receivers

► 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A

► Electronic test and measurement systems

► Phased array radar and electronic warfare

► DOCSIS 3.0 CMTS upstream receive paths

► HFC digital reverse path receivers

► LIDAR

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

Rev. 0

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Data Sheet

AD9699

TABLE OF CONTENTS

Features................................................................ 1

Applications........................................................... 1

Functional Block Diagram......................................1

General Description...............................................3

Product Highlights.............................................. 3

Specifications........................................................ 4

DC Specifications...............................................4

AC Specifications............................................... 5

Digital Specifications.......................................... 7

Switching Specifications.....................................8

Timing Specifications......................................... 8

Absolute Maximum Ratings.................................10

Thermal Resistance......................................... 10

ESD Caution.....................................................10

Pin Configuration and Function Descriptions.......11

Typical Performance Characteristics...................13

Equivalent Circuits...............................................19

Theory of Operation.............................................21

ADC Architecture..............................................21

Analog Input Considerations............................ 21

Voltage Reference............................................24

DC Offset Calibration....................................... 24

Clock Input Considerations.............................. 25

Power-Down/Standby Mode.............................27

Temperature Diode...........................................27

ADC Overrange and Fast Detect.........................29

ADC Overrange................................................29

Fast Threshold Detection (FD).........................29

ADC Application Modes and JESD204B Tx

Converter Mapping............................................30

Programmable FIR Filters................................... 31

Supported Modes.............................................31

Programming Instructions................................ 32

Digital Downconverter (DDC).............................. 33

DDC I/Q Output Selection................................ 33

DDC General Description.................................33

DDC Frequency Translation.............................35

DDC Decimation Filters....................................43

DDC Gain Stage...............................................48

DDC Complex to Real Conversion...................48

DDC Mixed Decimation Settings......................50

DDC Example Configurations.......................... 51

DDC Power Consumption................................ 53

Signal Monitor......................................................54

SPORT over JESD204B.................................. 54

Digital Outputs.....................................................56

Introduction to the JESD204B Interface...........56

JESD204B Overview........................................56

Functional Overview.........................................57

JESD204B Link Establishment.........................57

Physical Layer (Driver) Outputs....................... 59

f_S× 4 Mode...................................................... 60

Setting Up the AD9699 Digital Interface...........62

Deterministic Latency.......................................... 68

Subclass 0 Operation.......................................68

Subclass 1 Operation.......................................68

Multichip Synchronization....................................70

Normal Mode....................................................70

Timestamp Mode..............................................70

SYSREF Input..................................................71

SYSREF± Setup/Hold Window Monitor........... 73

Latency................................................................76

End to End Total Latency................................. 76

Example Latency Calculations......................... 76

LMFC Referenced Latency.............................. 76

Test Modes.......................................................... 78

ADC Test Modes.............................................. 78

JESD204B Block Test Modes...........................79

Serial Port Interface.............................................81

Configuration Using the SPI.............................81

Hardware Interface...........................................81

SPI Accessible Features.................................. 81

Memory Map........................................................82

Reading the Memory Map Register Table........82

Memory Map Register Details..........................82

Applications Information.................................... 119

Power Supply Recommendations.................. 119

Layout Guidelines...........................................119

AVDD1_SR (Pin E7) and AGND (Pin E6

and Pin E8)...................................................120

Outline Dimensions........................................... 121

Ordering Guide...............................................121

Evaluation Boards.......................................... 121

REVISION HISTORY

5/2021—Revision 0: Initial Version

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Data Sheet

AD9699

GENERAL DESCRIPTION

The AD9699 is a single, 14-bit, 3 GSPS analog-to-digital converter

(ADC). The device has an on-chip buffer and a sample-and-hold

circuit designed for low power, small size, and ease of use. This

product is designed to support applications capable of direct sam-

pling wide bandwidth analog signals of up to 5 GHz. The −3 dB

bandwidth of the ADC input is 9 GHz. The AD9699 is optimized

for wide input bandwidth, high sampling rate, excellent linearity, and

low power in a small package.

provides additional information about the signal being digitized by

the ADC.

The user can configure the Subclass 1 JESD204B-based high

speed serialized output in a variety of one-lane, two-lane, four-lane,

and eight-lane configurations, depending on the DDC configuration

and the acceptable lane rate of the receiving logic device. Multi-

device synchronization is supported through the SYSREF± and

SYNCINB± input pins.

The ADC core features a multistage, differential pipelined architec-

ture with integrated output error correction logic. The ADC features

wide bandwidth inputs supporting a variety of user-selectable input

ranges. An integrated voltage reference eases design considera-

tions. The analog input and clock signals are differential inputs.

The ADC data outputs are internally connected to four digital down-

converters (DDCs) through a crossbar multiplexer (mux). Each

DDC consists of up to five cascaded signal processing stages: a

48-bit frequency translator (numerically controlled oscillator (NCO)),

and up to four half-band decimation filters. The NCO has the

option to select preset bands over the general-purpose input/output

(GPIO) pins, which enables the selection of up to three bands.

Operation of the AD9699 between the DDC modes is selectable via

serial peripheral interface (SPI)-programmable profiles.

The AD9699 has flexible power-down options that allow significant

power savings when desired. All of these features can be program-

med using a 3-wire SPI.

The AD9699 is available in a Pb-free, 12 mm × 12 mm, 196-ball

BGA and is specified over the −40°C to +85°C ambient temperature

range. This product is protected by a U.S. patent.

Note that throughout this data sheet, multifunction pins, such as

FD/GPIO_A0, are referred to either by the entire pin name or by a

single function of the pin, for example, FD, when only that function

is relevant.

PRODUCT HIGHLIGHTS

1. Wide, input −3 dB bandwidth of 9 GHz supports direct RF

In addition to the DDC blocks, the AD9699 has several functions

that simplify the automatic gain control (AGC) function in a com-

munications receiver. The programmable threshold detector allows

monitoring of the incoming signal power using the fast detect

control bits in Register 0x0245 of the ADC. If the input signal level

exceeds the programmable threshold, the fast detect indicator goes

high. Because this threshold indicator has low latency, the user can

quickly turn down the system gain to avoid an overrange condition

at the ADC input. In addition to the fast detect outputs, the AD9699

also offers signal monitoring capability. The signal monitoring block

sampling of signals up to about 5 GHz.

2. Four integrated, wideband decimation filter and NCO blocks

supporting multiband receivers.

3. Fast NCO switching enabled through the GPIO pins.

4. An SPI controls various product features and functions to meet

specific system requirements.

5. Programmable fast overrange detection and signal monitoring.

6. On-chip temperature diode for system thermal management.

7. 12 mm × 12 mm, 196-ball BGA.

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Data Sheet

AD9699

SPECIFICATIONS

DC SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD =

1.9 V, specified maximum sampling rate, 1.54 V p-p full-scale differential input, input amplitude (A_IN) = −2.0 dBFS, L = 4, M = 1,

F = 1, and −20°C ≤ junction temperature (T_J) ≤ +100°C, unless otherwise noted. The T_Jrange of −20°C to +100°C translates to a T_Arange of

−40°C to +85°C. Typical specifications represent performance at T_J= 40°C (T_A= 25°C).

Table 1.

Parameter

Min

Typ

Max

Unit

RESOLUTION

14

Bits

ACCURACY

No Missing Codes

Guaranteed

Offset Error

0

% FSR

LSB

Gain Error

−6.07

−0.59

−25.4

±1

±0.4

±6

+6.07

+0.68

+18.1

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

LSB

±15

440

0.5

5.6

ppm/°C

V

Gain Error

INTERNAL VOLTAGE REFERENCE

INPUT-REFERRED NOISE

ANALOG INPUTS

LSB rms

Differential Input Voltage Range

1.54

1.35

200

0.25

−7

V p-p

V

Common-Mode Voltage (V_CM

Differential Input Resistance

)

1.33

1.54

Ω

Differential Input Capacitance

Differential Input Return Loss at 2.1 GHz¹

pF

dB

−3 dB Bandwidth

POWER SUPPLY

AVDD1

9

GHz

0.95

1.85

2.44

0.95

1.85

0.975

1.9

1.0

V

AVDD2

1.95

2.56

1.0

V

AVDD3

2.5

V

AVDD1_SR

DVDD

0.975

1.9

V

1.0

V

DRVDD1

DRVDD2

SPIVDD

I_AVDD1

1.0

V

1.95

408.5

483.9

62.57

34

V

1.9

V

335

420

56

mA

I_AVDD2

I_AVDD3

I_{AVDD1_SR}

I_DVDD

22

285

420

30

518.4

491.6

33.5

0.996

2

I_DRVDD1

I_DRVDD2

I_SPIVDD

0.20

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Data Sheet

AD9699

SPECIFICATIONS

Table 1.

Parameter

Min

Typ

Max

Unit

POWER CONSUMPTION

Total Power Dissipation (Including Output Drivers)³

Power-Down Dissipation

2.0

250

1.0

2.472

594

W

mW

Standby⁴

1.41

1

For more information, see the Analog Input Considerations section.

2

All lanes running. Power dissipation on DRVDD1 changes with the lane rate and number of lanes used.

3

Default mode. No DDCs used.

4

Can be controlled by the SPI.

AC SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD =

1.9 V, specified maximum sampling rate, 1.54 V p-p full-scale differential input, default SPI settings, and −20°C ≤ T_J≤ +100°C, unless otherwise

noted. The T_Jrange of −20°C to +100°C translates to a T_Arange of −40°C to +85°C. Typical specifications represent performance at T_J= 40°C

(T_A= 25°C).

Table 2.

A_IN= −2 dBFS

Typ

A_IN= −9 dBFS

Parameter¹

Min

Max

Min

Typ

Max

Unit

NOISE DENSITY²

1.54 V p-p Setting

1.85 V p-p Setting

NOISE FIGURE

−152

−154

24.5

−152

−154

24.5

dBFS/Hz

dB

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 255 MHz

60.2

61.4

59.8

59.5

58.7

58.2

57.2

55.1

60.2

61.8

60.2

60.0

59.8

59.5

58.6

dBFS

f_IN= 255 MHz (1.85 V p-p Setting)

f_IN= 765 MHz

f_IN= 900 MHz

f_IN= 1800 MHz

f_IN= 2100 MHz

f_IN= 2600 MHz

50.2

f_IN= 3950 MHz

SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)

f_IN= 255 MHz

59.7

60.0

58.8

58.6

57.4

56.7

56.1

52.8

60.0

61.5

60.0

59.9

59.7

59.4

59.2

58.2

dBFS

f_IN= 255 MHz (1.85 V p-p Setting)

f_IN= 765 MHz

f_IN= 900 MHz

f_IN= 1800 MHz

f_IN= 2100 MHz

f_IN= 2600 MHz

44.1

f_IN= 3950 MHz

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Data Sheet

AD9699

SPECIFICATIONS

Table 2.

A_IN= −2 dBFS

Typ

A_IN= −9 dBFS

Parameter¹

Min

Max

Min

Typ

Max

Unit

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 255 MHz

9.6

9.5

9.4

9.2

9.1

9.0

8.5

9.7

9.6

9.5

9.4

Bits

dBFS

Bits

f_IN= 765 MHz

f_IN= 900 MHz

f_IN= 1800 MHz

f_IN= 2100 MHz

f_IN= 2600 MHz

8.1

f_IN= 3950 MHz

SPURIOUS-FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD HARMONIC

f_IN= 255 MHz

71

65

71

69

67

70

58

78

83

79

78

81

73

78

73

dBFS

f_IN= 255 MHz (1.85 V p-p Setting)

f_IN= 765 MHz

f_IN= 900 MHz

f_IN= 1800 MHz

f_IN= 2100 MHz

f_IN= 2600 MHz

47.2

f_IN= 3950 MHz

WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC

f_IN= 255 MHz

−89

−90

−89

−81

−80

−84

−80

−90

−89

−90

−94

−98

−90

dBFS

f_IN= 255 MHz (1.85 V p-p Setting)

f_IN= 765 MHz

f_IN= 900 MHz

f_IN= 1800 MHz

f_IN= 2100 MHz

f_IN= 2600 MHz

−73.8

f_IN= 3950 MHz

TWO-TONE, THIRD-ORDER INTERMODULATION DISTORTION (IMD3)

f_IN1= 1.842 GHz, f_IN2= 1.847 GHz, A_IN1and A_IN2= −8.0 dBFS

f_IN1= 1.842 GHz, f_IN2= 1.847 GHz, A_IN1and A_IN2= −15.0 dBFS

f_IN1= 2.62 GHz, f_IN2= 2.69 GHz, A_IN1and A_IN2= −8.0 dBFS

f_IN1= 2.62 GHz, f_IN2= 2.69 GHz, A_IN1and A_IN2= −15.0 dBFS

−73

−69

−75

dBFS

−87

−88

f_IN1= 2.62 GHz, f_IN2= 2.69 GHz, A_IN1and A_IN2= −8.0 dBFS, Full-Scale Voltage (V_FS) = 1.02 V

p-p

f_IN1= 2.62 GHz, f_IN2= 2.69 GHz, A_IN1and A_IN2= −15.0 dBFS, V_FS= 1.02 V p-p

ANALOG INPUT BANDWIDTH, FULL POWER³

−111

5

dBFS

GHz

5

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.

Noise density is measured at a low analog input frequency (30 MHz).

2

3

Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.

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Data Sheet

AD9699

SPECIFICATIONS

DIGITAL SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD

= 1.9 V, specified maximum sampling rate, 1.54 V p-p full-scale differential input, A_IN= −2.0 dBFS, L = 4, M = 1, F = 1, and −20°C ≤ T_J≤

+100°C, unless otherwise noted. The T_Jrange of −20°C to +100°C translates to a T_Arange of −40°C to+85°C. Typical specifications represent

performance at T_J= 40°C (T_A= 25°C).

Table 3.

Parameter

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

Low voltage differential signaling (LVDS)/low voltage positive emitter-

coupled logic (LVPECL)

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

300

800

1800

mV p-p

0.675

106

V

Ω

0.9

pF

dB

Differential Input Return Loss at 3 GHz¹

SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−)

Logic Compliance

−9.4

LVDS/LVPECL

Differential Input Voltage

400

800

0.675

18

1800

2.0

mV p-p

V

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance (Differential)

kΩ

1

pF

LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD/GPIO_A0, GPIO_B0,

GPIO_A1, GPIO_B1)

Logic Compliance

Logic 1 Voltage

CMOS

0.65 × SPIVDD

0

V

Logic 0 Voltage

0.35 × SPIVDD

V

Input Resistance

30

kΩ

LOGIC OUTPUTS (SDIO, FD)

Logic Compliance

Logic 1 Voltage (Output High Current (I_OH) = 4 mA)

Logic 0 Voltage (Output Low Current (I_OL) = 4 mA)

SYNCIN INPUT (SYNCINB+/SYNCINB−)

Logic Compliance

SPIVDD − 0.45V

0

V

0.45

LVDS/LVPECL

800

Differential Input Voltage

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

400

1800

2.0

mV p-p

V

0.675

18

kΩ

1

pF

SYNCINB+ INPUT

Logic Compliance

CMOS

2.6

Logic 1 Voltage

0.9 × DRVDD1

2 × DRVDD1

V

Logic 0 Voltage

0.1 × DRVDD1

V

Input Resistance

kΩ

DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7)

Logic Compliance

Source series terminated (SST)

Differential Output Voltage

Differential Termination Impedance

360

80

560

100

770

120

mV p-p

Ω

1

Reference impedance = 100 Ω.

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Data Sheet

AD9699

SPECIFICATIONS

SWITCHING SPECIFICATIONS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD

= 1.9 V, specified maximum sampling rate, 1.54 V p-p full-scale differential input, A_IN= −2.0 dBFS, default SPI settings, and −20°C ≤ T_J≤

+100°C, unless otherwise noted. The T_Jrange of −20°C to +100°C translates to a T_Arange of −40°C to +85°C. Typical specifications represent

performance at T_J= 40°C (T_A= 25°C).

Table 4.

Parameter

Min

Typ

Max

Unit

CLOCK

Clock Rate (at CLK+ and CLK− Pins)

Sample Rate¹

3

6

GHz

MSPS

ps

2500

3000

166.67

3100

192.31

Clock Pulse Width High

Clock Pulse Width Low

OUTPUT PARAMETERS

Unit Interval (UI)²

161.29

ps

62.5

66.67

26

592.6

ps

Rise Time (t_R) (20% to 80% into 100 Ω Load)

Fall Time (t_F) (20% to 80% into 100 Ω Load)

Phase-Locked Loop (PLL) Lock Time

Data Rate per Channel (Nonreturn to Zero)³

LATENCY⁴

ps

26

ps

5

ms

Gbps

1.6875

15

16

Pipeline Latency⁵

75

26

Clock cycles

Fast Detect Latency

WAKE-UP TIME

Standby

400

15

µs

Power-Down

ms

NCO CHANNEL SELECTION TO OUTPUT

APERTURE

8

Clock cycles

Aperture Delay (t_A)

250

55

1

ps

Aperture Uncertainty (Jitter, t_J)

Out of Range Recovery Time

fs rms

Clock cycles

1

The maximum sample rate is the clock rate after the divider.

2

Baud rate = 1/UI. A subset of this range can be supported.

3

Default L = 8. This number can be changed based on the sample rate and decimation ratio.

4

No DDCs used. L = 8, M = 2, and F = 1.

5

Refer to the End to End Total Latency section for more details.

TIMING SPECIFICATIONS

Table 5.

Parameter

Description

Min

Typ

Max

Unit

CLK+ to SYSREF+ TIMING REQUIREMENTS

t_{SU_SR}

Device clock to SYSREF+ setup time

Device clock to SYSREF+ hold time

−65

95

ps

t_{H_SR}

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

2

ns

2

40

2

Setup time between CSB and SCLK

t_H

Hold time between CSB and SCLK

2

t_HIGH

Minimum period that SCLK must be in a logic high state

10

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Data Sheet

AD9699

SPECIFICATIONS

Table 5.

Parameter

Description

Min

Typ

Max

Unit

t_LOW

Minimum period that SCLK must be in a logic low state

10

ns

t_ACCESS

Maximum time delay between the falling edge of SCLK and output data valid for

a read operation

6

10

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an input, relative to

the SCLK rising edge (not shown in Figure 4)

10

ns

Timing Diagrams

Figure 2. Data Output Timing Diagram

Figure 3. SYSREF± Setup and Hold Timing Diagram

Figure 4. SPI Timing Diagram

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Data Sheet

AD9699

ABSOLUTE MAXIMUM RATINGS

Table 6.

THERMAL RESISTANCE

Parameter

Rating

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to PCB

thermal design is required. θ_JAis the natural convection junction-to-

ambient thermal resistance measured in a one cubic foot sealed

enclosure. θ_{JC_TOP}is the junction-to-case thermal resistance. Ψ_JBis

the junction-to-board thermal resistance. Ψ_JTmeasures the temper-

ature change between the junction and the top of the package (or

junction vs. top of package thermal resistance).

Electrical

AVDD1 to AGND

1.05 V

AVDD1_SR to AGND

AVDD2 to AGND

1.05 V

2.0 V

AVDD3 to AGND

2.70 V

DVDD to DGND

1.05 V

DRVDD1 to DRGND

DRVDD2 to DRGND

SPIVDD to DGND

AGND to DRGND

AGND to DGND

1.05 V

2.0 V

Table 7. Thermal Resistance

2.0 V

Package Type

θ_JA

θ_{JC_TOP}

Ψ_JB

Ψ_JT

Unit

−0.3 V to +0.3 V

AGND − 0.3 V to AVDD3 + 0.3 V

AGND − 0.3 V to AVDD1 + 0.3 V

DGND − 0.3 V to SPIVDD + 0.3 V

2.5 V

BP-196-4¹

16.26

1.4

5.44

1.68

°C/W

1

DGND to DRGND

VIN±x to AGND

Test Condition 1: Thermal impedance simulated values are based on JEDEC

2S2P thermal test board with 190 thermal vias. See JEDEC JESD51.

CLK± to AGND

SCLK, SDIO, CSB to DGND

PDWN/STBY to DGND

SYSREF± to AGND

SYNCINB± to DRGND

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Charged devi-

ces and circuit boards can discharge without detection. Although

this product features patented or proprietary protection circuitry,

damage may occur on devices subjected to high energy ESD.

Therefore, proper ESD precautions should be taken to avoid

performance degradation or loss of functionality.

2.5 V

T_JRange

Storage Temperature Range, T_A

−20°C to +100°C

−40°C to +85°C

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress

rating only; functional operation of the product at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum operat-

ing conditions for extended periods may affect product reliability.

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Data Sheet

AD9699

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration (Top View)

Table 8. Pin Function Descriptions¹

Pin No.

Mnemonic

Type

Description

Power Supplies

A3, A12, B3, B12, C3, C12

A4, A5, A10, A11, B4, B11

AVDD1

AVDD1²

AVDD2

Power

Analog Power Supply (0.975 V Nominal).

Analog Power Supply for the Clock Domain (0.975 V Nominal).

Analog Power Supply (1.9 V Nominal).

A1, A2, A13, A14, B1, B2, B13, B14, C1,

C2, C13, C14

D1, D14, G1, G14

AVDD3

Power

Ground

Analog Power Supply (2.5 V Nominal).

E7

AVDD1_SR

SPIVDD

DVDD

Analog Power Supply for SYSREF± (0.975 V Nominal).

Digital Power Supply for SPI (1.9 V Nominal).

Digital Power Supply (0.975 V Nominal).

L3, L10

M14, N1, N2, N14, P1, P2, P14

M5 to M8, M11

M13

DRVDD1

DRVDD2

Digital Driver Power Supply (0.975 V Nominal).

Digital Driver Power Supply (1.9 V Nominal).

Analog Ground. These pins connect to the analog ground plane.

B5, B10, C4, C5, C10, C11, D2 to D6, D9 to AGND

D13, E2 to E5, E9 to E13, F2 to F6, F9 to

F13, G2 to G13, H1 to H9, H11 to H14, J1

to J14

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Data Sheet

AD9699

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 8. Pin Function Descriptions¹

Pin No.

A6, A9, B6 to B9, C6 to C9, D7, D8

Mnemonic

Type

Description

AGND³

AGND⁴

AGND⁵

DGND

Ground

Ground Reference for the Clock Domain.

Ground Reference for SYSREF±.

Isolation Ground.

E6, E8

K1 to K14

L1, L12 to L14, M1, M2

Digital Control Ground Supply. These pins connect to the digital

ground plane.

M3, M4, M9, M10, M12, N3, N12, P3, P12

DRGND

Ground

Digital Driver Ground Supply. These pins connect to the digital

driver ground plane.

Analog

E14, F14

VIN−, VIN+

CLK+, CLK−

VREF

Input

ADC Analog Input Complement/True.

Clock Input True/Complement.

A7, A8

H10

Input

Input/DNC

0.50 V Reference Voltage Input/Do Not Connect. This pin is

configurable through the SPI as a no connect or an input. Do not

connect this pin if using the internal reference. This pin requires

a 0.50 V reference voltage input if using an external voltage

reference source.

DNC

E1, F1

DNC

Do not connect.

CMOS Inputs/Outputs

L2

L4

GPIO_B1

GPIO_B0

FD/GPIO_A0

GPIO_A1

Input/output

GPIO B1.

GPIO B0.

L9

Fast Detect Outputs/GPIO A0.

GPIO A1.

L11

Digital Inputs

F7, F8

SYSREF+, SYSREF−

Input

Active High JESD204B LVDS System Reference Input True/

Complement.

N13

P13

SYNCINB+

SYNCINB−

Input

Active Low JESD204B LVDS/CMOS Sync Input True.

Active Low JESD204B LVDS Sync Input Complement.

Data Outputs

N4, P4

SERDOUT7+, SERDOUT7−

SERDOUT6+, SERDOUT6−

SERDOUT5+, SERDOUT5−

SERDOUT4+, SERDOUT4−

SERDOUT3+, SERDOUT3−

SERDOUT2+, SERDOUT2−

SERDOUT1+, SERDOUT1−

SERDOUT0+, SERDOUT0−

Output

Lane 7 Output Data True/Complement.

Lane 6 Output Data True/Complement.

Lane 5 Output Data True/Complement.

Lane 4 Output Data True/Complement.

Lane 3 Output Data True/Complement.

Lane 2 Output Data True/Complement.

Lane 1 Output Data True/Complement.

Lane 0 Output Data True/Complement.

N5, P5

N6, P6

N7, P7

N8, P8

N9, P9

N10, P10

N11, P11

Digital Controls

L8

PDWN/STBY

Input

Power-Down Input (Active High). The operation of this pin depends

on the SPI mode and can be configured as power-down or

standby.

L5

L6

L7

CSB

Input

SPI Chip Select (Active Low).

SPI Serial Clock.

SCLK

SDIO

Input

Input/output

SPI Serial Data Input/Output.

1

See the Theory of Operation section and the Power Supply Recommendations section for more information on isolating the planes for optimal performance.

2

3

4

5

Denotes clock domain.

Denotes SYSREF± domain.

Denotes isolation domain.

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Data Sheet

AD9699

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V, SPIVDD =

1.9 V, sampling rate = 3000 MHz, 1.54 V p-p full-scale differential input, default buffer current settings, T_A= 25°C, and 128,000 fast Fourier

transform (FFT) sample, unless otherwise noted. See Table 10 for the recommended settings.

Figure 6. Single-Tone FFT at f_IN= 255 MHz (NSD is Noise Spectral Density)

Figure 9. Single-Tone FFT at f_IN= 1807 MHz

Figure 10. Single-Tone FFT at f_IN= 1807 MHz, A_IN= −9 dBFS

Figure 11. Single-Tone FFT at f_IN= 2100 MHz

Figure 7. Single-Tone FFT at f_IN= 765 MHz

Figure 8. Single-Tone FFT at f_IN= 905 MHz

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Data Sheet

AD9699

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 12. Single-Tone FFT at f_IN= 2100 MHz, A_IN= −9 dBFS

Figure 15. Single-Tone FFT at f_IN= 3957 MHz

Figure 13. Single-Tone FFT at f_IN= 2600 MHz

Figure 16. Single-Tone FFT at f_IN= 3957 MHz, A_IN= −9 dBFS

Figure 14. Single-Tone FFT at f_IN= 2600 MHz, A_IN= −9 dBFS

Figure 17. SNR vs. Input Frequency (f_IN), A_IN= −2 dBFS and −9 dBFS

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Data Sheet

AD9699

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 21. Two-Tone FFT, f_IN1= 1821.5 MHz, f_IN2= 1831.5 MHz,

Figure 18. SFDR vs. Input Frequency (f_IN), A_IN= −2 dBFS and −9 dBFS

A_IN1and A_IN2= −8 dBFS (IMD2 is Second-Order Intermodulation Distortion

and IMD3 is Third-Order Intermodulation Distortion)

Figure 22. Two-Tone FFT, f_IN1= 1821.5 MHz, f_IN2= 1831.5 MHz,

A_IN1and A_IN2= −15 dBFS

Figure 19. Second-Order Harmonic Distortion (HD2) vs. Input Frequency (f_IN),

A_IN= −2 dBFS and −9 dBFS

Figure 23. Two-Tone FFT, f_IN1= 2621.5 MHz, f_IN2= 2631.5 MHz,

A_IN1and A_IN2= −8 dBFS

Figure 20. Third-Order Harmonic Distortion (HD3)vs. Input Frequency (f_IN),

A_IN= −2 dBFS and −9 dBFS

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Data Sheet

AD9699

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 24. Two-Tone FFT, f_IN1= 2621.5 MHz, f_IN2= 2631.5 MHz,

A_IN1and A_IN2= −15 dBFS

Figure 27. Two-Tone FFT, f_IN1= 1800 MHz, f_IN2= 2100 MHz,

f_CLK= 2.94912 GHz, Decimation Ratio = 8, NCO Frequency = 1874.28 MHz

Figure 25. Two-Tone FFT, f_IN1= 2621.5 MHz, f_IN2= 2631.5 MHz,

Full-Scale Voltage = 1.1 V p-p, A_IN1and A_IN2= −8 dBFS

Figure 28. Two-Tone FFT, f_IN1= 1800 MHz, f_IN2= 2100 MHz,

f_CLK= 2.94912 GHz, Decimation Ratio = 8, NCO Frequency = 2176.92 MHz

Figure 26. Two-Tone FFT, f_IN1= 2621.5 MHz, f_IN2= 2631.5 MHz,

Full-Scale Voltage = 1.1 V p-p, A_IN1and A_IN2= −15 dBFS

Figure 29. Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

f_IN1= 1821.5 MHz, f_IN2= 1831.5 MHz

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Data Sheet

AD9699

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 30. Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN) with

f_IN1= 2621.5 MHz, f_IN2= 2631.5 MHz

Figure 33. SNR/SFDR vs. T_J, f_IN= 950 MHz, A_IN= −9 dBFS

Figure 31. SNR/SFDR vs. Input Amplitude (A_IN), f_IN= 950 MHz

Figure 34. Power vs. T_J, f_IN= 950 MHz

Figure 32. SNR/SFDR vs. Input Amplitude (A_IN), f_IN= 1800 MHz

Figure 35. SNR vs. Analog Input Frequency (f_IN) vs. Various Clock Amplitude

in Differential Voltages, A_IN= −2dBFS

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Data Sheet

AD9699

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 36. SNR vs. Sample Frequency (f_S), f_IN= 1.8 GHz, A_IN= −2 dBFS and

−9 dBFS

Figure 39. Input Bandwidth (See Figure 55 for the Input Configuration)

Figure 40. Input Referred Noise Histogram

Figure 37. SFDR vs. Sample Frequency (f_S), f_IN= 1.8 GHz, A_IN= −2 dBFS and

−9 dBFS

Figure 38. Power Dissipation vs. Sample Frequency (f_S), f_IN= 1.8 GHz,

A_IN= −2 dBFS

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Data Sheet

AD9699

EQUIVALENT CIRCUITS

Figure 43. SYSREF± Inputs

Figure 41. Analog Inputs

Figure 44. Digital Outputs

Figure 42. Clock Inputs

Figure 45. SYNCINB± Inputs

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Data Sheet

AD9699

EQUIVALENT CIRCUITS

Figure 49. PDWN/STBY Input

Figure 46. SCLK Input

Figure 50. VREF Input/Output

Figure 47. CSB Input

Figure 51. FD/GPIO_A0, GPIO_B0

Figure 52. GPIO_A1/GPIO_B1

Figure 48. SDIO Input

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Data Sheet

AD9699

THEORY OF OPERATION

The AD9699 has a single analog input channel and up to eight

JESD204B output lane pairs. The ADC samples wide bandwidth

analog signals of up to 5 GHz. The actual −3 dB roll-off of the

analog inputs is 9 GHz. The AD9699 is optimized for wide input

bandwidth, high sampling rate, excellent linearity, and low power in

a small package.

a low-pass filter that limits unwanted broadband noise. For more

information, refer to the Analog Dialogue article “Transformer-Cou-

pled Front-End for Wideband A/D Converters” (Volume 39, April

2005). In general, the precise front-end network component values

depend on the application.

Figure 53 shows the differential input return loss curve for the

analog inputs across a frequency range of 100 MHz to 10 GHz. The

reference impedance is 100 Ω.

The ADC core features a multistage, differential pipelined architec-

ture with integrated output error correction logic. The ADC features

wide bandwidth inputs supporting a variety of user-selectable input

ranges. An integrated voltage reference eases design considera-

tions.

The AD9699 has several functions that simplify the AGC function in

a communications receiver. The programmable threshold detector

allows monitoring of the incoming signal power using the fast

detect output bits of the ADC. If the input signal level exceeds

the programmable threshold, the fast detect indicator goes high.

Because this threshold indicator has low latency, the user can

quickly turn down the system gain to avoid an overrange condition

at the ADC input.

The Subclass 1 JESD204B-based high speed serialized output

data lanes can be configured in one-lane (L = 1), two-lane (L = 2),

four-lane (L = 4), and eight-lane (L = 8) configurations, depending

on the sample rate and the decimation ratio. Multiple device syn-

chronization is supported through the SYSREF± and SYNCINB±

input pins. The SYSREF± pin in the AD9699 can also be used as

a timestamp of data as it passes through the ADC and out of the

JESD204B interface.

ADC ARCHITECTURE

The architecture of the AD9699 consists of an input buffered pipe-

lined ADC. The input buffer provides a termination impedance to

the analog input signal. This termination impedance is set to 200

Ω. The equivalent circuit diagram of the analog input termination is

shown in Figure 41. The input buffer is optimized for high linearity,

low noise, and low power across a wide bandwidth.

Figure 53. Differential Input Return Loss

The input buffer provides a linear high input impedance (for ease of

drive) and reduces kickback from the ADC. The quantized outputs

from each stage are combined into a final 14-bit result in the digital

correction logic. The pipelined architecture permits the first stage to

operate with a new input sample. At the same time, the remaining

stages operate with the preceding samples. Sampling occurs on the

rising edge of the clock.

For best dynamic performance, the source impedances driving

VIN+ and VIN− must be matched such that common-mode settling

errors are symmetrical. These errors are reduced by the common-

mode rejection of the ADC. An internal reference buffer creates a

differential reference that defines the span of the ADC core.

Maximum SNR performance is achieved by setting the ADC to

the largest span in a differential configuration. For the AD9699,

the available span is programmable through the SPI port from

1.02 V p-p to 1.85 V p-p differential, with 1.54 V p-p differential

being the default.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9699 is a differential buffer. The internal

common-mode voltage of the buffer is 1.35 V. The clock signal

alternately switches the input circuit between sample mode and

hold mode.

Either a differential capacitor or two single-ended capacitors (or

a combination of both) can be placed on the inputs to provide

a matching passive network. These capacitors ultimately create

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Data Sheet

AD9699

THEORY OF OPERATION

Differential Input Configurations

There are several ways to drive the AD9699, either actively or

passively. Optimum performance is achieved by driving the analog

input differentially.

For applications where SNR and SFDR are key parameters, differ-

ential transformer coupling is the recommended input configuration

(see Figure 54 and Table 9) because the noise performance of

most amplifiers is not adequate to achieve the true performance of

the AD9699.

Figure 54. Differential Transformer Coupled Configuration for the AD9699

For low to midrange frequencies, a double balun or double trans-

former network (see Figure 54 and Table 9) is recommended for

optimum performance of the AD9699. For higher frequencies in the

second or third Nyquist zones, it is recommended to remove some

of the front-end passive components to ensure wideband operation

(see Figure 55 and Table 9).

Figure 55. Input Network Configuration for Frequencies > 5 GHz

Table 9. Differential Transformer-Coupled Input Configuration Component Values

Frequency Range

Transformer

R1

R2

R3

C1

C2

C3

C4

<5000 MHz

BAL-0006

25 Ω

10 Ω

0.1 μF

0.4 pF

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Data Sheet

AD9699

THEORY OF OPERATION

Input Common Mode

The analog input of the AD9699 is internally biased to the common-

mode voltage, as shown in Figure 57. The common-mode buffer

has a limited range in that the performance suffers greatly if the

common-mode voltage drops by more than 50 mV on either side of

the nominal value.

For dc-coupled applications, the recommended operation proce-

dure is to export the common-mode voltage to the VREF pin using

the SPI writes listed in this section. The common-mode voltage

must be set by the exported value to ensure proper ADC operation.

Disconnect the internal common-mode buffer from the analog input

using Register 0x1908.

When performing SPI writes for dc coupling operation, use the

following register settings in order:

Figure 57. Analog Input Controls

1. Set Register 0x1908, Bit 2 to disconnect the internal common-

mode buffer from the analog input. Note that this is a local

register.

2. Set Register 0x18A6 to 0x00 to turn off the voltage reference.

3. Set Register 0x18E6 to 0x00 to turn off the temperature diode

Using Register 0x1A4C and Register 0x1A4D, the buffer behavior

of the converter can be adjusted to optimize the SFDR over various

input frequencies and bandwidths of interest. Use Register 0x1910

to change the internal reference voltage. Changing the internal

reference voltage results in a change in the input full-scale voltage.

export.

When the input buffer current in Register 0x1A4C and Regis-

ter 0x1A4D is set, the amount of current required by the AVDD3

supply changes. This relationship is shown in Figure 58. For a

complete list of buffer current settings, see Table 44.

4. Set Register 0x18E0 to 0x02.

5. Set Register 0x18E1 to 0x9A.

6. Set Register 0x18E2 to 0x1E.

7. Set Register 0x18E3, Bit 6 to 1 to turn on the V_CMexport.

8. Set Register 0x18E3, Bits[5:0] to the buffer current setting (Reg-

ister 0x1A4C and Register 0x1A4D) to improve the accuracy of

the common-mode export.

Figure 56 shows the block diagram representation of a dc-coupled

application.

Figure 56. DC-Coupled Application Using the AD9699

Analog Input Buffer Controls and SFDR

Optimization

Figure 58. AVDD3 Current (I_AVDD3) vs. Buffer Current Setting (Buffer Control 1

Setting in Register 0x1A4C and Buffer Control 2 Setting in Register 0x1A4D)

The AD9699 input buffer offers flexible controls for the analog

inputs, such as buffer current, dc coupling, and input full-scale

adjustment. All the available controls are shown in Figure 57.

Table 10 shows the recommended values for the buffer current for

various Nyquist zones.

Table 10. SFDR Optimization for Input Frequencies

Frequency

Register 0x1A4C and Register 0x1A4D

DC to 1500 MHz

1500 MHz to 3000 MHz

>3000 MHz

400 µA/500 µA

500 µA

500 µA/700 µA

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Data Sheet

THEORY OF OPERATION

Dither

AD9699

The SPI Register 0x18A6 enables the user to either use this inter-

nal 0.5 V reference or to provide an external 0.5 V reference. When

using an external voltage reference, provide a 0.5 V reference.

The full-scale adjustment is made using the SPI, irrespective of the

reference voltage. For more information on adjusting the full-scale

level of the AD9699, refer to the Memory Map Register Details

section.

The AD9699 has internal on-chip dither circuitry that improves the

ADC linearity and SFDR, particularly at smaller signal levels. A

known but random amount of white noise is injected into the input

of the AD9699. This dither improves the small signal linearity within

the ADC transfer function and is precisely subtracted out digitally.

The dither is turned on by default and does not reduce the ADC

input dynamic range. The data sheet specifications and limits are

obtained with the dither turned on.

The SPI writes required to use the external voltage reference are as

follows:

1. Set Register 0x18E3 to 0x00 to turn off the V_CMexport.

The dither is on by default. It is not recommended to turn it off.

2. Set Register 0x18E6 to 0x00 to turn off the temperature diode

export.

Absolute Maximum Input Swing

3. Set Register 0x18A6 to 0x01 to turn on the external voltage

The absolute maximum input swing allowed at the inputs of the

AD9699 is 5.8 V p-p differential. Signals operating near or at this

level can cause permanent damage to the ADC. See Table 6 for

more information.

reference.

The use of an external reference may be necessary, in some

applications, to enhance the gain accuracy of the ADC or to

improve thermal drift characteristics. Figure 61 shows the typical

drift characteristics of the internal 0.5 V reference.

Figure 59. Internal Reference Configuration and Controls

Figure 61. Typical V_REFDrift

The external reference must be a stable 0.5 V reference. The

ADR130 is a sufficient option for providing the 0.5 V reference.

Figure 60 shows how the ADR130 can be used to provide the

external 0.5 V reference to the AD9699. The dashed lines show

unused blocks within the AD9699 while using the ADR130 to

provide the external reference.

DC OFFSET CALIBRATION

Figure 60. External Reference Using the ADR130

The AD9699 contains a digital filter to remove the dc offset from

the output of the ADC. For ac-coupled applications, this filter can

be enabled by setting Register 0x0701, Bit 7 to 0x1 and setting

Register 0x73B, Bit 7 to 0x0. The filter computes the average dc

signal and it is digitally subtracted from the ADC output. As a result,

the dc offset is improved to better than 70 dBFS at the output.

Because the filter does not distinguish between the source of dc

signals, this feature can be used when the signal content at dc is

VOLTAGE REFERENCE

A stable and accurate 0.5 V voltage reference is built into the

AD9699. This internal 0.5 V reference sets the full-scale input range

of the ADC. The full-scale input range can be adjusted via the

ADC input full-scale control register (Register 0x1910). For more

information on adjusting the input swing, see Table 44. Figure 59

shows the block diagram of the internal 0.5 V reference controls.

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Data Sheet

AD9699

THEORY OF OPERATION

not of interest. The filter corrects dc up to ±512 codes and saturates

beyond that.

Another option is to ac couple a differential CML or LVPECL signal

to the sample clock input pins, as shown in Figure 64 and Figure

65.

CLOCK INPUT CONSIDERATIONS

For optimum performance, drive the AD9699 sample clock inputs

(CLK+ and CLK−) with a differential signal. This signal is ac-cou-

pled to the CLK+ and CLK− pins via a transformer or clock drivers.

These pins are biased internally and require no additional biasing.

Figure 62 shows the differential input return loss curve for the

clock inputs across a frequency range of 100 MHz to 6 GHz. The

reference impedance is 100 Ω.

Figure 64. Differential LVPECL Sample Clock

Figure 65. Differential CML Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a varie-

ty of internal timing signals. The AD9699 contains an internal clock

divider and a duty cycle stabilizer comprised of DCS1 and DCS2,

which is enabled by default. In applications where the clock duty

cycle cannot be guaranteed to be 50%, a higher multiple frequency

clock along with the usage of the clock divider is recommended.

When it is not possible to provide a higher frequency clock, it

is recommended to turn on the DCS using Register 0x011C and

Register 0x011E. Figure 66 shows the different controls to the

AD9699 clock inputs. The output of the divider offers a 50% duty

cycle, high slew rate (fast edge) clock signal to the internal ADC.

See the Memory Map Register Details section for more details on

using this feature.

Figure 62. Differential Input Return Loss for the CLK± Inputs

Figure 63 shows a preferred method for clocking the AD9699. The

low jitter clock source is converted from a single-ended signal to a

differential signal using an RF transformer.

Input Clock Divider

The AD9699 contains an input clock divider with the ability to

divide the input clock by 1, 2, or 4. Select the divider ratios using

Register 0x0108 (see Figure 66).

The maximum frequency at the CLK± inputs is 6 GHz, which is the

limit of the divider. In applications where the clock input is a multiple

of the sample clock, take care to program the appropriate divider

Figure 63. Transformer-Coupled Differential Clock

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Data Sheet

AD9699

THEORY OF OPERATION

ratio into the clock divider before applying the clock signal. This

action ensures that the current transients during device startup are

controlled.

Figure 67. Clock Divider Phase and Delay Controls

The clock delay adjustment takes effect immediately when it is

enabled via SPI writes. Enabling the clock fine delay adjust in

Register 0x0110 causes a datapath reset. However, the contents

of Register 0x0111 and Register 0x0112 can be changed without

affecting the stability of the JESD204B link.

Clock Coupling Considerations

The AD9699 has many different domains within the analog supply

that control various aspects of the data conversion. The clock

domain is supplied by Pin A4, Pin A5, Pin A10, Pin A11, Pin B4,

and Pin B11 on the analog supply, AVDD1 (0.975 V) and Pin A6,

Pin A9, Pin B6, Pin B7, Pin B8, Pin B9, Pin C6, Pin C7, Pin C8, Pin

C9, Pin D7, and Pin D8 on the ground (AGND) side. To minimize

coupling between the clock supply domain and the other analog

domains, it is recommended to add a supply Q factor reduction

circuitry (de-Q) for Pin A4 and Pin A11, as well as Pin B4 and Pin

B11, as shown in Figure 68.

Figure 66. Clock Divider Circuit

The AD9699 clock divider can be synchronized using the external

SYSREF± input. A valid SYSREF± signal causes the clock divider

to reset to a programmable state. This synchronization feature

allows multiple devices to have their clock dividers aligned to

guarantee simultaneous input sampling. See Table 44 for more

information.

Input Clock Divider ½ Period Delay Adjust

The input clock divider in the AD9699 provides phase delay in

increments of ½ the input clock cycle. Register 0x0109 can be

programmed to enable this delay. Changing this register does not

affect the stability of the JESD204B link.

Clock Fine Delay and Superfine Delay Adjust

Adjust the AD9699 sampling edge instant by writing to Regis-

ter 0x0110, Register 0x0111, and Register 0x0112. Bits[2:0] of

Register 0x0110 enable the selection of the fine delay, or the

fine delay with superfine delay. The fine delay allows the user to

delay the clock edges with 16 step or 192 step delay options. The

superfine delay is an unsigned control to adjust the clock delay in

superfine steps of 0.25 ps each.

Register 0x0112, Bits[7:0] offer the user the option to delay the

clock in 192 delay steps. Register 0x0111, Bits[7:0] offer the user

the option to delay the clock in 128 superfine steps. To use the su-

perfine delay option, set the clock delay control in Register 0x0110,

Bits[2:0] to 0x2 or 0x6. Figure 67 shows the controls available to the

clock dividers within the AD9699. It is recommended to apply the

same delay settings to the digital delay circuits as are applied to the

analog delay circuits to maintain sample accuracy through the pipe.

Figure 68. De-Q Network Recommendation for the Clock Domain Supply

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. Calculate the degradation in SNR at a given input

frequency (f_A) due only to aperture jitter (t_J) by

SNR_JITTER= −20 × log₁₀(2 × π × f_A× t_J)

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications.

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Data Sheet

AD9699

THEORY OF OPERATION

IF undersampling applications are particularly sensitive to jitter (see

Figure 69).

Figure 70. Estimated SNR Degradation for the AD9699 vs. Input Frequency

and RMS Jitter

Figure 69. Ideal SNR vs. Input Frequency and Jitter

POWER-DOWN/STANDBY MODE

The AD9699 has a PDWN/STBY pin that can be used to configure

the device in power-down or standby mode. The default operation

is PDWN. The PDWN/STBY pin is a logic high pin. When in pow-

er-down mode, the JESD204B link is disrupted. The power-down

option can also be set via Register 0x003F and Register 0x0040.

Treat the clock input as an analog signal when aperture jitter

may affect the dynamic range of the AD9699. Separate power

supplies for clock drivers from the ADC output driver supplies to

avoid modulating the clock signal with digital noise. If the clock is

generated from another type of source (by gating, dividing, or other

methods), retime the clock by the original clock at the last step.

Refer to the AN-501 Application Note and the AN-756 Application

Note for more in depth information about jitter performance as it

relates to ADCs.

In standby mode, the JESD204B link is not disrupted and transmits

zeros for all converter samples. Change this transmission using

Register 0x0571, Bit 7 to select /K/ characters.

TEMPERATURE DIODE

Figure 70 shows the estimated SNR of the AD9699 across the input

frequency for different clock induced jitter values. Estimate the SNR

by using the following equation:

The AD9699 contains diode-based temperature sensors. The di-

odes output voltages commensurate to the temperature of the

silicon. There are multiple diodes on the die, but the results estab-

lished using the temperature diode at the central location of the

die can be regarded as representative of the entire die. Figure 71

shows the locations of the diodes in the AD9699 with voltages that

can be output to the VREF pin. In each location, there is a pair of

diodes, one of which is 20× the size of the other. It is recommended

to use both diodes in a location to obtain an accurate estimate

of the die temperature. For more information, see the AN-1432

Application Note, Practical Thermal Modeling and Measurements in

High Power ICs.

−SNR

ADC

10

SNR dBFS = − 10log₁₀10

+ 10

−SNR

JITTER

10

Figure 71. Temperature Diode Locations in the Die

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Data Sheet

AD9699

THEORY OF OPERATION

The temperature diode voltages can be exported to the VREF pin

using the SPI. Use Register 0x18E6 to enable or disable diodes.

It is important to note that other voltages may be exported to

the VREF pin at the same time, which can result in undefined

behavior. To ensure a proper readout, switch off all other voltage

exporting circuits as described in this section. Figure 72 shows the

block diagram of the controls that are required to enable the diode

voltage readout.

a more accurate result, see the AN-1432 Application Note,

Practical Thermal Modeling and Measurements in High Power

ICs.

Figure 73. Typical Voltage Response of the 1× Temperature Diode

The relationship between the measured delta voltage (ΔV) and the

junction temperature in °C is shown in Figure 74.

Figure 72. Register Controls to Output Temperature Diode Voltage on the

VREF Pin

The SPI writes required to export the central temperature diode are

as follows (see Table 44 for more information):

1. Set Register 0x0008 to 0x01.

2. Set Register 0x18E3 to 0x00 to turn off V_CMexport.

3. Set Register 0x18A6 to 0x00 to turn off voltage reference

export.

4. Set Register 0x18E6 to 0x01 to turn on voltage export of the

central 1× temperature diode. The typical voltage response of

the temperature diode is shown in Figure 73. Although this volt-

age represents the die temperature, it is recommended to take

measurements from a pair of diodes for improved accuracy. The

following step explains how to enable the 20× diode.

5. Set Register 0x18E6 to 0x02 to turn on the second central

temperature diode of the pair, which is 20× the size of the first.

For the method using two diodes simultaneously to achieve

Figure 74. Junction Temperature vs. ΔV (mV)

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Data Sheet

AD9699

ADC OVERRANGE AND FAST DETECT

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped. The

standard overrange bit in the JESD204B outputs provides informa-

tion on the state of the analog input that is of limited usefulness.

Therefore, it is helpful to have a programmable threshold below full

scale that allows time to reduce the gain before the clip actually

occurs. In addition, because input signals can have significant slew

rates, the latency of this function is of major concern. Highly pipe-

lined converters can have significant latency. The AD9699 contains

fast detect circuitry to monitor the threshold and assert the FD pin.

The operation of the upper threshold and lower threshold registers,

along with the dwell time registers, is shown in Figure 75.

The FD indicator is asserted if the input magnitude exceeds the

value programmed in the fast detect upper threshold registers,

located at Register 0x0247 and Register 0x0248. The selected

threshold register is compared with the signal magnitude at the

output of the ADC. The fast upper threshold detection has a latency

of 28 clock cycles (maximum). The approximate upper threshold

magnitude is defined by

Upper Threshold Magnitude (dBFS) = 20log(Threshold Magni-

ADC OVERRANGE

tude/2¹³

)

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange indicator can be

embedded within the JESD204B link as a control bit (when CSB

> 0). The latency of this overrange indicator matches the sample

latency.

The FD indicators are not cleared until the signal drops below the

lower threshold for the programmed dwell time. The lower threshold

is programmed in the fast detect lower threshold registers, located

at Register 0x0249 and Register 0x024A. The fast detect lower

threshold register is a 13-bit register that is compared with the

signal magnitude at the output of the ADC. This comparison is

subject to the ADC pipeline latency, but is accurate in terms of

converter resolution. The lower threshold magnitude is defined by

The AD9699 also records any overrange condition in any of the

eight virtual converters. For more information on the virtual con-

verters, refer to Figure 81. The overrange status of each virtual

converter is registered as a sticky bit in Register 0x0563. The

contents of Register 0x0563 can be cleared using Register 0x0562,

by toggling the bits corresponding to the virtual converter to set and

reset position.

Lower Threshold Magnitude (dBFS) = 20log(Threshold Magni-

tude/2¹³

)

For example, to set an upper threshold of −6 dBFS, write 0xFFF to

Register 0x0247 and Register 0x0248. To set a lower threshold of

−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.

FAST THRESHOLD DETECTION (FD)

The FD pin is immediately set whenever the absolute value of

the input signal exceeds the programmable upper threshold level.

The FD bit is only cleared when the absolute value of the input

signal drops below the lower threshold level for greater than the

programmable dwell time. This feature provides hysteresis and

prevents the FD bit from excessively toggling.

The dwell time can be programmed from 1 to 65,535 sample clock

cycles by placing the desired value in the fast detect dwell time

registers, located at Register 0x024B and Register 0x024C. See

Register 0x0040 and Register 0x0245 to Register 0x024C in the

Memory Map Register Details for more details.

Figure 75. Threshold Settings for FD Signal

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Data Sheet

AD9699

ADC APPLICATION MODES AND JESD204B TX CONVERTER MAPPING

The AD9699 contains a configurable signal path that allows differ-

ent features to be enabled for different applications. These features

are controlled using the chip application mode register, Register

0x0200. The chip operating mode is controlled by Bits[3:0] in this

register, and the chip Q ignore is controlled by Bit 5.

the number of virtual converters are the same whether a single

real converter is used along with a digital downconverter block

producing I/Q outputs, or whether an analog downconversion is

used with two real converters producing I/Q outputs.

Figure 77 shows a block diagram of the two scenarios described for

I/Q transport layer mapping.

The AD9699 contains the following modes:

► Full bandwidth mode: 14-bit ADC core running at the full sample

rate.

► DDC mode: up to four digital downconverter (DDC) channels.

After the chip application mode is selected, the output decimation

ratio is set using the chip decimation ratio in Register 0x0201,

Bits[3:0]. The output sample rate = ADC sample rate/the chip

decimation ratio.

To support the different application layer modes, the AD9699 treats

each sample stream (real, I, or Q) as originating from separate

virtual converters.

Table 11 shows the number of virtual converters required and the

transport layer mapping when channel swapping is disabled. Figure

76 shows the virtual converters and their relationship to the DDC

outputs when complex outputs are used.

Figure 76. DDCs and Virtual Converter Mapping

Each DDC channel outputs either two sample streams (I/Q) for the

complex data components (real + imaginary) or one sample stream

for real (I) data. The AD9699 can be configured to use up to eight

virtual converters, depending on the DDC configuration.

The I/Q samples are always mapped in pairs with the I samples

mapped to the first virtual converter and the Q samples mapped

to the second virtual converter. With this transport layer mapping,

Figure 77. I/Q Transport Layer Mapping

Table 11. Virtual Converter Mapping

Number of

Virtual

Chip Operating

Mode

Virtual Converter Mapping

Converters

Supported

(Reg. 0x0200,

Bits[3:0])

Chip Q Ignore

(0x0200, Bit 5)

0

1

2

3

4

5

6

7

1

2

4

8

Full bandwidth

mode (0x0)

Real or complex

(0x0)

ADC

samples

Unused

One DDC mode

(0x1)

Real (I only) (0x1)

DDC0 I

samples

Unused

One DDC mode

(0x1)

Complex (I/Q) (0x0) DDC0 I

samples

DDC0 Q

samples

Two DDC mode

(0x2)

Real (I only) (0x1)

DDC0 I

samples

DDC1 I

samples

Two DDC mode

(0x2)

Complex (I/Q) (0x0) DDC0 I

samples

DDC0 Q

samples

DDC1 I

samples

DDC1 Q

samples

Four DDC mode

(0x3)

Real (I only) (0x1)

DDC0 I

samples

DDC1 I

samples

DDC2 I

samples

DDC3 I

samples

Four DDC mode

(0x3)

Complex (I/Q) (0x0) DDC0 I

samples

DDC0 Q

samples

DDC1 I

samples

DDC1 Q

samples

DDC2 I

samples

DDC2 Q

samples

DDC3 I

samples

DDC3 Q

samples

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Data Sheet

AD9699

PROGRAMMABLE FIR FILTERS

► Real 96-tap filter (see Figure 79)

► DOUT[n] = DIN[n] × XY[n]

► Real set of two cascaded 24-tap filters (see Figure 80)

► DOUT[n] = DIN[n] × X[n] × Y[n]

SUPPORTED MODES

The AD9699 supports the following modes of operation (the aster-

isk symbol (*) denotes convolution):

► Real 48-tap filter (see Figure 78)

► DOUT[n] = DIN_I[n] × XY[n]

Figure 78. Real 48-Tap Filter Configuration

Figure 79. Real 96-Tap Filter Configuration

Figure 80. Real, Two Cascaded, 24-Tap Filter Configuration

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Data Sheet

AD9699

PROGRAMMABLE FIR FILTERS

Table 12. Register 0x0DF8 Definition

PROGRAMMING INSTRUCTIONS

Bits

Description

Use the following procedure to set up the programmable FIR filter:

[7:3]

[2:0]

Reserved

1. Enable the sample clock to the device.

Filter mode (I mode)

2. Set the I path mode (I mode) and gain in Register 0x0DF8 and

Register 0x0DF9 (see Table 12 and Table 13). Only I Mode is

available. Q Mode is not available on single-channel devices.

000: filters bypassed

001: real 24-tap filter (X only)

010: real 48-tap filter (X and Y together)

3. Wait at least 5 µs to allow the programmable filter to power up.

4. Program the I path coefficients to the internal shadow registers

100: real set of two cascaded 24-tap filters (X then Y cascaded)

111: real 96-tap filter (X and Y together)

as follows:

Table 13. Register 0x0DF9 Definition

a. Program the XI coefficients in Register 0x0E00 to Register

Bits

Description

0x0E2F (see Table 14 and Table 15).

b. Program the YI coefficients in Register 0x0F00 to Register

0x0F2F (see Table 14 and Table 15).

c. Program the tapped delay in Register 0x0F30 (note that this

7

Reserved

[6:4]

Y filter gain

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

Reserved

step is optional).

5. Set the chip transfer bit using either of the following methods

(note that setting the chip transfer bit applies the programmed

shadow coefficients to the filter):

3

[2:0]

X filter gain

a. Via the register map using the write the chip transfer bit

(Register 0x000F = 0x01).

b. Via a GPIO pin, as follows:

110: −12 dB loss

111: −6 dB loss

000: 0 dB gain

001: 6 dB gain

010: 12 dB gain

1. Configure one of the GPIO pins as the chip transfer bit

in Register 0x0040 to Register 0x0042.

2. Toggle the GPIO pin to initiate the chip transfer (the

rising edge is triggered).

6. When the I path mode register changes in Register 0x0DF8, all

Table 14 shows the coefficient tables in Register 0x0E00 to Regis-

ter 0x0F30. Note that all coefficients are Q1.15 format (sign bit + 15

fractional bits).

coefficients must be reprogrammed.

Table 14. I Coefficient Table (Device Selection = 0x1)¹

Single 24-Tap Filter (I Mode

[2:0] = 0x1)

Single 48-Tap Filter (I Mode

[2:0] = 0x2)

Two Cascaded 24-Tap Filters (I Single 96-Tap Filter (I Mode

Addr.

Mode [2:0] = 0x4)

[2:0] = 0x7)

0x0E00

0x0E01

0x0E02

0x0E03

…

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

…

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

…

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

…

XI C0 [7:0]

XI C0 [15:8]

XI C1 [7:0]

XI C1 [15:8]

…

0x0E2E

0x0E2F

0x0F00

0x0F01

0x0F02

0x0F03

…

XI C23 [7:0]

XI C23 [15:0]

Unused

XI C23 [7:0]

XI C23 [15:0]

YI C24 [7:0]

YI C24 [15:8]

YI C25 [7:0]

YI C25 [15:8]

…

XI C23 [7:0]

XI C23 [15:0]

YI C0 [7:0]

YI C0 [15:8]

YI C1 [7:0]

YI C1 [15:8]

…

XI C23 [7:0]

XI C23 [15:0]

YI C24 [7:0]

YI C24 [15:8]

YI C25 [7:0]

YI C25 [15:8]

…

Unused

…

0x0F2E

0x0F2F

0x0F30

Unused

YI C47 [7:0]

YI C47 [15:0]

Unused

YI C23 [7:0]

YI C23 [15:0]

Unused

YI C47 [7:0]

YI C47 [15:0]

Unused

1

XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n.

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

The AD9699 includes four digital downconverters (DDC0 to DDC3)

that provide filtering and reduce the output data rate. This digital

processing section includes an NCO, multiple decimating FIR fil-

ters, a gain stage, and a complex to real conversion stage. Each

of these processing blocks has control lines that allow it to be inde-

pendently enabled and disabled to provide the desired processing

function. The digital downconverter can be configured to output

either real data or complex output data.

► Frequency translation stage (optional)

► Filtering stage

► Gain stage (optional)

► Complex to real conversion stage (optional)

DDC Frequency Translation Stage (Optional)

This stage consists of a phase coherent NCO and quadrature

mixers that can be used for frequency translation of both real or

complex input signals. The phase coherent NCO allows an infinite

number of frequency hops that are all referenced back to a single

synchronization event. It also includes 16 shadow registers for fast

switching applications. This stage shifts a portion of the available

digital spectrum down to baseband.

The DDCs output a 16-bit stream. To enable this operation, the

converter number of bits, N, is set to a default value of 16, even

though the analog core only outputs 14 bits. In full bandwidth

operation, the ADC output is the 14-bit word followed by two zeros,

unless the tail bits are enabled.

DDC I/Q OUTPUT SELECTION

DDC Filtering Stage

Each DDC channel has two output ports that can be paired to

support both real and complex outputs. For real output signals, only

the DDC Output Port I is used (the DDC Output Port Q is invalid).

For complex I/Q output signals, both DDC Output Port I and DDC

Output Port Q are used.

After shifting down to baseband, this stage decimates the frequency

spectrum using multiple low-pass finite impulse response (FIR)

filters for rate conversion. The decimation process lowers the output

data rate, which in turn reduces the output interface rate.

The I/Q outputs to each DDC channel are controlled by the DDC

complex to real enable bit, Bit 3, in the DDC control registers

(Register 0x0310, Register 0x0330, Register 0x0350, and Register

0x0370).

DDC Gain Stage (Optional)

Because of losses associated with mixing a real input signal down

to baseband, this stage compensates by adding an additional 0 dB

or 6 dB of gain.

The chip Q ignore bit in the chip mode register (Register 0x0200,

Bit 5) controls the chip output muxing of all the DDC channels.

When all DDC channels use real outputs, set this bit high to ignore

all DDC Q output ports. When any of the DDC channels are set to

use complex I/Q outputs, the user must clear this bit to use both

DDC Output Port I and DDC Output Port Q. For more information,

see Figure 97.

DDC Complex to Real Conversion Stage

(Optional)

When real outputs are necessary, this stage converts the complex

outputs back to real by performing an f_S/4 mixing operation plus a

filter to remove the complex component of the signal.

DDC GENERAL DESCRIPTION

Figure 81 shows the detailed block diagram of the DDCs imple-

mented in the AD9699.

The four DDC blocks are used to extract a portion of the full digital

spectrum captured by the ADC. They are intended for IF sampling

or oversampled baseband radios requiring wide bandwidth input

signals.

Figure 82 shows an example usage of one of the four DDC

channels with a real input signal and four half-band filters (HB4 +

HB3 + HB2 + HB1) used. It shows both complex (decimate by 16)

and real (decimate by 8) output options.

Each DDC block contains the following signal processing stages:

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Figure 81. DDC Detailed Block Diagram

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Figure 82. DDC Theory of Operation Example (Real Input)

Register 0x0350, and Register 0x0370). These IF modes are as

follows:

DDC FREQUENCY TRANSLATION

DDC Frequency Translation General

Description

► Variable IF mode

► 0 Hz IF or zero IF (ZIF) mode

► f_S/4 Hz IF mode

Frequency translation is accomplished by using a 48-bit complex

NCO with a digital quadrature mixer. This stage translates either

a real or complex input signal from an IF to a baseband complex

digital output (carrier frequency = 0 Hz).

► Test mode

Variable IF Mode

The frequency translation stage of each DDC can be controlled

individually and supports four different IF modes using Bits[5:4]

of the DDC control registers (Register 0x0310, Register 0x0330,

In this mode, the NCO and mixers are enabled. The NCO output

frequency can be used to digitally tune the IF frequency.

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

0 Hz IF (ZIF) Mode

Test Mode

In this mode, the mixers are bypassed, and the NCO is disabled.

In this mode, input samples are forced to 0.999 to positive full

scale. The NCO is enabled. This test mode allows the NCOs to

directly drive the decimation filters.

f_S/4 Hz IF Mode

Figure 83 show examples of the frequency translation stage for real

inputs.

In this mode, the mixers and the NCO are enabled in downmixing

by f_S/4 mode to save power.

Figure 83. DDC NCO Frequency Tuning Word Selection—Real Inputs

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

DDC NCO Description

DDC NCO Coherent Mode

Each DDC contains one NCO. Each NCO enables the frequency

translation process by creating a complex exponential frequency

(e^-jωct), which can be mixed with the input spectrum to translate the

desired frequency band of interest to dc, where it can be filtered by

the subsequent low-pass filter blocks to prevent aliasing.

This mode allows an infinite number of frequency hops where the

phase is referenced to a single synchronization event at time 0.

This mode is useful when phase coherency must be maintained

when switching between different frequency bands. In this mode,

the user can switch to any tuning frequency without the need to re-

set the NCO. Although only one FTW is required, the NCO contains

16 shadow registers for fast-switching applications. Selection of the

shadow registers is controlled by the CMOS GPIO pins or through

the register map of the SPI. In this mode, the NCO can be set up by

providing the following:

When placed in variable IF mode, the NCO supports two different

additional modes.

DDC NCO Programmable Modulus Mode

This mode supports >48-bit frequency tuning accuracy for appli-

cations that require exact rational (M/N) frequency synthesis at

a single carrier frequency. In this mode, the NCO is set up by

providing the following:

► Up to sixteen 48-bit FTWs.

► Up to sixteen 48-bit POWs.

► The 48-bit MAW must be set to zero in coherent mode.

Figure 84 shows a block diagram of one NCO and its connection

to the rest of the design. The coherent phase accumulator block

contains the logic that allows an infinite number of frequency hops.

The gray lines in Figure 84 represent SPI control lines.

► 48-bit frequency tuning word (FTW)

► 48-bit Modulus A word (MAW)

► 48-bit Modulus B word (MBW)

► 48-bit phase offset word (POW)

Figure 84. NCO + Mixer Block Diagram

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

and for negative numbers, mod(–32,10)= –2.

NCO FTW/POW/MAW/MAB Description

floor(x) is defined as the largest integer less than or equal to x. For

example, floor(3.6) = 3.

The NCO frequency value is determined by the following settings:

► 48-bit twos complement number entered in the FTW

► 48-bit unsigned number entered in the MAW

► 48-bit unsigned number entered in the MBW

Note that Equation 1 to Equation 4 apply to the aliasing of signals

in the digital domain (that is, aliasing introduced when digitizing

analog signals).

M and N are integers reduced to their lowest terms. MAW and

MBW are integers reduced to their lowest terms. When MAW is set

to zero, the programmable modulus logic is automatically disabled.

Frequencies between −f_S/2 and +f_S/2 (f_S/2 excluded) are represent-

ed using the following values:

► FTW = 0x8000_0000_0000 and MAW = 0x0000_0000_0000

represents a frequency of –f_S/2.

► FTW = 0x0000_0000_0000 and MAW = 0x0000_0000_0000

represents dc (frequency is 0 Hz).

► FTW = 0x7FFF_FFFF_FFFF and MAW = 0x0000_0000_0000

represents a frequency of +f_S/2.

For example, if the ADC sampling frequency (f_S) is 3000 MSPS and

the carrier frequency (f_C) is 1001.5 MHz, then,

mod 1001 . 5, 3000

3000

M

N

2003

=

6000

=

mod 1001 . 5, 3000

3000

FTW = floor 2⁴⁸

NCO FTW/POW/MAW/MAB Programmable

Modulus Mode

= 0x5576_19F0_FB3

MAW = mod(2⁴⁸× 2003, 6000) = 0x0000_0000_0F80

MBW = 0x0000_0000_1770

For programmable modulus mode, the MAW must be set to a

nonzero value (not equal to 0x0000_0000_0000). This mode is

only needed when frequency accuracy of >48 bits is required. One

example of a rational frequency synthesis requirement that requires

>48 bits of accuracy is a carrier frequency of 1/3 the sample rate.

When frequency accuracy of ≤48 bits is required, coherent mode

must be used (see the NCO FTW/POW/MAW/MAB Coherent Mode

section).

The actual carrier frequency can be calculated based on the follow-

ing equation:

MAW

MBW

FTW +

× f

S

f_{C_ACTUAL}

=

48

2

For the previous example, the actual carrier frequency (f_{C_ACTUAL}

is

)

In programmable modulus mode, the FTW, MAW, and MBW must

satisfy the following four equations (for a detailed description of

the programmable modulus feature, see the DDS architecture de-

scribed in the AN-953 Application Note):

0x0000_0000_0F80

0x5576_19F0_FB38 ×

0x0000_0000_1770

48

f_{C_ACTUAL}

=

2

1001.5 MHz

MAW

MBW

48

FTW +

mod f , f

C

S

M

N

=

(1)

(2)

A 48-bit POW is available for each NCO to create a known phase

relationship between multiple chips or individual DDC channels

inside the chip.

f

S

2

mod f , f

FTW = floor 2⁴⁸

C

S

f

S

While in programmable modulus mode, the FTW and POW regis-

ters can be updated at any time while still maintaining deterministic

phase results in the NCO. However, the following procedure must

be followed to update the MAW and/or MBW registers to ensure

proper operation of the NCO:

MAW = mod 2⁴⁸× M, N (3)

MBW = N (4)

where:

f_Cis the desired carrier frequency.

f_Sis the ADC sampling frequency.

M is the integer representing the rational numerator of the frequen-

cy ratio.

N is the integer representing the rational denominator of the fre-

quency ratio.

1. Write to the MAW and MBW registers for all the DDCs.

2. Synchronize the NCOs either through the DDC soft reset bit

accessible through the SPI or through the assertion of the

SYSREF± pin (see the Reading the Memory Map Register

Table section).

FTW is the 48-bit twos complement number representing the NCO

FTW.

NCO FTW/POW/MAW/MAB Coherent Mode

For coherent mode, the NCO MAW must be set to zero

(0x0000_0000_0000). In this mode, the NCO FTW can be calculat-

ed by the following equation:

MAW is the 48-bit unsigned number representing the NCO MAW

(must be <2⁴⁷).

MBW is the 48-bit unsigned number representing the NCO MBW.

mod(x) is a remainder function. For example, mod(110,100) = 10

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

mod f ,

f

S

FTW = round 2⁴⁸

(5)

For the previous example, the actual carrier frequency (f_{C_ACTUAL}

is

)

C

f

S

416 . 667 × 3000

where:

f_{C_ACTUAL}

=

= 416 . 66699 MHz

48

2

FTW is the 48-bit twos complement number representing the

NCO FTW.

f_Sis the ADC sampling frequency.

A 48-bit POW is available for each NCO to create a known phase

relationship between multiple chips or individual DDC channels

inside the chip.

f_Cis the desired carrier frequency.

mod(x) is a remainder function. For example mod(110,100) = 10

and for negative numbers, mod(–32,10) = –2.

round(x) is a rounding function. For example round(3.6) = 4 and for

negative numbers, round(–3.4) = –3.

While in coherent mode, the FTW and POW registers can be

updated at any time while still maintaining deterministic phase

results in the NCO.

Note that Equation 5 applies to the aliasing of signals in the digital

domain (that is, aliasing introduced when digitizing analog signals).

The MAW must be set to zero to use coherent mode. When MAW is

zero, the programmable modulus logic is automatically disabled.

NCO Channel Selection

When configured in coherent mode, only one FTW is required in

the NCO. In this mode, the user can switch to any tuning frequency

without the need to reset the NCO by writing to the FTW directly.

However, for fast switching applications, where either all FTWs

are known beforehand or it is possible to queue up the next set

of FTWs, the NCO contains 16 additional shadow registers (see

Figure 84). These shadow registers are hereafter referred to as the

NCO channels.

For example, if the ADC sampling frequency (f_S) is 3000 MSPS and

the carrier frequency (f_C) is 416.667 MHz, then,

mod 416 . 667, 3000

NCO_FTW = round 2⁴⁸

3000

= 0x2EC6_C03A_8E23

The actual carrier frequency can be calculated based on the follow-

ing equation:

Figure 85 shows a simplified block diagram of the NCO channel

selection block. The gray lines in Figure 85 represent SPI control

lines.

FTW × f

S

f_{C_ACTUAL}

=

48

2

Figure 85. NCO Channel Selection Block

analog.com

Rev. 0 | 39 of 121

Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Only one NCO channel is active at a time and NCO channel

selection is controlled either by the CMOS GPIO pins or through the

register map.

The following procedure must be followed to use GPIO edge control

mode for NCO channel selection:

1. Configure one or more GPIO pins as NCO channel selection

Each NCO channel selector supports three different modes, descri-

bed as follows:

inputs.

a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to 0x6

► GPIO level control mode. In this mode, the GPIO pins determine

the exact NCO channel selected.

and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to 0x6

► GPIO edge control mode. A low to high transition on a single

GPIO pin determines the exact NCO channel selected. The

internal channel selection counter is reset by either SYSREF± or

by the DDC soft reset.

► Register map mode. In this mode, the NCO channel selected is

determined directly through the register map.

and Bits[7:4] in Register 0x0041 to 0x0.

c. To use GPIO_A1, write Bits[3:0] in Register 0x0042 to 0x0.

d. To use GPIO_B1, write Bits[7:4] in Register 0x0042 to 0x0.

2. Configure the NCO channel selector in GPIO edge control

mode by setting Bits[7:4] in the NCO control registers (Regis-

ter 0x0314, Register 0x0334, Register 0x0354, and Register

0x0374) to 0x8 through 0xB, depending on the desired GPIO

pin.

The following procedure must be followed to use GPIO level control

mode for NCO channel selection:

3. Configure the wrap point for the NCO channel selection by

setting Bits[3:0] in the NCO control registers (Register 0x0314,

Register 0x0334, Register 0x0354, and Register 0x0374). A

value of 4 causes the channel selection to wrap at Channel 4

(for example, 0, 1, 2, 3, 4, 0, 1, 2, 3, 4).

1. Configure one or more GPIO pins as NCO channel selection

inputs. The GPIO pins not configured as NCO channel selection

inputs are internally tied low.

a. To use GPIO_A0, write Bits[2:0] in Register 0x0040 to 0x6

and Bits[3:0] in Register 0x0041 to 0x0.

b. To use GPIO_B0, write Bits[5:3] in Register 0x0040 to 0x6

4. Transition the selected GPIO pin from low to high to increment

the NCO channel selection.

and Bits[7:4] in Register 0x0041 to 0x0.

c. To use GPIO_A1, write Bits[3:0] in Register 0x0042 to 0x0.

d. To use GPIO_B1, write Bits[7:4] in Register 0x0042 to 0x0.

Figure 86 shows an example use case for coherent mode using

three NCO channels. In this example, NCO Channel 0 is actively

downconverting Bandwidth 0 (B0), while NCO Channel 1 and

Channel 2 are in standby mode and are tuned to Bandwidth 1 and

Bandwidth 2 (B1 and B2), respectively.

2. Configure the NCO channel selector in GPIO level control

mode by setting Bits[7:4] in the NCO control registers (Regis-

ter 0x0314, Register 0x0334, Register 0x0354, and Register

0x0374) to 0x1 through 0x6, depending on the desired GPIO

pin order.

The phase coherent NCO switching feature allows an infinite num-

ber of frequency hops that are all phase coherent. The initial phase

of the NCO is established at time t₀from SYSREF± synchroniza-

tion. Switching the NCO FTW does not affect the phase. With this

feature, only one FTW is required, but the user may wish to use all

16 channels to queue up the next hop.

3. Select the desired NCO channel through the GPIO pins.

After SYSREF± synchronization at startup, all NCOs across multi-

ple chips are inherently synchronized.

Figure 86. NCO Coherent Mode with Three NCO Channels (B0 Selected)

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Rev. 0 | 40 of 121

Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

► Using the SYSREF± pin. When the SYSREF± pin is enabled

Setting Up the Multichannel NCO Feature

in the SYSREF control registers (Register 0x0120 and Register

0x0121), and the DDC synchronization is enabled in the DDC

synchronization control register (Register 0x0300, Bits[1:0]), any

subsequent SYSREF± event resets all the PAWs in the chip.

Note that this method can be used to synchronize DDC channels

within the same chip or DDC channels within separate chips.

The first step to configure the multichannel NCO is to program the

FTWs. The AD9699 memory map has an FTW index register for

each DDC. This index determines which NCO channel receives the

FTW from the register map. The following sequence describes the

method for programming the FTWs:

1. Write the FTW index register with the desired DDC channel.

2. Write the FTW with the desired value. This value is applied to

NCO Multichip Synchronization

the NCO channel index mentioned in Step 1.

3. Repeat Step 1 and Step 2 for other NCO channels.

In some applications, it is necessary to synchronize all the NCOs

and local multiframe clocks (LMFCs) within multiple devices in a

system. For applications requiring multiple NCO tuning frequencies

in the system, a designer likely needs to generate a single SYSREF

pulse at all devices simultaneously. For many systems, generating

or receiving a single-shot SYSREF pulse at all devices is challeng-

ing because of the following factors:

After setting the FTWs, the user must then select an active NCO

channel. This selection can be performed either through the SPI

registers or through the external GPIO pins. The following se-

quence describes the method for selecting the active NCO channel

using the SPI:

► Enabling or disabling the SYSREF pulse is often an asynchro-

nous event.

► Not all clock generation chips support this feature.

1. Set the NCO channel select mode bits (Bits[7:4] in Regis-

ter 0x0314, Register 0x0334, Register 0x0354, and Register

0x0374) to 0x0 to enable SPI selection.

2. Choose the active NCO channel using Bits[3:0] in Regis-

ter 0x0314, Register 0x0334, Register 0x0354, and Register

0x0374.

For these reasons, the AD9699 contains a synchronization trigger-

ing mechanism that allows the following:

► Multichip synchronization of all NCOs and LMFCs at system

startup.

► Multichip synchronization of all NCOs after applying new tuning

frequencies during normal operation.

The following sequence describes the method for selecting the

active NCO channel using the GPIO CMOS pins:

1. Set the NCO channel select mode bits (Bits[7:4] in Regis-

ter 0x0314, Register 0x0334, Register 0x0354, and Register

0x0374) to a nonzero value to enable GPIO pin selection.

The synchronization triggering mechanism uses a master/slave

arrangement, as shown in Figure 87.

2. Configure the GPIO pins as NCO channel selection inputs

by writing to Register 0x0040, Register 0x0041, and Register

0x0042.

3. NCO switching is performed by externally controlling the GPIO

CMOS pins.

NCO Synchronization

Each NCO contains a separate phase accumulator word (PAW).

The initial reset value of each PAW is set to zero and incremented

every clock cycle. The instantaneous phase of the NCO is calcu-

lated using the PAW, FTW, MAW, MBW, and POW. Due to this

architecture, the FTW and POW registers can be updated at any

time while still maintaining deterministic phase results in the PAW of

the NCO.

Two methods can be used to synchronize multiple PAWs within the

chip:

Figure 87. System Using Master/Slave Synchronization Triggering

► Using the SPI. Use the DDC soft reset bit in the DDC synchroni-

zation control register (Register 0x0300, Bit 4) to reset all the

PAWs in the chip. This reset is accomplished by setting the DDC

soft reset bit high, and then setting this bit low. Note that this

method can only be used to synchronize DDC channels within

the same chip.

Each device has an internal next synchronization trigger enable

(NSTE) signal that controls whether the next SYSREF signal caus-

es a synchronization event. Slave ADC devices must source their

NSTE from an external slave next trigger input (SNTI) pin. Master

devices can either use an external master next trigger output

(MNTO) pin (default setting), or use an external SNTI pin.

analog.com

Rev. 0 | 41 of 121

Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

See Memory Map Register Details (Register 0x0041 and Register

0x0042) to configure the FD/GPIO pins for this operation.

SYSREF at startup. Using this startup sequence synchronizes all

the NCOs and LMFCs in the system at once.

NCO Multichip Synchronization at Startup

Figure 88 shows a timing diagram along with the required sequence

of events for NCO multichip synchronization using triggering and

Figure 88. NCO Multichip Synchronization at Startup (Using Triggering and SYSREF)

analog.com

Rev. 0 | 42 of 121

Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

the dynamic range of the signal within the full scale of the output

bits (see the DDC Gain Stage (Optional) section).

NCO Multichip Synchronization During Normal

Operation

The worst case spurious signal from the NCO is greater than 102

dBc SFDR for all output frequencies.

See the Setting Up the Multichannel NCO Feature section.

DDC Mixer Description

DDC DECIMATION FILTERS

When not bypassed (Register 0x0200 ≠ 0x00), the digital quadra-

ture mixer performs a similar operation to an analog quadrature

mixer. It performs the downconversion of the input signal by using

the NCO frequency as a local oscillator. Because the input of the

DDC is a real signal, a real mixer operation (with two multipliers) is

performed.

After the frequency translation stage, there are multiple decimation

filter stages that reduce the output data rate. After the carrier of

interest is tuned down to dc (carrier frequency = 0 Hz), these filters

efficiently lower the sample rate, while providing sufficient alias

rejection from unwanted adjacent carriers around the bandwidth of

interest.

DDC NCO + Mixer Loss and SFDR

Figure 89 shows a simplified block diagram of the decimation

filter stage, and Table 15 describes the filter characteristics of the

different finite impulse response (FIR) filter blocks.

When mixing a real input signal down to baseband, −6 dB of loss

is introduced in the signal due to filtering of the negative image. An

additional −0.05 dB of loss is introduced by the NCO. The total loss

of a real input signal mixed down to baseband is −6.05 dB. For this

reason, it is recommended that the user compensate for this loss by

enabling the 6 dB of gain in the gain stage of the DDC to recenter

Table 16 and Table 17 show the different filter configurations select-

able by including different filters. In all cases, the DDC filtering

stage provides 80% of the available output bandwidth, <±0.005 dB

of pass-band ripple and >100 dB of stop band alias rejection.

Figure 89. DDC Decimation Filter Block Diagram

Table 15. DDC Decimation Filter Characteristics

Pass Band (rad/

sec)

Stop Band (rad/

sec)

Pass-Band Ripple

(dB)

Filter Name

Filter Type

Decimation Ratio

Stop-Band Attenuation (dB)

HB4

HB3

HB2

HB1

TB2

TB1¹

FB2

FIR low-pass

2

3

5

0.1 × π/2

0.2 × π/2

0.4 × π/2

0.8 × π/2

0.4 × π/3

0.8 × π/3

0.4 × π/5

1.9 × π/2

1.8 × π/2

1.6 × π/2

1.2 ×x π/2

1.6 × π/3

1.2 × π/3

1.6 × π/5

<±0.001

<±0.002

<±0.005

<±0.001

>100

1

TB1 is only supported in DDC0 and DDC1.

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Rev. 0 | 43 of 121

Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 16. DDC Filter Configurations¹

Real (I) Output

Decimation Sample

Complex (I/Q) Outputs

Decimation

ADC

Sample

Rate

Alias Protected

Bandwidth

Ideal²SNR

Improvement (dB)

DDC Filter Configuration

Ratio

Rate

Ratio

Sample Rate

f_S

HB1

TB1³

1

f_S

2

f_S/2 (I) + f_S/2 (Q)

f_S/3 (I) + f_S/3 (Q)

f_S/4 (I) + f_S/4 (Q)

f_S/6 (I) + f_S/6 (Q)

f_S/8 (I) + f_S/8 (Q)

f_S/10 (I) + f_S/10 (Q)

f_S/12 (I) + f_S/12 (Q)

f_S/15 (I) + f_S/15 (Q)

f_S/16 (I) + f_S/16 (Q)

f_S/20 (I) + f_S/20 (Q)

f_S/24 (I) + f_S/24 (Q)

f_S/30 (I) + f_S/30 (Q)

f_S/40 (I) + f_S/40 (Q)

f_S/48 (I) + f_S/48 (Q)

f_S/2 × 80%

f_S/3 × 80%

f_S/4 × 80%

f_S/6 × 80%

f_S/8 × 80%

f_S/10 × 80%

f_S/12 × 80%

f_S/15 × 80%

f_S/16 × 80%

f_S/20 × 80%

f_S/24 × 80%

f_S/30 × 80%

f_S/40 × 80%

f_S/48 × 80%

1

N/A

2

N/A

f_S/2

f_S/3

f_S/4

f_S/5

f_S/6

N/A

f_S/8

f_S/10

f_S/12

N/A

f_S/20

f_S/24

3

2.7

4

HB2 + HB1

4

TB2 + HB1

3

6

5.7

7

HB3 + HB2 + HB1

FB2 + HB1

4

8

5

10

12

15

16

20

24

30

40

48

8

TB2 + HB2 + HB1

FB2 + TB1⁴

6

8.8

9.7

10

11

N/A

8

HB4 + HB3 + HB2 + HB1

FB2 + HB2 + HB1

TB2 + HB3 + HB2 + HB1

HB2 + FB2 + TB1⁵

FB2 + HB3 + HB2 + HB1

TB2 + HB4 + HB3 + HB2 + HB1

10

12

N/A

20

24

11.8

12.7

14

14.8

1

N/A means not applicable.

2

3

4

5

Ideal SNR improvement due to oversampling + filtering = 10log(bandwidth/f_S/2).

TB1 is only supported in DDC0 and DDC1.

Table 17. DDC Filter Configurations (f_S= 3000 MSPS)¹

Real (I) Output

Complex (I/Q) Outputs

Sample

Rate

(MSPS)

ADC Sample

Rate (MSPS) DDC Filter Configuration

Decimation

Ratio

Alias Protected

Bandwidth (MHz)

Decimation Ratio

Sample Rate (MSPS)

3000

HB1

TB1²

1

3000

N/A

1500

1000

750

600

500

N/A

375

300

250

N/A

150

125

2

1500 (I) + 1500 (Q)

1000 (I) + 1000 (Q)

750 (I) + 750 (Q)

500 (I) + 500 (Q)

375 (I) + 375 (Q)

300 (I) + 300 (Q)

250 (I) + 250 (Q)

200 (I) + 200 (Q)

187.5 (I) + 187.5 (Q)

150 (I) + 150 (Q)

125 (I) + 125 (Q)

100 (I) + 100 (Q)

75 (I) + 75 (Q)

1200

800

600

400

300

240

200

160

150

120

100

80

N/A

2

3

HB2 + HB1

4

TB2 + HB1

3

6

HB3 + HB2 + HB1

FB2 + HB1

4

8

5

10

12

15

16

20

24

30

40

48

TB2 + HB2 + HB1

FB2 + TB1³

6

N/A

8

HB4 + HB3 + HB2 + HB1

FB2 + HB2 + HB1

TB2 + HB3 + HB2 + HB1

HB2 + FB2 + TB1⁴

FB2 + HB3 + HB2 + HB1

TB2 + HB4 + HB3 + HB2 + HB1

10

12

N/A

20

24

60

62.5 (I) + 62.5 (Q)

50

1

N/A means not applicable.

2

3

4

TB1 is only supported in DDC0 and DDC1.

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 19. HB3 Filter Coefficients

HB4 Filter Description

HB3 Coefficient

Number

Normalized

Coefficient

Decimal Coefficient (17-

Bit)

The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses

an 11-tap, symmetrical, fixed coefficient filter implementation that is

optimized for low power consumption. The HB4 filter is only used

when complex outputs (decimate by 16) or real outputs (decimate

by 8) are enabled. Otherwise, it is bypassed. Table 18 and Figure

90 show the coefficients and response of the HB4 filter.

C1, C11

C2, C10

C3, C9

C4, C8

C5, C7

C6

0.006637

0

435

0

−0.051055

0

−3346

0

0.294418

0.500000

19295

65,536

Table 18. HB4 Filter Coefficients

Normalized

Coefficient

Decimal Coefficient (15-

Bit)

HB4 Coefficient Number

C1, C11

C2, C10

C3, C9

C4, C8

C5, C7

C6

0.006042

99

0

−0.049377

−809

0

0.293304

0.5

4806

8192

Figure 91. HB3 Filter Response

HB2 Filter Description

The third decimate by 2, half-band, low-pass, FIR filter (HB2) uses

a 19-tap, symmetrical, fixed coefficient filter implementation that

is optimized for low power consumption. The HB2 filter is only

used when complex or real outputs (decimate by 4, 8, or 16) is

enabled. Otherwise, it is bypassed. Table 20 and Figure 92 show

the coefficients and response of the HB2 filter.

Figure 90. HB4 Filter Response

Table 20. HB2 Filter Coefficients

HB3 Filter Description

HB2 Coefficient

Number

Normalized

Coefficient

Decimal Coefficient (18-

Bit)

The second decimate by 2, half-band, low-pass, FIR filter (HB3)

uses an 11-tap, symmetrical, fixed coefficient filter implementation

that is optimized for low power consumption. The HB3 filter is only

used when complex outputs (decimate by 8 or 16) or real outputs

(decimate by 4 or 8) are enabled. Otherwise, it is bypassed. Table

19 and Figure 91 show the coefficients and response of the HB3

filter.

C1, C19

C2, C18

C3, C17

C4, C16

C5, C15

C6, C14

C7, C13

C8, C12

C9, C11

C10

0.000671

88

0

−0.005325

−698

0

0.022743

2981

0

−0.074180

−9723

0

0.306091

0.5

40120

65536

analog.com

Rev. 0 | 45 of 121

Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 21. HB1 Filter Coefficients

Normalized

Decimal Coefficient (20-

Bit)

HB1 Coefficient Number

Coefficient

C25, C39

C26, C38

C27, C37

C28, C36

C29, C35

C30, C34

C31, C33

C32

−0.036404

−19086

0

0.056866

29814

0

−0.101892

−53421

0

0.316883

0.5

166138

262144

Figure 92. HB2 Filter Response

HB1 Filter Description

The fourth and final decimate by 2, half-band, low-pass, FIR filter

(HB1) uses a 63-tap, symmetrical, fixed coefficient filter implemen-

tation that is optimized for low power consumption. The HB1 filter is

always enabled and cannot be bypassed. Table 21 and Figure 93

show the coefficients and response of the HB1 filter.

Table 21. HB1 Filter Coefficients

Normalized

Coefficient

Decimal Coefficient (20-

Bit)

HB1 Coefficient Number

Figure 93. HB1 Filter Response

C1, C63

C2, C62

C3, C61

C4, C60

C5, C59

C6, C58

C7, C57

C8, C56

C9, C55

C10, C54

C11, C53

C12, C52

C13, C51

C14, C50

C15, C49

C16, C48

C17, C47

C18, C46

C19, C45

C20, C44

C21, C43

C22, C42

C23, C41

C24, C40

−0.000019

−10

0

TB2 Filter Description

0.000072

38

0

The TB2 uses a 26-tap, symmetrical, fixed coefficient filter imple-

mentation that is optimized for low power consumption. The TB2 fil-

ter is only used when decimation ratios of 6, 12, or 24 are required.

Table 22 and Figure 94 show the coefficients and response of the

TB2 filter.

−0.000195

−102

0

0.000443

232

0

−0.000891

−467

Table 22. TB2 Filter Coefficients

0

Normalized

Coefficient

Decimal Coefficient (19-

Bit)

0.001644

862

TB2 Coefficient Number

0

C1, C26

C2, C25

C3, C24

C4, C23

C5, C22

C6, C21

C7, C20

C8, C19

C9, C18

C10, C17

C11, C16

C12, C15

−0.000190

−0.000793

−0.00113

0.000915

0.006290

0.009822

0.000915

−0.023483

−0.043151

−0.019317

0.071327

0.201171

−50

−0.00284

−1489

208

0

−298

240

0.004654

2440

0

1649

2575

240

−0.007311

−3833

0

0.011122

5831

−6156

−11312

−5064

18698

52736

0

−0.016554

−8679

0

0.02442

0

12803

0

analog.com

Rev. 0 | 46 of 121

Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 22. TB2 Filter Coefficients

Table 23. TB1 Filter Coefficients

Normalized

Coefficient

Decimal Coefficient (19-

Bit)

TB1 Coefficient

Number

TB2 Coefficient Number

Decimal Coefficient

Quantized Coefficient (22-Bit)

C13, C14

0.297756

78055

21, 56

22, 55

23, 54

24, 53

25, 52

26, 51

27, 50

28, 49

29, 48

30, 47

31, 46

32, 45

33, 44

34, 43

35, 42

36, 41

37, 40

38, 39

−0.007410

−0.008039

0.000053

0.010874

0.013313

0.001817

−0.015579

−0.021590

−0.005603

0.022451

0.035774

0.013541

−0.034655

−0.066549

−0.035213

0.071220

0.210777

0.309200

−31080

−33718

222

45608

55840

7620

−65344

−90556

−23502

94167

150046

56796

−145352

−279128

−147694

298720

884064

1296880

Figure 94. TB2 Filter Response

TB1 Filter Description

The TB1 decimate by 3, low-pass, FIR filter uses a 76-tap, symmet-

rical, fixed coefficient filter implementation. Table 23 shows the TB1

filter coefficients, and Figure 95 shows the TB1 filter response. TB1

is only supported in DDC0 and DDC1.

Table 23. TB1 Filter Coefficients

TB1 Coefficient

Number

Decimal Coefficient

Quantized Coefficient (22-Bit)

1, 96

−0.000023

−0.000053

−0.000037

0.000090

0.000291

0.000366

0.000095

−0.000463

−0.000822

−0.000412

0.000739

0.001665

0.001132

−0.000981

−0.002961

−0.002438

0.001087

0.004833

0.004614

−0.000871

−96

2, 75

−224

−156

379

3, 74

4, 73

5, 72

1220

6, 71

1534

7, 70

398

Figure 95. TB1 Filter Response

8, 69

−1940

−3448

−1729

3100

9, 68

FB2 Filter Description

10, 67

11, 66

12, 65

13, 64

14, 63

15, 62

16, 61

17, 60

18, 59

19, 58

20, 57

The FB2 decimate by 5, low-pass, FIR filter uses a 48-tap, symmet-

rical, fixed coefficient filter implementation. Table 24 shows the FB2

filter coefficients, and Figure 96 shows the FB2 filter response.

6984

4748

−4114

−12418

−10226

4560

Table 24. FB2 Filter Coefficients

FB2 Coefficient

Number

Decimal Coefficient

Quantized Coefficient (21-Bit)

1, 48

2, 47

3, 46

4, 45

0.000007

7

20272

19352

−3652

−0.000004

−0.000069

−0.000244

−4

−72

−256

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 24. FB2 Filter Coefficients

DDC GAIN STAGE

FB2 Coefficient

Number

Each DDC contains an independently controlled gain stage. The

gain is selectable as either 0 dB or 6 dB. When mixing a real input

signal down to baseband, it is recommended that the user enable

the 6 dB of gain to recenter the dynamic range of the signal within

the full scale of the output bits.

Decimal Coefficient

Quantized Coefficient (21-Bit)

5, 44

−0.000544

−0.000870

−0.000962

−0.000448

0.000977

0.003237

0.005614

0.006714

0.004871

−0.001011

−0.010456

−0.020729

−0.026978

−0.023453

−0.005608

0.027681

0.072720

0.121223

0.162346

0.185959

−570

6, 43

−912

7, 42

−1009

−470

8, 41

When mixing a complex input signal down to baseband, the mixer

has already recentered the dynamic range of the signal within

the full scale of the output bits, and no additional gain is necessa-

ry. However, the optional 6 dB gain compensates for low signal

strengths. The downsample by 2 portion of the HB1 FIR filter is

bypassed when using the complex to real conversion stage. The

TB1 filter does not have the 6 dB gain stage.

9, 40

1024

10, 39

11, 38

12, 37

13, 36

14, 35

15, 34

16, 33

17, 32

18, 31

19, 30

20, 29

21, 28

22, 27

23, 26

24, 25

3394

5887

7040

5108

−1060

−10964

−21736

−28288

−24592

−5880

29026

76252

127112

170232

194992

DDC COMPLEX TO REAL CONVERSION

Each DDC contains an independently controlled complex to real

conversion block. The complex to real conversion block reuses the

last filter (HB1 FIR) in the filtering stage along with an f_S/4 complex

mixer to upconvert the signal. After upconverting the signal, the Q

portion of the complex mixer is no longer needed and is dropped.

The TB1 filter does not support complex to real conversion.

Figure 97 shows a simplified block diagram of the complex to real

conversion.

Figure 96. FB2 Filter Response

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Figure 97. Complex to Real Conversion Block

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 25 shows the DDC sample mapping when the chip decima-

tion ratio is different than the DDC decimation ratio.

DDC MIXED DECIMATION SETTINGS

The AD9699 also supports DDCs with different decimation rates.

In this scenario, the chip decimation ratio must be set to the

lowest decimation ratio of all the DDC channels. Samples of higher

decimation ratio DDCs are repeated to match the chip decimation

ratio sample rate. Only mixed decimation ratios that are integer

multiples of 2 are supported. For example, decimate by 1, 2, 4, 8,

or 16 can be mixed together, decimate by 3, 6, 12, 24, or 48 can

be mixed together, or decimate by 5, 10, 20, or 40 can be mixed

together.

For example, if the chip decimation ratio is set to decimate by 4,

DDC0 is set to use the HB2 + HB1 filters (complex outputs are

decimate by 4) and DDC1 is set to use the HB4 + HB3 + HB2 +

HB1 filters (real outputs are decimate by 8), then DDC1 repeats

its output data two times for every one DDC0 output. The resulting

output samples are shown in Table 26.

Table 25. Sample Mapping when the Chip Decimation Ratio (DCM) Does Not Match DDC DCM

Sample Index

DDC DCM = Chip DCM

DDC DCM = 2 × Chip DCM

DDC DCM = 4 × Chip DCM

DDC DCM = 8 × Chip DCM

0

N

1

N + 1

N

2

N + 2

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N

3

N + 3

N

4

N + 4

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N

5

N + 5

N

6

N + 6

N

7

N + 7

N

8

N + 8

N + 1

N + 2

N + 3

9

N + 9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

N + 16

N + 17

N + 18

N + 19

N + 20

N + 21

N + 22

N + 23

N + 24

N + 25

N + 26

N + 27

N + 28

N + 29

N + 30

N + 31

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 26. Chip DCM = 4, DDC0 DCM = 4 (Complex), and DDC1 DCM = 8 (Real)¹

DDC0

DDC1

Output Port Q

DDC Input Samples

Output Port I

Output Port Q

Output Port I

N

I0[N]

Q0[N]

I1[N]

Not applicable

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

N + 7

N + 8

N + 9

N + 10

N + 11

N + 12

N + 13

N + 14

N + 15

I0[N]

Q0[N]

I1[N]

I0[N]

Q0[N]

I1[N]

I0[N]

Q0[N]

I1[N]

I0[N + 1]

I0[N + 2]

I0[N + 3]

Q0[N + 1]

Q0[N + 2]

Q0[N + 3]

I1[N]

I1[N + 1]

1

DCM means decimation.

DDC EXAMPLE CONFIGURATIONS

Table 27 describes the register settings for multiple DDC example configurations.

Table 27. DDC Example Configurations (Per ADC Channel Pair)

No. of Virtual

Chip Application Chip Decimation DDC Output Bandwidth Per

Converters

Required

Layer

Ratio

Type

DDC¹

Register Settings

Two DDCs

4

Real

10% × f_S

2

0x0200 = 0x22 (two DDCs, I only selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x49 (real mixer, 6 dB gain variable IF, real output, HB3

+ HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 decimation rate selection)

0x0331 = 0x00 (DDC1 decimation rate selection)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E,

0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by

application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E,

0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by

application for DDC1

Two DDCs

4

Complex

20% × f_S

4

0x0200 = 0x02 (two DDCs, I/Q selected)

0x0201 = 0x02 (chip decimate by 4)

0x0310, 0x0330 = 0x40 (real mixer, 6 dB gain, variable IF, complex output,

HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 decimation rate selection)

0x0331 = 0x00 (DDC1 decimation rate selection)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E,

0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by

application for DDC0

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 27. DDC Example Configurations (Per ADC Channel Pair)

Chip Application Chip Decimation DDC Output Bandwidth Per

No. of Virtual

Converters

Required

Layer

Ratio

Type

DDC¹

Register Settings

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E,

0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by

application for DDC1

Two DDCs

8

Real

5% × f_S

2

0x0200 = 0x22 (two DDCs, I only selected)

0x0201 = 0x03 (chip decimate by 8)

0x0310, 0x0330 = 0x4A (real mixer, 6 dB gain, variable IF, real output, HB4

+ HB3 + HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 decimation rate selection)

0x0331 = 0x00 (DDC1 decimation rate selection)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E,

0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by

application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E,

0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by

application for DDC1

Four DDCs

8

Complex

10% × f_S

8

0x0200 = 0x03 (four DDCs, I/Q selected)

0x0201 = 0x03 (chip decimate by 8)

0x0310, 0x0330, 0x0350, 0x0370 = 0x41 (real mixer, 6 dB gain, variable IF,

complex output, HB3 + HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 decimation rate selection)

0x0331 = 0x00 (DDC1 decimation rate selection)

0x0311 = 0x00 (DDC2 decimation rate selection)

0x0331 = 0x00 (DDC3 decimation rate selection)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E,

0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by

application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E,

0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by

application for DDC1

0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E,

0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by

application for DDC2

0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E,

0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by

application for DDC3

Four DDCs

8

Real

5% × f_S

4

0x0200 = 0x23 (four DDCs, I only selected)

0x0201 = 0x03 (chip decimate by 8)

0x0310, 0x0330, 0x0350, 0x0370 = 0x4A (real mixer, 6 dB gain, variable IF,

real output, HB4 + HB3 + HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 decimation rate selection)

0x0331 = 0x00 (DDC1 decimation rate selection)

0x0311 = 0x00 (DDC2 decimation rate selection)

0x0331 = 0x00 (DDC3 decimation rate selection)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E,

0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by

application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E,

0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by

application for DDC1

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Data Sheet

AD9699

DIGITAL DOWNCONVERTER (DDC)

Table 27. DDC Example Configurations (Per ADC Channel Pair)

Chip Application Chip Decimation DDC Output Bandwidth Per

No. of Virtual

Converters

Required

Layer

Ratio

Type

DDC¹

Register Settings

0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E,

0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by

application for DDC2

0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E,

0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by

application for DDC3

Four DDCs

16

Complex

5% × f_S

8

0x0200 = 0x03 (four DDCs, I/Q selected)

0x0201 = 0x04 (chip decimate by 16)

0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer, 6 dB gain, variable IF,

complex output, HB4 + HB3 + HB2 + HB1 filters)

0x0311 = 0x00 (DDC0 decimation rate selection)

0x0331 = 0x00 (DDC1 decimation rate selection)

0x0311 = 0x00 (DDC2 decimation rate selection)

0x0331 = 0x00 (DDC3 decimation rate selection)

0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E,

0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by

application for DDC0

0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E,

0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by

application for DDC1

0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E,

0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by

application for DDC2

0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E,

0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by

application for DDC3

1

f_Sis the ADC sample rate.

DDC POWER CONSUMPTION

Table 28 describes the typical and maximum DVDD and DRVDD1 power for certain DDC modes; f_S= 3 GHz in all cases.

Table 28. DDC Power Consumption for Example Configurations

DVDD Power (mW)

DRVDD1 Power (mW)

Number of

DDCs

DDC Decimation

Ratio¹

Number of

Lanes (L)

Number of Virtual

Converters (M)

Number of Octets per

Frame (F)

Typ

Max

Typ

Max

2

4

2

8

4

2

8

4

8

1

2

4

2

615

675

585

590

570

585

745

755

715

1190

1250

1150

1145

1120

1135

1350

1365

1320

415

310

250

175

145

105

415

305

250

565

435

370

275

245

205

570

440

370

3

4

6

8

12

4

6

8

1

See Table 16 and Table 17 for details on decimation filter selection, the associated alias protected bandwidths, and SNR improvements.

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Data Sheet

AD9699

SIGNAL MONITOR

The signal monitor block provides additional information about the

signal being digitized by the ADC. The signal monitor computes

the peak magnitude of the digitized signal. This information can be

used to drive an AGC loop to optimize the range of the ADC in the

presence of real-world signals.

When the monitor period timer reaches a count of 1, the 13-bit

peak level value is transferred to the signal monitor holding register,

which can be read through the memory map or output through the

SPORT over the JESD204B interface. The monitor period timer is

reloaded with the value in the SMPR, and the countdown restarts.

In addition, the magnitude of the first input sample is updated in

the magnitude storage register, and the comparison and update

procedure, as explained previously, continues.

The results of the signal monitor block can be obtained either by

reading back the internal values from the SPI port or by embedding

the signal monitoring information into the JESD204B interface as

separate control bits. A global, 24-bit programmable period controls

the duration of the measurement. Figure 98 shows the simplified

block diagram of the signal monitor block.

To enable Signal Monitor feature:

1. Enable signal monitoring and set SMPR accordingly.

2. Write result update bit through SPI (register 0x274[4]). This

would update the frame counter and the signal monitor result.

Please see register map for more details.

3. Read frame counter register (0x278)

4. Repeat steps 2 and 3, until the frame counter register (0x278)

read back a different value. This indicates that the signal moni-

tor result has been updated and is ready for read back.

5. Read signal monitor result (registers 0x275 to 0x277). The

signal monitor result is 13 bit. Only the upper 13 bit of the 20-bit

word read back is valid (MSB aligned).

SPORT OVER JESD204B

Figure 98. Signal Monitor Block

The signal monitor data can also be serialized and sent over the

JESD204B interface as control bits. These control bits must be

deserialized from the samples to reconstruct the statistical data.

The signal control monitor function is enabled by setting Bits[1:0]

of Register 0x0279 and Bit 1 of Register 0x027A. Figure 99 shows

two different example configurations for the signal monitor control

bit locations inside the JESD204B samples. A maximum of three

control bits can be inserted into the JESD204B samples. However,

only one control bit is required for the signal monitor. Control bits

are inserted from MSB to LSB. If only one control bit is to be

inserted (CS = 1), only the most significant control bit is used

(see Example Configuration 1 and Example Configuration 2 in

Figure 99). To select the SPORT over JESD204B option, program

Register 0x0559, Register 0x055A, and Register 0x058F. See Table

44 for more information on setting these bits.

The peak detector captures the largest signal within the observation

period. The detector only observes the magnitude of the signal. The

resolution of the peak detector is a 13-bit value, and the observa-

tion period is 24 bits and represents converter output samples. The

peak magnitude can be derived by using the following equation:

Peak Magnitude (dBFS) = 20log(Peak Detector Value/2¹³

)

The magnitude of the input port signal is monitored over a program-

mable time period, which is determined by the signal monitor period

register (SMPR). The peak detector function is enabled by setting

Bit 1 in the signal monitor control register (Register 0x0270). The

24-bit SMPR must be programmed before activating this mode.

After enabling peak detection mode, the value in the SMPR is load-

ed into a monitor period timer, which decrements at the decimated

clock rate. The magnitude of the input signal is compared with the

value in the internal magnitude storage register (not accessible to

the user), and the greater of the two is updated as the current peak

level. The initial value of the magnitude storage register is set to

the current ADC input signal magnitude. This comparison continues

until the monitor period timer reaches a count of 1.

Figure 100 shows the 25-bit frame data that encapsulates the peak

detector value. The frame data is transmitted MSB first with five

5-bit subframes. Each subframe contains a start bit that can be

used by a receiver to validate the deserialized data. Figure 101

shows the SPORT over JESD204B signal monitor data with a

monitor period timer set to 80 samples.

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Data Sheet

AD9699

SIGNAL MONITOR

Figure 99. Signal Monitor Control Bit Locations

Figure 100. SPORT over JESD204B Signal Monitor Frame Data

Figure 101. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples

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Data Sheet

AD9699

DIGITAL OUTPUTS

► N is the converter resolution. AD9699 value = 7 to 16.

► CS is the number of control bits per sample.

AD9699 value = 0, 1, 2, or 3.

► K is the number of frames per multiframe.

AD9699 value = 4, 8, 12, 16, 20, 24, 28, or 32.

► S is the samples transmitted per single converter per frame

cycle. AD9699 value is set automatically based on L, M, F, and

N΄.

► HD is the high density mode. the AD9699 mode is set automati-

cally based on L, M, F, and N΄.

► CF is the number of control words per frame clock cycle per

converter device. AD9699 value = 0.

INTRODUCTION TO THE JESD204B

INTERFACE

The AD9699 digital outputs are designed to the JEDEC standard

JESD204B, serial interface for data converters. JESD204B is a

protocol to link the AD9699 to a digital processing device over a

serial interface with lane rates of up to 16 Gbps. The benefits of

the JESD204B interface over LVDS include a reduction in required

board area for data interface routing and an ability to enable smaller

packages for converter and logic devices.

JESD204B OVERVIEW

The JESD204B data transmit block assembles the parallel data

from the ADC into frames and uses 8-bit/10-bit encoding as well as

optional scrambling to form serial output data. Lane synchronization

is supported through the use of separate control characters during

the initial establishment of the link. Additional control characters

are embedded in the data stream to maintain synchronization

thereafter. A JESD204B receiver is required to complete the serial

link. For additional details on the JESD204B interface, refer to the

JESD204B standard.

Figure 102 shows a simplified block diagram of the AD9699

JESD204B link. By default, the AD9699 is configured to use

one converter and four lanes. The converter data is output to

SERDOUT0± and/or SERDOUT1± and/or SERDOUT2± and/or

SERDOUT3±.

By default in the AD9699, the 14-bit converter word is broken into

two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are

in the first octet. The second octet contains Bit 5 through Bit 0

(LSB) and two tail bits. The tail bits can be configured as zeros or

as a pseudorandom number sequence. The tail bits can also be

replaced with control bits indicating overrange, SYSREF±, or fast

detect output.

The AD9699 JESD204B data transmit block maps one physical

ADC or up to eight virtual converters (when DDCs are enabled)

over a link. A link can be configured to use one, two, four, or eight

JESD204B lanes. The JESD204B specification refers to a number

of parameters to define the link, and these parameters must match

between the JESD204B transmitter (the AD9699 output) and the

JESD204B receiver (the logic device input).

The two resulting octets can be scrambled. Scrambling is optional.

However, it is recommended to avoid spectral peaks when transmit-

ting similar digital data patterns. The scrambler uses a self synchro-

nizing, polynomial-based algorithm defined by the equation 1 +

x¹⁴+ x¹⁵. The descrambler in the receiver is a self synchronizing

version of the scrambler polynomial.

The JESD204B link is described according to the following parame-

ters:

► L is the number of lanes per converter device (lanes per link).

AD9699 value = 1, 2, 4, or 8.

► M is the number of converters per converter device (virtual

converters per link). AD9699 value = 1, 2, 4, or 8.

► F is the octets per frame. AD9699 value = 1, 2, 4, 8, or 16.

► N΄ is the number of bits per sample (JESD204B word size).

AD9699 value = 8 or 16.

The two octets are then encoded with an 8-bit/10-bit encoder. The

8-bit/10-bit encoder works by taking eight bits of data (an octet)

and encoding them into a 10-bit symbol. Figure 103 shows how the

14-bit data is taken from the ADC, how the tail bits are added, how

the two octets are scrambled, and how the octets are encoded into

two 10-bit symbols. Figure 103 shows the default data format.

Figure 102. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)

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Data Sheet

AD9699

DIGITAL OUTPUTS

Figure 103. ADC Output Datapath Showing Data Framing

Figure 104. Data Flow

FUNCTIONAL OVERVIEW

Physical Layer

The block diagram in Figure 104 shows the flow of data through the

JESD204B hardware from the sample input to the physical output.

The processing can be divided into layers that are derived from

the open source initiative (OSI) model widely used to describe the

abstraction layers of communications systems. These layers are

the transport layer, data link layer, and physical layer (serializer and

output driver).

The physical layer consists of the high speed circuitry clocked at

the serial clock rate. In this layer, parallel data is converted into one,

two, or four lanes of high speed differential serial data.

JESD204B LINK ESTABLISHMENT

The AD9699 JESD204B transmitter (Tx) interface operates in

Subclass 1 as defined in the JEDEC Standard 204B (July 2011

specification). The link establishment process is divided into the

following steps: code group synchronization and SYNCINB±, initial

lane alignment sequence, and user data and error correction.

Transport Layer

The transport layer handles packing the data (consisting of samples

and optional control bits) into JESD204B frames that are mapped

to 8-bit octets. These octets are sent to the data link layer. The

transport layer mapping is controlled by rules derived from the link

parameters. Tail bits are added to fill gaps where required. The

following equation can be used to determine the number of tail bits

within a sample (JESD204B word):

Code Group Synchronization (CGS) and

SYNCINB±

The CGS is the process by which the JESD204B receiver finds the

boundaries between the 10-bit symbols in the stream of data. Dur-

ing the CGS phase, the JESD204B transmit block transmits /K28.5/

characters. The receiver must locate /K28.5/ characters in its input

data stream using clock and data recovery (CDR) techniques.

T = N΄ – N – CS

Data Link Layer

The receiver issues a synchronization request by asserting the

SYNCINB± pin of the AD9699 low. The JESD204B Tx then begins

sending /K/ characters. After the receiver synchronizes, it waits for

the correct reception of at least four consecutive /K/ symbols. It

then deasserts SYNCINB±. The AD9699 then transmits an ILAS on

the following LMFC boundary.

The data link layer is responsible for the low level functions

of passing data across the link. These functions include optionally

scrambling the data, inserting control characters for multichip syn-

chronization/lane alignment/monitoring, and encoding

8-bit octets into 10-bit symbols. The data link layer is also responsi-

ble for sending the initial lane alignment sequence (ILAS), which

contains the link configuration data used by the receiver to verify

the settings in the transport layer.

For more information on the code group synchronization phase, re-

fer to the JEDEC Standard JESD204B, July 2011, Section 5.3.3.1.

The SYNCINB± pin operation can also be controlled by the SPI.

The SYNCINB± signal is a differential dc-coupled LVDS mode

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Data Sheet

AD9699

DIGITAL OUTPUTS

signal by default, but it can also be driven single-ended. For more

information on configuring the SYNCINB± pin operation, refer to

Register 0x0572.

configuration data is to follow. All undefined data slots are filled with

ramp data. The ILAS sequence is never scrambled.

The ILAS sequence construction is shown in Figure 105. The four

multiframes include the following:

The SYNCINB± pins can also be configured to run in CMOS

(single-ended) mode, by setting Bit 4 in Register 0x0572. When

running SYNCINB± in CMOS mode, connect the CMOS SYNCINB

signal to Pin N13 (SYNCINB+) and leave Pin R13 (SYNCINB−)

floating.

► Multiframe 1 begins with an /R/ character (/K28.0/) and ends with

an /A/ character (/K28.3/).

► Multiframe 2 begins with an /R/ character followed by a /Q/

character (/K28.4/), followed by link configuration parameters

over 14 configuration octets (see Table 43) and ends with an /A/

character. Many of the parameter values are of the value − 1

notation.

► Multiframe 3 begins with an /R/ character (/K28.0/) and ends with

an /A/ character (/K28.3/).

► Multiframe 4 begins with an /R/ character (/K28.0/) and ends with

an /A/ character (/K28.3/).

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and begins on the next

LMFC boundary. The ILAS consists of four multiframes, with an /R/

character marking the beginning and an /A/ character marking the

end. The ILAS begins by sending an /R/ character followed by 0

to 255 ramp data for one multiframe. On the second multiframe,

the link configuration data is sent, starting with the third character.

The second character is a /Q/ character to confirm that the link

Figure 105. Initial Lane Alignment Sequence

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Data Sheet

AD9699

DIGITAL OUTPUTS

The AD9699 digital outputs can interface with custom ASICs and

field programmable gate array (FPGA) receivers, providing superior

switching performance in noisy environments. Single point-to-point

network topologies are recommended with a single differential 100

Ω termination resistor placed as close to the receiver inputs as

possible.

User Data and Error Detection

After the initial lane alignment sequence is complete, the user data

is sent. Normally, within a frame, all characters are considered user

data. However, to monitor the frame clock and multiframe clock

synchronization, there is a mechanism for replacing characters

with /F/ or /A/ alignment characters when the data meets certain

conditions. These conditions are different for unscrambled and

scrambled data. The scrambling operation is enabled by default.

However, it can be disabled using the SPI.

If there is no far end receiver termination, or if there is poor

differential trace routing, timing errors can result. To avoid such

timing errors, it is recommended that the trace length be less than

six inches, and that the differential output traces be close together

and at equal lengths.

For scrambled data, any 0xFC character at the end of a frame

is replaced by an /F/, and any 0x7C character at the end of a multi-

frame is replaced by an /A/. The JESD204B receiver (Rx) checks

for /F/ and /A/ characters in the received data stream and verifies

that they only occur in the expected locations. If an unexpected /F/

or /A/ character is found, the receiver handles the situation by using

dynamic realignment or asserting the SYNCINB± signal for more

than four frames to initiate a resynchronization. For unscrambled

data, if the final character of two subsequent frames is equal, the

second character is replaced with an /F/ if it is at the end of a frame,

and an /A/ if it is at the end of a multiframe.

Figure 106 to Figure 108 show examples of the digital output

data eye, jitter histogram, and bathtub curve, respectively, for one

AD9699 lane running at 16 Gbps. The format of the output data is

twos complement by default. To change the output data format, see

Memory Map section (Register 0x0561) for more details.

Insertion of alignment characters can be modified using the SPI.

The frame alignment character insertion (FACI) is enabled by

default. More information on the link controls is available in the

Memory Map section, Register 0x0571.

Figure 106. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps

8-Bit/10-Bit Encoder

The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols

and inserts control characters into the stream when needed. The

control characters used in JESD204B are shown in Table 43. The

8-bit/10-bit encoding ensures that the signal is dc balanced by

using the same number of ones and zeros across multiple symbols.

The 8-bit/10-bit interface has options that can be controlled via the

SPI. These operations include bypass and invert. These options

are troubleshooting tools for the verification of the digital front end

(DFE). See the Memory Map section, Register 0x0572, Bits[2:1] for

information on configuring the 8-bit/10-bit encoder.

Figure 107. Digital Outputs Jitter Histogram, External 100 Ω Terminations at

16 Gbps

PHYSICAL LAYER (DRIVER) OUTPUTS

Digital Outputs, Timing, and Controls

The AD9699 physical layer consists of drivers that are defined in

the JEDEC Standard JESD204B, July 2011. The differential digital

outputs are powered up by default. The drivers use a dynamic

100 Ω internal termination to reduce unwanted reflections.

Figure 108. Digital Outputs Bathtub Curve, External 100 Ω Terminations at 16

Gbps

Place a 100 Ω differential termination resistor at each receiver input

to result in a nominal 0.85 × DRVDD1 V p-p swing at the receiver.

The swing is adjustable through the SPI registers. AC coupling is

recommended to connect to the receiver. See the Memory Map

section (Register 0x05C0 to Register 0x05C3) for more details.

De-Emphasis

De-emphasis enables the receiver eye diagram mask to be met

in conditions where the interconnect insertion loss does not meet

the JESD204B specification. Use the de-emphasis feature only

when the receiver is unable to recover the clock due to excessive

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Data Sheet

AD9699

DIGITAL OUTPUTS

insertion loss. Under normal conditions, it is disabled to conserve

power. Additionally, enabling and setting too high a de-emphasis

value on a short link can cause the receiver eye diagram to fail.

Use the de-emphasis setting with caution because it can increase

electromagnetic interference (EMI). See the Memory Map section

(Register 0x05C4 to Register 0x05CB) for more details.

► L = 4

► M = 1

► F = 2

► S = 4

► N’ = 16

► N = 16

► CS = 0

► CF = 0

► HD = 0

Phase-Locked Loop (PLL)

The PLL generates the serializer clock, which operates at the

JESD204B lane rate. The status of the PLL lock can be checked in

the PLL locked status bit (Register 0x056F, Bit 7). This read only bit

notifies the user if the PLL achieved a lock for the specific setup.

Register 0x056F also has a loss of lock (LOL) sticky bit (Bit 3) that

notifies the user that a loss of lock is detected. The sticky bit can

be reset by issuing a JESD204B link restart (Register 0x0571 =

0x15, followed by Register 0x0571 = 0x14). Refer to Table 30 for

the reinitialization of the link following a link power cycle.

In f_S× 4 mode, five 12-bit ADC samples (along with an extra 4 bits)

are packed into four 16-bit JESD204B samples to create a 64-bit

frame.

The following SPI writes are necessary to place the device in f_S× 4

mode:

► Register 0x0570 = 0xFD. This setting places the device in M = 1,

L = 4, f_S× 4 mode.

► Register 0x058F = 0x0F. This setting places the device CS = 0,

N’ = 16 mode.

The JESD204B lane rate control, Bits[7:4] of Register 0x056E, must

be set to correspond with the lane rate. Table 29 shows the lane

rates supported by the AD9699 using Register 0x056E.

► Register 0x0590 = 0x2F. This setting places the device in Sub-

class 1 mode, N = 16.

Table 29. AD9699 Register 0x056E Supported Lane Rates

Value

Lane Rate

► Register 0x56E must be set based on lane rate. For example, at

3 GSPS, the lane rate in f_S× 4 mode is 12 Gbps. Register 0x56E

= 0x00.

► The lane rate of f_S× 4 mode can be calculated using the

following equation.

0x00

0x10

0x30

0x50

Lane rate = 6.75 Gbps to 13.5 Gbps

Lane rate = 3.375 Gbps to 6.75 Gbps

Lane rate = 13.5 Gbps to 15.5 Gbps (default for AD9699)

Lane rate = 1.6875 Gbps to 3.375 Gbps

F_S× 4 MODE

10

8

M × N′ ×

× f

S

Lane Rate f_S× 4 mode =

×

L

f_S× 4 mode adds a separate packing mode on top of a JESD204B

transmitter/receiver to fix the serial lane rate at four times the

sample rate (f_S).

data packing ratio

The JESD204B link settings are

where f_S× 4 data packing ratio = 4/5

► L = 4

► M = 1

► F = 2

► S = 5

► N’ = 12

► N = 12

► CS = 0

► CF = 2

► HD = 1

In the AD9699, M = 1 and N‘ = 16

Lane Rate (f_S× 4 mode) = 1 × 16 × (10/8) × f_S× 4/5/L = f_S× 16/L

For example:

f_S= 3 GSPS, L = 4

Lane Rate = 3 × 16/4 = 12 Gbps

The transmit architecture of f_S× 4 mode is shown in Figure 109 and

the receive portion is shown in Figure 110. f_S× 4 mode only works

in full bandwidth mode (Register 0x0200 = 0x00).

However, CF = 2 is not supported by the design. Therefore, the

following link parameters are used along with separate packing:

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Data Sheet

AD9699

DIGITAL OUTPUTS

Figure 109. f_S× 4 Mode (Transmit)

Figure 110. f_S× 4 Mode (Receive)

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Data Sheet

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DIGITAL OUTPUTS

If the internal DDCs are used for on-chip digital processing, M

SETTING UP THE AD9699 DIGITAL INTERFACE

represents the number of virtual converters. The virtual converter

mapping setup is shown in Figure 76.

To ensure proper operation of the AD9699 at startup, some SPI

writes are required to initialize the link. Additionally, these registers

must be written every time the ADC is reset. Any one of the

following resets warrants the initialization routine for the digital

interface:

The maximum lane rate allowed by the AD9699 is 16 Gbps. The

lane rate is related to the JESD204B parameters using the following

equation:

10

8

L

► Hard reset, as with power-up.

► Power-up using the PDWN pin.

M × N′ ×

× f

OUT

Lane Rate =

► Power-up using the SPI via Register 0x0002, Bits[1:0].

► SPI soft reset by setting Register 0x0000 = 0x81.

► Datapath soft reset by setting Register 0x0001 = 0x02.

► JESD204B link power cycle by setting Register 0x0571 = 0x15,

then 0x14.

f

ADC_CLOCK

where f_OUT

=

Decimation Ratio

The decimation ratio (DCM) is the parameter programmed in Regis-

ter 0x201.

Use the following procedure to configure the output:

The initialization SPI writes are as shown in Table 30.

1. Power down the link.

Table 30. AD9699 JESD204B Initialization

2. Select the JESD204B link configuration options.

3. Configure the detailed options.

4. Set output lane mapping (optional).

5. Set additional driver configuration options (optional).

6. Power up the link.

Register

Value

Comment

0x1228

0x1222

0x1262

0x4F

0x0F

0x00

0x04

0x00

0x08

0x00

Reset JESD204B start-up circuit

JESD204B start-up circuit in normal operation

JESD204B PLL force normal operation

Reset JESD204B PLL calibration

JESD204B PLL normal operation

Clear loss of lock bit

7. Initialize the JESD204B link by issuing the commands descri-

bed in Table 30.

If the lane rate calculated is less than 6.25 Gbps, select the low

lane rate option by programming a value of 0x10 to Regis-

ter 0x056E.

Loss of lock bit normal operation

The AD9699 has one JESD204B link. The serial outputs (SERD-

OUT0± to SERDOUT7±) are considered to be part of one

JESD204B link. The basic parameters that determine the link setup

are

Table 31, Table 32, and Table 33 show the JESD204B output con-

figurations supported for N΄ = 16, N' = 12, and N΄ = 8, respectively,

for a given number of virtual converters. Take care to ensure that

the serial lane rate for a given configuration is within the supported

range of 3.4 Gbps to 16 Gbps.

► Number of lanes per link (L)

► Number of converters per link (M)

► Number of octets per frame (F)

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Data Sheet

AD9699

DIGITAL OUTPUTS

Table 31. JESD204B Output Configurations for N΄ = 16¹

Number of

Virtual

Supported Decimation Rates

JESD204B Transport Layer Settings³

Converters

Supported

(Same as M)

JESD204B Lane Rate =

Serial Lane 1.7 Gbps to

Lane Rate =

3.4 Gbps to

6.8 Gbps

Lane Rate =

6.8 Gbps to

13.6 Gbps

Lane Rate =

13.6 Gbps to

15.5 Gbps

Rate²

3.4 Gbps

L

M

F

S

HD

N

N'

CS

K

1

20 × f_OUT

2, 4, 5, 6, 8, 10, 12, 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

20, 24 10, 12

2, 4, 5, 6, 8, 10, 12, 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1

2

1

0

8 to 16 16

0 to See

3

Note ⁴

20 × f_OUT

10 × f_OUT

5 × f_OUT

1, 2, 3, 4

1

2

4

8

1

2

4

1

2

1

2

1

2

4

2

1

2

4

8

1

0

1

0

1

0

1

0

0 to See

20, 24

10, 12

3

Note⁴

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

1

0 to See

3

Note⁴

1, 2, 3, 4, 5, 6, 8,

10, 12

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

1, 2, 3, 4

0 to See

3

Note⁴

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

1

0 to See

3

Note⁴

5 × f_OUT

1

0 to See

3

Note⁴

2.5 × f_OUT

40 × f_OUT

0 to See

3

Note⁴

1, 2, 3, 4

1, 2

1

0 to See

3

Note⁴

2

4, 8, 10, 12, 15, 16, 2, 4, 5, 6, 8, 10,

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

0 to See

20, 24, 30, 40, 48

12, 15, 16, 20,

24, 30

3

Note⁴

40 × f_OUT

4, 8, 10, 12, 15, 16, 2, 4, 5, 6, 8, 10,

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

1

2

8

2

0

8 to 16 16

0 to See

3

20, 24, 30, 40, 48

12, 15, 16, 20,

24, 30

Note⁴

20 × f_OUT

10 × f_OUT

5 × f_OUT

2, 4, 5, 6, 8, 10, 12, 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

15, 16, 20, 24, 30 10, 12, 15, 16

2, 4, 5, 6, 8, 10, 12, 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

2

4

8

2

4

1

2

1

2

1

2

1

2

4

0

1

0

1

0

8 to 16 16

0 to See

3

Note⁴

1, 2, 3, 4

0 to See

15, 16, 20, 24, 30

10, 12, 15, 16

3

Note⁴

1, 2, 3, 4, 5, 6, 8,

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

1

0 to See

3

Note⁴

1, 2, 3, 4, 5, 6, 8,

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

0 to See

3

Note⁴

1, 2, 3, 4, 5, 6, 8

0 to See

3

Note⁴>

5 × f_OUT

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

1

0 to See

3

Note⁴

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Data Sheet

AD9699

DIGITAL OUTPUTS

Table 31. JESD204B Output Configurations for N΄ = 16¹

Number of

Virtual

Supported Decimation Rates

JESD204B Transport Layer Settings³

Converters

Supported

(Same as M)

JESD204B Lane Rate =

Serial Lane 1.7 Gbps to

Lane Rate =

3.4 Gbps to

6.8 Gbps

Lane Rate =

6.8 Gbps to

13.6 Gbps

Lane Rate =

13.6 Gbps to

15.5 Gbps

Rate²

3.4 Gbps

L

M

F

S

HD

N

N'

CS

K

4

80 × f_OUT

8, 16, 20, 24, 30,

40, 48

4, 8, 10, 12, 16,

20, 24, 30, 40, 48 16, 20, 24, 30

2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10,

1

4

8

1

0

8 to 16 16

0 to See

3

12, 16

Note⁴

40 × f_OUT

4, 8, 10, 12, 15, 16, 2, 4, 5, 6, 8, 10,

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

2

4

8

1

2

0

8 to 16 16

0 to See

3

20, 24, 30, 40, 48

12, 15, 16, 20,

24, 30

Note⁴

4, 8, 10, 12, 15, 16, 2, 4, 5, 6, 8, 10,

1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

10, 12, 15, 16

8 to 16 16

0 to See

20, 24, 30, 40, 48

12, 15, 16, 20,

24, 30

3

Note⁴

20 × f_OUT

10 × f_OUT

160 × f_OUT

80 × f_OUT

40 × f_OUT

20 × f_OUT

2, 4, 5, 6, 8, 10, 12, 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

15, 16, 20, 24, 30 10, 12, 15, 16

2, 4, 5, 6, 8, 10, 12, 1, 2, 3, 4, 5, 6, 8, 1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1, 2

4

8

1

2

4

8

4

8

2

4

1

2

1

2

1

2

1

2

0

1

0

8 to 16 16

0 to See

3

Note⁴

0 to See

15, 16, 20, 24, 30

10, 12, 15, 16

3

Note⁴

1, 2, 3, 4, 5, 6, 8,

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8

1, 2, 3, 4

1

0 to See

3

Note⁴

1, 2, 3, 4, 5, 6, 8,

10, 12, 15, 16

1, 2, 3, 4, 5, 6, 8

1, 2

2

0 to See

3

Note⁴

8

16, 40, 48

8, 16, 20, 24, 40, 4, 8, 12, 16, 20,

4, 8, 12, 16, 20,

24

16

8

0 to See

48

24, 40, 48

3

Note⁴

8, 16, 20, 24, 40,

48

4, 8, 10, 12, 16,

20, 24, 40, 48

2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10,

16, 20, 24 12, 16

0 to See

3

Note⁴

4, 8, 10, 12, 16, 20, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8

24, 40, 48 16, 20, 24 16

4, 8, 10, 12, 16, 20, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8, 10, 12, 2, 4, 6, 8

4

0 to See

3

Note⁴

8

0 to See

24, 40, 48

16, 20, 24

16

3

Note⁴

2, 4, 6, 8, 10, 12,

16, 20, 24

2, 4, 6, 8, 10, 12, 2, 4, 6, 8

16

2, 4

2

0 to See

3

Note⁴

2, 4, 6, 8, 10, 12,

16, 20, 24

2, 4, 6, 8, 10, 12, 2, 4, 6, 8

16

4

0 to See

3

Note⁴

1

Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.

2

f_{ADC_CLK}is the ADC sample rate, DCM = chip decimation ratio, f_OUTis the output sample rate = f_{ADC_CLK}/DCM, SLR is the JESD204B serial lane rate. The following

equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps, SLR/40 ≤ f_{ADC_CLK}, least common multiple (20 × DCM ×

f_OUT/SLR, DCM) ≤ 64. When the SLR is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps,

Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5

Mbps, Register 0x056E must be set to 0x50.

3

4

JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link), M is the number of virtual converters per converter

device (virtual converters per link), F is the octets per frame, S is the samples transmitted per virtual converter per frame cycle, HD is the high density mode, N is the virtual

converter resolution (in bits), N' is the total number of bits per sample (JESD204B word size), CS is the number of control bits per conversion sample, and K is the number

of frames per multiframe.

Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32, for F = 2, K = 12, 16, 20, 24, 28, 32, for F = 4, K = 8, 12, 16, 20, 24, 28, 32, for F =

8, K = 4, 8, 12, 16, 20, 24, 28, 32, and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

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Data Sheet

AD9699

DIGITAL OUTPUTS

Table 32. JESD204B Output Configurations (N' = 12)¹

Number of

Virtual

Supported Decimation Rates

JESD204B Transport Layer Settings³

Converters

Supported

(Same Value as Lane

JESD204B

Serial

Lane Rate =

1.7 Gbps to

3.4 Gbps

Lane Rate =

3.4 Gbps to

6.8 Gbps

Lane Rate =

6.8 Gbps to

13.5 Gbps

Lane Rate =

13.5 Gbps

to 15.5 Gbps

M)

Rate²

L

M

F

S

HD

N

N'

12

CS

K

1

15 × f_OUT

7.5 × f_OUT

5 × f_OUT

3, 6, 12

3, 6

3, 6, 12

3, 6

3

1

3

2

0

8 to 12

0 to 3

See Note ⁴

See Note⁴

2

3

1

2

3

1

2

3

6

1

3

1

4

8

2

1

2

1

0

1

0

1

12

3, 6

3

1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4

1, 2

3, 6, 12

3, 6

1

2

4

30 × f_OUT

15 × f_OUT

10 × f_OUT

3, 6, 12, 24

3, 6, 12

3, 6, 12, 24

3, 6, 12

1, 2, 3, 4, 5, 6,

8, 10, 12, 16

1, 2, 3, 4, 5, 6, 8 1, 2, 3, 4

1, 2

7.5 × f_OUT

60 × f_OUT

30 × f_OUT

20 × f_OUT

3, 6

3

4

1

2

3

2

4

3

6

3

2

4

1

0

1

8 to 12

12

0 to 3

See Note⁴

6, 12, 24, 48

3, 6, 12, 24

3, 6, 12, 24, 48

3, 6, 12, 24

3, 6, 12

2, 4, 5, 6, 8, 10, 1, 2, 3, 4, 5, 6,

12, 16, 20, 24

1, 2, 3, 4, 5,

6, 8

1, 2, 3, 4

8, 10, 12, 16

15 × f_OUT

60 × f_OUT

30 × f_OUT

3, 6, 12

3, 6

4

2

4

8

3

6

3

2

1

0

8 to 12

12

0 to 3

See Note⁴

8

6, 12, 24, 48

6, 12, 24

6, 12, 24, 48

6, 12, 24

6, 12

1

Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.

2

f_{ADC_CLK}is the ADC sample rate, DCM is the chip decimation ratio, f_OUTis the output sample rate = f_{ADC_CLK}/DCM, SLR is the JESD204B serial lane rate. The following

equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps, SLR/40 ≤ f_{ADC_CLK}, least common multiple (20 × DCM ×

f_OUT/SLR, DCM) ≤ 64. When the SLR is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps,

Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5

Mbps, Register 0x056E must be set to 0x50.

3

4

JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link), M is the number of virtual converters per converter

device (virtual converters per link), F is the octets per frame, S is the samples transmitted per virtual converter per frame cycle, HD is the high density mode, N is the virtual

converter resolution (in bits), N' is the total number of bits per sample (JESD204B word size), CS is the number of control bits per conversion sample, and K is the number

of frames per multiframe.

Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32, for F = 2, K = 12, 16, 20, 24, 28, 32, for F = 4, K = 8, 12, 16, 20, 24, 28, 32, for F =

8, K = 4, 8, 12, 16, 20, 24, 28, 32, and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

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Data Sheet

AD9699

DIGITAL OUTPUTS

Table 33. JESD204B Output Configurations for N΄ = 8 ¹

Number of

Virtual

Supported Decimation Rates

JESD204B Transport Layer Settings³

Converters

Supported

(Same Value as Lane

JESD204B

Serial

Lane Rate =

1.7 Gbps to

3.4 Gbps

Lane Rate =

3.4 Gbps to

6.8 Gbps

Lane Rate =

6.8 Gbps to

13.5 Gbps

Lane Rate =

13.5 Gbps to

15.5 Gbps

M)

Rate²

L

M

F

S

HD

N

N'

CS

K

1

10 × f_OUT

1, 2, 3, 4, 5, 6,

8, 10, 12

1, 2, 3, 4, 5, 6, 1, 2, 3, 4

8

1, 2

1

2

4

1

2

1

0

7 to 8

8

0 to 1

See Note

4

1

2

10 × f_OUT

5 × f_OUT

1, 2, 3, 4, 5, 6,

8, 10, 12

1, 2, 3, 4, 5, 6, 1, 2, 3, 4

8

2

1

2

4

1

2

4

8

4

8

1

7 to 8

0 to 1

See

Note⁴

1, 2, 3, 4, 5, 6,

8

1, 2, 3, 4

1, 2

1

See

Note⁴

5 × f_OUT

1, 2, 3, 4, 5, 6,

8

1

See

Note⁴

5 × f_OUT

1, 2, 3, 4, 5, 6,

8

1

See

Note⁴

2.5 × f_OUT

20 × f_OUT

1, 2, 3, 4

See

Note⁴

1, 2, 3, 4

1, 2

1

See

Note⁴

2, 4, 5, 6, 8, 10, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 1, 2, 3, 4

12, 15, 16, 20,

24, 30

See

8, 10, 12, 15,

16

8

Note⁴

2

10 × f_OUT

1, 2, 3, 4, 5, 6,

8, 10, 12, 15,

16

1, 2, 3, 4, 5, 6, 1, 2, 3, 4

8

1, 2

2

1

2

1

2

0

7 to 8

8

0 to 1

See

Note⁴

1, 2, 3, 4, 5, 6,

8, 10, 12, 15,

16

1, 2, 3, 4, 5, 6, 1, 2, 3, 4

8

See

Note⁴

2

5 × f_OUT

1, 2, 3, 4, 5, 6,

8

1, 2, 3, 4

1, 2

1

4

2

1

2

4

2

4

8

0

7 to 8

8

0 to 1

See

Note⁴

1, 2, 3, 4, 5, 6,

8

See

Note⁴

1, 2, 3, 4, 5, 6,

8

See

Note⁴

1

Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.

2

f_{ADC_CLK}is the ADC sample rate, DCM is the chip decimation ratio, f_OUTis the output sample rate = f_{ADC_CLK}/DCM, SLR is the JESD204B serial lane rate. The following

equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps, SLR/40 ≤ f_{ADC_CLK}, least common multiple (20 × DCM ×

f_OUT/SLR, DCM) ≤ 64. When the SLR is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps,

Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5

Mbps, Register 0x056E must be set to 0x50.

3

4

JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link), M is the number of virtual converters per converter

device (virtual converters per link), F is the octets per frame, S is the samples transmitted per virtual converter per frame cycle, HD is the high density mode, N is the virtual

converter resolution (in bits), N' is the total number of bits per sample (JESD204B word size), CS is the number of control bits per conversion sample, and K is the number

of frames per multiframe.

Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32, for F = 2, K = 12, 16, 20, 24, 28, 32, for F = 4, K = 8, 12, 16, 20, 24, 28, 32, for F =

8, K = 4, 8, 12, 16, 20, 24, 28, 32, and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.

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Data Sheet

AD9699

DIGITAL OUTPUTS

Example 1—Full Bandwidth Mode

Example 2—ADC with DDC Option (One ADCs

Plus Two DDCs)

Figure 112. One ADCs Plus Two DDCs Mode (L = 2, M = 4, F = 4, S = 1)

This example shows the flexibility in the digital and lane configu-

rations for theAD9699. The sample rate is 3 GSPS. However,

the outputs are all combined in either two or four lanes, depending

on the input/output speed capability of the receiving device.

Figure 111. Full Bandwidth Mode

The AD9699 is set up as shown in Figure 111, with the following

configurations:

The AD9699 is set up as shown in Figure 112, with the following

configurations:

► One 14-bit converter at 3 GSPS.

► Full bandwidth application layer mode.

► Decimation filters bypassed.

► One 14-bit converters at 3 GSPS.

► Two DDC application layer mode with complex outputs (I/Q).

► Chip decimation ratio = 8.

The JESD204B output configuration is as follows:

► DDC decimation ratio = 8 (see Table 44).

► One virtual converter required (see Table 31).

► Output sample rate (f_OUT) = 3000/1 = 3000 MSPS.

The JESD204B output configuration is as follows:

► Four virtual converters required (see Table 31).

► Output sample rate (f_OUT) = 3000/8 = 375 MSPS.

The JESD204B supported output configurations are as follows (see

Table 31):

The JESD204B supported output configurations are as follows (see

Table 31):

► N΄ = 16 bits.

► N = 14 bits.

► L = 4, M = 1, and F = 1.

► CS = 0.

► N΄ = 16 bits.

► N = 14 bits .

► L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 2.

► CS = 0.

► K = 32.

► Output serial lane rate = 15 Gbps per lane.

► The PLL control register, Register 0x056E, is set to 0x30.

► Output serial lane rate = 15 Gbps per lane (L = 2) or 7.5 Gbps

per lane (L = 4).

For L = 2, set the PLL control register, Register 0x056E, to 0x30.

For L = 4, set the PLL control register, Register 0x056E, to 0x00.

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Data Sheet

AD9699

DETERMINISTIC LATENCY

Both ends of the JESD204B link contain various clock domains

distributed throughout each system. Data traversing from one clock

domain to a different clock domain can lead to ambiguous delays

in the JESD204B link. These ambiguities lead to non-repeatable

latencies across the link from one power cycle or link reset to the

next. Section 6 of the JESD204B specification addresses the issue

of deterministic latency with mechanisms defined as Subclass 1

and Subclass 2.

Figure 113. SYSREF and LMFC

Setting Deterministic Latency Registers

The AD9699 supports JESD204B Subclass 0 and Subclass 1

operation. Register 0x0590, Bits[7:5] set the subclass mode for

the AD9699 and its default is set for Subclass 1 operating mode

(Register 0x0590, Bit 5 = 1). If deterministic latency is not a

system requirement, Subclass 0 operation is recommended and the

SYSREF signal may not be required. Even in Subclass 0 mode, the

SYSREF signal may be required in an application where multiple

AD9699 devices must be synchronized with each other. This topic

is addressed in the Timestamp Mode section.

The JESD204B receiver in the logic device buffers data starting

on the LMFC boundary. If the total link latency in the system is

near an integer multiple of the LMFC period, it is possible that from

one power cycle to the next, the data arrival time at the receive

buffer may straddle an LMFC boundary. To ensure deterministic

latency in this case, a phase adjustment of the LMFC at either the

transmitter or receiver must be performed. Typically, adjustments

to accommodate the receive buffer are made to the LMFC of the

receiver. Alternatively, this adjustment can be made in the AD9699

using the LMFC offset register (Register 0x0578, Bits[4:0]). This

delays the LMFC in frame clock increments, depending on the F

parameter (number of octets per lane per frame). For F = 1, every

fourth setting (0, 4, 8, and so on) is valid and results in a four

frame clock shift. For F = 2, every other setting (0, 2, 4, and so

on) is valid and results in a two frame clock shift. For all other

values of F, each setting results in a one frame clock shift. Figure

114 shows that, when the link latency is near an LMFC boundary,

the local LMFC of the AD9699 can be adjusted to delay the data

arrival time at the receiver. Figure 115 shows how the LMFC of

the receiver is delayed to accommodate the receive buffer timing.

Consult the applicable JESD204B receiver user guide for details

on making this adjustment. If the total latency in the system is not

near an integer multiple of the LMFC period or if the appropriate

adjustments have been made to the LMFC phase at the clock

source, it is still possible to have variable latency from one power

cycle to the next. By design, the AD9699 has circuitry in place to

minimize this variation from power-up to power-up. In this case, the

user must check for the possibility that the setup and hold time

requirements for the SYSREF signal are not being met, by reading

the SYSREF setup/hold monitor register (Register 0x0128). This

function is described in the SYSREF± Setup/Hold Window Monitor

section.

SUBCLASS 0 OPERATION

If there is no requirement for multichip synchronization while operat-

ing in Subclass 0 mode (Register 0x0590, Bits[7:5]= 0),

the SYSREF input can be left disconnected. In this mode, the

relationship of the JESD204B clocks between the JESD204B trans-

mitter and receiver are arbitrary but does not affect the ability of the

receiver to capture and align the lanes within the link.

SUBCLASS 1 OPERATION

The JESD204B protocol organizes data samples into octets,

frames, and multiframes as described in the Transport Layer

section. The LMFC is synchronous with the beginnings of these

multiframes. In Subclass 1 operation, the SYSREF is used to

synchronize the LMFCs for each device in a link or across multiple

links (within the AD9699, SYSREF also synchronizes the internal

sample dividers), as shown in Figure 113. The JESD204B receiver

uses the multiframe boundaries and buffering to achieve consistent

latency across lanes (or even multiple devices), and also to achieve

a fixed latency between power cycles and link reset conditions.

Deterministic Latency Requirements

Several key factors are required for achieving deterministic latency

in a JESD204B Subclass 1 system.

If reading Register 0x0128 indicates there may be a timing prob-

lem, there are a few adjustments that can made in the AD9699.

Changing the SYSREF level that is used for alignment is possible

using the SYSREF transition select bit (Register 0x0120, Bit 4).

Also, changing which edge of CLK is used to capture SYSREF

can be done using the CLK edge select bit (Register 0x0120, Bit

3). Both of these options are described in the SYSREF Control

Features section. If neither of these measures helps to achieve an

acceptable setup and hold time, adjusting the phase of SYSREF

and/or the device clock (CLK±) may be required.

► SYSREF± signal distribution skew within the system must be

less than the desired uncertainty for the system.

► SYSREF± setup and hold time requirements must be met for

each device in the system.

► The total latency variation across all lanes, links, and devices

must be ≤1 LMFC periods (see Figure 113). This includes both

variable delays and the variation in fixed delays from lane to

lane, link to link, and device to device in the system.

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Data Sheet

AD9699

DETERMINISTIC LATENCY

Figure 114. Adjusting the JESD204B Tx LMFC in the AD9699

Figure 115. Adjusting the JESD204B Rx LMFC in the Logic Device

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Data Sheet

AD9699

MULTICHIP SYNCHRONIZATION

The flowchart in Figure 117 shows the internal mechanism for

multichip synchronization in the AD9699. There are two methods

by which multichip synchronization can take place, as determined

by the chip synchronization mode bit (Register 0x01FF, Bit 0). Each

method involves different applications of the SYSREF signal.

0x01FF, Bit 0) is set to 1, the timestamp method is used for

synchronization of multiple channels and/or devices. In this mode,

SYSREF resets the sample dividers and the JESD204B clocking.

When the chip sync mode is set to 1, the clocks are not reset.

Instead, the coinciding sample is timestamped using the JESD204B

control bits of that sample. To operate in timestamp mode, these

additional settings are necessary:

NORMAL MODE

The default state of the chip synchronization mode bit is 0,

► Continuous or N-shot SYSREF must be enabled (Regis-

ter 0x0120, Bits[2:1] = 1 or 2).

► At least one control bit must be enabled (Register 0x058F,

Bits[7:6] = 1, 2, or 3).

► Set the function for one of the control bits to SYSREF:

► Register 0x0559, Bits[3:0] = 5 if using Control Bit 0.

► Register 0x0559, Bits[7:4] = 5 if using Control Bit 1.

► Register 0x055A, Bits[3:0] = 5 if using Control Bit 2.

which configures the AD9699 for normal chip synchronization. The

JESD204B standard specifies the use of SYSREF to provide for

deterministic latency within a single link. This same concept, when

applied to a system with multiple converters and logic devices

can also provide multichip synchronization. In Figure 117, this is

referred to as normal mode. Following the process in the flowchart

ensures that the AD9699 is configured appropriately. The user must

also consult the logic devices user intellectual property (IP) guide to

ensure that the JESD204B receivers are configured appropriately.

Figure 116 shows how the input sample coincident with SYSREF

is timestamped and ultimately output of the ADC. In this example,

there are two control bits, and Control Bit 0 is the bit indicating

which sample was coincident with the SYSREF rising edge. Note

that the pipeline latencies for each channel are identical. If so

desired, the SYSREF timestamp delay register (Register 0x0123)

can be used to adjust the timing of which sample is time stamped.

TIMESTAMP MODE

For all AD9699 full bandwidth operating modes, the SYSREF input

can also be used to timestamp samples. This is another method by

which multiple channels and multiple devices can achieve synchro-

nization. This method is especially effective when synchronizing

multiple devices to one or more logic devices. The logic devices

buffer the data streams, identify the timestamped samples, and

align them. When the chip synchronization mode bit (Register

Note that time stamping is not supported by any AD9699 operating

modes that use decimation, or in f_S× 4 mode.

Figure 116. AD9699 Timestamping Example—CS = 2 (Register 0x058F, Bits[7:6] = 2), Control Bit 0 is SYSREF (Register 0x0559, Bits[3:0] = 5)

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Data Sheet

AD9699

MULTICHIP SYNCHRONIZATION

Figure 117. SYSREF Capture Scenarios and Multichip Synchronization

to divide by 8, the minimum pulse width is 16 CLK± cycles). When

using a continuous SYSREF signal (Register 0x0120, Bits[2:1] = 1),

the period of the SYSREF signal must be an integer multiple of the

LMFC. LMFC can be derived using the following formula:

SYSREF INPUT

The SYSREF input signal is used as a high accuracy system

reference for deterministic latency and multichip synchronization.

The AD9699 accepts a single-shot or periodic input signal. The

SYSREF mode select bits (Register 0x0120, Bits[2:1]) select the

input signal type and also arm the SYSREF state machine when

set. If in single- (or N) shot mode (Register 0x0120, Bits[2:1] = 2),

the SYSREF mode select bit self clears after the appropriate SYS-

REF transition is detected. The pulse width must have a minimum

width of two CLK± periods. If the clock divider (Register 0x010B,

Bits[3:0]) is set to a value other than divide by 1, multiply this

minimum pulse width requirement by the divide ratio (that is, if set

LMFC = ADC Clock/(S × K)

where:

S is the JESD204B parameter for number of samples per converter.

K is the number of frames per multiframe.

The input clock divider, DDCs, signal monitor block, and JESD204B

link are all synchronized using the SYSREF± input when in normal

synchronization mode (Register 0x01FF, Bit 0 = 0). The SYSREF±

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Data Sheet

AD9699

MULTICHIP SYNCHRONIZATION

input can also be used to timestamp an ADC sample to provide a

mechanism for synchronizing multiple AD9699 devices in a system.

For the highest level of timing accuracy, SYSREF± must meet

setup and hold requirements relative to the CLK± input. There

are several features in the AD9699 that can be used to ensure

these requirements are met. These features are described in the

SYSREF Control Features section.

Figure 119. SYSREF Low to High Transition Using Falling Edge Clock

Capture (Register 0x0120, Bit 4 = 1’b0, Register 0x0120, Bit 3 = 1’b1)

SYSREF Control Features

SYSREF is used, along with the input clock (CLK), as part of a

source-synchronous timing interface and requires setup and hold

timing requirements of −65 ps and 95 ps relative to the input clock

(see Figure 118). The AD9699 has several features that aid users

in meeting these requirements. First, the SYSREF sample event

can be defined as either a synchronous low to high transition or

synchronous high to low transition. Second, the AD9699 allows the

SYSREF signal to be sampled using either the rising edge or falling

edge of the input clock. Figure 118, Figure 119, Figure 120, and

Figure 121 show all four possible combinations.

Figure 120. SYSREF High to Low Transition Using Rising Edge Clock

Capture (Register 0x0120, Bit 4 = 1’b1, Register 0x0120, Bit 3 = 1’b0)

The third SYSREF related feature available is the ability to ignore a

programmable number (up to 16) of SYSREF events. The AD9699

is able to ignore N SYSREF events (note that the SYSREF ignore

feature is enabled by setting the SYSREF mode register (Register

0x0120, Bits[2:1]) to 2'b10, which is labeled as N-shot mode). This

feature is useful for handling periodic SYSREF signals, which need

time to settle after startup. Ignoring SYSREF until the clocks in

the system have settled can avoid an inaccurate SYSREF trigger.

Figure 122 shows an example of the SYSREF ignore feature when

ignoring three SYSREF events.

Figure 121. SYSREF High to Low Transition Using Falling Edge Clock

Capture (Register 0x0120, Bit 4 = 1’b1, Register 0x0120, Bit 3 = 1’b1)

Figure 118. SYSREF Setup and Hold Time Requirements—SYSREF Low to

High Transition Using Rising Edge Clock (Default)

Figure 122. SYSREF Ignore Example (SYSREF Ignore Count, Register 0x0121, Bits[3:0] = 3)

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Data Sheet

AD9699

MULTICHIP SYNCHRONIZATION

Figure 123. SYSREF Skew Window

When in continuous SYSREF mode (Register 0x0120, Bits[2:1] =

1), the AD9699 monitors the placement of the SYSREF leading

edge compared to the internal LMFC. If the SYSREF is captured

with a clock edge other than the one that is aligned with LMFC,

the AD9699 initiates a resynchronization of the link. Because input

clock rates for AD9699 can be up to 4 GHz, the AD9699 provides

another SYSREF related feature that makes it possible to accom-

modate periodic SYSREF signals where cycle accurate capture is

not feasible or not required. For these scenarios, the AD9699 has

a programmable SYSREF skew window that allows the internal

dividers to remain undisturbed unless SYSREF occurs outside the

skew window. The resolution of the SYSREF skew window is set

in sample clock cycles. If the SYSREF negative skew window is

1 and the positive skew window is 1, the total skew window is

±1 sample clock cycles, meaning that, as long as SYSREF is

captured within ±1 sample clock cycle of the clock that is aligned

with LMFC, the link continues to operate normally. If the SYSREF

has jitter, which can cause a misalignment between SYSREF and

LMFC, this feature allows the system to continue running without

a resynchronization, while still allowing the device to monitor for

larger errors not caused by jitter. For the AD9699, the positive

and negative skew window is controlled by the SYSREF window

negative register (Register 0x0122, Bits[3:2]) and SYSREF window

positive register (Register 0x0122, Bits[1:0]). Figure 123 shows

information on the location of the skew window settings relative

to Phase 0 of the internal dividers. Negative skew is defined as

occurring before the internal dividers reach Phase 0, and positive

skew is defined after the internal dividers reach Phase 0.

SYSREF± SETUP/HOLD WINDOW MONITOR

To ensure a valid SYSREF signal capture, the AD9699 has a SYS-

REF± setup/hold window monitor. This feature allows the system

designer to determine the location of the SYSREF± signals relative

to the CLK± signals by reading back the amount of setup/hold

margin on the interface through the memory map. Figure 124 and

Figure 125 show the setup and hold status values for different

phases of SYSREF±. The setup detector returns the status of the

SYSREF± signal before the CLK± edge, and the hold detector

returns the status of the SYSREF signal after the CLK± edge.

Register 0x0128 stores the status of SYSREF± and notifies the

user if the SYSREF± signal is captured by the ADC.

Table 34 shows the description of the contents of Register 0x0128

and how to interpret them.

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Data Sheet

AD9699

MULTICHIP SYNCHRONIZATION

Figure 124. SYSREF± Setup Detector

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Data Sheet

AD9699

MULTICHIP SYNCHRONIZATION

Figure 125. SYSREF± Hold Detector

Table 34. SYSREF± Setup/Hold Monitor, Register 0x0128

Register 0x0128, Bits[7:4]

Hold Status

Register 0x0128, Bits[3:0]

Setup Status

Description

0x0

0x0 to 0x7

0x8

Possible setup error. The smaller this number, the smaller the setup margin.

0x0 to 0x8

0x8

No setup or hold error (best hold margin).

0x9 to 0xF

0x0

No setup or hold error (best setup and hold margin).

No setup or hold error (best setup margin).

0x8

0x9 to 0xF

0x0

Possible hold error. The larger this number, the smaller the hold margin.

Possible setup or hold error.

0x0

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Data Sheet

AD9699

LATENCY

END TO END TOTAL LATENCY

EXAMPLE LATENCY CALCULATIONS

Total latency in the AD9699 is dependent on the chip application

mode and the JESD204B configuration. For any given combination

of these parameters, the latency is deterministic, however, the

value of this deterministic latency must be calculated as described

in the Example Latency Calculations section.

Example Configuration 1 is as follows:

► ADC application mode = full bandwidth

► Real outputs

► L = 4, M = 1, F = 1, S = 2 (JESD204B mode)

► 20 × (M/L) = 5

Table 35 shows the combined latency through the ADC and DSP

for the different chip application modes supported by the AD9699.

Table 36 shows the latency through the JESD204B block for each

application mode based on the M/L ratio. For both tables, latency is

typical and is in units of the encode clock. The latency through the

JESD204B block does not depend on the output data type (real or

complex). Therefore, data type is not included in Table 36.

► Latency = 31 + 44 = 75 encode clocks

Example Configuration 2 is as follows:

► ADC application mode = DCM4

► Complex outputs

► L = 4, M = 2, F = 1, S = 1 (JESD204B mode)

► 20 × (M/L) = 10

To determine the total latency, select the appropriate ADC + DSP

latency from Table 35 and add it to the appropriate JESD204B

latency from Table 36. Example calculations are provided in the

Example Latency Calculations section.

► Latency = 162 + 88 = 250 encode clocks

LMFC REFERENCED LATENCY

Some FPGA vendors may require the end user to know LMFC-ref-

erenced latency to make appropriate deterministic latency adjust-

ments. If they are required, the latency values in Table 35 and Table

36 can be used for the analog input to LMFC and LMFC to data

output latency values, respectively.

Table 35. Latency Through the ADC + DSP Blocks (Number of Sample Clocks)¹

Chip Application Mode

Enabled Filters

ADC + DSP Latency

Full Bandwidth

DCM1 (Real)

Not applicable

31

HB1

90

DCM2 (Complex)

DCM3 (Complex)

DCM2 (Real)

HB1

90

TB1

102

162

212

292

380

424

500

552

694

814

836

1420

1594

HB2 + HB1

DCM4 (Complex)

DCM3 (Real)

HB2 + HB1

TB2 + HB1

DCM6 (Complex)

DCM4 (Real)

TB2 + HB1

HB3 +HB2 + HB1

FB2 + HB1

DCM8 (Complex)

DCM5 (Real)

DCM10 (Complex)

DCM6 (Real)

FB2 + HB1

TB2 + HB2 + HB1

FB2 + TB1

DCM12 (Complex)

DCM15 (Real)

DCM8 (Real)

HB4 + HB3 + HB2 + HB1

FB2 + HB2 + HB1

TB2 + HB3 + HB2 + HB1

HB2 + FB2 + TB1

FB2 + HB3 + HB2 + HB1

TB2 + HB4 + HB3 + HB2 + HB1

DCM16 (Complex)

DCM10 (Real)

DCM20 (Complex)

DCM12 (Real)

DCM24 (Complex)

DCM30 (Complex)

DCM20 (Real)

DCM40 (Complex)

DCM24 (Real)

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Data Sheet

AD9699

LATENCY

Table 35. Latency Through the ADC + DSP Blocks (Number of Sample Clocks)¹

Chip Application Mode

Enabled Filters

ADC + DSP Latency

DCM48 (Complex)

TB2 + HB4 + HB3 + HB2 + HB1

1594

1

DCMx indicates the decimation ratio.

Table 36. Latency Through JESD204B Block (Number of Sample Clocks)¹

M/L Ratio²

Chip Application Mode

0.125

0.25

0.5

1

2

4

8

Full Bandwidth

f_S× 4 Mode

DCM1

82

44

25

14

7

9

3

N/A

82

46

N/A

25

N/A

14

N/A

7

N/A

7

N/A

9

44

DCM2

160

237

315

N/A

84

46

27

14

DCM3

124

164

203³

243

323

N/A

67

39

21

11

DCM4

88

50

62³

27

43³

14

DCM5

109³

130

172

213

255

318⁴

339⁴

N/A

21

N/A

14

DCM6

73

39

DCM8

96

50

27

18

DCM10

DCM12

DCM15

DCM16

DCM20

DCM24

DCM30

DCM40

DCM48

119

142

176⁴

188⁴

233

279

348⁴

N/A

62

33

22

73

39

27

90⁴

96⁴

119

142

176⁴

233⁴

279⁴

47⁴

50⁴

62

33 ⁴

35⁴

43

73

51

90⁴

119⁴

142⁴

62⁴

82⁴

97⁴

1

N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed.

The M/L ratio is the number of converters divided by the number of lanes for the configuration.

The application mode at the M/L ratio listed is only supported in real output mode.

2

3

4

The application mode at the M/L ratio listed is only supported in complex output mode.

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Data Sheet

TEST MODES

AD9699

If the application mode is set to select a DDC mode of operation,

the test modes must be enabled for each DDC enabled. The test

patterns can be enabled via Bit 0 of Register 0x0327, Register

0x0347, Register 0x0367, and Register 0x0387 depending on

which DDC(s) are selected. The (I) data uses the test patterns

selected, and the (Q) data does not output the test patterns.

ADC TEST MODES

The AD9699 has various test options that aid in the system level

implementation. The AD9699 has ADC test modes that are availa-

ble in Register 0x550. These test modes are described in Table 37.

When an output test mode is enabled, the analog section of the

ADC is disconnected from the digital back-end blocks, and the test

pattern is run through the output formatting block. Some of the test

patterns are subject to output formatting, and some are not. The PN

generators from the PN sequence tests can be reset by setting Bit

4 or Bit 5 of Register 0x0550. These tests can be performed with

or without an analog signal (if present, the analog signal is ignored).

However, these tests do require an encode clock.

Bit 0 of Register 0x0387 selects the Channel A test patterns to be

used for the (I) data.

For more information, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI.

Table 37. ADC Test Modes

Output Test Mode

Default/

Bit Sequence

Pattern Name

Expression

Seed Value

Sample (N, N + 1, N + 2, …)

0000

0001

0010

0011

0100

0101

0110

0111

1000

Off (default)

Not applicable

0x3AFF

Not applicable

Midscale short

0000 0000 0000

01 1111 1111 1111

10 0000 0000 0000

10 1010 1010 1010

x²³+ x¹⁸+ 1

Not applicable

Positive full-scale short

Negative full-scale short

Checkerboard

Not applicable

0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555

0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6

0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697

0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000

PN sequence long

PN sequence short

One-/zero-word toggle

User input

x⁹+ x⁵+ 1

0x0092

11 1111 1111 1111

Not applicable

Register 0x0551 to

Register 0x0558

User Pattern 1[15:2], User Pattern 2[15:2], User Pattern

3[15:2], User Pattern 4[15:2], User Pattern 1[15:2] … for

repeat mode

User Pattern 1[15:2], User Pattern 2[15:2], User Pattern

3[15:2], User Pattern 4[15:2],

0x0000 … for single mode

(x) % 2¹⁴, (x +1) % 2¹⁴, (x +2) % 2¹⁴, (x +3) % 2¹⁴

1111

Ramp output

(x) % 2¹⁴

Not applicable

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Data Sheet

AD9699

TEST MODES

These tests are shown in Register 0x0571, Bit 5. The test pattern is

equivalent to the raw samples from the ADC.

JESD204B BLOCK TEST MODES

In addition to the ADC pipeline test modes, the AD9699 also has

flexible test modes in the JESD204B block. These test modes are

listed in Register 0x0573 and Register 0x0574. These test patterns

can be injected at various points along the output datapath. These

test injection points are shown in Figure 103. Table 38 describes

the various test modes available in the JESD204B block. For the

AD9699, a transition from test modes (Register 0x0573 ≠ 0x00) to

normal mode (Register 0x0573 = 0x00) requires an SPI soft reset.

This is done by writing 0x81 to Register 0x0000 (self cleared).

Interface Test Modes

The interface test modes are described in Register 0x0573,

Bits[3:0]. These test modes are also explained in Table 38. The

interface tests can be injected at various points along the data.

See Figure 103 for more information on the test injection points.

Register 0x0573, Bits[5:4] show where these tests are injected.

Table 39, Table 40, and Table 41 show examples of some of the

test modes when injected at the JESD204B sample input, PHY

10-bit input, and scrambler 8-bit input. UPx in the tables represent

the user pattern control bits from the user register map.

Transport Layer Sample Test Mode

The transport layer samples are implemented in the AD9699 as

defined by Section 5.1.6.3 in the JEDEC JESD204B specification.

Table 38. JESD204B Interface Test Modes

Output Test Mode

Bit Sequence

Pattern Name

Expression

Default

0000

0001

0010

0011

0100

0101

0110

0111

1000

1110

1111

Off (default)

Not applicable

Alternating checker board

1/0 word toggle

0x5555, 0xAAAA, 0x5555, …

0x0000, 0xFFFF, 0x0000, …

x³¹+ x²⁸+ 1

x²³+ x¹⁸+ 1

x¹⁵+ x¹⁴+ 1

x⁹+ x⁵+ 1

x⁷+ x⁶+ 1

(x) % 2¹⁶

Not applicable

31-bit PN sequence

23-bit PN sequence

15-bit PN sequence

9-bit PN sequence

7-bit PN sequence

Ramp output

0x0003AFFF

0x003AFF

0x03AF

0x092

0x07

Ramp size depends on test injection point

User Pattern 1 to User Pattern 4, then repeat

User Pattern 1 to User Pattern 4, then zeros

Continuous/repeat user test

Single user test

Register 0x0551 to Register 0x0558

Table 39. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00)

Frame

Number

Converter

Number

Sample

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

PN9

PN23

User Repeat

User Single

0

1

2

3

4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0x5555

0xAAAA

0x5555

0xAAAA

0x5555

0x0000

0xFFFF

0x0000

0xFFFF

0x0000

(x) % 2¹⁶

0x496F

0xC9A9

0x980C

0x651A

0x5FD1

0xFF5C

0x0029

0xB80A

0x3D72

0x9B26

UP1[15:0]

UP2[15:0]

UP3[15:0]

UP4[15:0]

UP1[15:0]

UP2[15:0]

UP3[15:0]

UP4[15:0]

0x0000

(x +1) % 2¹⁶

(x +2) % 2¹⁶

(x +3) % 2¹⁶

(x +4) % 2¹⁶

0x0000

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Data Sheet

AD9699

TEST MODES

Table 39. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00)

Frame

Number

Converter

Number

Sample

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

PN9

PN23

User Repeat

User Single

4

1

0

1

0x5555

0x0000

(x +4) % 2¹⁶

0x5FD1

0x9B26

UP1[15:0]

0x0000

Table 40. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01)

10-Bit Symbol

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

PN9

PN23

User Repeat

User Single

0

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x155

0x2AA

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

0x000

0x3FF

(x) % 2¹⁰

0x125

0x2FC

0x26A

0x198

0x031

0x251

0x297

0x3D1

0x18E

0x2CB

0x0F1

0x3DD

0x3FD

0x1C0

0x00A

0x1B8

0x028

0x3D7

0x0A6

0x326

0x10F

0x3FD

0x31E

0x008

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

UP1[15:6]

UP2[15:6]

UP3[15:6]

UP4[15:6]

0x000

1

(x + 1) % 2¹⁰

(x + 2) % 2¹⁰

(x + 3) % 2¹⁰

(x + 4) % 2¹⁰

(x + 5) % 2¹⁰

(x + 6) % 2¹⁰

(x + 7) % 2¹⁰

(x + 8) % 2¹⁰

(x + 9) % 2¹⁰

(x + 10) % 2¹⁰

(x + 11) % 2¹⁰

2

3

4

5

0x000

6

0x000

7

0x000

8

0x000

9

0x000

10

11

0x000

Table 41. Scrambler 8-bit Input (Register 0x0573, Bits[5:4] = 'b10)

8-Bit Octet

Number

Alternating

Checkerboard

1/0 Word

Toggle

Ramp

PN9

PN23

User Repeat

User Single

0

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x55

0xAA

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

0x00

0xFF

(x) % 2⁸

0x49

0x6F

0xC9

0xA9

0x98

0x0C

0x65

0x1A

0x5F

0xD1

0x63

0xAC

0xFF

0x5C

0x00

0x29

0xB8

0x0A

0x3D

0x72

0x9B

0x26

0x43

0xFF

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

UP1[15:9]

UP2[15:9]

UP3[15:9]

UP4[15:9]

0x00

1

(x + 1) % 2⁸

(x + 2) % 2⁸

(x + 3) % 2⁸

(x + 4) % 2⁸

(x + 5) % 2⁸

(x + 6) % 2⁸

(x + 7) % 2⁸

(x + 8) % 2⁸

(x + 9) % 2⁸

(x + 10) % 2⁸

(x + 11) % 2⁸

2

3

4

5

0x00

6

0x00

7

0x00

8

0x00

9

0x00

10

11

0x00

patterns inserted at this point are useful for verifying the functionali-

ty of the data link layer. When the data link layer test modes are

enabled, disable SYNCINB± by writing 0xC0 to Register 0x0572.

Data Link Layer Test Modes

The data link layer test modes are implemented in the AD9699

as defined by Section 5.3.3.8.2 in the JEDEC JESD204B Specifi-

cation. These tests are shown in Register 0x0574, Bits[2:0]. Test

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Data Sheet

AD9699

SERIAL PORT INTERFACE

The AD9699 SPI allows the user to configure the converter for

specific functions or operations through a structured register space

provided inside the ADC. The SPI gives the user added flexibility

and customization, depending on the application. Addresses are

accessed via the serial port and can be written to or read from via

the port. Memory is organized into bytes that can be further divided

into fields. These fields are documented in the Serial Port Interface

section. For detailed operational information, see the Serial Control

Interface Standard (Rev. 1.0).

from an input to an output at the appropriate point in the serial

frame.

Data can be sent in MSB first mode or in LSB first mode. MSB first

is the default on power-up and can be changed via the SPI port

configuration register. For more information about this and other

features, see the Serial Control Interface Standard (Rev. 1.0).

HARDWARE INTERFACE

The pins described in Table 42 comprise the physical interface

between the user programming device and the serial port of the

AD9699. The SCLK pin and the CSB pin function as inputs when

using the SPI. The SDIO pin is bidirectional, functioning as an input

during write phases and as an output during readback.

CONFIGURATION USING THE SPI

Three pins define the SPI of the AD9699 ADC: the SCLK pin, the

SDIO pin, and the CSB pin (see Table 42). The SCLK (serial clock)

pin synchronizes the read and write data presented to and from the

ADC. The SDIO (serial data input/output) pin is a dual-purpose pin

that allows data to be sent and read from the internal ADC memory

map registers. The CSB (chip select bar) pin is an active low control

that enables or disables the read and write cycles.

The SPI is flexible enough to be controlled by either FPGAs or

microcontrollers. One method for SPI configuration is described in

detail in the AN-812 Application Note, Microcontroller-Based Serial

Port Interface (SPI) Boot Circuit.

Table 42. SPI Pins

Do not activate the SPI port during periods when the full dynamic

performance of the converter is required. Because the SCLK signal,

the CSB signal, and the SDIO signal are typically asynchronous

to the ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9699 to prevent these signals from transitioning at the converter

inputs during critical sampling periods.

Function

SCLK

Serial clock. The serial shift clock input that is used to synchronize

serial interface, reads, and writes.

SDIO

CSB

Serial data input/output. A dual-purpose pin that typically serves as an

input or an output, depending on the instruction being sent and the

relative position in the timing frame.

Chip select bar. An active low control that gates the read and write

cycles.

SPI ACCESSIBLE FEATURES

The falling edge of CSB, in conjunction with the rising edge of

SCLK, determines the start of the framing. An example of the serial

timing and its definitions can be found in Figure 4 and Table 5.

Table 43 provides a brief description of the general features that are

accessible via the SPI. These features are described in detail in the

Serial Control Interface Standard (Rev. 1.0). The AD9699 device

specific features are described in the Serial Port Interface section.

Other modes involving the CSB pin are available. The CSB pin can

be held low indefinitely, which permanently enables the device. This

is called streaming. The CSB can stall high between bytes to allow

additional external timing. When CSB is tied high, SPI functions are

placed in a high impedance mode. This mode turns on any SPI pin

secondary functions.

Table 43. Features Accessible Using the SPI

Feature

Description

Mode

Allows the user to set either power-down mode or

standby mode.

Clock

Allows the user to access the clock divider via the

SPI.

All data is composed of 8-bit words. The first bit of each individual

byte of serial data indicates whether a read or write command is

issued, which allows the SDIO pin to change direction from an input

to an output.

DDC

Allows the user to set up decimation filters for different

applications.

Test Input/Output

Output Mode

Allows the user to set test modes to have known data

on output bits.

In addition to word length, the instruction phase determines whether

the serial frame is a read or write operation, allowing the serial

port to be used both to program the chip and to read the contents

of the on-chip memory. If the instruction is a readback operation,

performing a readback causes the SDIO pin to change direction

Allows the user to set up outputs.

Serializer/Deserializer

(SERDES) Output Setup

Allows the user to vary SERDES settings, such as

swing and emphasis.

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Data Sheet

AD9699

MEMORY MAP

address location with 0s unless the default value is set otherwise.

Writing to these locations is required only when part of an address

location is unassigned (for example, Address 0x0561). If the entire

address location is open (for example, Address 0x0013), do not

write to this address location.

READING THE MEMORY MAP REGISTER

TABLE

Each row in Table 44 has eight bit locations. The memory map is

divided into the following sections:

► Analog Devices SPI registers (Register 0x0000 to Regis-

ter 0x000F)

Default Values

► Clock/SYSREF/chip power-down pin control registers (Regis-

ter 0x003F to Register 0x0201)

► Fast detect and signal monitor control registers (Register 0x0245

to Register 0x027A)

After the AD9699 is reset, critical registers are loaded with default

values. The default values for the registers are given in Table 44.

Logic Levels

► DDC function registers (Register 0x0300 to Register 0x03CD)

► Digital outputs and test modes registers (Register 0x0550 to

Register 0x05CB)

► Programmable filter control and coefficients registers (Regis-

ter 0x0DF8 to Register 0x0F7F)

► VREF/analog input control registers (Register 0x18A6 to Regis-

ter 0x1A4D)

An explanation of logic level terminology follows:

► “Bit is set” is synonymous with “bit is set to Logic 1” or “writing

Logic 1 for the bit.”

► “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing

Logic 0 for the bit.”

► X denotes a don’t care bit.

Table 44 (see the Memory Map Register Details section) docu-

ments the default hexadecimal value for each hexadecimal address

shown. The column with the heading Bit 7 (MSB) is the start of the

default hexadecimal value given. For example, Address 0x0561,

the output sample mode register, has a hexadecimal default value

of 0x01, which means that Bit 0 = 1, and the remaining bits are

0s. This setting is the default output format value, which is twos

complement. For more information on this function and others, see

Table 44.

SPI Soft Reset

After issuing a soft reset by programming 0x81 to Register 0x0000,

the AD9699 requires 5 ms to recover. When programming the

AD9699 for application setup, ensure that an adequate delay is

programmed into the firmware after asserting the soft reset and

before starting the device setup.

MEMORY MAP REGISTER DETAILS

All address locations that are not included in Table 44 are not

currently supported for this device and must not be written

Open and Reserved Locations

All address and bit locations that are not included in Table 44 are

not currently supported for this device. Write unused bits of a valid

Table 44. Memory Map Register Details

Addr.

Analog Devices SPI Registers

0x0000 SPI Configuration A

Name

Bits Bit Name

Settings

Description

Reset Access

7

Soft reset mirror

Whenever a soft reset is issued, the user must wait 5 ms before

writing to any other register. This provides sufficient time for the boot

loader to complete.

0x0

R/WC

(self clearing)

0

1

Do nothing.

Reset the SPI and registers (self clearing).

6

5

LSB first mirror

0x0

R/W

1

0

LSB shifted first for all SPI operations.

MSB shifted first for all SPI operations.

Address ascension mirror

0

1

Multibyte SPI operations cause addresses to autodecrement.

Multibyte SPI operations cause addresses to autoincrement.

Reserved.

[4:3] Reserved

0x0

R

2

Address ascension

R/W

0

1

Multibyte SPI operations cause addresses to auto-decrement.

Multibyte SPI operations cause addresses to auto-increment.

1

LSB first

0x0

R/W

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

1

0

LSB shifted first for all SPI operations.

MSB shifted first for all SPI operations.

0

Soft reset (self clearing)

Whenever a soft reset is issued, the user must wait 5 ms before

writing to any other register. This provides sufficient time for the boot

loader to complete.

0x0

R/WC

0

1

Do nothing.

Reset the SPI and registers (self clearing).

Reserved.

0x0001

0x0002

SPI Configuration B

[7:2] Reserved

0x0

R

1

Datapath soft reset

R/WC

(self clearing)

0

1

Normal operation.

Datapath soft reset (self clearing).

Reserved.

0

Reserved

0x0

R

Chip configuration

(local)

[7:2] Reserved

Reserved.

[1:0] Channel power mode

Channel power modes.

0x0

R/W

00

10

Normal mode (power-up).

Standby mode, digital datapath clocks disabled, JESD204B interface

enabled.

11

Power-down mode, digital datapath clocks disabled, digital datapath

held in reset, JESD204B interface disabled.

0x0003

0x0004

Chip type

[7:0] Chip type

Chip type.

0x03

0xE2

R

0x3

High speed ADC.

Chip ID.

Chip ID LSB

[7:0] Chip ID LSB [7:0]

0xDF

0x0

AD9699.

0x0005

0x0006

Chip ID MSB

Chip grade

[7:0] Chip ID MSB [15:8]

[7:4] Chip speed grade

[3:0] Reserved

Chip ID.

0x0

0x1

R

Chip speed grade.

Reserved.

R

0x0008

Device index

[7:2] Reserved

Reserved.

R

0

ADC Core

R/W

0

1

ADC Core does not receive the next SPI command.

ADC Core receives the next SPI command.

0x000A

0x000B

Scratch pad

SPI revision

[7:0] Scratch pad

[7:0] SPI revision

Chip scratch pad register. This register provides a consistent memory 0x0

location for software debugging.

R/W

R

SPI revision register. 0x01: Revision 1.0.

0x1

00000001 Revision 1.0.

Vendor ID [7:0].

Vendor ID [15:8].

Reserved.

0x000C

0x000D

0x000F

Vendor ID LSB

Vendor ID MSB

Transfer

[7:0] Vendor ID LSB

[7:0] Vendor ID MSB

[7:1] Reserved

0x56

0x04

0x0

R

0

Chip transfer

Self clearing chip transfer bit. This bit is used to update the

0x0

R/W

DDC phase increment and phase offset registers when DDC phase

update mode (Register 0x0300, Bit 7 ) = 1. This makes it possible

to synchronously update the DDC mixer frequencies. This bit is also

used to update the coefficients for the programmable filter (PFILT).

0

1

Do nothing. Bit is only cleared after transfer is complete.

Self clearing bit used to synchronize the transfer of data from master

to slave registers.

Clock/SYSREF/Chip PDWN Pin Control Registers

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Local chip PDWN pin

disable

Settings

Description

Reset Access

0x003F

Chip PDWN pin

(local)

7

Function is determined by Register 0x0040, Bits[7:6].

0x0

R/W

0

1

Power-down pin (PDWN/STBY) enabled (default).

Power-down pin (PDWN/STBY) disabled/ignored.

Reserved.

[6:0] Reserved

0x0

R

0x0040

Chip Pin Control 1

[7:6] Global chip PDWN pin

functionality

External power-down pin functionality. Assertion of the external

power-down pin (PDWN/STBY) has higher priority than the channel

power mode control bits (Register 0x0002, Bits[1:0]). The PDWN/

STBY pin is only used when Register 0x0040, Bits[7:6] = 00 or 01.

R/W

00

01

10

Power-down pin (default). Assertion of external power-down pin

(PDWN/STBY) causes the chip to enter full power-down mode.

Standby pin. Assertion of external power-down pin (PDWN/STBY)

causes the chip to enter standby mode.

Pin disabled. Power-down pin (PDWN/STBY) is ignored.

GPIO B0 pin functionality.

[5:3] GPIO_B0 pin functionality

0x7

R/W

001

110

111

JESD204B LMFC output.

Pin functionality determined by 0x0041[7:4]

Disabled. Configured as input with weak pull-down (default).

Fast Detect /GPIO A0 pin functionality.

[2:0] Chip FD/GPIO_A0 pin

functionality

000

001

110

111

Fast Detect output.

JESD204B LMFC output.

Pin functionality determined by Register 0x0041, Bits[3:0]

Disabled. Configured as an input with weak pull-down (default).

0x0041

0x0042

0x0108

Chip Pin Control 2

[7:4] GPIO_B0 pin secondary

functionality

GPIO B0 pin secondary functionality (only used when Register

0x0040, Bits[5:3] = 110).

0x0

0xF

0x0

R/W

R

0000

0001

1000

1001

Chip GPIO B0 input (NCO channel selection).

Chip transfer input.

Master next trigger output (MNTO).

Slave next trigger input (SNTI).

[3:0] Chip FD/GPIO_A0 pin

secondary functionality

Fast Detect /GPIO B0 pin secondary functionality (only used when

Register 0x0040, Bits[2:0] = 110).

0000

0001

1000

1001

Chip GPIO A0 input (NCO channel selection).

Chip transfer input.

Master next trigger output (MNTO).

Slave next trigger input (SNTI).

GPIO B1 pin functionality.

Chip Pin Control 3

[7:4] Chip GPIO_B1 pin

functionality

0000

1000

1001

1111

Chip GPIO B1 input (NCO channel selection).

Master next trigger output (MNTO).

Slave next trigger input (SNTI).

Disabled (configured as input with weak pull-down).

GPIO A1 pin functionality.

[3:0] Chip GPIO_B1 pin

functionality

0000

1000

1001

1111

Chip GPIO A1 input (NCO channel selection).

Master next trigger output (MNTO).

Slave next trigger input (SNTI).

Disabled (configured as input with weak pull-down).

Reserved.

Clock divider control [7:3] Reserved

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

[2:0] Input clock divider

(CLK± pins)

0x0

R/W

00

01

11

Divide by 1.

Divide by 2.

Divide by 4.

Reserved.

0x0109

Clock divider phase

(local)

[7:4] Reserved

0x0

R

[3:0] Clock divider phase offset

R/W

0000

0001

0010

…

0 input clock cycles delayed.

½ input clock cycles delayed (invert clock).

1 input clock cycles delayed.

…

1110

1111

7 input clock cycles delayed.

7½ input clock cycles delayed.

0x010A

Clock divider and

SYSREF control

7

Clock divider auto phase

adjust enable

Clock divider autophase adjust enable. When enabled,

Register 0x0129, Bits[3:0] contain the phase of the divider

when SYSREF occurred. The actual divider phase offset =

Register 0x0129, Bits[3:0] + Register 0x0109, Bits[3:0].

0x0

R/W

0

1

Clock divider phase is not changed by SYSREF (disabled).

Clock divider phase is automatically adjusted by SYSREF (enabled).

Reserved.

[6:4] Reserved

0x0

R

[3:2] Clock divider negative skew

window

Clock divider negative skew window (measured in ½ input device

clocks). Number of ½ clock cycles before the input device clock by

which captured SYSREF transitions are ignored. Only used when

Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register

0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. This allows some

uncertainty in the sampling of SYSREF without disturbing the input

clock divider. Also, SYSREF must be disabled (Register 0x0120,

Bits[2:1] = 0x0) when changing this control field.

R/W

0

No negative skew, SYSREF must be captured accurately.

½ device clock of negative skew.

1

10

11

1 device clocks of negative skew.

1½ device clocks of negative skew.

[1:0] Clock divider positive skew

window

Clock divider positive skew window (measured in ½ input device

clocks). Number of clock cycles after the input device clock by which

captured SYSREF transitions are ignored. Only used when Register

0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A,

Bits[1:0] < Register 0x0108, Bits[2:0]. This allows some uncertainty

in the sampling of SYSREF without disturbing the input clock divider.

Also, SYSREF must be disabled (Register 0x0120, Bits[2:1] = 0x0)

when changing this control field.

0x0

R/W

0

No positive skew, SYSREF must be captured accurately.

½ device clock of positive skew.

1 device clocks of positive skew.

1½ device clocks of positive skew.

Reserved.

1

10

11

0x010B

Clock divider

[7:4] Reserved

0x0

R

SYSREF status

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Rev. 0 | 85 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

[3:0] Clock divider SYSREF

offset

Clock divider phase status (measured in ½ clock cycles). Internal

clock divider phase of the captured SYSREF signal applied to the

phase offset. Only used when 0x010A[7] = 1. When Register 0x010A,

Bit 7 = 1, Register 0x010A, Bits[3:2] = 0, and Register 0x010A,

Bits[1:0] = 0, the clock divider SYSREF offset = Register 0x0129,

Bits[3:0].

0x0

R

0x0110

Clock delay control

[7:3] Reserved

Reserved.

0x0

R

[2:0] Clock delay mode select

Clock delay mode select. Used in conjunction with Register 0x0111

and Register 0x0112.

R/W

000

010

011

100

110

No clock delay.

Fine delay: only 0 to 16 delay steps are valid.

Fine delay (lowest jitter): only 0 to 16 delay steps are valid.

Fine delay: all 192 delay steps are valid.

Fine delay enabled (all 192 delay steps are valid), superfine delay

enabled (all 128 delay steps are valid).

0x0111

Clock superfine

delay (local)

[7:0] Clock superfine delay adjust

Clock superfine delay adjust. This is an unsigned control to adjust the 0x0

superfine sample clock delay in 0.25 ps steps. These bits are only

used when Register 0x0110, Bits[2:0] = 010 or 110.

R/W

0x00

…

0 delay steps.

…

0x08

…

8 delay steps.

…

0x80

128 delay steps.

0x0112

Clock fine delay

(local)

[7:0] Set clock fine delay

Clock fine delay adjust. This is an unsigned control to adjust the fine

sample clock skew in 1.725 ps steps. These bits are only used when

Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6. Minimum = 0.

Maximum = 192. Increment = 1. Unit = delay steps.

0xC0 R/W

0x00

…

0 delay steps.

…

0x08

…

8 delay steps.

…

0xC0

192 delay steps.

Reserved.

0x011B

0x011C

Clock status

[7:1] Reserved

0x0

R

0

Input clock detect

Clock detection status.

Input clock not detected.

Input clock detected/locked.

Reserved

0

1

Clock Duty Cycle

Stabilizer 1 control

(local)

[7:2] Reserved

0x0

0x1

R/W

1

0

DCS1 enable

Clock DCS1 enable.

DCS1 bypassed.

DCS1 enabled.

0

1

DCS1 power up

Clock DCS1 power-up.

DCS1 powered down.

DCS1 powered up.

Reserved.

0x1

R/W

0

1

0x011E

Clock Duty Cycle

Stabilizer 2 control

[7:2] Reserved

0x0

0x1

R/W

1

DCS2 enable

Clock DCS2 enable.

DCS2 bypassed.

DCS2 enabled.

0

1

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Rev. 0 | 86 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0

DCS2 power up

Clock DCS2 power-up.

DCS2 powered down.

DCS2 powered up.

Reserved.

0x1

R/W

0

1

0x0120

SYSREF Control 1

7

6

Reserved

0x0

R

SYSREF± flag reset

R/W

0

1

Normal flag operation.

SYSREF flags held in reset (setup and hold error flags cleared).

Reserved.

5

4

Reserved

0x0

R

SYSREF± transition select

R/W

0

1

SYSREF is valid on low to high transitions using the selected CLK±

edge. When changing this setting, SYSREF± mode select must be

set to disabled.

SYSREF is valid on high to low transitions using the selected CLK±

edge. When changing this setting, SYSREF± mode select must be

set to disabled.

3

CLK± edge select

0x0

R/W

0

1

Captured on the rising edge of CLK± input.

Captured on the falling edge of CLK± input.

[2:1] SYSREF± mode select

0

Disabled.

Continuous.

N-shot.

1

10

0

Reserved

Reserved.

0x0

R

0x0121

SYSREF Control 2

[7:4] Reserved

R

[3:0] SYSREF N-shot ignore

counter select

R/W

0000

0001

0010

0011

…

Next SYSREF only (do not ignore).

Ignore the first SYSREF± transition.

Ignore the first two SYSREF± transitions.

Ignore the first three SYSREF± transitions.

…

1110

1111

Ignore the first 14 SYSREF± transitions.

Ignore the first 15 SYSREF± transitions.

Reserved.

0x0122

SYSREF Control 3

[7:4] Reserved

0x0

R

[3:2] SYSREF window negative

Negative skew window (measured in sample clocks). Number of

clock cycles before the sample clock by which captured SYSREF

transitions are ignored.

R/W

00

01

10

11

No negative skew, SYSREF must be captured accurately.

One sample clock of negative skew.

Two sample clocks of negative skew.

Three sample clocks of negative skew.

[1:0] SYSREF window positive

Positive skew window (measured in sample clocks). Number of

clock cycles before the sample clock by which captured SYSREF

transitions are ignored.

0x0

R/W

00

01

10

11

No positive skew, SYSREF must be captured accurately.

One sample clock of positive skew.

Two sample clocks of positive skew.

Three sample clocks of positive skew.

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Rev. 0 | 87 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Reserved

Settings

Description

Reset Access

0x0123

SYSREF Control 4

7

Reserved.

0x0

R

[6:0] SYSREF± timestamp delay,

Bits[6:0]

SYSREF timestamp delay (in converter sample clock cycles).

0x00

R/W

0

0 sample clock cycle delay.

1 sample clock cycle delay.

…

1

…

111 1111

127 sample clock cycle delay.

SYSREF hold status.

SYSREF setup status.

Reserved.

0x0128

0x0129

SYSREF Status 1

SYSREF Status 2

[7:4] SYSREF± hold status

[3:0] SYSREF± setup status

[7:4] Reserved

0x0

R

[3:0] Clock divider phase when

SYSREF± was captured

SYSREF divider phase. Represents the phase of the divider when

SYSREF was captured.

0000

0001

0010

0011

0100

…

In phase.

SYSREF± is ½ cycle delayed from clock.

SYSREF± is 1 cycle delayed from clock.

SYSREF± is 1½ input clock cycles delayed.

SYSREF± is 2 input clock cycles delayed.

…

1111

SYSREF± is 7½ input clock cycles delayed.

0x012A

0x01FF

SYSREF Status 3

Chip sync mode

[7:0] SYSREF counter, Bits[7:0]

increments when a

SYSREF count. Running counter that increments whenever a

SYSREF event is captured. Reset by Register 0x120, Bit 6. Wraps

around at 255. Read these bits only when Register 0x120, Bits[2:1]

are set to disabled.

0x0

R

SYSREF± is captured

[7:1] Reserved

Reserved.

0x0

R

0

Synchronization mode

R/W

0

1

JESD204B synchronization mode. The SYSREF signal resets all

internal clock dividers. Use this mode when synchronizing multiple

chips as specified in the JESD204B standard. If the phase of any of

the dividers must change, the JESD204B link goes down.

Timestamp mode. The SYSREF signal does not reset internal clock

dividers. In this mode, the JESD204B link and the signal monitor are

not affected by the SYSREF signal. The SYSREF signal timestamps

a sample as it passes through the ADC and is used as a control bit in

the JESD204B output word.

Chip Operating Mode Control Registers

0x0200

Chip mode

[7:6] Reserved

Reserved.

0x0

R/W

5

Chip Q ignore

Chip real (I) only selection.

Both real (I) and complex (Q) selected.

Only real (I) selected, complex (Q) is ignored.

Reserved.

0

1

4

Reserved

0x0

R

[3:0] Chip application mode

R/W

0000

0001

0010

0011

Full bandwidth mode (default).

One DDC mode (DDC0 only)

Two DDC mode (DDC0 and DDC1 only)

Four DDC mode (DDC0, DDC1, DDC2, and DDC3)

Reserved.

0x0201

Chip decimation

ratio

[7:4] Reserved

0x0

R

[3:0] Chip decimation ratio

Chip decimation ratio.

R/W

0000

Full sample rate (decimate by 1, DDCs are bypassed).

analog.com

Rev. 0 | 88 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0001

1000

0010

0101

1001

0011

0110

1010

0111

0100

1101

1011

1110

1111

1100

Decimate by 2.

Decimate by 3.

Decimate by 4.

Decimate by 5.

Decimate by 6.

Decimate by 8.

Decimate by 10.

Decimate by 12.

Decimate by 15.

Decimate by 16.

Decimate by 20.

Decimate by 24.

Decimate by 30.

Decimate by 40.

Decimate by 48.

Fast Detect and Signal Monitor Control Registers

0x0245

Fast detect control

(local)

[7:4] Reserved

Reserved.

0x0

R

3

Force FD pin

R/W

0

1

Normal operation of the fast detect pin.

Force a value on the fast detect pin (see Bit 2).

2

Force value of FD pin

The fast detect output pin is set to this value when the output is

forced.

0x0

R/W

1

0

Reserved

Reserved.

0x0

R

Enable fast detect output

R/W

0

1

Fast detect disabled.

Fast detect enabled.

0x0247

0x0248

Fast detect up LSB

(local)

[7:0] Fast detect upper threshold

LSBs of the fast detect upper threshold. This register contains the

8 LSBs of the programmable 13-bit upper threshold that is compared

to the fine ADC magnitude.

0x0

R/W

Fast detect up MSB

(local)

[7:5] Reserved

Reserved.

0x0

R

[4:0] Fast detect upper threshold

MSBs of the fast detect upper threshold. This register contains the

8 LSBS of the programmable 13-bit upper threshold that is compared

to the fine ADC magnitude.

R/W

0x0249

0x024A

Fast detect low LSB [7:0] Fast detect lower threshold

(local)

LSBs of the fast detect lower threshold. This register contains the

8 LSBS of the programmable 13-bit lower threshold that is compared

to the fine ADC magnitude.

0x0

R/W

Fast detect low MSB [7:5] Reserved

(local)

Reserved.

0x0

R

[4:0] Fast detect lower threshold

MSBs of the fast detect lower threshold. This register contains the

8 LSBs of the programmable 13-bit lower threshold that is compared

to the fine ADC magnitude

R/W

0x024B

0x024C

Fast detect dwell

LSB (local)

[7:0] Fast detect dwell time

LSBs of the fast detect dwell time counter target. This is a load value 0x0

for a 16-bit counter that determines how long the ADC data must

remain below the lower threshold before the FD pins are reset to 0.

R/W

Fast detect dwell

MSB (local)

MSBs of the fast detect dwell time counter target. This is a load value 0x0

for a 16-bit counter that determines how long the ADC data must

remain below the lower threshold before the FD pins are reset to 0.

analog.com

Rev. 0 | 89 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x026F

Signal monitor sync

control

[7:2] Reserved

Reserved.

0x0

R

1

Signal monitor next

Signal monitor next synchronization mode.

0x0

R/W

synchronization mode

0

1

Continuous mode.

Next synchronization mode. Only the next valid edge of the

SYSREF± pin is used to synchronize the signal monitor block.

Subsequent edges of the SYSREF± pin are ignored. When the next

SYSREF is found, Register 0x026F, Bit 0 clears. The SYSREF±

pin must be an integer multiple of the signal monitor period for this

function to operate correctly in continuous mode.

0

Signal monitor

Signal monitor synchronization enable

0x0

R/W

synchronization mode

0

1

Synchronization disabled.

If Register 0x026F, Bit 1 = 1, only the next valid edge of the

SYSREF± pin is used to synchronize the signal monitor block.

Subsequent edges of the SYSREF± pin are ignored. When the next

SYSREF signal is received, this bit is cleared. The SYSREF± input

pin must be enabled to synchronize the signal monitor blocks.

0x0270

Signal monitor

control (local)

[7:2] Reserved

Reserved.

0x0

R

1

Peak detector

R/W

0

1

Peak detector disabled.

Peak detector enabled.

Reserved.

0

Reserved

0x0

R

0x0271

0x0272

0x0273

0x0274

Signal Monitor

Period 0 (local)

[7:0] Signal monitor period [7:0]

Bits[7:0] of the 24-bit value that sets the number of output clock

cycles over which the signal monitor performs its operation. Only

even values are supported.

0x80

R/W

Signal Monitor

Period 1 (local)

[7:0] Signal monitor period [15:8]

Bits[15:8] of the 24-bit value that sets the number of output clock

cycles over which the signal monitor performs its operation. Only

even values are supported.

0x0

R/W

Signal Monitor

Period 2 (local)

[7:0] Signal monitor period

[23:16]

Bits[23:16] of the 24-bit value that sets the number of output clock

cycles over which the signal monitor performs its operation. Only

even values are supported.

Signal monitor status [7:5] Reserved

control (local)

Reserved.

0x0

R

4

Result update

R/WC

1

Update signal monitor status registers, Register 0x0275 to

Register 0x0278. Self clearing.

3

Reserved

Reserved.

0x0

0x1

R

[2:0] Result selection

R/W

001

Peak detector placed on status readback signals.

0x0275

0x0276

0x0277

Signal Monitor

Status 0 (local)

[7:0] Signal monitor result [7:0]

[7:0] Signal monitor result [15:8]

[7:4] Reserved

Signal monitor status result. This 20-bit value contains the status

result calculated by the signal monitor block.

0x0

R

Signal Monitor

Status 1 (local)

Signal monitor status result.

Signal Monitor

Status 2 (local)

Reserved.

[3:0] Signal monitor result [19:16]

Signal monitor status result.

0x0

R

0x0278

Signal monitor status [7:0] Frame count result, Bits[7:0]

frame counter (local)

Signal monitor frame counter status bits. Frame counter increments

whenever the period counter expires.

analog.com

Rev. 0 | 90 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x0279

Signal monitor serial [7:2] Reserved

framer control (local)

Reserved.

0x0

R

[1:0] Signal monitor SPORT over

JESD204B enable

0x0

R/W

00

11

Disabled.

Enabled.

Reserved.

0x027A

SPORT over

[7:6] Reserved

0x0

R

JESD204B input

selection (local)

1

SPORT over JESD204B

input selection

Signal monitor serial framer input selection. When each individual bit 0x1

is a 1, the corresponding signal statistics information is sent within

the frame.

R/W

0

1

Disabled.

Peak detector data inserted in the serial frame.

0

Reserved

Reserved.

0x0

R

DDC Function Registers (See the Digital Downconverter (DDC) Section)

0x0300

DDC SYNC control

7

DDC

Select DDC FTW/POW/MAW/MBW update mode.

R/W

FTW/POW/MAW/MBW

update mode

0

1

Instantaneous/continuous update. FTW/POW/MAW/MBW values are

updated immediately.

FTW/POW/MAW/MBW values are updated synchronously when the

chip transfer bit (Register 0x000F, Bit 0) is set.

[6:5] Reserved

Reserved.

0x0

R

4

DDC NCO soft reset

This bit can be used to synchronize all the NCOs inside the DDC

blocks.

R/W

0

1

Normal operation.

DDC held in reset.

Reserved.

[3:2] Reserved

0x0

R

1

DDC next synchronization

R/W

0

1

Continuous mode. The SYSREF frequency must be an integer

multiple of the NCO frequency for this function to operate correctly in

continuous mode.

Only the next valid edge of the SYSREF± pin is used to synchronize

the NCO in the DDC block. Subsequent edges of the SYSREF±

pin are ignored. When the next SYSREF signal is found, the DDC

synchronization enable bit (Register 0x0300, Bit 0) is cleared.

0

DDC synchronization mode

The SYSREF input pin must be enabled to synchronize the DDCs.

Synchronization disabled.

0x0

R/W

0

1

If DDC next synchronization (Register 0x0300, Bit 1 = 1), only the

next valid edge of the SYSREF± pin is used to synchronize the

NCO in the DDC block. Subsequent edges of the SYSREF± pin

are ignored. When the next SYSREF signal is received, this bit is

cleared.

0x0310

DDC0 control

7

6

Reserved

Reserved.

0x0

R/W

DDC0 gain select

Gain can be used to compensate for the 6 dB loss associated with

mixing an input signal down to baseband and filtering out its negative

component.

0

1

0 dB gain.

6 dB gain (multiply by 2).

analog.com

Rev. 0 | 91 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

[5:4] DDC0 intermediate

frequency (IF) mode

0x0

R/W

00

01

10

11

Variable IF mode.

0 Hz IF mode.

f_SHz IF mode.

Test mode.

3

DDC0 complex to real

enable

0x0

R/W

0

1

Complex (I and Q) outputs contain valid data.

Real (I) output only. complex to real enabled. Uses extra f_Smixing to

convert to real.

[2:0] DDC0 decimation rate

select

Decimation filter selection.

000

001

010

011

100

101

110

111

HB1 + HB2 filter selection: decimate by 2 (complex to real enabled),

or decimate by 4 (complex to real disabled).

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to

real enabled), or decimate by 16 (complex to real disabled).

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

HB1 + TB2 filter selection: decimate by 3 (complex to real enabled),

or decimate by 6 (complex to real disabled).

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to

real enabled), or decimate by 24 (complex to real disabled).

Decimation determined by Register 0x0311, Bits[7:4].

Only valid when Register 0x0310, Bits[2:0] = 3'b111.

0x0311

DDC0 input select

[7:4] DDC0 decimation rate

select

0x0

R/W

0

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled).

10

FB2 + HB1 filter selection: decimate by 10 (complex to real disabled),

or decimate by 5 (complex to real enabled).

11

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled).

100

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to

real disabled), or decimate by 20 (complex to real enabled).

111

TB1 filter selection: decimate by 3 (decimate by 1.5 not supported).

1000

FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not

supported).

1001

HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15 not

supported).

[3:0] Reserved

Reserved.

0x0

R

0x0314

DDC0 NCO control

[7:4] DDC0 NCO channel select

mode

For edge control, the internal counter wraps after the

Register 0x0314, Bits[3:0] value is reached.

R/W

0

Use Register 0x0314, Bits[3:0].

11

2'b00, GPIO_A1, GPIO_A0.

1000

1001

Increment internal counter on rising edge of the GPIO_A0 pin.

Increment internal counter on rising edge of the GPIO_A1 pin.

analog.com

Rev. 0 | 92 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

[3:0] DDC0 NCO register map

channel select

NCO channel select register map control.

0x0

R/W

0

Select NCO Channel 0.

Select NCO Channel 1.

Select NCO Channel 2.

Select NCO Channel 3.

Select NCO Channel 4.

Select NCO Channel 5.

Select NCO Channel 6.

Select NCO Channel 7.

Select NCO Channel 8.

Select NCO Channel 9.

Select NCO Channel 10.

Select NCO Channel 11.

Select NCO Channel 12.

Select NCO Channel 13.

Select NCO Channel 14.

Select NCO Channel 15.

Reserved.

1

10

11

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

0x0315

DDC0 phase control [7:4] Reserved

[3:0] DDC0 phase update index

0x0

R

Indexes the NCO channel whose phase and offset is updated. The

update method is based on the DDC phase update mode, which can

be continuous or require chip transfer.

R/W

0000

0001

0010

0011

Update NCO Channel 0.

Update NCO Channel 1.

Update NCO Channel 2.

Update NCO Channel 3.

0x0316

0x0317

0x0318

0x0319

0x031A

0x031B

0x031D

0x031E

0x031F

0x0320

0x0321

0x0322

DDC0 Phase

Increment 0

[7:0] DDC0 phase increment

[7:0]

FTW. Twos complement phase increment value for the NCO.

0x0

R/W

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

.

DDC0 Phase

Increment 1

[7:0] DDC0 phase increment

[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC0 Phase

Increment 2

[7:0] DDC0 phase increment

[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC0 Phase

Increment 3

[7:0] DDC0 phase increment

[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC0 Phase

Increment 4

[7:0] DDC0 phase increment

[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC0 Phase

Increment 5

[7:0] DDC0 phase increment

[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC0 Phase

Offset 0

[7:0] DDC0 phase offset [7:0]

[7:0] DDC0 phase offset [15:8]

[7:0] DDC0 phase offset [23:16]

[7:0] DDC0 phase offset [31:24]

[7:0] DDC0 phase offset [39:32]

[7:0] DDC0 phase offset [47:40]

Twos complement phase offset value for the NCO.

DDC0 Phase

Offset 1

DDC0 Phase

Offset 2

DDC0 Phase

Offset 3

DDC0 Phase

Offset 4

DDC0 Phase

Offset 5

analog.com

Rev. 0 | 93 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x0327

DDC0 test enable

[7:2] Reserved

Reserved.

0x0

R

1

0

Reserved

R

DDC0 I output test mode

enable

I samples always use the Test Mode A block. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

Reserved.

0x0330

DDC1 control

7

6

Reserved

0x0

R/W

DDC1 gain select

Gain can be used to compensates for the 6 dB loss associated with

mixing an input signal down to baseband and filtering out its negative

component.

0

1

0 dB gain.

6 dB gain (multiply by 2).

[5:4] DDC1 intermediate

frequency (IF) mode

0x0

R/W

00

01

10

11

Variable IF mode.

0 Hz IF mode.

f_SHz IF mode.

Test mode.

3

DDC1 complex to real

enable

0x0

R/W

0

1

Complex (I and Q) outputs contain valid data.

Real (I) output only. Complex to real enabled. Uses extra f_Smixing to

convert to real.

[2:0] DDC1 decimation rate

select

Decimation filter selection.

000

001

010

011

100

101

110

111

HB1 + HB2 filter selection: decimate by 2 (complex to real enabled),

or decimate by 4 (complex to real disabled).

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to

real enabled), or decimate by 16 (complex to real disabled).

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

HB1 + TB2 filter selection: decimate by 3 (complex to real enabled),

or decimate by 6 (complex to real disabled).

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to

real enabled), or decimate by 24 (complex to real disabled).

Decimation determined by Register 0x0331, Bits[7:4].

Only valid when Register 0x0310, Bits[2:0] = 3'b111.

0x0331

DDC1 input select

[7:4] DDC1 decimation rate

select

0x0

R/W

0

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled).

10

FB2 + HB1 filter selection: decimate by 10 (complex to real disabled),

or decimate by 5 (complex to real enabled).

11

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled).

100

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to

real disabled), or decimate by 20 (complex to real enabled).

analog.com

Rev. 0 | 94 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

111

TB1 filter selection: decimate by 3 (decimate by 1.5 not supported).

1000

FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not

supported).

1001

HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by 15 not

supported).

[3:0] Reserved

Reserved.

0x0

R

0x0334

DDC1 NCO control

[7:4] DDC1 NCO channel select

mode

For edge control, the internal counter wraps when the

Register 0x0334, Bits[3:0] value is reached.

R/W

0

Use Register 0x0314, Bits[3:0]

11

2'b00, GPIO_A1, GPIO_A0.

1000

1001

Increment internal counter when rising edge of the GPIO_A0 pin.

Increment internal counter when rising edge of the GPIO_A1 pin.

NCO channel select register map control.

[3:0] DDC1 NCO register map

channel select

0x0

R/W

0

Select NCO Channel 0.

Select NCO Channel 1.

Select NCO Channel 2.

Select NCO Channel 3.

Select NCO Channel 4.

Select NCO Channel 5.

Select NCO Channel 6.

Select NCO Channel 7.

Select NCO Channel 8.

Select NCO Channel 9.

Select NCO Channel 10.

Select NCO Channel 11.

Select NCO Channel 12.

Select NCO Channel 13.

Select NCO Channel 14.

Select NCO Channel 15.

Reserved.

1

10

11

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

0x0335

DDC1 phase control [7:4] Reserved

[3:0] DDC1 phase update index

0x0

R

Indexes the NCO channel for which the phase and offset is to be

updated. The update method is based on the DDC phase update

mode, which can be continuous or require chip transfer.

R/W

0000

0001

0010

0011

Update NCO Channel 0.

Update NCO Channel 1.

Update NCO Channel 2.

Update NCO Channel 3.

0x0336

0x0337

0x0338

0x0339

0x033A

DDC1 Phase

Increment 0

[7:0] DDC1 phase increment

[7:0]

FTW. Twos complement phase increment value for the NCO.

0x0

R/W

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

.

DDC1 Phase

Increment 1

[7:0] DDC1 phase increment

[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC1 Phase

Increment 2

[7:0] DDC1 phase increment

[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC1 Phase

Increment 3

[7:0] DDC1 phase increment

[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC1 Phase

Increment 4

[7:0] DDC1 phase increment

[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

analog.com

Rev. 0 | 95 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x033B

DDC1 Phase

Increment 5

[7:0] DDC1 phase increment

[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0

R/W

.

0x033D

0x033E

0x033F

0x0340

0x0341

0x0342

0x0347

DDC1 Phase

Offset 0

[7:0] DDC1 phase offset [7:0]

[7:0] DDC1 phase offset [15:8]

[7:0] DDC1 phase offset [23:16]

[7:0] DDC1 phase offset [31:24]

[7:0] DDC1 phase offset [39:32]

[7:0] DDC1 phase offset [47:40]

[7:2] Reserved

Twos complement phase offset value for the NCO.

DDC1 Phase

Offset 1

DDC1 Phase

Offset 2

DDC1 Phase

Offset 3

DDC1 Phase

Offset 4

DDC1 Phase

Offset 5

DDC1 test enable

Reserved.

0x0

R

1

0

Reserved

R

DDC1 I output test mode

enable

I samples always use the Test Mode A block. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

Reserved.

0x0350

DDC2 control

7

6

Reserved

0x0

R/W

DDC2 gain select

Gain can be used to compensates for the 6 dB loss associated with

mixing an input signal down to baseband and filtering out its negative

component.

0

1

0 dB gain.

6 dB gain (multiply by 2).

[5:4] DDC2 intermediate

frequency (IF) mode

0x0

R/W

00

01

10

11

Variable IF mode.

0 Hz IF mode.

f_SHz IF mode.

Test mode.

3

DDC2 complex to real

enable

0x0

R/W

0

1

Complex (I and Q) outputs contain valid data.

Real (I) output only. Complex to real enabled. Uses extra f_Smixing to

convert to real.

[2:0] DDC2 decimation rate

select

Decimation filter selection.

000

001

010

011

100

101

HB1 + HB2 filter selection: decimate by 2 (complex to real enabled),

or decimate by 4 (complex to real disabled).

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to

real enabled), or decimate by 16 (complex to real disabled).

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

HB1 + TB2 filter selection: decimate by 3 (complex to real enabled),

or decimate by 6 (complex to real disabled).

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

analog.com

Rev. 0 | 96 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

110

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to

real enabled), or decimate by 24 (complex to real disabled).

111

0

Decimation determined by Register 0x0351, Bits[7:4].

Only valid when Register 0x0310, Bits[2:0] = 3'b111.

0x0351

DDC2 input select

[7:4] DDC2 decimation rate

select

0x0

R/W

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled).

10

FB2 + HB1 filter selection: decimate by 10 (complex to real disabled),

or decimate by 5 (complex to real enabled).

11

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled).

100

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to

real disabled), or decimate by 20 (complex to real enabled).

[3:0] Reserved

Reserved.

0x0

R

0x0354

DDC2 NCO control

[7:4] DDC2 NCO channel select

mode

For edge control, the internal counter wraps when the

Register 0x0354, Bits[3:0] value is reached.

R/W

0

Use Register 0x0314, Bits[3:0].

11

2'b00, GPIO A1, GPIO A0.

1000

1001

Increment internal counter when rising edge of the GPIO_A0 pin.

Increment internal counter when rising edge of the GPIO_A1 pin.

NCO channel select register map control.

[3:0] DDC2 NCO register map

channel select

0x0

R/W

0

Select NCO Channel 0.

Select NCO Channel 1.

Select NCO Channel 2.

Select NCO Channel 3.

Select NCO Channel 4.

Select NCO Channel 5.

Select NCO Channel 6.

Select NCO Channel 7.

Select NCO Channel 8.

Select NCO Channel 9.

Select NCO Channel 10.

Select NCO Channel 11.

Select NCO Channel 12.

Select NCO Channel 13.

Select NCO Channel 14.

Select NCO Channel 15.

Reserved.

1

10

11

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

0x0355

DDC2 phase control [7:4] Reserved

[3:0] DDC2 phase update index

0x0

R

Indexes the NCO channel whose phase and offset gets updated. The 0x0

update method is based on the DDC phase update mode, which can

be continuous or require chip transfer.

R/W

0000

0001

0010

0011

Update NCO Channel 0.

Update NCO Channel 1.

Update NCO Channel 2.

Update NCO Channel 3.

0x0356

DDC2 Phase

Increment 0

[7:0] DDC2 phase increment

[7:0]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0

R/W

.

analog.com

Rev. 0 | 97 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x0357

DDC2 Phase

Increment 1

[7:0] DDC2 phase increment

[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0

R/W

.

0x0358

0x0359

0x035A

0x035B

0x035D

0x035E

0x035F

0x0360

0x0361

0x0362

0x0367

DDC2 Phase

Increment 2

[7:0] DDC2 phase increment

[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC2 Phase

Increment 3

[7:0] DDC2 phase increment

[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC2 Phase

Increment 4

[7:0] DDC2 phase increment

[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC2 Phase

Increment 5

[7:0] DDC2 phase increment

[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC2 Phase

Offset 0

[7:0] DDC2 phase offset [7:0]

[7:0] DDC2 phase offset [15:8]

[7:0] DDC2 phase offset [23:16]

[7:0] DDC2 phase offset [31:24]

[7:0] DDC2 phase offset [39:32]

[7:0] DDC2 phase offset [47:40]

[7:2] Reserved

Twos complement phase offset value for the NCO.

DDC2 Phase

Offset 1

DDC2 Phase

Offset 2

DDC2 Phase

Offset 3

DDC2 Phase

Offset 4

DDC2 Phase

Offset 5

DDC2 test enable

Reserved.

0x0

R

1

0

Reserved

R

DDC2 I output test mode

enable

I samples always use the Test Mode A block. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

Reserved

0x0370

DDC3 control

7

6

Reserved

0x0

R/W

DDC3 gain select

Gain can be used to compensate for the 6 dB loss associated with

mixing an input signal down to baseband and filtering out its negative

component.

0

1

0 dB gain.

6 dB gain (multiply by 2).

[5:4] DDC3 intermediate

frequency (IF) mode

0x0

R/W

00

01

10

11

Variable IF mode.

0 Hz IF mode.

f_SHz IF mode.

Test mode.

3

DDC3 complex to real

enable

0x0

R/W

0

1

Complex (I and Q) outputs contain valid data.

Real (I) output only. Complex to real enabled. Uses extra f_Smixing to

convert to real.

[2:0] DDC3 decimation rate

select

Decimation filter selection.

000

001

HB1 + HB2 filter selection: decimate by 2 (complex to real enabled),

or decimate by 4 (complex to real disabled).

HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to real

enabled), or decimate by 8 (complex to real disabled).

analog.com

Rev. 0 | 98 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

010

HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8 (complex to

real enabled), or decimate by 16 (complex to real disabled).

011

100

101

110

111

HB1 filter selection: decimate by 1 (complex to real enabled), or

decimate by 2 (complex to real disabled).

HB1 + TB2 filter selection: decimate by 3 (complex to real enabled),

or decimate by 6 (complex to real disabled).

HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real

enabled), or decimate by 12 (complex to real disabled).

HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to

real enabled), or decimate by 24 (complex to real disabled).

Decimation determined by Register 0x0371, Bits[7:4].

Only valid when Register 0x0310, Bits[2:0] = 3'b111.

0x0371

DDC3 input select

[7:4] DDC3 decimation rate

select

0x0

R/W

0

TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48

(complex to real disabled), or decimate by 24 (complex to real

enabled).

10

FB2 + HB1 filter selection: decimate by 10 (complex to real disabled),

or decimate by 5 (complex to real enabled).

11

FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real

disabled), or decimate by 10 (complex to real enabled).

100

FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to

real disabled), or decimate by 20 (complex to real enabled).

[3:0] Reserved

Reserved.

0x0

R

0x0374

DDC3 NCO control

[7:4] DDC3 NCO channel select

mode

For edge control, the internal counter wraps when the

Register 0x0374, Bits[3:0] value is reached.

R/W

0

Use Register 0x0314, Bits[3:0].

11

2'b00, GPIO A1, GPIO A0.

1000

1001

Increment internal counter when rising edge of GPIO_A0 pin.

Increment internal counter when rising edge of GPIO_A1 pin.

NCO channel select register map control.

[3:0] DDC3 NCO register map

channel select

0x0

R/W

0

Select NCO Channel 0.

Select NCO Channel 1.

Select NCO Channel 2.

Select NCO Channel 3.

Select NCO Channel 4.

Select NCO Channel 5.

Select NCO Channel 6.

Select NCO Channel 7.

Select NCO Channel 8.

Select NCO Channel 9.

Select NCO Channel 10.

Select NCO Channel 11.

Select NCO Channel 12.

Select NCO Channel 13.

Select NCO Channel 14.

Select NCO Channel 15.

Reserved.

1

10

11

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

0x0375

DDC3 phase control [7:4] Reserved

0x0

R

analog.com

Rev. 0 | 99 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

[3:0] DDC3 phase update index

Indexes the NCO channel whose phase and offset gets updated. The 0x0

update method is based on the DDC phase update mode, which can

be continuous or require chip transfer.

R/W

0000

0001

0010

0011

Update NCO Channel 0.

Update NCO Channel 1.

Update NCO Channel 2.

Update NCO Channel 3.

0x0376

0x0377

0x0378

0x0379

0x037A

0x037B

0x037D

0x037E

0x037F

0x0380

0x0381

0x0382

0x0387

DDC3 Phase

Increment 0

[7:0] DDC3 phase increment

[7:0]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

0x0

R/W

.

DDC3 Phase

Increment 1

[7:0] DDC3 phase increment

[15:8]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC3 Phase

Increment 2

[7:0] DDC3 phase increment

[23:16]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC3 Phase

Increment 3

[7:0] DDC3 phase increment

[31:24]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC3 Phase

Increment 4

[7:0] DDC3 phase increment

[39:32]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC3 Phase

Increment 5

[7:0] DDC3 phase increment

[47:40]

FTW. Twos complement phase increment value for the NCO.

Complex mixing frequency = (DDC phase increment × f_S)/2⁴⁸

DDC3 Phase

Offset 0

[7:0] DDC3 phase offset [7:0]

[7:0] DDC3 phase offset [15:8]

[7:0] DDC3 phase offset [23:16]

[7:0] DDC3 phase offset [31:24]

[7:0] DDC3 phase offset [39:32]

[7:0] DDC3 phase offset [47:40]

[7:2] Reserved

Twos complement phase offset value for the NCO.

DDC3 Phase

Offset 1

DDC3 Phase

Offset 2

DDC3 Phase

Offset 3

DDC3 Phase

Offset 4

DDC3 Phase

Offset 5

DDC3 test enable

Reserved.

0x0

R

1

0

Reserved

R

DDC3 I output test mode

enable

I samples always use the Test Mode A block. The test mode is

selected using the channel dependent Register 0x0550, Bits[3:0].

R/W

0

1

Test mode disabled.

Test mode enabled.

0x0390

0x0391

0x0392

0x0393

DDC0 Phase

Increment Fractional

A0

[7:0] DDC0 Phase Increment

Fractional A [7:0]

Numerator correction term for Modulus Phase Accumulator A.

0x0

R/W

DDC0 Phase

Increment Fractional

A1

[7:0] DDC0 Phase Increment

Fractional A [15:8]

Numerator correction term for Modulus Phase Accumulator A.

DDC0 Phase

Increment Fractional

A2

[7:0] DDC0 Phase Increment

Fractional A [23:16]

DDC0 Phase

Increment Fractional

A3

[7:0] DDC0 Phase Increment

Fractional A [31:24]

analog.com

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x0394

DDC0 Phase

Increment Fractional

A4

[7:0] DDC0 Phase Increment

Fractional A [39:32]

Numerator correction term for Modulus Phase Accumulator A.

0x0

R/W

0x0395

0x0398

0x0399

0x039A

0x039B

0x039C

0x039D

0x03A0

0x03A1

0x03A2

0x03A3

0x03A4

0x03A5

0x03A8

0x03A9

0x03AA

0x03AB

DDC0 Phase

Increment Fractional

A5

[7:0] DDC0 Phase Increment

Fractional A [47:40]

Numerator correction term for Modulus Phase Accumulator A.

Denominator correction term for Modulus Phase Accumulator B.

Numerator correction term for Modulus Phase Accumulator A.

Denominator correction term for Modulus Phase Accumulator B.

DDC0 Phase

Increment Fractional

B0

[7:0] DDC0 Phase Increment

Fractional B [7:0]

DDC0 Phase

Increment Fractional

B1

[7:0] DDC0 Phase Increment

Fractional B [15:8]

DDC0 Phase

Increment Fractional

B2

[7:0] DDC0 Phase Increment

Fractional B [23:16]

DDC0 Phase

Increment Fractional

B3

[7:0] DDC0 Phase Increment

Fractional B [31:24]

DDC0 Phase

Increment Fractional

B4

[7:0] DDC0 Phase Increment

Fractional B [39:32]

DDC0 Phase

Increment Fractional

B5

[7:0] DDC0 Phase Increment

Fractional B [47:40]

DDC1 Phase

Increment Fractional

A0

[7:0] DDC1 Phase Increment

Fractional A [7:0]

DDC1 Phase

Increment Fractional

A1

[7:0] DDC1 Phase Increment

Fractional A [15:8]

DDC1 Phase

Increment Fractional

A2

[7:0] DDC1 Phase Increment

Fractional A [23:16]

DDC1 Phase

Increment Fractional

A3

[7:0] DDC1 Phase Increment

Fractional A [31:24]

DDC1 Phase

Increment Fractional

A4

[7:0] DDC1 Phase Increment

Fractional A [39:32]

DDC1 Phase

Increment Fractional

A5

[7:0] DDC1 Phase Increment

Fractional A [47:40]

DDC1 Phase

Increment Fractional

B0

[7:0] DDC1 Phase Increment

Fractional B [7:0]

DDC1 Phase

Increment Fractional

B1

[7:0] DDC1 Phase Increment

Fractional B [15:8]

DDC1 Phase

Increment Fractional

B2

[7:0] DDC1 Phase Increment

Fractional B [23:16]

DDC1 Phase

Increment Fractional

B3

[7:0] DDC1 Phase Increment

Fractional B [31:24]

analog.com

Rev. 0 | 101 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x03AC

DDC1 Phase

Increment Fractional

B4

[7:0] DDC1 Phase Increment

Fractional B [39:32]

Denominator correction term for Modulus Phase Accumulator B.

0x0

R/W

0x03AD

0x03B0

0x03B1

0x03B2

0x03B3

0x03B4

0x03B5

0x03B8

0x03B9

0x03BA

0x03BB

0x03BC

0x03BD

0x03C0

0x03C1

0x03C2

0x03C3

DDC1 Phase

Increment Fractional

B5

[7:0] DDC1 Phase Increment

Fractional B [47:40]

Denominator correction term for Modulus Phase Accumulator B.

Numerator correction term for Modulus Phase Accumulator A.

Denominator correction term for Modulus Phase Accumulator B.

Numerator correction term for Modulus Phase Accumulator A.

DDC2 Phase

Increment Fractional

A0

[7:0] DDC2 Phase Increment

Fractional A [7:0]

DDC2 Phase

Increment Fractional

A1

[7:0] DDC2 Phase Increment

Fractional A [15:8]

DDC2 Phase

Increment Fractional

A2

[7:0] DDC2 Phase Increment

Fractional A [23:16]

DDC2 Phase

Increment Fractional

A3

[7:0] DDC2 Phase Increment

Fractional A [31:24]

DDC2 Phase

Increment Fractional

A4

[7:0] DDC2 Phase Increment

Fractional A [39:32]

DDC2 Phase

Increment Fractional

A5

[7:0] DDC2 Phase Increment

Fractional A [47:40]

DDC2 Phase

Increment Fractional

B0

[7:0] DDC2 Phase Increment

Fractional B [7:0]

DDC2 Phase

Increment Fractional

B1

[7:0] DDC2 Phase Increment

Fractional B [15:8]

DDC2 Phase

Increment Fractional

B2

[7:0] DDC2 Phase Increment

Fractional B [23:16]

DDC2 Phase

Increment Fractional

B3

[7:0] DDC2 Phase Increment

Fractional B [31:24]

DDC2 Phase

Increment Fractional

B4

[7:0] DDC2 Phase Increment

Fractional B [39:32]

DDC2 Phase

Increment Fractional

B5

[7:0] DDC2 Phase Increment

Fractional B [47:40]

DDC3 Phase

Increment Fractional

A0

[7:0] DDC3 Phase Increment

Fractional A [7:0]

DDC3 Phase

Increment Fractional

A1

[7:0] DDC3 Phase Increment

Fractional A [15:8]

DDC3 Phase

Increment Fractional

A2

[7:0] DDC3 Phase Increment

Fractional A [23:16]

DDC3 Phase

Increment Fractional

A3

[7:0] DDC3 Phase Increment

Fractional A [31:24]

analog.com

Rev. 0 | 102 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x03C4

DDC3 Phase

Increment Fractional

A4

[7:0] DDC3 Phase Increment

Fractional A [39:32]

Numerator correction term for Modulus Phase Accumulator A.

0x0

R/W

0x03C5

0x03C8

0x03C9

0x03CA

0x03CB

0x03CC

0x03CD

DDC3 Phase

Increment Fractional

A5

[7:0] DDC3 Phase Increment

Fractional A [47:40]

Numerator correction term for Modulus Phase Accumulator A.

Denominator correction term for Modulus Phase Accumulator B.

DDC3 Phase

Increment Fractional

B0

[7:0] DDC3 Phase Increment

Fractional B [7:0]

DDC3 Phase

Increment Fractional

B1

[7:0] DDC3 Phase Increment

Fractional B [15:8]

DDC3 Phase

Increment Fractional

B2

[7:0] DDC3 Phase Increment

Fractional B [23:16]

DDC3 Phase

Increment Fractional

B3

[7:0] DDC3 Phase Increment

Fractional B [31:24]

DDC3 Phase

Increment Fractional

B4

[7:0] DDC3 Phase Increment

Fractional B [39:32]

DDC3 Phase

Increment Fractional

B5

[7:0] DDC3 Phase Increment

Fractional B [47:40]

Digital Outputs and Test Modes Registers

0x0550

ADC test mode

control (local)

7

User pattern selection

Test mode user pattern selection. This bit is only used when Register 0x0

0x0550, Bits[3:0] = 4’b1000 (user input mode). Otherwise, it is

ignored. User Pattern 1 is found in the User Pattern 1 MSB register

(Register 0x0552) and the User Pattern 1 LSB (Register 0x0551)

registers. User Pattern 2 is found in the User Pattern 2 MSB register

(Register 0x0554) and the User Patter 2 LSB (Register 0x0553)

register, and so on.

R/W

0

1

Continuous/repeat pattern. Place each user pattern (1, 2, 3, and 4)

on the output for 1 clock cycle and then repeat. (Output User Pattern

1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, and so on.)

Single pattern. Place each user pattern (1, 2, 3, and 4) on the output

for 1 clock cycle and then output all zeros. (Output User Pattern 1, 2,

3, 4, and then output all zeros.)

6

5

Reserved

Reserved.

0x0

R

Reset PN long generator

Test mode long pseudorandom number test generator reset.

Long PN enabled.

R/W

0

1

Long PN held in reset.

4

Reset PN short generator

Test mode short pseudorandom number test generator reset.

Short PN enabled.

0x0

R/W

0

1

Short PN held in reset.

[3:0] Test mode selection

Test mode generation selection.

Off (normal operation).

0000

0001

0010

0011

0100

0101

Midscale short.

Positive full scale.

Negative full scale.

Alternating checker board.

PN sequence (long).

analog.com

Rev. 0 | 103 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0110

0111

1000

PN sequence (short).

1/0 word toggle.

User pattern test mode (used with Register 0x0550, Bit 7 and the

User Pattern 1, User Pattern 2, User Pattern 3, and User Pattern 4

registers).

1111

Ramp output.

0x0551

0x0552

0x0553

0x0554

0x0555

0x0556

0x0557

0x0558

0x0559

User Pattern 1 LSB

[7:0] User Pattern 1 [7:0]

User Test Pattern 1 least significant byte.

User Test Pattern 2 least significant byte.

User Test Pattern 3 least significant bits.

User Test Pattern 4 least significant bits.

0x0

R/W

User Pattern 1 MSB [7:0] User Pattern 1 [15:8]

User Pattern 2 LSB [7:0] User Pattern 2 [7:0]

User Pattern 2 MSB [7:0] User Pattern 2 [15:8]

User Pattern 3 LSB [7:0] User Pattern 3 [7:0]

User Pattern 3 MSB [7:0] User Pattern 3 [15:8]

User Pattern 4 LSB [7:0] User Pattern 4 [7:0]

User Pattern 4 MSB [7:0] User Pattern 4 [15:8]

Output Mode Control [7:4] Converter control Bit 1

1

selection

0000

0001

0010

0011

0101

Tie low (1'b0).

Overrange bit.

Signal monitor bit.

Fast detect (FD) bit.

SYSREF.

[3:0] Converter control Bit 0

selection

0x0

R/W

0000

0001

0010

0011

0101

Tie low (1'b0).

Overrange bit.

Signal monitor bit.

Fast detect (FD) bit.

SYSREF.

0x055A

Output Mode Control [7:4] Reserved

2

Reserved.

0x0

0x1

R

[3:0] Converter control Bit 2

R/W

selection

0000

0001

0010

0011

0101

Tie low (1'b0).

Overrange bit.

Signal monitor bit.

Fast detect (FD) bit.

SYSREF.

0x0561

Out sample mode

[7:3] Reserved

Reserved.

0x0

R/W

2

Sample invert

0

1

ADC sample data is not inverted.

ADC sample data is inverted.

[1:0] Data format select

0x1

R/W

00

01

Offset binary.

Twos complement (default).

0x0562

Out overrange clear [7:0] Data format overrange clear

Overrange clear bits (one bit for each virtual converter). Writing a 1 to 0x0

the overrange clear bit clears the corresponding overrange sticky bit.

0

1

Overrange bit enabled.

Overrange bit cleared.

analog.com

Rev. 0 | 104 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x0563

Out overrange status [7:0] Data format overrange

Overrange sticky bit status (one bit for each virtual converter). Writing 0x0

a 1 to the overrange clear bit clears the corresponding overrange

sticky bit.

R

0

1

No overrange occurred.

Overrange occurred.

0x0564

0x056E

Out channel select

PLL control

[7:1] Reserved

Converter channel swap

control

Reserved.

0x0

R

0

R/W

0

1

Normal channel ordering.

Channel swap enabled.

[7:4] JESD204B lane rate control

0x3

R/W

0000

0001

0011

0101

Lane rate = 6.75 Gbps to 13.5 Gbps.

Lane rate = 3.375 Gbps to 6.75 Gbps.

Lane rate = 13.5 Gbps to 15.5 Gbps.

Lane rate = 1.6875 Gbps to 3.375 Gbps.

Reserved.

[3:0] Reserved

7 PLL lock status

0x0

R

0x056F

PLL status

0

1

Not locked.

Locked.

[6:4] Reserved

Reserved.

0x0

R

3

PLL loss of lock

Loss of lock sticky bit.

1

Indicate a loss of lock has occurred at some time. Cleared by setting

Register 0x0571, Bit 0.

[2:0] Reserved

[7:0]

Reserved.

0x0570

0x0571

f_S× 4 configuration

See the fS × 4 Mode section.

0xFF R/W

0xFD

0xFF

L = 4, M=1, F = 2, S = 4, N’ = 16, N = 16, CS = 0, CF = 0, HD = 0, fs

× 4 mode enabled

f_S× 4 mode disabled. L, M, and F set by Register 0x058B,

Bits[4:0], Register 0x58E, Bits[7:0], and Register 0x058C, Bits[7:0],

respectively.

JESD204B Link

Control 1

7

Standby mode

0x0

R/W

0

1

Standby mode forces zeros for all converter samples.

Standby mode forces code group synchronization (K28.5 characters).

6

5

Tail bit(t) PN

0x0

R/W

0

1

Disable.

Enable.

Long transport layer test

0

1

JESD204B test samples disabled.

JESD204B test samples enabled, long transport layer test sample

sequence (as specified in JESD204B Section 5.1.6.3) sent on all link

lanes.

4

Lane synchronization

0x1

R/W

0

1

Disable FACI uses /K28.7/.

Enable FACI uses /K28.3/ and /K28.7/.

[3:2] ILAS sequence mode

00

01

Initial lane alignment sequence disabled (JESD204B

Section 5.3.3.5).

Initial lane alignment sequence enabled (JESD204B Section 5.3.3.5).

analog.com

Rev. 0 | 105 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

11

Initial lane alignment sequence always on test mode. JESD204B

data link layer test mode where repeated lane alignment sequence

(as specified in JESD204B Section 5.3.3.8.2) sent on all lanes.

1

0

FACI

0x0

R/W

0

1

Frame alignment character insertion enabled (JESD204B Section

5.3.3.4).

Frame alignment character insertion disabled. For debug only

(JESD204B Section 5.3.3.4).

Link control

0

1

JESD204B serial transmit link enabled. Transmission of the /K28.5/

characters for code group synchronization is controlled by the

SYNC~ signal.

JESD204B serial transmit link powered down (held in reset and clock

gated).

0x0572

JESD204B Link

Control 2

[7:6] SYNCINB± pin control

0x0

R/W

00

10

11

Normal mode.

Ignore SYNCINB± (force CGS).

Ignore SYNCINB± (force ILAS/user data).

5

4

SYNCINB± pin invert

SYNCINB± pin type

0x0

R/W

0

1

SYNCINB± pin not inverted.

SYNCINB± pin inverted.

0

1

LVDS differential pair SYNC~ input.

CMOS single-ended SYNC~ input. SYNCINB+ used.

Reserved.

3

2

Reserved

0x0

R

8-bit/10-bit bypass

R/W

0

1

8-bit/10-bit enabled.

8-bit/10-bit bypassed (most significant 2 bits are 0).

1

8-bit/10-bit bit invert

0x0

R/W

0

1

Normal.

Invert a, b, c, d, e, f, g, h, I, and j symbols.

Reserved.

0

Reserved

0x0

R/W

0x0573

JESD204B Link

Control 3

[7:6] Checksum mode

00

01

Checksum is the sum of all 8-bit registers in the link configuration

table.

Checksum is the sum of all individual link configuration fields (LSB

aligned).

10

11

Checksum is disabled (set to zero). For test purposes only.

Unused.

[5:4] Test injection point

0x0

R/W

0

N' sample input.

1

10-bit data at 8-bit/10-bit output (for PHY testing).

8-bit data at scrambler input.

10

[3:0] JESD204B test mode

patterns

0

1

Normal operation (test mode disabled).

Alternating checkerboard.

analog.com

Rev. 0 | 106 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

10

1/0 word toggle.

11

31-bit pseudorandom number (PN) sequence: x³¹+ x²⁸+ 1.

23-bit PN sequence: x²³+ x¹⁸+ 1.

15-bit PN sequence: x¹⁵+ x¹⁴+ 1.

9-bit PN sequence: x⁹+ x⁵+ 1.

7-bit PN sequence: x⁷+ x⁶+ 1.

Ramp output.

100

101

110

111

1000

1110

1111

Continuous/repeat user test.

Single user test.

0x0574

JESD204B Link

Control 4

[7:4] ILAS delay

0x0

R/W

0

Transmit ILAS on first LMFC after SYNCINB± deasserted.

Transmit ILAS on second LMFC after SYNCINB± deasserted.

Transmit ILAS on third LMFC after SYNCINB± deasserted.

Transmit ILAS on fourth LMFC after SYNCINB± deasserted.

Transmit ILAS on fifth LMFC after SYNCINB± deasserted.

Transmit ILAS on sixth LMFC after SYNCINB± deasserted.

Transmit ILAS on seventh LMFC after SYNCINB± deasserted.

Transmit ILAS on eighth LMFC after SYNCINB± deasserted.

Transmit ILAS on ninth LMFC after SYNCINB± deasserted.

Transmit ILAS on tenth LMFC after SYNCINB± deasserted.

Transmit ILAS on eleventh LMFC after SYNCINB± deasserted.

Transmit ILAS on twelfth LMFC after SYNCINB± deasserted.

Transmit ILAS on thirteenth LMFC after SYNCINB± deasserted.

Transmit ILAS on fourteenth LMFC after SYNCINB± deasserted.

Transmit ILAS on fifteenth LMFC after SYNCINB± deasserted.

Transmit ILAS on sixteenth LMFC after SYNCINB± deasserted.

Reserved.

1

10

11

100

101

110

111

1000

1001

1010

1011

1100

1101

1110

1111

3

Reserved

0x0

R

[2:0] Link layer test mode

R/W

000

001

010

011

100

101

110

111

Normal operation (link layer test mode disabled).

Continuous sequence of /D21.5/ characters.

Reserved.

Modified RPAT test sequence.

JSPAT test sequence.

JTSPAT test sequence.

Reserved.

0x0578

JESD204B LMFC

offset

[7:5] Reserved

Reserved.

0x0

R

[4:0] LMFC phase offset value

[7:0] JESD204B Tx DID value

[7:4] Reserved

Local multiframe clock (LMFC) phase offset value (in frame clocks).

Refer to the Deterministic Latency section.

R/W

R

0x0580

0x0581

JESD204B DID

configuration

JESD204B serial device identification (DID) number.

JESD204B BID

configuration

Reserved.

[3:0] JESD204B Tx BID value

[7:5] Reserved

JESD204B serial bank identification (BID) number (extension to DID). 0x0

Reserved. 0x0

R/W

R

0x0583

JESD204B LID0

configuration

analog.com

Rev. 0 | 107 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

[4:0] Lane 0 LID value

[7:5] Reserved

JESD204B serial lane identification (LID) number for Lane 0.

Reserved.

0x0

R/W

R

0x0584

JESD204B LID1

configuration

[4:0] Lane 1 LID value

[7:5] Reserved

JESD204B serial lane identification (LID) number for Lane 1.

Reserved.

0x1

0x0

R/W

R

0x0585

0x0586

0x0587

0x0588

0x0589

0x058A

0x058B

JESD204B LID2

configuration

[4:0] Lane 2 LID value

[7:5] Reserved

JESD204B serial lane identification (LID) number for Lane 2.

Reserved.

0x2

0x0

R/W

R

JESD204B LID3

configuration

[4:0] Lane 3 LID value

[7:5] Reserved

JESD204B serial lane identification (LID) number for Lane 3.

Reserved.

0x3

0x0

R/W

R

JESD204B LID4

configuration

[4:0] Lane 4 LID value

[7:5] Reserved

JESD204B serial lane identification (LID) number for Lane 4.

Reserved.

0x4

0x0

R/W

R

JESD204B LID5

configuration

[4:0] Lane 5 LID value

[7:5] Reserved

JESD204B serial lane identification (LID) number for Lane 5.

Reserved.

0x5

0x0

R/W

R

JESD204B LID6

configuration

[4:0] Lane 6 LID value

[7:5] Reserved

JESD204B serial lane identification (LID) number for Lane 6.

Reserved.

0x6

0x0

R/W

R

JESD204B LID7

configuration

[4:0] Lane 7 LID value

JESD204B serial lane identification (LID) number for Lane 7.

0x7

0x1

R/W

JESD204B

7

JESD204B scrambling

(SCR)

scrambling and

number lanes (L)

configuration

0

1

JESD204B scrambler disabled (SCR = 0).

JESD204B scrambler enabled (SCR = 1).

Reserved.

[6:5] Reserved

0x0

0x7

R

[4:0] JESD204B lanes (L)

R/W

0x0

0x1

0x3

0x7

One lane per link (L = 1).

Two lanes per link (L = 2).

Four lanes per link (L = 4).

Eight lanes per Link (L = 8).

0x058C

JESD204B link

number of octets per

frames (F)

[7:0] JESD204B F configuration

JESD204B number of octets per frame (F = JESD204B

F configuration + 1)

0x0

R/W

0

F = 1.

1

F = 2.

10

11

F = 3.

F = 4.

101

111

1111

F = 6.

F = 8.

F = 16.

Reserved.

0x058D

JESD204B link

[7:5] Reserved

0x0

R

number of frames

per multiframe (K)

[4:0] JESD204B K configuration

JESD204B number of frames per multiframe (K = JESD204B K

configuration + 1). Only values where F × K is divisible by 4 can be

used.

0x1F

R/W

analog.com

Rev. 0 | 108 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x058E

JESD204B link

number of

[7:0] JESD204B M configuration

JESD204B number of converters per link/device (M = JESD204B M

configuration).

0x1

R/W

converters (M)

0

Link connected to one virtual converter (M = 1).

Link connected to two virtual converters (M = 2).

Link connected to four virtual converters (M = 4).

Link connected to eight virtual converters (M = 8).

1

11

111

0x058F

JESD204B number

of control bits (CS)

and ADC resolution

(N)

[7:6] Number of control bits (CS)

per sample

0x0

R/W

0

No control bits (CS = 0).

1

1 control bit (CS = 1), Control Bit 2 only.

2 control bits (CS = 2), Control Bit 2 and Control Bit 1 only.

10

11

3 control bits (CS = 3), all control bits (Control Bit 2, Control Bit 1, and

Control Bit 0).

5

Reserved

Reserved.

0x0

0xF

R

[4:0] ADC converter resolution

(N)

R/W

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

N = 7-bit resolution.

N = 8-bit resolution.

N = 9-bit resolution.

N = 10-bit resolution.

N = 11-bit resolution.

N = 12-bit resolution.

N = 13-bit resolution.

N = 14-bit resolution.

N = 15-bit resolution.

N = 16-bit resolution.

0x0590

JESD204B SCV NP [7:5] Subclass support

configuration

0x1

0xF

R/W

000

001

Subclass 0.

Subclass 1.

[4:0] ADC number of bits per

sample (N')

0 0111

0 1011

0 1111

N' = 8.

N' = 12.

N' = 16.

Reserved.

0x0591

0x0592

JESD204B JV S

configuration

[7:5] Reserved

0x1

0x0

R

[4:0] Samples per converter

frame cycle (S)

Samples per converter frame cycle (S = Register 0x0591, Bits[4:0] +

1).

JESD204B HD CF

configuration

7

HD value

0

1

High density format disabled.

High density format enabled.

Reserved.

[6:5] Reserved

0x0

R

[4:0] Control words per frame

clock cycle per link (CF)

Number of control words per frame clock cycle per link

(CF = Register 0x0592, Bits[4:0]).

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

0x05A0

JESD204B

Checksum 0

configuration

[7:0] Checksum 0 checksum

value for SERDOUT0±

Serial checksum value for Lane 0. Automatically calculated for each

lane. Sum (all link configuration parameters for Lane 0) mod 256.

0xC3

0xC4

0xC5

0xC6

0x0

R

0x05A1

0x05A2

0x05A3

0x05B0

JESD204B

Checksum 1

configuration

[7:0] Checksum 1 checksum

value for SERDOUT1±

Serial checksum value for Lane 1. Automatically calculated for each

lane. Sum (all link configuration parameters for Lane 1) mod 256.

R

JESD204B

Checksum 2

configuration

[7:0] Checksum 2 checksum

value for SERDOUT2±

Serial checksum value for Lane 2. Automatically calculated for each

lane. Sum (all link configuration parameters for each lane) mod 256.

R

JESD204B

Checksum 3

configuration

[7:0] Checksum 3 checksum

value for SERDOUT3±

Serial checksum value for Lane 3. Automatically calculated for each

lane. Sum (all link configuration parameters for Lane 3) mod 256.

R

JESD204B lane

power-down

7

6

5

4

3

2

1

0

7

JESD204B Lane 7 power-

down

Physical Lane 7 force power-down.

R/W

0

1

SERDOUT7± normal operation.

SERDOUT7± power-down.

JESD204B Lane 6 power-

down

Physical Lane 6 force power-down.

0x0

R/W

0

1

SERDOUT6± normal operation.

SERDOUT6± power-down.

JESD204B Lane 5 power-

down

Physical Lane 5 force power-down.

0

1

SERDOUT5± normal operation.

SERDOUT5± power-down.

JESD204B Lane 4 power-

down

Physical Lane 4 force power-down.

0

1

SERDOUT4± normal operation.

SERDOUT4± power-down.

JESD204B Lane 3 power-

down

Physical Lane 3 force power-down.

0

1

SERDOUT3± normal operation.

SERDOUT3± power-down.

JESD204B Lane 2 power-

down

Physical Lane 2 force power-down.

0

1

SERDOUT2± normal operation.

SERDOUT2± power-down.

JESD204B Lane 1 power-

down

Physical Lane 1 force power-down.

0

1

SERDOUT1± normal operation.

SERDOUT1± power-down.

JESD204B Lane 0 power-

down

Physical Lane 0 force power-down.

0

1

SERDOUT0± normal operation.

SERDOUT0± power-down.

Reserved.

0x05B2

JESD204B Lane

Assign 1

Reserved

0x0

0x1

R

[6:4] SERDOUT1± lane

assignment

Physical Lane 1 assignment.

R/W

0

1

Logical Lane 0.

Logical Lane 1 (default).

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

10

Logical Lane 2.

Logical Lane 3.

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

Reserved.

11

100

101

110

111

3

Reserved

0x0

R

[2:0] SERDOUT0± lane

assignment

Physical Lane 0 assignment.

R/W

0

Logical Lane 0 (default).

Logical Lane 1.

Logical Lane 2.

Logical Lane 3.

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

Reserved.

1

10

11

100

101

110

111

0x05B3

JESD204B Lane

Assign 2

7

Reserved

0x0

0x3

R

[6:4] SERDOUT3± lane

assignment

Physical Lane 3 assignment.

R/W

0

Logical Lane 0.

1

Logical Lane 1.

10

11

Logical Lane 2.

Logical Lane 3 (default).

Logical Lane 4.

100

101

110

111

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

3

Reserved

Reserved.

0x0

0x2

R

[2:0] SERDOUT2± lane

assignment

Physical Lane 2 assignment.

R/W

0

Logical Lane 0.

Logical Lane 1

Logical Lane 2 (default).

Logical Lane 3.

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

Reserved.

1

10

11

100

101

110

111

0x05B5

JESD204B Lane

Assign 3

7

Reserved

0x0

0x5

R

[6:4] SERDOUT5± lane

assignment

Physical Lane 5 assignment.

R/W

0

Logical Lane 0.

Logical Lane 1.

Logical Lane 2.

Logical Lane 3.

1

10

11

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

100

101

110

111

Logical Lane 4.

Logical Lane 5 (default).

Logical Lane 6.

Logical Lane 7.

3

Reserved

Reserved.

0x0

0x4

R

[2:0] SERDOUT4± lane

assignment

Physical Lane 4 assignment.

R/W

0

Logical Lane 0.

Logical Lane 1.

Logical Lane 2.

Logical Lane 3.

Logical Lane 4 (default).

Logical Lane 5.

Logical Lane 6.

Logical Lane 7.

Reserved.

1

10

11

100

101

110

111

0x05B6

JESD204B Lane

Assign 4

7

Reserved

0x0

0x7

R

[6:4] SERDOUT7± lane

assignment

Physical Lane 7 assignment.

R/W

0

Logical Lane 0.

1

Logical Lane 1.

10

11

Logical Lane 2.

Logical Lane 3.

100

101

110

111

Logical Lane 4.

Logical Lane 5.

Logical Lane 6.

Logical Lane 7 (default).

Reserved.

3

Reserved

0x0

0x6

R

[2:0] SERDOUT6± lane

assignment

Physical Lane 6 assignment.

R/W

0

Logical Lane 0.

1

Logical Lane 1.

10

11

Logical Lane 2.

Logical Lane 3.

100

101

110

111

Logical Lane 4.

Logical Lane 5.

Logical Lane 6 (default).

Logical Lane 7.

0x05BF

SERDOUTx± data

invert

7

Invert SERDOUT7± data

Invert SERDOUT7± data.

0x0

R/W

0

1

Normal.

Invert.

6

5

Invert SERDOUT6± data

Invert SERDOUT5± data

Invert SERDOUT6± data.

0x0

R/W

0

1

Normal.

Invert.

Invert SERDOUT5± data.

0

1

Normal.

Invert.

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Invert SERDOUT4± data

Settings

Description

Reset Access

4

3

2

1

0

7

Invert SERDOUT4± data.

Normal.

0x0

R/W

0

1

Invert.

Invert SERDOUT3± data

Invert SERDOUT2± data

Invert SERDOUT1± data

Invert SERDOUT0± data

Reserved

Invert SERDOUT3± data.

Normal.

0

1

Invert.

Invert SERDOUT2± data.

Normal.

0

1

Invert.

Invert SERDOUT1± data.

Normal.

0

1

Invert.

Invert SERDOUT0± data.

Normal.

0

1

Invert.

0x05C0

0x05C1

0x05C2

JESD204B Swing

Adjust 1

Reserved.

0x0

0x1

R

[6:4] SERDOUT1± voltage swing

adjust

Output swing level for SERDOUT1±.

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

3

Reserved

0x0

0x1

R

[2:0] SERDOUT0± voltage swing

adjust

Output swing level for SERDOUT0±.

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

JESD204B Swing

Adjust 2

7

Reserved

0x0

0x1

R

[6:4] SERDOUT3± voltage swing

adjust

Output swing level for SERDOUT3±.

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

3

Reserved

0x0

0x1

R

[2:0] SERDOUT2± voltage swing

adjust

Output swing level for SERDOUT2±.

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

JESD204B Swing

Adjust 3

7

Reserved

0x0

0x1

R

[6:4] SERDOUT5± voltage swing

adjust

Output swing level for SERDOUT5±.

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

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Rev. 0 | 113 of 121

Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Reserved

Settings

Description

Reset Access

3

Reserved.

0x0

0x1

R

[2:0] SERDOUT4± voltage swing

adjust

Output swing level for SERDOUT4±.

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

0x05C3

JESD204B Swing

Adjust 4

7

Reserved

0x0

0x1

R

[6:4] SERDOUT7± voltage swing

adjust

Output swing level for SERDOUT7±.

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Reserved.

3

Reserved

0x0

0x1

R

[2:0] SERDOUT6± voltage swing

adjust

Output swing level for SERDOUT6±.

R/W

000

001

010

1.0 × DRVDD1.

0.850 × DRVDD1.

0.750 × DRVDD1.

Post tap enable.

0x05C4

0x05C5

0x05C6

SERDOUT0 pre-

emphasis select

7

Post tap enable

0x0

R/W

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT0±

Set post tap level.

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

SERDOUT1 pre-

emphasis select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT1±

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

SERDOUT2 pre-

emphasis select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT2±

Set post tap level.

0x0

R/W

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05C7

SERDOUT3 pre-

emphasis select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT3±

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05C8

0x05C9

0x05CA

SERDOUT4 pre-

emphasis select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT4±

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

SERDOUT5 pre-

emphasis select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT5±

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

SERDOUT6 pre-

emphasis select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT6±

Set post tap level.

0x0

R/W

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

Reserved.

Post tap enable.

0x0

R/W

0x05CB

SERDOUT7 pre-

emphasis select

7

Post tap enable

0

1

Disable.

Enable.

[6:4] Set post tap level for

SERDOUT7±

Set post tap level.

0x0

R/W

000

001

010

011

100

0 dB.

3 dB.

6 dB.

9 dB.

12 dB.

[3:0] Reserved

[7:0]

Reserved.

See Table 30.

0x0

R/W

0x1222

0x1228

0x1262

JESD204B PLL

calibration

0x00

0x04

JESD204B PLL normal operation.

Reset JESD204B PLL calibration

See Table 30.

JESD204B PLL

start-up control

[7:0]

0x0F

0x00

R/W

0x0F

0x4F

JESD204B start-up circuit in normal operation.

Reset JESD204B start-up circuit.

See Table 30.

JESD204B PLL LOL [7:0]

bit control

0x00

0x80

Loss of lock bit normal operation.

Clear loss of lock bit.

Programmable Filter Control and Coefficients Registers

0x0DF8

PFILT control

[7:3] Reserved

Reserved.

0x0

R

[2:0] PFILT mode

Programmable filter (PFILT) mode.

Disabled (filters bypassed).

Single filter (X only).

DOUT[n] = DIN[n] × X[n].

Single filter (X and Y together).

DOUT[n] = DIN[n] * XY_I[n].

Cascaded filters (X to Y).

DOUT[n] = DIN[n] × X[n] × Y[n].

Real 96-tap filter.

R/W

000

001

010

100

111

DOUT[n] = DIN_I[n] × XY[n].

Reserved.

0x0DF9

PFILT gain

7

Reserved

0x0

R

[6:4] PFILT Y gain

PFILT Y gain.

R/W

110

111

000

001

−12 dB loss.

−6 dB loss.

0 dB gain.

+6 dB gain.

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

010

+12 dB gain.

Reserved.

3

Reserved

0x0

R

[2:0] PFILT X gain

PFILT X gain.

−12 dB loss.

−6 dB loss.

0 dB gain.

R/W

110

111

000

001

010

+6 dB gain.

+12 dB gain.

0x0E0 to PFILT X

[7:0] Programmable Filter X

Coefficient 0 to 127

Refer to the coefficient table (Table 14) in the Programmable FIR

Filters section for details. Coefficients are only applied after the chip

transfer bit (Register 0x000F, Bit 0) is set.

0x0

R/W

0x0E7F

Coefficient x

0x0F00

to

PFILT Y

Coefficient x

[7:0] Programmable Filter Y

Coefficient 0 to 127

Refer to the coefficient table (Table 14) in the Programmable FIR

Filters section for details. Coefficients are only applied after the chip

transfer bit (Register 0x000F, Bit 0) is set.

0x0F7F

VREF/Analog Input Control Registers

0x0701

DC offset calibration [7:0] DC offset calibration control

0x06

R/W

control (local)

0x06

0x86

Disable.

Enable.

0x18A6

VREF control

[7:1] Reserved

Reserved.

0x0

R

0

VREF control

R/W

0

1

Internal reference.

External reference.

Reserved.

0x18E3

0x18E6

External VCM buffer

control

7

6

Reserved

0x0

R

External VCM buffer

R/W

0

1

Disable.

Enable.

[5:0] External VCM buffer [5:0]

See the Input Common Mode section.

See the Temperature Diode section.

0x0

R/W

Temperature diode

export

[7:0] Temperature diode location

select

0x00

0x01

0x02

0x03

0x40

0x41

0x42

0x43

Central diode. VREF pin = high-Z.

Central diode. VREF pin = 1× diode voltage output.

Central diode. VREF pin = 20× diode voltage output.

Central diode. VREF pin = GND.

ADC Core diode. VREF pin = high-Z.

ADC Core diode. VREF pin = 1× diode voltage output.

ADC Core diode. VREF pin = 20× diode voltage output.

ADC Core diode. VREF pin = GND.

0x1908

0x1910

Analog input control [7:3] Reserved

(local)

Reserved.

0x0

R

2

Enable dc coupling

R/W

0

1

Analog input is optimized for ac coupling.

Analog input is optimized for dc coupling.

Reserved.

[1:0] Reserved

[7:4] Reserved

0x0

R

Input full-scale

control (local)

Reserved.

[3:0] Input full-scale voltage

Full-scale voltage setting.

0xD

R/W

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Data Sheet

AD9699

MEMORY MAP

Table 44. Memory Map Register Details

Addr.

Name

Bits Bit Name

Settings

Description

Reset Access

1000

1001

1101

1110

1111

0000

1.02 V p-p differential.

1.13 V p-p differential.

1.54 V p-p differential.

1.64 V p-p differential.

1.75 V p-p differential.

1.85 V p-p differential.

Reserved.

0x1A4C

Buffer Control 1

(local)

[7:6] Reserved

0x0

R

[5:0] Buffer Control 1

Input Buffer Main Current 1. See the Analog Input Buffer Controls

and SFDR Optimization section.

0x19

R/W

01 0100

01 1001

01 1110

10 0011

10 1000

11 0010

Buffer current set to 400 µA.

Buffer current set to 500 µA.

Buffer current set to 600 µA.

Buffer current set to 700 µA.

Buffer current set to 800 µA.

Buffer current set to 1000 µA.

Reserved.

0x1A4D

Buffer Control 2

(local)

[7:6] Reserved

0x0

R

[5:0] Buffer Control 2

Input Buffer Main Current 2. See the Analog Input Buffer Controls

and SFDR Optimization section.

0x19

R/W

01 0100

01 1001

01 1110

10 0011

10 1000

11 0010

Buffer current set to 400 µA.

Buffer current set to 500 µA.

Buffer current set to 600 µA.

Buffer current set to 700 µA.

Buffer current set to 800 µA.

Buffer current set to 1000 µA.

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Data Sheet

AD9699

APPLICATIONS INFORMATION

DRVDD1, in that order. Figure 127 shows the simplified schematic.

The dc resistance (DCR) of the ferrite bead must be taken into con-

sideration when choosing the appropriate ferrite bead. Otherwise,

excessive loss across the ferrite bead can lead to a malfunctioning

ADC. Adjustable LDO regulators can be employed to output a

higher voltage to account for the drop across the ferrite bead.

POWER SUPPLY RECOMMENDATIONS

Table 45 shows the power supplies needed to power the AD9699.

A power-on sequence is not required to operate the AD9699. The

power supply domains can be powered up in any order.

Table 45. Typical Power Supplies for the AD9699

Domain

Voltage (V)

Tolerance (%)

Alternatively, the LDO regulators can be bypassed altogether and

the AD9699 can be driven directly from the dc-to-dc converter.

Note that this approach has risks in that there may be more power

supply noise injected into the power supply domains of the ADC.

To minimize noise, follow the layout guidelines of the dc-to-dc

converter.

AVDD1

0.975

1.9

±2.5

AVDD1_SR

DVDD

DRVDD1

AVDD2

DRVDD2

SPIVDD

AVDD3

1.9

2.5

For applications requiring an optimal high power efficiency and low

noise performance, it is recommended that the ADP5054 quad

switching regulator be used to convert an input voltage in the 6.0

V to 15 V range to intermediate rails (1.3 V, 2.4 V, and 3.0 V).

These intermediate rails are then postregulated by very low noise,

low dropout (LDO) regulators (ADP1763, ADP7159, and ADP151).

Figure 126 shows the recommended power supply scheme for the

AD9699.

Figure 127. Simplified Power Solution for the AD9699

The user can employ several different decoupling capacitors to

cover both high and low frequencies. These capacitors must be

located close to the point of entry at the PCB level and close to the

devices, with minimal trace lengths.

LAYOUT GUIDELINES

The ADC evaluation board can be used as a guide to follow good

layout practices. The evaluation board layout is set up in such a

way as to

► Minimize clock coupling to the analog inputs.

► Provide enough power and ground planes for the various supply

domains while reducing cross coupling.

► Provide adequate thermal relief to the ADC.

Figure 126. High Efficiency, Low Noise Power Solution for the AD9699

Figure 128 shows the overall layout scheme used for the AD9699

evaluation board.

It is not necessary to split all of these power domains in all cases.

The recommended solution shown in Figure 126 provides the low-

est noise, highest efficiency power delivery system for the AD9699.

If only one 0.975 V supply is available, route to AVDD1 first and

then tap it off and isolate it with a ferrite bead or a filter choke,

preceded by decoupling capacitors for AVDD1_SR, DVDD, and

analog.com

Rev. 0 | 119 of 121

Data Sheet

AD9699

APPLICATIONS INFORMATION

AVDD1_SR (PIN E7) AND AGND (PIN E6 AND

PIN E8)

AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8) can be used

to provide a separate power supply node to the SYSREF± circuits

of the AD9699. If running in Subclass 1, the AD9699 can support

periodic one-shot or gapped signals. To minimize the coupling of

this supply into the AVDD1 supply node, adequate supply bypass-

ing is needed.

Figure 128. Recommended PCB Layout for the AD9699

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Data Sheet

AD9699

OUTLINE DIMENSIONS

Figure 129. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]

12 mm × 12 mm (BP-196-4)

Dimensions shown in millimeters

Updated: May 01, 2021

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Packing Quantity

Package Option

AD9699BBPZ-3000

−40°C to +105°C

196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] Tray, 189

196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] Reel, 1500

BP-196-4

AD9699BBPZRL-3000

1

Z = RoHS Compliant Part.

EVALUATION BOARDS

Model¹

Description

AD9208-3000EBZ

Evaluation Board

1

The AD9208-3000EBZ can be used to evaluate the AD9699.

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Rev. 0 | 121 of 121


型号：	AD9699BBPZRL-3000
厂家：	ADI
描述：	14-Bit, 3 GSPS, JESD204B, Single Analog-to-Digital Converter
文件：	总121页 (文件大小：8185K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9699BBPZRL-3000 [ADI]

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