AD9708ARUZ_技术文档

8-Bit, 100 MSPS+

TxDAC^®D/A Converter

a

AD9708

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Member of Pin-Compatible TxDAC Product Family

125 MSPS Update Rate

+5V

0.1␮F

8-Bit Resolution

Linearity: 1/4 LSB DNL

Linearity: 1/4 LSB INL

Differential Current Outputs

SINAD @ 5 MHz Output: 50 dB

Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V

Power-Down Mode: 20 mW @ 5 V

On-Chip 1.20 V Reference

Single +5 V or +3 V Supply Operation

Packages: 28-Lead SOIC and 28-Lead TSSOP

Edge-Triggered Latches

AVDD

REFLO COMP1

+1.20V REF

ACOM

AD9708

50pF

0.1␮F

REF IO

0.1␮F

COMP2

CURRENT

SOURCE

ARRAY

FS ADJ

R

SET

IOUTA

IOUTB

+5V

DVDD

SEGMENTED

SWITCHES

DCOM

CLOCK

LATCHES

SLEEP

Fast Settling: 35 ns Full-Scale Settling to 0.1%

DIGITAL DATA INPUTS (DB7–DB0)

APPLICATIONS

Differential current outputs are provided to support single-

ended or differential applications. The current outputs may be

directly tied to an output resistor to provide two complemen-

tary, single-ended voltage outputs. The output voltage compliance

range is 1.25 V.

Communications

Signal Reconstruction

Instrumentation

PRODUCT DESCRIPTION

The AD9708 is the 8-bit resolution member of the TxDAC

series of high performance, low power CMOS digital-to-analog

converters (DACs). The TxDAC family, which consists of pin

compatible 8-, 10-, 12-, and 14-bit DACs, was specifically opti-

mized for the transmit signal path of communication systems. All

of the devices share the same interface options, small outline

package and pinout, thus providing an upward or downward

component selection path based on performance, resolution and

cost. The AD9708 offers exceptional ac and dc performance

while supporting update rates up to 125 MSPS.

The AD9708 contains a 1.2 V on-chip reference and reference

control amplifier, which allows the full-scale output current to

be simply set by a single resistor. The AD9708 can be driven by

a variety of external reference voltages. The AD9708’s full-scale

current can be adjusted over a 2 mA to 20 mA range without

any degradation in dynamic performance. Thus, the AD9708

may operate at reduced power levels or be adjusted over a 20 dB

range to provide additional gain ranging capabilities.

The AD9708 is available in 28-lead SOIC and 28-lead TSSOP

packages. It is specified for operation over the industrial tem-

perature range.

The AD9708’s flexible single-supply operating range of +2.7 V

to +5.5 V and low power dissipation are well suited for portable

and low power applications. Its power dissipation can be

further reduced to 45 mW, without a significant degradation in

performance, by lowering the full-scale current output. In addi-

tion, a power-down mode reduces the standby power dissipa-

tion to approximately 20 mW.

PRODUCT HIGHLIGHTS

1. The AD9708 is a member of the TxDAC product family, which

provides an upward or downward component selection path

based on resolution (8 to 14 bits), performance and cost.

2. Manufactured on a CMOS process, the AD9708 uses a pro-

prietary switching technique that enhances dynamic perfor-

mance well beyond 8- and 10-bit video DACs.

3. On-chip, edge-triggered input CMOS latches readily interface

to +3 V and +5 V CMOS logic families. The AD9708 can

support update rates up to 125 MSPS.

4. A flexible single-supply operating range of +2.7 V to +5.5 V

and a wide full-scale current adjustment span of 2 mA to

20 mA allows the AD9708 to operate at reduced power levels

(i.e., 45 mW) without any degradation in dynamic performance.

The AD9708 is manufactured on an advanced CMOS process.

A segmented current source architecture is combined with a

proprietary switching technique to reduce spurious components

and enhance dynamic performance. Edge-triggered input latches

and a temperature compensated bandgap reference have been inte-

grated to provide a complete monolithic DAC solution. Flexible

supply options support +3 V and +5 V CMOS logic families.

The AD9708 is a current-output DAC with a nominal full-scale

output current of 20 mA and > 100 kΩ output impedance.

TxDAC is a registered trademark of Analog Devices, Inc.

5. A temperature compensated, 1.20 V bandgap reference is

included on-chip providing a complete DAC solution. An

external reference may be used.

REV. B

6. The current output(s) of the AD9708 can easily be config-

ured for various single-ended or differential applications.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

AD9708–SPECIFICATIONS

DC SPECIFICATIONS

Parameter

(T_MINto T_MAX, AVDD = +5 V, DVDD = +5 V, I_OUTFS= 20 mA, unless otherwise noted)

Min

Typ

Max

Units

RESOLUTION

8

Bits

MONOTONICITY

GUARANTEED OVER SPECIFIED TEMPERATURE RANGE

DC ACCURACY¹

Integral Linearity Error (INL)

Differential Nonlinearity (DNL)

–1/2

±1/4

+1/2

LSB

ANALOG OUTPUT

Offset Error

Gain Error (Without Internal Reference)

Gain Error (With Internal Reference)

Full-Scale Output Current²

Output Compliance Range

Output Resistance

–0.025

–10

2.0

–1.0

+0.025

+10

20.0

1.25

% of FSR

mA

V

kΩ

±2

±1

100

5

Output Capacitance

pF

REFERENCE OUTPUT

Reference Voltage

1.08

0.1

1.20

100

1.32

1.25

V

nA

Reference Output Current³

REFERENCE INPUT

Input Compliance Range

V

Reference Input Resistance

Small Signal Bandwidth (w/o C_COMP1

1

1.4

MΩ

MHz

4

)

TEMPERATURE COEFFICIENTS

Offset Drift

Gain Drift (Without Internal Reference)

Gain Drift (With Internal Reference)

Reference Voltage Drift

0

ppm of FSR/°C

ppm/°C

±50

±100

±50

POWER SUPPLY

Supply Voltages

AVDD⁵

2.7

5.0

25

3

5.5

30

V

mA

DVDD

Analog Supply Current (I_AVDD

Digital Supply Current (I_DVDD

)

6

Supply Current Sleep Mode (I_AVDD

)

8.5

175

mA

mW

% of FSR/V

Power Dissipation⁶(5 V, I_OUTFS= 20 mA)

Power Dissipation⁷(5 V, I_OUTFS= 20 mA)

Power Dissipation⁷(3 V, I_OUTFS= 2 mA)

Power Supply Rejection Ratio—AVDD

Power Supply Rejection Ratio—DVDD

140

190

45

–0.4

–0.025

+0.4

+0.025

OPERATING RANGE

–40

+85

°C

NOTES

¹Measured at IOUTA, driving a virtual ground.

²Nominal full-scale current, I_OUTFS, is 32 × the I_REFcurrent.

³Use an external buffer amplifier to drive any external load.

⁴Reference bandwidth is a function of external cap at COMP1 pin.

⁵For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.

⁶Measured at f_CLOCK= 50 MSPS and f_OUT= 1.0 MHz.

⁷Measured as unbuffered voltage output into 50 Ω R_LOADat IOUTA and IOUTB, f_CLOCK= 100 MSPS and f_OUT= 40 MHz.

Specifications subject to change without notice.

–2–

REV. B

AD9708

_MINto T_MAX, AVDD = +5 V, DVDD = +5 V, I_OUTFS= 20 mA, Single-Ended Output, IOUTA, 50 ⍀ Doubly

DYNAMIC SPECIFICATIONS T^(Terminated, unless otherwise noted)

P

arameter

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f_CLOCK

)

100

125

35

1

MSPS

ns

pV-s

ns

Output Settling Time (t_ST) (to 0.1%)¹

Output Propagation Delay (t_PD

Glitch Impulse

)

5

Output Rise Time (10% to 90%)¹

Output Fall Time (10% to 90%)¹

Output Noise (I_OUTFS= 20 mA)

Output Noise (I_OUTFS= 2 mA)

2.5

50

30

pA/√Hz

AC LINEARITY TO NYQUIST

Signal-to-Noise and Distortion Ratio

f

_CLOCK= 10 MSPS; f_OUT= 1.00 MHz

50

48

50

45

dB

_CLOCK= 50 MSPS; f_OUT= 1.00 MHz

_CLOCK= 50 MSPS; f_OUT= 12.51 MHz

_CLOCK= 100 MSPS; f_OUT= 5.01 MHz

_CLOCK= 100 MSPS; f_OUT= 25.01 MHz

–67

–59

–64

–48

dBc

–62

Spurious-Free Dynamic Range to Nyquist

f_CLOCK= 10 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 50 MSPS; f_OUT= 1.00 MHz

f_CLOCK= 50 MSPS; f_OUT= 12.51 MHz

f_CLOCK= 100 MSPS; f_OUT= 5.01 MHz

68

63

67

50

dBc

62

f_CLOCK= 100 MSPS; f_OUT= 25.01 MHz

NOTES

¹Measured single ended into 50 Ω load.

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS (T_MINto T_MAX, AVDD = +5 V, DVDD = +5 V, I_OUTFS= 20 mA unless otherwise noted)

P

arameter

Min

Typ

Max

Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V

Logic “1” Voltage @ DVDD = +3 V

Logic “0” Voltage @ DVDD = +5 V

Logic “0” Voltage @ DVDD = +3 V

Logic “1” Current

Logic “0” Current

Input Capacitance

Input Setup Time (t_S)

Input Hold Time (t_H)

Latch Pulsewidth (t_LPW

3.5

2.1

5

3

0

V

µA

pF

ns

1.3

0.9

+10

–10

5

2.0

1.5

3.5

)

Specifications subject to change without notice.

DB0–DB7

t_S

t_H

CLOCK

t_LPW

t_ST

t_PD

IOUTA

OR

IOUTB

0.1%

Figure 1. Timing Diagram

–3–

REV. B

AD9708

ABSOLUTE MAXIMUM RATINGS*

PIN FUNCTION DESCRIPTIONS

With

Respect to Min

Pin No. Name

Description

Parameter

Max

Units

1

2–7

8

DB7

Most Significant Data Bit (MSB).

AVDD

DVDD

ACOM

AVDD

ACOM

DCOM

DVDD

DCOM

ACOM

–0.3

–6.5

–0.3

–1.0

–0.3

+6.5

+0.3

+6.5

DVDD + 0.3

AVDD + 0.3

+0.3

V

°C

DB6–DB1 Data Bits 1–6.

DB0 Least Significant Data Bit (LSB).

9–14, 25 NC

No Internal Connection.

15

SLEEP

Power-Down Control Input. Active

High. Contains active pull-down circuit,

thus may be left unterminated if not

used.

Reference Ground when Internal 1.2 V

Reference Used. Connect to AVDD to

disable internal reference.

Reference Input/Output. Serves as

reference input when internal reference

disabled (i.e., Tie REFLO to AVDD).

Serves as 1.2 V reference output when

internal reference activated (i.e., Tie

REFLO to ACOM). Requires 0.1 µF

capacitor to ACOM when internal

reference activated.

CLOCK, SLEEP

Digital Inputs

IOUTA, IOUTB

COMP1, COMP2

REFIO, FSADJ

REFLO

Junction Temperature

Storage Temperature

Lead Temperature

(10 sec)

16

17

REFLO

REFIO

+150

–65

+300

°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum

ratings for extended periods may effect device reliability.

18

19

FS ADJ

COMP1

Full-Scale Current Output Adjust.

Bandwidth/Noise Reduction Node.

Add 0.1 µF to AVDD for optimum

performance.

THERMAL CHARACTERISTICS

Thermal Resistance

28-Lead 300 mil SOIC

θ_JA= 71.4°C/W

20

21

ACOM

IOUTB

Analog Common.

Complementary DAC Current Output.

Full-scale current when all data bits

are 0s.

DAC Current Output. Full-scale

current when all data bits are 1s.

Internal Bias Node for Switch Driver

Circuitry. Decouple to ACOM with

0.1 µF capacitor.

θ_JC= 23°C/W

28-Lead TSSOP

θ_JA= 97.9°C/W

θ_JC= 14.0°C/W

22

23

IOUTA

COMP2

PIN CONFIGURATION

24

AVDD

Analog Supply Voltage (+2.7 V to

+5.5 V).

Digital Common.

Digital Supply Voltage (+2.7 V to

+5.5 V).

Clock Input. Data latched on positive

28

27

26

25

24

23

22

21

20

1

2

3

4

5

6

(MSB) DB7

DB6

CLOCK

DVDD

DCOM

NC

26

27

DCOM

DVDD

DB5

DB4

DB3

AVDD

COMP2

IOUTA

IOUTB

ACOM

AD9708

TOP VIEW

(Not to Scale)

28

CLOCK

DB2

edge of clock.

DB1

7

8

9

DB0

NC

ORDERING GUIDE

19 COMP1

NC 10

NC 11

NC 12

NC 13

18

17

FS ADJ

REFIO

Temperature

Range

Package

Descriptions

Package

Options*

Model

16 REFLO

15 SLEEP

AD9708AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28

AD9708ARU –40°C to +85°C 28-Lead TSSOP

AD9708-EB Evaluation Board

NC

14

RU-28

NC = NO CONNECT

*R = Small Outline IC; RU = Thin Small Outline IC.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD9708 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. B

–4–

AD9708

DEFINITIONS OF SPECIFICATIONS

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per degree C. For reference drift, the drift is

reported in ppm per degree C.

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the

actual analog output from the ideal output, determined by a

straight line drawn from zero to full scale.

Power Supply Rejection

The maximum change in the full-scale output as the supplies

are varied from nominal to minimum and maximum specified

voltages.

Differential Nonlinearity (or DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Settling Time

Monotonicity

The time required for the output to reach and remain within a

specified error band about its final value, measured from the

start of the output transition.

A D/A converter is monotonic if the output either increases or

remains constant as the digital input increases.

Offset Error

Glitch Impulse

The deviation of the output current from the ideal of zero is

called offset error. For IOUTA, 0 mA output is expected when

the inputs are all 0s. For IOUTB, 0 mA output is expected

when all inputs are set to 1s.

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in pV-s.

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output

signal and the peak spurious signal over the specified bandwidth.

Gain Error

The difference between the actual and ideal output span. The

actual span is determined by the output when all inputs are set

to 1s minus the output when all inputs are set to 0s.

Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio

S/N+D is the ratio of the rms value of the measured output

signal to the rms sum of all other spectral components below the

Nyquist frequency, including harmonics but excluding dc. The

value for S/N+D is expressed in decibels.

Output Compliance Range

The range of allowable voltage at the output of a current-output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown resulting in

nonlinear performance.

Total Harmonic Distortion

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured output signal. It is

expressed as a percentage or in decibels (dB).

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (+25°C) value to the value at either T_MINor T_MAX. For

+5V

0.1␮F

AVDD

REFLO

+1.20V REF

COMP1

50pF

ACOM

AD9708

0.1␮F

REF IO

FS ADJ

COMP2

CURRENT

SOURCE

ARRAY

0.1␮F

R

SET

2k⍀

IOUTA

IOUTB

+5V

DVDD

DCOM

CLOCK

TO HP3589A

SPECTRUM/

NETWORK

ANALYZER

50⍀ INPUT

SEGMENTED

SWITCHES

50⍀

20pF

LATCHES

DVDD

DCOM

SLEEP

50⍀

20pF

RETIMED

CLOCK

OUTPUT*

DIGITAL

DATA

CLOCK

OUTPUT

* AWG2021 CLOCK RETIMED

SUCH THAT DIGITAL DATA

TRANSITIONS ON FALLING EDGE

OF 50% DUTY CYCLE CLOCK.

LECROY 9210

PULSE GENERATOR

TEKTRONIX

AWG-2021

Figure 2. Basic AC Characterization Test Setup

REV. B

–5–

AD9708

Typical AC Characterization Curves _{(AVDD = +5 V or +3 V, DVDD = +5 V or +3 V, 50 ⍀ Doubly Terminated Load,}

Single-Ended Output, I_OUTA, I_OUTFS= 20 mA, T_A= +25؇C, unless otherwise noted)

70

65

60

55

50

70

65

60

55

50

55

THD @ 10MSPS

THD @ 50MSPS

THD

THD @ 10MSPS

I

= 20mA

= 10mA

OUTFS

50

THD

@ 100MSPS

I

OUTFS

@ 100MSPS

45

40

I

= 5mA

OUTFS

THD @ 50MSPS

I

= 2.5mA

OUTFS

SINAD @ 10MSPS

35

30

SINAD @ 50MSPS

45

40

45

40

SINAD @ 100MSPS

10

SINAD @ 100MSPS

0.1

1

100

0.1

1

10

100

1

10

FREQUENCY – MHz

100

FREQUENCY – MHz

Figure 3. SINAD/THD vs. f_OUT(AVDD

and DVDD = 5.0 V)

Figure 4. SINAD/THD vs. f_OUT(Differ-

ential Output, AVDD and DVDD = 5.0 V)

Figure 5. SINAD vs. I_OUTFS

@ 100 MSPS

52

70

THD

@ 10MSPS

I

= 20mA

= 5mA

OUTFS

THD @ 10MSPS

65

THD

@ 50MSPS

65

60

55

50

I

= 10mA

OUTFS

50

THD

@ 100MSPS

I

OUTFS

60

48

46

THD @ 50MSPS

55

THD @ 100MSPS

SINAD @ 10MSPS

I

= 2.5mA

OUTFS

50

SINAD @ 10MSPS

SINAD @ 50MSPS

45

44

42

45

40

SINAD @ 100MSPS

40

0.1

1

10

100

0.1

1

10

100

0.1

1

FREQUENCY – MHz

10

FREQUENCY – MHz

Figure 6. SINAD/THD vs. f_OUT(AVDD

and DVDD = 3.0 V)

Figure 7. SINAD/THD vs. f_OUT(Differ-

ential Output, AVDD and DVDD = 3.0 V)

Figure 8. SINAD vs. I_OUTFS

@ 20 MSPS

0

0.6

f

= 25MSPS

= 7.81MHz

CLOCK

f

= 125MSPS

CLOCK

OUT

0.5

f

= 27.0MHz

OUT

SFDR = +60.7dBc

AMPLITUDE = 0dBFS

SFDR = +52.7dBc

0.4

0.3

AMPLITUDE = 0dBc

0.2

0.1

0.0

–0.1

–0.2

–100

START: 0Hz

STOP: 12.5MHz

START: 0Hz

STOP: 62.5MHz

TIME – 5ns/Div

Figure 9. Single-Tone Spectral Plot

@ 25 MSPS

Figure 10. Single-Tone Spectral

Plot @ 125 MSPS

Figure 11. Step Response

REV. B

–6–

AD9708

FUNCTIONAL DESCRIPTION

As previously mentioned, I_OUTFSis a function of the reference

current I_REF, which is nominally set by a reference voltage

V_REFIOand external resistor R_SET. It can be expressed as:

Figure 12 shows a simplified block diagram of the AD9708. The

AD9708 consists of a large PMOS current source array capable of

providing up to 20 mA of total current. The array is divided into

31 equal currents that make up the five most significant bits

(MSBs). The remaining 3 LSBs are also implemented with equally

weighted current sources whose sum total equals 7/8th of an

MSB current source. Implementing the upper and lower bits

with current sources helps maintain the DAC’s high output

impedance (i.e. > 100 kΩ). All of these current sources are

switched to one or the other of the two output nodes (i.e., IOUTA

or IOUTB) via PMOS differential current switches. The switches

are based on a new architecture that drastically improves

distortion performance.

I_OUTFS= 32 × I_REF

(3)

where

I_REF= V_REFIO/R_SET

(4)

The two current outputs will typically drive a resistive load

directly. If dc coupling is required, IOUTA and IOUTB should

be directly connected to matching resistive loads, R_LOAD, which

are tied to analog common, ACOM. Note, R_LOADmay repre-

sent the equivalent load resistance seen by IOUTA or IOUTB

as would be the case in a doubly terminated 50 Ω or 75 Ω cable.

The single-ended voltage output appearing at the IOUTA and

IOUTB nodes is simply:

The analog and digital sections of the AD9708 have separate

power supply inputs (i.e., AVDD and DVDD) that can operate

independently over a 2.7 volt to 5.5 volt range. The digital section,

which is capable of operating up to a 125 MSPS clock rate,

consists of edge-triggered latches and segment decoding logic

circuitry. The analog section includes the PMOS current

sources, the associated differential switches, a 1.20 V bandgap

voltage reference and a reference control amplifier.

V

_OUTA= I_OUTA× R_LOAD

(5)

(6)

V

_OUTB= I_OUTB× R_LOAD

Note the full-scale value of V_OUTAand V_OUTBshould not exceed

the specified output compliance range to maintain specified

distortion and linearity performance.

The differential voltage, V_DIFF, appearing across IOUTA and

IOUTB is:

The full-scale output current is regulated by the reference con-

trol amplifier and can be set from 2 mA to 20 mA via an exter-

nal resistor, R_SET. The external resistor, in combination with

both the reference control amplifier and voltage reference

V_REFIO, sets the reference current I_REF, which is mirrored over to

the segmented current sources with the proper scaling factor.

V

_DIFF= (I_OUTA– I_OUTB) × R_LOAD

(7)

Substituting the values of I_OUTA, I_OUTB, and I_REF; V_DIFFcan be

expressed as:

V

_DIFF= {(2 DAC CODE – 255)/256}/ × (32 R_LOAD/R_SET

)

× V_REFIO

(8)

The full-scale current, I_OUTFS, is thirty-two times the value of I_REF

.

VOLTAGE REFERENCE AND CONTROL AMPLIFIER

DAC TRANSFER FUNCTION

The AD9708 contains an internal 1.20 V bandgap reference

The AD9708 provides complementary current outputs, IOUTA

and IOUTB. IOUTA will provide a near full-scale current output,

I_OUTFS, when all bits are high (i.e., DAC CODE = 255), while

IOUTB, the complementary output, provides no current. The

current output appearing at IOUTA and IOUTB are a function

of both the input code and I_OUTFSand can be expressed as:

that can be easily disabled and overridden by an external refer-

ence. REFIO serves as either an input or output depending on

whether the internal or an external reference is selected. If

REFLO is tied to ACOM, as shown in Figure 13, the internal

reference is activated and REFIO provides a 1.20 V output. In

this case, the internal reference must be compensated externally

with a ceramic chip capacitor of 0.1 µF or greater from REFIO

to REFLO. Note that REFIO is not designed to drive any ex-

ternal load. It should be buffered with an external amplifier

having an input bias current less than 100 nA if any additional

loading is required.

I_OUTA= (DAC CODE/256) × I_OUTFS

(1)

(2)

I_OUTB= (255 – DAC CODE)/256 × I_OUTFS

where DAC CODE = 0 to 255 (i.e., Decimal Representation).

+5V

0.1␮F

AVDD

REFLO

+1.20V REF

COMP1

50pF

ACOM

AD9708

V

0.1␮F

REFIO

COMP2

CURRENT

SOURCE

ARRAY

I

REF

FS ADJ

0.1␮F

R

SET

V

= V

– V

OUTA OUTB

DIFF

2k⍀

DVDD

+5V

I

IOUTA

IOUTB

OUTA

V

OUTA

SEGMENTED

SWITCHES

I

DCOM

OUTB

V

OUTB

LOAD

R

LOAD

CLOCK

50⍀

R

CLOCK

LATCHES

50⍀

SLEEP

DIGITAL DATA INPUTS (DB7–DB0)

Figure 12. Functional Block Diagram

–7–

REV. B

AD9708

+5V

The small signal bandwidth of the reference control amplifier is

approximately 1.8 MHz and can be reduced by connecting an

external capacitor between COMP1 and AVDD. The output of

the control amplifier, COMP1, is internally compensated via a

50 pF capacitor that limits the control amplifier small-signal

bandwidth and reduces its output impedance. Any additional

external capacitance further limits the bandwidth and acts as

a filter to reduce the noise contribution from the reference

amplifier. If I_REFis fixed for an application, a 0.1 µF ceramic chip

capacitor is recommended.

0.1␮F

OPTIONAL

EXTERNAL

REF BUFFER

REFLO

COMP1

AVDD

+1.2V REF

REFIO

FS ADJ

50pF

CURRENT

SOURCE

ARRAY

ADDITIONAL

LOAD

0.1␮F

2k⍀

AD9708

Figure 13. Internal Reference Configuration

I

_REFcan be varied for a fixed R_SETby disabling the internal

reference and varying the common-mode voltage over its

compliance range of 1.25 V to 0.10 V. REFIO can be driven by

a single-supply amplifier or DAC, thus allowing I_REFto be var-

ied for a fixed R_SET. Since the input impedance of REFIO is

approximately 1 MΩ, a simple R-2R ladder DAC configured in

the voltage mode topology may be used to control the gain. This

circuit is shown in Figure 15 using the AD7524 and an external

1.2 V reference, the AD1580. Note another AD9708 could also

be used as the gain control DAC since it can also provide a

programmable unipolar output up to 1.2 V.

The internal reference can be disabled by connecting REFLO to

AVDD. In this case, an external reference may then be applied

to REFIO as shown in Figure 14. The external reference may

provide either a fixed reference voltage to enhance accuracy and

drift performance or a varying reference voltage for gain control.

Note that the 0.1 µF compensation capacitor is not required

since the internal reference is disabled, and the high input

impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the

external reference.

AVDD

ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS

The AD9708 produces two complementary current outputs,

I_OUTAand I_OUTB, which may be converted into complementary

single-ended voltage outputs, V_OUTAand V_OUTB, via a load resistor,

R_LOAD, as described in the DAC TRANSFER FUNCTION

section. Figure 16 shows the AD9708 configured to provide a

positive unipolar output range of approximately 0 V to +0.5 V

for a double terminated 50 Ω cable for a nominal full-scale

current, I_OUTFS, of 20 mA. In this case, R_LOADrepresents the

equivalent load resistance seen by IOUTA or IOUTB and is

equal to 25 Ω. The unused output (IOUTA or IOUTB) can be

connected to ACOM directly or via a matching R_LOAD. Different

values of I_OUTFSand R_LOADcan be selected as long as the posi-

tive compliance range is adhered to.

0.1␮F

REFLO

+1.2V REF

COMP1

AVDD

50pF

V

REFIO

FS ADJ

EXTERNAL

REF

CURRENT

SOURCE

ARRAY

R

I

V

=

SET

REF

/R

REFERENCE

CONTROL

AMPLIFIER

REFIO SET

AD9708

Figure 14. External Reference Configuration

The AD9708 also contains an internal control amplifier that is

used to regulate the DAC’s full-scale output current, I_OUTFS

.

The control amplifier is configured as a V-I converter, as shown

in Figure 14, such that its current output, I_REF, is determined by

the ratio of the V_REFIOand an external resistor, R_SET, as stated

in Equation 4. The control amplifier allows a wide (10:1)

adjustment span of I_OUTFSover a 2 mA to 20 mA range by setting

I_REFbetween 62.5 µA and 625 µA. The wide adjustment span of

I_OUTFSprovides several application benefits. The first benefit

relates directly to the power dissipation of the AD9708, which is

proportional to I_OUTFS(refer to the POWER DISSIPATION

section). The second benefit relates to the 20 dB adjustment,

which is useful for system gain control purposes.

AD9708

I

= 20mA

OUTFS

V

= 0 TO +0.5V

OUTA

IOUTA

22

21

50⍀

IOUTB

25⍀

Figure 16. 0 V to +0.5 V Unbuffered Voltage Output

Alternatively, an amplifier could be configured as an I-V converter

thus converting IOUTA or IOUTB into a negative unipolar

AVDD

OPTIONAL

BANDLIMITING

CAPACITOR

AVDD

REFLO

COMP1

AVDD

+1.2V REF

REFIO

FS ADJ

R

V

FB

DD

50pF

1.2V

OUT1

OUT2

0.1V TO 1.2V

AD7524

V

REF

CURRENT

SOURCE

ARRAY

AD1580

AGND

R

I

=

SET

REF

AD9708

V

/R

REF SET

DB7–DB0

Figure 15. Single-Supply Gain Control Circuit

–8–

REV. B

AD9708

voltage. Figure 17 shows a buffered singled-ended output con-

figuration in which the op amp, U1, performs an I-V conversion

on the AD9708 output current. U1 provides a negative unipolar

output voltage and its full-scale output voltage is simply the

product of R_FBand I_OUTFS. The full-scale output should be set

within U1’s voltage output swing capabilities by scaling I_OUTFS

and/or R_FB. An improvement in ac distortion performance may

result with a reduced I_OUTFS, since the signal current U1 will be

required to sink and will be subsequently reduced. Note, the ac

distortion performance of this circuit at higher DAC update

rates may be limited by U1’s slewing capabilities.

over a digital supply range of 2.7 V to 5.5 V. As a result, the

digital inputs can also accommodate TTL levels when DVDD is

set to accommodate the maximum high level voltage, V_OH(MAX)

of the TTL drivers. A DVDD of 3 V to 3.3 V will typically

ensure upper compatibility of most TTL logic families.

,

DVDD

DIGITAL

INPUT

C

OPT

R

FB

Figure 18. Equivalent Digital Input

200⍀

I

= 10mA

OUTFS

AD9708

Since the AD9708 is capable of being updated up to 125 MSPS,

the quality of the clock and data input signals are important in

achieving the optimum performance. The drivers of the digital

data interface circuitry should be specified to meet the minimum

setup-and-hold times of the AD9708 as well as its required min/

max input logic level thresholds. Typically, the selection of the

slowest logic family that satisfies the above conditions will result

in the lowest data feedthrough and noise.

22

21

IOUTA

U1

V

= I

؋

R

OUT

OUTFS FB

IOUTB

200⍀

Figure 17. Unipolar Buffered Voltage Output

IOUTA and IOUTB also have a negative and positive voltage

compliance range that must be adhered to in order to achieve

optimum performance. The positive output compliance range is

slightly dependent on the full-scale output current, I_OUTFS. It

degrades slightly from its nominal 1.25 V for an I_OUTFS= 20 mA

to 1.00 V for an I_OUTFS= 2 mA. Applications requiring the

AD9708’s output (i.e., V_OUTAand/or V_OUTB) to extend up to its

output compliance range should size R_LOADaccordingly. Operation

beyond this compliance range will adversely affect the AD9708’s

linearity.

Digital signal paths should be kept short and run lengths matched

to avoid propagation delay mismatch. The insertion of a low

value resistor network (i.e., 20 Ω to 100 Ω) between the AD9708

digital inputs and driver outputs may be helpful in reducing any

overshooting and ringing at the digital inputs that contribute to

data feedthrough. For longer run lengths and high data update

rates, strip line techniques with proper termination resistors

should be considered to maintain “clean” digital inputs. Also,

operating the AD9708 with reduced logic swings and a corre-

sponding digital supply (DVDD) will also reduce data feedthrough.

The differential voltage, V_DIFF, existing between V_OUTAand

V_OUTBmay also be converted to a single-ended voltage via a

transformer or differential amplifier configuration. Refer to the

DIFFERENTIAL OUTPUT CONFIGURATION section for

more information.

The external clock driver circuitry should provide the AD9708

with a low jitter clock input meeting the min/max logic levels

while providing fast edges. Fast clock edges will help minimize

any jitter that will manifest itself as phase noise on a recon-

structed waveform. However, the clock input could also be

driven by via a sine wave, which is centered around the digital

threshold (i.e., DVDD/2), and meets the min/max logic threshold.

This may result in a slight degradation in the phase noise, which

becomes more noticeable at higher sampling rates and output

frequencies. Note, at higher sampling rates the 20% tolerance

of the digital logic threshold should be considered since it will

affect the effective clock duty cycle and subsequently cut into

the required data setup-and-hold times.

DIGITAL INPUTS

The AD9708’s digital input consists of eight data input pins and

a clock input pin. The 8-bit parallel data inputs follow standard

positive binary coding where DB7 is the most significant bit

(MSB) and DB0 is the least significant bit (LSB). The digital

interface is implemented using an edge-triggered master slave

latch. The DAC output is updated following the rising edge of

the clock as shown in Figure 1 and is designed to support a

clock rate as high as 125 MSPS. The clock can be operated at

any duty cycle that meets the specified latch pulsewidth. The

setup-and-hold times can also be varied within the clock cycle as

long as the specified minimum times are met; although the

location of these transition edges may affect digital feedthrough

and distortion performance.

SLEEP MODE OPERATION

The AD9708 has a power-down function that turns off the

output current and reduces the supply current to less than 8.5 mA

over the specified supply range of 2.7 V to 5.5 V and tempera-

ture range. This mode can be activated by applying a logic level

“1” to the SLEEP pin. This digital input also contains an active

pull-down circuit that ensures the AD9708 remains enabled if

this input is left disconnected. The SLEEP input with active

pull-down requires <40 µA of drive current.

The digital inputs are CMOS compatible with logic thresholds,

V_THRESHOLDset to approximately half the digital positive supply

(DVDD) or

V_THRESHOLD= DVDD/2 (±20%)

The power-up and power-down characteristics of the AD9708

are dependent on the value of the compensation capacitor con-

nected to COMP2 (Pin 23). With a nominal value of 0.1 µF, the

AD9708 takes less than 5 µs to power down and approximately

3.25 ms to power back up.

Figure 18 shows the equivalent digital input circuit for the data

and clock inputs. The sleep mode input is similar, except that

it contains an active pull-down circuit, thus ensuring that the

AD9708 remains enabled if this input is left disconnected. The

internal digital circuitry of the AD9708 is capable of operating

REV. B

–9–

AD9708

18

16

14

8

6

4

30

125MSPS

25

20

15

10

100MSPS

12

10

8

50MSPS

6

2

25MSPS

5MSPS

25MSPS

5MSPS

4

5

0

2

0

2

4

6

8

10 12 14 16 18 20

– mA

0.01

0.1

RATIO (f

1

0.01

0.1

RATIO (f

1

/f

)

I

/f

)

OUT CLK

OUTFS

OUT CLK

Figure 21. I_DVDDvs. Ratio

@ DVDD = 3 V

Figure 19. I_AVDDvs. I_OUTFS

Figure 20. I_DVDDvs. Ratio

@ DVDD = 5 V

FERRITE

BEADS

POWER DISSIPATION

The power dissipation, P_D, of the AD9708 is dependent on

several factors, including: (1) AVDD and DVDD, the power

supply voltages; (2) I_OUTFS, the full-scale current output; (3)

f_CLOCK, the update rate; (4) and the reconstructed digital input

waveform. The power dissipation is directly proportional to the

analog supply current, I_AVDD, and the digital supply current,

I_DVDD.I_AVDDis directly proportional to I_OUTFS, as shown in

AVDD

TTL/CMOS

LOGIC

10-22␮F

0.1␮F

100␮F

CIRCUITS

TANT.

CER.

ELECT.

ACOM

+5V OR +3V

POWER SUPPLY

Figure 19, and is insensitive to f_CLOCK

.

Conversely, I_DVDDis dependent on both the digital input wave-

form, f_CLOCK, and digital supply DVDD. Figures 20 and 21

show I_DVDDas a function of full-scale sine wave output ratios

(f_OUT/f_CLOCK) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note, how I_DVDDis reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

Figure 22. Differential LC Filter for Single +5 V or +3 V

Applications

Maintaining low noise on power supplies and ground is critical

to obtaining optimum results from the AD9708. If properly

implemented, ground planes can perform a host of functions on

high speed circuit boards: bypassing, shielding, current trans-

port, etc. In mixed signal design, the analog and digital portions

of the board should be distinct from each other, with the analog

ground plane confined to the areas covering the analog signal

traces, and the digital ground plane confined to areas covering

the digital interconnects.

APPLYING THE AD9708

Power and Grounding Considerations

In systems seeking to simultaneously achieve high speed and

high performance, the implementation and construction of the

printed circuit board design is often as important as the circuit

design. Proper RF techniques must be used in device selection

placement and routing and supply bypassing and grounding.

The evaluation board for the AD9708, which uses a four layer

PC board, serves as a good example for the above mentioned

considerations. The evaluation board provides an illustration of

the recommended printed circuit board ground, power and

signal plane layouts.

All analog ground pins of the DAC, reference and other analog

components, should be tied directly to the analog ground plane.

The two ground planes should be connected by a path 1/8 to

1/4 inch wide underneath or within 1/2 inch of the DAC to

maintain optimum performance. Care should be taken to ensure

that the ground plane is uninterrupted over crucial signal paths.

On the digital side, this includes the digital input lines running

to the DAC as well as any clock signals. On the analog side, this

includes the DAC output signal, reference signal and the supply

feeders.

Proper grounding and decoupling should be a primary objective

in any high speed system. The AD9708 features separate analog

and digital supply and ground pins to optimize the management

of analog and digital ground currents in a system. In general,

AVDD, the analog supply, should be decoupled to ACOM, the

analog common, as close to the chip as physically possible. Simi-

larly, DVDD, the digital supply, should be decoupled to DCOM

as close as physically as possible.

The use of wide runs or planes in the routing of power lines is

also recommended. This serves the dual role of providing a low

series impedance power supply to the part, as well as providing

some “free” capacitive decoupling to the appropriate ground

plane. It is essential that care be taken in the layout of signal and

power ground interconnects to avoid inducing extraneous

voltage drops in the signal ground paths. It is recommended that

all connections be short, direct and as physically close to the

package as possible in order to minimize the sharing of conduc-

tion paths between different currents. When runs exceed an inch

in length, strip line techniques with proper termination resistor

For those applications requiring a single +5 V or +3 V supply

for both the analog and digital supply, a clean analog supply

may be generated using the circuit shown in Figure 22. The

circuit consists of a differential LC filter with separate power

supply and return lines. Lower noise can be attained using low

ESR type electrolytic and tantalum capacitors.

REV. B

–10–

AD9708

500⍀

should be considered. The necessity and value of this resistor

will be dependent upon the logic family used.

AD9708

225⍀

22

21

IOUTA

For a more detailed discussion of the implementation and

construction of high speed, mixed signal printed circuit boards,

refer to Analog Devices’ application notes AN-280 and AN-333.

AD8072

IOUTB

C

OPT

500⍀

DIFFERENTIAL OUTPUT CONFIGURATIONS

25⍀

For applications requiring the optimum dynamic performance

and/or a bipolar output swing, a differential output configura-

tion is suggested. A differential output configuration may con-

sists of either an RF transformer or a differential op amp

configuration. The transformer configuration is well suited for

ac coupling applications. It provides the optimum high fre-

quency performance due to its excellent rejection of common-

mode distortion (i.e., even-order harmonics) and noise over a

wide frequency range. It also provides electrical isolation and

the ability to deliver twice the power to the load (i.e., assuming

no source termination). The differential op amp configuration is

suitable for applications requiring dc coupling, a bipolar output,

signal gain, and/or level shifting.

Figure 24. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically

determined by the resistor matching. In this circuit, the differ-

ential op amp circuit is configured to provide some additional

signal gain. The op amp must operate off a dual supply since its

output is approximately ±1.0 V. A high speed amplifier capable

of preserving the differential performance of the AD9708 while

meeting other system level objectives (i.e., cost, power) should

be selected. The op amps differential gain, its gain setting resis-

tor values and full-scale output swing capabilities should all be

considered when optimizing this circuit.

Figure 23 shows the AD9708 in a typical transformer coupled

output configuration. The center-tap on the primary side of the

transformer must be connected to ACOM to provide the necessary

dc current path for both IOUTA and IOUTB. The complemen-

tary voltages appearing at IOUTA and IOUTB (i.e., V_OUTAand

V_OUTB) swing symmetrically around ACOM and should be

maintained within the specified output compliance range of the

AD9708. A differential resistor, R_DIFF, may be inserted in

applications in which the output of the transformer is connected

to the load, R_LOAD, via a passive reconstruction filter or cable.

R_DIFFis determined by the transformer’s impedance ratio and

provides the proper source termination. Note that approxi-

The differential circuit shown in Figure 25 provides the neces-

sary level-shifting required in a single supply system. In this

case, AVDD, which is the positive analog supply for both the

AD9708 and the op amp, is also used to level-shift the differ-

ential output of the AD9762 to midsupply (i.e., AVDD/2).

500⍀

AD9708

225⍀

22

IOUTA

AD8072

225⍀

21

IOUTB

C

OPT

1k⍀

AVDD

mately half the signal power will be dissipated across R_DIFF

.

25⍀

1k⍀

MINI-CIRCUITS

T1-1T

IOUTA 22

Figure 25. Single-Supply DC Differential Coupled Circuit

R

AD9708

LOAD

AD9708 EVALUATION BOARD

General Description

IOUTB 21

OPTIONAL R

DIFF

The AD9708-EB is an evaluation board for the AD9708 8-bit

D/A converter. Careful attention to layout and circuit design,

combined with a prototyping area, allows the user to easily and

effectively evaluate the AD9708 in any application where high

resolution, high speed conversion is required.

Figure 23. Differential Output Using a Transformer

An op amp can also be used to perform a differential to single-

ended conversion as shown in Figure 24. The AD9708 is

configured with two equal load resistors, R_LOAD, of 25 Ω. The

differential voltage developed across IOUTA and IOUTB is

converted to a single-ended signal via the differential op amp

configuration. An optional capacitor can be installed across

IOUTA and IOUTB forming a real pole in a low-pass filter.

The addition of this capacitor also enhances the op amps distortion

performance by preventing the DACs high slewing output from

overloading the op amp’s input.

This board allows the user the flexibility to operate the AD9708

in various configurations. Possible output configurations include

transformer coupled, resistor terminated, inverting/noninverting

and differential amplifier outputs. The digital inputs are

designed to be driven directly from various word generators,

with the on-board option to add a resistor network for proper

load termination. Provisions are also made to operate the

AD9708 with either the internal or external reference, or to

exercise the power-down feature.

Refer to the application note AN-420 “Using the AD9760/

AD9762/AD9764-EB Evaluation Board” for a thorough

description and operating instructions for the AD9708 evalua-

tion board.

REV. B

–11–

AD9708

Figure 26. Evaluation Board Schematic

–12–

REV. B

AD9708

Figure 27. Silkscreen Layer—Top

Figure 28. Component Side PCB Layout (Layer 1)

–13–

REV. B

AD9708

Figure 29. Ground Plane PCB Layout (Layer 2)

Figure 30. Power Plane PCB Layout (Layer 3)

–14–

REV. B

AD9708

Figure 31. Solder Side PCB Layout (Layer 4)

Figure 32. Silkscreen Layer—Bottom

–15–

REV. B

AD9708

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead, 300 Mil SOIC

(R-28)

0.7125 (18.10)

0.6969 (17.70)

28

1

15

0.2992 (7.60)

0.2914 (7.40)

0.4193 (10.65)

0.3937 (10.00)

14

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

0.0098 (0.25)

؋

45؇

8؇

0؇

0.0500

(1.27)

BSC

SEATING

PLANE

0.0192 (0.49)

0.0138 (0.35)

0.0118 (0.30)

0.0040 (0.10)

0.0500 (1.27)

0.0157 (0.40)

0.0125 (0.32)

0.0091 (0.23)

28-Lead TSSOP

(RU-28)

0.386 (9.80)

0.378 (9.60)

15

14

28

1

PIN 1

0.006 (0.15)

0.002 (0.05)

0.0433

(1.10)

MAX

0.028 (0.70)

0.020 (0.50)

8°

0°

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

BSC

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

REV. B

–16–


型号：	AD9708ARUZ
厂家：	ADI
描述：	8-Bit, 100 MSPS TxDACÂ® D/A Converter 8位， 100 MSPS TxDACÂ® D / A转换器转换器数模转换器光电二极管 PC
文件：	总16页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9708ARUZ [ADI]

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