AD9712BSQ/883B [ADI]
12-Bit, 100 MSPS D/A Converters; 12位， 100 MSPS D / A转换器
| 型号： | AD9712BSQ/883B |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 100 MSPS D/A Converters |
| 文件： | 总12页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 100 MSPS
D/A Converters
a
AD9712B/AD9713B
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
100 MSPS Update Rate
ECL/ TTL Com patibility
SFDR @ 1 MHz: 70 dBc
Low Glitch Im pulse: 28 pV-s
Fast Settling: 27 ns
Low Pow er: 725 m W
1/ 2 LSB DNL (B Grade)
40 MHz Multiplying Bandw idth
AD9712B/AD9713B
LATCH
ENABLE
26
28
1
(MSB)
DIGITAL
INPUTS
14
16
I
OUT
OUT
DECODERS
AND
DRIVERS
SWITCH
NETWORK
D
1
APPLICATIONS
ATE
THRU
D
12
I
Signal Reconstruction
Arbitrary Waveform Generators
Digital Synthesizers
Signal Generators
(LSB)
11
24
REFERENCE
IN
17
18
+
R
SET
CONTROL
AMP
CONTROL
AMP OUT
INTERNAL
VOLTAGE
GENERAL D ESCRIP TIO N
–
T he AD9712B and AD9713B D/A converters are replacements
for the AD9712 and AD9713 units which offer improved ac and
dc performance. Like their predecessors, they are 12-bit, high
speed digital-to-analog converters fabricated in an advanced
oxide isolated bipolar process. T he AD9712B is an ECL-
compatible device featuring update rates of 100 MSPS mini-
mum; the T T L-compatible AD9713B will update at 80 MSPS
minimum.
REFERENCE
20
19
REFERENCE
OUT
CONTROL
AMP IN
Designed for direct digital synthesis, waveform reconstruction,
and high resolution imaging applications, both devices feature
low glitch impulse of 28 pV-s and fast settling times of 27 ns.
Both units are characterized for dynamic performance and have
excellent harmonic suppression.
T he AD9712B and AD9713B are available in 28-pin plastic
DIPs and PLCCs, with an operating temperature range of
–25°C to +85°C. Both are also available for extended tempera-
ture ranges of –55°C to +125°C in cerdips and 28-pin LCC
packages.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD9712B/AD9713B–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS [–V = –5.2 V; +V = +5 V (AD9713B only); Reference Voltage = –1.2 V;
RSET = 7.5 k⍀; V = 0 V (virtual ground); unless otherwise noted]
S
S
OUT
AD 9712B/AD 9713B
AN/AP
AD 9712B/AD 9713B
BN/BP
AD 9712B/AD 9713B AD 9712B/AD 9713B
Test
SE/SQ
TE/TQ
P aram eter (Conditions)
Tem p
Level
Min
Typ
Max
Min
Typ
Max Min Typ Max
Min Typ Max Units
RESOLUT ION
12
12
12
12
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
I
VI
I
–1.25 1.0
–2.0
+1.25 –0.75
0.5
+0.75 –1.5 1.0 +1.5
–1.0 0.5
–1.5
–1.25 1.0
–1.75
+1.0 LSB
2.0
1.5
2.0
–1.5
–1.0
–1.75
1.5
1.0
–2.0
2.0
1.5
LSB
Integral Nonlinearity
(“Best Fit” Straight Line)
–1.5
–2.0
1.0
0.75
–1.75 1.5 1.75
1.25 LSB
1.75 LSB
VI
1.75 –2.0
2.0
AD 9712B
All Grades
Typ
AD 9713B
All Grades
Typ
Test
Level
P aram eter (Conditions)
Tem p
Min
Max
Min
Max
Units
INIT IAL OFFSET ERROR
Zero-Scale Offset Error
+25°C
Full
+25°C
Full
I
VI
I
VI
V
0.5
2.5
5.0
5
0.5
2.5
5.0
5
µA
µA
%
%
µA/°C
Full-Scale Gain Error1
Offset Drift Coefficient
1.0
1.0
8
8
+25°C
0.01
0.01
REFERENCE/CONT ROL AMP
Internal Reference Voltage
+25°C
Full
Full
Full
+25°C
+25°C
I
–1.14
–1.12
–1.18
50
–1.22
–1.24
–1.14
–1.12
–1.18
50
–1.22
–1.24
V
V
VI
V
IV
V
V
Internal Reference Voltage Drift
Internal Reference Output Current
Amplifier Input Impedance
Amplifier Bandwidth
ppm/°C
µA
kΩ
–50
+500
–50
+500
50
300
50
300
kHz
REFERENCE INPUT2
Reference Input Impedance
Reference Multiplying Bandwidth3
+25°C
+25°C
V
V
3
40
3
40
kΩ
MHz
DYNAMIC PERFORMANCE
Full-Scale Output Current4
Output Compliance Range
Output Resistance
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
V
20.48
20.48
mA
V
kΩ
pF
MSPS
ns
ns
pV-s
ns
ns
IV
IV
V
IV
V
V
V
V
V
–1.2
2.0
+2
3.0
–1.2
2.0
+2
3.0
2.5
15
110
27
6
28
2
2
2.5
15
100
27
7
28
2
2
Output Capacitance
Output Update Rate5
Output Settling T ime (tST
100
80
6
)
7
Output Propagation Delay (tPD
Glitch Impulse8
)
Output Rise T ime9
Output Fall T ime9
DIGIT AL INPUT S
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup T ime (tS)10
Full
Full
Full
Full
+25°C
+25°C
Full
+25°C
Full
VI
VI
VI
VI
V
IV
IV
IV
IV
IV
–1.0
–0.8
–1.7
2.0
V
V
–1.5
20
10
0.8
20
600
µA
µA
pF
ns
ns
ns
ns
ns
ns
3
–0.3
3
–0.3
0.5
0.8
1.8
2.0
2.5
2.8
0.5
0.8
1.8
2.0
2.5
2.8
Input Hold T ime (tH)11
1.2
1.7
1.2
1.7
Latch Pulse Width (tLPW) (LOW)
(T ransparent)
+25°C
Full
AC LINEARIT Y12
Spurious-Free Dynamic Range (SFDR)
1.23 MHz; 10 MSPS; 2 MHz Span
5.055 MHz; 20 MSPS; 2 MHz Span
10.1 MHz; 50 MSPS; 2 MHz Span
16 MHz; 40 MSPS; 10 MHz Span
+25°C
+25°C
+25°C
+25°C
V
V
V
V
70
72
68
68
70
72
68
68
dB
dB
dB
dB
–2–
REV. B
AD9712B/AD9713B
AD 9712B
All Grades
Typ
AD 9713B
All Grades
Test
Level
P aram eter (Conditions)
Tem p
Min
Max
Min
Typ
Max
Units
POWER SUPPLY13
Positive Supply Current (+5.0 V)
+25°C
Full
+25°C
Full
+25°C
+25°C
I
VI
I
VI
V
I
6
12
14
184
188
mA
mA
mA
mA
mW
µA/V
Negative Supply Current (–5.2 V)14
140
178
183
145
Nominal Power Dissipation
728
30
784
30
Power Supply Rejection Radio (PSRR)15
100
100
NOT ES
1Measured as error in ratio of full-scale current to current through R SET (160 µA nominal); ratio is nominally 128.
2Full-scale variations among devices are higher when driving REFERENCE INPUT directly.
3Frequency at which the gain is flat ±0.5 dB; RL = 50 Ω; 50% modulation at midscale.
4Based on IFS = 128 (VREF/RSET ) when using internal amplifier.
5Data registered into DAC accurately at this rate; does not imply settling to 12-bit accuracy.
6Measured as voltage settling at midscale transition to ±0.024%, RL = 50 Ω.
7Measured as the time between the 50% point of the falling edge of LAT CH ENABLE and the point where the output signal has left a 1 LSB error band
around its previous value.
8Peak glitch impulse is measured as the largest area under a single positive or negative transient.
9Measured with RL = 50 Ω and DAC operating in latched mode.
10Data must remain stable for specified time prior to falling edge of LAT CH ENABLE signal.
11Data must remain stable for specified time after rising edge of LAT CH ENABLE signal.
12SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is
centered at the fundamental frequency and covers the indicated span.
13Supply voltages should remain stable within ±5% for normal operation.
14108 mA typ on Digital –VS, 37 mA typ on Analog –VS.
15Measured at ±5% of +VS (AD9713B only) and –VS (AD9712B or AD9713B) using external reference.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
Positive Supply Voltage (+VS) (AD9713B Only) . . . . . . . +6 V
Tem perature
Range
P ackage
D escription
P ackage
O ption
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . –7 V
Analog-to-Digital Ground Voltage Differential . . . . . . . . 0.5 V
Digital Input Voltages (D1–D12, LAT CH ENABLE)
Model
AD9712BAN
AD9712BBN
AD9712BAP
AD9712BBP
AD9712BSQ/883B
AD9712BSE/883B
AD9712BT Q/883B
AD9712BT E/883B
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
28-Pin PDIP
28-Pin PDIP
28-Pin PLCC
28-Pin PLCC
28-Pin Cerdip
28-Pin LCC
28-Pin Cerdip
28-Pin LCC
N-28
N-28
AD9712B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to –VS
AD9713B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Internal Reference Output Current . . . . . . . . . . . . . . . . 500 µA
Control Amplifier Input Voltage Range . . . . . . . . . 0 V to –4 V
Control Amplifier Output Current . . . . . . . . . . . . . . . ±2.5 mA
Reference Input Voltage Range (VREF) . . . . . . . . . . . 0 V to –VS
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating T emperature Range
AD9712B/AD9713BAN/AP/BN/BP . . . . . . . –25°C to +85°C
AD9712B/AD9713BSE/SQ/T E/T Q . . . . . . –55°C to +125°C
Maximum Junction T emperature2
AD9712B/AD9713BAN/AP/BN/BP . . . . . . . . . . . . . +150°C
AD9712B/AD9713BSE/SQ/T E/T Q . . . . . . . . . . . . . +175°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
P-28A
P-28A
Q-28
E-28A
Q-28
E-28A
AD9713BAN
AD9713BBN
AD9713BAP
AD9713BBP
AD9713BSQ/883B
AD9713BSE/883B
AD9713BT Q/883B
AD9713BT E/883B
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
28-Pin PDIP
28-Pin PDIP
28-Pin PLCC
28-Pin PLCC
28-Pin Cerdip
28-Pin LCC
28-Pin Cerdip
28-Pin LCC
N-28
N-28
P-28A
P-28A
Q-28
E-28A
Q-28
E-28A
NOT ES
EXP LANATIO N O F TEST LEVELS
Test Level
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2T ypical thermal impedances with parts soldered in place: 28-pin plastic DIP:
θJA = 37°C/W, θJC = 10°C/W; 28-pin PLCC: θJA = 44°C/W, θJC = 14°C/W;
Cerdip: θJA = 32°C/W, θJC = 10°C/W; LCC: θJA = 41°C/W, θJC = 13°C/W. No air
flow.
I
II
–
–
100% production tested.
100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V
–
Parameter is a typical value only.
VI – All devices are 100% tested at +25°C. 100% production
tested at temperature extremes for extended tempera-
ture devices; sample tested at temperature extremes for
commercial/industrial devices.
REV. B
–3–
AD9712B/AD9713B
P IN D ESCRIP TIO NS
P in # Nam e
Function
1–10
11
D2–D11
T en bits of twelve-bit digital input word.
Least Significant Bit (LSB) of digital input word.
Input Coding vs. Cur r ent O utput
D12 (LSB)
Input Code D1–D12
IOUT (mA)
IOUT (mA)
1111111111
0000000000
–20.475
0
0
–20.475
12
13
DIGIT AL –VS
One of two negative digital supply pins; nominally –5.2 V.
ANALOG RET URN
Analog ground return. T his point and the reference side of the DAC load resistors should be
connected to the same potential (nominally ground).
14
15
16
17
IOUT
Analog current output; full-scale output occurs with digital inputs at all “1.”
One of two negative analog supply pins; nominally –5.2 V.
ANALOG –VS
IOUT
Complementary analog current output; zero scale output occurs with digital inputs at all “1.”
REFERENCE IN
Normally connected to CONT ROL AMP OUT (Pin 18). Direct line to DAC current source
network. Voltage changes at this point have a direct effect on the full-scale output value of
unit. Full-scale current output = 128 (Reference voltage/RSET ) when using internal amplifier.
18
CONT ROL AMP OUT
Normally connected to REFERENCE INPUT (Pin 17). Output of internal control amplifier,
which provides a temperature-compensated drive level to the current switch network.
19
20
CONT ROL AMP IN
REFERENCE OUT
Normally connected to REFERENCE OUT (Pin 20) if not connected to external reference.
Normally connected to CONT ROL AMP IN (Pin 19). Internal voltage reference, nominally
–1.18 V.
21
22
23
DIGIT AL –VS
One of two negative digital supply pins; nominally –5.2 V.
Ground return for the internal voltage reference and amplifier.
REFERENCE GROUND
DIGIT AL +VS
Positive digital supply pin, used only on the AD9713B; nominally +5 V. No connection to this
pin on AD9712B.
24
RSET
Connection for external resistance reference. Full-scale current out = 128 (Reference voltage/
R
SET) when using internal amplifier. Nominally 7.5 kΩ.
25
26
27
28
ANALOG –VS
One of two negative analog supply pins; nominally –5.2 V.
T ransparent latch control line. Register is transparent when LAT CH ENABLE is LOW.
Digital ground return.
LAT CH ENABLE
DIGIT AL GROUND
D1 (MSB)
Most Significant Bit (MSB) of digital input word.
P IN CO NFIGURATIO NS
P LCC/LCC
D IP
D
(MSB0)
D
D
1
28
27
26
25
24
23
22
21
20
2
3
1
3
2
3
DIGITAL GROUND
LATCH ENABLE
4
3
2
1
28 27 26
D
4
D
D
D
D
4
5
5
6
ANALOG –V
S
ANALOG –V
S
5
6
25
24
23
22
21
20
19
D
D
D
D
6
7
R
SET
R
SET
AD9712B
AD9713B
AD9712B
AD9713B
6
DIGITAL +V
S
7
DIGITAL +V
7
S
8
9
REFERENCE
GROUND
REFERENCE GROUND
7
8
8
TOP VIEW
(Not to Scale)
TOP VIEW
(Not to Scale)
D
9
8
DIGITAL –V
S
DIGITAL –V
S
9
D
D
10
11
REFERENCE
OUT
9
10
11
D
D
REFERENCE OUT
CONTROL AMP IN
CONTROL AMP OUT
10
CONTROL
AMP IN
D
(LSB)
10
11
12
19
18
12
11
D
(LSB)
12
12 13 14
16 17 18
15
DIGITAL –V
17 REFERENCE IN
S
I
ANALOG RETURN 13
14
16
15
OUT
I
ANALOG –V
OUT
S
–4–
REV. B
AD9712B/AD9713B
D IE LAYO UT AND METALIZATIO N INFO RMATIO N
Die Dimensions . . . . . . . . . . . . . . . . . 220 × 196 × 15 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
D igital Inputs/Tim ing
T he AD9712B employs single-ended ECL-compatible inputs
for data inputs D1–D12 and LAT CH ENABLE. T he internal
ECL midpoint reference is designed to match 10K ECL device
thresholds. On the AD9713B, a T T L translator is added at each
input; with this exception, the AD9712B and AD9713B are
identical.
In the Decoder/Driver section, the four MSBs (D1–D4) are
decoded to 15 “thermometer code” lines. An equalizing delay is
included for the eight Least Significant Bits (LSBs) and
LAT CH ENABLE. T his delay minimizes data skew, and data
setup and hold times at the latch inputs; this is important when
operating the latches in the transparent mode. Without the
delay, skew caused by the decoding circuits would degrade
glitch impulse.
T he latches operate in their transparent mode when LAT CH
ENABLE (Pin 26) is at logic level “0.” T he latches should be
used to synchronize data to the current switches by applying a
narrow LAT CH ENABLE pulse with proper data setup and
hold times as shown in the T iming Diagram. An external latch
at each data input, clocked out of phase with the Latch Enable,
operates the AD9712B/AD9713B in a master slave (edge-
triggered) mode. T his is the optimum way to operate the DAC
because data is always stable at the DAC input. An external
latch eases timing constraints when using the converter.
Although the AD9712B/AD9713B chip is designed to provide
isolation from digital inputs to the outputs, some coupling of
digital transitions is inevitable, especially with T T L or CMOS
inputs applied to the AD9713B. Digital feedthrough can be re-
duced by forming a low-pass filter using a (200 Ω) series resistor
in series with the capacitance of each digital input; this rolls off
the slew rate of the digital inputs.
TH EO RY AND AP P LICATIO NS
T he AD9712B and AD9713B high speed digital-to-analog
converters utilize Most Significant Bit (MSB) decoding and
segmentation techniques to reduce glitch impulse and main-
tain 12-bit linearity without trimming.
Refer ences
As shown in the functional block diagram, the internal bandgap
reference, control amplifier, and reference input are pinned out
for maximum user flexibility when setting the reference.
As shown in the functional block diagram, the design is based
on four main subsections: the Decoder/Driver circuits, the
T ransparent Latches, the Switch Network, and the Control Am-
plifier. An internal bandgap reference is also included to allow
operation with a minimum of external components.
When using the internal reference, REFERENCE OUT (Pin 20)
should be connected to CONT ROL AMP IN (Pin 19). CON-
T ROL AMP OUT (Pin 18) should be connected to REFER-
ENCE IN (Pin 17) through a 20 Ω resistor. A 0.1 µF ceramic
capacitor from Pin 17 to –VS (Pin 15) improves settling by
decoupling switching noise from the current sink base line. A
reference current cell provides feedback to the control amp by
sinking current through RSET (Pin 24).
tLPW
LATCH
ENABLE
LATCH ENABLE
ERROR
BAND
tS
tH
OUTPUT
ERROR
VALID DATA
DATA INPUTS
OUTPUT
tPD
tST
tPD
t H
– INPUT HOLD TIME
tST
tLPW
– LATCH PULSE WIDTH
– OUTPUT SETTLING TIME
tS
tPD
– INPUT SETUP TIME
– OUTPUT PROPAGATION DELAY
Tim ing Diagram
REV. B
–5–
AD9712B/AD9713B
Full-scale output current is determined by CONT ROL AMP
IN and RSET according to the equation:
T he REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. T he analog signal for this
mode of operation must have a signal swing in the range of
–3.75 V to –4.25 V. T his can be implemented by capacitively
coupling into REFERENCE IN a signal with a dc bias of –3.75 V
to –4.25 V, as shown in Figure 3; or by driving REFERENCE
IN with a low impedance op amp whose signal swing is limited
to the stated range.
IOUT (FS) = (CONTROL AMP IN/RSET) × 128
T he internal reference is nominally –1.18 V with a tolerance of
±3.5% and typical drift over temperature of 50 ppm/°C. If
greater accuracy or better temperature stability is required, an
external reference can be utilized. T he AD589 reference shown
in Figure 1 features ±10 ppm/°C drift over temperatures from
0°C to +70°C.
O utputs
As indicated earlier, D1–D4 (four MSBs) are decoded and drive
15 discrete current sinks. D5 and D6 are binarily weighted; and
D7–D12 are applied to the R-2R network. T his segmented archi-
tecture reduces frequency domain errors due to glitch impulse.
AD9712B
AD9713B
+
AD589
AD9712B
AD9713B
–
CONTROL
AMP IN
19
REFERENCE
R
11k
1
IN
17
~
–
~
–
–4V
–V
S
Figure 1. Use of AD589 as External Reference
–V
–V
S
S
T wo modes of multiplying operation are possible with the
AD9712B/AD9713B. Signals with small signal bandwidths up
to 300 kHz and input swings of 100 mV, or dc signals from
–0.6 V to –1.2 V can be applied to the CONT ROL AMP input
as shown in Figure 2. Because the control amplifier is internally
compensated, the 0.1 µF capacitor at Pin 17 can be reduced to
0.01 µF to maximize the multiplying bandwidth. However, it
should be noted that settling time for changes to the digital in-
puts will be degraded.
Figure 3. Wideband Multiplying Circuit
T he Switch Network provides complementary current outputs
IOUT and IOUT . T hese current outputs are based on statistical
current source matching which provides 12-bit linearity without
trim. Current is steered to either IOUT or IOUT in proportion to
the digital input code. T he sum of the two currents is always
equal to the full-scale output current minus one LSB.
T he current output can be converted to a voltage by resistive
loading as shown in Figure 4. Both IOUT and IOUT should be
loaded equally for best overall performance. T he voltage which
is developed is the product of the output current and the value
of the load resistor.
R
SET
24
19
R
SET
CONTROL
AMP IN
–0.6V TO –1.2V
300 kHz MAX
R
AD9712B
AD9713B
T
CONTROL
AMP OUT
18
17
18
REFERENCE
IN
Figure 2. Low Frequency Multiplying Circuit
–6–
REV. B
AD9712B/AD9713B
DAC current across feedback resistor RFB determines the
AD9617 output swing. A current divider formed by RL and RFF
limits the current used in the I-to-V conversion, and provides an
output voltage swing within the specifications of the AD9617.
Current through R2 provides dc offset at the output of the
AD9617. Adjusting the value of R1 adjusts the value of offset
current. T his offset current is based on the reference of the
AD9712B/AD9713B, to avoid coupling noise into the output
signal.
0.1µF
0.01µF
–5.2V
0.01µF
0.1µF
12,21
DIGITAL –V
15,25
ANALOG –V
S
S
0.1µF
28
1
D
1 (MSB)
T he resistor values in Figure 5 provide a 4.096 V swing, cen-
tered at ground, at the output of the AD9617 amplifier.
REFERENCE
IN
17
D
2
20Ω
P ower and Gr ounding
2
3
4
5
6
D
D
D
3
CONTROL
AMP OUT
18
20
19
Maintaining low noise on power supplies and ground is critical
for obtaining optimum results with the AD9712B or AD9713B.
DACs are most often used in circuits which are predominantly
digital. T o preserve 12-bit performance, especially at conversion
speeds up to 100 MSPS, special precautions are necessary for
power supplies and grounding.
4
5
REFERENCE
OUT
D
6
CONTROL
AMP IN
ECL
DRIVE
LOGIC
D
7
24
16
R
SET
7
8
D
8
Ideally, the DAC should have a separate analog ground plane.
All ground pins of the DAC, as well as reference and analog
output components, should be tied directly to this analog
ground plane. T he DAC’s ground plane should be connected to
the system ground plane at a single point.
I
OUT
D
9
9
D
10
R
L
L
AD9712B
AD9713B
10
11
26
D
11
V
=
OUT
x R
I
D
12
(LSB)
R
FS
L
Ferrite beads such as the Stackpole 57-1392 or Amidon
FB-43B-101, along with high frequency, low-inductance decou-
pling capacitors, should be used for the supply connections to
isolate digital switching currents from the DAC supply pins.
Separate isolation networks for the digital and analog supply
connections will further reduce supply noise coupling to the
output.
14
I
LATCH ENABLE
OUT
ANALOG REFERENCE DIGITAL
RETURN
GROUND GROUND
22 27
13
SYSTEM
GROUND
Figure 4. Typical Resistive Load Connection
Molded socket assemblies should be avoided even when
prototyping circuits with the AD9712B or AD9713B. When
the DAC cannot be directly soldered into the board, individual
pin sockets such as AMP # 6-330808-0 (knock-out end), or
# 60330808-3 (open end) should be used. T hese have much
less effect on inter-lead capacitance than do molded assemblies.
An operational amplifier can also be used to perform the I to V
conversion of the DAC output. Figure 5 shows an example of a
circuit which uses the AD9617, a high speed, current feedback
amplifier.
10k
D D S Applications
Numerically controlled oscillators (NCOs) are digital devices
which generate samples of a sine wave. When the NCO is com-
bined with a high performance D/A converter (DAC), the com-
bination system is referred to as a Direct Digital Synthesizer
(DDS).
10k
+
1/2 AD708
200
–
1/2 AD708
–
R
1
+
T he digital samples generated by the NCO are reconstructed by
the DAC and the resulting sine wave is usable in any system
which requires a stable, spectrally pure, frequency-agile refer-
ence. T he DAC is often the limiting factor in DDS applications,
since it is the only analog function in the circuit. T he AD9712B/
AD9713B D/A converters offer the highest level of performance
available for DDS applications.
100
R
2
I
OS
20
19
400
REF CONTROL
OUT AMP IN
25
R
I
FS
V
OUT
FF
R
FB
±2.048V
14
I
OUT
–
AD9617
25
R
AD9712B
AD9713B
L
+
DC linearity errors of a DAC are the dominant effect in low-
frequency applications and can affect both noise and harmonic
content in the output waveform. Differential Nonlinearity
(DNL) errors determine the quantization error between adja-
cent codes, while Integral Nonlinearity (INL) is a measure of
how closely the overall transfer function of the DAC compares
with an ideal device. T ogether, these errors establish the limits
of phase and amplitude accuracy in the output waveform.
12.5
16
I
OUT
Figure 5. I/VConversion Using Current Feedback
REV. B
–7–
AD9712B/AD9713B
SYSTEM
CLOCK
LATCH
ENABLE
NUMERICALLY-CONTROLLED OSCILLATOR
D
1
AD9712B
AD9713B
OUTPUT
TTL
REGISTER
TUNING 32
WORD
14
12
12
PHASE
ACCUMULATOR
PHASE-TO-AMPLITUDE
CONVERSION
SINE DATA
D/A CONVERTER
D
12
Figure 6. Direct Digital Synthesizer Block Diagram
When the analog frequency (fA) is exactly fC/N and N is an even
integer, the DDS continually uses a small subset of the available
DAC codes. T he DNL of the converter is effectively the DNL
error of the codes used, and is typically worse than the error
measured against all available DAC codes. T his increase in
DNL is translated into higher harmonic and noise levels at the
output.
100
90
5mV/div
Glitch impulse, often considered a figure of merit in DDS appli-
cations, is simply the initial transient response of the DAC as it
moves between two output levels. T his nonlinearity is com-
monly associated with external data skew, but this effect is mini-
mized by using the on-board registers of the AD9712B/AD9713B
converters (see Digital Inputs/T iming section). T he majority of
the glitch impulse, shown below, is produced as the current in
the R-2R ladder network settles, and is fairly constant over the
full-scale range of the DAC. T he fast transients which form the
glitch impulse appear as high-frequency spurs in the output
spectrum.
10
0%
5ns/div
Figure 7. AD9712B/AD9713B Glitch Im pulse
200mV/div
100
90
While it is difficult to predict the effects of glitch on the output
waveform, slew rate limitations translate directly into harmonics.
T his makes slew rate the dominant effect in ac linearity of the
DAC. Applications in which the ratio of analog frequency (fA)
to clock frequency (fC) is relatively high will benefit from the
high slew rate and low output capacitance of the AD9712B/
AD9713B devices.
10
0%
Another concern in DDS applications is the presence of aliased
harmonics in the output spectrum. Aliased harmonics appear as
spurs in the output spectrum at frequencies which are deter-
mined by:
1ns/div
Figure 8. Rise and Fall Characteristics
MfA ± NfC
where M and N are integers.
T he effects of these spurs are most easily observed in applica-
tions where fA is nearly equal to an integer fraction of the clock
rate. T his condition causes the aliased harmonics to fold near
the fundamental output frequency (see Performance Curves.)
–8–
REV. B
AD9712B/AD9713B
Figure 9a.
Figure 9b.
Figure 9c.
Figure 9d.
Figure 9e.
Figure 9f.
Figure 9. Typical Spectral Perform ance
REV. B
–9–
AD9712B/AD9713B
Figure 10c.
Figure 10a.
Figure 10d.
Figure 10b.
Figure 10e.
Figure 10. Typical Spectral Perform ance
–10–
REV. B
AD9712B/AD9713B
+5V
10 kΩ
CONTROL
AMP IN
19
TTL
IN
ECL V
MID
ECL
IN
–5.2 V
–5.2 V
TTL Input Buffer
ECL Input Buffer
Control Am plifier Input
±
24
R
SET
REFERENCE
20
OUT
V
BIAS
CONTROL
AMP OUT
18
+
CONTROL
AMP
18
17
CONTROL
19
AMP IN
–
CONTROL
AMP OUT
REFERENCE
IN
–5.2 V
–5.2 V
Control Am p Output
Full-Scale Current Control Loop
ANALOG
RETURN
13
14
138 CURRENT SOURCES
2R
R
2R
2R
2R
2R
R
R
R
R
R
R
REFERENCE
IN
I
17
OUT
or
16
I
OUT
D
D
D
9
D
D
D
7
D
D
–
6
8
1
11
10
12
–5.2 V
Reference Input
R-2R DAC (for 6 LSBs)
ANALOG
RETURN
I
I
OUT
16
OUT
14
13
16pF
16pF
2.5kΩ
2.5kΩ
REFERENCE
OUT
20
–5.2 V
–V
S
Reference Output
Output Circuit
Figure 11. Equivalent Circuits
REV. B
–11–
AD9712B/AD9713B
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-P in P lastic D IP (Suffix N)
28-P in P lastic Leaded Chip Carrier (Suffix P )
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
28
1
15
14
0.550 (13.97)
0.530 (13.46)
4
26
25
5
PIN 1
0.625 (15.8)
0.050
(1.27)
BSC
IDENTIFIER
1.565 (39.70)
1.380 (35.10)
0.600 (15.24)
0.060 (1.52)
0.015 (0.38)
0.430 (10.92)
0.390 (9.91)
0.250 (6.35)
MAX
0.140
(3.56)
MIN
0.015 (0.381)
0.008 (0.204)
0.021 (0.53)
0.013 (0.33)
0.032 (0.81)
11
19
0.70 (1.77)
MAX
0.026 (0.66)
0.100 (2.54)
BSC
0.022 (0.558)
0.014 (0.356)
12
18
0.025 (0.63)
0.015 (0.38)
0.456 (11.58)
0.450 (11.43)
0.040 (1.01)
0.025 (0.64)
0.110 (2.79)
0.085 (2.16)
0.495 (12.57)
0.485 (12.32)
0.180 (4.57)
0.165 (4.19)
28-P in Cerdip (Suffix Q)
28-P in LCC P ackage (Suffix E)
1.490 (37.84) MAX
15
28
0.075
(1.91)
REF
0.055 (1.40)
0.045 (1.14)
0.610 (15.49)
0.500 (12.70)
27
28
1
2
3
4
26
0.028 (0.71)
0.022 (0.56)
1
25
5
14
0.620 (15.74)
0.590 (14.93)
24
23
22
21
20
19
6
GLASS SEALANT
0.22
(5.59)
MAX
7
8
0.018 (0.45)
BOTTOM VIEW
0.008 (0.20)
0.050 (1.27)
15
0
9
0.026 (0.660) 0.110 (2.79) 0.07 (1.78)
0.125
(3.175)
MIN
0.014 (0.356)
0.03 (0.76)
10
11
0.098 (2.45)
18
17
16
15 14
13
12
0.458 (11.63)
0.442 (11.23)
0.100 (2.54)
0.064 (1.63)
–12–
REV. B
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