AD9714_18 [ADI]
Digital-to-Analog Converters;
| 型号： | AD9714_18 |
| 厂家： | 
ADI |
| 描述： | Digital-to-Analog Converters |
| 文件： | 总80页 (文件大小：2985K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, Low Power, 8-/10-/12-/14-Bit
TxDACDigital-to-Analog Converters
Data Sheet
AD9714/AD9715/AD9716/AD9717
FEATURES
GENERAL DESCRIPTION
Power dissipation @ 3.3 V, 2 mA output
37 mW @ 10 MSPS
The AD9714/AD9715/AD9716/AD9717 are pin-compatible,
dual, 8-/10-/12-/14-bit, low power digital-to-analog converters
(DACs) that provide a sample rate of 125 MSPS. These TxDAC®
converters are optimized for the transmit signal path of commu-
nication systems. All the devices share the same interface, package,
and pinout, providing an upward or downward component
selection path based on performance, resolution, and cost.
86 mW @ 125 MSPS
Sleep mode: <3 mW @ 3.3 V
Supply voltage: 1.8 V to 3.3 V
SFDR to Nyquist
84 dBc @ 1 MHz output
75 dBc @ 10 MHz output
The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and
dc performance and support update rates up to 125 MSPS.
AD9717 NSD @ 1 MHz output, 125 MSPS, 2 mA: −151 dBc/Hz
Differential current outputs: 1 mA to 4 mA
2 on-chip auxiliary DACs
The flexible power supply operating range of 1.8 V to 3.3 V and
low power dissipation of the AD9714/AD9715/AD9716/AD9717
make them well-suited for portable and low power applications.
CMOS inputs with single-port operation
Output common mode: adjustable 0 V to 1.2 V
Small footprint 40-lead LFCSP RoHS-compliant package
PRODUCT HIGHLIGHTS
APPLICATIONS
1. Low Power.
DACs operate on a single 1.8 V to 3.3 V supply; total power
consumption reduces to 35 mW at 125 MSPS with a 1.8 V
supply. Sleep and power-down modes are provided for low
power idle periods.
Wireless infrastructures
Picocell, femtocell base stations
Medical instrumentation
Ultrasound transducer excitation
Portable instrumentation
2. CMOS Clock Input.
High speed, single-ended CMOS clock input supports a
125 MSPS conversion rate.
Signal generators, arbitrary waveform generators
3. Easy Interfacing to Other Components.
Adjustable output common mode from 0 V to 1.2 V allows
easy interfacing to other components that accept common-
mode levels greater than 0 V.
Rev. B
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9714/AD9715/AD9716/AD9717
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Estimating the Overall DAC Pipeline Delay........................... 42
Reference Operation .................................................................. 43
Reference Control Amplifier .................................................... 43
DAC Transfer Function............................................................. 44
Analog Output............................................................................ 44
Self-Calibration........................................................................... 45
Coarse Gain Adjustment........................................................... 46
Using the Internal Termination Resistors............................... 47
Applications Information .............................................................. 48
Output Configurations.............................................................. 48
Differential Coupling Using a Transformer ............................... 48
Single-Ended Buffered Output Using an Op Amp................ 48
Differential Buffered Output Using an Op Amp ................... 49
Auxiliary DACs........................................................................... 49
DAC-to-Modulator Interfacing................................................ 50
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 7
AC Specifications.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 31
Theory of Operation ...................................................................... 32
Serial Peripheral Interface (SPI) ................................................... 33
General Operation of the Serial Interface............................... 33
Instruction Byte .......................................................................... 33
Serial Interface Port Pin Descriptions ..................................... 33
MSB/LSB Transfers..................................................................... 34
Serial Port Operation ................................................................. 34
Pin Mode ..................................................................................... 34
SPI Register Map............................................................................. 35
SPI Register Descriptions .............................................................. 36
Digital Interface Operation ........................................................... 40
Digital Data Latching and Retimer Block............................... 41
Correcting for Nonideal Performance of Quadrature
Modulators on the IF-to-RF Conversion ................................ 50
I/Q-Channel Gain Matching .................................................... 50
LO Feedthrough Compensation .............................................. 51
Results of Gain and Offset Correction.................................... 51
Modifying the Evaluation Board to Use the ADL5370 On-
Board Quadrature Modulator................................................... 52
Evaluation Board Shematics and Artwork.................................. 53
Schematics................................................................................... 53
Silkscreens ................................................................................... 61
Bill of Materials............................................................................... 76
Outline Dimensions....................................................................... 79
Ordering Guide .......................................................................... 79
Rev. B | Page 2 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
REVISION HISTORY
1/2018—Rev. A to Rev. B
Changes to Table 13 ........................................................................36
Changes to Table 14 ........................................................................37
Changes to Digital Interface Operation Section and Figure 89 to
Figure 93...........................................................................................40
Changes to Digital Data Latching and Retimer Block Section,
Figure 94, and Retimer Section.....................................................41
Changes to Estimating the Overall DAC Pipeline Delay
Changes to Figure 94 ......................................................................41
Changes to Estimating the Overall DAC Pipeline Section........42
Changes to Ordering Guide...........................................................79
3/2009—Rev. 0 to Rev. A
Changes to Figure 1...........................................................................4
Changed DVDD = 3.3 V to DVDD = 1.8 V,
Section ..............................................................................................42
Added Reference Operation Section, Figure 96,
Table 1 Conditions ............................................................................5
Changes to Table 1 ............................................................................5
Changed DVDD = 3.3 V to DVDD = 1.8 V,
Recommendations When Using an External Reference Section,
and Reference Control Amplifier Section....................................43
Added Table 17; Renumbered Sequentially.................................43
Added DAC Transfer Function Section and Analog Output
Section ..............................................................................................44
Changes to Figure 99 and Figure 100...........................................46
Changes to Auxiliary DACs Section and Figure 107..................49
Changes to DAC-to-Modulator Interfacing Section and
Table 2 Conditions ............................................................................7
Changed DVDD = 3.3 V to DVDD = 1.8 V, and DVDDIO = 1.8 V
to DVDDIO = 3.3 V, Table 3 Conditions .......................................8
Changed DVDD = 3.3 V to DVDD = 1.8 V, CVDD = 3.3 V to
CVDD = 1.8 V, Table 4 Conditions.................................................8
Changes to Table 5 and Table 6 .......................................................9
Changes to Figure 2 and Table 7 ...................................................10
Changes to Figure 3 and Table 8 ...................................................12
Changes to Figure 4 and Table 9 ...................................................14
Changes to Table 10 ........................................................................16
Changes to Typical Performance Characteristics Section .........18
Changes to Figure 84 and Theory of Operation Section ...........32
Added Figure 85 to Figure 88; Renumbered Sequentially.........34
Changes to Pin Mode Section........................................................35
Figure 108.........................................................................................49
Changes to Figure 108 and Figure 109.........................................50
Added Evaluation Board Schematics and Artwork Section, and
Figure 112 to Figure 134.................................................................53
Added Bill of Materials Section and Table 18 .............................76
8/2008—Revision 0: Initial Version
Rev. B | Page 3 of 80
AD9714/AD9715/AD9716/AD9717
FUNCTIONAL BLOCK DIAGRAM
Data Sheet
AD9717
1V
SPI
INTERFACE
DB11
QR
IR
SET
SET
16kΩ
16kΩ
IR
CML
1kΩ TO
250Ω
DB10
RLIN
500Ω
500Ω
10kΩ
DB9
DB8
IOUTN
IOUTP
I
I DAC
REF
100µA
BAND
GAP
RLIP
AUX1DAC
AUX2DAC
DVDDIO
1 INTO 2
AVDD
AVSS
RLQP
INTERLEAVED
DATA
INTERFACE
I DATA
DVSS
500Ω
500Ω
DVDD
DB7
1.8V
LDO
QOUTP
QOUTN
Q DATA
Q DAC
RLQN
CLOCK
DIST
DB6
QR
CML
1kΩ TO
250Ω
DB5
Figure 1.
Rev. B | Page 4 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 1.
AD9714
AD9715
Typ
AD9716
Typ
AD9717
Typ
Parameter
Min
Typ
Max
Min
Max
Min
Max
Min
Max
Unit
RESOLUTION
8
10
12
14
Bits
ACCURACY, AVDD = DVDDIO =
CVDD = 3.3 V
Differential Nonlinearity (DNL)
Precalibration
0.02
0.08
0.01
0.4
0.2
1.7
1.0
LSB
LSB
Postcalibration
0.003
Integral Nonlinearity (INL)
Precalibration
0.025
0.01
0.13
0.05
0.4
0.3
1.8
1.3
LSB
LSB
Postcalibration
ACCURACY, AVDD = DVDDIO =
CVDD = 1.8 V
Differential Nonlinearity (DNL)
Precalibration
0.02
0.08
0.01
0.4
0.2
1.2
1.0
LSB
LSB
Postcalibration
0.005
Integral Nonlinearity (INL)
Precalibration
0.025
0.02
0.12
0.05
0.4
1.5
1.1
LSB
LSB
Postcalibration
0.25
MAIN DAC OUTPUTS
Offset Error
−1
−2
0
+1
+2
−1
−2
0
+1
+2
−1
−2
0
+1
+2
−1
−2
0
+1
+2
mV
Gain Error
Internal Reference
Full-Scale Output Current1
AVDD = 3.3 V
% of FSR
1
2
4
1
2
4
1
2
4
1
2
4
mA
mA
V
AVDD = 1.8 V
1
2
2.5
+1.2
1
2
2.5
+1.2
1
2
2.5
+1.2
1
2
2.5
+1.2
Output Compliance Range
Output Resistance
Crosstalk, Q DAC to I DAC
fOUT = 30 MHz
−0.5
0
−0.5
0
−0.5
0
−0.5
0
200
200
200
200
MΩ
97
78
97
78
97
78
97
78
dB
dB
fOUT = 60 MHz
MAIN DAC TEMPERATURE DRIFT
Offset
0
0
0
0
ppm/°C
ppm/°C
ppm/°C
Gain
40
25
40
25
40
25
40
25
Reference Voltage
AUXDAC OUTPUTS
Resolution
10
10
10
10
Bits
µA
Full-Scale Output Current
(Current Sourcing Mode)
125
125
125
125
Voltage Output Mode
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
VSS
VSS
VDD
V
V
Output Compliance Range
(Sourcing 1 mA)
VDD
0.25
−
VDD
0.25
−
VDD
0.25
−
VDD −
0.25
Output Compliance Range
(Sinking 1 mA)
VSS +
0.25
VDD
VSS +
0.25
VDD
VSS +
0.25
VDD
VSS +
0.25
VDD
V
Output Resistance in Current
Output Mode, AVSS to 1 V
1
1
1
1
MΩ
Bits
AUX DAC Monotonicity
Guaranteed
REFERENCE OUTPUT
10
10
10
10
Internal Reference Voltage
Output Resistance
0.98
1.025
10
1.08
0.98
1.025
10
1.08
0.98
1.025
10
1.08
0.98
1.025
10
1.08
V
kΩ
Rev. B | Page 5 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
AD9714
AD9715
Typ
AD9716
Typ
AD9717
Typ
Parameter
Min
Typ
Max
Min
Max
Min
Max
Min
Max
Unit
REFERENCE INPUT
Voltage Compliance
AVDD = 3.3 V
0.1
0.1
1.25
1.0
0.1
0.1
1.25
1.0
0.1
0.1
1.25
1.0
0.1
0.1
1.25
1.0
V
AVDD = 1.8 V
V
Input Resistance External
Reference Mode
1
1
1
1
MΩ
DAC MATCHING
Gain Matching
ANALOG SUPPLY VOLTAGES
AVDD
−1
+1
−1
+1
−1
+1
−1
+1
% FSR
1.7
1.7
3.5
3.5
1.7
1.7
3.5
3.5
1.7
1.7
3.5
3.5
1.7
1.7
3.5
3.5
V
V
CVDD
DIGITAL SUPPLY VOLTAGES
DVDD
1.7
1.7
1.9
3.5
1.7
1.7
1.9
3.5
1.7
1.7
1.9
3.5
1.7
1.7
1.9
3.5
V
V
DVDDIO
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 3.3 V
fDAC = 125 MSPS, IF = 12.5 MHz
IAVDD
86
86
86
86
mW
mA
10
10
10
10
IDVDD + IDVDDIO
11
11
11
11
mA
ICVDD
3
3
3
3
mA
Power-Down Mode with Clock
Power-Down Mode, No Clock
Power Supply Rejection Ratio
50
50
50
50
mW
mW
% FSR/V
1.5
−0.04
1.5
−0.04
1.5
−0.04
1.5
−0.04
POWER CONSUMPTION, AVDD =
DVDDIO = CVDD = 1.8 V.
fDAC = 125 MSPS, IF = 12.5 MHz
IAVDD
35
35
35
35
mW
mA
10
10
10
10
IDVDD + IDVDDIO
8
8
8
8
mA
ICVDD
1.5
12
1.5
12
1.5
12
1.5
12
mA
Power-Down Mode with Clock
Power-Down Mode, No Clock
Power Supply Rejection Ratio
OPERATING RANGE
mW
µW
850
−0.001
+25
850
−0.001
+25
850
−0.001
+25
850
−0.001
+25
% FSR/V
°C
–40
+85
–40
+85
–40
+85
–40
+85
1 Based on a 10 kΩ external resistor.
Rev. B | Page 6 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, CVDD = 3.3 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
DAC CLOCK INPUT (CLKIN)
VIH
2.1
3
0
V
VIL
0.9
V
Maximum Clock Rate
125
MSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
25
20
20
MHz
ns
Minimum Pulse Width High
Minimum Pulse Width Low
ns
INPUT DATA
1.8 V Q Channel or DCLKIO Falling Edge
Setup
0.25
1.2
ns
ns
Hold
1.8 V I Channel or DCLKIO Rising Edge
Setup
0.13
1.1
ns
ns
Hold
3.3 V Q Channel or DCLKIO Falling Edge
Setup
−0.2
1.5
ns
ns
Hold
3.3 V I Channel or DCLKIO Rising Edge
Setup
Hold
VIH
−0.2
1.6
3
ns
ns
V
2.1
VIL
0
0.9
V
Rev. B | Page 7 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
AC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 1.8 V, DVDDIO = 3.3 V, C V DD = 3. 3 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 3.
AD9714
Min Typ
AD9715
Max Min Typ
AD9716
Max Min Typ
AD9717
Max Min Typ
Parameter
Max Unit
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
75
60
82
61
83
62
84
63
dBc
dBc
TWO TONE INTERMODULATION
DISTORTION (IMD)
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
86
71
87
71
88
71
89
71
dBc
dBc
NOISE SPECTRAL DENSITY (NSD)
EIGHT-TONE, 500 kHz TONE SPACING
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
−129
−123
−141
−135
−149
−137
−152
−141
dBc/Hz
dBc/Hz
W-CDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 61.44 MSPS, fOUT = 20 MHz
fDAC = 122.88 MSPS, fOUT = 30 MHz
−71
−72
−71
−72
−71
−72
−71
−72
dBc
dBc
TMIN to TMAX, AVDD = 1.8 V, DVDD = 1.8 V, DVDDIO = 1.8 V, CVDD = 1.8 V, IxOUTFS = 2 mA, maximum sample rate, unless
otherwise noted.
Table 4.
AD9714
Min Typ
AD9715
Max Min Typ
AD9716
Max Min Typ
AD9717
Max Min Typ
Parameter
Max Unit
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
75
55
78
56
79
57
80
58
dBc
dBc
TWO TONE INTERMODULATION
DISTORTION (IMD)
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
79
53
80
53
84
53
85
53
dBc
dBc
NOISE SPECTRAL DENSITY (NSD)
EIGHT-TONE, 500 kHz TONE SPACING
fDAC = 125 MSPS, fOUT = 10 MHz
fDAC = 125 MSPS, fOUT = 50 MHz
−132
−126
−141
−131
−146
−131
−148
−132
dBc/Hz
dBc/Hz
W-CDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 61.44 MSPS, fOUT = 20 MHz
fDAC = 122.88 MSPS, fOUT = 30 MHz
−68
−68
−68
−68
−68
−68
−68
−68
dBc
dBc
Rev. B | Page 8 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
Parameter
Rating
AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS
DVDD to DVSS
−0.3 V to +3.9 V
Table 6.
−0.3 V to +2.1 V
1
1
Package Type
θJA
θJB
19.0
θJC
3.4
Unit
AVSS to DVSS, CVSS
−0.3 V to +0.3 V
40-Lead LFCSP (with No Airflow 29.8
Movement)
°C/W
DVSS to AVSS, CVSS
−0.3 V to +0.3 V
CVSS to AVSS, DVSS
−0.3 V to +0.3 V
1 These calculations are intended to represent the thermal performance of the
indicated packages using a JEDEC multilayer test board. Do not assume the
same level of thermal performance in actual applications without a careful
inspection of the conditions in the application to determine that they are
similar to those assumed in these calculations.
REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS
−0.3 V to AVDD + 0.3 V
−1.0 V to AVDD + 0.3 V
QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN,
RLIP, RLIN to AVSS
1
CS
DBn (MSB) to DB0 (LSB), , SCLK, SDIO,
RESET to DVSS
−0.3 V to DVDDIO + 0.3 V
CLKIN to CVSS
−0.3 V to CVDD + 0.3 V
125°C
ESD CAUTION
Junction Temperature
Storage Temperature Range
−65°C to +150°C
1 n stands for 7 for the AD9714, 9 for the AD9715, 11 for the AD9716, and 13
for the AD9717.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 9 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
DB5
DB4
1
2
3
4
5
6
7
8
9
30 RLIN
INDICATOR
29 IOUTN
28 IOUTP
27 RLIP
DB3
DB2
AD9714
DVDDIO
DVSS
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQN
TOP VIEW
DVDD
DB1
(Not to Scale)
DB0 (LSB)
NC 10
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 2. AD9714 Pin Configuration
Table 7. AD9714 Pin Function Descriptions
Pin No.
Mnemonic
DB[5:2]
DVDDIO
DVSS
Description
1 to 4
Digital Inputs.
5
6
7
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
Digital Common.
DVDD
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8
DB1
Digital Inputs.
9
DB0 (LSB)
NC
Digital Input (LSB).
10 to 15
16
No Connect. These pins are not connected to the chip.
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
DCLKIO
CVDD
CLKIN
CVSS
17
18
19
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
21
RLQN
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
23
24
QOUTN
QOUTP
RLQP
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
26
27
AVSS
AVDD
RLIP
Analog Common.
Analog Supply Voltage (1.8 V to 3.3 V).
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
29
30
IOUTP
IOUTN
RLIN
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. B | Page 10 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Pin No.
Mnemonic
CMLI
Description
31
I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
(see the Using the Internal Termination Resistors section). The recommended value for this external resistor
is 0 Ω.
32
33
FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-
scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
output.
FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is full-scale
current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
output.
34
35
REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36
37
38
SCLK/CLKMD
SDIO/FORMAT
CS/PWRDN
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
Retimer section).
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for serial port.
Format Pin (FORMAT ). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-
down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the two
complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select. In pin mode, a logic
high (pull-up to DVDDIO) powers down the device, except for the SPI port.
Power-Down (PWRDN). In pin mode, PWRDN powers down the device except for the SPI port.
Digital Input (MSB).
39
DB7 (MSB)
DB6
40
Digital Input.
41 (EPAD)
Exposed Pad
(EPAD)
The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. B | Page 11 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
PIN 1
DB7
DB6
1
2
3
4
5
6
7
8
9
30 RLIN
INDICATOR
29 IOUTN
28 IOUTP
27 RLIP
DB5
DB4
AD9715
DVDDIO
DVSS
DVDD
DB3
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQN
TOP VIEW
(Not to Scale)
DB2
DB1 10
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 3. AD9715 Pin Configuration
Table 8. AD9715 Pin Function Descriptions
Pin No.
Mnemonic
DB[7:4]
DVDDIO
DVSS
Description
1 to 4
Digital Inputs.
5
6
7
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
Digital Common.
DVDD
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 10
11
DB[3:1]
DB0 (LSB)
NC
Digital Inputs.
Digital Input (LSB).
12 to 15
16
No Connect. These pins are not connected to the chip.
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
DCLKIO
CVDD
CLKIN
CVSS
17
18
19
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
21
RLQN
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
23
24
QOUTN
QOUTP
RLQP
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
26
27
AVSS
AVDD
RLIP
Analog Common.
Analog Supply Voltage (1.8 V to 3.3 V).
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
29
30
IOUTP
IOUTN
RLIN
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. B | Page 12 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Pin No.
Mnemonic
CMLI
Description
31
I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
(see the Using the Internal Termination Resistors section). The recommended value for this external resistor
is 0 Ω.
32
33
FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-
scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
output.
FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is the full-
scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
output.
34
35
REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36
37
38
SCLK/CLKMD
SDIO/FORMAT
CS/PWRDN
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
Retimer section).
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
39
DB9 (MSB)
DB8
Digital Input (MSB).
Digital Input.
40
41 (EPAD)
Exposed Pad
(EPAD)
The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. B | Page 13 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
PIN 1
DB9
DB8
1
2
3
4
5
6
7
8
9
30 RLIN
INDICATOR
29 IOUTN
28 IOUTP
27 RLIP
DB7
DB6
AD9716
DVDDIO
DVSS
DVDD
DB5
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQN
TOP VIEW
(Not to Scale)
DB4
DB3 10
NOTES
1. NC = NO CONNECT
2. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 4. AD9716 Pin Configuration
Table 9. AD9716 Pin Function Descriptions
Pin No.
Mnemonic
DB[9:6]
DVDDIO
DVSS
Description
1 to 4
Digital Inputs.
5
6
7
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
Digital Common.
DVDD
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 12
13
DB[5:1]
DB0 (LSB)
NC
Digital Inputs.
Digital Input (LSB).
14, 15
16
No Connect. These pins are not connected to the chip.
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
DCLKIO
CVDD
CLKIN
CVSS
17
18
19
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
21
RLQN
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
23
24
QOUTN
QOUTP
RLQP
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
26
27
AVSS
AVDD
RLIP
Analog Common.
Analog Supply Voltage (1.8 V to 3.3 V).
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
29
30
IOUTP
IOUTN
RLIN
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. B | Page 14 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Pin No.
Mnemonic
CMLI
Description
31
I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
(see the Using the Internal Termination Resistors section). The recommended value for this external resistor
is 0 Ω.
32
33
FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-
scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
output.
FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is the full-
scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
output.
34
35
REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36
37
38
SCLK/CLKMD
SDIO/FORMAT
CS/PWRDN
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
Retimer section).
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
39
DB11 (MSB)
DB10
Digital Input (MSB).
Digital Input.
40
41 (EPAD)
Exposed Pad
(EPAD)
The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. B | Page 15 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
PIN 1
DB11
DB10
DB9
1
2
3
4
5
6
7
8
9
30 RLIN
INDICATOR
29 IOUTN
28 IOUTP
27 RLIP
DB8
AD9717
DVDDIO
DVSS
DVDD
DB7
26 AVDD
25 AVSS
24 RLQP
23 QOUTP
22 QOUTN
21 RLQN
TOP VIEW
(Not to Scale)
DB6
DB5 10
NOTES
1. THE EXPOSED PAD IS CONNECTED TO AVSS AND
SHOULD BE SOLDERED TO THE GROUND PLANE.
EXPOSED METAL AT PACKAGE CORNERS IS
CONNECTED TO THIS PAD.
Figure 5. AD9717 Pin Configuration
Table 10. AD9717 Pin Function Descriptions
Pin No.
Mnemonic
DB[11:8]
DVDDIO
DVSS
Description
1 to 4
Digital Inputs.
5
6
7
Digital I/O Supply Voltage (1.8 V to 3.3 V Nominal).
Digital Common.
DVDD
Digital Core Supply Voltage (1.8 V). Strap DVDD to DVDDIO at 1.8 V. If DVDDIO > 1.8 V, bypass DVDD with a
1.0 µF capacitor; however, do not otherwise connect it. The LDO should not drive external loads.
8 to 14
15
DB[7:1]
DB0 (LSB)
DCLKIO
CVDD
Digital Inputs.
Digital Input (LSB).
16
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
17
18
CLKIN
19
CVSS
Sampling Clock Supply Voltage Common.
20
CMLQ
Q DAC Output Common-Mode Level. When the internal on chip (QRCML) is enabled, this pin is connected to
the on-chip QRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip
(QRCML) is disabled, this pin is the common-mode load for Q DAC and must be connected to AVSS through a
resistor (see the Using the Internal Termination Resistors section). The recommended value for this external
resistor is 0 Ω.
21
RLQN
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTN externally.
22
23
24
QOUTN
QOUTP
RLQP
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (500 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to
QOUTP externally.
25
26
27
AVSS
AVDD
RLIP
Analog Common.
Analog Supply Voltage (1.8 V to 3.3 V).
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTP externally.
28
29
30
IOUTP
IOUTN
RLIN
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (500 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to
IOUTN externally.
Rev. B | Page 16 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Pin No.
Mnemonic
CMLI
Description
31
I DAC Output Common-Mode Level. When the internal on chip (IRCML) is enabled, this pin is connected to the
on-chip IRCML resistor. It is recommended to leave this pin unconnected. When the internal on chip (IRCML) is
disabled, this pin is the common-mode load for I DAC and must be connected to AVSS through a resistor
(see the Using the Internal Termination Resistors section). The recommended value for this external resistor
is 0 Ω.
32
33
FSADJQ/AUXQ Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-
scale current output adjust for Q DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on chip (QRSET) is enabled, this pin is the auxiliary Q DAC
output.
FSADJI/AUXI
Full-Scale Current Output Adjust (FSADJI). When the internal on chip (IRSET) is disabled, this pin is the full-
scale current output adjust for I DAC and must be connected to AVSS through a resistor (see the Theory of
Operation section). The nominal value for this external resistor is 16 kΩ for a 2 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on chip (IRSET) is enabled, this pin is the auxiliary I DAC
output.
34
35
REFIO
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V
reference output when in internal reference mode (a 0.1 μF capacitor to AVSS is required).
RESET/PINMD
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode.
Pulse RESET high to reset the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
36
37
38
SCLK/CLKMD
SDIO/FORMAT
CS/PWRDN
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When
DCLKIO = CLKIN, tie it to 0. When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer (see the
Retimer section).
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low
(pull-down to DVSS) selects the binary input data format. A logic high (pull-up to DVDDIO) selects the
twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for
the SPI port.
39
DB13 (MSB)
DB12
Digital Input (MSB).
Digital Input.
40
41 (EPAD)
Exposed Pad
(EPAD)
The exposed pad is connected to AVSS and should be soldered to the ground plane. Exposed metal at the
package corners is connected to this pad.
Rev. B | Page 17 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
IxOUTFS = 2 mA, maximum sample rate, unless otherwise noted. DVDD is always at 1.8 V.
1.5
1.0
0.5
0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 6. AD9717 Precalibration INL at 1.8 V (DVDD = 1.8 V)
Figure 9. AD9717 Postcalibration INL at 1.8 V (DVDD = 1.8 V)
1.5
1.5
1.0
0.5
0
1.0
0.5
0
–0.5
–1.0
–1.5
–0.5
–1.0
–1.5
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 7. AD9717 Precalibration DNL at 1.8 V (DVDD = 1.8 V)
Figure 10. AD9717 Postcalibration DNL at 1.8 V (DVDD = 1.8 V)
1.75
1.75
1.25
1.25
0.75
0.75
0.25
0.25
–0.25
–0.75
–1.25
–1.75
–0.25
–0.75
–1.25
–1.75
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 8. AD9717 Precalibration INL at 3.3 V (DVDD = 1.8 V)
Figure 11. AD9717 Postcalibration INL at 3.3 V (DVDD = 1.8 V)
Rev. B | Page 18 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
1.75
1.25
1.75
1.25
0.75
0.75
0.25
0.25
–0.25
–0.75
–1.25
–1.75
–0.25
–0.75
–1.25
–1.75
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
0
2048
4096
6144
8192 10,240 12,288 14,336 16,384
CODE
Figure 12. AD9717 Precalibration DNL at 3.3 V
Figure 15. AD9717 Postcalibration DNL at 3.3 V
0.4
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
0
512
1024
1536
2048
2560
3072 3584
4096
0
512
1024
1536
2048
2560
3072 3584
4096
CODE
CODE
Figure 13. AD9716 Precalibration INL at 1.8 V
Figure 16. AD9716 Postcalibration INL at 1.8 V
0.4
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
0
512
1024
1536
2048
2560
3072 3584
4096
0
512
1024
1536
2048
2560
3072 3584
4096
CODE
CODE
Figure 14. AD9716 Precalibration DNL at 1.8 V
Figure 17. AD9716 Postcalibration DNL at 1.8 V
Rev. B | Page 19 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
0.4
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
0
512
1024
1536
2048
2560
3072 3584
4096
0
512
1024
1536
2048
2560
3072 3584
4096
CODE
CODE
Figure 18. AD9716 Precalibration INL at 3.3 V
Figure 21. AD9716 Postcalibration INL at 3.3 V
0.4
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
–0.3
–0.4
0
512
1024
1536
2048
2560
3072 3584
4096
0
512
1024
1536
2048
2560
3072 3584
4096
CODE
CODE
Figure 19. AD9716 Precalibration DNL at 3.3 V
Figure 22. AD9716 Postcalibration DNL at 3.3 V
0.13
0.13
0.08
0.08
0.03
0.03
–0.02
–0.07
–0.02
–0.07
–0.12
–0.12
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 20. AD9715 Precalibration INL at 1.8 V
Figure 23. AD9715 Postcalibration INL at 1.8 V
Rev. B | Page 20 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
0.13
0.13
0.08
0.08
0.03
0.03
–0.02
–0.07
–0.12
–0.02
–0.07
–0.12
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 24. AD9715 Precalibration DNL at 1.8 V
Figure 27. AD9715 Postcalibration DNL at 1.8 V
0.13
0.08
0.13
0.08
0.03
0.03
–0.02
–0.07
–0.02
–0.07
–0.12
–0.12
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 25. AD9715 Precalibration INL at 3.3 V
Figure 28. AD9715 Postcalibration INL at 3.3 V
0.13
0.08
0.13
0.08
0.03
0.03
–0.02
–0.07
–0.02
–0.07
–0.12
–0.12
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 26. AD9715 Precalibration DNL at 3.3 V
Figure 29. AD9715 Postcalibration DNL at 3.3 V
Rev. B | Page 21 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
0.025
0.020
0.015
0.010
0.005
0
0.025
0.020
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.025
–0.005
–0.010
–0.015
–0.020
–0.025
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
Figure 30. AD9714 Precalibration INL at 1.8 V
Figure 33. AD9714 Postcalibration INL at 1.8 V
0.025
0.020
0.015
0.010
0.005
0
0.025
0.020
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.025
–0.005
–0.010
–0.015
–0.020
–0.025
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
Figure 31. AD9714 Precalibration DNL at 1.8 V
Figure 34. AD9714 Postcalibration DNL at 1.8 V
0.025
0.020
0.015
0.010
0.005
0
0.025
0.020
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.025
–0.005
–0.010
–0.015
–0.020
–0.025
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
Figure 32. AD9714 Precalibration INL at 3.3 V
Figure 35. AD9714 Postcalibration INL at 3.3 V
Rev. B | Page 22 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
0.025
0.020
0.015
0.010
0.005
0
0.025
0.020
0.015
0.010
0.005
0
–0.005
–0.010
–0.015
–0.020
–0.025
–0.005
–0.010
–0.015
–0.020
–0.025
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
0
16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256
CODE
CODE
Figure 36. AD9714 Precalibration DNL at 3.3 V
Figure 39. AD9714 Postcalibration DNL at 3.3 V
–126
–126
AD9714
AD9714
–129
–132
–135
–138
–132
–138
–144
–150
AD9715
AD9715
–141
–144
AD9716
AD9717
–147
–150
–153
AD9716
AD9717
–156
–156
0
5
10
15
20
25
30
35
40
45
50
55
0
5
10
15
20
25
30
35
40
45
50
55
fOUT (MHz)
fOUT (MHz)
Figure 37. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 1.8 V
Figure 40. AD9714/AD9715/AD9716/AD9717 Noise Spectral Density at 3.3 V
–133
–133
–136
–136
–40°C
+85°C
–139
–139
+25°C
–142
–142
+25°C
–40°C
–145
–148
–151
–154
–145
+85°C
–148
–151
–154
5
10
15
20
25
30
35
40
45
50
55
5
10
15
20
25
30
35
40
45
50
55
fOUT (MHz)
fOUT (MHz)
Figure 38. AD9717 Noise Spectral Density at Three Temperatures, 1.8 V
Figure 41. AD9717 Noise Spectral Density at Three Temperatures, 3.3 V
Rev. B | Page 23 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
–130
–133
–136
–139
–130
–133
–136
–139
–142
–145
–148
–151
–154
–157
3.3V, 1mA
1.8V, 1mA
–142
1.8V, 2mA
–145
3.3V, 4mA
3.3V, 2mA
–148
–151
–154
–157
0
5
10
15
20
25
30
35
40
45
50
55
0
5
10
15
20
25
30
35
40
45
50
55
fOUT (MHz)
fOUT (MHz)
Figure 42. AD9717 Noise Spectral Density at Two Output Currents, 1.8 V
Figure 45. AD9717 Noise Spectral Density at Three Output Currents, 3.3 V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
START 1MHz
1.5MHz/DIV
STOP 16MHz
START 1MHz
1.4MHz/DIV
STOP 15MHz
Figure 43. AD9717 Two Tone Spectrum, 1.8 V
Figure 46. AD9717 Two Tone Spectrum, 3.3 V
88
100
AD9717
82
76
70
64
58
52
94
88
AD9716
AD9715
AD9714
AD9715
AD9716
AD9717
82
AD9714
76
70
5
10
15
20
25
30
35
40
45
50
5
10
15
20
25
30
35
40
45
50
fOUT (MHz)
fOUT (MHz)
Figure 44. AD9714/AD9715/AD9716/AD9717 IMD at 1.8 V
Figure 47. AD9714/AD9715/AD9716/AD9717 IMD at 3.3 V
Rev. B | Page 24 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
90
90
84
78
72
66
60
54
+85°C
84
+25°C
+25°C
–40°C
78
+85°C
–40°C
72
66
60
54
5
10
15
20
25
30
35
40
45
50
5
10
15
20
25
30
35
40
45
50
fOUT (MHz)
fOUT (MHz)
Figure 48. AD9717 IMD at Three Temperatures, 1.8 V
Figure 51. AD9717 IMD at Three Temperatures, 3.3 V
88
82
91
88
85
82
0dB
–3dB
76
70
–3dB
–6dB
–6dB
64
0dB
79
76
58
52
5
10
15
20
25
30
35
40
45
50
5
10
15
20
25
30
35
40
45
50
fIN (MHz)
fIN (MHz)
Figure 49. AD9717 IMD at Three Digital Input Levels, 1.8 V
Figure 52. AD9717 IMD at Three Digital Input Levels, 3.3 V
90
90
2mA
84
78
72
66
60
54
84
78
72
66
60
54
4mA
1mA
1mA
2mA
5
10
15
20
25
30
35
40
45
50
5
10
15
20
25
30
35
40
45
50
fOUT (MHz)
fOUT (MHz)
Figure 50. AD9717 IMD at Two Output Currents, 1.8 V
Figure 53. AD9717 IMD at Three Output Currents, 3.3 V
Rev. B | Page 25 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
START 1MHz
1.5MHz/DIV
STOP 16MHz
START 1MHz
1.4MHz/DIV
STOP 15MHz
Figure 54. AD9717 Single-Tone Spectrum, 1.8 V
Figure 57. AD9717 Single-Tone Spectrum, 3.3 V
86
80
74
68
62
56
50
93
90
87
84
81
78
75
72
69
66
AD9717
AD9716
AD9715
AD9714
AD9717
AD9716
AD9715
AD9714
5
10
15
20
25
30
35
40
45
50
55
60
5
10
15
20
25
30
35
40
45
50
55
60
fOUT (MHz)
fOUT (MHz)
Figure 55. AD9714/AD9715/AD9716/AD9717 SFDR at 1.8 V
Figure 58. AD9714/AD9715/AD9716/AD9717 SFDR at 3.3 V
90
84
90
84
3.3V, +85°C
78
+85°C
78
+25°C
72
72
66
3.3V, –40°C
3.3V, +25°C
66
60
54
–40°C
60
54
48
5
10
15
20
25
30
35
40
45
50
55
60
5
10
15
20
25
30
35
40
45
50
55
60
fOUT (MHz)
fOUT (MHz)
Figure 59. AD9717 SFDR at Three Temperatures, 3.3 V
Figure 56. AD9717 SFDR at Three Temperatures, 1.8 V
Rev. B | Page 26 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
90
90
85
80
75
70
85
80
75
70
–6dB
–6dB
0dB
–3dB
–3dB
65
60
55
50
65
60
55
50
0dB
0
10
20
30
fIN (MHz)
40
50
60
0
10
20
30
40
50
60
fIN (MHz)
Figure 60. SFDR at Three Digital Input Levels vs. fIN, 1.8 V
Figure 63. SFDR at Three Digital Input Levels vs. fIN, 3.3 V
90
84
78
72
66
60
54
48
90
84
78
72
66
60
54
4mA
1mA
2mA
2mA
1mA
5
10
15
20
25
30
35
40
45
50
55
60
5
10
15
20
25
30
35
40
45
50
55
60
fOUT (MHz)
fOUT (MHz)
Figure 61. SFDR at Two Output Currents, 1.8 V
Figure 64. SFDR at Three Output Currents, 3.3 V
AC-COUPLED: UNSPECIFIED
BELOW 20MHz
AC-COUPLED: UNSPECIFIED
BELOW 20MHz
CENTER 22.90MHz
RES BW 30kHz
SPAN 38.84MHz
CENTER 22.90MHz
RES BW 30kHz
SPAN 38.84MHz
VBW 300kHz
VBW 300kHz
SWEEP 126ms (601pts)
SWEEP 126ms (601pts)
TOTAL CARRIER POWER –19.81dBm/7.87420MHz
REF CARRIER POWER –19.81dBm/4.03420MHz
RCC FILTER: OFF FILTER ALPHA 0.22
TOTAL CARRIER POWER –25.42dBm/7.68000MHz
REF CARRIER POWER –25.42dBm/3.84000MHz
RCC FILTER: OFF FILTER ALPHA 0.22
OFFSET INTEG
FREQ BW
LOWER
dBc dBm
UPPER
dBc dBm
OFFSET INTEG
FREQ BW
LOWER
dBc dBm
UPPER
dBc dBm
1. –19.81dBm 5.000MHz 3.840MHz –70.32 –90.13 –72.61 –92.42
2. –85.75dBm 10.00MHz 3.840MHz –71.81 –91.61 –71.60 –91.41
15.00MHz 3.840MHz –72.59 –92.40 –65.50 –85.31
1. –25.42dBm 5.000MHz 3.840MHz –72.52 –97.94 –72.44 –97.86
2. –88.16dBm 10.00MHz 3.840MHz –72.82 –98.24 –73.02 –98.44
15.00MHz 3.840MHz –72.18 –97.60 –71.88 –97.30
Figure 62. AD9717 One-Carrier ACLR, 1.8 V
Figure 65. AD9717 One-Carrier ACLR, 3.3 V
Rev. B | Page 27 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
–60
–60
–65
1mA PRECAL
1mA PRECAL
1mA POSTCAL
–65
2mA POSTCAL
1mA POSTCAL
–70
–75
–80
2mA POSTCAL
–70
2mA PRECAL
4mA POSTCAL
2mA PRECAL
4mA PRECAL
fOUT (MHz)
–75
15
25
35
45
15
25
35
45
fOUT (MHz)
Figure 66. AD9717 One-Carrier W-CDMA First ACLR, 1.8 V
Figure 69. AD9717 One-Carrier W-CDMA First ACLR, 3.3 V
–60
–60
1mA PRECAL
2mA PRECAL
1mA PRECAL
–65
–70
–75
–80
–65
1mA POSTCAL
1mA POSTCAL
2mA PRECAL
–70
–75
2mA POSTCAL
4mA PRECAL
2mA POSTCAL
4mA POSTCAL
fOUT (MHz)
15
25
35
45
15
25
35
45
fOUT (MHz)
Figure 67. AD9717 One-Carrier W-CDMA Second ACLR, 1.8 V
Figure 70. AD9717 One-Carrier W-CDMA Second ACLR, 3.3 V
–60
–60
1mA PRECAL
1mA PRECAL
–65
–65
2mA POSTCAL
1mA POSTCAL
2mA PRECAL
1mA POSTCAL
–70
4mA PRECAL
–70
2mA POSTCAL
–75
2mA PRECAL
4mA POSTCAL
–80
20
–75
20
30
fOUT (MHz)
40
30
fOUT (MHz)
40
Figure 68. AD9717 One-Carrier W-CDMA Third ACLR, 1.8 V
Figure 71. AD9717 One-Carrier W-CDMA Third ACLR, 3.3 V
Rev. B | Page 28 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
AC-COUPLED:UNSPECIFIED
BELOW 20MHz
AC-COUPLED: UNSPECIFIED
BELOW 20MHz
CENTER 22.90MHz
RES BW 30kHz
SPAN 38.84MHz
CENTER 22.90MHz
RES BW 30kHz
SPAN 38.84MHz
VBW 300kHz
VBW 300kHz
SWEEP 126ms (601pts)
SWEEP 126ms (601pts)
TOTAL CARRIER POWER –23.08dBm/7.87420MHz
REF CARRIER POWER –25.84dBm/4.03420MHz
RCC FILTER: OFF FILTER ALPHA 0.22
TOTAL CARRIER POWER –33.14dBm/7.87420MHz
REF CARRIER POWER –25.86dBm/4.03420MHz
RCC FILTER: OFF FILTER ALPHA 0.22
OFFSET INTEG
FREQ BW
LOWER
dBc dBm
UPPER
dBc dBm
OFFSET INTEG
FREQ BW
LOWER
dBc dBm
UPPER
dBc dBm
1. –25.84dBm 5.000MHz 3.840MHz –65.45 –91.30 –65.63 –91.47
2. –26.35dBm 10.00MHz 3.840MHz –67.01 –92.85 –67.05 –92.89
15.00MHz 3.840MHz –65.22 –91.06 –65.33 –91.18
1. –25.86dBm 5.000MHz 3.840MHz –66.28 –92.13 –66.68 –92.53
2. –26.47dBm 10.00MHz 3.840MHz –68.17 –94.02 –66.93 –92.78
15.00MHz 3.840MHz –64.89 –90.73 –65.84 –91.69
Figure 72. AD9717 Two-Carrier ACLR, 1.8 V
Figure 75. AD9717 Two-Carrier ACLR, 3.3 V
–55
–55
1mA POSTCAL
1mA PRECAL
1mA PRECAL
1mA POSTCAL
–60
2mA PRECAL
–60
2mA PRECAL
–65
2mA POSTCAL
2mA POSTCAL
4mA PRECAL
–65
–70
–70
4mA POSTCAL
–75
15
20
25
30
35
40
15
20
25
30
35
40
fOUT (MHz)
fOUT (MHz)
Figure 73. AD9717 Two-Carrier W-CDMA First ACLR, 1.8 V
Figure 76. AD9717 Two-Carrier W-CDMA First ACLR, 3.3 V
–55
–55
1mA PRECAL
1mA PRECAL
–60
–65
–70
–75
–60
1mA POSTCAL
2mA PRECAL
1mA POSTCAL
2mA PRECAL
–65
–70
2mA POSTCAL
2mA POSTCAL
4mA POSTCAL
35
4mA PRECAL
25
15
20
25
30
35
40
15
20
30
40
fOUT (MHz)
fOUT (MHz)
Figure 74. AD9717 Two-Carrier W-CDMA Second ACLR, 1.8 V
Figure 77. AD9717 Two-Carrier W-CDMA Second ACLR, 3.3 V
Rev. B | Page 29 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
–55
–55
–60
–65
–70
–75
1mA PRECAL
1mA PRECAL
–60
1mA POSTCAL
2mA PRECAL
1mA POSTCAL
2mA PRECAL
–65
–70
2mA POSTCAL
4mA PRECAL
2mA POSTCAL
4mA POSTCAL
35
20
25
30
fOUT (MHz)
35
40
20
25
30
40
fOUT (MHz)
Figure 78. AD9717 Two-Carrier W-CDMA Third ACLR, 1.8 V
Figure 81. AD9717 Two-Carrier W-CDMA Third ACLR, 3.3 V
0.4
1.0
0.3
0.2
0.8
0.6
0.4
0.1
0.2
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.2
–0.4
–0.6
–0.8
–1.0
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
CODE
CODE
Figure 82. AUXDAC INL
Figure 79. AUXDAC DNL
25
TOTAL CURRENT @ 1mA OUT
TOTAL CURRENT @ 2mA OUT
TOTAL CURRENT @ 4mA OUT
30
20
10
20
15
10
5
TOTAL CURRENT @ 2mA OUT
AVDD @ 4mA OUT
TOTAL CURRENT @ 1mA OUT
AVDD @ 2mA OUT
AVDD @ 1mA OUT
DVDD
AVDD @ 2mA OUT
AVDD @ 1mA OUT
DVDD
CVDD
CVDD
0
0
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
fCLK (MHz)
fCLK (MHz)
Figure 80. Supply Current vs. Clock Frequency at 1.8 V
Figure 83. Supply Current vs. Clock Frequency at 3.3 V
Rev. B | Page 30 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
TERMINOLOGY
Linearity Error or Integral Nonlinearity (INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by
a straight line drawn from zero scale to full scale.
Power Supply Rejection
Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from minimum to maximum
specified voltages.
Differential Nonlinearity (DNL)
Settling Time
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the peak
amplitude of the output signal and the peak spurious signal
between dc and the frequency equal to half the input data rate.
Offset Error
Offset error is the deviation of the output current from the
ideal of zero. For IOUTP, 0 mA output is expected when the
inputs are all 0. For IOUTN, 0 mA output is expected when all
inputs are set to 1.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental.
It is expressed as a percentage or in decibels.
Gain Error
Gain error is the difference between the actual and the ideal
output span. The actual span is determined by the difference
between the output when all inputs are set to 1 and the output
when all inputs are set to 0.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels (dB).
Output Compliance Range
Output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc)
between the measured power within a channel relative to its
adjacent channel.
Temperature Drift
Complex Image Rejection
Temperature drift is specified as the maximum change from
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect of
wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
the ambient value (25°C) to the value at either TMIN or TMAX
.
For offset and gain drift, the drift is reported in ppm of full-
scale range per degree Celsius (ppm FSR/°C). For reference
drift, the drift is reported in parts per million per degree
Celsius (ppm/°C).
Rev. B | Page 31 of 80
AD9714/AD9715/AD9716/AD9717
THEORY OF OPERATION
Data Sheet
1V
AD9717
SPI
INTERFACE
DB11
QR
16kΩ
IR
SET
16kΩ
SET
IR
CML
1kΩ TO
250Ω
DB10
RLIN
500Ω
500Ω
10kΩ
DB9
DB8
IOUTN
IOUTP
I
I DAC
REF
100µA
BAND
GAP
RLIP
AUX1DAC
AUX2DAC
DVDDIO
1 INTO 2
AVDD
AVSS
RLQP
INTERLEAVED
DATA
INTERFACE
I DATA
DVSS
500Ω
500Ω
DVDD
1.8V
LDO
QOUTP
QOUTN
Q DATA
Q DAC
DB7
DB6
CLOCK
DIST
RLQN
QR
CML
1kΩ TO
250Ω
DB5
Figure 84. Simplified Block Diagram
Figure 84 shows a simplified block diagram of the AD9714/
AD9715/AD9716/AD9717 that consists of two DACs, digital
control logic, and a full-scale output current control. Each DAC
contains a PMOS current source array capable of providing a
nominal full-scale current (IxOUTFS) of 2 mA and a maximum of
4 mA. The arrays are divided into 31 equal currents that make
up the five most significant bits (MSBs). The next four bits, or
middle bits, consist of 15 equal current sources whose value is
1/16 of an MSB current source. The remaining LSBs are binary
weighted fractions of the current sources of the middle bits.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
high output impedance of the DACs (that is, >200 MΩ).
LDO is provided for DVDDIO supplies greater than 1.8 V, or the
1.8 V can be supplied directly through DVDD. A 1.0 µF bypass
capacitor at DVDD (Pin 7) is required when using the LDO.
The core is capable of operating at a rate of up to 125 MSPS. It
consists of edge-triggered latches and the segment decoding logic
circuitry. The analog section includes PMOS current sources,
associated differential switches, a 1.0 V band gap voltage
reference, and a reference control amplifier.
Each DAC full-scale output current is regulated by the reference
control amplifier and can be set from 1 mA to 4 mA via an external
resistor, xRSET, connected to its full-scale adjust pin (FSADJx).
The external resistor, in combination with both the reference
control amplifier and voltage reference, VREFIO, sets the reference
current, IxREF, which is replicated to the segmented current sources
with the proper scaling factor. The full-scale current, IxOUTFS, is
All of these current sources are switched to one or the other
of the two output nodes (IOUTP or IOUTN) via PMOS differential
current switches. The switches are based on the architecture that
was pioneered in the AD976x family, with further refinements
to reduce distortion contributed by the switching transient. This
switch architecture also reduces various timing errors and
provides matching complementary drive signals to the inputs
of the differential current switches.
32 × IxREF
.
Optional on-chip xRSET resistors are provided that can be pro-
grammed between a nominal value of 8 kΩ to 32 kΩ (4 mA to
1 mA IxOUTFS, respectively).
The AD9714/AD9715/AD9716/AD9717 provide the option of
setting the output common mode to a value other than AVSS
via the output common-mode pins (CMLI and CMLQ). This
facilitates directly interfacing the output of the AD9714/AD9715/
AD9716/AD9717 to components that require common-mode
levels greater than 0 V.
The analog and digital I/O sections of the AD9714/AD9715/
AD9716/AD9717 have separate power supply inputs (AVDD and
DVDDIO) that can operate independently over a 1.8 V to 3.3 V
range. The core digital section requires 1.8 V. An optional on-chip
Rev. B | Page 32 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
SERIAL PERIPHERAL INTERFACE (SPI)
The serial port of the AD9714/AD9715/AD9716/AD9717 is a
flexible, synchronous serial communications port that allows easy
interfacing to many industry-standard microcontrollers and
microprocessors. The serial I/O is compatible with most synchron-
ous transfer formats, including both the Motorola SPI and Intel®
SSR protocols. The interface allows read/write access to all registers
that configure the AD9714/AD9715/AD9716/AD9717. Single or
multiple byte transfers are supported, as well as MSB first or
LSB first transfer formats. The serial interface port of the AD9714/
AD9715/AD9716/AD9717 is configured as a single I/O pin on
the SDIO pin.
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 11.
Table 11.
MSB
DB7
R/W
LSB
DB6
DB5
DB4 DB3 DB2 DB1 DB0
N1
N0
A4
A3
A2
A1
A0
W
R/ (Bit 7 of the instruction byte) determines whether a read or a
write data transfer occurs after the instruction byte write. Logic 1
indicates a read operation. Logic 0 indicates a write operation.
N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the
number of bytes to be transferred during the data transfer cycle.
The bit decodes are shown in Table 12.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communications cycle on the AD9714/
AD9715/AD9716/AD9717. Phase 1 is the instruction cycle, which
is the writing of an instruction byte into the AD9714/AD9715/
AD9716/AD9717, coinciding with the first eight SCLK rising
edges. In Phase 2, the instruction byte provides the serial port
controller of the AD9714/AD9715/AD9716/AD9717 with infor-
mation regarding the data transfer cycle. The Phase 1 instruction
byte defines whether the upcoming data transfer is a read or write,
the number of bytes in the data transfer, and the starting register
address for the first byte of the data transfer. The first eight SCLK
rising edges of each communication cycle are used to write the
instruction byte into the AD9714/AD9715/AD9716/AD9717.
Table 12. Byte Transfer Count
N1
0
N0
0
Description
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
0
1
1
0
1
1
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte) determine which register is accessed during the
data transfer portion of the communications cycle. For multi-
byte transfers, this address is the starting byte address. The
following register addresses are generated internally by the
AD9714/AD9715/AD9716/AD9717, based on the LSBFIRST bit
(Register 0x00, Bit 6).
A Logic 1 on Pin 35 (RESET/PINMD), followed by a Logic 0,
resets the SPI port timing to the initial state of the instruction
cycle. This is true regardless of the present state of the internal
registers or the other signal levels present at the inputs to the
SPI port. If the SPI port is in the midst of an instruction cycle
or a data transfer cycle, none of the present data is written.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9714/AD9715/AD9716/AD9717 and to run the internal state
machines. The SCLK maximum frequency is 20 MHz. All data
input to the AD9714/AD9715/AD9716/AD9717 is registered on
the rising edge of SCLK. All data is driven out of the AD9714/
AD9715/AD9716/AD9717 on the falling edge of SCLK.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9714/
AD9715/AD9716/AD9717 and the system controller. Phase 2 of
the communication cycle is a transfer of one, two, three, or four
data bytes, as determined by the instruction byte. Using one multi-
byte transfer is the preferred method. Single-byte data transfers
are useful to reduce CPU overhead when register access requires
one byte only. Registers change immediately upon writing to the
last bit of each transfer byte.
CS
—Chip Select
An active low input starts and gates a communications cycle.
It allows more than one device to be used on the same serial
communications lines. The SDIO/FORMAT pin reaches a
high impedance state when this input is high. Chip select
should stay low during the entire communications cycle.
SDIO—Serial Data I/O
The SDIO pin is used as a bidirectional data line to transmit
and receive data.
Rev. B | Page 33 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
MSB/LSB TRANSFERS
CS
The serial port of the AD9714/AD9715/AD9716/AD9717 can
support both most significant bit (MSB) first or least significant
bit (LSB) first data formats. This functionality is controlled by
the LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first
(LSBFIRST = 0).
SCLK
R/W N1 N0 A4 A3 A2 A1 A0
D7
D6 D5
N
D3 D2 D1 D0
0 0 0 0
N
SDIO
SDO
When LSBFIRST = 0 (MSB first), the instruction and data bytes
must be written from the most significant bit to the least significant
bit. Multibyte data transfers in MSB first format start with an
instruction byte that includes the register address of the most
significant data byte. Subsequent data bytes should follow in
order from a high address to a low address. In MSB first mode,
the serial port internal byte address generator decrements for
each data byte of the multibyte communications cycle.
Figure 86. Serial Register Interface Timing, MSB First Read
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20
D4N D5N D6N D7N
When LSBFIRST = 1 (LSB first), the instruction and data bytes
must be written from the least significant bit to the most signifi-
cant bit. Multibyte data transfers in LSB first format start with
an instruction byte that includes the register address of the least
significant data byte followed by multiple data bytes. The serial
port internal byte address generator increments for each byte
of the multibyte communication cycle.
Figure 87. Serial Register Interface Timing, LSB First Write
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
The serial port controller data address of the AD9714/AD9715/
AD9716/AD9717 decrements from the data address written
toward 0x00 for multibyte I/O operations if the MSB first mode
is active. The serial port controller address increments from the
data address written toward 0x1F for multibyte I/O operations
if the LSB first mode is active.
A0 A1 A2 A3 A4 N0 N1 R/W
D0
D10 D20
D4N D5N D6N D7N
SDIO
SDO
Figure 88. Serial Register Interface Timing, LSB First Read
PIN MODE
The AD9714/AD9715/AD9716/AD9717 can also be operated
without ever writing to the serial port. With the RESET/PINMD
pin tied high, the SCLK pin becomes CLKMD to provide for
clock mode control (see the Retimer section), the SDIO pin
becomes FORMAT and selects the input data format, and the
SERIAL PORT OPERATION
The serial port configuration of the AD9714/AD9715/AD9716/
AD9717 is controlled by Register 0x00. It is important to note
that the configuration changes immediately upon writing to the
last bit of the register. For multibyte transfers, writing to this
register can occur during the middle of the communications
cycle. Care must be taken to compensate for this new configu-
ration for the remaining bytes of the current communications cycle.
CS
/PWRDN pin serves to power down the device.
Operation is otherwise exactly as defined by the default register
values in Table 13; therefore, external resistors at FSADJI and
FSADJQ are needed to set the DAC currents, and both DACs
are active. This is also a convenient quick checkout mode.
The same considerations apply to setting the software reset bit
(Register 0x00, Bit 5). All registers are set to their default values
except Register 0x00, which remains unchanged.
DAC currents can be externally adjusted in pin mode by sourcing
or sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ
pins as desired with the fixed resistors installed. An op amp
output with appropriate series resistance is one of many possibili-
ties. This has the same effect as changing the resistor value.
Place at least 10 kΩ resistors in series right at the DAC to guard
against accidental short circuits and noise modulation. The
REFIO pin can be adjusted ±±5ꢀ in a similar manner, if desired.
Use of single-byte transfers or initiating a software reset is
recommended when changing serial port configurations to
prevent unexpected device behavior.
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5
D3 D2 D1 D0
0 0 0 0
N
N
N
Figure 85. Serial Register Interface Timing, MSB First Write
Rev. B | Page 34 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
SPI REGISTER MAP
Table 13.
Name
Addr Default Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI Control
Power-Down
Data Control
I DAC Gain
IRSET
0x00 0x00
0x01 0x40
0x02 0x34
0x03 0x00
0x04 0x00
0x05 0x00
0x06 0x00
0x07 0x00
0x08 0x00
0x09 0x00
0x0A 0x00
0x0B 0x00
0x0C 0x00
Reserved
LDOOFF
TWOS
LSBFIRST Reset
LDOSTAT PWRDN
Reserved IFIRST
LNGINS
Q DACOFF I DACOFF
IRISING SIMULBIT
QCLKOFF
DCI_EN
ICLKOFF EXTREF
DCOSGL DCODBL
Reserved
I DACGAIN[5:0]
IRSETEN
Reserved
Reserved
IRSET[5:0]
IRCML[5:0]
IRCML
IRCMLEN
Q DAC Gain
QRSET
Reserved
Q DACGAIN[5:0]
QRSET[5:0]
QRSETEN
Reserved
QRCML
QRCMLEN Reserved
QRCML[5:0]
AUXDAC Q
AUX CTLQ
AUXDAC I
AUX CTLI
QAUXDAC[7:0]
QAUXOFS[2:0]
IAUXDAC[7:0]
IAUXOFS[2:0]
RREF[5:0]
CALCLK DIVSEL[2:0]
CALMEMQ[1:0]
MEMADDR[5:0]
MEMDATA[5:0]
SMEMWR SMEMRD
QAUXEN
QAUXRNG[1:0]
IAUXRNG[1:0]
QAUXDAC[9:8]
IAUXDAC[9:8]
IAUXEN
Reference Resistor 0x0D 0x00
Reserved
PRELDQ PRELDI
Cal Control
Cal Memory
Memory Address
Memory Data
Memory R/W
CLKMODE
0x0E 0x00
0x0F 0x00
0x10 0x00
0x11 0x34
0x12 0x00
0x14 0x00
0x1F 0x03
CALSELQ CALSELI
CALSTATQ CALSTATI
Reserved
CALMEMI[1:0]
Reserved
CALRSTQ
CALRSTI
CALEN
UNCALQ UNCALI
CLKMODEQ[1:0]
Searching Reacquire
Version[7:0]
CLKMODEN CLKMODEI[1:0]
Version
Rev. B | Page 35 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 14.
Register
Address Bit
Name
Description
SPI Control
0x00
6
5
LSBFIRST
0 (default): MSB first, per SPI standard.
1: LSB first, per SPI standard.
Note that the user must always change the LSB/MSB order in single-byte
instructions to avoid erratic behavior due to bit order errors.
Reset
Execute software reset of SPI and controllers, reload default register values except
Register 0x00.
1: sets software reset; write 0 on the next (or any following) cycle to release reset.
0 (default): the SPI instruction word uses a 5-bit address.
1: the SPI instruction word uses a 13-bit address.
0 (default): LDO voltage regulator on.
4
7
6
5
4
3
2
1
0
7
5
4
3
2
LNGINS
LDOOFF
LDOSTAT
PWRDN
Q DACOFF
I DACOFF
QCLKOFF
ICLKOFF
EXTREF
0x01
Power-Down
1: turns core LDO voltage regulator off.
0: indicates that the core LDO voltage regulator is off.
1 (default) : indicates that the core LDO voltage regulator is on.
0 (default): all analog and digital circuitry and SPI logic are powered on.
1: powers down all analog and digital circuitry except for SPI logic.
0 (default): turns on Q DAC output current.
1: turns off Q DAC output current.
0 (default): turns on I DAC output current.
1: turns off I DAC output current.
0 (default): turns on Q DAC clock.
1: turns off Q DAC clock.
0 (default): turns on I DAC clock.
1: turns off I DAC clock.
0 (default): turns on internal voltage reference.
1: powers down internal voltage reference (external reference required).
0 (default): unsigned binary input data format.
1: twos complement input data format.
Data Control
0x02
TWOS
IFIRST
0: pairing of data—Q first of pair on data input pads.
1 (default): pairing of data—I first of pair on data input pads.
0: Q data latched on DCLKIO rising edge.
IRISING
1 (default): I data latched on DCLKIO rising edge.
0 (default): allows simultaneous input and output enable on DCLKIO.
1: disallows simultaneous input and output enable on DCLKIO.
Controls the use of the DCLKIO pad for data clock input.
0: data clock input disabled.
SIMULBIT
DCI_EN
1 (default): data clock input enabled.
1
0
DCOSGL
DCODBL
Controls the use of the DCLKIO pad for data clock output.
0 (default): data clock output disabled.
1: data clock output enabled; regular strength driver.
Controls the use of the DCLKIO pad for data clock output.
0 (default): DCODBL data clock output disabled.
1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive
current.
I DAC Gain
0x03
5:0
I DACGAIN[5:0]
DAC I fine gain adjustment; alters the full-scale current as shown in Figure 100.
Default IDACGAIN = 0x00.
Rev. B | Page 36 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Register
Address Bit
Name
Description
IRSET
0x04
7
IRSETEN
0 (default): IRSET resistor value for I channel is set by an external resistor connected
to the FADJI/AUXI pin. Nominal value for this external resistor is 16 kΩ.
1: enables the on-chip IRSET value to be changed for I channel.
5:0
IRSET[5:0]
Changes the value of the on-chip IRSET resistor for I channel; this scales the full-scale
current of the DAC in ~0.25 dB steps twos complement (nonlinear); see Figure 99.
000000 (default): IRSET = 16 kΩ.
011111: IRSET = 32 kΩ.
100000: IRSET = 8 kΩ.
111111: IRSET = 16 kΩ.
IRCML
0x05
7
IRCMLEN
0 (default): IRCML resistor value for the I channel is set by an external resistor
connected to the CMLI pin. Recommended value for this external resistor is 0 Ω.
1: enables on-chip IRCML adjustment for I channel.
5:0
IRCML[5:0]
Changes the value of the on-chip IRCML resistor for I channel; this adjusts the
common-mode level of the DAC output stage.
000000 (default): IRCML = 250 Ω.
100000: IRCML= 625 Ω.
111111: IRCML = 1 kΩ.
Q DAC Gain
QRSET
0x06
0x07
5:0
7
Q DACGAIN[5:0] DAC Q fine gain adjustment; alters the full-scale current as shown in Figure 100.
Default QDACGAIN = 0x00.
QRSETEN
0 (default): QRSET resistor value for Q channel is set by an external resistor connected
to the FADJQ/AUXQ pin. Recommended value for this external resistor is 16 kΩ.
1: enables on-chip QRSET adjustment for Q channel.
5:0
QRSET[5:0]
Changes the value of the on-chip QRSET resistor for Q channel; this scales the full-
scale current of the DAC in ~0.25 dB steps twos complement (nonlinear); see
Figure 99.
000000 (default): QRSET = 16 kΩ.
011111: QRSET = 32 kΩ.
100000: QRSET = 8 kΩ.
111111: QRSET = 16 kΩ.
QRCML
0x08
7
QRCMLEN
0 (default): QRCML resistor value for the Q channel is set by an external resistor
connected to CMLQ pin. Recommended value for this external resistor is 0 Ω.
1: enables on-chip QRCML adjustment for Q channel.
5:0
QRCML[5:0]
Changes the value of the on-chip QRCML resistor for Q channel; this adjusts the
common-mode level of the DAC output stage.
000000 (default): QRCML = 250 Ω.
100000: QRCML = 625 Ω.
111111: QRCML = 1 kΩ.
AUXDAC Q
AUX CTLQ
0x09
0x0A
7:0
QAUXDAC[7:0]
AUXDAC Q output voltage adjustment word LSBs.
0x3FF: sets AUXDAC Q output to full scale.
0x200: sets AUXDAC Q output to midscale.
0x000 (default): sets AUXDAC Q output to bottom of scale.
0 (default): AUXDAC Q output disabled.
7
QAUXEN
1: enables AUXDAC Q output.
6:5
QAUXRNG[1:0]
00 (default): sets AUXDAC Q output voltage range to 2 V.
01: sets AUXDAC Q output voltage range to 1.5 V.
10: sets AUXDAC Q output voltage range to 1.0 V.
11: sets AUXDAC Q output voltage range to 0.5 V.
000 (default): sets AUXDAC Q top of range to 1.0 V.
001: sets AUXDAC Q top of range to 1.5 V.
010: sets AUXDAC Q top of range to 2.0 V.
011: sets AUXDAC Q top of range to 2.5 V.
100: sets AUXDAC Q top of range to 2.9 V.
AUXDAC Q output voltage adjustment word MSBs (default = 00).
4:2
1:0
QAUXOFS[2:0]
QAUXDAC[9:8]
Rev. B | Page 37 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Register
Address Bit
Name
Description
AUXDAC I
0x0B
7:0
IAUXDAC[7:0]
AUXDAC I output voltage adjustment word LSBs.
0x3FF: sets AUXDAC I output to full scale.
0x200: sets AUXDAC I output to midscale.
0x000 (default): sets AUXDAC I output to bottom of scale.
0 (default): AUXDAC I output disabled.
AUX CTLI
0x0C
7
IAUXEN
1: enables AUXDAC I output.
6:5
IAUXRNG[1:0]
00 (default): sets AUXDAC I output voltage range to 2 V.
01: sets AUXDAC I output voltage range to 1.5 V.
10: sets AUXDAC I output voltage range to 1.0 V.
11: sets AUXDAC I output voltage range to 0.5 V.
000 (default): sets AUXDAC I top of range to 1.0 V.
001: sets AUXDAC I top of range to 1.5 V.
010: sets AUXDAC I top of range to 2.0 V.
011: sets AUXDAC I top of range to 2.5 V.
100: sets AUXDAC I top of range to 2.9 V.
AUXDAC I output voltage adjustment word MSBs (default = 00).
4:2
IAUXOFS[2:0]
1:0
5:0
IAUXDAC[9:8]
RREF[5:0]
Reference
Resistor
0x0D
0x0E
Permits an adjustment of the on-chip reference voltage and output at REFIO (see
Figure 98) twos complement.
000000 (default): sets the value of RREF to 10 kΩ, VREF = 1.0 V.
011111: sets the value of RREF to 12 kΩ, VREF = 1.2 V.
100000: sets the value of RREF to 8 kΩ, VREF = 0.8 V.
111111: sets the value of RREF to 10 kΩ, VREF = 1.0 V.
0 (default): preload Q DAC calibration reference set to 32.
1: preload Q DAC calibration reference set by user (Cal Address 1).
0 (default): preload I DAC calibration reference set to 32.
1: preload I DAC calibration reference set by user (Cal Address 1).
0 (default): Q DAC self-calibration done.
1: select Q DAC self-calibration.
Cal Control
7
PRELDQ
PRELDI
6
5
CALSELQ
CALSELI
CALCLK
4
0 (default): I DAC self-calibration done.
1: select I DAC self-calibration.
3
0 (default): calibration clock disabled.
1: calibration clock enabled.
2:0
DIVSEL[2:0]
Calibration clock divide ratio from DAC clock rate.
000 (default): divide by 256.
001: divide by 128.
…
110: divide by 4.
111: divide by 2.
Cal Memory
0x0F
7
CALSTATQ
0 (default): Q DAC calibration in progress.
1: calibration of Q DAC complete.
0 (default): I DAC calibration in progress.
1: calibration of I DAC complete.
6
CALSTATI
3:2
CALMEMQ[1:0]
Status of Q DAC calibration memory.
00 (default): uncalibrated.
01: self-calibrated.
10: user calibrated.
1:0
CALMEMI[1:0]
Status of I DAC calibration memory.
00 (default): uncalibrated.
01: self-calibrated.
10: user calibrated.
Memory Address 0x10
Memory Data 0x11
5:0
5:0
MEMADDR[5:0]
MEMDATA[5:0]
Address of static memory to be accessed.
Data for static memory access.
Rev. B | Page 38 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Register
Address Bit
Name
Description
Memory R/W
0x12
7
CALRSTQ
0 (default): no action.
1: clear CALSTATQ.
0 (default): no action.
1: clear CALSTATI.
0 (default): no action.
6
CALRSTI
CALEN
4
1: initiate device self-calibration.
3
SMEMWR
SMEMRD
UNCALQ
UNCALI
0 (default): no action.
1: write to static memory (calibration coefficients).
0 (default): no action.
2
1: read from static memory (calibration coefficients).
0 (default): no action.
1
1: reset Q DAC calibration coefficients to default (uncalibrated).
0 (default): no action.
0
1: reset I DAC calibration coefficients to default (uncalibrated).
CLKMODE
0x14
7:6
CLKMODEQ[1:0] Depending on the CLKMODEN bit setting, these two bits reflect the phase
relationship between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
4
Searching
Data path retimer status bit.
0 (default): clock relationship established.
1: indicates that the internal data path retimer is searching for clock relationship
(device output is not usable while this bit is high).
3
2
Reacquire
Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
CLKMODEN
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and
read back in CLKMODEI[1:0] and CLKMODEQ[1:0].
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers.
1:0
7:0
CLKMODEI[1:0]
Version[7:0]
Depending on CLKMODEN bit setting, these two bits reflect the phase
relationship between DCLKIO and CLKIN as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Version
0x1F
Hardware version of the device. This register is set to 0x03 for the latest version of
the device.
Rev. B | Page 39 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
DIGITAL INTERFACE OPERATION
Digital data for the I and Q DACs is supplied over a single
parallel bus (DB[n:0), where n is 7 for the AD9714, 9 for
the AD9715, 11 for the AD9716, and 13 for the AD9717)
accompanied by a qualifying clock (DCLKIO). The I and Q
data are provided to the chip in an interleaved double data
rate (DDR) format. The maximum guaranteed data rate is
±50 MSPS with a 1±5 MHz clock. The order of data pairing
and the sampling edge selection is user programmable using
the IFIRST and IRISING data control bits, resulting in four
possible timing diagrams. These are shown in Figure 89,
Figure 90, Figure 91, and Figure 9±.
DCLKIO
DB[n:0]
I DATA
Z
A
B
C
D
E
F
G
H
Z
B
D
F
Q DATA
NOTES:
A
C
E
G
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0
DCLKIO
DCLKIO
DB[n:0]
I DATA
Z
A
B
C
D
E
F
G
H
DB[n:0]
I DATA
Z
A
B
C
D
E
F
G
H
Z
B
D
F
E
Y
A
C
E
F
Q DATA
NOTES:
Y
A
C
Q DATA
NOTES:
Z
B
D
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1
DCLKIO
Ideally, the rising and falling edges of the clock fall in the center
of the keep-in-window formed by the setup and hold times, tS
and tH. Refer to Table ± for setup and hold times. A detailed
timing diagram is shown in Figure 93.
DB[n:0]
I DATA
Z
A
B
C
D
E
F
G
H
Y
A
C
E
D
DCLKIO
Q DATA
NOTES:
X
Z
B
tS tH
tS tH
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE AD9715, 11 FOR THE
AD9716, AND 13 FOR THE AD9717.
DB[n:0]
NOTES:
Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1
1. DB[n:0], WHERE n IS 7 FOR THE AD9714, 9 FOR THE
AD9715, 11 FOR THE AD9716, AND 13 FOR THE AD9717.
Figure 93. Setup and Hold Times for All Input Modes
In addition to the different timing modes listed in Table ±, the
input data can also be presented to the device in either unsigned
binary or twos complement format. The format type is chosen
via the TWOS data control bit.
Rev. B | Page 40 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
OR
RETIMER-CLK
D-FF
D-FF
D-FF
1
D-FF
2
D-FF
3
D-FF
5
0
4
TO DAC CORE
CLKIN-INT
I
OUT
DB[n:0]
(INPUT)
DCLKIO-INT
I
OUT
NOTES
D-FFs:
0: RISING OR FALLING EDGE
TRIGGERED FOR I OR Q DATA.
1, 2, 3, 4: RISING EDGE TRIGGERED.
IE
IE
OE
DELAY2
DCLKIO
(INPUT/OUTPUT)
CLKIN
(INPUT)
Figure 94. Simplified Diagram of AD9714/AD9715/AD9716/AD9717 Timing
Setting Bit 1 or Bit 0 of SPI Address 0x02, DCOSGL or DCODBL,
respectively, to logic high allows the user to obtain a DCLKIO
output from the CLKIN input for use in the user’s PCB system.
DIGITAL DATA LATCHING AND RETIMER BLOCK
The AD9714/AD9715/AD9716/AD9717 have two clock inputs,
DCLKIO and CLKIN. The CLKIN is the analog clock whose
jitter affects DAC performance, and the DCLKIO is a digital
clock from an FPGA that needs to have a fixed relationship with
the input data to ensure that the data is picked
It is strongly recommended that DCI_EN = DCOSGL = high or
DCI_EN = DCODBL = high not be used even though the
device may appear to function correctly. Similarly, do not set
DCOSGL and DCODBL to logic high simultaneously.
up correctly by the flip-flops on the pads.
Retimer
Figure 94 is a simplified diagram of the entire data capture
system in the AD9714/AD9715/AD9716/AD9717. The double
data rate input data (DB[n:0), where n is 7 for the AD9714, 9
for the AD9715, 11 for the AD9716, and 13 for the AD9717) is
latched at the pads/pins either on the rising edge or the falling edge
of the DCLKIO-INT clock, as determined by IRISING, Bit 4 of
SPI Address 0x02. Bit 5 of SPI Address 0x02, IFIRST, determines
which channel data is latched first (that is, I or Q). The captured
data is then retimed to the internal clock (CLKIN-INT) in the
retimer block before being sent to the final analog DAC core
(D-FF 4), which controls the current steering output switches. All
delay blocks depicted in Figure 94 are noninverting, and any wires
without an explicit delay block can be assumed to have no delay.
The AD9714/AD9715/AD9716/AD9717 have an internal data
retimer circuit that compares the CLKIN-INT and DCLKIO-INT
clocks and, depending on their phase relationship, selects a
retimer clock (RETIMER-CLK) to safely transfer data from
the DCLKIO used at the chip’s input interface to the CLKIN
used to clock the analog DAC cores (D-FF 4).
The retimer selects one of the three phases shown in Figure 95.
The retimer is controlled by the CLKMODE SPI bits, as shown
in Table 15.
RETIMER-CLKs
1/2 PERIOD
DATA
CLOCK
180°
90°
270°
Only one channel is shown in Figure 94 with the data pads
(DB[n:0), where n is 7 for the AD9714, 9 for the AD9715, 11 for
the AD9716, and 13 for the AD9717) serving as double data
rate pads for both channels.
1/4 PERIOD 1/2 PERIOD
Figure 95. RETIMER-CLK Phases
Note that, in most cases, more than one retimer phase works
and ,in such cases, the retimer arbitrarily picks one phase that
works. The retimer cannot pick the best or safest phase. If the
user has a working knowledge of the exact phase relationship
between DCLKIO and CLKIN (and thus DCLKIO-INT and
CLKIN-INT because the delay is approximately the same for
both clocks and equal to DELAY1), then the retimer can be
forced to this phase with CLKMODEN = 1, as described in
Table 15 and the following paragraphs.
The default PINMD and SPI settings are IE = high (closed)
and OE = low (open). These settings are enabled when RESET/
PINMD (Pin 35) is held high. In this mode, the user has to supply
both DCLKIO and CLKIN. In PINMD, it is also recommended
that the DCLKIO and the CLKIN be in phase for proper func-
tioning of the DAC, which can easily be ensured by tying the
pins together on the PCB. If the user can access the SPI, setting
Bit 2 of SPI Address 0x02, DCI_EN, to logic low causes the
CLKIN to be used as the DCLKIO also.
Rev. B | Page 41 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Table 15. Timer Register List
Bit Name
Description
CLKMODEQ[1:0] Q data path retimer clock selected output. Valid after the searching bit goes low.
Searching
Reacquire
CLKMODEN
High indicates that the internal data path retimer is searching for the clock relationship (DAC is not usable until it is low again).
Changing this bit from 0 to 1 causes the data path retimer circuit to reacquire the clock relationship.
0: uses CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking.
1: uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both I and Q retimers (that is, force the retimer).
I data path retimer clock selected output. Valid after searching goes low.
CLKMODEI[1:0]
If CLKMODEN = 1, a value written to this register overrides both the I and Q automatic retimer values.
Table 16. CLKMODEI/CLKMODEQ Details
CLKMODEI[1:0]/CLKMODEQ[1:0] DCLKIO-to-CLKIN Phase Relationship
RETIMER-CLK Selected
Phase 2
00
01
10
11
0° to 90°
90° to 180°
180° to 270°
270° to 360°
Phase 3
Phase 3
Phase 1
When RESET is pulsed high and then returns low (the part is in
SPI mode), the retimer runs and automatically selects a suitable
clock phase for the RETIMER-CLK within 128 clock cycles. The
SPI searching bit, Bit 4 of SPI Address 0x14, returns to low,
indicating that the retimer has locked and the part is ready for
use. The reacquire bit, Bit 3 of SPI Address 0x14, can be used to
reinitiate phase detection in the I and Q retimers at any time.
CLKMODEQ[1:0] and CLKMODEI[1:0] of SPI Address 0x14
provide readback for the values picked by the internal phase
detectors in the retimer (see Table 16).
ESTIMATING THE OVERALL DAC PIPELINE DELAY
DAC pipeline latency is affected by the phase of the RETIMER-
CLK that is selected. If latency is critical to the system and must
be constant, the retimer should be forced to a particular phase and
not be allowed to automatically select a phase each time.
Consider the case in which DCLKIO = CLKIN (that is, in
phase), and the RETIMER-CLK is forced to Phase 2. Assume
that IRISING is 1 (that is, I data is latched on the rising edge
and Q data is latched on the falling edge). Then the latency to the
output for the I channel is four clock cycles total; one clock cycle
from the input interface (D-FF 1, not D-FF0, as it latches data
on either edge and does not cause any delay); two clock cycles
from the retimer (D-FF 2 and D-FF 4, but not D-FF 3, because
it is latched on the half clock cycle or 180°); and one clock cycle
going through the analog core (D-FF 5). The latency to the output
for the Q channel from the time the falling edge latches it at the
pads in D-FF 0 is 3.5 clock cycles (no delay due to D-FF0, 1 clock
cycle due to D-FF 1, ½ clock cycle to D-FF 2, 1 clock cycle to D-
FF 4, and 1 clock cycle to D-FF 5). This latency for the AD9714/
AD9715/AD9716/AD9717 is case specific and needs to be calcu-
lated based on the RETIMER-CLK phase that is automatically
selected or manually forced.
To force the two retimers (I and Q) to pick a particular phase
for the retimer clock (they must both be forced to the same
value), CLKMODEN, Bit 2 of SPI Address 0x14, should be set
high and the required phase value is written into CLKMODEI[1:0]
and CLKMODEQ[1:0]. For example, if the DCLKIO and the
CLKIN are in phase to the first order, the user can safely force the
retimers to pick Phase 2 for the RETIMER-CLK. This forcing
function may be useful for synchronizing multiple devices.
In pin mode, it is expected that the user tie CLKIN and DCLKIO
together. The device has a small amount of programmable
CS
functionality using the unused SPI pins (SCLK, SDIO, and ).
If the two chip clocks are tied together, the SCLK pin can be
tied to ground, and the chip uses a clock for the retimer that is
180° out of phase with the two input clocks (that is, Phase 2,
which is the safest and best option). The chip has an additional
option in pin mode when the redefined SCLK pin is high. Use
this mode if using pin mode, but CLKIN and DCLKIO are not
tied together (that is, not in phase). Holding SCLK high causes
the internal clock detector to use the phase detector output to
determine which clock to use in the retimer (that is, select a
suitable RETIMER-CLK phase). The action of taking SCLK
high causes the internal phase detector to reexamine the two
clocks and determine the relative phase. Whenever the user
wants to reevaluate the relative phase of the two clocks, the
SCLK pin can be taken low and then high again.
Rev. B | Page 42 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
REFERENCE OPERATION
REFERENCE CONTROL AMPLIFIER
The AD9714/AD9715/AD9716/AD9717 contain an internal
1.0 V band gap reference. The internal reference can be disabled
by setting Bit 0 (EXTREF) of the power-down register (Address
0x01) through the SPI interface. To use the internal reference,
decouple the REFIO pin to AVSS with a 0.1 μF capacitor, enable
the internal reference, and clear Bit 0 of the power-down register
(Address 0x01) through the SPI interface. Note that this is the
default configuration. The internal reference voltage is present
at REFIO. If the voltage at REFIO is to be used anywhere else in
the circuit, an external buffer amplifier with an input bias current
of less than 100 nA must be used to avoid loading the reference.
An example of the use of the internal reference is shown in
Figure 96.
The AD9714/AD9715/AD9716/AD9717 contain a control
amplifier that regulates the full-scale output current, IxOUTFS
.
The control amplifier is configured as a V-I converter, as shown
in Figure 96. The output current, IxREF, is determined by the
ratio of the VREFIO and an external resistor, xRSET, as stated in
Equation 4 (see the DAC Transfer Function section). IxREF, is
mirrored to the segmented current sources with the proper scale
factor to set IxOUTFS, as stated in Equation 3.
The control amplifier allows a 2.5:1 adjustment span of IxOUTFS
from 1 mA to 4 mA by setting IxREF between 125 μA and 31.25 μA
(set xRSET between 8 kΩ and 32 kΩ). The wide adjustment span
of IxOUTFS provides several benefits. The first relates directly to
the power dissipation of the AD9714/AD9715/AD9716/AD9717,
which is proportional to IxOUTFS (see the DAC Transfer Function
section). The second benefit relates to the ability to adjust the
output over a 8 dB range with 0.25 dB steps, which is useful for
controlling the transmitted power. The small signal bandwidth
of the reference control amplifier is approximately 500 kHz.
This allows the device to be used for low frequency, small signal
multiplying applications.
AD9714/AD9715/
AD9716/AD9717
I DAC
OR
V
BG
1.0V
Q DAC
REFIO
–
+
FSADJx
CURRENT
SCALING
×32
0.1µF
I
xOUTFS
xR
SET
When an external resistor greater than 16 kΩ is used on the
FSADJx pins, care must be taken to maintain the high frequency
equivalent circuit to an impedance lower than 16 kΩ by
splitting the resistor into two resistors in series with a 10 nF
capacitor in parallel with the resistor to AVSS (see Figure 97).
I
xREF
AVSS
Figure 96. Internal Reference Configuration
REFIO serves as either an input or an output, depending on
whether the internal or an external reference is used. Table 17
summarizes the reference operation.
AD9714/AD9715/
AD9716/AD9717
REFIO
Table 17. Reference Operation
Reference Mode
REFIO Pin
Connect 0.1 µF Register 0x01, Bit 0 = 0
capacitor (default)
Apply external Register 0x01, Bit 0 = 1
capacitor (for power saving)
Register Setting
FSADJx
0.1µF
Internal
R < 16kΩ
External
xR
SET
10nF
An external reference can be used in applications requiring
tighter gain tolerances or lower temperature drift. Also, a
variable external voltage reference can be used to implement a
method for gain control of the DAC output.
AVSS
Figure 97. xRSET Configuration for Values > 16 kΩ
Recommendations When Using an External Reference
Apply the external reference to the REFIO pin. The internal
reference can be directly overdriven by the external reference,
or the internal reference can be powered down to save power
consumption
The external 0.1 μF compensation capacitor on REFIO is not
required unless specified by the external voltage reference
manufacturer. The input impedance of REFIO is 10 kΩ when
the internal reference is powered up and 1 MΩ when it is
powered down.
Rev. B | Page 43 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Substituting the values of IOUTP, IOUTN, and IxREF, VIDIFF can
be expressed as
DAC TRANSFER FUNCTION
The AD9714/AD9715/AD9716/AD9717 provide two differen-
tial current outputs, IOUTP/IOUTN and QOUTP/QOUTN.
IOUTP and QOUTP provide a near full-scale current output,
VIDIFF = {(2 × IDAC CODE – (2N − 1))/2N} ×
(8)
(32 × VREFIO/IRSET) × IRLOAD
I
xOUTFS, when all bits are high (that is, DAC CODE = 2N − 1,
Equation 8 highlights some of the advantages of operating the
AD9714/AD9715/AD9716/AD9717 differentially. First, the
differential operation helps cancel common-mode error sources
associated with IOUTP and IOUTN, such as noise, distortion,
and dc offsets. Second, the differential code-dependent current and
subsequent voltage, VIDIFF, is twice the value of the single-ended
voltage output (that is, VIOUTP or VIOUTN), thus providing twice
the signal power to the load. Note that the gain drift temperature
performance for a single-ended output (VIOUTP and VIOUTN) or
differential output (VIDIFF) of the AD9714/AD9715/AD9716/
AD9717 can be enhanced by selecting temperature-tracking
resistors for xRLOAD and xRSET because of their ratiometric
relationship, as shown in Equation 8.
where N = 8, 10, 12, or 14 for the AD9714, AD9715, AD9716,
and AD9717, respectively), while IOUTN and QOUTN, the
complementary outputs, provide no current. The current
outputs appearing at the positive DAC outputs, IOUTP and
QOUTP, and at the negative DAC outputs, IOUTN and QOUTN,
are a function of both the input code and IxOUTFS and can be
expressed as follows:
IOUTP = (IDAC CODE/2N) × IIOUTFS
(1)
QOUTP = (QDAC CODE/2N) × IQOUTFS
IOUTN = ((2N − 1) − IDAC CODE)/2N × IIOUTFS
QOUTN = ((2N − 1) − QDAC CODE)/2N × IQOUTFS
(2)
where:
IDAC CODE and QDAC CODE = 0 to 2N − 1 (that is, decimal
ANALOG OUTPUT
The complementary current outputs in each DAC, IOUTP/
IOUTN and QOUTP/QOUTN, can be configured for single-
ended or differential operation. IOUTP/IOUTN and QOUTP/
QOUTN can be converted into complementary single-ended
voltage outputs, VIOUTP and VIOUTN, as well as VQOUTP and VQOUTN
via a load resistor, xRLOAD, as described in the DAC Transfer
Function section by Equation 6 through Equation 8. The differen-
representation).
IIOUTFS and IQOUTFS are functions of the reference currents, IIREF
and IQREF, respectively, which are nominally set by a reference
voltage, VREFIO, and external resistors, IRSET and QRSET, respec-
tively. IIOUTFS and IQOUTFS can be expressed as follows:
IIOUTFS = 32 × IIREF
IQOUTFS = 32 × IQREF
(3)
tial voltages, VIDIFF and VQDIFF, existing between VIOUTP and VIOUTN
,
and VQOUTP and VQOUTN, can also be converted to a single-ended
voltage via a transformer or a differential amplifier configuration.
The ac performance of the AD9714/AD9715/AD9716/AD9717
is optimum and is specified using a differential transformer-
coupled output in which the voltage swing at IOUTP and IOUTN
is limited to 0.5 V. The distortion and noise performance of
the AD9714/AD9715/AD9716/AD9717 can be enhanced when
it is configured for differential operation. The common-mode
error sources of both IOUTP/IOUTN and QOUTP/QOUTN
can be significantly reduced by the common-mode rejection
of a transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed wave-
form increases and/or its amplitude increases. This is due to
the first-order cancellation of various dynamic common-mode
distortion mechanisms, digital feedthrough, and noise. Performing
a differential-to-single-ended conversion via a transformer also
provides the ability to deliver twice the reconstructed signal
power to the load (assuming no source termination). Because
the output currents of IOUTP/IOUTN and QOUTP/QOUTN
are complementary, they become additive when processed
differentially.
where:
IIREF = VREFIO/IRSET
IQREF = VREFIO/QRSET
(4)
(5)
or
IIOUTFS = 32 × VREFIO/IRSET
I
QOUTFS = 32 × VREFIO/QRSET
A differential pair (IOUTP/IOUTN or QOUTP/QOUTN)
typically drives a resistive load directly or via a transformer. If
dc coupling is required, the differential pair (IOUTP/IOUTN or
QOUTP/QOUTN) should be connected to matching resistive
loads, xRLOAD, that are tied to analog common, AVSS. The
single-ended voltage output appearing at the positive and
negative nodes is
VIOUTP = IOUTP × IRLOAD
VQOUTP = QOUTP × QRLOAD
VIOUTN = IOUTN × IRLOAD
VQOUTN = QOUTN × QRLOAD
(6)
(7)
To achieve the maximum output compliance of 1 V at the
nominal 4 mA output current, IRLOAD = QRLOAD must be set
to 250 Ω.
Rev. B | Page 44 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
The AD9714/AD9715/AD9716/AD9717 allow reading and
writing of the calibration coefficients. There are 32 coefficients
in total. The read/write feature of the coefficients can be useful
for improving the results of the self-calibration routine by
averaging the results of several self-calibration cycles and
loading the averaged results back into the device.
SELF-CALIBRATION
The AD9714/AD9715/AD9716/AD9717 have a self-calibration
feature that improves the DNL of the device. Performing a self-
calibration on the device improves device performance in low
frequency applications. The device performance in applications
where the analog output frequencies are above 5 MHz are generally
influenced more by dynamic device behavior than by DNL and,
in these cases, self-calibration is unlikely to provide much benefit.
The calibration clock frequency is equal to the DAC clock
divided by the division factor chosen by the DIVSEL value. Each
calibration clock cycle is between 32 and 2048 DAC input clock
cycles, depending on the value of DIVSEL[2:0] (Register 0x0E,
Bits[2:0]). The frequency of the calibration clock should be
between 0.5 MHz and 4 MHz for reliable calibrations. Best
results are obtained by setting DIVSEL[2:0] (Register 0x0E,
Bits[2:0]) to produce a calibration clock frequency between
these values. Separate self-calibration hardware is included
for each DAC. The DACs can be self-calibrated individually or
simultaneously.
To read the calibration coefficients, use the following steps:
1. Select which DAC core to read by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Write the address of the first
coefficient (0x01) to Register 0x10.
2. Set the SMEMRD bit (Register 0x12, Bit 2) by writing 0x04
to Register 0x12.
3. Read the 6-bit value of the first coefficient by reading the
contents of Register 0x11.
4. Clear the SMEMRD bit by writing 0x00 to Register 0x12.
5. Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by 1 for each read.
6. Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
To perform a device self-calibration, the following procedure
can be used:
1. Write 0x00 to Register 0x12. This ensures that the
UNCALI and UNCALQ bits are reset.
To write the calibration coefficients to the device, use the
following steps:
2. Set up a calibration clock between 0.5 MHz and 4 MHz
using DIVSEL[2:0], and then enable the calibration clock
by setting the CALCLK bit (Register 0x0E, Bit 3).
3. Select the DAC(s) to self-calibrate by setting either Bit 4
(CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the
Q DAC in Register 0x0E. Note that each DAC contains
independent calibration hardware so that they can be
calibrated simultaneously.
1. Select which DAC core to write to by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q
DAC in Register 0x0E.
2. Set the SMEMWR bit (Register 0x12, Bit 3) by writing 0x08
to Register 0x12.
3. Write the address of the first coefficient (0x01) to
Register 0x10.
4. Write the value of the first coefficient to Register 0x11.
5. Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by one for each
write.
4. Start self-calibration by setting the CALEN bit (Register 0x12,
Bit 4). Wait approximately 300 calibration clock cycles.
5. Check if the self-calibration has completed by reading
the CALSTATI bit (Bit 6) and CALSTATQ bit (Bit 7) in
Register 0x0F. Logic 1 indicates that the calibration has
completed.
6. Clear the SMEMWR bit by writing 0x00 to Register 0x12.
7. Deselect the DAC core by clearing either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
6. When the self-calibration has completed, write 0x00 to
Register 0x12.
7. Disable the calibration clock by clearing the CALCLK bit
(Register 0x0E, Bit 3).
Rev. B | Page 45 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Option 3
COARSE GAIN ADJUSTMENT
Even when the device is in pin mode, full-scale values can be
adjusted by sourcing or sinking current from the FSADJx pins.
Any noise injected here appears as amplitude modulation of the
output. Thus, a portion of the required series resistance (at least
±0 kꢁ) must be installed right at the pin. A range of ±10ꢀ is
quite practical using this method.
Option 1
A coarse full-scale output current adjustment can be achieved
using the lower six bits in Register 0x0D. This adds or subtracts
up to ±0ꢀ from the band gap voltage on Pin 34 (REFIO), and
the voltage on the FSADJx resistors tracks this change. As a
result, the DAC full-scale current varies by the same amount.
A secondary effect to changing the REFIO voltage is that the
full-scale voltage in the AUXDAC also changes by the same
magnitude. The register uses twos complement format, in
which 011111 maximizes the voltage on the REFIO node
and 100000 minimizes the voltage.
Option 4
As in Option 3, when the device is in pin mode, both full-scale
values can be adjusted by sourcing or sinking current from the
REFIO pin. Noise injected here appears as amplitude modulation
of the output; therefore, a portion of the required series resis-
tance (at least 10 kꢁ) must be installed at the pin. A range of
±±5ꢀ is quite practical when using this method.
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
Fine Gain
Each main DAC has independent fine gain control using the
lower six bits in Register 0x03 (I DAC gain) and Register 0x06
(Q DAC gain). Unlike Coarse Gain Option 1, this impacts only
the main DAC full-scale output current. These registers use straight
binary format. One application in which straight binary format
is critical is for side-band suppression while using a quadrature
modulator. This is described in more detail in the Applications
Information section.
2.22
0
8
16
24
32
40
48
56
3.3V DAC1
CODE
3.3V DAC2
1.8V DAC1
2.20
Figure 98. Typical VREF Voltage vs. Code
1.8V DAC2
Option 2
2.18
While using the internal FSADJx resistors, each main DAC can
achieve independently controlled coarse gain using the lower
six bits of Register 0x04 (IRSET[5:0]) and Register 0x07
(QRSET[5:0]). Unlike Coarse Gain Option 1, this impacts only
the main DAC full-scale output current. The register uses twos
complement format and allows the output current to be changed
in approximately 0.±5 dB steps.
2.16
2.14
2.12
2.10
4.0
0
8
16
24
32
40
48
56
64
GAIN DAC CODE
3.5
3.0
Figure 100. Typical DAC Gain Characteristics
V
_
OR V _
OUT I
OUT
Q
2.5
2.0
1.5
1.0
0.5
0
0
10
20
30
40
50
60
xR
CODE
SET
Figure 99. Effect of xRSET Code
Rev. B | Page 46 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
1200
1100
1000
900
800
700
600
500
400
300
200
USING THE INTERNAL TERMINATION RESISTORS
The AD9717/AD9716/AD9715/AD9714 have four 500 ꢁ
termination internal resistors (two for each DAC output).
To use these resistors to convert the DAC output current to a
voltage, connect each DAC output pin to the adjacent load pin.
For example, on the I DAC, IOUTP must be shorted to RLIP
and IOUTN must be shorted to RLIN. In addition, the CMLI
or CMLQ pin must be connected to ground directly or through
a resistor. If the output current is at the nominal ± mA and the
CMLI or CMLQ pin is tied directly to ground, this produces a
dc common-mode bias voltage on the DAC output equal to 0.5 V.
If the DAC dc bias must be higher than 0.5 V, an external
resistor can be connected between the CMLI or CMLQ pin and
ground. This part also has an internal common-mode resistor
that can be enabled. This is explained in the Using the Internal
Common-Mode Resistor section.
0
8
16
24
32
40
48
56
CODE
Figure 102. Typical CML Resistor Value vs. Register Code
Using the CMLx Pins for Optimal Performance
CML
The CMLx pins also serve to change the DAC bias voltages
in the parts allowing them to run at higher dc output bias
voltages. When running the bias voltage below 0.9 V and an
AVDD of 3.3 V, the parts perform optimally when the CMLx
pins are tied to ground. When the dc bias increases above 0.9 V,
set the CMLx pins at 0.5 V for optimal performance. The maxi-
mum dc bias on the DAC output should be kept at or below 1.± V
when the supply is 3.3 V. When the supply is 1.8 V, keep the dc
bias close to 0 V and connect the CMLx pins directly to ground.
R
CML
RLIN
500Ω
500Ω
IOUTN
IOUTP
RLIP
I DAC
OR
Q DAC
Figure 101. Simplified Internal Load Options
Using the Internal Common-Mode Resistor
These devices contain an adjustable internal common-mode
resistor that can be used to increase the dc bias of the DAC
outputs. By default, the common-mode resistor is not con-
nected. When enabled, it can be adjusted from ~±50 ꢁ to
~1 kꢁ. Each main DAC has an independent adjustment
using the lower six bits in Register 0x05 (IRCML[5:0]) and
Register 0x08 (QRCML[5:0]).
Rev. B | Page 47 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
APPLICATIONS INFORMATION
OUTPUT CONFIGURATIONS
A differential resistor, RDIFF, can be inserted in applications
where the output of the transformer is connected to the load,
RLOAD, via a passive reconstruction filter or cable. RDIFF, as
reflected by the transformer, is chosen to provide a source
termination that results in a low voltage standing wave ratio
(VSWR). Note that approximately half the signal power is
The following sections illustrate some typical output confi-
gurations for the AD9714/AD9715/AD9716/AD9717. Unless
otherwise noted, it is assumed that IxOUTFS is set to a nominal
± mA. For applications requiring the optimum dynamic perfor-
mance, a differential output configuration is suggested. A
differential output configuration can consist of either an
RF transformer or a differential op amp configuration. The
transformer configuration provides the optimum high fre-
quency performance and is recommended for any application
that allows ac coupling. The differential op amp configuration
is suitable for applications requiring dc coupling, signal gain,
and/or a low output impedance.
dissipated across RDIFF
.
SINGLE-ENDED BUFFERED OUTPUT USING
AN OP AMP
An op amp such as the ADA4899-1 can be used to perform
a single-ended current-to-voltage conversion, as shown in
Figure 104. The AD9714/AD9715/AD9716/AD9717 are config-
ured with a pair of series resistors, RS, off each output. For best
distortion performance, RS should be set to 0 ꢁ. The feedback
resistor, RFB, determines the peak-to-peak signal swing by the
formula
A single-ended output is suitable for applications in which low
cost and low power consumption are primary concerns.
DIFFERENTIAL COUPLING USING A TRANSFORMER
VOUT = RFB × IFS
An RF transformer can be used to perform a differential-to-
single-ended signal conversion, as shown in Figure 103. The
distortion performance of a transformer typically exceeds
that available from standard op amps, particularly at higher
frequencies. Transformer coupling provides excellent rejection
of common-mode distortion (that is, even-order harmonics)
over a wide frequency range. It also provides electrical isolation
and can deliver voltage gain without adding noise. Transformers
with different impedance ratios can also be used for impedance
matching purposes. The main disadvantages of transformer
coupling are low frequency roll-off, lack-of-power gain, and
high output impedance.
The common-mode voltage of the output is determined by the
formula
RFB
RB
R
FB IFS
VCM VREF 1
2
The maximum and minimum voltages out of the amplifier are,
respectively,
RFB
RB
VMAX VREF 1
VMIN = VMAX – IFS × RFB
C
F
29
IOUTN
R
R
FB
B
AD9714/AD9715/
AD9716/AD9717
+5V
AD9714/AD9715/
AD9716/AD9717
R
LOAD
R
S
28
–
IOUTP
28
IOUTP
ADA4899-1
+
V
OUT
OPTIONAL R
DIFF
34
REFIO
C
R
–5V
S
Figure 103. Differential Output Using a Transformer
29
25
IOUTN
AVSS
The center tap on the primary side of the transformer must be
connected to a voltage that keeps the voltages on IOUTP and
IOUTN within the output common-mode voltage range of the
device. Note that the dc component of the DAC output current
is equal to IxOUTFS and flows out of both IOUTP and IOUTN.
The center tap of the transformer should provide a path for
this dc current. In most applications, AGND provides the most
convenient voltage for the transformer center tap. The complemen-
tary voltages appearing at IOUTP and IOUTN (that is, VIOUTP
and VIOUTN) swing symmetrically around AGND and should be
maintained with the specified output compliance range of the
AD9714/AD9715/AD9716/AD9717.
Figure 104. Single-Supply Single-Ended Buffer
Rev. B | Page 48 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
To keep the pin count reasonable, these auxiliary DACs each
share a pin with the corresponding FSADJx resistor. They are,
therefore, usable only when enabled and when that DAC is
operated on its internal full-scale resistors. A simple I-to-V
converter is implemented on chip with selectable shunt resistors
(3.± kꢁ to 16 kꢁ) such that if REFIO is set to exactly 1 V, REFIO/±
equals 0.5 V and the following equation describes the no load
output voltage:
DIFFERENTIAL BUFFERED OUTPUT
USING AN OP AMP
A dual op amp (see the circuit shown in Figure 105) can be used
in a differential version of the single-ended buffer shown in
Figure 104. The same RC network is used to form a one-pole
differential, low-pass filter to isolate the op amp inputs from
the high frequency images produced by the DAC outputs. The
feedback resistors, RFB, determine the differential peak-to-peak
signal swing by the formula
1.5
VOUT 0.5 V IDAC
16 k
RS
VOUT = ± × RFB × IFS
The maximum and minimum single-ended voltages out of the
amplifier are, respectively,
Figure 106 illustrates the function of all the SPI bits controlling
these DACs with the exception of the QAUXEN (Register 0x0A,
Bit 7) and IAUXEN (Register 0x0C, Bit 7) bits and gating to
prohibit RS < 3.± kꢁ.
RFB
RB
VMAX VREF 1
AVDD
RNG0
RNG1
VMIN = VMAX − RFB × IFS
RNG: 00 = > 125µA fS
01 = > 62µA fS
AUXDAC
[9:0]
10 = > 31µA fS
The common-mode voltage of the differential output is
determined by the formula
11 = > 16µA fS
(OFS > 4 = 4)
VCM = VMAX − RFB × IFS
OFS2
OFS1
OFS0
C
F
16kΩ
AUX
PIN
R
R
FB
B
4kΩ 8kΩ 16kΩ 16kΩ
–
AD9714/AD9715/
AD9716/AD9717
IOUTP
OP AMP
+
R
S
28
34
–
REFIO
2
ADA4841-2
+
REFIO
V
C
OUT
Figure 106. AUXDAC Simplified Circuit Diagram
AVSS
25
29
+
R
S
The SPI speed limits the update rate of the auxiliary DACs. The
data is inverted such that IAUXDAC is full scale at 0x000 and zero
at 0x1FF, as shown in Figure 107.
IOUTN
ADA4841-2
–
C
F
3.0
OP AMP OUTPUT VOLTAGE vs. CHANGES
2.8
R
R
IN R
AND DAC CURRENT IN µA
FB
B
OFFSET
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
R
R
R
R
R
= 3.3kΩ
= 4kΩ
= 5.3kΩ
= 8kΩ
OFFSET
OFFSET
OFFSET
OFFSET
OFFSET
Figure 105. Single-Supply Differential Buffer
AUXILIARY DACs
= 16kΩ
The DACs of the AD9714/AD9715/AD9716/AD9717 feature
two versatile and independent 10-bit auxiliary DACs suitable
for dc offset correction and similar tasks.
Because the AUXDACs are driven through the SPI port, they
should never be used in timing-critical applications, such
as inside analog feedback loops.
0
10 20 30 40 50 60 70 80 90 100 110 120 130
(µA)
I
AUXDAC
Figure 107. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V, No Load,
AUXDAC 0x1FF to 0x000
Rev. B | Page 49 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
ADL537x
FAMILY
AD9714/AD9715/
AD9716/AD9717
I OR Q DAC
OPTIONAL
LOW-PASS
FILTERING
Two registers are assigned to each DAC with 10 bits for the actual
DAC current to be generated, a 3-bit offset (and gain) adjust-
ment, a ±-bit current range adjustment, and an enable/disable
bit. Setting the QAUXOFS (Register 0x0A, Bits[4:±]) and
IAUXOFS (Register 0x0C, Bits[4:±]) bits to all 1s disables the
respective op amp and routes the DAC current directly to the
respective FSADJI/AUXI or FSADJQ/AUXQ pins. This is
especially useful when the loads to be driven are beyond the
limited capability of the on-chip amplifier.
1kΩ
I OR Q
INPUTS
500Ω
500Ω
AD9714/AD9715/
AD9716/AD9717
AUX DAC
50kΩ
Figure 109. Simplified DC Coupling to Quadrature Modulator ADL537x
Family or Equivalent Is Enabled By Using Internal Components
CORRECTING FOR NONIDEAL PERFORMANCE OF
QUADRATURE MODULATORS ON THE IF-TO-RF
CONVERSION
When not enabled (QAUXEN or IAUXEN = 0), the respective
DAC output is in open circuit.
Analog quadrature modulators make it very easy to realize
single sideband radios. However, there are several nonideal
aspects of quadrature modulator performance. Among these
analog degradations are gain mismatch and LO feedthrough.
DAC-TO-MODULATOR INTERFACING
The auxiliary DACs can be used for local oscillator (LO) cancella-
tion when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
DAC-to-quadrature modulator interfaces are shown in Figure 108
and Figure 109, with the series resistor value chosen to give an
appropriate adjustment range. Figure 108 also shows external
load resistors in use. Often, the input common-mode voltage for
the modulator is much higher than the output compliance range
of the DAC, so that ac coupling or a dc level shift is necessary. If
the required common-mode input voltage on the quadrature
modulator matches that of the DAC, the dc blocking capacitors in
Figure 108 can be removed and the on-chip resistors can be
connected.
Gain Mismatch
The gain in the real and imaginary signal paths of the quad-
rature modulator may not be matched perfectly. This leads
to less than optimal image rejection because the cancellation of
the negative frequency image is less than perfect.
LO Feedthrough
The quadrature modulator has a finite dc referred offset, as well
as coupling from its LO port to the signal inputs. These can lead
to a significant spectral spur at the frequency of the quadrature
modulator LO.
The AD9714/AD9715/AD9716/AD9717 have the capability
to correct for both of these analog degradations. However,
understand that these degradations drift over temperature;
therefore, if close to optimal single sideband performance
is desired, a scheme for sensing these degradations over
temperature and correcting them may be necessary.
MODULATOR
V+
0.1µF
QUADRATURE
AD9714/AD9715/
AD9716/AD9717
I OR Q DAC
OPTIONAL
PASSIVE
FILTERING
MODULATOR
I OR Q
INPUTS
0.1µF
I/Q-CHANNEL GAIN MATCHING
AD9714/AD9715/
AD9716/AD9717
AUX DAC
5kΩ
TO
100kΩ
Fine gain matching is achieved by adjusting the values in the
DAC fine gain adjustment registers. For the I DAC, these values
are in the I DAC gain register (Register 0x03). For the Q DAC,
these values are in the Q DAC gain register (Register 0x06). These
are 6-bit values that cover ±±ꢀ of full scale. To perform gain
compensation starting from the default values of zero, raise the
value of one of these registers a few steps until it can be deter-
mined if the amplitude of the unwanted image is increased or
decreased. If the unwanted image increases in amplitude, remove
the step and try the same adjustment on the other DAC control
register. Iterate register changes until the rejection cannot be
improved further. If the fine gain adjustment range is not sufficient
to find a null (that is, the register goes full scale with no null
apparent), adjust the course gain settings of the two DACs
accordingly and try again. Variations on this simple method
are possible.
499Ω
499Ω
Figure 108. Typical Use of Auxiliary DACs and External Components for
Coupling to Quadrature Modulators
Figure 109 shows a greatly simplified circuit that takes full
advantage of the internal components supplied in the DAC. A
low-pass or band-pass passive filter is recommended when
spurious signals from the DAC (distortion and DAC images)
at the quadrature modulator inputs can affect the system
performance. In the example shown in Figure 109, the filter
must be able to pass dc to properly bias the modulator. Placing
the filter at the location shown in Figure 108 and Figure 109
allows easy design of the filter because the source and load imped-
ances can easily be designed close to 500 Ω for a ± mA full-scale
output. Once the resistance at the modulator inputs is known,
the user can easily look up the range of input offsets that may be
encountered and compute a value for the series resistor on the
AUXDAC output.
Rev. B | Page 50 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
5
0
–5
Note that LO feedthrough compensation is independent of
phase compensation. However, gain compensation can affect
the LO compensation because the gain compensation may
change the common-mode level of the signal. The dc offset of
some modulators is common-mode level dependent. Therefore,
it is recommended that the gain adjustment be performed prior
to LO compensation.
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
LO FEEDTHROUGH COMPENSATION
To achieve LO feedthrough compensation in a circuit, each
output of the two AUXDACs must be connected through a
100 kꢁ resistor to one side of the differential DAC output. See
the Auxiliary DACS section for details of how to use AUXDACs.
The purpose of these connections is to drive a very small amount
of current into the nodes at the quadrature modulator inputs,
thereby adding a slight dc bias to one or the other of the
quadrature modulator signal inputs.
447.5
449.0
450.0
451.0
452.5
FREQUENCY (MHz)
Figure 110. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a Single-
Tone Signal at 450 MHz, No Gain or LO Compensation
5
0
To achieve LO feedthrough compensation, the user should start
with the default conditions of the AUXDAC registers, and then
increment the magnitude of one or the other AUXDAC output
voltages. While this is being done, the amplitude of the LO
feedthrough at the quadrature modulator output should be
sensed. If the LO feedthrough amplitude increases, try either
decreasing the output voltage of the AUXDAC being adjusted,
or try adjusting the output voltage of the other AUXDAC. It
may take practice before an effective algorithm is achieved. The
AD9714/AD9715/AD9716/AD9717 evaluation board can be
used to adjust the LO feedthrough down to the noise floor,
although this is not stable over temperature.
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
447.5
449.0
450.0
451.0
452.5
FREQUENCY (MHz)
RESULTS OF GAIN AND OFFSET CORRECTION
Figure 111. AD9714/AD9715/AD9716/AD9717 and ADL5370 with a Single-
Tone Signal at 450 MHz, Gain and LO Compensation Optimized
The results of gain and offset correction can be seen in Figure 110
and Figure 111. Figure 110 shows the output spectrum of the
quadrature demodulator before gain and offset correction.
Figure 111 shows the output spectrum after correction. The
LO feedthrough spur at 450 MHz has been suppressed to the
noise level. This result can be achieved by applying the correc-
tion, but the correction must be repeated after a large change in
temperature.
Note that gain matching improves the negative frequency image
rejection, but it is also related to the phase mismatch in the
quadrature modulator. It can be improved by adjusting the
relative phase between the two quadrature signals at the digital
side or properly designing the low-pass filter between the DACs
and quadrature modulators. Phase mismatch is frequency depen-
dent; therefore, routines must be developed to adjust it if
wideband signals are desired.
Rev. B | Page 51 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
To evaluate the ADL5370 on this board, the population of these
same components should be reversed so that they are in the
following positions:
MODIFYING THE EVALUATION BOARD TO
USE THE ADL5370 ON-BOARD QUADRATURE
MODULATOR
•
•
•
JP55, JP56, JP76, JP82—soldered
R13, R14, R52, R53—populated
R50, R57, T1, T2—unpopulated
The evaluation board contains an Analog Devices, Inc.,
ADL5370 quadrature modulator. The AD9714/AD9715/
AD9716/AD9717 and the ADL5370 provide an easy-to-
interface DAC/modulator combination that can be easily
characterized on the evaluation board. Solderable jumpers
can be configured to evaluate the single-ended or differential
outputs of the AD9714/AD9715/AD9716/AD9717. This setup
is the default configuration from the factory and consists of
the following population of the components:
The AUXDAC outputs can be connected to Test Point TP44 and
Test Point TP45 if LO feedthrough compensation is necessary.
•
•
•
JP55, JP56, JP76, JP82—unsoldered
R13, R14, R52, R53—unpopulated
R50, R57, T1, T2—populated
Rev. B | Page 52 of 80
JP6
5VGND;3,4,5
L1
SMAEDGE
CVDD
DVDD
AVDD
DVDDX
CVDDX
3
3
3
3
1
CVDD_IN
DVDD_IN
LC1812
EXC-CL4532U1
1
J2
B
A
2
TP12
RED
C14
CC0603
0.1UF
C2
10UF
6.3V
0.1UF
2
5V
CC0603
ACASE
ACASE
ACASE
ACASE
ACASE
CC0603
IN4
IN3
SD
OUT5
OUT6
FB
R2
76.8K
4
3
2
1
5
6
7
8
C13
100PF
CVDD_IN
1UF
EXC-CL4532U1
L5
C3
C10
TP14
BLK
C
C12
CC0603
5V
U2
LC1812
5V
5V
5V
5V
5V
1UF
GND
ADP3334
NC
R8 64.9K
2
L2
5V
5V
A
B
3
RC0603
1
LC1812
EXC-CL4532U1
JP22
78.7K R5
TP13
RED
3.3
1.8
0.1UF
CC0603
C4
10UF
6.3V
0.1UF
CC0603
EXC-CL4532U1
RC0603
5VGND;3,4,5
SMAEDGE
5V
C7
C6
TP4
BLK
JP10
1
L6
1
J4
B
A
2
LC1812
C17
CC0603
2
IN3
OUT5
OUT6
R23
76.8K
L3
4
3
2
1
5
6
7
8
C19
5V
100PF
DVDD_IN
1UF
IN4
AVDD_IN
LC1812
EXC-CL4532U1
C18
CC0603
5V
SD
TP5
U4
FB
NC
0.1UF
CC0603
C5
10UF
6.3V
0.1UF
CC0603
1UF
RED
GND
R12
64.9K
EXC-CL4532U1
2
ADP3334
5V
5V
C9
C8
TP6
BLK
A
B
3
L7
1
JP26
LC1812
78.7K
R10
3.3
1.8
RC0603
L4
5VGND;3,4,5
SMAEDGE
5V
JP54
DVDDX_IN
LC1812
EXC-CL4532U1
1
1
J5
TP8
B
A
2
0.1UF
CC0603
C1
10UF
6.3V
0.1UF
CC0603
C20
RED
2
EXC-CL4532U1
L12
CC0603
IN3
IN4
SD
OUT5
R31
76.8K
4
3
2
1
5
6
7
8
C30
5V
100PF
C15
C16
TP9
BLK
1UF
AVDD_IN
OUT6
C21
LC1812
5V
CC0603
FB
NC
U6
1UF
GND
R30 64.9K
L16
2
A
JP29
ADP3334
5V
5V
B
3
CVDDX_IN
LC1812
RC0603
1
EXC-CL4532U1
TP24
RED
C57
10UF
6.3V
0.1UF
CC0603
0.1UF
CC0603
78.7K R29
3.3
1.8
EXC-CL4532U1
L19
RC0603
5VGND;3,4,5
C61
C60
TP23
BLK
SMAEDGE
5V
JP15
1
1
LC1812
J8
C
B
A
2
C31
2
CC0603
IN3
IN4
SD
OUT5
OUT6
FB
R36
76.8K
4
3
2
1
5
6
7
8
C38
5V
100PF
1UF
DVDDX_IN
CVDDX_IN
2
C37
CC0603
5V
5VGND;3,4,5
U7
SMAEDGE
1UF
GND
NC
R32
64.9K
1
2
A
J11
B
A
ADP3334
3
1
5V
5V
B
RC0603
C86
1
3
JP78
2
JP88
1.8
CC0603
IN4
4
OUT5
OUT6
R25
76.8K
5
C89
5V
100PF
3.3
1UF
78.7K
R3
IN3
C88
3
6
7
8
CC0603
SD
2
FB
NC
U11
RC0603
5V
1UF
GND
R92 64.9K
1
2
A
5VINT
ADP3334
5V
5V
B
3
RC0603
1
5VGND;3,4,5
5VIN
JP89
SMAEDGE
JP28
JP3
3.3
1.8
1
78.7K R4
J3
5VUSB
RC0603
5V
2
5V
TP22
WHT
TP10
BLK
R6
RC0402
0
2
MSB
No stub
Match length
to path from
S5 to Pin 18
of U1.
1
RP3
1
22
16
15
14
13
12
11
10
9
PCB Bottom Side
2
DB13X
DB12X
DB11X
DB10X
DB9X
DB13
DB12
DB11
DB10
DB9
1
3
5
7
9
2
3
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
4
4
6
5
8
6
10
7
DB8X
DB8
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
8
DB7X
DB7
RNETCTS743-8
RP4
22
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
DB6
DB5
DB4
DB3
DB2
DB1
DB0
RNETCTS743-8
SSW-120-02-SM-D-R-A
1
J1
DIGITAL INPUTS
1
IN J1 AND RP3, THE MSB IS DB13, DB11, DB9, OR DB7, DEPENDING ON THE PART.
=
SHARE COMPONENT PAD.
OUT2R
DVDDX
CLKIN
C59
4.7UF
6.3V
00.1UF
1NF
C56
DCLKIO
ACASE
CC0402
CC0402
OUT0R
R65
R64
C55
DNP R122
0
R33
0
0
DVDDX
RC0402
RC0402
RC0402
CVDDX
R70
10K
R66
DNP
R34
0
TP25
WHT
TP26
WHT
DGND;3
DVDDX;5
C34 00.1UF
DNP R110
0
R72
2
4
S5
S11
00.1UF
00.01UF
CC0402 C78
RC0402
RC0402
R108
10K
CC0402
C
SN74LVC1G34DCK
CGND;3,4,5
DGND;3,4,5
C77
R68
DNP
R17
DNP
U8
C101
00.1UF
C
R71
10K
C
C
R67
R107
DNP
U12
RC0402
0
1
2
4
EN
OVCC
Keep parallel
R18
49.9
3
GND
OUT
C
R69
DNP
OSC-S1703
C
R46
RC0402
0
R47
RC0402
0
R48
RC0402
0
C
CVDD
DNP
R80
1
2
40
DB11
DB10
DB11
DB10
DB9
DB12
DB12
REFIO
RC0402
39
DB13 (MSB)
CS/PWRDN
DB13
0.1UF
CC0603
0.01UF
DVDD
3
38
CC0603
DB9
SLEEP-CSB
MODE-SDIO
RMODE-SCLK
4
37
JP11
C27
C28
DB8
DB8
SDIO/FORMAT
SCLK/CLKMD
RESET/PINMD
REFIO
5
36
DVDDIO
DVSS
DVDD
DB7
DVDDIO
TP30
WHT
6
35
SW1
7
34
4
2
TP3
WHT
C11
0.1UF
AVDD
8
33
3
1
DB7
DB6
FSADJI/AUXI
FSADJQ/AUXQ
CMLI
FSADJ1
9
32
1UF
CC0603
DB6
FSADJ2
IOTC
0.1UF
CC0603
0.01UF
CC0603
DGND;5
10
11
12
13
14
15
16
17
18
19
20
31
CC0603
DB5
DB5
C39
30 JP35
29
10K
C26
C25
DB4
DB4
RLIN
DB3
DB3
IOUTN
IOUTB
28
DB2
DB2
IOUTP
IOUTA
27
40-LEAD LFCSP
AD9717
DB1
DB1
RLIP
AVDD
DVDD
JP34
26
DB0 (LSB)
DCLKIO
CVDD
CLKIN
DB0 (LSB)
DCLKIO
CVDD
AVDD
0
R19
RC0402
25
AVSS
IOTC
IOT_CML
0.1UF
CC0603
0.01UF
CC0603
24 JP33
RLQP
DNP
R20
RC0402
23
22
C24
C23
CLKIN
QOUTP
QOUTN
RLQN
QOUTA
QOUTB
AGND;41
U1
CVSS
0
R21
RC0402
21
QOTC
CMLQ
QOTC
QOT_CML
JP32
DNP
R26
RC0402
C
THE AD9714/AD9715/AD9716
CAN BE USED IN U1.
TP32
DNP
OPAMPIN
JP55
D1P
AGND;3,4,5
S3
R11
0
R111
10-DNP
RC0603
0
R9
DNP
DNP
IOUTA
RC0603
RC0603
R93
TP31
WHT
R118
T8
TP33
DNP
ADTL1-12
6
5
4
S
P
1
2
3
JP56
R57
453
3
1
4
P
S
D1N
6
T2
ADT9-1T
DNP
AGND;3,4,5
S4
R79
0
0
RC0603
RC0603
IOUTB
RC0603
R119
R35
100K
R94
R37
DNP
R123
0-DNP
RC0603
R14
DNP
R13
DNP
WHT
TP44
WHEN R13 AND R14 ARE NOT
DNP, 499 IS RECOMMENDED
IOT_CML
C22
0.1UF
R22
DNP
R15
0-DNP
CC0603
TP40
ORG
TP39
RED
C102
TP1
WHT
0.2NF
DNP
JP90
FSADJ1
N5V
P5V
S9
AGND;3,4,5
R113 499
10V
10UF
C103
C104
10UF
10V
RC0402
ACASE
ACASE
R116 0
P5V
TP41
BLK
C106
TP34
WHT
0.1UF
OPAMPIN
RC0402
R115 499
R1
R49
16K
R51
7
R99
100K
R98
DNP
8
+V
-IN
RC0402
2
1
DIS
DNP
FB
R114 15
32K
0.1%
8K
C105
CERAMIC
ADA4899-1
U13
1UF
1
R97
DNP
OUT 6
R117 0
S12
AGND;3,4,5
-V2
0.1%
0.1%
RC0402
-V1
3
DNP
CC0603
+IN
REFIO
2
RC0402
5
DNP
4
AGND;9
C95
0.1UF
C108
CC0603
0.1UF
C107
WHEN C95 IS NOT
DNP, 10pF TO 1nF IS RECOMMENDED
FSADJ resistors must have low TC
N5V
IOUT NETWORK AND FSADJ1
OPAMPIN
TP36
DNP
JP76
D2P
R38
0
WHEN R112 IS NOT DNP,
10 IS RECOMMENDED
R112
DNP
S6
RC0603
AGND;3,4,5
R105
0
R42
DNP
R120 DNP
QOUTA
RC0603
RC0603
TP38
WHT
T1
ADT9-1T
TP37
DNP
1
3
6
JP82
R50
453
4
5
6
3
2
1
P
S
D2N
4
S
P
ADTL1-12
T5
AGND;3,4,5
S8
R83
0
R106
0
R121 DNP
RC0603
QOUTB
RC0603
RC0603
R56
DNP
R55 100k
0
R52
DNP
R53
DNP
R124
RC0603
WHT
TP45
WHEN R52 AND R53 ARE NOT
DNP, 499 IS RECOMMENDED
QOT_CML
C48
0.1UF
R54
DNP
R16
0
CC0603
TP17
WHT
DNP
JP91
1
FSADJ2
S10
AGND;3,4,5
2
TP35
WHT
R58
32K
R59
16K
R60
8K
R102
100K
R101
DNP
0.1%
0.1%
0.1%
R100
DNP
DNP
CC0603
C96
WHEN C96 IS NOT DNP,
10pF TO 1nF IS RECOMMENDED
FSADJ resistors must have low TC
QOUT NETWORK AND FSADJ2
5VUSB
0.1UF
CC0603
0.1UF
CC0603
0.1UF
CC0603
0.1UF
CC0603
C32
10UF
6.3V
C99
C98
C97
C84
L15
EXC-CL3225U1
2
GND-4
ID-X
PIC18F4450
5
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RC7-RX-DT
5V
MOSI
EN1
RC6-TX-CK
RC5-D+-VP
RC4-D--VM
RD3
4
3
2
1
RD4
D+
pcb Top side
3
RD5
D-
EN2
4
RD6
VBUS
5VUSB
5
RD7
P1
R63
RD2
U3
6
VSS1
RD1
499
7
AVDD1
5VGND;45
RD0
RC0403
8
VDD1
5VUSB
MISO
VUSB
2
1
9
RB0-AN12-INT0
RB1-AN10-INT1
RB2-AN8-INT2-VMO
RB3-AN9-VPO
RC2-CCP1
RC1-T1OSI-UOE
470NF
CC0603
10
11
12
13
14
15
16
17
18
19
20
21
22
D1
SCK
C110
LNJ312G8TRA
SSEL1
SSEL2
RC0-TIOSO-T1CKI
OSC2-CLKO-RA6
OSC1-CLK1
VSS2
5V
N31C
0
0
R82
RC0402
MP1
1M
R27
Y1CC0603
RB4-AN11-KBI0
RB5-KBI1-PGM
RB6-KBI2-PGC
RB7-KBI3-PGD
MCLR-VPP-RE3
RA0-AN0
1
2
5VUSB
AVSS
20.000MHZ
VDD2
5VUSB
3
3
AVDD2
5VGND;2
10PF-1%
4
RE2-AN7
10PF-1%
CC0603
5
CC0603
RA0
RE1-AN6
0.1UF
CC0603
MP2
R62
RC0402
C49
C33
RA1-AN1
RE0-AN5
C114
RA2-AN2-VREF-
RA3-AN3-VREF+
RA5-AN4-HLVDIN
RA4-T0CKI-RCV
P3
pcb bottom side
5V
5V
TP2
TP7
BLK
R87
0
DNP
DVDD
5VUSB
DVDDX
5VUSB
0.1UF
CC0603
0.1UF
CC0603
0.1UF
CC0603
0.1UF
CC0603
RC1206
C100
C109
C111
C112
R43
5V
0
MISO
MOSI
RC0402
TP18
WHT
1
2
3
4
5
6
7
1
14
14
13
12
11
10
9
VCCA
A1
VCCY
VCCA
A1
VCCY
22
R103
R44
22
22
22
R28
R39
R40
2
3
4
5
6
7
13
12
11
10
9
Y1
Y2
Y1
Y2
Y3
Y4
MODE-SDO
MISO
SDIO
TP19
MISO
MOSI
SCK
RC0402
U5
U14
A2
A2
MODE-SDIO
RMODE-SCLK
SLEEP-CSB
MOSI
SCK
22
WHT
Y3
A3
A3
SCLK
ADG3304
ADG3304
22RC0402 R41
22 RC0402R45
A4
Y4
A4
SSEL1
CSB
SSEL2
RC0402
NCA
NCY
EN
TP20
WHT
NCA
GND
8
8
GND
EN
EN1
EN2
MOD_IP
MOD_IN
MOD_QN
MOD_QP
4.7PF
CC0805
7.5PF
CC0805
DNP
CC0805
0
R73
RC0603
MOD_IP
C82
L17
C92
T6
C81
L10
VDDM
DNP
DNP
1.8UH
1
3
6
D1N
D1P
LC1008
LC1008
NC=2,5
P
S
4
C52
C51
L11
L14
1.8UH
C44
ACASE
CC0402
CC0402
DNP
LC1008
LC1008
ADTL1-12
1
2
24
23
22
21
20
19
18
17
16
15
14
13
10UF
10V
DNP
0.1UF
100PF
COM1A
COM1B
VPS1A
VPS1B
VPS1C
VPS1D
COM2A
LOIP
QBBP
QBBN
COM4B
COM4A
IBBN
CC0805
CC0805
CC0805
0
R74
RC0603
VDDM
C80
4.7PF
C79
C91
MOD_IN
3
7.5PF
4
5
C43
CC0402
CC0402
C83
ACASE
6
10UF
10V
CC0402
C50
100PF
IBBP
C47
0.1UF
7
100PF
VPS5
8
VPS4
VDDM
C90
ADL5370
U9
9
LOIN
VPS3
VPS2B
VPS2A
VOUT
10
11
12
CC0402
COM2B
COM3A
COM3B
C87
0.1UF
CC0402
CC0402
CC0402
100PF
0
R75
RC0603
AGND;25
4.7PF
CC0805
7.5PF
CC0805
DNP
CC0805
MOD_QN
T3
C75
L20
C94
C74
L8
VDDM
C41
DNP
DNP
1.8UH
CC0402
1
3
6
D2N
D2P
C72
LC1008
LC1008
LC1008
C63
P
S
4
CC0402
NC=2,5
CC0402
L9
L18
ACASE
1.8UH
10UF
10V
0.1UF
100PF
AGND;3,4,5
SMAEDGE
AGND;3,4,5
SMAEDGE
LC1008
ADTL1-12
DNP
CC0805
1
1
0
CC0805
CC0805
R78
RC0603
J6
J7
MOD_QP
C65
4.7PF
C64
7.5PF
C93
2
2
RED
RED
TP16
TP42
L13
VDDM
VDDM_IN
LC1812
EXC-CL4532U1
C35
22UF
16V
0.1UF
CC0402
0.1UF
ACASE
CC0402
BLK
TP21
BLK
TP43
C36
C29
MODULATED OUTPUT
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VS18
VS17
CVDDX
CVDDX
DSYNC
DSYNCB
VS1
3
CVDDX
CVDDX
GND6
RSET
VS16
4.12K
R81
RC0402
4
VS2
5
C
CVDDX
NC1
6
CVDDX
CVDDX
GND5
OUT0
OUT0B
VS15
VS3
7
CLK2
CLK2B
VS4
8
9
C45 0.1UF
T9
CGND;3,4,5
J10
CVDDX
CVDDX
1
2
3
6
5
4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P
S
VS14
CLK1
CLK1B
FUNC
STATUS
SCLK
SDIO
SDO
GND4
GND3
VS13
3
1
R91
49.9
CVDDX
JTX-4-10T+
1:4
C
C
0
0
R88
RC0402
2
D3
RMODE-SCLK
MODE-SDIO
MODE-SDO
SLEEP-CSB
CVDDX
OUT3
OUT3B
VS12
OUT0R
DNP R90
C46
0.1UF
RC0402
CVDDX
CVDDX
C
C
VS11
CSB
AD9512BCPZ
R89
1.8K R77
1.8K R76
CVDDX
OUT4
OUT4B
VS10
OUT2R
DNP R109
VS5
RC0402
RC0402
RC0402
CGND;49
GND1
OUT2B
OUT2
VS6
1NF
CC0402
CVDDX
CVDDX
SW2
RC0402
C62
2
4
VS9
C
U10
WHEN R90 AND R109
ARE NOT DNP, 49.9
IS RECOMMENDED
1
3
CVDDX
CVDDX
OUT1
OUT1B
VS8
C
C
CGND;5
VS7
CVDDX
GND2
C
C
0
R86
RC0402
RA0
CVDDX
0.1UF
C42
0.1UF
C66
0.1UF
0.1UF
C68
CC0402
CC0402
CC0402
CC0402
CC0402
CC0402
CC0402
CC0402
C67
0.1UF
C69
0.1UF
C70
0.1UF
C71
0.1UF
C76
CC0402
CC0402
0.1UF
C113
0.1UF
C85
0.1UF
C58
0.1UF
C40
CC0402
CC0402
C
CLOCK DRIVER CHIP
Data Sheet
AD9714/AD9715/AD9716/AD9717
SILKSCREENS
Figure 120. Layer 2, Ground Plane
Rev. B | Page 61 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Figure 121. Layer 3, Power Plane
Rev. B | Page 62 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Figure 122. Assembly—Primary Side
Rev. B | Page 63 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Figure 123. Assembly—Secondary Side
Rev. B | Page 64 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Figure 124. Solder Mask—Primary Side with Socket
Rev. B | Page 65 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Figure 125. Solder Mask—Secondary Side
Rev. B | Page 66 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Figure 126. Hard Gold Plated with Bumps and Socket
Rev. B | Page 67 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Figure 127. Primary Side Paste
Rev. B | Page 68 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Figure 128. Secondary Side Paste
Rev. B | Page 69 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Figure 129. Silkscreen—Primary Side
Rev. B | Page 70 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Figure 130. Silkscreen—Secondary Side
Rev. B | Page 71 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Figure 131. Layer 1—Primary Side
Rev. B | Page 72 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Figure 132. Layer 4—Secondary Side
Rev. B | Page 73 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Figure 133. Immersion Gold, No Socket, No Bumps
Rev. B | Page 74 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Figure 134. Solder Mask—Primary Side, No Socket
Rev. B | Page 75 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
BILL OF MATERIALS
Table 18.
Part No./
Manufacturer
Qty Reference Designator
Device
Package
ACASE
Description
6
C1, C2, C4, C5, C32, C57
CAPSMDA
CC0603
10 µF, 6.3 V capacitor
0.1 µF capacitor
17
C3, C6, C7, C8, C9, C10, C11,
C15, C16, C22, C24, C26,
C27, C48, C60, C61, C107
CC0603
11
C12, C14, C17, C18, C20,
C21, C31, C37, C39, C86, C88
CC0603
CC0603
1 µF capacitor
5
C13, C19, C30, C38, C89
C23, C25, C28
CC0603
CC0603
CC0603
CC0603
CC0402
CC0603
CC0402
100 pF capacitor
0.01 µF capacitor
0.1 µF capacitor
10 pF, 1% capacitor
0.1 µF capacitor
3
6
C29, C36, C47, C52, C72, C90 CC0402
2
C33, C49
CC0603
CC0402
18
C34, C40, C42, C45, C46,
C55, C58, C66, C67, C68,
C69, C70, C71, C76, C77,
C85, C101, C113
1
3
8
C35
CAPSMDA
CAPSMDB
CC0402
ACASE
ACASE
CC0402
22 µF,16 V capacitor
10 µF, 10 V capacitor
100 pF capacitor
C41, C43, C44
C50, C51, C53, C54, C63,
C73, C83, C87
2
C56, C62
CC0402
CAPSMDA
CC0805
CC0805
CC0402
CC0603
CC0402
ACASE
1 nF capacitor
1
C59
4.7 µF, 6.3 V capacitor
7.5 pF, 1% capacitor
4.7 pF, 1% capacitor
0.01 µF capacitor
0.1 µF capacitor
4
C64, C75, C79, C82
C65, C74, C80, C81
C78
CC0805
CC0805
CC0402
CC0603
4
1
11
C84, C97, C98, C99, C100,
C106, C108, C109, C111,
C112, C114
4
2
1
2
1
1
1
1
1
C91, C92, C93, C94
CC0805
CC0805
DNP
C95, C96
C102
C103, C104
C105
C110
D1
CC0603
CC0603
DNP
CC0402
CC0402
0.2 nF capacitor
10 µF, 10 V capacitor
1 µF ceramic capacitor
470 nF capacitor
LED-SMD-TSS-GRN
HSMS-281C
CAPSMDA
CC0805
ACASE
CC0805
CC0603
CC0603
Panasonic LNJ312G8TRA
HSMS-281C
1.6 mm x 0.8 mm
SOT323-3
LNJ312G8TRA
HSMS-281C
D3
J1
Samtec
SSW-120-02-SM-D-RA
40-pin through
hole
40-pin right angle
header female
SSW-120-02-SM-D-RA/
Samtec
6
2
5
J2, J3, J4, J5, J8, J11
J6, J7
SMAEDGE
SMAEDGE
SMAUPA04
SMAUPA04
SMAEDGE
SMAEDGE
SMA200UP
DNP SMA connector
edge right angle
SMA connector
edge right angle
J10, S3, S5, S6, S11
SMA connector RF
5-pin upright
5
S4, S8, S9, S10, S12
SMA200UP
JPRBLK02
DNP
11
JP3, JP7, JP8, JP9, JP11, JP12, JPRBLK02
JP16, JP20, JP21, JP28, JP77
2-pin jumper header
10
10
JP6, JP10, JP15, JP22, JP26,
JP29, JP54, JP78, JP88, JP89
JPRBLK03
JPRBLK03
JPRSLD02
3-pin jumper header
Solder jumper
JP32, JP33, JP34, JP35, JP55,
JP56, JP76, JP82, JP90, JP91
JPRSLD02
Rev. B | Page 76 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
Part No./
Manufacturer
Qty Reference Designator
Device
Package
Description
11
L1, L2, L3, L4, L5, L6, L7,
L12, L13, L16, L19
IND1812
LC1812
EXC-CL4532U1
EXC-CL4532U1
4
4
1
1
1
L8, L9, L10, L11
IND1008
LC1008
1.8 µH, 10%
DNP
L14, L17, L18, L20
IND1008
LC1008
L15
P1
IND1210
LC1210
EXC-CL3225U1
USB mini 5-pin
EXC-CL3225U1
USB-MINIB
Molex 0532610571
USB-MINIB
Molex 0532610571
P3
1.25 mm, 5-pin wire-
to-board connector
0532610571/
Molex
2
R1, R58
RC0805
RC0805
32 kΩ, 0.1% resistor
ERA6YEB323V,
ERA6Y
5
5
6
7
R2, R23, R25, R31, R36
R3, R4, R5, R10, R29
RC0603
RC0603
RC0402
RC0402
RC0603
RC0603
RC0402
RC0402
76.8 kΩ resistor
78.7 kΩ resistor
0 Ω resistor
DNP
R6, R33, R34, R64, R65, R67
R17, R66, R68, R69, R107,
R110, R122
1
5
8
R7
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
10 kΩ resistor
64.9 kΩ resistor
DNP
R8, R12, R30, R32, R92
R9, R37, R42, R56, R97, R98,
R100, R101
4
R11, R38, R79, R83
R13, R14, R52, R53
RC0603
RC0603
RC0603
RC0603
RC0603
RC0603
0 Ω resistor
DNP
4
10
R15, R16, R123, R124,
R73 to R75, R78, R93, R94,
R105, R106
0 Ω resistor
6
R22, R54, R118, R119,
R120, R121
RC0603
RC0603
DNP
1
2
3
2
1
7
R18
RC0402
RC0402
RC0402
RC0603
RC0603
RC0402
RC0402
RC0402
RC0402
RC0603
RC0603
RC0402
49.9 Ω resistor
0 Ω resistor
DNP
R19, R21
R20 , R26, R80
R24, R61
R27
1 kΩ resistor
1 MΩ resistor
22 Ω resistor
R28, R39, R40, R41, R44,
R45, R103
4
1
8
R35, R55, R99, R102
R43
RC0603
RC0402
RC0402
RC0603
RC0402
RC0402
100 kΩ resistor
0 Ω resistor
R46, R47, R48, R62, R82,
R86, R116, R117
0 Ω resistor
2
R49, R59
RC0805
RC0805
16 kΩ, 0.1% resistor
ERA6YEB323V,
ERA6Y
2
2
R50, R57
R51, R60
RC0603
RC0805
RC0603
RC0805
453 Ω resistor
8 kΩ, 0.1% resistor
ERA6YEB323V,
ERA6Y
3
3
1
2
1
1
2
2
1
2
1
2
R63, R113, R115
R70, R71, R108
R72
RC0402
RC0402
RC0402
RC0402
RC0402
RC1206
RC0402
RC0402
RC0805
RC0603
RC0402
RNETCTS743-8
RC0402
RC0402
RC0402
RC0402
RC0402
RC1206
RC0402
RC0402
RC0805
RC0603
RC0402
RNETCTS743-8
499 Ω resistor
10 kΩ resistor
25 Ω resistor
1.8 kΩ resistor
4.12 kΩ resistor
0 Ω resistor
0 Ω resistor
DNP
R76, R77
R81
R87
R88, R89
R90, R109
R91
49.9 Ω resistor
DNP
R111, R112
R114
15 Ω resistor
DNP
RP1, RP5
Rev. B | Page 77 of 80
AD9714/AD9715/AD9716/AD9717
Data Sheet
Part No./
Manufacturer
Qty Reference Designator
Device
Package
Description
2
2
4
1
RP3, RP4
SW1, SW2
T1, T2, T3, T6
T4
RNETCTS743-8
KEYBDSWG
ADTL1-12
ETC1-1-13
RNETCTS743-8
OMRONB3SG
MINI_CD542
SM-22
22 Ω resistor
B3S-1100 push-button
DNP
M/A COM ETC1-1-13
ETC1-1-13/
M/A-COM
2
T5, T8
T9
ADT9-1T
MINI_CD542
MINI_BH292
LOOPMINI
ADT9-1T
ADT9-1T/
Mini-Circuits
1
JTX-4-10T
LOOPMINI
JTX-4-10T+
White test point
JTX-4-10T/
Mini-Circuits
16
TP1, TP3, TP17, TP18,
TP19, TP20, TP22, TP25,
TP26, TP30, TP31, TP34,
TP35, TP38, TP44, TP45
4
8
TP32, TP33, TP36, TP37
LOOPMINI
LOOPMINI
LOOPMINI
LOOPMINI
DNP
TP5, TP8, TP12, TP13,
TP16, TP24, TP39, TP42
Red test point
1
TP2
LOOPMINI
LOOPMINI
LOOPMINI
LOOPMINI
DNP
12
TP4, TP6, TP7, TP9, TP10,
TP11, TP14, TP15, TP21,
TP23, TP41, TP43
Black test point
1
1
TP40
U1
LOOPMINI
LOOPMINI
Orange test point
40-lead LFCSP, AD9717
LFCSP040-CP1
40-lead LFCSP,
AD9717
AD9717/
Analog Devices
5
1
U2, U4, U6, U7, U11
U3
ADP3334
8-lead SOIC
ADP3334 voltage
regulator
ADP3334/
Analog Devices
USB-PIC18F4550-I/ML-ND
QFN044P65MM-EP1
PIC18F4550,
microchip USB
port chip
PIC18F4550
QFN44 8X8MM
2
1
1
1
U5, U14
U8
ADG3304BRUZ
74LVC1G34
ADL5370
14-lead TSSOP
SC70-05
ADG3304,
14-lead TSSOP
ADG3304BRUZ/
Analog Devices
SN74LVC1G34DCK,
TI buffer
TI-DCK =
SC70_05 PKG
U9
LFCSP024P5MM-EP1
LFCSP048-CP1
ADL5370ACPZ
ADL5370ACPZ/
Analog Devices
U10
AD9512
AD9512BCPZ
AD9512BCPZ/
Analog Devices
1
1
U12
U13
OSC-S1703
OSC-S1703
SOIC8-N-EP
DNP
8-lead SOIC, ADA4899-1
Op amp, ADA4899-1
ADA4899-1/
Analog Devices
1
Y1
ABM3B-20.000MHZ-10-1-U-T SMD 3.2 mm × 5.0 mm 20 MHz
300-8214-1-ND/
Digi-Key
Rev. B | Page 78 of 80
Data Sheet
AD9714/AD9715/AD9716/AD9717
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
40
1
30
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
4.25
4.10 SQ
3.95
5.75
BSC SQ
EXPOSED
PAD
(BOT TOM VIEW)
0.50
0.40
0.30
21
10
20
11
0.25 MIN
4.50
REF
12° MAX
0.80 MAX
0.65 TYP
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 135. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm and 0.85 mm Package Height
(CP-40-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead LFCSP
40-Lead LFCSP
40-Lead LFCSP
40-Lead LFCSP
40-Lead LFCSP
40-Lead LFCSP
40-Lead LFCSP
40-Lead LFCSP
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Package Option
CP-40-1
AD9714BCPZ
AD9714BCPZRL7
AD9715BCPZ
CP-40-1
CP-40-1
AD9715BCPZRL7
AD9716BCPZ
CP-40-1
CP-40-1
AD9716BCPZRL7
AD9717BCPZ
CP-40-1
CP-40-1
AD9717BCPZRL7
AD9714-DPG2-EBZ
AD9715-DPG2-EBZ
AD9716-DPG2-EBZ
AD9717-DPG2-EBZ
CP-40-1
1 Z = RoHS Compliant Part.
Rev. B | Page 79 of 80
AD9714/AD9715/AD9716/AD9717
NOTES
Data Sheet
©2008–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07265-0-1/18(B)
Rev. B | Page 80 of 80
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