AD9742AR [ADI]
12-Bit, 165 MSPS TxDAC D/A Converter; 12位， 165 MSPS TxDAC系列D / A转换器
| 型号： | AD9742AR |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 165 MSPS TxDAC D/A Converter |
| 文件： | 总20页 (文件大小：776K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 165 MSPS
®
a
TxDAC D/A Converter
AD9742*
FUNCTIONAL BLOCK DIAGRAM
3.3V
FEATURES
High Performance Member of Pin-Compatible
TxDAC Product Family
Excellent Spurious-Free Dynamic Range Performance
SNR @ 5 MHz Output, 125 MSPS: 73 dB
Two’s Complement or Straight Binary Data Format
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 135 mW @ 3.3 V
Power-Down Mode: 15 mW @ 3.3 V
On-Chip 1.20 V Reference
CMOS-Compatible Digital Interface
Package: 28-Lead SOIC and TSSOP Packages
Edge-Triggered Latches
REFLO
+1.20V REF
REFIO
AVDD ACOM
150pF
0.1F
AD9742
CURRENT
FS ADJ
SOURCE
ARRAY
R
SET
DVDD
3.3V
IOUTA
IOUTB
LSB
SEGMENTED
SWITCHES
DCOM
SWITCHES
CLOCK
MODE
CLOCK
LATCHES
DIGITAL DATA INPUTS (DB11–DB0)
SLEEP
APPLICATIONS
Wideband Communication Transmit Channel:
Direct IF
Base Stations
Wireless Local Loop
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9742 is a 12-bit resolution, wideband, third generation
member of the TxDAC series of high-performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communica-
tion systems. All of the devices share the same interface options,
small outline package, and pinout, providing an upward or down-
ward component selection path based on performance, resolution,
and cost. The AD9742 offers exceptional ac and dc performance
while supporting update rates up to 165 MSPS.
1. The AD9742 is the 12-bit member of the pin compatible
TxDAC family that offers excellent INL and DNL
performance.
2. Data input supports two’s complement or straight binary
data coding.
3. High-speed, single-ended CMOS clock input supports
165 MSPS conversion rate.
4. Low power: Complete CMOS DAC function operates on
135 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation, and
a sleep mode is provided for low power idle periods.
The AD9742’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can be
further reduced to a mere 60 mW with a slight degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance. Edge-
triggered input latches and a 1.2 V temperature compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V CMOS
logic families.
5. On-chip voltage reference: The AD9742 includes a 1.2 V
temperature-compensated band gap voltage reference.
6. Industry standard 28-lead SOIC and TSSOP packages.
TxDAC is a registered trademark of Analog Devices, Inc.
* Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD9742
DC SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
RESOLUTION
12
Bits
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
–2.5
–1.3
±0.5
±0.4
+2.5
+1.3
LSB
LSB
ANALOG OUTPUT
Offset Error
–0.02
–0.5
–0.5
2.0
+0.02
+0.5
+0.5
20.0
% of FSR
% of FSR
% of FSR
mA
V
kW
pF
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
±0.1
±0.1
–1.0
+1.25
100
5
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
1.14
0.1
1.20
100
1.26
1.25
V
nA
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (Ext. Ref)
Small Signal Bandwidth
V
MW
MHz
1
0.5
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
0
ppm of FSR/∞C
ppm of FSR/∞C
ppm of FSR/∞C
ppm/∞C
±50
±100
±50
POWER SUPPLY
Supply Voltages
AVDD
2.7
2.7
3.3
3.3
33
8
3.6
3.6
36
9
V
V
mA
mA
DVDD
Analog Supply Current (IAVDD
Digital Supply Current (IDVDD
)
)
4
Supply Current Sleep Mode (IAVDD
)
5
135
145
6
145
mA
mW
mW
% of FSR/V
Power Dissipation4
Power Dissipation5
Power Supply Rejection Ratio—AVDD6
Power Supply Rejection Ratio—DVDD6
–1
–0.04
+1
+0.04
% of FSR/V
OPERATING RANGE
–40
+85
∞C
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4Measured at fCLOCK = 25 MSPS and fOUT = 1.0 MHz.
5Measured as unbuffered voltage output with IOUTFS = 20 mA and 50 W RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
6
±5% power supply variation.
Specifications subject to change without notice.
–2–
REV. 0
AD9742
(TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, Differential Transformer Coupled
DYNAMIC SPECIFICATIONS Output, 50 ⍀ Doubly Terminated, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK
)
165
MSPS
ns
ns
pV-s
ns
ns
pA/÷Hz
pA/÷Hz
dBm/Hz
Output Settling Time (tST) (to 0.1%)1
11
1
5
2.5
2.5
50
30
–151
Output Propagation Delay (tPD
Glitch Impulse
)
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)2
Output Noise (IOUTFS = 2 mA)2
Noise Spectral Density3
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
fCLOCK = 65 MSPS; fOUT = 1.00 MHz
74
84
85
82
76
85
83
80
75
74
72
60
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fCLOCK = 65 MSPS; fOUT = 2.51 MHz
f
f
CLOCK = 65 MSPS; fOUT = 10 MHz
CLOCK = 65 MSPS; fOUT = 15 MHz
fCLOCK = 65 MSPS; fOUT = 25 MHz
f
f
CLOCK = 165 MSPS; fOUT = 21 MHz
CLOCK = 165 MSPS; fOUT = 41 MHz
Spurious-Free Dynamic Range within a Window
fCLOCK = 25 MSPS; fOUT = 1.00 MHz; 2 MHz Span
80
dBc
dBc
dBc
dBc
f
CLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span
fCLOCK = 65 MSPS; fOUT = 5.03 MHz; 2.5 MHz Span
CLOCK = 125 MSPS; fOUT = 5.04 MHz; 4 MHz Span
90
90
90
f
Total Harmonic Distortion
fCLOCK = 25 MSPS; fOUT = 1.00 MHz
–82
–77
–77
–77
–74
dBc
dBc
dBc
dBc
f
f
CLOCK = 50 MSPS; fOUT = 2.00 MHz
CLOCK = 65 MSPS; fOUT = 2.00 MHz
fCLOCK = 125 MSPS; fOUT = 2.00 MHz
Signal-to-Noise Ratio
f
CLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA
78
86
73
78
69
71
dB
dB
dB
dB
dB
dB
fCLOCK = 65 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA
f
f
CLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA
CLOCK = 125 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA
fCLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 20 mA
CLOCK = 165 MSPS; fOUT = 5 MHz; IOUTFS = 5 mA
f
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz
0 dBFS Output
65
67
65
63
dBc
dBc
dBc
dBc
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
NOTES
1Measured single-ended into 50 W load.
2Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
Specifications subject to change without notice.
–3–
REV. 0
AD9742
DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic “1” Voltage
Logic “0” Voltage
2.1
3
0
V
V
0.9
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW
–10
–10
+10
+10
mA
mA
pF
ns
ns
ns
5
2.0
1.5
1.5
)
DB0–DB11
CLOCK
tS
tH
tLPW
tST
tPD
IOUTA
OR
0.1%
IOUTB
0.1%
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options*
With
Model
Parameter
Respect to Min Max
Unit
AD9742AR –40∞C to +85∞C 28-Lead 300 Mil SOIC R-28
AD9742ARU –40∞C to +85∞C 28-LeadTSSOP RU-28
AD9742-EB Evaluation Board
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
IOUTA, IOUTB
REFIO, REFLO, FSADJ
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
–0.3 +3.9
–0.3 +3.9
–0.3 +0.3
–3.9 +3.9
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–1.0 AVDD + 0.3
–0.3 AVDD + 0.3
150
V
V
V
V
V
V
V
V
*R = Small Outline IC; RU =Thin Shrink Small Outline Package
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300-Mil SOIC
JA= 71.4∞C/W
28-LeadTSSOP
JA= 97.9∞C/W
∞C
∞C
∞C
–65
+150
300
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9742 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. 0
AD9742
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
28 CLOCK
DVDD
(MSB) DB11
27
26 DCOM
DB10
DB9
DB8
DB7
25
24
23
MODE
AVDD
AD9742
DB6
DB5
DB4
DB3
RESERVED
TOP VIEW
(Not to Scale)
22 IOUTA
21
IOUTB
20
19
18
17
ACOM
NC
DB2 10
FS ADJ
REFIO
DB1
11
12
13
14
(LSB) DB0
16 REFLO
15 SLEEP
NC
NC
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
2–11
DB11
DB10–DB1
Most Significant Data Bit (MSB)
Data Bits 10–1
12
13, 14
15
DB0
NC
SLEEP
Least Significant Data Bit (LSB)
No Internal Connection
Power-Down Control Input. Active high. Contains active pull-down circuit; it may be left
unterminated if not used.
16
17
REFLO
REFIO
Reference Ground when internal 1.2 V reference used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO
to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to AGND).
Requires 0.1 mF capacitor to AGND when internal reference activated.
Full-Scale Current Output Adjust
No Internal Connection
Analog Common
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Reserved. Do Not Connect to Common or Supply.
Analog Supply Voltage (3.3 V)
Selects Input Data Format. Connect to DGND for straight binary, DVDD for two’s complement.
Digital Common
18
19
20
21
22
23
24
25
26
27
28
FS ADJ
NC
ACOM
IOUTB
IOUTA
RESERVED
AVDD
MODE
DCOM
DVDD
CLOCK
Digital Supply Voltage (3.3 V)
Clock Input. Data latched on positive edge of clock.
REV. 0
–5–
AD9742
DEFINITIONS OF SPECIFICATIONS
Power Supply Rejection
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight line
drawn from zero to full scale.
The maximum change in the full-scale output as the supplies are
varied from nominal to minimum and maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Glitch Impulse
Monotonicity
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
Spurious-Free Dynamic Range
The deviation of the output current from the ideal of zero is
called the offset error. For IOUTA, 0 mA output is expected
when the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Multitone Power Ratio
The spurious-free dynamic range containing multiple carrier
tones of equal amplitude. It measures as the difference between
the rms amplitude of a carrier tone to the peak spurious signal
in the region of a removed tone.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25∞C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale range
(FSR) per ∞C. For reference drift, the drift is reported in ppm per ∞C.
3.3V
REFLO
+1.20V REF
REFIO
AVDD
ACOM
150pF
AD9742
0.1F
PMOS
CURRENT SOURCE
ARRAY
FS ADJ
MINI-CIRCUITS
T1-1T
R
SET
ROHDE & SCHWARZ
FSEA30
2k⍀
3.3V
DVDD
IOUTA
IOUTB
SEGMENTED SWITCHES
FOR DB11–DB3
LSB
100⍀
SPECTRUM
DCOM
SWITCHES
ANALYZER
MODE
CLOCK
SLEEP
LATCHES
DVDD
DCOM
50⍀
20pF
50⍀
RETIMED
50⍀
20pF
CLOCK
DIGITAL
DATA
OUTPUT*
*AWG2021 CLOCK RETIMED
CLOCK
OUTPUT
SUCH THAT DIGITAL DATA
TEKTRONIX
AWG-2021
LECROY 9210
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
PULSE GENERATOR
W/OPTION 4
Figure 2. Basic AC Characterization Test Setup
–6–
REV. 0
Typical Performance Characteristics–AD9742
95
90
85
80
75
70
65
60
55
50
45
95
90
85
80
75
70
65
60
55
50
45
95
90
85
80
0dBFS
65MSPS
–12dBFS
75
–6dBFS
–6dBFS
70
125MSPS
–12dBFS
65
0dBFS
60
55
50
45
165MSPS
1
10
– MHz
100
0
5
10
f
15
– MHz
20
25
0
5
10 15 20 25 30 35 40 45
f
OUT
f
– MHz
OUT
OUT
TPC 1. SFDR vs. fOUT @ 0 dBFS
TPC 2. SFDR vs. fOUT @ 65 MSPS
TPC 3. SFDR vs. fOUT @ 125 MSPS
95
90
95
90
85
80
75
95
90
85
85
65MSPS
80
80
75
70
65
60
55
50
45
20mA
125MSPS
75
10mA
70
70
165MSPS
–6dBFS
5mA
65
60
55
50
45
65
–12dBFS
60
0dBFS
55
50
45
0
10
20
30
– MHz
40
50
60
0
5
10
15
– MHz
20
25
–25
–20
–15
–10
–5
0
f
f
A – dBFS
OUT
OUT
OUT
TPC 6. Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/11
TPC 4. SFDR vs. fOUT @ 165 MSPS
TPC 5. SFDR vs. fOUT and IOUTFS
@ 65 MSPS and 0 dBFS
95
90
85
90
95
78MSPS (10.1,12.1)
90
85
80
75
70
65
60
55
50
45
65MSPS (8.3,10.3)
85
5mA
65MSPS
80
80
75
10mA
125MSPS
125MSPS (16.9, 18.9)
75
70
20mA
65
165MSPS
165MSPS (22.6, 24.6)
70
65
60
55
50
45
60
170
–25
–20
–15
A
–10
– dBFS
–5
50
70
90
f
110
130
– MSPS
150
0
–25
–20
–15
A
–10
–5
0
– dBFS
OUT
CLOCK
OUT
TPC 8. SNR vs. fCLOCK and
IOUTFS @ fOUT = 5 MHz and 0 dBFS
TPC 9. Dual-Tone IMD vs. AOUT
@ fOUT = fCLOCK/7
TPC 7. Single-Tone SFDR vs.
OUT @ fOUT = fCLOCK/5
A
–7–
REV. 0
AD9742
90
85
80
75
70
65
60
55
50
1.0
0.8
1.0
4MHz
0.6
0.5
0.4
0.2
19MHz
49MHz
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
34MHz
–1.0
0
–40
–20
0
20
40
60
80
1024
2048
3072
4096
0
1024
2048
3072
4096
TEMPERATURE – ؇C
CODE
CODE
TPC 10. Typical INL
TPC 11. Typical DNL
TPC 12. SFDR vs. Temperature @
165 MSPS, 0 dBFS
0
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
fCLOCK = 78MSPS
fCLOCK = 78MSPS
fCLOCK = 78MSPS
–10
–10
–20
fOUT1 = 15.0MHz
fOUT = 15.0MHz
SFDR = 79dBc
fOUT1 = 15.0MHz
fOUT2 = 15.4MHz
SFDR = 77dBc
–20
–30
–40
–50
–60
–70
–80
–90
–100
fOUT2 = 15.4MHz
fOUT3 = 15.8MHz
fOUT4 = 16.2MHz
AMPLITUDE = 0dBFS
–30
–40
AMPLITUDE = 0dBFS
SFDR = 75dBc
AMPLITUDE = 0dBFS
–50
–60
–70
–80
–90
–100
1
6
11
16
21
26
31
36
1
6
11
16
21
26
31
36
1
6
11
16
21
26
31
36
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
TPC 13. Single-Tone SFDR
TPC 14. Dual-Tone SFDR
TPC 15. Four-Tone SFDR
–8–
REV. 0
AD9742
3.3V
REFLO
+1.20V REF
REFIO
AVDD
ACOM
150pF
AD9742
V
REFIO
PMOS
CURRENT SOURCE
ARRAY
I
REF
FS ADJ
0.1F
V
= V
– V
R
DIFF
OUTA OUTB
SET
2k⍀
3.3V
DVDD
IOUTA
IOUTB
IOUTA
V
OUTA
SEGMENTED SWITCHES
FOR DB11–DB3
LSB
DCOM
IOUTB
MODE
SWITCHES
V
OUTB
R
50⍀
LOAD
CLOCK
SLEEP
R
50⍀
LOAD
LATCHES
CLOCK
DIGITAL DATA INPUTS (DB11–DB0)
Figure 3. Simplified Block Diagram
REFERENCE OPERATION
FUNCTIONAL DESCRIPTION
The AD9742 contains an internal 1.2 V band gap reference.
The internal reference can be disabled by raising REFLO to
AVDD. It can also be easily overridden by an external reference
with no effect on performance. REFIO serves as either an input
or output depending on whether the internal or an external
reference is used. To use the internal reference, simply decouple
the REFIO pin to ACOM with a 0.1 mF capacitor and connect
REFLO to ACOM via a resistance less than 5 W. The internal
reference voltage will be present at REFIO. If the voltage at
REFIO is to be used anywhere else in the circuit, an external
buffer amplifier with an input bias current of less than 100 nA
should be used. An example of the use of the internal reference
is given in Figure 4.
Figure 3 shows a simplified block diagram of the AD9742. The
AD9742 consists of a DAC, digital control logic, and full-scale
output current control. The DAC contains a PMOS current
source array capable of providing up to 20 mA of full-scale
current (IOUTFS). The array is divided into 31 equal currents
that make up the five most significant bits (MSBs). The next
four bits, or middle bits, consist of 15 equal current sources
whose value is 1/16th of an MSB current source. The remaining
LSBs are binary weighted fractions of the middle bits current
sources. Implementing the middle and lower bits with current
sources, instead of an R-2R ladder, enhances its dynamic perfor-
mance for multitone or low amplitude signals and helps maintain
the DAC’s high output impedance (i.e., >100 kW).
3.3V
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS
differential current switches. The switches are based on the
architecture that was pioneered in the AD9764 family, with
further refinements to reduce distortion contributed by the
switching transient. This switch architecture also reduces
various timing errors and provides matching complementary
drive signals to the inputs of the differential current switches.
OPTIONAL
EXTERNAL
REF BUFFER
REFLO
+1.2V REF
REFIO
FS ADJ
AVDD
150pF
CURRENT
SOURCE
ARRAY
ADDITIONAL
LOAD
0.1F
2k⍀
AD9742
The analog and digital sections of the AD9742 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating up to a 165 MSPS clock rate,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.2 V band gap
voltage reference, and a reference control amplifier.
Figure 4. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 5. The external reference may provide either a fixed refer-
ence voltage to enhance accuracy and drift performance or a
varying reference voltage for gain control. Note that the 0.1 mF
compensation capacitor is not required since the internal refer-
ence is overridden, and the relatively high input impedance of
REFIO minimizes any loading of the external reference.
The DAC full-scale output current is regulated by the refer-
ence control amplifier and can be set from 2 mA to 20 mA via
an external resistor, RSET, connected to the full-scale adjust
(FSADJ) pin. The external resistor, in combination with both
3.3V
the reference control amplifier and voltage reference, VREFIO
sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
,
REFLO
+1.2V REF
REFIO
FS ADJ
150pF
AVDD
AVDD
full-scale current, IOUTFS, is 32 times IREF
.
V
REFIO
EXTERNAL
REF
CURRENT
SOURCE
ARRAY
R
I
=
SET
REF
V
/R
REFERENCE
REFIO SET
CONTROL
AMPLIFIER
AD9742
Figure 5. External Reference Configuration
REV. 0
–9–
AD9742
REFERENCE CONTROL AMPLIFIER
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can
The AD9742 contains a control amplifier that is used to regu-
late the full-scale output current, IOUTFS. The control amplifier
is configured as a V-I converter as shown in Figure 4, so that its
current output, IREF, is determined by the ratio of the VREFIO
and an external resistor, RSET, as stated in Equation 4. IREF is
copied to the segmented current sources with the proper scale
factor to set IOUTFS as stated in Equation 3.
be expressed as:
VDIFF = (2 ¥ DAC CODE – 4095)/ 4096
{
}
(8)
32¥ R
/ RSET ¥V
(
)
LOAD
REFIO
These last two equations highlight some of the advantages of
operating the AD9742 differentially. First, the differential
operation will help cancel common-mode error sources associ-
ated with IOUTA, and IOUTB such as noise, distortion, and dc
offsets. Second, the differential code dependent current and
subsequent voltage, VDIFF, is twice the value of the single-ended
voltage output (i.e., VOUTA or VOUTB), thus providing twice the
signal power to the load.
The control amplifier allows a wide (10:1) adjustment span of
I
OUTFS over a 2 mA to 20 mA range by setting IREF between
62.5 mA and 625 mA. The wide adjustment span of IOUTFS provides
several benefits. The first relates directly to the power dissipation
of the AD9742, which is proportional to IOUTFS (refer to the
Power Dissipation section). The second relates to the 20 dB
adjustment, which is useful for system gain control purposes.
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9742
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown in
Equation 8.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low-frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
ANALOG OUTPUTS
Both DACs in the AD9742 provide complementary current
outputs, IOUTA and IOUTB. IOUTA will provide a near full-
scale current output, IOUTFS, when all bits are high (i.e., DAC
CODE = 4095), while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA
and IOUTB is a function of both the input code and IOUTFS and
can be expressed as:
The complementary current outputs in each DAC, IOUTA and
IOUTB, may be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into comple-
mentary single-ended voltage outputs, VOUTA and VOUTB, via a
load resistor, RLOAD, as described in the DAC Transfer Function
section by Equations 5 through 8. The differential voltage, VDIFF
,
existing between VOUTA and VOUTB can also be converted to a
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9742 is optimum and
specified using a differential transformer coupled output in which
the voltage swing at IOUTA and IOUTB is limited to ±0.5 V.
(1)
IOUTA = (DAC CODE / 4096)¥ IOUTFS
(2)
IOUTB = (4095 – DAC CODE)/ 4096 ¥ IOUTFS
where DAC CODE = 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage,
REFIO, and external resistor, RSET. It can be expressed as:
The distortion and noise performance of the AD9742 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode error
sources include even-order distortion products and noise. The
enhancement in distortion performance becomes more signifi-
cant as the frequency content of the reconstructed waveform
increases and/or its amplitude decreases. This is due to the first
order cancellation of various dynamic common-mode distortion
mechanisms, digital feedthrough, and noise.
V
(3)
(4)
IOUTFS = 32¥ IREF
where
IREF =VREFIO / RSET
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note,
Performing a differential-to-single-ended conversion via a trans-
former also provides the ability to deliver twice the reconstructed
signal power to the load (i.e., assuming no source termination).
Since the output currents of IOUTA and IOUTB are comple-
mentary, they become additive when processed differentially. A
properly selected transformer will allow the AD9742 to provide
the required power and voltage levels to different loads.
R
LOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 W or 75 W cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply;
(5)
VOUTA = IOUTA ¥ RLOAD
VOUTB = IOUTB ¥ RLOAD
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kW in
parallel with 5 pF. It is also slightly dependent on the output
voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration will result in
the optimum dc linearity. Note the INL/DNL specifications
for the AD9742 are measured with IOUTA maintained at a
virtual ground via an op amp.
(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
(7)
VDIFF = (IOUTA – IOUTB)¥ RLOAD
–10–
REV. 0
AD9742
80
75
70
65
60
55
50
45
40
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9742.
fOUT = 20MHz
fOUT = 50MHz
The positive output compliance range is slightly dependent on the
full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.2 V for an IOUTFS = 20 mA to 1.0 V for an IOUTFS = 2 mA.
The optimum distortion performance for a single-ended or differ-
ential output is achieved when the maximum full-scale signal at
IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
–3
–2
–1
0
1
2
3
The AD9742’s digital section consists of 12 input bit channels
and a clock input. The 12-bit parallel data inputs follow stan-
dard positive binary coding where DB11 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
TIME (ns) OF DATA CHANGE RELATIVE
TO RISING CLOCK EDGE
Figure 7. SFDR vs. Clock Placement @ fOUT = 20 MHz
and 50 MHz
Sleep Mode Operation
The AD9742 has a power-down function that turns off the
output current and reduces the supply current to less than 4 mA
over the specified supply range of 3.0 V to 3.6 V and tempera-
ture range. This mode can be activated by applying a logic level
1 to the SLEEP pin. The SLEEP pin logic threshold is equal to
0.5 ¥ AVDD. This digital input also contains an active pull-
down circuit that ensures the AD9742 remains enabled if this
input is left disconnected. The AD9742 takes less than 50 ns to
power down and approximately 5 ms to power back up.
DVDD
DIGITAL
INPUT
POWER DISSIPATION
The power dissipation, PD, of the AD9742 is dependent on
several factors that include:
Figure 6. Equivalent Digital Input
The digital interface is implemented using an edge-triggered master/
slave latch. The DAC output updates on the rising edge of the clock
and is designed to support a clock rate as high as 165 MSPS. The
clock can be operated at any duty cycle that meets the specified
latch pulsewidth. The setup and hold times can also be varied
within the clock cycle as long as the specified minimum times are
met, although the location of these transition edges may affect
digital feedthrough and distortion performance. Best performance
is typically achieved when the input data transitions on the falling
edge of a 50% duty cycle clock.
•
•
•
•
The power supply voltages (AVDD and DVDD)
The full-scale current output IOUTFS
The update rate fCLOCK
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD
.
IAVDD is directly proportional to IOUTFS as shown in Figure 8
and is insensitive to fCLOCK. Conversely, IDVDD is dependent on
both the digital input waveform, fCLOCK, and digital supply
DVDD. Figure 9 shows IDVDD as a function of full-scale sine
wave output ratios (fOUT/fCLOCK) for various update rates with
DVDD = 3.3 V.
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relation-
ship between the position of the clock edges and the point in
time at which the input data changes. The AD9742 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9742 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 7 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
REV. 0
–11–
AD9742
35
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-to-single-
ended signal conversion as shown in Figure 10. A differentially
coupled transformer output provides the optimum distortion per-
formance for output signals whose spectral content lies within the
transformer’s pass band. An RF transformer, such as the Mini-
Circuits T1–1T, provides excellent rejection of common-mode
distortion (i.e., even-order harmonics) and noise over a wide fre-
quency range. It also provides electrical isolation and the ability to
deliver twice the power to the load. Transformers with different
impedance ratios may also be used for impedance matching pur-
poses. Note that the transformer provides ac coupling only.
30
25
20
15
10
MINI-CIRCUITS
0
2
4
6
8
10
OUTFS
12
– mA
14
16
18
20
T1-1T
IOUTA
I
R
LOAD
AD9742
Figure 8. IAVDD vs. IOUTFS
IOUTB
16
14
12
10
8
OPTIONAL R
DIFF
165MSPS
125MSPS
Figure 10. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB
)
swing symmetrically around ACOM and should be maintained
with the specified output compliance range of the AD9742. A
differential resistor, RDIFF, may be inserted in applications where
6
65MSPS
4
the output of the transformer is connected to the load, RLOAD
,
2
via a passive reconstruction filter or cable. RDIFF is determined by
the transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately
0
0.01
0.1
RATIO – fOUT
1
/fCLOCK
half the signal power will be dissipated across RDIFF
.
Figure 9. IDVDD vs. Ratio @ DVDD = 3.3 V
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-single-ended
conversion as shown in Figure 11. The AD9742 is configured with
two equal load resistors, RLOAD, of 25 W. The differential voltage
developed across IOUTA and IOUTB is converted to a single-ended
signal via the differential op amp configuration. An optional capaci-
tor can be installed across IOUTA and IOUTB, forming a real pole
in a low-pass filter. The addition of this capacitor also enhances the
op amp’s distortion performance by preventing the DACs high
slewing output from overloading the op amp’s input.
APPLYING THE AD9742
Output Configurations
The following sections illustrate some typical output configura-
tions for the AD9742. Unless otherwise noted, it is assumed
that IOUTFS is set to a nominal 20 mA. For applications requir-
ing the optimum dynamic performance, a differential output
configuration is suggested. A differential output configuration
may consist of either an RF transformer or a differential op amp
configuration. The transformer configuration provides the opti-
mum high frequency performance and is recommended for any
application that allows ac coupling. The differential op amp
configuration is suitable for applications requiring dc coupling, a
bipolar output, signal gain, and/or level shifting, within the
bandwidth of the chosen op amp.
500⍀
AD9742
225⍀
IOUTA
AD8047
225⍀
IOUTB
C
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor, RLOAD, referred to ACOM. This configuration
may be more suitable for a single-supply system requiring a
dc-coupled, ground referred output voltage. Alternatively, an
amplifier could be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This
configuration provides the best dc linearity since IOUTA or
IOUTB is maintained at a virtual ground.
OPT
500⍀
25⍀
25⍀
Figure 11. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential
op amp circuit using the AD8047 is configured to provide some
additional signal gain. The op amp must operate off of a dual
supply since its output is approximately ±1.0 V. A high-speed
amplifier capable of preserving the differential performance of the
–12–
REV. 0
AD9742
C
AD9742 while meeting other system level objectives (i.e., cost,
power) should be selected. The op amp’s differential gain, its gain
setting resistor values, and full-scale output swing capabilities
should all be considered when optimizing this circuit.
OPT
R
200⍀
FB
I
= 10mA
OUTFS
AD9742
The differential circuit shown in Figure 12 provides the necessary
level-shifting required in a single-supply system. In this case,
AVDD, which is the positive analog supply for both the AD9742
and the op amp, is also used to level shift the differential output
of the AD9742 to midsupply (i.e., AVDD/2).The AD8041 is a
suitable op amp for this application.
IOUTA
U1
V
= I
؋
R OUT
OUTFS FB
IOUTB
200⍀
Figure 14. Unipolar Buffered Voltage Output
500⍀
POWER AND GROUNDING CONSIDERATIONS,
POWER SUPPLY REJECTION
AD9742
225⍀
IOUTA
Many applications seek high-speed and high-performance under
less than ideal operating conditions. In these application circuits,
the implementation and construction of the printed circuit board
is as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figures 19 to 22 illustrate the recommended printed
circuit board ground, power, and signal plane layouts that are
implemented on the AD9742 evaluation board.
AD8041
225⍀
IOUTB
C
OPT
1k⍀
AVDD
25⍀
25⍀
1k⍀
Figure 12. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
Figure 13 shows the AD9742 configured to provide a unipo-
lar output range of approximately 0 V to 0.5 V for a doubly
terminated 50 W cable, since the nominal full-scale current,
IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 W.
In this case, RLOAD represents the equivalent load resistance
seen by IOUTA or IOUTB. The unused output (IOUTA or
IOUTB) can be connected to ACOM directly or via a match-
ing RLOAD. Different values of IOUTFS and RLOAD can be selected
as long as the positive compliance range is adhered to. One
additional consideration in this mode is the integral nonlinearity
(INL) as discussed in the Analog Output section of this data
sheet. For optimum INL performance, the single-ended, buffered
voltage output configuration is suggested.
One factor that can measurably affect system performance is the
ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio. For dc
variations of the power supply, the resulting performance of the
DAC directly corresponds to a gain error associated with the
DAC’s full-scale current, IOUTFS. AC noise on the dc supplies is
common in applications where the power distribution is gener-
ated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR vs frequency of the AD9742 AVDD
supply over this frequency range is shown in Figure 15.
85
80
75
AD9742
I
= 20mA
OUTFS
V
= 0V TO 0.5V
OUTA
IOUTA
50⍀
50⍀
70
65
IOUTB
25⍀
60
55
50
45
Figure 13. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 14 shows a buffered single-ended output configuration in
which the op amp U1 performs an I-V conversion on the AD9742
output current. U1 maintains IOUTA (or IOUTB) at a virtual
ground, minimizing the nonlinear output impedance effect on the
DAC’s INL performance as discussed in the Analog Output section.
Although this single-ended configuration typically provides the best
dc linearity performance, its ac distortion performance at higher
DAC update rates may be limited by U1’s slew rate capabilities.
U1 provides a negative unipolar output voltage and its full-scale
output voltage is simply the product of RFB and IOUTFS. The full-
scale output should be set within U1’s voltage output swing
capabilities by scaling IOUTFS and/or RFB. An improvement in ac
distortion performance may result with a reduced IOUTFS since
U1 will be required to sink less signal current.
40
0
2
4
6
8
10
12
FREQUENCY – MHz
Figure 15. Power Supply Rejection Ratio
Note that the units in Figure 15 are given in units of (amps out/
volts in). Noise on the analog power supply has the effect of
modulating the internal switches, and therefore the output current.
The voltage noise on AVDD, therefore, will be added in a
nonlinear manner to the desired IOUT. Due to the relative
different size of these switches, PSRR is very code dependent.
This can produce a mixing effect that can modulate low-frequency
power supply noise to higher frequencies. Worst-case PSRR for
REV. 0
–13–
AD9742
FERRITE
BEADS
either one of the differential DAC outputs will occur when the
full-scale current is directed toward that output. As a result, the
PSRR measurement in Figure 15 represents a worst-case condition in
which the digital inputs remain static and the full-scale output
current of 20 mA is directed to the DAC output being measured.
AVDD
TTL/CMOS
LOGIC
100F
10–22F
0.1F
CIRCUITS
ELECT.
TANT.
CER.
ACOM
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity
sake (i.e., ignore harmonics), all of this noise is concentrated at
250 kHz. To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC’s full-scale
current, IOUTFS, one must determine the PSRR in dB using
Figure 15 at 250 kHz. To calculate the PSRR for a given RLOAD
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 15 by the scaling factor 20 ¥ log(RLOAD).
For instance, if RLOAD is 50 W, the PSRR is reduced by 34 dB (i.e.,
PSRR of the DAC at 250 kHz which is 85 dB in Figure 15
becomes 51 dB VOUT/VIN).
3.3V
POWER SUPPLY
Figure 16. Differential LC Filter for Single 3.3 V Applications
EVALUATION BOARD
General Description
,
The TxDAC Family Evaluation Board allows for easy set up
and testing of any TxDAC product in the 28-lead SOIC pack-
age. Careful attention to layout and circuit design combined
with a prototyping area allow the user to evaluate the AD9742
easily and effectively in any application where high resolution,
high-speed conversion is required.
Proper grounding and decoupling should be a primary objective
in any high-speed, high resolution system. The AD9742 features
separate analog and digital supply and ground pins to optimize
the management of analog and digital ground currents in a system.
In general, AVDD, the analog supply, should be decoupled to
ACOM, the analog common, as close to the chip as physically
possible. Similarly, DVDD, the digital supply, should be decoupled
to DCOM as close to the chip as physically possible.
This board allows the user the flexibility to operate the AD9742
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, and single and differ-
ential outputs. The digital inputs are designed to be driven from
various word generators, with the on-board option to add a
resistor network for proper load termination. Provisions are also
made to operate the AD9742 with either the internal or external
reference or to exercise the power-down feature.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 16. The circuit
consists of a differential LC filter with separate power supply
and return lines. Lower noise can be attained by using low ESR
type electrolytic and tantalum capacitors.
–14–
REV. 0
AD9742
J1
2
4
6
1
3
5
7
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
8
RP5
50
RP1
50
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
RP3
RP3
RP3
RP3
RP3
RP3
RP3
RP3
RP4
RP4
RP4
RP4
RP4
RP4
RP4
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
16
15
14
13
12
11
10
9
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
16
15
14
13
12
11
10
JP3
CKEXTX
RP4
22
8
9
CKEXT
CKEXTX
RIBBON
RP6
50
RP2
50
RED
TP2
L2
10H
DVDD
TB1
TB1
TB1
TB1
1
2
3
4
C4
+
+
C7
C6
10F
25V
BLK
BLK
TP7
BLK
TP8
0.1F
0.1F
TP4
RED
TP5
L3
10H
AVDD
C5
C9
C8
10F
25V
BLK
TP6
BLK
TP10
BLK
TP9
0.1F
0.1F
Figure 17. Evaluation Board: Power Supply and Digital Inputs
REV. 0
–15–
AD9742
AVDD
CUT
C14
+
+
UNDER DUT
C16
C17
10F
16V
0.1F
0.1F
JP6
DVDD
DVDD
C15
JP10
C18
C19
10F
16V
1
3
0.1F
0.1F
A
B
IX
2
R5
10k⍀
S2
CLOCK
S5
R11
IOUTA
50⍀
CKEXT
CLOCK
DVDD
JP4
R4
TP1
50⍀
WHT
R2
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
C13
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLOCK
DVDD
DB13
DB12
DB11
DB10
DB9
10k⍀
10pF
2
3
4
5
6
7
8
9
10
11
12
13
14
JP8
T1
DVDD
JP2
IOUT
S3
DCOM
MODE
AVDD
RESERVED
IOUTA
MODE
3
2
1
4
5
6
AVDD
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R6
OPT
ADU91742
IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
T1-1T
JP9
REF
TP3
C1
0.1F
C2
WHT
0.1F
C12
C11
10pF
R1
2k⍀
0.1F
AVDD
2
R10
50⍀
AVDD
A
B
3
SLEEP
S1
IOUTB
1
TP11
WHT
JP5
REF
INT
EXT
R3
2
IY
10k⍀
A
B
3
1
JP11
Figure 18. Evaluation Board: Output Signal Conditioning
–16–
REV. 0
AD9742
Figure 19. Primary Side
Figure 20. Secondary Side
–17–
REV. 0
AD9742
Figure 21. Ground Plane
Figure 22. Power Plane
–18–
REV. 0
AD9742
Figure 23. Assembly – Primary Side
Figure 24. Assembly – Secondary Side
–19–
REV. 0
AD9742
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
28-Lead Standard Small Outline Package (SOIC)
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
14
1
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
؋
45؇ 0.0500 (1.27)
8؇
0؇ 0.0157 (0.40)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
0.0125 (0.32)
0.0091 (0.23)
PLANE
28-Lead Thin Shrink SO Package (TSSOP)
(RU-28)
0.386 (9.80)
0.378 (9.60)
15
14
28
1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8؇
0؇
0.0118 (0.30)
0.0075 (0.19)
0.0256 (0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
–20–
REV. 0
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