AD9777BSV_技术文档

16-Bit, 160 MSPS 2ꢀ/4ꢀ/8ꢀ

®

a

Interpolating Dual TxDAC+ D/A Converter

AD9777^*

FEATURES

APPLICATIONS

16-Bit Resolution, 160/400 MSPS Input/Output Data Rate

Selectable 2ꢀ/4ꢀ/8ꢀ Interpolating Filter

Programmable Channel Gain and Offset Adjustment

f_S/4, f_S/8 Digital Quadrature Modulation

Capability

Communications

Analog Quadrature Modulation Architectures

3G, Multicarrier GSM, TDMA, CDMA Systems

Broadband Wireless, Point-to-Point Microwave Radios

Instrumentation/ATE

Direct IF Transmission Mode for 70 MHz + IFs

Enables Image Rejection Architecture

Fully Compatible SPI Port

Excellent AC Performance

SFDR –73 dBc @ 2 MHz–35 MHz

WCDMA ACPR 71 dB @ IF = 71 MHz

Internal PLL Clock Multiplier

Selectable Internal Clock Divider

Versatile Clock Input

Differential/Single-Ended Sine Wave or

TTL/CMOS/LVPECL Compatible

Versatile Input Data Interface

GENERAL DESCRIPTION

The AD9777 is the 16-bit member of the AD977x pin compatible,

high performance, programmable 2×/4×/8× interpolating TxDAC+

family. The AD977x family features a serial port interface (SPI)

providing a high level of programmability, thus allowing for

enhanced system level options. These options include: selectable

2×/4×/8× interpolation filters; f_S/2, f_S/4, or f_S/8 digital quadrature

modulation with image rejection; a direct IF mode; programmable

channel gain and offset control; programmable internal clock

divider; straight binary or two’s complement data interface; and

a single-port or dual-port data interface.

Two’s Complement/Straight Binary Data Coding

Dual-Port or Single-Port Interleaved Input Data

Single 3.3 V Supply Operation

Power Dissipation: Typical 1.2 W @ 3.3 V

On-Chip 1.2 V Reference

The selectable 2×/4×/8× interpolation filters simplify the require-

ments of the reconstruction filters while simultaneously enhancing

the TxDAC+ family’s pass-band noise/distortion performance.

The independent channel gain and offset adjust registers allow

the user to calibrate LO feedthrough and sideband suppression

(continued on page 2)

80-Lead Thermally Enhanced TQFP Package

FUNCTIONAL BLOCK DIAGRAM

IDAC

COS

AD9777

HALF-

BAND

HALF-

BAND

HALF-

BAND

OFFSET

DAC

GAIN

DAC

*

FILTER 1

FILTER 2 FILTER 3

DATA

SIN

f_DAC/2, 4, 8

SIN

ASSEMBLER

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

16

I

I/Q DAC

GAIN/OFFSET

REGISTERS

LATCH

I AND Q

NONINTERLEAVED

OR

INTERLEAVED

DATA

16

Q

LATCH

16

FILTER

BYPASS

MUX

COS

WRITE

MUX

CONTROL

I

IDAC

OUT

SELECT

/2

(f_DAC)

CLOCK OUT

/2

PRESCALER

SPI INTERFACE AND

CONTROL REGISTERS

DIFFERENTIAL

CLK

PHASE DETECTOR

AND VCO

*

HALF-BAND FILTERS ALSO CAN BE

CONFIGURED FOR "ZERO STUFFING ONLY"

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

TxDAC+ is a registered trademark of Analog Devices, Inc.

*Protected by U.S. Patent Numbers, 5568145, 5689257, and 5703519. Other patents pending.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

AD9777

(continued from page 1)

PRODUCT HIGHLIGHTS

errors associated with analog quadrature modulators. The 6 dB

of gain adjustment range can also be used to control the output

power level of each DAC.

1.

The AD9777 is the 16-bit member of the AD977x pin-

compatible, high performance, programmable 2× /4×/8×

interpolating TxDAC+ family.

The AD9777 features the ability to perform f_S/2, f_S/4, and f_S/8

digital modulation and image rejection when combined with an

analog quadrature modulator. In this mode, the AD9777 accepts

I and Q complex data (representing a single or multicarrier wave-

form), generates a quadrature modulated IF signal along with its

orthogonal representation via its dual DACs, and presents these

two reconstructed orthogonal IF carriers to an analog quadrature

modulator to complete the image rejection upconversion process.

Another digital modulation mode (i.e., the Direct IF Mode)

allows the original baseband signal representation to be frequency

translated such that pairs of images fall at multiples of one-half

the DAC update rate.

2.

3.

Direct IF transmission is possible for 70 MHz + IFs through

a novel digital mixing process.

f_S/2, f_S/4, and f_S/8 digital quadrature modulation and

user-selectable image rejection simplify/remove cascaded

SAW filter stages.

4.

5.

6.

7.

A 2×/4×/8× user-selectable interpolating filter eases data

rate and output signal reconstruction filter requirements.

User-selectable two’s complement/straight binary data

coding.

User programmable channel gain control over 1 dB range

in 0.01 dB increments.

The AD977x family includes a flexible clock interface accepting

differential or single-ended sine wave or digital logic inputs. An

internal PLL clock multiplier is included and generates the

necessary on-chip high frequency clocks. It can also be disabled

to allow the use of a higher performance external clock source. An

internal programmable divider simplifies clock generation in the

converter when using an external clock source. A flexible data

input interface allows for straight binary or two’s complement

formats and supports single-port interleaved or dual-port data.

User-programmable channel offset control 10% over

the FSR.

8.

9.

Ultra high speed 400 MSPS DAC conversion rate.

Internal clock divider provides data rate clock for easy

interfacing.

10. Flexible clock input with single-ended or differential input,

CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: Complete CMOS DAC operates on 1.2 W

from a 3.1 V to 3.5 V single supply. The 20 mA full-scale

current can be reduced for lower power operation, and

several sleep functions are provided to reduce power during

idle periods.

Dual high performance DAC outputs provide a differential

current output programmable over a 2 mA to 20 mA range. The

AD9777 is manufactured on an advanced 0.35 micron CMOS

process, operates from a single supply of 3.1 V to 3.5 V, and

consumes 1.2 W of power.

12. On-chip voltage reference: The AD9777 includes a 1.20 V

temperature compensated band gap voltage reference.

Targeted at wide dynamic range, multicarrier and multistandard

systems, the superb baseband performance of the AD9777 is

ideal for wideband CDMA, multicarrier CDMA, multicarrier

TDMA, multicarrier GSM, and high performance systems

employing high order QAM modulation schemes. The image

rejection feature simplifies and can help to reduce the number

of signal band filters needed in a transmit signal chain. The

direct IF mode helps to eliminate a costly mixer stage for a

variety of communications systems.

13. 80-lead thermally enhanced TQFP.

–2–

REV. 0

AD9777

AD9777–SPECIFICATIONS

(T_MINto T_MAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I_OUTFS= 20 mA, unless

DC SPECIFICATIONS

otherwise noted.)

Parameter

Min

Typ

Max

Unit

RESOLUTION

16

Bits

DC Accuracy¹

Integral Nonlinearity

Differential Nonlinearity

6

3

LSB

–6.5

+6.5

ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)

Offset Error

–0.025

–1.0

–1

2

–1.0

0.01

0.1

+0.025

+1.0

+1

20

+1.25

% of FSR

mA

V

kΩ

pF

Gain Error (with Internal Reference)

Gain Matching

Full-Scale Output Current²

Output Compliance Range

Output Resistance

200

Output Resistance

3

Gain, Offset Cal DACs, Monotonicity Guaranteed

REFERENCE OUTPUT

Reference Voltage

1.14

0.1

1.20

100

1.26

1.25

V

nA

Reference Output Current³

REFERENCE INPUT

Input Compliance Range

V

Reference Input Resistance (REFLO = 3 V)

Small Signal Bandwidth

10

0.5

MΩ

MHz

TEMPERATURE COEFFICIENTS

Offset Drift

Gain Drift (With Internal Reference)

Reference Voltage Drift

0

50

ppm of FSR/°C

ppm/°C

POWER SUPPLY

AVDD

Voltage Range

3.1

3.3

72.5

23.3

3.5

76

26

V

mA

4

Analog Supply Current (I_AVDD

I_AVDDin SLEEP Mode

CLKVDD (PLL OFF)

Voltage Range

Clock Supply Current (I_CLKVDD

CLKVDD (PLL ON)

Clock Supply Current (I_CLKVDD

DVDD

)

3.3

8.5

3.5

V

mA

4

)

23.5

mA

Voltage Range

3.1

3.3

34

380

1.75

6.0

0.4

3.5

41

410

V

mA

mW

W

mW

% of FSR/V

4

Digital Supply Current (I_DVDD

)

Nominal Power Dissipation⁴

5

P_DIS

P

_DISin PWDN

Power Supply Rejection Ratio—AVDD

OPERATING RANGE

–40

+85

°C

NOTES

¹Measured at I_OUTAdriving a virtual ground.

²Nominal full-scale current, I_OUTFS, is 32× the I_REFcurrent.

³Use an external amplifier to drive any external load.

⁴100 MSPS f_DACwith f_OUT= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

⁵400 MSPS f_DAC, f_DATA= 50 MSPS, f_S/2 modulation, PLL enabled.

Specifications subject to change without notice.

REV. 0

–3–

AD9777

(T_MINto T_MAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I_OUTFS= 20 mA,

Interpolation = 2ꢀ, Differential Transformer Coupled Output, 50 ꢁ Doubly Terminated,

unless otherwise noted.)

DYNAMIC SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f_DAC

Output Settling Time (t_ST) (to 0.025%)

Output Rise Time (10% to 90%)*

Output Fall Time (10% to 90%)*

Output Noise (I_OUTFS= 20 mA)

)

400

MSPS

ns

pA√Hz

11

0.8

50

AC LINEARITY—BASEBAND MODE

Spurious-Free Dynamic Range (SFDR) to Nyquist (f_OUT= 0 dBFS)

f_DATA= 100 MSPS, f_OUT= 1 MHz

f_DATA= 65 MSPS, f_OUT= 1 MHz

f_DATA= 65 MSPS, f_OUT= 15 MHz

f_DATA= 78 MSPS, f_OUT= 1 MHz

71

73

85

84

85

83

85

83

dBc

f_DATA= 78 MSPS, f_OUT= 15 MHz

f_DATA= 160 MSPS, f_OUT= 1 MHz

f

_DATA= 160 MSPS, f_OUT= 15 MHz

Spurious-Free Dynamic Range within a 1 MHz Window

(f_OUT= 0 dBFS, f_DATA= 100 MSPS, f_OUT= 1 MHz)

99.1

Two-Tone Intermodulation (IMD) to Nyquist (f_OUT1= f_OUT2= –6 dBFS)

f_DATA= 65 MSPS, f_OUT1= 10 MHz; f_OUT2= 11 MHz

f_DATA= 65 MSPS, f_OUT1= 20 MHz; f_OUT2= 21 MHz

85

78

85

78

85

84

dBc

f

_DATA= 78 MSPS, f_OUT1= 10 MHz; f_OUT2= 11 MHz

f_DATA= 78 MSPS, f_OUT1= 20 MHz; f_OUT2= 21 MHz

f_DATA= 160 MSPS, f_OUT1= 10 MHz; f_OUT2= 11 MHz

f

_DATA= 160 MSPS, f_OUT1= 20 MHz; f_OUT2= 21 MHz

Total Harmonic Distortion (THD)

f_DATA= 100 MSPS, f_OUT= 1 MHz; 0 dBFS

Signal-to-Noise Ratio (SNR)

–71

–83

dB

f_DATA= 78 MSPS, f_OUT= 5 MHz; 0 dBFS

f_DATA= 160 MSPS, f_OUT= 5 MHz; 0 dBFS

Adjacent Channel Power Ratio (ACLR)

WCDMA with MHz BW, MHz Channel Spacing

IF = Baseband, f_DATA= 76.8 MSPS

IF = 19.2 MHz, f_DATA= 76.8 MSPS

Four-Tone Intermodulation

79

75

dB

77

73

dBc

21 MHz, 22 MHz, 23 MHz, and 24 MHz at –12 dBFS

(f_DATA= MSPS, Missing Center)

76

dBFS

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

201 MHz, 202 MHz, 203 MHz, and 204 MHz at –12 dBFS

(f_DATA= 160 MSPS, f_DAC= 320 MHz)

72

dBFS

*Measured single ended into 50 Ω load.

Specifications subject to change without notice.

–4–

REV. 0

AD9777

(T_MINto T_MAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I_OUTFS= 20 mA, unless

DIGITAL SPECIFICATIONS ^{otherwise noted.)}

Parameter

Min

Typ

Max

Unit

DIGITAL INPUTS

Logic “1” Voltage

Logic “0” Voltage

Logic “1” Current

Logic “0” Current

Input Capacitance

2.1

3

0

V

µA

pF

0.9

+10

–10

5

CLOCK INPUTS

Input Voltage Range

Common-Mode Voltage

Differential Voltage

0

0.75

0.5

3

2.25

V

1.5

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Parameter

With Respect to

Min

Max

Unit

AVDD, DVDD, CLKVDD

AGND, DGND, CLKGND

REFIO, REFLO, FSADJ1/2

I_OUTA, I_OUTB

P1B15–P1B0, P2B15–P2B0

DATACLK, PLL_LOCK

CLK+, CLK–, RESET

LPF

SPI_CSB, SPI_CLK,

SPI_SDIO, SPI_SDO

Junction Temperature

Storage Temperature

Lead Temperature (10 sec)

AGND, DGND, CLKGND

AVDD, DVDD, CLKVDD

AGND, DGND, CLKGND

AGND

DGND

CLKGND

DGND

–0.3

–4.0

–0.3

–1.0

–0.3

+4.0

+0.3

AVDD + 0.3

DVDD + 0.3

CLKVDD + 0.3

DVDD + 0.3

V

+125

+150

+300

°C

–65

*Stresses above those listed under the ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only; functional

operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum ratings for extended periods may affect device reliability.

ORDERING GUIDE

THERMAL CHARACTERISTICS

Thermal Resistance

80-Lead Thermally Enhanced

Temperature

Range

Package

Description

Package

Option*

Model

TQFP Package ␪_JA= 23.5 °C/W*

AD9777BSV –40°C to +85°C 80-Lead TQFP

SV-80

*With thermal pad soldered to PCB.

AD9777EB

Evaluation Board

*SV = Thin Plastic Quad Flatpack

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD9777 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD9777

PIN CONFIGURATION

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1

2

CLKVDD

LPF

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

FSADJ1

FSADJ2

REFIO

RESET

SPI_CSB

SPI_CLK

SPI_SDIO

SPI_SDO

DGND

PIN 1

IDENTIFIER

3

CLKVDD

CLKGND

CLK+

4

5

6

CLK–

7

CLKGND

DATACLK/PLL_LOCK

8

AD9777

TxDAC+

TOP VIEW

(Not to Scale)

9

DGND

DVDD

10

11

12

13

14

15

16

17

18

19

20

DVDD

P1B15 (MSB)

P1B14

P2B0 (LSB)

P2B1

P1B13

P2B2

P1B12

P2B3

P1B11

P2B4

P1B10

P2B5

DGND

DVDD

P1B9

P2B6

P1B8

P2B7

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

–6–

REV. 0

AD9777

PIN FUNCTION DESCRIPTIONS

Description

Pin Number

Mnemonic

1, 3

2

CLKVDD

LPF

Clock Supply Voltage

PLL Loop Filter

4, 7

5

6

CLKGND

CLK+

CLK–

Clock Supply Common

Differential Clock Input

8

DATACLK/PLL_LOCK

With the PLL enabled, this pin indicates the state of the PLL. A read of a

Logic “1” indicates the PLL is in the locked state. Logic “0” indicates the

PLL has not achieved lock. This pin may also be programmed to act as

either an input or output (Address 02h, Bit 3) DATACLK signal running at

the input data rate.

9, 17, 25, 35, 44, 52

DGND

Digital Common

10, 18, 26, 36, 43, 51 DVDD

Digital Supply Voltage

11–16, 19–24, 27–30 P1B15 (MSB) to P1B0 (LSB) Port “1” Data Inputs

31

IQSEL/P2B15 (MSB)

In “1” port mode, IQSEL = 1 followed by a rising edge of the differential

input clock will latch the data into the I channel input register. IQSEL = 0

will latch the data into the Q channel input register. In “2” port mode, this

pin becomes the port “2” MSB.

32

ONEPORTCLK/P2B14

With the PLL disabled and the AD9777 in “1” port mode, this pin becomes

a clock output that runs at twice the input data rate of the I and Q channels.

This allows the AD9777 to accept and demux interleaved I and Q data to

the I and Q input registers.

33, 34, 37–42, 45–50 P2B13 to P2B0 (LSB)

Port “2” Data Inputs

53

54

55

56

57

SPI_SDO

SPI_SDIO

SPI_CLK

SPI_CSB

RESET

In the case where SDIO is an input, SDO acts as an output. When SDIO

becomes an output, SDO enters a High-Z state.

Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register

Address 00h. The default setting for this bit is “0,” which sets SDIO as an input.

Data input to the SPI port is registered on the rising edge of SPI_CLK.

Data output on the SPI port is registered on the falling edge.

Chip Select/SPI Data Synchronization. On momentary logic high, resets

SPI port logic and initializes instruction cycle.

Logic “1” resets all of the SPI port registers, including Address 00h, to their

default values. A software reset can also be done by writing a Logic “1” to

SPI Register 00h, Bit 5. However, the software reset has no effect on the bits

in Address 00h.

58

59

60

REFIO

FSADJ2

FSADJ1

Reference Output, 1.2 V Nominal

Full-Scale Current Adjust, Q Channel

Full-Scale Current Adjust, I Channel

Analog Supply Voltage

61, 63, 65, 76, 78, 80 AVDD

62, 64, 66, 67, 70, 71, AGND

74, 75, 77, 79

Analog Common

68, 69

72, 73

I

_OUTA2, I_OUTB2

Differential DAC Current Outputs, Q Channel

Differential DAC Current Outputs, I Channel

I_OUTA1, I_OUTB1

REV. 0

–7–

AD9777

DIGITAL FILTER SPECIFICATIONS

20

0

Half-Band Filter No. 1 (43 Coefficients)

–20

–40

–60

–80

–100

Tap

Coefficient

1, 43

2, 42

3, 41

4, 40

5, 39

6, 38

7, 37

8, 36

8

0

–29

0

67

0

–134

0

244

0

–414

0

673

0

–1079

0

1772

0

–3280

0

–120

9, 35

0

0.5

1.0

1.5

2.0

10, 34

11, 33

12, 32

13, 31

14, 30

15, 29

16, 28

17, 27

18, 26

19, 25

20, 24

21, 23

22

f

– Normalized to Input Data Rate

OUT

Figure 1a. 2ꢀ Interpolating Filter Response

20

0

–20

–40

–60

–80

–100

10364

16384

Half-Band Filter No. 2 (19 Coefficients)

Tap

Coefficient

–120

0

0.5

1.0

1.5

2.0

1, 19

2, 18

3, 17

4, 16

5, 15

6, 14

7, 13

8, 12

9, 11

10

19

0

–120

0

438

0

–1288

0

5047

8192

f

– Normalized to Input Data Rate

OUT

Figure 1b. 4ꢀ Interpolating Filter Response

20

0

–20

–40

–60

Half-Band Filter No. 3 (11 Coefficients)

–80

Tap

Coefficient

1, 11

2, 10

3, 9

4, 8

5, 7

6

7

0

–53

0

302

512

–100

–120

0

2

4

6

8

f

– Normalized to Input Data Rate

OUT

Figure 1c. 8ꢀ Interpolating Filter Response

–8–

REV. 0

AD9777

Offset Error

DEFINITIONS OF SPECIFICATIONS

Adjacent Channel Power Ratio (ACPR)

A ratio in dBc between the measured power within a channel

relative to its adjacent channel.

The deviation of the output current from the ideal of “0” is

called offset error. For I_OUTA, 0 mA output is expected when the

inputs are all “0.” For I_OUTB, 0 mA output is expected when all

inputs are set to “1.”

Complex Image Rejection

Output Compliance Range

In a traditional two-part upconversion, two images are created

around the second IF frequency. These images are redundant

and have the effect of wasting transmitter power and system

bandwidth. By placing the real part of a second complex modu-

lator in series with the first complex modulator, either the upper

or lower frequency image near the second IF can be rejected.

The range of allowable voltage at the output of a current-output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

Pass Band

Frequency band in which any input applied therein passes

unattenuated to the DAC output.

Complex Modulation

The process of passing the real and imaginary components of a

signal through a complex modulator (transfer function = e^j␻t

=

Power Supply Rejection

The maximum change in the full-scale output as the supplies

are varied from minimum to maximum specified voltages.

cos␻t + jsin␻t) and realizing real and imaginary components on

the modulator output.

Differential Nonlinearity (DNL)

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the Nyquist

frequency, excluding the first six harmonics and dc. The value

for SNR is expressed in decibels.

Gain Error

The difference between the actual and ideal output span. The

actual span is determined by the output when all inputs are set

to “1,” minus the output when all inputs are set to “0.”

Spurious-Free Dynamic Range

The difference, in dB, between the rms amplitude of the output

signal and the peak spurious signal over the specified bandwidth.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in pV–S.

Settling Time

The time required for the output to reach and remain within a

specified error band about its final value, measured from the

start of the output transition.

Group Delay

Number of input clocks between an impulse applied at the

device input and peak DAC output current. A half-band FIR

filter has constant group delay over its entire frequency range.

Stop-Band Rejection

The amount of attenuation of a frequency outside the pass band

applied to the DAC, relative to a full-scale signal applied at the

DAC input within the pass band.

Impulse Response

Response of the device to an impulse applied to the input.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (25°C) value to the value at either T_MINor T_MAX. For

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per °C. For reference drift, the drift is reported in

ppm per °C.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

f_DATA(interpolation rate), a digital filter can be constructed that has a

sharp transition band near f_DATA/2. Images that would typically

appear around f_DAC(output data rate) can be greatly suppressed.

Total Harmonic Distortion (THD)

Linearity Error (Also Called Integral Nonlinearity or INL)

Linearity error is defined as the maximum deviation of the actual

analog output from the ideal output, determined by a straight

line drawn from zero to full scale.

THD is the ratio of the rms sum of the first six harmonic com-

ponents to the rms value of the measured fundamental. It is

expressed as a percentage or in decibels (dB).

Monotonicity

A D/A converter is monotonic if the output either increases or

remains constant as the digital input increases.

REV. 0

–9–

–Typical Performance Characteristics

AD9777

(T = 25ꢂC, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I_OUTFS= 20 mA, Interpolation = 2ꢀ, Differential Coupled Transformer Output, 50 ꢁ

Doubly Terminated, unless otherwise noted.)

90

85

90

85

10

0dBFS

–6dBFS

0dBFS

–12dBFS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

80

75

70

65

60

55

50

80

75

70

65

60

55

50

–12dBFS

–6dBFS

0

5

10

15

20

25

30

50

0

5

10

15

20

25

30

0

65

130

FREQUENCY – MHz

TPC 1. Single-Tone Spec-

trum @ f_DATA= 65 MSPS with

_OUT= f_DATA/3

TPC 2. In-Band SFDR vs. f_OUT

@ f_DATA= 65 MSPS

TPC 3. Out-of-Band SFDR vs.

_OUT@ f_DATA= 65 MSPS

f

90

85

90

85

10

0dBFS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

80

75

70

65

60

55

50

80

75

70

65

60

55

50

–6dBFS

–12dBFS

–6dBFS

–12dBFS

0

5

10

15

20

25

0

5

10

15

20

25

30

0

50

100

150

FREQUENCY – MHz

TPC 4. Single-Tone Spec-

trum @ f_DATA= 78 MSPS with

f_OUT= f_DATA/3

TPC 5. In-Band SFDR vs. f_OUT

@ f_DATA= 78 MSPS

TPC 6. Out-of-Band SFDR vs.

f_OUT@ f_DATA= 78 MSPS

90

85

90

85

10

0dBFS

–6dBFS

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

80

75

70

65

60

55

50

80

75

70

65

60

55

50

–12dBFS

–6dBFS

–12dBFS

0dBFS

0

10

20

30

40

50

0

10

20

30

40

0

100

200

300

FREQUENCY – MHz

TPC 7. Single-Tone Spec-

trum @ f_DATA= 160 MSPS

with f_OUT= f_DATA/3

TPC 8. In-Band SFDR vs. f_OUT

@ f_DATA= 160 MSPS

TPC 9. Out-of-Band SFDR vs.

f_OUT@ f_DATA= 160 MSPS

–10–

REV. 0

AD9777

(T = 25ꢂC, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I_OUTFS= 20 mA, Interpolation = 2ꢀ, Differential Coupled Transformer Output, 50 ꢁ

Doubly Terminated, unless otherwise noted.)

90

85

90

85

0dBFS

85

80

75

70

65

60

55

50

80

75

70

65

60

55

50

80

75

70

65

60

55

50

–3dBFS

–6dBFS

–3dBFS

–6dBFS

0

5

10

15

20

25

30

0

5

10

15

20

25

30

0

10

20

30

40

50

60

FREQUENCY – MHz

TPC 10. Third Order IMD Products

vs. Two-Tone f_OUT@ f_DATA= 65 MSPS

TPC 11. Third Order IMD Products

vs. Two-Tone f_OUT@ f_DATA= 78 MSPS

TPC 12. Third Order IMD Products

vs. Two-Tone f_OUT@ f_DATA= 160 MSPS

90

8ꢀ

4ꢀ

85

80

75

70

65

60

55

50

0dBFS

80

8ꢀ

–6dBFS

4ꢀ

75

1ꢀ

–12dBFS

2ꢀ

70

2ꢀ

65

60

55

50

60

55

50

0

10

20

30

40

50

60

–15

–10

A

–5

– dBFS

0

3.1

3.2

3.3

AVDD – V

3.4

3.5

FREQUENCY – MHz

OUT

TPC 13. Third Order IMD Products

vs. Two-Tone f_OUTand Interpola-

tion Rate

1ϫ f_DATA= 160 MSPS,

2ϫ f_DATA= 160 MSPS,

4ϫ f_DATA= 80 MSPS,

TPC 15. SFDR vs. AVDD @

f_OUT= 10 MHz, f_DAC= 320 MSPS,

f_DATA= 160 MSPS

TPC 14. Third Order IMD Products vs.

Two-Tone A_OUTand Interpolation Rate

f_DATA= 50 MSPS for All Cases

1ϫ f_DAC= 50 MSPS,

2ϫ f_DAC= 100 MSPS,

4ϫ f_DAC= 200 MSPS,

8ϫ f_DATA= 50 MSPS

8ϫ f_DAC= 400 MSPS

90

78MSPS

0dBFS

85

80

75

70

65

60

55

50

PLL OFF

–3dBFS

80

75

–6dBFS

75

70

65

60

55

50

160MSPS

FDATA = 65MSPS

70

PLL ON

65

60

55

50

–50

0

50

100

3.1

3.2

3.3

3.4

3.5

0

50

100

150

TEMPERATURE – ꢂC

AVDD – V

INPUT DATA RATE – MSPS

TPC 16. Third Order IMD Products

vs. AVDD @ f_OUT= 10 MHz,

TPC 17. SNR vs. Data Rate for

f_OUT= 5 MHz

TPC 18. SFDR vs. Temperature @

f_OUT= f_DATA/11

f_DAC= 320 MSPS, f_DATA= 160 MSPS

REV. 0

–11–

AD9777

(T = 25ꢂC, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I_OUTFS= 20 mA, Interpolation = 2ꢀ, Differential Coupled Transformer Output, 50 ꢁ

Doubly Terminated, unless otherwise noted.)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–20

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–40

–60

–80

–100

10

20

30

40

50

200

FREQUENCY – MHz

300

0

50

100

150

0

50

0

100

150

250

FREQUENCY – MHz

TPC 19. Single-Tone Spurious

Performance, f_OUT= 10 MHz,

TPC 20. Two-Tone IMD

Performance, f_DATA= 150 MSPS,

No Interpolation

TPC 21. Single-Tone Spurious

Performance, f_OUT= 10 MHz,

f_DATA= 150 MSPS, Interpolation = 2ꢀ

f

_DATA= 150 MSPS, No Interpolation

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–20

0

–20

–40

–60

–80

–100

250

FREQUENCY – MHz

0

50

100

150

200

300

20 25 30 35

10 15

FREQUENCY – MHz

45

5

10

FREQUENCY – MHz

20

0

5

40

0

15

25

TPC 22. Two-Tone IMD Performance,

f_DATA= 90 MSPS, Interpolation = 4ϫ

TPC 23. Single-Tone Spurious

Performance, f_OUT= 10 MHz,

f_DATA= 80 MSPS, Interpolation = 4ϫ

TPC 24. Two-Tone IMD Performance,

f_OUT= 10 MHz, f_DATA= 50 MSPS,

Interpolation = 8ϫ

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

300

FREQUENCY – MHz

60

FREQUENCY – MHz

0

100

200

400

0

20

40

80

TPC 25. Single-Tone Spurious

Performance, f_OUT= 10 MHz,

TPC 26. Eight-Tone IMD Performance,

f_DATA= 160 MSPS, Interpolation = 8ϫ

f_DATA= 50 MSPS, Interpolation = 8ϫ

–12–

REV. 0

AD9777

MODE CONTROL (VIA SPI PORT)

Table I. Mode Control via SPI Port

(Default Values Are Highlighted)

Address Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

01h

02h

SDIO

LSB, MSB First

0 = MSB

1 = LSB

Software Reset on Sleep Mode

Power-Down Mode

1R/2R Mode

PLL_LOCK

Indicator

Bidirectional

0 = Input

1 = I/O

Logic “1”

Logic “1” shuts down Logic “1” shuts down

DAC output current set

by one or two external

resistors.

the DAC output

currents.

all digital and analog

functions.

0 = 2R, 1 = 1R

Filter

Interpolation

Rate

Filter

Interpolation

Rate

Modulation

Mode

(None, f_S/2,

f_S/4, f_S/8)

Modulation Mode

(None, f_S/2, f_S/4, f_S/8) on Interpolation

Filters, Logic “1”

0 = No Zero Stuffing

1 = Real Mix Mode

0 = Complex

Mix Mode

0 = e^–jꢃ

DATACLK/

PLL_LOCK

Select

0 = PLLLOCK

1 = DATACLK

1 = e^+j␻

(1×, 2×, 4×, 8×)

enables zero stuffing.

0 = Signed Input 0 = Two Port Mode

Data

1 = Unsigned

DATACLK Driver DATACLK Invert

ONEPORTCLK Invert

0 = No Invert

1 = Invert

IQSEL Invert

0 = No Invert

1 = Invert

Q First

0 = I First

1 = Q First

1 = One Port Mode

Strength

0 = No Invert

1 = Invert

03h

04h

PLL Divide

(Prescaler) Ratio

PLL Divide

(Prescaler) Ratio

0 = PLL OFF

1 = PLL ON

0 = Automatic

Charge Pump Control

1 = Programmable

PLL Charge Pump

Control

PLL Charge Pump

Control

PLL Charge Pump

Control

05h

06h

07h

08h

IDAC Fine Gain

Adjustment

IDAC Fine Gain

Adjustment

IDAC Fine Gain

Adjustment

IDAC Fine Gain

Adjustment

IDAC Fine Gain

Adjustment

IDAC Fine Gain

Adjustment

IDAC Fine Gain

Adjustment

IDAC Fine Gain

Adjustment

IDAC Coarse Gain

Adjustment

IDAC Coarse Gain

Adjustment

IDAC Coarse Gain

Adjustment

IDAC Coarse Gain

Adjustment

IDAC Offset

Adjustment Bit 9

IDAC Offset

Adjustment Bit 8

IDAC Offset

Adjustment Bit 7

IDAC Offset

Adjustment Bit 6

IDAC Offset

Adjustment Bit 5

IDAC Offset

Adjustment Bit 4

IDAC Offset

Adjustment Bit 3

IDAC Offset

Adjustment Bit 2

IDAC I_OFFSET

Direction

IDAC Offset

Adjustment Bit 1

IDAC Offset

Adjustment Bit 0

0 = I_OFFSET

on I_OUTA

1 = I_OFFSETon

I_OUTB

09h

0Ah

0Bh

0Ch

QDAC Fine Gain

Adjustment

QDAC Fine Gain

Adjustment

QDAC Fine Gain

Adjustment

QDAC Fine Gain

Adjustment

QDAC Fine Gain

Adjustment

QDAC Fine Gain

Adjustment

QDAC Fine Gain

Adjustment

QDAC Fine Gain

Adjustment

QDAC Coarse

Gain Adjustment

QDAC Coarse

Gain Adjustment

QDAC Coarse

Gain Adjustment

QDAC Coarse

Gain Adjustment

QDAC Offset

Adjustment Bit 9

QDAC Offset

Adjustment Bit 8

QDAC Offset

Adjustment Bit 7

QDAC Offset

Adjustment Bit 6

QDAC Offset

Adjustment Bit 5

QDAC Offset

Adjustment Bit 4

QDAC Offset

Adjustment Bit 3

QDAC Offset

Adjustment Bit 2

QDAC I_OFFSET

Direction

QDAC Offset

Adjustment Bit 1

QDAC Offset

Adjustment Bit 0

0 = I_OFFSET

on I_OUTA

1 = I_OFFSET

on I_OUTB

0Dh

Version Register

REV. 0

–13–

AD9777

REGISTER DESCRIPTION

Address 00h

Bit 2

Default (“1”) enables the real mix mode. The I and

Q data channels are individually modulated by f_S/2,

f_S/4, or f_S/8 after the interpolation filters. However,

no complex modulation is done. In the complex mix

mode (Logic “0”), the digital modulators on the I and

Q data channels are coupled to create a digital com-

plex modulator. When the AD9777 is applied in

conjunction with an external quadrature modulator,

rejection can be achieved of either the higher or lower

frequency image around the second IF frequency (i.e.,

the second IF frequency is the LO of the analog

quadrature modulator external to the AD9777)

according to the bit value of Register 01h, Bit 1.

Bit 7

Logic “0” (default) causes the SDIO pin to act as

an input during the data transfer (Phase 2) of the

communications cycle. When set to “1,” SDIO

can act as an input or output, depending on Bit 7 of

the instruction byte.

Bit 6

Bit 5

Logic “0” (default). Determines the direction

(LSB/MSB first) of the communications and data

transfer communications cycles. Refer to the section

MSB/LSB Transfers for a detailed description.

Writing a “1” to this bit resets the registers to their

default values and restarts the chip. The RESET bit

always reads back “0.” Register Address 00h bits

are not cleared by this software reset. However, a

high level at the RESET pin forces all registers,

including those in Address 00h, to their default state.

Bit 1

Bit 0

Logic “0” (default) causes the complex modulation to

be of the form e^–j␻t, resulting in the rejection of the

higher frequency image when the AD9777 is used

with an external quadrature modulator. A Logic “1”

causes the modulation to be of the form e^+j␻t, which

causes rejection of the lower frequency image.

Bit 4

Bit 3

Bit 2

Sleep mode. A Logic “1” to this bit shuts down the

DAC output currents.

In two port mode, a Logic “0” (default) causes Pin 8

to act as a lock indicator for the internal PLL. A

Logic “1” in this register causes Pin 8 to act as a

DATACLK, either generating or acting as an input

clock (see Register 02h, Bit 3) at the input data rate

of the AD9777.

Power-Down. Logic “1” shuts down all analog

and digital functions except for the SPI port.

1R/2R Mode. The default (“0”) places the AD9777

in two resistor mode. In this mode, the I_REFcurrents

for the I and Q DAC references are set separately

by the R_SETresistors on FSADJ1 and FSADJ2 (Pins

60 and 59). In the 2R mode, assuming the coarse

gain setting is full scale and the fine gain setting

is “0,” I_FULLSCALE1= 32 × V_REF/FSADJ1 and

I_FULLSCALE2= 32 × V_REF/FSADJ2. With this bit set

to “1,” the reference currents for both I and Q

DACs are controlled by a single resistor on Pin 60.

I_FULLSCALEin one resistor mode for both the I and

Q DACs is half of what it would be in the 2R mode,

assuming all other conditions (R_SET, register settings)

remain unchanged. The full-scale current of each DAC

can still be set to 20 mA by choosing a resistor of half

the value of the R_SETvalue used in the 2R mode.

Address 02h

Bit 7

Logic “0” (default) causes data to be accepted on

the inputs as two’s complement binary. Logic “1”

causes data to be accepted as straight binary.

Bit 6

Logic “0” (default) places the AD9777 in two port

mode. I and Q data enters the AD9777 via Ports 1

and 2, respectively. A Logic “1” places the AD9777

in one port mode in which interleaved I and Q

data is applied to Port 1. See the Pin Function

Descriptions for DATACLK/PLL_LOCK, IQSEL,

and ONEPORTCLK for detailed information on

how to use these modes.

Bit 5

DATACLK Driver Strength. With the internal PLL

disabled and this bit set to Logic “0,” it is recom-

mended that DATACLK be buffered. When this bit

is set to Logic “1,” DATACLK acts as a stronger

driver capable of driving small capacitive loads.

Bit 1

PLL_LOCK Indicator. When the PLL is enabled,

reading this bit will give the status of the PLL. A

Logic “1” indicates the PLL is locked. A Logic “0”

indicates an unlocked state.

Address 01h

Bits 7, 6

Bit 4

Bit 2

Bit 1

Default Logic “0.” A value of “1” inverts

DATACLK at Pin 8.

Filter interpolation rate according to the follow-

ing table:

Default Logic “0.” A value of “1” inverts

ONEPORTCLK at Pin 32.

00

1×

2×

4×

8×

01

10

11

The default of Logic “0” causes IQSEL = 1 to

direct input data to the I channel, while IQSEL = 0

directs input data to the Q channel. A Logic “1” in

this register inverts the sense of IQSEL.

Bits 5, 4

Bit 3

Modulation mode according to the following table:

00

01

10

11

none

f_S/2

f_S/4

f_S/8

Bit 0

The default of Logic “0” defines IQ pairing as IQ,

IQ... while programming a Logic “1” causes the

pair ordering to be QI, QI...

Logic “1” enables zero stuffing mode for interpola-

tion filters.

–14–

REV. 0

AD9777

Address 03h

Address 05h, 09h

Bits 7–0

Bits 1, 0

Setting this divide ratio to a higher number allows

the VCO in the PLL to run at a high rate (for best

performance) while the DAC input and output

clocks run substantially slower. The divider ratio is

set according to the following table:

These bits represent an 8-bit binary number (Bit 7

MSB) that defines the fine gain adjustment of the I

(05h) and Q (09h) DAC according to the equation

given below.

Address 06h, 0Ah

Bits 3–0 These bits represent a 4-bit binary number (Bit 3

00

Ϭ1

Ϭ2

Ϭ4

Ϭ8

01

10

11

MSB) that defines the coarse gain adjustment of the

I (06h) and Q (0Ah) DACs according to the equa-

tion below.

Address 04h

Address 07h, 0Bh

Bit 7

Logic “0” (default) disables the internal PLL.

Logic “1” enables the PLL.

Bits 7–0

Address 08h, 0Ch

Bit 6

Logic “0” (default) sets the charge pump control to

automatic. In this mode, the charge pump bias

current is controlled by the divider ratio defined in

Address 03h, Bits 1 and 0. Logic “1” allows the

user to manually define the charge pump bias cur-

rent using Address 04h, Bits 2, 1, and 0. Adjusting

the charge pump bias current allows the user to

optimize the noise/settling performance of the PLL.

Bits 1, 0

The 10 bits from these two address pairs (07h, 08h

and 0Bh, 0Ch) represent a 10-bit binary number that

defines the offset adjustment of the I and Q DACs

according to the equation below

(07h, 0Bh–Bit 7 MSB/08h, 0Ch–Bit 0 LSB).

Address 08h, 0Ch

Bit 7

This bit determines the direction of the offset of the

I (08h) and Q (0Ch) DACs. A Logic “0” will apply

a positive offset current to I_OUTA, while a Logic “1”

will apply a positive offset current to I_OUTB. The

magnitude of the offset current is defined by the

bits in Addresses 07h, 0Bh, 08h, 0Ch according to

the formulas given below.

Bits 2, 1, 0 With the charge pump control set to manual, these

bits define the charge pump bias current according

to the following table:

000 50 µA

001 100 µA

010 200 µA

011 400 µA

100 800 µA



















 6 × I_REF



 3 × I_REF









COARSE +1

 FINE

256

1024 DATA

I_OUTA

=

–

×





































2¹⁶









8

16

32

24



16















 6 × I_REF



 3 × I_REF



COARSE +1

 FINE

1024 2 – DATA – 1





(1)

I_OUTB































2¹⁶













24



8

16

32

256









OFFSET 

I_OFFSET= 4 × I





^REF



1024

Equation 1 shows I_OUTAand I_OUTBas a function of fine gain, coarse gain, and offset adjustment when using the 2R mode. In the 1R

mode, the current I_REFis created by a single FSADJ resistor (Pin 60). This current is divided equally into each channel so that a

scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.

REV. 0

–15–

AD9777

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE FOR REGISTER CONTROL

The AD9777 serial port is a flexible, synchronous serial com-

munications port allowing easy interface to many industry

standard microcontrollers and microprocessors. The serial I/O is

compatible with most synchronous transfer formats, including

both the Motorola SPI and Intel SSR protocols. The interface

allows read/write access to all registers that configure the AD9777.

Single- or multiple-byte transfers are supported as well as MSB

first or LSB first transfer formats. The AD9777’s serial interface

port can be configured as a single pin I/O (SDIO) or two unidi-

rectional pins for in/out (SDIO/SDO).

The AD9777 dual interpolating DAC consists of two data

channels that can be operated completely independently or

coupled to form a complex modulator in an image reject transmit

architecture. Each channel includes three FIR filters, making

the AD9777 capable of 2×, 4×, or 8× interpolation. High

speed input and output data rates can be achieved within the

following limitations:

Interpolation

Rate (MSPS)

Input Data

Rate (MSPS)

DAC Sample

Rate (MSPS)

1×

2×

4×

8×

160

100

50

160

320

400

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9777.

Phase 1 is the instruction cycle, which is the writing of an instruc-

tion byte into the AD9777 coincident with the first eight SCLK

rising edges. The instruction byte provides the AD9777 serial

port controller with information regarding the data transfer

cycle, which is Phase 2 of the communication cycle. The Phase 1

instruction byte defines whether the upcoming data transfer is

read or write, the number of bytes in the data transfer, and the

starting register address for the first byte of the data transfer.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9777.

Both data channels contain a digital modulator capable of mix-

ing the data stream with an LO of f_DAC/2, f_DAC/4, or f_DAC/8,

where f_DACis the output data rate of the DAC. A zero stuffing

feature is also included and can be used to improve pass-band

flatness for signals being attenuated by the SIN(x)/x characteris-

tic of the DAC output. The speed of the AD9777, combined

with its digital modulation capability, enables direct IF conver-

sion architectures at 70 MHz and higher.

A logic high on the CSB pin, followed by a logic low, will reset

the SPI port timing to the initial state of the instruction cycle.

This is true regardless of the present state of the internal regis-

ters or the other signal levels present at the inputs to the SPI

port. If the SPI port is in the midst of an instruction cycle or a

data transfer cycle, none of the present data will be written.

The digital modulators on the AD9777 can be coupled to form

a complex modulator. By using this feature with an external analog

quadrature modulator, such as the Analog Devices AD8345, an

image rejection architecture can be enabled. To optimize the

image rejection capability, as well as LO feedthrough in this

architecture, the AD9777 offers programmable (via the SPI

port) gain and offset adjust for each DAC.

The remaining SCLK edges are for Phase 2 of the communica-

tion cycle. Phase 2 is the actual data transfer between the AD9777

and the system controller. Phase 2 of the communication cycle

is a transfer of 1, 2, 3, to 4 data bytes as determined by the

instruction byte. Normally, using one multibyte transfer is the

preferred method. However, single byte data transfers are useful

to reduce CPU overhead when register access requires one byte

only. Registers change immediately upon writing to the last bit of

each transfer byte.

Also included on the AD9777 are a phase-locked loop (PLL)

clock multiplier and a 1.20 V band gap voltage reference. With

the PLL enabled, a clock applied to the CLK+/CLK– inputs

is frequency multiplied internally and generates all necessary

internal synchronization clocks. Each 16-bit DAC provides

two complementary current outputs whose full-scale currents

can be determined either from a single external resistor, or

independently from two separate resistors (see 1R/2R mode).

The AD9777 features a low jitter, differential clock input that

provides excellent noise rejection while accepting a sine or square

wave input. Separate voltage supply inputs are provided for

each functional block to ensure optimum noise and distortion

performance.

INSTRUCTION BYTE

The instruction byte contains the information shown below.

N1

N0

Description

0

1

0

1

0

1

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

SLEEP and power-down modes can be used to turn off the

DAC output current (SLEEP) or the entire digital and analog

sections (power-down) of the chip. An SPI-compliant serial port

is used to program the many features of the AD9777. Note that

in power-down mode, the SPI port is the only section of the

chip still active.

R/W

Bit 7 of the instruction byte determines whether a read or a write

data transfer will occur after the instruction byte write. Logic high

indicates read operation. Logic zero indicates a write operation.

SDO (PIN 53)

SDIO (PIN 54)

AD9777 SPI PORT

INTERFACE

SCLK (PIN 55)

CSB (PIN 56)

Figure 2. SPI Port Interface

–16–

REV. 0

AD9777

N1, N0

SDIO (Pin 54)—Serial Data I/O

Bits 6 and 5 of the instruction byte determine the number of

bytes to be transferred during the data transfer cycle. The bit

decodes are shown in the following table:

Data is always written into the AD9777 on this pin. However, this

pin can be used as a bidirectional data line. The configuration of

this pin is controlled by Bit 7 of Register Address 00h. The default

is Logic “0,” which configures the SDIO Pin as unidirectional.

MSB

LSB

SDO (Pin 53)—Serial Data Out

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. In the case where the AD9777

operates in a single bidirectional I/O mode, this pin does not

output data and is set to a high impedance state.

I7

R/W

I6

N1

I5

N0

I4

A4

I3

A3

I2

A2

I1

A1

I0

A0

A4, A3, A2, A1, A0

Bits 4, 3, 2, 1, and 0 of the instruction byte determine which

register is accessed during the data transfer portion of the com-

munications cycle. For multibyte transfers, this address is the

starting byte address. The remaining register addresses are

generated by the AD9777.

MSB/LSB TRANSFERS

The AD9777 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by Register Address 00h, Bit 6. The

default is MSB first. When this bit is set active high, the AD9777

serial port is in LSB first format. That is, if the AD9777 is in

LSB first mode, the instruction byte must be written from least

significant bit to most significant bit. Multibyte data transfers in

MSB format can be completed by writing an instruction byte

that includes the register address of the most significant byte. In

MSB first mode, the serial port internal byte address generator

decrements for each byte required of the multibyte communica-

tion cycle. Multibyte data transfers in LSB first format can be

completed by writing an instruction byte that includes the regis-

ter address of the least significant byte. In LSB first mode, the

serial port internal byte address generator increments for each

byte required of the multibyte communication cycle.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SCLK (Pin 55)—Serial Clock

The Serial Clock Pin is used to synchronize data to and from the

AD9777 and to run the internal state machines. SCLK maximum

frequency is 15 MHz. All data input to the AD9777 is registered

on the rising edge of SCLK. All data is driven out of the AD9777

on the falling edge of SCLK.

CSB (Pin 56)—Chip Select

Active low input starts and gates a communication cycle. It

allows more than one device to be used on the same serial com-

munications lines. The SDO and SDIO Pins will go to a high

impedance state when this input is high. Chip select should stay

low during the entire communication cycle.

The AD9777 serial port controller address will increment from

1Fh to 00h for multibyte I/O operations if the MSB first mode is

active. The serial port controller address will decrement from 00h

to 1Fh for multibyte I/O operations if the LSB first mode is active.

DATA TRANSFER CYCLE

INSTRUCTION CYCLE

CS

SCLK

SDIO

SDO

R/W

I6

I5

(N)

I4

I3

I2

I1

I0

D7

D6

D2

D1

D0

(N)

N

0

D2

D1

0

N

Figure 3a. Serial Register Interface Timing MSB First

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

SCLK

SDIO

I0

I1

I2

I3

I4

I5

I6

R/W

D0

D1

D2

D6

D7

(N)

0

N

D2

SDO

0

N

Figure 3b. Serial Register Interface Timing LSB First

–17–

REV. 0

AD9777

t_DS

t_SCLK

CS

SCLK

SDIO

t_PWH

t_PWL

t_DS

t_DH

INSTRUCTION BIT 7

INSTRUCTION BIT 6

Figure 4. Timing Diagram for Register Write to AD9777

CS

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N–1

Figure 5. Timing Diagram for Register Read from AD9777

NOTES ON SERIAL PORT OPERATION

DAC OPERATION

The AD9777 serial port configuration bits reside in Bits 6 and 7

of Register Address 00h. It is important to note that the configura-

tion changes immediately upon writing to the last bit of the register.

For multibyte transfers, writing to this register may occur during

the middle of the communication cycle. Care must be taken to

compensate for this new configuration for the remaining bytes

of the current communication cycle.

The dual 16-bit DAC output of the AD9777, along with the

reference circuitry, gain, and offset registers, is shown in Figure 6.

Referring to the transfer functions in Equation 1, a reference

current is set by the internal 1.2 V reference, the external R_SET

resistor, and the values in the coarse gain register. The fine gain

DAC subtracts a small amount from this and the result is input

to IDAC and QDAC, where it is scaled by an amount equal to

1024/24. Figures 7a and 7b show the scaling effect of the coarse

and fine adjust DACs. IDAC and QDAC are PMOS current

source arrays, segmented in a 5-4-7 configuration. The five

most significant bits control an array of 31 current sources. The

next four bits consist of 15 current sources whose values are all

equal to 1/16 of an MSB current source. The seven LSBs are

binary weighted fractions of the middle bit’s current sources. All

current sources are switched to either I_OUTAor I_OUTB, depend-

ing on the input code.

The same considerations apply to setting the reset bit in Register

Address 00h. All other registers are set to their default values, but

the software reset doesn’t affect the bits in Register Address 00h.

It is recommended to use only single byte transfers when chang-

ing serial port configurations or initiating a software reset.

A write to Bits 1, 2, and 3 of Address 00h with the same logic

levels as for Bits 7, 6, and 5 (bit pattern: XY1001YX binary) allows

the user to reprogram a lost serial port configuration and to reset

the registers to their default values. A second write to Address

00h with reset bit low and serial port configuration as specified

above (XY) reprograms the OSC IN multiplier setting. A changed

The fine adjustment of the gain of each channel allows for

improved balance of QAM modulated signals, resulting in

improved modulation accuracy and image rejection. In the

Applications section of this data sheet, performance data is

included that shows to what degree image rejection can be

improved when the AD9777 is used with an AD8345 quadra-

ture modulator from ADI.

f

_SYSCLKfrequency is stable after a maximum of 200 f_MCLKcycles

(equals wake-up time).

–18–

REV. 0

AD9777

0

The offset control defines a small current that can be added

to I_OUTAor I_OUTB(not both) on the IDAC and QDAC. The

selection of which I_OUTthis offset current is directed toward is

programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch,

Bit 7 (QDAC). Figure 9 shows the scale of the offset current

that can be added to one of the complementary outputs on the

IDAC and QDAC. Offset control can be used for suppression of

LO leakage resulting from modulation of dc signal components.

If the AD9777 is dc-coupled to an external modulator, this

feature can be used to cancel the output offset on the AD9777

as well as the input offset on the modulator. Figure 9 shows a

typical example of the effect that the offset control has on LO

suppression.

–0.5

–1.0

1R MODE

–1.5

–2.0

–2.5

–3.0

2R MODE

0

5

10

15

20

OFFSET

FINE GAIN REGISTER CODE – Assuming

OFFSET

DAC

CONTROL

FINE

GAIN

DAC

RSET1, 2 = 1.9kꢁ

REGISTERS

GAIN

CONTROL

Figure 7b. Fine Gain Effect on I_FULLSCALE

REGISTERS

In Figure 9, the negative scale represents an offset added to

I_OUTB, while the positive scale represents an offset added to

I_OUTAof the respective DAC. Offset Register 1 corresponds

to IDAC, while Offset Register 2 corresponds to QDAC. Figure 9

represents the AD9777 synthesizing a complex signal that is

then dc-coupled to an AD8345 quadrature modulator with an

LO of 800 MHz. The dc-coupling allows the input offset of the

AD8345 to be calibrated out as well. The LO suppression at the

AD8345 output was optimized first by adjusting Offset Register 1,

in the AD9777. When an optimal point was found (roughly

Code 54), this code was held in Offset Register 1, and

Offset Register 2 was adjusted. The resulting LO suppression is

70 dBFS. These are typical numbers, and the specific code for

optimization will vary from part to part.

FINE

GAIN

DAC

I

IDAC

OUTA1

1.2VREF

REFIO

0.1ꢄF

OUTB1

COARSE COARSE

I

QDAC

OUTA2

GAIN

DAC

GAIN

DAC

OUTB2

FSADJ1

RSET1

FSADJ2

OFFSET

CONTROL

REGISTERS

OFFSET

DAC

GAIN

RSET2

CONTROL

REGISTERS

Figure 6. DAC Outputs, Reference Current Scaling, and

Gain/Offset Adjust

25

5

20

4

2R MODE

15

3

2R MODE

10

2

1R MODE

5

1R MODE

1

0

5

10

15

20

0

COARSE GAIN REGISTER CODE – Assuming

0

200

400

600

800

1000

RSET1, 2 = 1.9kꢁ

COARSE GAIN REGISTER CODE – Assuming

RSET1, 2 = 1.9kꢁ

Figure 7a. Coarse Gain Effect on I_FULLSCALE

Figure 8. DAC Output Offset Current

REV. 0

–19–

AD9777

0

–10

–20

–30

–40

–50

–60

–70

–80

AD9777

1k

ꢁ

0.1ꢄF

OFFSET REGISTER 1 ADJUSTED

CLK+

1k

0.1ꢄF

ECL/PECL

CLKVDD

CLK–

0.1ꢄ

F

CLKGND

OFFSET REGISTER 2

ADJUSTED, WITH OFFSET

REGISTER 1 SET

Figure 11. Differential Clock Driving Clock Inputs

A transformer, such as the T1-1T from Mini-Circuits, can also be

used to convert a single-ended clock to differential. This method is

used on the AD9777 evaluation board so that an external sine

wave with no dc offset can be used as a differential clock.

TO OPTIMIZED VALUE

–1024 –768

–512

–256

0

256

512

768

1024

DAC1, DAC2 – Offset Register Codes

Figure 9. Offset Adjust Control, Effect on LO Suppression

PECL/ECL drivers require varying termination networks, the

details of which are left out of Figures 10 and 11 but can be found

in application notes such as AND8020/D from On Semiconductor.

These networks depend on the assumed transmission line imped-

ance and power supply voltage of the clock driver. Optimum

performance of the AD9777 is achieved when the driver is placed

very close to the AD9777 clock inputs, thereby negating any

transmission line effects such as reflections due to mismatch.

1R/2R MODE

In the 2R mode, the reference current for each channel is set

independently by the FSADJ resistor on that channel. The

AD9777 can be programmed to derive its reference current from a

single resistor on Pin 60 by placing the part in the 1R mode. The

transfer functions in Equation 1 are valid for the 2R mode. In the

1R mode, the current developed in the single FSADJ resistor is

split equally between the two channels. The result is that in the

1R mode, a scale factor of one-half must be applied to the formulas

in Equation 1. The full-scale DAC current in the 1R mode can still

be set to as high as 20 mA by using the internal 1.2 V reference and

a 950 Ω resistor, instead of the 1.9 kΩ resistor typically used

in the 2R mode.

The quality of the clock and data input signals is important in

achieving optimum performance. The external clock driver cir-

cuitry should provide the AD9777 with a low jitter clock input

that meets the min/max logic levels while providing fast edges.

Although fast clock edges help minimize any jitter that will manifest

itself as phase noise on a reconstructed waveform, the high gain

bandwidth product of the AD9777’s differential comparator can

tolerate sine wave inputs as low as 0.5 V p-p, with minimal

degradation of the output noise floor.

CLOCK INPUT CONFIGURATIONS

The clock inputs to the AD9777 can be driven differentially or

single-ended. The internal clock circuitry has supply and ground

(CLKVDD, CLKGND) separate from the other supplies on the

chip to minimize jitter from internal noise sources.

PROGRAMMABLE PLL

CLKIN can function either as an input data rate clock (PLL

enabled) or as a DAC data rate clock (PLL disabled) according

to the state of Address 02h, Bit 7 in the SPI port register. The

internal operation of the AD9777 clock circuitry in these two

modes is illustrated in Figures 12 and 13.

Figure 10 shows the AD9777 driven from a single-ended clock

source. The CLK+/CLK– Pins form a differential input (CLKIN),

so that the statically terminated input must be dc-biased to the

midswing voltage level of the clock driven input.

The PLL clock multiplier and distribution circuitry produce the

necessary internal synchronized 1×, 2×, 4×, and 8× clocks for the

rising edge triggered latches, interpolation filters, modulators, and

DACs. This circuitry consists of a phase detector, charge pump,

voltage controlled oscillator (VCO), prescaler, clock distribution,

and SPI port control. The charge pump and VCO are powered

from PLLVDD while the differential clock input buffer, phase

detector, prescaler, and clock distribution are powered from

CLKVDD. PLL lock status is indicated by the logic signal at the

PLL_LOCK Pin, as well as by the status of Bit 1, Register 00h.

To ensure optimum phase noise performance from the PLL clock

multiplier, and distribution, PLLVDD and CLKVDD should

originate from the same clean analog supply. The speed of the

VCO with the PLL enabled also has an effect on phase noise.

Optimal phase noise with respect to VCO speed is achieved by

running the VCO in the range of 450 MHz to 550 MHz. The

VCO speed is a function of the input data rate, the interpolation

rate, and the VCO prescaler, according to the following function:

AD9777

R

SERIES

CLK+

CLKVDD

CLK–

V

THRESHOLD

0.1ꢄF

CLKGND

Figure 10. Single-Ended Clock Driving Clock

Inputs

A configuration for differentially driving the clock inputs is

given in Figure 11. DC-blocking capacitors can be used to

couple a clock driver output whose voltage swings exceed

CLKVDD or CLKGND. If the driver voltage swings are within

the supply range of the AD9777, the dc-blocking capacitors

and bias resistors are not necessary.

VCO Speed (MHz) =

Input Data Rate (MHz) × InterpolationRate × Prescaler

–20–

REV. 0

AD9777

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

CLK–

CLK+

PLLVDD

PLL_LOCK

1 = LOCK

AD9777

0 = NO LOCK

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

PHASE

DETECTOR

CHARGE

PUMP

LPF

2

4

8

1

CLOCK

DISTRIBUTION

CIRCUITRY

PRESCALER

VCO

INPUT

DATA

LATCHES

0

1

2

3

4

5

PLL DIVIDER

(PRESCALER)

CONTROL

INTERNAL SPI

CONTROL

REGISTERS

FREQUENCY OFFSET – MHz

INTERPOLATION

RATE

Figure 14. Phase Noise Performance

PLL

CONTROL

(PLL ON)

MODULATION

RATE

CONTROL

It is important to note that the resistor/capacitor needed for the

PLL loop filter is internal on the AD9777. This will suffice unless

the input data rate is below 10 MHz, in which case an external

series RC is required between the LPF and PLLVDD Pins.

SPI PORT

Figure 12. PLL and Clock Circuitry with PLL Enabled

POWER DISSIPATION

CLK–

CLK+

The AD9777 has three voltage supplies: AVDD, DVDD, and

CLKVDD. Figures 15, 16, and 17 show the current required

from each of these supplies when each is set to the 3.3 V nomi-

nal specified for the AD9777. Power dissipation (P_D) can easily

be extracted by multiplying the given curves by 3.3. As Figure 15

shows, I_DVDDis very dependent on the input data rate, the

interpolation rate, and the activation of the internal digital

modulator. I_DVDD, however, is relatively insensitive to the

modulation rate by itself. In Figure 16, I_AVDDshows the same

type of sensitivity to data, interpolation rate, and the modulator

function but to a much lesser degree (<10%). In Figure 17,

I_CLKVDDvaries over a wide range yet is responsible for only a small

percentage of the overall AD9777 supply current requirements.

PLL_LOCK

1 = LOCK

AD9777

0 = NO LOCK

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

PHASE

CHARGE

PUMP

DETECTOR

2

4

8

1

CLOCK

DISTRIBUTION

CIRCUITRY

PRESCALER

VCO

INPUT

DATA

LATCHES

PLL DIVIDER

(PRESCALER)

CONTROL

INTERNAL SPI

CONTROL

REGISTERS

400

INTERPOLATION

RATE

PLL

CONTROL

(PLL ON)

, (MOD. ON)

8

ꢀ

MODULATION

RATE

CONTROL

2

, (MOD. ON)

ꢀ

350

300

250

200

150

100

4

, (MOD. ON)

ꢀ

SPI PORT

Figure 13. PLL and Clock Circuitry with PLL Disabled

8ꢀ

4

ꢀ

2

ꢀ

In addition, if the zero stuffing option is enabled, the VCO will

double its speed again. Phase noise may be slightly higher with

the PLL enabled. Figure 14 illustrates typical phase noise per-

formance of the AD9777 with 2× interpolation and various

input data rates. The signal synthesized for the phase noise

measurement was a single carrier at a frequency of f_DATA/4.

The repetitive nature of this signal eliminated quantization noise

and distortion spurs as a factor in the measurement. Although

the curves blend together in Figure 14, the different conditions

are called out here for clarity.

1

ꢀ

50

0

50

100

– MHz

150

200

f

DATA

Figure 15. I_DVDDvs. f_DATAvs. Interpolation Rate,

PLL Disabled

f_DATA

PLL

Prescaler Ratio

125 MSPS

100 MSPS

75 MSPS

50 MSPS

Disabled

Enabled

div1

div2

div4

REV. 0

–21–

AD9777

76.0

ONE/TWO PORT INPUT MODES

2

, (MOD. ON)

ꢀ

8

, (MOD. ON)

ꢀ

The digital data input ports can be configured as two independent

ports or as a single (one port mode) port. In two port mode, the

AD9777 can be programmed to generate an externally available

data rate clock (DATACLK) for the purpose of data synchroniza-

tion. Data at the two input ports can be latched into the AD9777

on every rising clock edge of DATACLK. In one port mode,

P2B14 and P2B15 from input data Port 2 are redefined as IQSEL

and ONEPORTCLK, respectively. The input data in one port

mode is steered to one of the two internal data channels based on

the logic level of IQSEL. A clock signal, ONEPORTCLK, is

generated by the AD9777 in this mode for the purpose of external

data synchronization. ONEPORTCLK runs at the input inter-

leaved data rate, which is 2× the data rate at the internal input

to either channel.

75.5

75.0

4

, (MOD. ON)

ꢀ

74.5

74.0

4

ꢀ

8

ꢀ

2

ꢀ

73.5

73.0

72.5

1

ꢀ

72.0

0

50

100

– MHz

150

200

f

DATA

Test configurations showing the various clocks that are required and

produced by the AD9777 in the PLL and one/two port modes are

given in Figures 55 through 58. Jumper positions needed to oper-

ate the AD9777 evaluation board in these modes are given as well.

Figure 16. I_AVDDvs. f_DATAvs. Interpolation Rate,

PLL Disabled

35

PLL ENABLED, TWO PORT MODE

(Control Register 02h, Bits 6–0 and 04h, Bits 7–1)

8

ꢀ

30

25

20

15

10

2

4

ꢀ

With the phase-locked loop (PLL) enabled and the AD9777 in

two port mode, the speed of CLKIN is inherently that of the input

data rate. In two port mode, Pin 8 (DATACLK/PLL_ LOCK)

can be programmed (Control Register 01h, Bit 0) to function as

either a lock indicator for the internal PLL or as a clock running

at the input data rate. When Pin 8 is used as a clock output

(DATACLK), its frequency is equal to that of CLKIN. Data at

the input ports is latched into the AD9777 on the rising edge of the

CLKIN. Figure 18 shows the delay, t_OD, inherent between the

rising edge of CLKIN and the rising edge of DATACLK, as well

as the setup and hold requirements for the data at Ports 1 and 2.

Note that the setup and hold times given in Figure 18 are the

input data transitions with respect to CLKIN. t_ODcan vary with

CLKIN speed, PLL divider setting, and interpolation rate. It is

therefore highly recommended that the input data be synchro-

nized to CLKIN rather than DATACLK when the PLL is enabled.

Note that in two port mode (PLL enabled or disabled), the data

rate at the interpolation filter inputs is the same as the input data

rate at Ports 1 and 2.

1

ꢀ

5

0

50

100

– MHz

150

200

f

DATA

Figure 17. I_CLKVDDvs. f_DATAvs. Interpolation Rate,

PLL Disabled

SLEEP/POWER-DOWN MODES

(Control Register 00h, Bits 3 and 4)

The AD9777 provides two methods for programmable reduction

in power savings. The sleep mode, when activated, turns off the

DAC output currents but the rest of the chip remains functioning.

When coming out of sleep mode, the AD9777 will immediately

return to full operation. Power-down mode, on the other hand,

turns off all analog and digital circuitry in the AD9777 except

for the SPI port. When returning from power-down mode, enough

clock cycles must be allowed to flush the digital filters of random

data acquired during the power-down cycle. Note that optimal

performance with the PLL enabled is achieved with the UCO in

the PLL control loop running at 450 MHz – 550 MHz.

The DAC output sample rate in two port mode is equal to the

clock input rate multiplied by the interpolation rate. If zero

stuffing is used, another factor of two must be included to cal-

culate the DAC sample rate.

DATACLK Inversion

(Control Register 02h, Bit 4)

By programming this bit, the DATACLK signal shown in

Figure 18 can be inverted. With inversion enabled, t_ODwill

refer to the time between the rising edge of CLKIN and the

falling edge of DATACLK. No other effect on timing will occur.

–22–

REV. 0

AD9777

t_OD

the data for the I or Q channel is determined by the state of the logic

level at Pin 31 (IQSEL when the AD9777 is in one port mode)

on the rising edge of ONEPORTCLK. IQSEL = 1 under these

conditions will latch the data into the I channel on the clock rising

edge, while IQSEL = 0 will latch the data into the Q channel.

It is possible to invert the I and Q selection by setting Control

Register 02h, Bit 1 to the invert state (Logic “1”). Figure 20

illustrates the timing requirements for the data inputs as well as

the IQSEL input. Note that the 1× interpolation rate is not

available in one port mode.

CLKIN

DATACLK

The DAC output sample rate in one port mode is equal to

CLKIN multiplied by the interpolation rate. If zero stuffing is

used, another factor of 2 must be included to calculate the

DAC sample rate.

DATA AT PORTS

1 AND 2

t_S= 0.0ns

ONEPORTCLK INVERSION

(Control Register 02h, Bit 2)

t_H= 2.5ns

t_S

t_H

(TYP SPECS)

By programming this bit, the ONEPORTCLK signal shown in

Figure 20 can be inverted. With inversion enabled, t_ODrefers to

the delay between the rising edge of the external clock and the

falling edge of ONEPORTCLK. The setup and hold times, t_S

and t_H, will be with respect to the falling edge of ONEPORTCLK.

There will be no other effect on timing.

Figure 18. Timing Requirements in Two Port

Input Mode with PLL Enabled

DATACLK DRIVER STRENGTH

(Control Register 02h, Bit 5)

The DATACLK output driver strength is capable of driving

>10 mA into a 330 Ω load while providing a rise time of 3 ns.

Figure 19 shows DATACLK driving a 330 Ω resistive load at a

frequency of 50 MHz. By enabling the drive strength option

(Control Register 02h, Bit 5), the amplitude of DATACLK

under these conditions will be increased by approximately 200 mV.

3.0

ONEPORTCLK DRIVER STRENGTH

The drive capability of ONEPORTCLK is identical to that of

DATACLK in the two port mode. Refer to Figure 19 for per-

formance under load conditions.

t_OD

t_OD= 4.7ns

2.5

2.0

1.5

1.0

0.5

t_S= 3.0ns

CLKIN

t_H= –0.5ns

t_IQS= 3.5ns

t_IQH= –1.5ns

ONEPORTCLK

0

DELTA APPROX. 2.8ns

I AND Q INTERLEAVED

INPUT DATA AT PORT 1

–0.5

0

10

20

30

40

50

TIME – ns

Figure 19. DATACLK Driver Capability into 330 ⍀

at 50 MHz

t_St_H

PLL ENABLED, ONE PORT MODE

IQSEL

(Control Register 02h, Bits 6–1 and 04h, Bits 7–1)

In one port mode, the I and Q channels receive their data from an

interleaved stream at digital input Port 1. The function of Pin 32

is defined as an output (ONEPORTCLK) that generates a clock at

the interleaved data rate, which is 2ϫ the internal input data rate

of the I and Q channels. The frequency of CLKIN is equal to the

internal input data rate of the I and Q channels. The selection of

t_IQS

t_IQH

Figure 20. Timing Requirements in One Port

Input Mode, with the PLL Enabled

REV. 0

–23–

AD9777

t_OD

IQ PAIRING

(Control Register 02h, Bit 0)

In one port mode, the interleaved data is latched into the AD9777

internal I and Q channels in pairs. The order of how the pairs

are latched internally is defined by this control register. The

following is an example of the effect this has on incoming inter-

leaved data.

CLKIN

Given the following interleaved data stream, where the data

indicates the value with respect to full scale:

DATACLK

I

Q

I

1

Q

1

I

Q

I

0

Q

0

I

Q

0.5 0.5

With the control register set to “0” (I first), the data will appear

at the internal channel inputs in the following order in time:

DATA AT PORTS

1 AND 2

I channel

Q channel

0.5

1

0.5

0

0.5

t_S= 5.0ns

t_H= –3.2ns

(TYP SPECS)

t_S

t_H

With the control register set to “1” (Q first), the data will appear at

the internal channel inputs in the following order in time:

Figure 21. Timing Requirements in Two Port

Input Mode, with PLL Disabled

I channel

Q channel

0.5

y

1

0.5

1

0

0.5

0

x

0.5

PLL DISABLED, ONE PORT MODE

The values x and y represent the next I value and the previous

Q value in the series.

In one port mode, data is received into the AD9777 as an

interleaved stream on Port 1. A clock signal (ONEPORTCLK),

running at the interleaved data rate, which is 2× the input data

rate of the internal I and Q channels is available for data syn-

chronization at Pin 32.

PLL DISABLED, TWO PORT MODE

With the PLL disabled, a clock at the DAC output rate must be

applied to CLKIN. Internal clock dividers in the AD9777 syn-

thesize the DATACLK signal at Pin 8, which runs at the input

data rate and can be used to synchronize the input data. Data is

latched into input Ports 1 and 2 of the AD9777 on the rising

edge of DATACLK. DATACLK speed is defined as the speed

of CLKIN divided by the interpolation rate. With zero stuffing

enabled, this division increases by a factor of 2. Figure 21

illustrates the delay between the rising edge of CLKIN and

the rising edge of DATACLK, as well as t_Sand t_Hin this mode.

With PLL disabled, a clock at the DAC output rate must be applied

to CLKIN. Internal dividers synthesize the ONEPORTCLK

signal at Pin 32. The selection of the data for the I or Q channel

is determined by the state of the logic level applied to Pin 31

(IQSEL when the AD9777 is in one port mode) on the rising

edge of ONEPORTCLK. IQSEL = 1 under these conditions

will latch the data into the I channel on the clock rising edge,

while IQSEL = 0 will latch the data into the Q channel. It is

possible to invert the I and Q selection by setting Control

Register 02h, Bit 1 to the invert state (Logic “1”). Figure 22

illustrates the timing requirements for the data inputs as well as

the IQSEL input. Note that the 1× interpolation rate is not

available in the one port mode.

The programmable modes DATACLK inversion and DATACLK

driver strength described in the previous section (PLL Enabled,

Two Port Mode) have identical functionality with the PLL disabled.

As described earlier in the PLL-Enabled Mode section, t_ODcan

vary depending on CLKIN frequency and interpolation rate.

However, with the PLL disabled, the input data latches are closely

synchronized to DATACLK so that it is recommended in this

mode that the input data be timed from DATACLK, not CLKIN.

One port mode is very useful when interfacing with devices

such as Analog Devices’ AD6622 or AD6623 transmit signal

processors, in which two digital data channels have been

interleaved (multiplexed).

–24–

REV. 0

AD9777

The programmable modes’ ONEPORTCLK inversion,

ONEPORTCLK driver strength, and IQ pairing described in

the previous section (PLL Enabled, One Port Mode) have

identical functionality with the PLL disabled.

AMPLITUDE MODULATION

Given two sine waves at the same frequency, but with a 90 phase

difference, a point of view in time can be taken such that the

waveform that leads in phase is cosinusoidal and the waveform

that lags is sinusoidal. Analysis of complex variables states that

the cosine waveform can be defined as having real positive and

negative frequency components, while the sine waveform consists

of imaginary positive and negative frequency images. This is

shown graphically in the frequency domain in Figure 23.

t_OD

CLKIN

–jꢃt

e

/2j

SINE

ONEPORTCLK

DC

–jꢃt

/2j

e

–jꢃt

e

/2

e

/2

COSINE

I AND Q INTERLEAVED

INPUT DATA AT PORT 1

DC

Figure 23. Real and Imaginary Components of

Sinusoidal and Cosinusoidal Waveforms

t_St_H

Amplitude modulating a baseband signal with a sine or a cosine

convolves the baseband signal with the modulating carrier in

the frequency domain. Amplitude scaling of the modulated

signal reduces the positive and negative frequency images by a

factor of two. This scaling will be very important in the discus-

sion of the various modulation modes. The phase relationship of

the modulated signals is dependent on whether the modulating

carrier is sinusoidal or cosinusoidal, again with respect to the

reference point of the viewer. Examples of sine and cosine

modulation are given in Figure 24.

IQSEL

t_OD= 4.7ns

t_S= 3.0ns

t_H= –1.0ns

t_IQS= 3.5ns

t_IQH= –1.5ns

(TYP SPECS)

t_IQS

t_IQH

Figure 22. Timing Requirements in One Port

Input Mode, with PLL Disabled

DIGITAL FILTER MODES

–jꢃt

Ae

/2j

The I and Q data paths of the AD9777 have their own indepen-

dent half-band FIR filters. Each data path consists of three FIR

filters, providing up to 8× interpolation for each channel. The rate

of interpolation is determined by the state of Control Register 01h,

Bits 7 and 6. Figures 1a–1c show the response of the digital

filters when the AD9777 is set to 2×, 4×, and 8× modes. The

frequency axes of these graphs have been normalized to the input

data rate of the DAC. As the graphs show, the digital filters can

provide greater than 75 dB of out-of-band rejection.

SINUSOIDAL

MODULATION

DC

–jꢃt

Ae

/2j

–jꢃt

/2

Ae

/2

Ae

COSINUSOIDAL

MODULATION

An online tool is available for quick and easy analysis of the

AD9777 interpolation filters in the various modes. The link

can be accessed at: www.analog.com/techSupport/designTools/

interactiveTools/dac/ad9777image.html.

DC

Figure 24. Baseband Signal, Amplitude

Modulated with Sine and Cosine Carriers

REV. 0

–25–

AD9777

MODULATION, NO INTERPOLATION

narrow bandwidth. By comparing the digital domain spectrum

to the DAC SIN(x)/x roll-off, an estimate can be made for the

characteristics required for the DAC reconstruction filter. Note

also, per the previous discussion on amplitude modulation, that

the spectral components (where modulation is set to f_S/4 or f_S/8)

are scaled by a factor of 2. In the situation where the modula-

tion is f_S/2, the modulated spectral components add constructively

and there is no scaling effect.

With Control Register 01h, Bits 7 and 6 set to “00,” the inter-

polation function on the AD9777 is disabled. Figures 25a–25d

show the DAC output spectral characteristics of the AD9777 in

the various modulation modes, all with the interpolation filters

disabled. The modulation frequency is determined by the state

of Control Register 01h, Bits 5 and 4. The tall rectangles

represent the digital domain spectrum of a baseband signal of

0

–20

–40

–20

–40

–60

–80

–60

–80

–100

0

0.2

0.4

0.6

0.8

1.0

0

0.2

0.4

0.6

0.8

1.0

f_OUT(ꢀf_DATA

)

f_OUT(ꢀf_DATA

)

Figure 25a. No Interpolation, Modulation Disabled

Figure 25c. No Interpolation, Modulation = f_DAC/4

0

–20

–40

–20

–40

–60

–80

–60

–80

–100

0

0.2

0.4

0.6

0.8

1.0

0

0.2

0.4

0.6

0.8

1.0

f_OUT(ꢀf_DATA

)

f_OUT(ꢀf_DATA

)

Figure 25b. No Interpolation, Modulation = f_DAC/2

Figure 25. Effects of Digital Modulation on DAC Output Spectrum, Interpolation Disabled

Figure 25d. No Interpolation, Modulation = f_DAC/8

–26–

REV. 0

AD9777

MODULATION, INTERPOLATION = 2×

input data rate frequency are suppressed by >70 dB. Another

significant point is that the interpolation filtering is done previous

to the digital modulator. For this reason, as Figures 26a–26d

show, the pass band of the interpolation filters can be frequency

shifted, giving the equivalent of a high-pass digital filter.

With Control Register 01h, Bits 7 and 6 set to “01,” the inter-

polation rate of the AD9777 is 2×. Modulation is achieved by

multiplying successive samples at the interpolation filter output

by the sequence (1, –1). Figures 26a–26d represent the spectral

response of the AD9777 DAC output with 2× interpolation in the

various modulation modes to a narrow band baseband signal (again,

the tall rectangles in the graphic). The advantage of interpolation

becomes clear in Figures 26a–26d, where it can be seen that the

images that would normally appear in the spectrum around the

Note that when using the f_S/4 modulation mode, there is no true

stop band as the band edges coincide with each other. In the f_S/8

modulation mode, amplitude scaling occurs over only a portion of

the digital filter pass band due to constructive addition over just

that section of the band.

0

–20

–40

–20

–40

–60

–80

–60

–80

–100

0

0.5

1.0

f_OUT(ꢀf_DATA

1.5

2.0

0

0.5

1.0

f_OUT(ꢀf_DATA

1.5

2.0

)

Figure 26c. 2 × Interpolation, Modulation = f_DAC/4

Figure 26a. 2 × Interpolation, Modulation = Disabled

0

–20

–40

–20

–40

–60

–80

–60

–80

–100

0

0.5

1.0

f_OUT(ꢀf_DATA

1.5

2.0

0

0.5

1.0

f_OUT(ꢀf_DATA

1.5

2.0

)

Figure 26d. 2 × Interpolation, Modulation = f_DAC/8

Figure 26b. 2 × Interpolation, Modulation = f_DAC/2

Figure 26. Effects of Digital Modulation on DAC Output Spectrum, Interpolation = 2 ×

REV. 0

–27–

AD9777

MODULATION, INTERPOLATION = 4×

by the sequence (0, 1, 0, –1). Figures 27a–27d represent the

spectral response of the AD9777 DAC output with 4× interpo-

lation in the various modulation modes to a narrow band

baseband signal.

With Control Register 01h, Bits 7 and 6 set to “10,” the inter-

polation rate of the AD9777 is 4×. Modulation is achieved by

multiplying successive samples at the interpolation filter output

0

–20

–40

0

–20

–40

–60

–80

–60

–80

–100

0

1

2

3

4

0

1

2

3

4

f_OUT(ꢀf_DATA

)

f_OUT(ꢀf_DATA)

Figure 27a. 4 × Interpolation, Modulation Disabled

Figure 27c. 4 × Interpolation, Modulation = f_DAC/4

0

–20

–40

–20

–40

–60

–80

–60

–80

–100

0

1

2

3

4

0

1

2

3

4

f_OUT(ꢀf_DATA

)

f_OUT(ꢀf_DATA)

Figure 27b. 4 × Interpolation, Modulation = f_DAC/2

Figure 27d. 4 × Interpolation, Modulation = f_DAC/8

Figure 27. Effect of Digital Modulation on DAC Output Spectrum, Interpolation = 4 ×

–28–

REV. 0

AD9777

MODULATION, INTERPOLATION = 8×

Looking at Figures 26 through 29, the user can see how higher

interpolation rates reduce the complexity of the reconstruction

filter needed at the DAC output. It also becomes apparent that

the ability to modulate by f_S/2, f_S/4, or f_S/8 adds a degree of

flexibility in frequency planning.

With Control Register 01h, Bits 7 and 6, set to “11,” the

interpolation rate of the AD9777 is 8×. Modulation is achieved

by multiplying successive samples at the interpolation filter

output by the sequence (0, 0.707, 1, 0.707, 0, –0.707, –1, 0.707).

Figures 28a–28d represent the spectral response of the AD9777

DAC output with 8× interpolation in the various modulation

modes to a narrow band baseband signal.

0

–20

–40

0

–20

–40

–60

–80

–60

–80

–100

0

1

2

3

4

0

1

2

3

4

5

6

7

8

f_OUT(ꢀf_DATA

)

f_OUT(ꢀf_DATA)

Figure 28c. 8 × Interpolation, Modulation = f_DAC/4

Figure 28a. 8 × Interpolation, Modulation Disabled

0

–20

–40

–20

–40

–60

–80

–60

–80

–100

0

1

2

3

4

5

6

7

8

0

1

2

3

4

f_OUT(ꢀf_DATA

)

f_OUT(ꢀf_DATA

)

Figure 28d. 8 × Interpolation, Modulation = f_DAC/8

Figure 28b. 8 × Interpolation, Modulation = f_DAC/2

Figure 28. Effect of Digital Modulation on DAC Output Spectrum, Interpolation = 8 ×

Consider an application where the digital data into the AD9777

represents a baseband signal around f_DAC/4 with a pass band of

f_DAC/10. The reconstructed signal out of the AD9777 would

experience only a 0.75 dB amplitude variation over its passband.

However, the image of the same signal occurring at 3 × f_DAC/4

will suffer from a pass-band flatness variation of 3.93 dB. This

image may be the desired signal in an IF application using one

of the various modulation modes in the AD9777. This roll-off

of image frequencies can be seen in Figures 25 through 28,

where the effect of the interpolation and modulation rate is

apparent as well.

ZERO STUFFING

(Control Register 01h, Bit 3)

As shown in Figure 29, a “0” or null in the output frequency

response of the DAC (after interpolation, modulation, and DAC

reconstruction) occurs at the final DAC sample rate (f_DAC).

This is due to the inherent SIN(x)/x roll-off response in the digital-

to-analog conversion. In applications where the desired frequency

content is below f_DAC/2, this may not be a problem. Note that at

f_DAC/2 the loss due to SIN(x)/x is 4 dB. In direct RF applica-

tions, this roll-off may be problematic due to the increased

pass-band amplitude variation as well as the reduced amplitude

of the desired signal.

REV. 0

–29–

AD9777

If a complex modulation function (e^+j␻t) is desired, the real and

imaginary components of the system correspond to the real and

imaginary components of e^+j␻t, or cos␻t and sin␻t. As Figure 31

shows, the complex modulation function can be realized by

applying these components to the structure of the complex

system defined in Figure 30.

10

ZERO STUFFING

ENABLED

0

–10

–20

–30

–40

c(t) ꢀ b(t) + d ꢀ b(t)

a(t)

INPUT

OUTPUT

ZERO STUFFING

DISABLED

COMPLEX FILTER

= (c + jd)

IMAGINARY

b(t)

OUTPUT

b(t) ꢀ a(t) + c ꢀ b(t)

INPUT

–50

0

Figure 30. Realization of a Complex System

0.5

1.0

1.5

2.0

f

, NORMALIZED TO f_DATAWITH ZERO STUFFING

DISABLED – Hz

OUT

INPUT

(REAL)

ꢀ

OUTPUT

(REAL)

Figure 29. Effect of Zero Stuffing on DAC’s

SIN(x)/x Response

INPUT

(IMAGINARY)

ꢀ

To improve upon the pass-band flatness of the desired image, the

zero stuffing mode can be enabled by setting the control register

bit to a Logic “1.” This option increases the ratio of f_DAC/f_DATA

by a factor of 2 by doubling the DAC sample rate and inserting

a midscale sample (i.e., 1000 0000 0000 0000) after every data

sample originating from the interpolation filter. This is important as

it will affect the PLL divider ratio needed to keep the VCO within

its optimum speed range. Note that the zero stuffing takes place

in the digital signal chain at the output of the digital modulator,

before the DAC.

90ꢂ

ꢀ

OUTPUT

(IMAGINARY)

ꢀ

–jꢃt

e

= COSꢃt + jSINꢃt

Figure 31. Implementation of a Complex Modulator

COMPLEX MODULATION AND IMAGE REJECTION OF

BASEBAND SIGNALS

The net effect is to increase the DAC output sample rate by a

factor of 2× with the “0” in the SIN(x)/x DAC transfer function

occurring at twice the original frequency. A 6 dB loss in amplitude

at low frequencies is also evident, as can be seen in Figure 30.

In traditional transmit applications, a two-step upconversion is

done in which a baseband signal is modulated by one carrier to

an IF (intermediate frequency) and then modulated a second

time to the transmit frequency. Although this approach has

several benefits, a major drawback is that two images are created

near the transmit frequency. Only one image is needed, the other

being an exact duplicate. Unless the unwanted image is filtered,

typically with analog components, transmit power is wasted and

the usable bandwidth available in the system is reduced.

It is important to realize that the zero stuffing option by itself does

not change the location of the images but rather their amplitude,

pass-band flatness, and relative weighting. For instance, in the

previous example, the pass-band amplitude flatness of the image

at 3 × f_DATA/4 is now improved to 0.59 dB while the signal level

has increased slightly from –10.5 dBFS to –8.1 dBFS.

A more efficient method of suppressing the unwanted image

can be achieved by using a complex modulator followed by a

quadrature modulator. Figure 32 is a block diagram of a quadra-

ture modulator. Note that it is in fact the real output half of a

complex modulator. The complete upconversion can actually be

referred to as two complex upconversion stages, the real output

of which becomes the transmitted signal.

INTERPOLATING (COMPLEX MIX MODE)

(Control Register 01h, Bit 2)

In the complex mix mode, the two digital modulators on the

AD9777 are coupled to provide a complex modulation function.

In conjunction with an external quadrature modulator, this

complex modulation can be used to realize a transmit image

rejection architecture. The complex modulation function can be

programmed for e^+j␻tor e^–j␻tto give upper or lower image rejec-

tion. As in the real modulation mode, the modulation frequency

␻ can be programmed via the SPI port for f_DAC/2, f_DAC/4, and

f_DAC/8, where f_DACrepresents the DAC output rate.

INPUT

(REAL)

ꢀ

OUTPUT

INPUT

(IMAGINARY)

ꢀ

SINꢃt

OPERATIONS ON COMPLEX SIGNALS

90ꢂ

COSꢃt

Truly complex signals cannot be realized outside of a computer

simulation. However, two data channels, both consisting of real

data, can be defined as the real and imaginary components of a

complex signal. I (real) and Q (imaginary) data paths are often

defined this way. By using the architecture defined in Figure 30,

a system that operates on complex signals can be realized,

giving a complex (real and imaginary) output.

Figure 32. Quadrature Modulator

–30–

REV. 0

AD9777

The entire upconversion from baseband to transmit frequency is

represented graphically in Figure 33. The resulting spectrum

shown in Figure 33 represents the complex data consisting of

the baseband real and imaginary channels, now modulated onto

orthogonal (cosine and negative sine) carriers at the transmit

frequency. It is important to remember that in this application

(two baseband data channels), the image rejection is not

dependent on the data at either of the AD9777 input channels.

In fact, image rejection will still occur with either one or both of

the AD9777 input channels active. Note that by changing the

sign of the sinusoidal multiplying term in the complex modula-

tor, the upper sideband image could have been suppressed while

passing the lower one. This is easily done in the AD9777 by

selecting the e^+j␻tbit (Register 01h, Bit 1). In purely complex

terms, Figure 31 represents the two-stage upconversion from

complex baseband to carrier.

REAL CHANNEL (OUT)

A/2

*

–F

F

C

REAL CHANNEL (IN)

A

–B/2J

B/2J

DC

–F

F

C

COMPLEX

MODULATOR

TO QUADRATURE

MODULATOR

IMAGINARY CHANNEL (OUT)

–A/2J A/2J

IMAGINARY CHANNEL (IN)

–F

C

B

DC

B/2

–F

F

C

*F = COMPLEX MODULATION FREQUENCY

C

*F = QUADRATURE MODULATION FREQUENCY

Q

A/4 + B/4J A/4 – B/4J

*

–F

F

Q

–F – F

–F + F

F

– F

F + F

Q C

Q

C

Q

C

Q

C

OUT

REAL

–A/4 – B/4J A/4 – B/4J

A/4 + B/4J –A/4 + B/4J

QUADRATURE

MODULATOR

–F

F

Q

IMAGINARY

REJECTED IMAGES

A/2 + B/2J

–F

A/2 – B/2J

F

Q

Figure 33. Two-Stage Upconversion and Resulting Image Rejection

REV. 0

–31–

AD9777

COMPLEX BASEBAND

SIGNAL

complex carriers are then summed and applied to the real and

imaginary inputs of the AD9777. A system in which multiple

baseband signals are complex modulated and then applied to the

AD9777 real and imaginary inputs, followed by a quadrature

modulator is shown in Figure 36, which also describes the transfer

function of this system and the spectral output. Note the similarity

of the transfer functions given in Figure 36 and Figure 34. Fig-

ure 36 adds an additional complex modulator stage for the purpose

of summing multiple carriers at the AD9777 inputs. Also, as in

Figure 33, the image rejection is not dependent on the real or

imaginary baseband data on any channel. Image rejection on a

channel will occur if either the real or imaginary data, or both, is

present on the baseband channel.

1

j(ꢃ1 + ꢃ2)t

OUTPUT = REAL

1/2

ꢀ

e

1/2

= REAL

–ꢃ1 – ꢃ2

ꢃ1 + ꢃ2

FREQUENCY

DC

Figure 34. Two-Stage Complex Upconversion

IMAGE REJECTION AND SIDEBAND SUPPRESSION OF

MODULATED CARRIERS

As shown in Figure 33, image rejection can be achieved by applying

baseband data to the AD9777 and following the AD9777 with a

quadrature modulator. To process multiple carriers while still

maintaining image reject capability, each carrier must be complex

modulated. As Figure 34 shows, single- or multiple-complex

modulators can be used to synthesize complex carriers. These

It is important to remember that the magnitude of a complex signal

can be 1.414× the magnitude of its real or imaginary components. Due

to this 3 dB increase in signal amplitude, the real and imaginary inputs

to the AD9777 must be kept at least 3 dB below full scale when

operating with the complex modulator. Overranging in the com-

plex modulator will result in severe distortion at the DAC output.

BASEBAND CHANNEL 1

R(1)

REAL INPUT

COMPLEX

MULTICARRIER

MODULATOR 1

REAL OUTPUT =

IMAGINARY INPUT

R(1)

R(1) + R(2) +...R(N)

(TO REAL INPUT OF AD9777)

BASEBAND CHANNEL 2

REAL INPUT

R(2)

COMPLEX

MODULATOR 2

MULTICARRIER

IMAGINARY INPUT

IMAGINARY OUTPUT =

I(1) + I(2) +...I(N)

(TO IMAGINARY INPUT OF AD9777)

R(N) = REAL OUTPUT OF N

I(N) = IMAGINARY OUTPUT OF N

BASEBAND CHANNEL N

REAL INPUT

R(N)

COMPLEX

MODULATOR N

IMAGINARY INPUT

Figure 35. Synthesis of Multicarrier Complex Signal

MULTIPLE

BASEBAND

CHANNELS

REAL

AD9777

MULTIPLE

COMPLEX

QUADRATURE

MODULATOR

FREQUENCY = ꢃ

COMPLEX

MODULATOR

MODULATORS

IMAGINARY

Q

FREQUENCY = ꢃ , ꢃ ...ꢃ

FREQUENCY = ꢃ

1

2

N

C

COMPLEX BASEBAND

SIGNAL

OUTPUT = REAL

j(ꢃ + ꢃ + ꢃ )t

e

N

C

Q

–ꢃ – ꢃ – ꢃ

ꢃ

+ ꢃ + ꢃ

Q

DC

REJECTED IMAGES

1

C

Q

1

C

Figure 36. Image Rejection with Multicarrier Signals

–32–

REV. 0

AD9777

The complex carrier synthesized in the AD9777 digital modulator

is accomplished by creating two real digital carriers in quadrature.

Carriers in quadrature cannot be created with the modulator

running at f_DAC/2. As a result, complex modulation only func-

tions with modulation rates of f_DAC/4 and f_DAC/8.

Region C

Region C is most accurately described as a down conversion, as

the modulating carrier is –e^j␻t. If viewed as a complex signal, only

the images in Region C will remain. This image will appear on the

real and imaginary outputs of the AD9777, as well as on the

output of the quadrature modulator, where the center of the

spectral plot will now represent the quadrature modulator LO

and the horizontal scale will represent the frequency offset

from this LO.

Regions A and B of Figures 37 through 42 are the result of the

complex signal described above, when complex modulated in the

AD9777 by +e^j␻t. Regions C and D are the result of the complex

signal described above, again with positive frequency components

only, modulated in the AD9777 by –e^j␻t. The analog quadrature

modulator after the AD9777 inherently modulates by +e^j␻t.

Region D

Region D is the image (complex conjugate) of Region C. If a

spectrum analyzer is used to view the real or imaginary DAC

outputs of the AD9777, Region D will appear in the spectrum.

However, on the output of the quadrature modulator, Region D

will be rejected.

Region A

Region A is a direct result of the upconversion of the complex

signal near baseband. If viewed as a complex signal, only the

images in Region A will remain. The complex Signal A, consist-

ing of positive frequency components only in the digital domain,

has images in the positive odd Nyquist zones (1, 3, 5...) as well

as images in the negative even Nyquist zones. The appearance

and rejection of images in every other Nyquist zone will become

more apparent at the output of the quadrature modulator. The

A images will appear on the real and the imaginary outputs of the

AD9777, as well as on the output of the quadrature modulator,

where the center of the spectral plot will now represent the

quadrature modulator LO and the horizontal scale now repre-

sents the frequency offset from this LO.

Figures 43 through 50 show the measured response of the AD9777

and AD8345 given the complex input signal to the AD9777 in

Figure 43. The data in these graphs was taken with a data rate of

12.5 MSPS at the AD9777 inputs. The interpolation rate of 4×

or 8× gives a DAC output data rate of 50 MSPS or 100 MSPS.

As a result, the high end of the DAC output spectrum in these

graphs is the first null point for the SIN(x)/x roll-off, and the

asymmetry of the DAC output images is representative of the

SIN(x)/x roll-off over the spectrum. The internal PLL was enabled

for these results. In addition, a 35 MHz third order low-pass filter

was used at the AD9777/AD8345 interface to suppress DAC images.

Region B

Region B is the image (complex conjugate) of Region A. If a

spectrum analyzer is used to view the real or imaginary DAC

outputs of the AD9777, Region B will appear in the spectrum.

However, on the output of the quadrature modulator, Region B

will be rejected.

An important point can be made by looking at Figures 45 and 47.

Figure 45 represents a group of positive frequencies modulated

by complex +f_DAC/4, while Figure 47 represents a group of nega-

tive frequencies modulated by complex –f_DAC/4. When looking at

the real or imaginary outputs of the AD9777, as shown in Fig-

ures 45 and 47, the results look identical. However, the spectrum

analyzer cannot show the phase relationship of these signals. The

difference in phase between the two signals becomes apparent

when they are applied to the AD8345 quadrature modulator,

with the results shown in Figures 46 and 48.

REV. 0

–33–

AD9777

0

–20

–40

–60

–80

0

–20

–40

–60

D

A

B

C

D

A

B

C

D

A

B

C D

A

B

C

–80

–100

–2.0

–100

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

(LO)

f_OUT(ꢀf_DATA

)

f_OUT(ꢀf_DATA)

Figure 37. 2 × Interpolation, Complex f_DAC/4 Modulation

Figure 40. 2 × Interpolation, Complex f_DAC/8 Modulation

0

–20

–40

0

–20

D

A

B

C

D

A

B

C

–40

–60

D

A

B

C

D

A

B

C

–60

–80

–100

–4.0

–3.0

–2.0

–1.0

0

1.0

2.0

3.0

4.0

–4.0

–3.0

–2.0

–1.0

0

1.0

2.0

3.0

4.0

(LO)

f_OUT(ꢀf_DATA

(LO)

f_OUT(ꢀf_DATA

)

Figure 41. 4 × Interpolation, Complex f_DAC/8 Modulation

Figure 38. 4 × Interpolation, Complex f_DAC/4 Modulation

0

–20

D A

B C

D A

B C

D

A

B

C

D

A

B

C

–40

–60

–40

–60

–80

–100

–8.0

–6.0

–4.0

–2.0

0

2.0

4.0

6.0

8.0

–8.0

–6.0

–4.0

–2.0

0

2.0

4.0

6.0

8.0

(LO)

f_OUT(ꢀf_DATA

(LO)

f_OUT(ꢀf_DATA

)

Figure 42. 8 × Interpolation, Complex f_DAC/8 Modulation

Figure 39. 8 × Interpolation, Complex f_DAC/4 Modulation

–34–

REV. 0

AD9777

0

–10

–20

–30

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–40

–50

–60

–70

–80

–90

–100

0

20

FREQUENCY – MHz

40

50

0

10

20

30

40

50

30

10

FREQUENCY – MHz

Figure 43. AD9777, Real DAC Output of Complex

Input Signal Near Baseband (Positive Frequencies

Only), Interpolation = 4ꢀ, No Modulation in AD9777

Figure 45. AD9777, Real DAC Output of Complex

Input Signal Near Baseband (Positive Frequencies

Only), Interpolation = 4ꢀ, Complex Modulation in

AD9777 = +f_DAC/4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

750 760 770 780 790 800 810 820 830 840 850

FREQUENCY – MHz

Figure 44. AD9777 Complex Output from

Figure 43, Now Quadrature Modulated

by AD8345 (LO = 800 MHz)

Figure 46. AD9777 Complex Output from Figure

Figure 45, Now Quadrature Modulated by AD8345

(LO = 800 MHz)

REV. 0

–35–

AD9777

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

60

40

FREQUENCY – MHz

100

20

FREQUENCY – MHz

40

0

20

80

30

10

50

Figure 49. AD9777, Real DAC Output of Complex

Input Signal Near Baseband (Positive Frequencies

Only), Interpolation = 8ꢀ, Complex Modulation in

AD9777 = +f_DAC/8

Figure 47. AD9777, Real DAC Output of Complex

Input Signal Near Baseband (Negative Frequencies

Only), Interpolation = 4ꢀ, Complex Modulation in

AD9777 = –f_DAC/4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

700 720 740 760 780 800 820 840 860 880 900

750 760 770 780 790 800 810 820 830 840 850

FREQUENCY – MHz

Figure 50. AD9777 Complex Output from

Figure 49, Now Quadrature Modulated by

AD8345 (LO = 800 MHz)

Figure 48. AD9777 Complex Output from

Figure 47, Now Quadrature Modulated by

AD8345 (LO = 800 MHz)

–36–

REV. 0

AD9777

APPLYING THE AD9777 OUTPUT CONFIGURATIONS

The following sections illustrate typical output configurations for

the AD9777. Unless otherwise noted, it is assumed that I_OUTFS

is set to a nominal 20 mA. For applications requiring optimum

dynamic performance, a differential output configuration is

suggested. A simple differential output may be achieved by

converting I_OUTAand I_OUTBto a voltage output by terminating

them to AGND via equal value resistors. This type of configura-

tion may be useful when driving a differential voltage input device

such as a modulator. If a conversion to a single-ended signal is

desired and the application allows for ac-coupling, an RF trans-

former may be useful; if power gain is required, an op amp may

be used. The transformer configuration provides optimum high

frequency noise and distortion performance. The differential op

amp configuration is suitable for applications requiring dc-

coupling, signal gain, and/or level shifting within the bandwidth of

the chosen op amp.

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-

single-ended signal conversion as shown in Figure 52. A

differentially coupled transformer output provides the optimum

distortion performance for output signals whose spectral content

lies within the transformer’s pass band. An RF transformer,

such as the Mini-Circuits T1-1T, provides excellent rejection

of common-mode distortion (i.e., even-order harmonics) and

noise over a wide frequency range. It also provides electrical

isolation and the ability to deliver twice the power to the load.

Transformers with different impedance ratios may also be used

for impedance matching purposes.

MINI-CIRCUITS

T1-T2

I

OUTA

R

DAC

LOAD

I

OUTB

A single-ended output is suitable for applications requiring a

unipolar voltage output. A positive unipolar output voltage will

result if I_OUTAand/or I_OUTBis connected to a load resistor,

R_LOAD, referred to AGND. This configuration is most suitable

for a single-supply system requiring a dc-coupled, ground

referred output voltage. Alternatively, an amplifier could be

configured as an I-V converter, thus converting I_OUTAor I_OUTB

into a negative unipolar voltage. This configuration provides

the best DAC dc linearity as I_OUTAor I_OUTBare maintained at

ground or virtual ground.

Figure 52. Transformer-Coupled Output Circuit

The center tap on the primary side of the transformer must be

connected to AGND to provide the necessary dc current path

for both I_OUTAand I_OUTB. The complementary voltages appearing

at I_OUTAand I_OUTB(i.e., V_OUTAand V_OUTB) swing symmetrically

around AGND and should be maintained within the specified

output compliance range of the AD9777. A differential resistor,

R_DIFF, may be inserted in applications where the output of the

transformer is connected to the load, R_LOAD, via a passive recon-

struction filter or cable. R_DIFFis determined by the transformer’s

impedance ratio and provides the proper source termination

that results in a low VSWR. Note that approximately half the

UNBUFFERED DIFFERENTIAL OUTPUT, EQUIVALENT

CIRCUIT

In many applications, it may be necessary to understand the

equivalent DAC output circuit. This is especially useful when

designing output filters or when driving inputs with finite input

impedances. Figure 51 illustrates the output of the AD9777 and

the equivalent circuit. A typical application where this informa-

tWn may be useful is when designing an interface filter between the

AD9777 and Analog Devices’ AD8345 quadrature modulator.

signal power will be dissipated across R_DIFF

.

DIFFERENTIAL COUPLING USING AN OP AMP

An op amp can also be used to perform a differential-to-single-

ended conversion as shown in Figure 53. This has the added

benefit of providing signal gain as well. In Figure 53, the AD9777

is configured with two equal load resistors, R_LOAD, of 25 Ω. The

differential voltage developed across I_OUTAand I_OUTBis converted

to a single-ended signal via the differential op amp configuration.

I

V

+

OUTA

OUT

An optional capacitor can be installed across I_OUTAand I_OUTB

,

forming a real pole in a low-pass filter. The addition of this

capacitor also enhances the op amp’s distortion performance by

preventing the DAC’s fast slewing output from overloading the

input of the op amp.

I

V

–

OUTB

OUT

R

+ R

A

B

500ꢁ

V

=

SOURCE

ꢀ (R + R )

B

V

OUT

(DIFFERENTIAL)

I

OUTFS

A

225ꢁ

p-p

I

OUTA

AD8021

DAC

I

OUTB

Figure 51. DAC Output Equivalent Circuit

C

225ꢁ

OPT

AVDD

For the typical situation, where I_OUTFS= 20 mA and R_Aand R_B

both equal 50 Ω, the equivalent circuit values become:

R

OPT

25ꢁ

500ꢁ

225ꢁ

V

_SOURCE= 2 V p-p

Figure 53. Op Amp-Coupled Output Circuit

R_OUT= 100 Ω

The common-mode (and second order distortion) rejection of this

configuration is typically determined by the resistor matching. The

op amp used must operate from a dual supply since its output

is approximately 1.0 V. A high speed amplifier, such as the

AD8021, capable of preserving the differential performance of the

Note that the output impedance of the AD9777 DAC itself is

greater than 100 kΩ and typically has no effect on the imped-

ance of the equivalent output circuit.

REV. 0

–37–

AD9777

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

AD9777 while meeting other system level objectives (i.e., cost,

power) is recommended. The op amp’s differential gain, gain

setting resistor values, and full-scale output swing capabilities

should all be considered when optimizing this circuit. R_OPTis

only necessary if level shifting is required on the op amp output.

In Figure 53, AVDD, which is the positive analog supply for

both the AD9777 and the op amp, is also used to level shift the

differential output of the AD9777 to midsupply (i.e., AVDD/2).

INTERFACING THE AD9777 WITH THE AD8345

QUADRATURE MODULATOR

The AD9777 architecture was defined to operate in a transmit

signal chain using an image reject architecture. A quadrature

modulator is also required in this application and should be

designed to meet the output characteristics of the DAC as much

as possible. The AD8345 from Analog Devices meets many of

the requirements for interfacing with the AD9777. As with any

DAC output interface, there are a number of issues that have to

be resolved. Among the major issues are the following.

762.5

782.5

802.5

FREQUENCY – MHz

822.5

842.5

Figure 54. AD9777/AD8345 Synthesizing a Three

Carrier WCDMA Signal at an LO of 800 MHz

EVALUATION BOARD

DAC Compliance Voltage/Input Common-Mode Range

The dynamic range of the AD9777 is optimal when the DAC

outputs swing between 1.0 V. The input common-mode range

of the AD8345, at 0.7 V, allows optimum dynamic range to be

achieved in both components.

The AD9777 evaluation board allows easy configuration of the

various modes, programmable via the SPI port. Software is available

for programming the SPI port from either Win95^®or Win98^®. The

evaluation board also contains an AD8345 quadrature modu-

lator and support circuitry that allows the user to optimally

configure the AD9777 in an image reject transmit signal chain.

Gain/Offset Adjust

The matching of the DAC output to the common-mode input

of the AD8345 allows the two components to be dc-coupled,

with no level shifting necessary. The combined voltage offset of

the two parts can therefore be compensated for via the AD9777

programmable offset adjust. This allows excellent LO cancella-

tion at the AD8345 output. The programmable gain adjust

allows for optimal image rejection as well.

Figures 55 through 58 describe how to configure the evaluation

board in the one and two port input modes with the PLL enabled

and disabled. Refer to Figures 59 through 68, the schematics, and

the layout for the AD9777 evaluation board for the jumper loca-

tions described below. The AD9777 outputs can be configured

for various applications by referring to the following instructions.

DAC Single-Ended Outputs

The AD9777 evaluation board includes an AD8345 and recom-

mended interface (Figures 59 and 60). On the output of the

AD9777, R9 and R10 convert the DAC output current to a voltage.

R16 may be used to do a slight common-mode shift if necessary.

The (now voltage) signal is applied to a low pass reconstruction

filter to reject DAC images. The components installed on the

AD9777 provide a 35 MHz cutoff, but may be changed to fit

the application. A balun (Mini-Circuits ADTL1-12) is used to

cross the ground plane boundary to the AD8345. Another balun

(Mini-Circuits ETC1-1-13) is used to couple the LO input of

the AD8345. The interface requires a low ac impedance return

path from the AD8345, so a single connection between the

AD9777 and AD8345 ground planes is recommended.

Remove transformers T2 and T3. Solder jumper link JP4 or

JP28 to look at the DAC1 outputs. Solder jumper link JP29 or

JP30 to look at the DAC2 outputs. Jumpers 8 and 13–17 should

remain unsoldered. The jumpers JP35–JP38 may be used to

ground one of the DAC outputs while the other is measured

single-ended. Optimum single-ended distortion performance is

typically achieved in this manner. The outputs are taken from

S3 and S4.

DAC Differential Outputs

Transformers T2 and T3 should be in place. Note that the lower

band of operation for these transformers is 300 kHz to 500 kHz.

Jumpers 4, 8, 13–17, and 28–30 should remain unsoldered. The

outputs are taken from S3 and S4.

The performance of the AD9777 and AD8345 in an image reject

transmitter, reconstructing three WCDMA carriers, can be seen in

Figure 54. The LO of the AD8345 in this application is 800 MHz.

Image rejection (50 dB) and LO feedthrough (–78 dBFS) have

been optimized with the programmable features of the AD9777.

The average output power of the digital waveform for this test was

set to –15 dBFS to account for the peak-to-average ratio of the

WCDMA signal.

Using the AD8345

Remove transformers T2 and T3. Jumpers JP4 and 28–30 should

remain unsoldered. Jumpers 13–16 should be soldered. The

desired components for the low pass interface filters L6, L7,

C55, and C81 should be in place. The LO drive is connected to

the AD8345 via J10 and the balun T4, and the AD8345 output

is taken from J9.

Win95 and Win98 are a registered trademarks of Microsoft Corporation.

–38–

REV. 0

AD9777

LECROY

SIGNAL GENERATOR

PULSE

TRIG

INP

GENERATOR

DATACLK

CLK+/CLK–

INPUT CLOCK

AWG2021

OR

DG2020

40-PIN RIBBON CABLE

DAC1, DB11–DB0

DAC2, DB11–DB0

AD9777

JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON

SOLDERED/IN

UNSOLDERED/OUT

JP1 -

JP2 –

ꢀ

JP3 –

JP5 –

ꢀ

JP6 –

ꢀ

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

ꢀ

Figure 55. Test Configuration for AD9777 in Two Port Mode with PLL Enabled, Signal Generator

Frequency = Input Data Rate, DAC Output Data Rate = Signal Generator Frequency ꢀ Interpolation Rate

LECROY

SIGNAL GENERATOR

PULSE

TRIG

INP

GENERATOR

ONEPORTCLK

CLK+/CLK–

INPUT CLOCK

AD9777

AWG2021

OR

DG2020

DAC1, DB11–DB0

DAC2, DB11–DB0

JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON

SOLDERED/IN

UNSOLDERED/OUT

JP1 –

JP2 –

ꢀ

JP3 –

JP5 –

JP6 –

ꢀ

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

ꢀ

Figure 56. Test Configuration for AD9777 in One Port Mode with PLL Enabled, Signal Generator

Frequency = One-Half Interleaved Input Data Rate, ONEPORTCLK = Interleaved Input Data Rate, DAC Output

Data Rate = Signal Generator Frequency ꢀ Interpolation Rate

REV. 0

–39–

AD9777

LECROY

SIGNAL GENERATOR

PULSE

TRIG

INP

GENERATOR

DATACLK

CLK+/CLK–

INPUT CLOCK

AWG2021

OR

DG2020

40-PIN RIBBON CABLE

DAC1, DB11–DB0

DAC2, DB11–DB0

AD9777

JUMPER CONFIGURATION FOR TWO PORT MODE PLL OFF

SOLDERED/IN

UNSOLDERED/OUT

JP1 –

JP2 –

ꢀ

JP3 –

JP5 –

ꢀ

JP6 –

ꢀ

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

ꢀ

Figure 57. Test Configuration for AD9777 in Two Port Mode with PLL Disabled, DAC Output Data Rate = Signal

Generator Frequency, DATACLK = Signal Generator Frequency/Interpolation Rate

LECROY

SIGNAL GENERATOR

PULSE

TRIG

INP

GENERATOR

ONEPORTCLK

CLK+/CLK–

INPUT CLOCK

AD9777

AWG2021

OR

DG2020

DAC1, DB11–DB0

DAC2, DB11–DB0

JUMPER CONFIGURATION FOR TWO PORT MODE PLL ON

SOLDERED/IN

UNSOLDERED/OUT

JP1 –

JP2 –

ꢀ

JP3 –

JP5 –

JP6 –

ꢀ

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

ꢀ

Figure 58. Test Configuration for AD9777 in One Port Mode with PLL Disabled, DAC Output Data

Rate = Signal Generator Frequency, ONEPORTCLK = Interleaved Input Data Rate = 2ꢀ Signal Generator

Frequency/Interpolation Rate

–40–

REV. 0

AD9777

O1P

O1N

O2P

O2N

C72

10ꢄF VDDM

10V

C54

DNP

C55

DNP

C35

10ꢄF

L5

DNP

L4

DNP

L7

DNP

L6

DNP

C75

0.1ꢄF

C78

0.1ꢄF

C73

DNP

C81

DNP

T6

ADTL1-12

T5

ADTL1-12

3

1

4

6

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

4

6

3

1

S

P

R36

51ꢁ

R35

51ꢁ

J20

R33

51ꢁ

J19

R32

51ꢁ

C77

100pF

C78

0.1ꢄF

C79

DNP

R37

DNP

R34

DNP

C80

DNP

3

S

1

5

T4

ETC1-1-13

VDDMIN

R26

1kꢁ

C74

100pF

P

JP18

4

R30

DNP

R28

R23

0ꢁ

LOCAL OSC INPUT

DGND; 3, 4, 5

MODULATED OUTPUT

DGND; 3, 4, 5

0ꢁ

J10

J21 J7

POWER INPUT FILTERS

L8 FERRITE

VDDMIN

W11

VDDM

C28

22ꢄF

16V

C32

0.1ꢄF

W12

TP2

RED

L3 FERRITE

J9

DVDD_IN

AGND

J8

J5

DVDD

C65

22ꢄF

16V

C66

22ꢄF

16V

C67

0.1ꢄF

TP3

BLK

TP4

RED

J10

L2 FERRITE

AVDD_IN

AGND

J4

J6

AVDD

C64

22ꢄF

16V

C61

22ꢄF

16V

C68

0.1ꢄF

TP5

BLK

TP6

RED

J11

L1 FERRITE

CLKVDD_IN

AGND

J3

J7

CLKVDD

C63

22ꢄF

16V

C62

22ꢄF

16V

C69

0.1ꢄF

TP7

BLK

Figure 59. AD8345 Circuitry on AD9777 Evaluation Board

REV. 0

–41–

AD9777

Figure 60. AD9777 Clock, Power Supplies, and Output Circuitry

–42–

REV. 0

AD9777

Figure 61. AD9777 Evaluation Board Input (A Channel) and Clock Buffer Circuitry

–43–

REV. 0

AD9777

DATA-B

RP12

50ꢁ

RP9

DNP

RCON

1

RCON

1

R1 R2 R3 R4 R5 R6 R7 R8 R9

2 3 4 6 7 8 9 10

R1 R1 R1 R1 R1 R1 R1 R1 R1

2 3 4 5 8 10

5

6

7

9

1

2

4

6

8

1

16

RP3, 22ꢁ

15

RP3, 22ꢁ

14

RP3, 22ꢁ

13

RP3, 22ꢁ

12

RP3, 22ꢁ

11

RP3, 22ꢁ

10

RP3, 22ꢁ

BD15

3

2

BD14

BD13

BD12

BD11

BD10

BD09

BD08

BD07

BD06

BD05

5

3

7

4

9

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

5

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

6

7

8

9

RP4, 22ꢁ

16

RP4, 22ꢁ

15

RP4, 22ꢁ

14

RP4, 22ꢁ

13

RP4, 22ꢁ

12

RP4, 22ꢁ

11

RP4, 22ꢁ

10

RP4, 22ꢁ

1

2

3

4

BD04

BD03

5

6

BD02

BD01

BD00

7

8

9

RP4, 22ꢁ

1

2

3

4

5

6

7

8

9

10

1

2

3

4

5

6

7

8

9

10

RP11

50ꢁ

RP10

R1 R2 R3 R4 R5 R6 R7 R8 R9

RCON

DNP

DVDD

C43

C44

C50

0.1ꢄF

C51

0.1ꢄF

4.7ꢄF

RIBBON

J2

6.3V

R50

9kꢁ

1

2

12

13

U5

AGND; 7

DVDD; 14

AGND; 7

DVDD; 14

74AC14

SPI PORT

P1

R48

9kꢁ

4

3

10

11

U5

1

2

3

4

5

6

AGND; 7

DVDD; 14

AGND; 7

DVDD; 14

74AC14

R45

9kꢁ

6

5

8

9

SPCSB

U5

AGND; 7

DVDD; 14

AGND; 7

DVDD; 14

74AC14

SPCLK

SPSDI

2

1

12

13

SPSDO

U6

AGND; 7

DVDD; 14

AGND; 7

DVDD; 14

74AC14

4

10

3

11

U6

AGND; 7

DVDD; 14

AGND; 7

DVDD; 14

74AC14

6

8

5

9

U6

AGND; 7

DVDD; 14

AGND; 7

DVDD; 14

74AC14

Figure 62. AD9777 Evaluation Board Input (B Channel) and SPI Port Circuitry

–44–

REV. 0

AD9777

Figure 63. AD9777 Evaluation Board Components, Top Side

Figure 64. AD9777 Evaluation Board Components, Bottom Side

REV. 0

–45–

AD9777

Figure 65. AD9777 Evaluation Board Layout, Layer One (Top)

Figure 66. AD9777 Evaluation Board Layout, Layer Two (Ground Plane)

–46–

REV. 0

AD9777

Figure 67. AD9777 Evaluation Board Layout, Layer Three (Power Plane)

Figure 68. AD9777 Evaluation Board Layout, Layer Four (Bottom)

REV. 0

–47–

AD9777

OUTLINE DIMENSIONS

80-Lead, Thermally Enhanced, Thin Plastic Quad Flatpack [TQFP]

(SV-80)

Dimensions shown in millimeters and (inches)

14.00 (0.5512) SQ

12.00 (0.4724) SQ

1.20 (0.0472)

MAX

0.75 (0.0295)

0.60 (0.0236)

0.45 (0.0177)

80

61

60

1

SEATING

PLANE

PIN 1

TOP VIEW

(PINS DOWN)

BOTTOM

VIEW

6.00 (0.2362) SQ

20

41

20

41

COPLANARITY

0.15 (0.0059)

0.05 (0.0020)

21

40

21

1.05 (0.0413)

1.00 (0.0394)

0.95 (0.0374)

0.20 (0.0079)

0.09 (0.0035)

GAGE PLANE

0.25 (0.0098)

0.27 (0.0106)

0.22 (0.0087)

0.17 (0.0067)

7ꢂ

3.5ꢂ

0ꢂ

0.50 (0.0197)

BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-026-ADD

AN APPLICATION NOTE DETAILING THE THERMALLY ENHANCED TQFP

CAN BE FOUND AT;

www.amkor.com/products/notes_papers/MLF_Appnote_0301.pdf

–48–

REV. 0


型号：	AD9777BSV
厂家：	ADI
描述：	16-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter 16位， 160 MSPS 2X / 4X / 8X插双通道TxDAC + D / A转换器转换器数模转换器
文件：	总48页 (文件大小：5676K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9777BSV [ADI]

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