AD9779BSVZRL1 [ADI]
Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters; 双12位/ 14位/ 16位， 1 GSPS ，数字 - 模拟转换器
| 型号： | AD9779BSVZRL1 |
| 厂家： | 
ADI |
| 描述： | Dual 12-/14-/16-Bit, 1 GSPS, Digital-to-Analog Converters |
| 文件： | 总56页 (文件大小：1532K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 12-/14-/16-Bit,
1 GSPS, Digital-to-Analog Converters
AD9776/AD9778/AD9779
FEATURES
GENERAL DESCRIPTION
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
SFDR = 78 dBc to fOUT = 100 MHz
Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high
dynamic range, digital-to-analog converters (DACs) that pro-
vide a sample rate of 1 GSPS, permitting multicarrier generation
up to the Nyquist frequency. They include features optimized
for direct conversion transmit applications, including complex
digital modulation, and gain and offset compensation. The DAC
outputs are optimized to interface seamlessly with analog quad-
rature modulators such as the AD8349. A serial peripheral interface
(SPI®) provides for programming/readback of many internal
parameters. Full-scale output current can be programmed over a
range of 10 mA to 30 mA. The devices are manufactured on an
advanced 0.18 μm CMOS process and operate on 1.8 V and
3.3 V supplies for a total power consumption of 1.0 W. They are
enclosed in 100-lead TQFP packages.
100-lead, exposed paddle TQFP package
APPLICATIONS
Wireless infrastructure
WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
Wideband communications: LMDS/MMDS, point-to-point
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. CMOS data input interface with adjustable set up and hold.
5. Novel 2×, 4×, and 8× interpolator/coarse complex
modulator allows carrier placement anywhere in DAC
bandwidth.
TYPICAL SIGNAL CHAIN
QUADRATURE
MODULATOR/
MIXER/
COMPLEX I AND Q
AMPLIFIER
LO
DC
DC
DIGITAL INTERPOLATION FILTERS
I DAC
POST DAC
ANALOG FILTER
FPGA/ASIC/DSP
Q DAC
A
AD9779
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
AD9776/AD9778/AD9779
TABLE OF CONTENTS
Features .............................................................................................. 1
SPI Register Map ............................................................................ 27
Interpolation Filter Architecture.................................................. 31
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 6
Digital Input Data Timing Specifications ................................. 7
AC Specifications.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 24
Theory of Operation ...................................................................... 25
Serial Peripheral Interface......................................................... 25
MSB/LSB Transfers..................................................................... 26
Interpolation Filter Minimum and Maximum Bandwidth
Specifications .............................................................................. 35
Driving the REFCLK Input....................................................... 35
Internal PLL Clock Multiplier/Clock Distribution................ 36
Full-Scale Current Generation ................................................. 38
Power Dissipation....................................................................... 39
Power-Down and Sleep Modes................................................. 41
Interleaved Data Mode .............................................................. 41
Timing Information................................................................... 41
Synchronization of Input Data to DATACLK
Output (Pin 37)........................................................................... 43
Synchronization of Input Data to the REFCLK Input (Pin 5
and Pin 6) with PLL Enabled or Disabled............................... 43
Evaluation Board Operation ......................................................... 46
Modifying the Evaluation Board to Use the AD8349 On-
Board Quadrature Modulator................................................... 48
Evaluation Board Schematics ................................................... 49
Outline Dimensions....................................................................... 56
Ordering Guide .......................................................................... 56
REVISION HISTORY
Added Table 19, Renumbered Tables Sequentially.................... 41
Changes to Figure 92 and Figure 93............................................. 42
Changes to Figure 94...................................................................... 42
Added New Figure 95, Renumbered Figures Sequentially ....... 42
Changes to Synchronization of Input Data to the REFCLK Input
(Pin 5 and Pin 6) with PLL Enabled or Disabled Section......... 43
3/07—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to General Product Highlights........................................ 1
Added Figure 1, Renumbered Figures Sequentially..................... 1
Changes to Table 1............................................................................ 4
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 5
Changes to Figure 53 and Figure 54............................................. 26
Changes to Table 12........................................................................ 29
Changes to Power Dissipation Section ........................................ 39
Added New Figure 96, Renumbered Figures Sequentially ....... 43
Changes to Figure 106 ................................................................... 51
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 56
AD9776/AD9778/AD9779
FUNCTIONAL BLOCK DIAGRAM
DELAY
LINE
SYNC_O
SYNC_I
CLOCK GENERATION/DISTRIBUTION
CLOCK
MULTIPLIER
2×/4×/8×
CLK+
CLK–
DELAY
DATACLK_OUT
LINE
DATA
1
ASSEMBLER
SYNC
IOUT1_P
IOUT1_N
16-BIT
IDAC
I
P1D(15:0)
LATCH
2×
2×
2×
2×
2×
2×
n × fDAC/8
n = 0, 1, 2 ... 7
Q
IOUT2_P
IOUT2_N
16-BIT
QDAC
LATCH
P2D(15:0)
1
SYNC
VREF
I120
DIGITAL CONTROLLER
10
10
GAIN
GAIN
SERIAL
PERIPHERAL
INTERFACE
POWER-ON
RESET
10
10
AUX1_P
AUX1_N
GAIN
GAIN
AUX2_P
AUX2_N
Figure 2. Functional Block Diagram
Rev. A | Page 3 of 56
AD9776/AD9778/AD9779
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, IOUTF = 20 mA, maximum sample rate, unless
S
otherwise noted.
Table 1. AD9776, AD9778, and AD9779 DC Specifications
AD9776
Typ
AD9778
Typ
AD9779
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
RESOLUTION
12
14
16
Bits
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal
Reference)
±±.1
±±.6
±±.65
±1
±2.1
±3.ꢀ
LSB
LSB
−±.±±1
±
±2
+±.±±1
−±.±±1
±
±2
+±.±±1
−±.±±1
±
±2
+±.±±1 % FSR
% FSR
Full-Scale Output Current1
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
MAIN DAC TEMPERATURE DRIFT
Offset
8.66
−1.±
2±.2
31.66
+1.±
8.66
−1.±
2±.2
31.66
+1.±
8.66
−1.±
2±.2
31.66
+1.±
mA
V
MΩ
1±
1±
1±
Guaranteed
Guaranteed
Guaranteed
±.±4
1±±
3±
±.±4
1±±
3±
±.±4
1±±
3±
ppm/°C
ppm/°C
ppm/°C
Gain
Reference Voltage
AUX DAC OUTPUTS
Resolution
Full-Scale Output Current1
Output Compliance Range
(Source)
1±
1±
1±
Bits
−1.998
±
+1.998
1.6
−1.998
±
+1.998
1.6
−1.998
±
+1.998 mA
1.6
V
Output Compliance Range
(Sink)
±.8
1.6
±.8
1.6
±.8
1.6
V
Output Resistance
1
1
1
MΩ
Aux DAC Monotonicity
Guaranteed
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
1.2
5
1.2
5
1.2
5
V
kΩ
3.13
1.ꢀ±
3.3
1.8
3.4ꢀ
1.9±
3.13
1.ꢀ±
3.3
1.8
3.4ꢀ
1.9±
3.13
1.ꢀ±
3.3
1.8
3.4ꢀ
1.9±
V
V
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
3.13
1.ꢀ±
3.3
1.8
3.4ꢀ
1.9±
3.13
1.ꢀ±
3.3
1.8
3.4ꢀ
1.9±
3.13
1.ꢀ±
3.3
1.8
3.4ꢀ
1.9±
V
V
POWER CONSUMPTION
1× Mode, fDAC = 1±± MSPS,
IF = 1 MHz
2× Mode, fDAC = 32± MSPS,
IF = 16 MHz, PLL Off
2× Mode, fDAC = 32± MSPS,
IF = 16 MHz, PLL On
4× Mode, fDAC/4 Modulation,
25±
498
588
5ꢀ2
3±±
25±
498
588
5ꢀ2
3±±
25±
498
588
5ꢀ2
3±±
mW
mW
mW
mW
f
DAC = 5±± MSPS,
IF = 13ꢀ.5 MHz, Q DAC Off
Rev. A | Page 4 of 56
AD9776/AD9778/AD9779
AD9776
Typ
AD9778
Typ
AD9779
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
8× Mode, fDAC/4 Modulation,
fDAC = 1 GSPS, IF = 262.5 MHz
98±
98±
98±
mW
Power-Down Mode
2
3.ꢀ
2
3.ꢀ
2
3.ꢀ
mW
Power Supply Rejection Ratio,
AVDD33
−±.3
−4±
+±.3
−±.3
−4±
+±.3
−±.3
−4±
+±.3
% FSR/V
OPERATING RANGE
+25
+85
+25
+85
+25
+85
°C
1 Based on a 1± kΩ external resistor.
Rev. A | Page 5 of 56
AD9776/AD9778/AD9779
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTF = 20 mA, maximum sample rate, unless
S
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2. AD9776, AD9778, and AD9779 Digital Specifications
Parameter
Conditions
Min
Typ Max
Unit
CMOS INPUT LOGIC LEVEL
Input VIN Logic High
Input VIN Logic Low
2.±
V
V
±.8
Maximum Input Data Rate at Interpolation
1×
2×
4×
8×
3±±
25±
2±±
125
MSPS
MSPS
MSPS
MSPS
CMOS OUTPUT LOGIC LEVEL (DATACLK, PIN 3ꢀ)1
Output VOUT Logic High
Output VOUT Logic Low
LVDS RECEIVER INPUTS (SYNC_I+, SYNC_I−)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
2.4
V
V
±.4
SYNC_I+ = VIA, SYNC_I− = VIB
825
−1±±
15ꢀ5 mV
+1±± mV
mV
2±
2
Receiver Differential Input Impedance, RIN
LVDS Input Rate
8±
12±
125
Ω
MSPS
ns
Set-Up Time, SYNC_I to DAC Clock
Hold Time, SYNC_I to DAC Clock
LVDS DRIVER OUTPUTS (SYNC_O+, SYNC_O−)
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
−±.2
1
ns
SYNC_O+ = VOA, SYNC_O− = VOB, 1±± Ω termination
825
1±25
15±
115±
8±
15ꢀ5 mV
mV
mV
125± mV
Output Differential Voltage, |VOD
Output Offset Voltage, VOS
Output Impedance, RO
|
2±± 25±
Single-ended
1±± 12±
Ω
Maximum Clock Rate
1
GHz
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage (CLK+, CLK−)3
Common-Mode Voltage
Maximum Clock Rate4
4±±
3±±
1
8±± 2±±± mV
4±± 5±±
mV
GSPS
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
4±
MHz
ns
ns
12.5
12.5
1 Specification is at a DATACLK frequency of 1±± MHz into a 1 kΩ load; maximum drive capability of 8 mA. At higher speeds or greater loads, best practice suggests
using an external buffer for this signal.
2 Guaranteed at 25°C. Can drift above 12± ꢀ at temperatures above 25°C.
3 When using the PLL, a differential swing of 2 V p-p is recommended.
4 Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.
Rev. A | Page 6 of 56
AD9776/AD9778/AD9779
DIGITAL INPUT DATA TIMING SPECIFICATIONS
Table 3. AD9776, AD9778, and AD9779 Digital Input Data Timing Specifications
Parameter
Min
Typ
Max
Unit
INPUT DATA (ALL MODES, −4±°C to +85°C)1
Set-Up Time, Input Data to DATACLK
Hold Time, Input Data to DATACLK
Set-Up Time, Input Data to REFCLK
Hold Time, Input Data to REFCLK
+2.5
−±.4
−±.8
+2.9
ns
ns
ns
ns
1 Timing vs. temperature and data valid keep out windows are delineated in Table 19.
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTF = 20 mA, maximum sample rate, unless
S
otherwise noted.
Table 4. AD9776, AD9778, and AD9779 AC Specifications
AD9776
Typ
AD9778
Max Min Typ
AD9779
Min Typ
Parameter
Min
Max
Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 1±± MSPS, fOUT = 2± MHz
fDAC = 2±± MSPS, fOUT = 5± MHz
fDAC = 4±± MSPS, fOUT = ꢀ± MHz
fDAC = 8±± MSPS, fOUT = ꢀ± MHz
82
81
8±
85
82
81
8±
85
82
82
8±
8ꢀ
dBc
dBc
dBc
dBc
TWO-TONE INTERMODULATION DISTORTION
(IMD)
fDAC = 2±± MSPS, fOUT = 5± MHz
fDAC = 4±± MSPS, fOUT = 6± MHz
fDAC = 4±± MSPS, fOUT = 8± MHz
fDAC = 8±± MSPS, fOUT = 1±± MHz
8ꢀ
8±
ꢀ5
ꢀ5
8ꢀ
85
81
8±
91
85
81
81
dBc
dBc
dBc
dBc
NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE,
5±± kHz TONE SPACING
fDAC = 2±± MSPS, fOUT = 8± MHz
fDAC = 4±± MSPS, fOUT = 8± MHz
fDAC = 8±± MSPS, fOUT = 8± MHz
−152
−155
−15ꢀ.5
−155
−159
−16±
−158
−16±
−161
dBm/Hz
dBm/Hz
dBm/Hz
WCDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 1±± MHz
fDAC = 491.52 MSPS, fOUT = 2±± MHz
ꢀ6
69
ꢀ8
ꢀ3
ꢀ9
ꢀ4
dBc
dBc
WCDMA SECOND ADJACENT CHANNEL
LEAKAGE RATIO (ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 1±± MHz
fDAC = 491.52 MSPS, fOUT = 2±± MHz
ꢀꢀ.5
ꢀ6
8±
ꢀ8
81
ꢀ8
dBc
dBc
Rev. A | Page ꢀ of 56
AD9776/AD9778/AD9779
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
With
Respect
To
Parameter
Rating
AVDD33, DVDD33
AGND,
DGND,
CGND
−±.3 V to +3.6 V
DVDD18, CVDD18
AGND,
DGND,
CGND
−±.3 V to +1.98 V
THERMAL RESISTANCE
AGND
DGND,
CGND
AGND,
CGND
AGND,
DGND
AGND
AGND
−±.3 V to +±.3 V
−±.3 V to +±.3 V
−±.3 V to +±.3 V
100-lead, thermally enhanced TQFP_EP package, θJA = 19.1°C/W
with the bottom EPAD soldered to the PCB. With the bottom
EPAD not soldered to the PCB, θJA = 27.4°C/W. These
specifications are valid with no airflow movement.
DGND
CGND
ESD CAUTION
I12±, VREF, IPTAT
−±.3 V to AVDD33 + ±.3 V
−1.± V to AVDD33 + ±.3 V
IOUT1-P, IOUT1-N, IOUT2-P
IOUT2-N, Aux1-P, Aux1-N
Aux2-P, Aux2-N
,
,
P1D15 to P1D±,
P2D15 to P2D±
DGND
−±.3 V to DVDD33 + ±.3 V
DATACLK, TXENABLE
CLK+, CLK−
RESET, IRQ, PLL_LOCK, DGND
SYNC_O+, SYNC_O−,
SYNC_I+, SYNC_I−,
DGND
CGND
−±.3 V to DVDD33 + ±.3 V
−±.3 V to CVDD18 + ±.3 V
−±.3 V to DVDD33 + ±.3 V
CSB, SCLK, SDIO, SDO
JunctionTemperature
+125°C
Storage Temperature
Range
−65°C to +15±°C
Rev. A | Page 8 of 56
AD9776/AD9778/AD9779
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CVDD18
I120
PIN 1
2
CVDD18
VREF
3
CGND
CGND
IPTAT
AGND
IRQ
ANALOG DOMAIN
DIGITAL DOMAIN
4
5
CLK+
6
CLK–
RESET
CSB
7
CGND
8
CGND
SCLK
SDIO
9
CVDD18
CVDD18
CGND
AD9776
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDO
PLL_LOCK
DGND
SYNC_O+
SYNC_O–
DVDD33
DVDD18
NC
AGND
SYNC_I+
SYNC_I–
DGND
DVDD18
P1D<11>
P1D<10>
P1D<9>
P1D<8>
P1D<7>
DGND
NC
NC
NC
P2D<0>
DGND
DVDD18
P2D<1>
P2D<2>
DVDD18
P1D<6>
P1D<5>
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
Figure 3. AD9776 Pin Configuration
Table 6. AD9776 Pin Function Descriptions
Pin
Pin
No. Mnemonic Description
No. Mnemonic Description
1
2
3
4
5
6
ꢀ
8
CVDD18
CVDD18
CGND
1.8 V Clock Supply.
1.8 V Clock Supply.
Clock Common.
Clock Common.
Differential Clock Input.
Differential Clock Input.
Clock Common.
Clock Common.
1.8 V Clock Supply.
1.8 V Clock Supply.
Clock Common.
Analog Common.
Differential Synchronization Input.
Differential Synchronization Input.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D11 (MSB).
Port 1, Data Input D1±.
Port 1, Data Input D9.
2±
21
22
23
24
25
26
2ꢀ
28
29
3±
31
32
33
34
35
36
3ꢀ
38
P1D<8>
P1D<ꢀ>
DGND
Port 1, Data Input D8.
Port 1, Data Input Dꢀ.
Digital Common.
CGND
DVDD18
P1D<6>
P1D<5>
P1D<4>
P1D<3>
P1D<2>
P1D<1>
P1D<±>
NC
DGND
DVDD18
NC
NC
NC
1.8 V Digital Supply.
Port 1, Data Input D6.
Port 1, Data Input D5.
Port 1, Data Input D4.
Port 1, Data Input D3.
Port 1, Data Input D2.
Port 1, Data Input D1.
Port 1, Data Input D± (LSB).
No Connect.
Digital Common.
1.8 V Digital Supply.
No Connect.
No Connect.
No Connect.
CLK+1
CLK−1
CGND
CGND
CVDD18
CVDD18
CGND
9
1±
11
12
13
14
15
16
1ꢀ
18
19
AGND
SYNC_I+
SYNC_I−
DGND
DVDD18
P1D<11>
P1D<1±>
P1D<9>
DATACLK
DVDD33
Data Clock Output.
3.3 V Digital Supply.
Rev. A | Page 9 of 56
AD9776/AD9778/AD9779
Pin
Pin
No. Mnemonic Description
No. Mnemonic Description
39
4±
41
42
43
44
45
46
4ꢀ
48
49
5±
51
52
53
54
55
56
5ꢀ
58
59
6±
61
62
63
64
65
66
6ꢀ
68
69
ꢀ±
ꢀ1
ꢀ2
TXENABLE
P2D<11>
P2D<1±>
P2D<9>
DVDD18
DGND
P2D<8>
P2D<ꢀ>
P2D<6>
P2D<5>
P2D<4>
P2D<3>
P2D<2>
P2D<1>
DVDD18
DGND
P2D<±>
NC
NC
NC
NC
DVDD18
DVDD33
SYNC_O−
SYNC_O+
DGND
PLL_LOCK
SDO
SDIO
Transmit Enable.
ꢀ3
IPTAT
Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 1± μA at 25°C with
approximately 2± nA/°C slope. This pin
should remain floating.
Voltage Reference Output.
12± μA Reference Current.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Port 2, Data Input D11 (MSB).
Port 2, Data Input D1±.
Port 2, Data Input D9.
1.8 V Digital Supply.
Digital Common.
Port 2, Data Input D8.
Port 2, Data Input Dꢀ.
Port 2, Data Input D6.
Port 2, Data Input D5.
Port 2, Data Input D4.
Port 2, Data Input D3.
Port 2, Data Input D2.
Port 2, Data Input D1.
1.8 V Digital Supply.
Digital Common.
Port 2, Data Input D± (LSB).
No Connect.
No Connect.
No Connect.
No Connect.
1.8 V Digital Supply.
3.3 V Digital Supply.
Differential Synchronization Output.
Differential Synchronization Output
Digital Common
ꢀ4
ꢀ5
ꢀ6
ꢀꢀ
ꢀ8
ꢀ9
8±
81
82
83
84
85
86
8ꢀ
88
89
9±
91
92
93
94
95
96
9ꢀ
98
99
VREF
I12±
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
AGND
OUT2_P
OUT2_N
AGND
AUX2_P
AUX2_N
AGND
AUX1_N
AUX1_P
AGND
OUT1_N
OUT1_P
AGND
AGND
AVDD33
AGND
Analog Common.
Analog Common.
Differential DAC Current Output, Channel 2.
Differential DAC Current Output, Channel 2.
Analog Common.
Auxiliary DAC Current Output, Channel 2.
Auxiliary DAC Current Output, Channel 2.
Analog Common.
Auxiliary DAC Current Output, Channel 1.
Auxiliary DAC Current Output, Channel 1.
Analog Common.
Differential DAC Current Output, Channel 1.
Differential DAC Current Output, Channel 1.
Analog Common.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
PLL Lock Indicator
SPI Port Data Output
SPI Port Data Input/Output
SPI Port Clock
SPI Port Chip Select Bar.
Reset, Active High.
AVDD33
AGND
SCLK
CSB
RESET
IRQ
1±± AVDD33
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as REFCLK.
Interrupt Request.
Analog Common.
AGND
Rev. A | Page 1± of 56
AD9776/AD9778/AD9779
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CVDD18
CVDD18
CGND
I120
PIN 1
2
VREF
3
IPTAT
AGND
IRQ
ANALOG DOMAIN
DIGITAL DOMAIN
4
CGND
5
CLK+
6
CLK–
RESET
CSB
7
CGND
8
CGND
SCLK
9
CVDD18
CVDD18
CGND
SDIO
AD9778
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDO
PLL_LOCK
DGND
SYNC_O+
SYNC_O–
DVDD33
DVDD18
NC
AGND
SYNC_I+
SYNC_I–
DGND
DVDD18
P1D<13>
P1D<12>
P1D<11>
P1D<10>
P1D<9>
DGND
NC
P2D<0>
P2D<1>
P2D<2>
DGND
DVDD18
P2D<3>
P2D<4>
DVDD18
P1D<8>
P1D<7>
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
Figure 4. AD9778 Pin Configuration
Table 7. AD9778 Pin Function Description
Pin
No.
Pin
No.
Mnemonic
CVDD18
CVDD18
CGND
Description
Mnemonic
P1D<9>
DGND
Description
1
2
3
4
5
6
ꢀ
8
1.8 V Clock Supply.
1.8 V Clock Supply.
Clock Common.
Clock Common.
Differential Clock Input.
Differential Clock Input.
Clock Common.
Clock Common.
1.8 V Clock Supply.
21
22
23
24
25
26
2ꢀ
28
29
3±
31
32
33
34
35
36
Port 1, Data Input D9.
Digital Common.
DVDD18
P1D<8>
P1D<ꢀ>
P1D<6>
P1D<5>
P1D<4>
P1D<3>
P1D<2>
P1D<1>
DGND
1.8 V Digital Supply.
Port 1, Data Input D8.
Port 1, Data Input Dꢀ.
Port 1, Data Input D6.
Port 1, Data Input D5.
Port 1, Data Input D4.
Port 1, Data Input D3.
Port 1, Data Input D2.
Port 1, Data Input D1.
Digital Common.
CGND
CLK+1
CLK−1
CGND
CGND
CVDD18
CVDD18
CGND
9
1±
11
12
13
14
15
16
1ꢀ
18
19
2±
1.8 V Clock Supply.
Clock Common.
Analog Common.
AGND
SYNC_I+
SYNC_I−
DGND
DVDD18
P1D<13>
P1D<12>
P1D<11>
P1D<1±>
Differential Synchronization Input.
Differential Synchronization Input.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D13 (MSB).
Port 1, Data Input D12.
Port 1, Data Input D11.
Port 1, Data Input D1±.
DVDD18
P1D<±>
NC
1.8 V Digital Supply.
Port 1, Data Input D± (LSB).
No Connect.
NC
No Connect.
DATACLK
DVDD33
TXENABLE
P2D<13>
3ꢀ
38
39
4±
Data Clock Output.
3.3 V Digital Supply.
Transmit Enable.
Port 2, Data Input D13 (MSB).
Rev. A | Page 11 of 56
AD9776/AD9778/AD9779
Pin
Pin
No.
No.
41
42
43
44
45
46
4ꢀ
48
49
5±
51
52
53
54
55
56
5ꢀ
58
59
6±
61
62
63
64
65
66
6ꢀ
68
69
ꢀ±
ꢀ1
ꢀ2
ꢀ3
Mnemonic
P2D<12>
P2D<11>
DVDD18
DGND
P2D<1±>
P2D<9>
P2D<8>
P2D<ꢀ>
P2D<6>
P2D<5>
P2D<4>
P2D<3>
DVDD18
DGND
Description
Mnemonic
VREF
I12±
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
AGND
Description
Port 2, Data Input D12.
Port 2, Data Input D11.
1.8 V Digital Supply.
Digital Common.
ꢀ4
ꢀ5
ꢀ6
ꢀꢀ
ꢀ8
ꢀ9
8±
81
82
83
Voltage Reference Output.
12± μA Reference Current.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
Analog Common.
Differential DAC Current Output,
Channel 2.
Differential DAC Current Output,
Channel 2.
Analog Common.
Auxiliary DAC Current Output,
Channel 2.
Auxiliary DAC Current Output,
Channel 2.
Analog Common.
Auxiliary DAC Current Output,
Channel 1.
Auxiliary DAC Current Output,
Channel 1.
Analog Common.
Differential DAC Current Output,
Channel 1.
Differential DAC Current Output,
Channel 1.
Port 2, Data Input D1±.
Port 2, Data Input D9.
Port 2, Data Input D8.
Port 2, Data Input Dꢀ.
Port 2, Data Input D6.
Port 2, Data Input D5.
Port 2, Data Input D4.
Port 2, Data Input D3.
1.8 V Digital Supply.
Digital Common.
OUT2_P
84
OUT2_N
85
86
AGND
AUX2_P
P2D<2>
P2D<1>
P2D<±>
NC
Port 2, Data Input D2.
Port 2, Data Input D1.
Port 2, Data Input D± (LSB).
No Connect.
8ꢀ
AUX2_N
88
89
AGND
AUX1_N
NC
No Connect.
DVDD18
DVDD33
SYNC_O−
SYNC_O+
DGND
PLL_LOCK
SDO
SDIO
SCLK
CSB
RESET
IRQ
1.8 V Digital Supply.
3.3 V Digital Supply.
Differential Synchronization Output.
Differential Synchronization Output.
Digital Common.
9±
AUX1_P
91
92
AGND
OUT1_N
PLL Lock Indicator.
93
OUT1_P
SPI Port Data Output.
SPI Port Data Input/Output.
SPI Port Clock.
SPI Port Chip Select Bar.
Reset, Active High.
Interrupt Request.
Analog Common.
Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 1± μA at 25°C with
approximately 2± nA/°C slope. This
pin should remain floating.
94
95
96
9ꢀ
98
99
1±±
AGND
AGND
AVDD33
AGND
AVDD33
AGND
Analog Common.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
AGND
IPTAT
AVDD33
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as REFCLK.
Rev. A | Page 12 of 56
AD9776/AD9778/AD9779
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
CVDD18
CVDD18
CGND
I120
PIN 1
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VREF
3
IPTAT
ANALOG DOMAIN
4
CGND
AGND
5
CLK+
IRQ
6
CLK–
DIGITAL DOMAIN
RESET
CSB
7
CGND
8
CGND
SCLK
9
CVDD18
CVDD18
CGND
SDIO
AD9779
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDO
PLL_LOCK
DGND
AGND
SYNC_I+
SYNC_I–
DGND
SYNC_O+
SYNC_O–
DVDD33
DVDD18
P2D<0>
P2D<1>
P2D<2>
P2D<3>
P2D<4>
DGND
DVDD18
P1D<15>
P1D<14>
P1D<13>
P1D<12>
P1D<11>
DGND
DVDD18
P1D<10>
P1D<9>
DVDD18
P2D<5>
P2D<6>
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Figure 5. AD9779 Pin Configuration
Table 8. AD9779 Pin Function Descriptions
Pin
No.
Pin
No.
Mnemonic
CVDD18
CVDD18
CGND
Description
Mnemonic
DGND
Description
1
2
3
4
5
6
ꢀ
8
1.8 V Clock Supply.
1.8 V Clock Supply.
Clock Common.
Clock Common.
Differential Clock Input.
Differential Clock Input.
Clock Common.
Clock Common.
1.8 V Clock Supply.
22
23
24
25
26
2ꢀ
28
29
3±
31
32
33
34
35
36
3ꢀ
38
39
4±
41
42
Digital Common.
DVDD18
P1D<1±>
P1D<9>
P1D<8>
P1D<ꢀ>
P1D<6>
P1D<5>
P1D<4>
P1D<3>
DGND
DVDD18
P1D<2>
P1D<1>
P1D<±>
DATACLK
DVDD33
TXENABLE
P2D<15>
P2D<14>
P2D<13>
1.8 V Digital Supply.
Port 1, Data Input D1±.
Port 1, Data Input D9.
Port 1, Data Input D8.
Port 1, Data Input Dꢀ.
Port 1, Data Input D6.
Port 1, Data Input D5.
Port 1, Data Input D4.
Port 1, Data Input D3.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D2.
Port 1, Data Input D1.
Port 1, Data Input D± (LSB).
Data Clock Output.
3.3 V Digital Supply.
Transmit Enable.
CGND
CLK+1
CLK−1
CGND
CGND
CVDD18
CVDD18
CGND
9
1±
11
12
13
14
15
16
1ꢀ
18
19
2±
21
1.8 V Clock Supply.
Clock Common.
Analog Common.
AGND
SYNC_I+
SYNC_I−
DGND
DVDD18
P1D<15>
P1D<14>
P1D<13>
P1D<12>
P1D<11>
Differential Synchronization Input.
Differential Synchronization Input.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D15 (MSB).
Port 1, Data Input D14.
Port 1, Data Input D13.
Port 1, Data Input D12.
Port 1, Data Input D11.
Port 2, Data Input D15 (MSB).
Port 2, Data Input D14.
Port 2, Data Input D13.
Rev. A | Page 13 of 56
AD9776/AD9778/AD9779
Pin
Pin
No.
No.
43
44
45
46
4ꢀ
48
49
5±
51
52
53
54
55
56
5ꢀ
58
59
6±
61
62
63
64
65
66
6ꢀ
68
69
ꢀ±
ꢀ1
ꢀ2
ꢀ3
Mnemonic
DVDD18
DGND
Description
Mnemonic
VREF
I12±
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
AGND
Description
1.8 V Digital Supply.
Digital Common.
ꢀ4
ꢀ5
ꢀ6
ꢀꢀ
ꢀ8
ꢀ9
8±
81
82
83
Voltage Reference Output.
12± μA Reference Current.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
Analog Common.
P2D<12>
P2D<11>
P2D<1±>
P2D<9>
P2D<8>
P2D<ꢀ>
P2D<6>
P2D<5>
DVDD18
DGND
P2D<4>
P2D<3>
P2D<2>
P2D<1>
P2D<±>
DVDD18
DVDD33
SYNC_O−
SYNC_O+
DGND
PLL_LOCK
SPI_SDO
SPI_SDIO
SCLK
SPI_CSB
RESET
IRQ
AGND
IPTAT
Port 2, Data Input D12.
Port 2, Data Input D11.
Port 2, Data Input D1±.
Port 2, Data Input D9.
Port 2, Data Input D8.
Port 2, Data Input Dꢀ.
Port 2, Data Input D6.
Port 2, Data Input D5.
1.8 V Digital Supply.
Digital Common.
Port 2, Data Input D4.
Port 2, Data Input D3.
Port 2, Data Input D2.
Port 2, Data Input D1.
Port 2, Data Input D± (LSB).
1.8 V Digital Supply.
3.3 V Digital Supply.
Differential Synchronization Output.
Differential Synchronization Output.
Digital Common.
OUT2_P
Differential DAC Current Output,
Channel 2.
Differential DAC Current Output,
Channel 2.
84
OUT2_N
85
86
8ꢀ
88
89
9±
91
92
AGND
Analog Common.
AUX2_P
AUX2_N
AGND
AUX1_N
AUX1_P
AGND
Auxiliary DAC Current Output, Channel 2.
Auxiliary DAC Current Output, Channel 2.
Analog Common.
Auxiliary DAC Current Output, Channel 1.
Auxiliary DAC Current Output, Channel 1.
Analog Common.
Differential DAC Current Output,
Channel 1.
Differential DAC Current Output,
Channel 1.
Analog Common.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
Analog Common.
3.3 V Analog Supply.
OUT1_N
93
OUT1_P
PLL Lock Indicator.
SPI Port Data Output.
SPI Port Data Input/Output.
SPI Port Clock.
SPI Port Chip Select Bar.
Reset, Active High.
Interrupt Request.
Analog Common.
Factory Test Pin. Output current is
proportional to absolute temperature,
approximately 1± μA at 25°C with
approximately 2± nA/°C slope. This pin
should remain floating.
94
95
96
9ꢀ
98
99
1±±
AGND
AGND
AVDD33
AGND
AVDD33
AGND
AVDD33
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as REFCLK.
Rev. A | Page 14 of 56
AD9776/AD9778/AD9779
TYPICAL PERFORMANCE CHARACTERISTICS
4
100
90
80
70
60
50
3
2
fDATA = 160MSPS
fDATA = 200MSPS
1
0
–1
–2
–3
–4
–5
–6
fDATA = 250MSPS
0
10k
20k
30k
CODE
40k
50k
60k
0
20
40
60
80
100
fOUT (MHz)
Figure 6. AD9779 Typical INL
Figure 9. AD9779 In-Band SFDR vs. fOUT, 2× Interpolation
100
1.5
1.0
fDATA = 200MSPS
fDATA = 100MSPS
90
80
70
60
50
0.5
0
fDATA = 150MSPS
–0.5
–1.0
–1.5
–2.0
0
20
40
60
80
100
0
10k
20k
30k
CODE
40k
50k
60k
fOUT (MHz)
Figure 10. AD9779 In-Band SFDR vs. fOUT, 4× Interpolation
Figure 7. AD9779 Typical DNL
100
90
80
70
60
50
100
fDATA = 100MSPS
fDATA = 50MSPS
90
80
70
60
50
fDATA = 160MSPS
fDATA = 250MSPS
fDATA = 125MSPS
fDATA = 200MSPS
0
20
40
60
80
100
0
10
20
30
40
50
fOUT (MHz)
fOUT (MHz)
Figure 8. AD9779 In-Band SFDR vs. fOUT, 1x Interpolation
Figure 11. AD9779 In-Band SFDR vs. fOUT, 8× Interpolation
Rev. A | Page 15 of 56
AD9776/AD9778/AD9779
100
100
90
80
70
60
50
90
PLL OFF
fDATA = 160MSPS
80
PLL ON
fDATA = 200MSPS
70
60
50
fDATA = 250MSPS
0
20
40
60
80
100
0
10
20
fOUT (MHz)
30
40
80
80
fOUT (MHz)
Figure 12. AD9779 Out-of-Band SFDR vs. fOUT, 2× Interpolation
Figure 15. AD9779 In-Band SFDR, 4× Interpolation,
fDATA = 100 MSPS, PLL On/Off
100
100
90
80
70
60
50
0dBFS
–3dBFS
90
80
fDATA = 150MSPS
–6dBFS
70
fDATA = 100MSPS
60
fDATA = 200MSPS
50
0
20
40
60
80
100
0
20
40
60
fOUT (MHz)
fOUT (MHz)
Figure 13. AD9779 Out-of-Band SFDR vs. fOUT, 4× Interpolation
Figure 16. AD9779 In-Band SFDR vs. Digital Full-Scale Input
100
100
10mA
90
90
20mA
fDATA = 50MSPS
80
70
60
50
80
fDATA = 100MSPS
70
30mA
60
50
fDATA = 125MSPS
0
10
20
30
40
50
0
20
40
60
fOUT (MHz)
fOUT (MHz)
Figure 14. AD9779 Out-of-Band SFDR vs. fOUT, 8× Interpolation
Figure 17. AD9779 In-Band SFDR vs. Output Full-Scale Current
Rev. A | Page 16 of 56
AD9776/AD9778/AD9779
100
90
80
70
60
50
100
90
80
70
60
50
fDATA = 160MSPS
fDATA = 200MSPS
fDATA = 250MSPS
fDATA = 75MSPS
fDATA = 100MSPS
fDATA = 50MSPS
fDATA = 125MSPS
0
20
40
60
80
100
120
fOUT (MHz)
fOUT (MHz)
Figure 18. AD9779 Third-Order IMD vs. fOUT, 1× Interpolation
Figure 21. AD9779 Third-Order IMD vs. fOUT, 8× Interpolation
100
100
fDATA = 160MSPS
90
80
90
80
PLL OFF
fDATA = 200MSPS
70
60
50
70
PLL ON
fDATA = 250MSPS
60
50
0
20 40 60 80 100 120 140 160 180 200 220
fOUT (MHz)
0
20
40
60
80
100 120 140 160 180 200
fOUT (MHz)
Figure 19. AD9779 Third-Order IMD vs. fOUT, 2× Interpolation
Figure 22. AD9779 Third-Order IMD vs. fOUT, 4× Interpolation,
fDATA = 100 MSPS, PLL On vs. PLL Off
100
90
100
95
90
85
80
80
fDATA = 150MSPS
75
70
65
60
70
fDATA = 100MSPS
60
fDATA = 200MSPS
55
50
50
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
Figure 20. AD9779 Third-Order IMD vs. fOUT, 4× Interpolation
Figure 23. AD9779 Third-Order IMD vs. fOUT, over 50 Parts,4× Interpolation,
fDATA = 200 MSPS
Rev. A | Page 1ꢀ of 56
AD9776/AD9778/AD9779
100
95
REF 0dBm
*ATTEN 20dB
*PEAK
Log
10dB/
EXT REF
DC COUPLED
90
0dBFS
85
–3dBFS
80
75
LGAV
51
–6dBFS
70
65
60
55
50
S2
FC
AA
W1
S3
£(f):
FTUN
SWP
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
START 1.0MHz
*RES BW 20kHz
STOP 400.0MHz
VBW 20kHz
SWEEP 1.203s (601 pts)
Figure 24. IMD Performance vs. Digital Full-Scale Input, 4× Interpolation,
fDATA = 200 MSPS
Figure 27. AD9779 Two-Tone Spectrum, 4× Interpolation,
fDATA = 100 MSPS, fOUT = 30 MHz, 35 MHz
100
95
–142
–146
90
20mA
10mA
85
80
–150
–154
–158
–162
–3dBFS
75
0dBFS
30mA
70
65
60
55
50
–6dBFS
–166
–170
0
20
40
fOUT (MHz)
60
80
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
Figure 28. AD9779 Noise Spectral Density vs. Digital Full-Scale of Single-Tone
Input, fDATA = 200 MSPS, 2× Interpolation
Figure 25. IMD Performance vs. Full-Scale Output Current, 4× Interpolation,
fDATA = 200 MSPS
–150
REF 0dBm
*ATTEN 20dB
*PEAK
Log
10dB/
EXT REF
DC COUPLED
–154
fDAC = 400MSPS
–158
–162
–166
–170
fDAC = 200MSPS
LGAV
51
S2
FC
AA
W1
S3
fDAC = 800MSPS
£(f):
FTUN
SWP
0
20
40
60
80
100
START 1.0MHz
*RES BW 20kHz
STOP 400.0MHz
SWEEP 1.203s (601 pts)
fOUT (MHz)
VBW 20kHz
Figure 29. AD9779 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
Figure 26. AD9779 Single Tone, 4× Interpolation, fDATA = 100 MSPS,
fOUT = 30 MHz
Rev. A | Page 18 of 56
AD9776/AD9778/AD9779
–150
–154
–158
–162
–166
–170
–55
–60
–65
–70
–75
–80
–85
–90
fDAC = 200MSPS
fDAC = 400MSPS
0dBFS – PLL ON
–6dBFS
fDAC = 800MSPS
–3dBFS
0dBFS
0
20
40
60
80
100
0
20 40 60 80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
fOUT (MHz)
Figure 30. AD9779 Noise Spectral Density vs. fDAC
,
Figure 32. AD9779 ACLR for Second Adjacent Band WCDMA, 4×
Interpolation, fDATA = 122.88 MSPS. On-Chip Modulation Translates
Baseband Signal to IF
Single-Tone Input at −6 dBFS
–55
–60
–65
–70
–75
–80
–85
–90
–55
–60
–65
0dBFS – PLL ON
–3dBFS
–70
0dBFS
0dBFS – PLL ON
–75
–6dBFS
–6dBFS
–80
–3dBFS
–85
0dBFS
–90
0
20 40 60 80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
0
20 40 60 80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
Figure 31. AD9779 ACLR for First Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
Figure 33. AD9779 ACLR for Third Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
Rev. A | Page 19 of 56
AD9776/AD9778/AD9779
REF –25.28dBm
*ATTEN 4dB
1.5
1.0
*AVG
Log
10dB/
EXT REF
0.5
0
–0.5
–1.0
–1.5
PAVG
10
W1 S2
0
2k
4k
6k
8k
10k
CENTER 143.88MHz
*RES BW 30kHz
SPAN 50MHz
SWEEP 162.2ms (601 pts)
CODE
VBW 300kHz
LOWER
UPPER
RMS RESULTS FREQ OFFSET REF BW
dBc dBm
dBc dBm
CARRIER POWER 5.000MHz
3.840MHz –76.75 –89.23 –77.42 –89.91
3.840MHz –80.94 –93.43 –80.47 –92.96
3.840MHz –79.95 –92.44 –78.96 –91.45
–12.49dBm/
3.84000MHz
10.00MHz
15.00MHz
Figure 34. AD9779 WCDMA Signal, 4× Interpolation,
fDATA =122.88 MSPS, fDAC/4 Modulation
Figure 36. AD9778 Typical INL
0.6
REF –30.28dBm
*ATTEN 4dB
*AVG
Log
10dB/
0.4
0.2
EXT REF
0
–0.2
–0.4
–0.6
–0.8
–1.0
PAVG
10
W1 S2
0
2k
4k
6k
8k
10k
12k
14k
16k
CENTER 151.38MHz
*RES BW 30kHz
SPAN 50MHz
SWEEP 162.2ms (601 pts)
CODE
VBW 300kHz
TOTAL CARRIER POWER –12.61dBm/15.3600MHz
REF CARRIER POWER –17.87dBm/3.84000MHz
LOWER
dBm
UPPER
dBc dBm
FREQ OFFSET INTEG BW dBc
1 –17.87dBm
2 –20.65dBm
3 –18.26dBm
4 –18.23dBm
5.000MHz
10.00MHz
15.00MHz
3.840MHz –67.70 –85.57 –67.70 –85.57
3.840MHz –70.00 –97.87 –69.32 –87.19
3.840MHz –71.65 –99.52 –71.00 –88.88
Figure 35. AD9779 Multicarrier WCDMA Signal, 4× Interpolation,
DAC =122.88 MSPS, fDAC/4 Modulation
Figure 37. AD9778 Typical DNL
f
Rev. A | Page 2± of 56
AD9776/AD9778/AD9779
REF –25.39dBm
*ATTEN 4dB
*AVG
Log
10dB/
100
90
80
70
60
50
4× 150MSPS
4× 200MSPS
4× 100MSPS
PAVG
10
W1 S2
CENTER 143.88MHz
*RES BW 30kHz
SPAN 50MHz
SWEEP 162.2ms (601 pts)
VBW 300kHz
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
LOWER
UPPER
RMS RESULTS FREQ OFFSET REF BW
CARRIER POWER 5.000MHz
–12.74dBm/
3.84000MHz
dBc dBm
dBc dBm
3.884MHz –76.49 –89.23 –76.89 –89.63
3.840MHz –80.13 –92.87 –80.02 –92.76
3.840MHz –80.90 –93.64 –79.53 –92.27
10.00MHz
15.00MHz
Figure 38. AD9778 IMD, 4× Interpolation
Figure 41. AD9778 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation
100
90
80
70
60
50
–150
–154
–158
–162
–166
–170
fDATA = 200MSPS
fDATA = 160MSPS
fDAC = 200MSPS
fDAC = 400MSPS
fDATA = 250MSPS
fDAC = 800MSPS
0
20
40
60
80
100
0
20
40
60
80
100
fOUT (MHz)
fOUT (MHz)
Figure 39. AD9778 In-Band SFDR, 2× Interpolation
Figure 42. AD9778 Noise Spectral Density vs. fDAC Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
–150
–60
–70
–154
fDAC = 200MSPS
fDAC = 400MSPS
–158
–162
–166
–170
1ST ADJ CHAN
3RD ADJ CHAN
fDAC = 800MSPS
–80
–90
2ND ADJ CHAN
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
0
20
40
60
80
100
fOUT (MHz)
Figure 40. AD9778 ACLR, Single-Carrier WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = −3 dBFS
Figure 43. AD9778 Noise Spectral Density vs. fDAC Single-Tone Input
at −6 dBFS, fDATA = 200 MSPS
Rev. A | Page 21 of 56
AD9776/AD9778/AD9779
0.4
100
90
80
70
60
50
0.3
0.2
fDATA = 160MSPS
0.1
0
fDATA = 250MSPS
–0.1
–0.2
–0.3
–0.4
fDATA = 200MSPS
0
512
1024
1536
2048 2560
CODE
3072
3584 4096
0
20
40
60
80
100
fOUT (MHz)
Figure 44. AD9776 Typical INL
Figure 47. AD9776 In-Band SFDR, 2× Interpolation
0.20
0.15
0.10
0.05
0
–55
–60
–65
–70
–75
–80
–85
–90
1ST ADJ CHAN
3RD ADJ CHAN
–0.05
–0.10
–0.15
–0.20
2ND ADJ CHAN
0
512
1024 1536
2048
2560
3072
3584 4096
0
25
50
75
100 125 150 175 200 225
(MHz)
250
CODE
F
OUT
Figure 45. AD9776 Typical DNL
Figure 48. AD9776 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation
REF –25.29dBm
*ATTEN 4dB
*AVG
Log
10dB/
100
95
90
85
80
75
70
65
60
55
50
4× 100MSPS
4× 150MSPS
4× 200MSPS
PAVG
10
W1 S2
CENTER 143.88MHz
*RES BW 30kHz
SPAN 50MHz
SWEEP 162.2ms (601 pts)
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
VBW 300kHz
LOWER
UPPER
RMS RESULTS FREQ OFFSET REF BW
CARRIER POWER 5.000MHz
–12.67dBm/
3.84000MHz
dBc dBm
dBc dBm
3.884MHz –75.00 –87.67 –75.30 –87.97
3.840MHz –78.05 –90.73 –77.99 –90.66
3.840MHz –77.73 –90.41 –77.50 –90.17
10.00MHz
15.00MHz
Figure 46. AD9776 IMD, 4× Interpolation
Figure 49. AD9776, Single Carrier WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = −3 dBFS
Rev. A | Page 22 of 56
AD9776/AD9778/AD9779
–150
–154
–158
–162
–166
–170
–150
–154
–158
–162
–166
–170
fDAC = 200MSPS
fDAC = 200MSPS
fDAC = 400MSPS
fDAC = 400MSPS
fDAC = 800MSPS
fDAC = 800MSPS
0
10
20
30
40
50
60
70
80
90
100
fOUT (MHz)
0
10
20
30
40
50
60
70
80
90
100
fOUT (MHz)
Figure 50. AD9776 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
Figure 51. AD9776 Noise Spectral Density vs. fDAC
Single-Tone Input at −6 dBFS, fDATA = 200 MSPS
,
Rev. A | Page 23 of 56
AD9776/AD9778/AD9779
TERMINOLOGY
Integral Nonlinearity (INL)
In-Band Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal between dc and the
frequency equal to half the input data rate.
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
Out-of-Band Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal within the band that
starts at the frequency of the input data rate and ends at the
Nyquist frequency of the DAC output sample rate. Normally,
energy in this band is rejected by the interpolation filters. This
specification, therefore, defines how well the interpolation
filters work and the effect of other parasitic coupling paths to
the DAC output.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the difference between the output
when all inputs are set to 1 and the output when all inputs are
set to 0.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
f
DATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference drift, the drift is
reported in ppm per degree Celsius.
Adjacent Channel Leakage Ratio (ACLR)
The ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect of
wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Power Supply Rejection (PSR)
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band around its final value, measured from the
start of the output transition.
Rev. A | Page 24 of 56
AD9776/AD9778/AD9779
THEORY OF OPERATION
ported, as well as MSB-first or LSB-first transfer formats. The
serial interface ports can be configured as a single pin I/O (SDIO)
or two unidirectional pins for input/output (SDIO/SDO).
The AD9776/AD9778/AD9779 combine many features that
make them very attractive DACs for wired and wireless
communications systems. The dual digital signal path and
dual DAC structure allow an easy interface with common
quadrature modulators when designing single sideband
transmitters. The speed and performance of the parts allow
wider bandwidths and more carriers to be synthesized than
in previously available DACs. The digital engine uses a break-
through filter architecture that combines the interpolation with
a digital quadrature modulator. This allows the parts to conduct
digital quadrature frequency upconversion. They also have
features that allow simplified synchronization with incoming
data and between multiple parts.
General Operation of the Serial Interface
There are two phases to a communication cycle with the
AD977x. Phase 1 is the instruction cycle (the writing of an
instruction byte into the device), coincident with the first eight
SCLK rising edges. The instruction byte provides the serial port
controller with information regarding the data transfer cycle,
Phase 2 of the communication cycle. The Phase 1 instruction
byte defines whether the upcoming data transfer is a read or
write, the number of bytes in the data transfer, and the starting
register address for the first byte of the data transfer. The first
eight SCLK rising edges of each communication cycle are used
to write the instruction byte into the device.
The serial port configuration is controlled by Register 0x00,
Bits<6:7>. It is important to note that the configuration changes
immediately upon writing to the last bit of the byte. For multi-
byte transfers, writing to this register can occur during the
middle of a communication cycle. Care must be taken to
compensate for this new configuration for the remaining bytes
of the current communication cycle.
A logic high on the CSB pin followed by a logic low resets the
SPI port timing to the initial state of the instruction cycle.
From this state, the next eight rising SCLK edges represent the
instruction bits of the current I/O operation, regardless of the
state of the internal registers or the other signal levels at the
inputs to the SPI port. If the SPI port is in an instruction cycle
or a data transfer cycle, none of the present data is written.
The same considerations apply to setting the software reset,
RESET (Register 0x00, Bit 5) or pulling the RESET pin (Pin 70)
high. All registers are set to their default values, except
Register 0x00 and Register 0x04, which remain unchanged.
The remaining SCLK edges are for Phase 2 of the communica-
tion cycle. Phase 2 is the actual data transfer between the device
and the system controller. Phase 2 of the communication cycle
is a transfer of one, two, three, or four data bytes as determined
by the instruction byte. Using one multibyte transfer is preferred.
Single-byte data transfers are useful in reducing CPU overhead
when register access requires only one byte. Registers change
immediately upon writing to the last bit of each transfer byte.
Use of only single-byte transfers when changing serial port
configurations or initiating a software reset is recommended to
prevent unexpected device behavior.
As described in this section, all serial port data is transferred
to/from the device in synchronization to the SCLK pin. If
synchronization is lost, the device has the ability to asynchro-
nously terminate an I/O operation, putting the serial port
controller into a known state and, thereby, regaining
synchronization.
Instruction Byte
The instruction byte contains the information shown in
Table 9.
Table 9. SPI Instruction Byte
MSB
SERIAL PERIPHERAL INTERFACE
LSB
I0
66
I7
I6
I5
I4
I3
I2
I1
SPI_SDO
SPI
PORT
R/W
N1
N±
A4
A3
A2
A1
A±
67
SPI_SDI
68
SPI_SCLK
W
R/ , Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation. Logic 0 indicates a write
operation.
69
SPI_CSB
Figure 52. SPI Port
The serial port is a flexible, synchronous serial communications
port allowing easy interface to many industry-standard micro-
controllers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI® and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9776/
AD9778/AD9779. Single or multiple byte transfers are sup-
N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine
the number of bytes to be transferred during the data transfer
cycle. The bit decodes are listed in Table 10.
A4, A3, A2, A1, and A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0, respec-
tively, of the instruction byte determine the register that is accessed
during the data transfer portion of the communication cycle.
Rev. A | Page 25 of 56
AD9776/AD9778/AD9779
For multibyte transfers, this address is the starting byte address.
The remaining register addresses are generated by the device
based on the LSB-first bit (Register 0x00, Bit 6).
When LSB-first = 1 (LSB-first) the instruction and data bit
must be written from LSB to MSB. Multibyte data transfers in
LSB-first format start with an instruction byte that includes the
register address of the least significant data byte followed by mul-
tiple data bytes. The serial port internal byte address generator
increments for each byte of the multibyte communication cycle.
Table 10. Byte Transfer Count
N1
N0
Description
±
±
1
1
±
1
±
1
Transfer one byte
Transfer three bytes
Transfer two bytes
Transfer four bytes
The serial port controller data address decrements from the
data address written toward 0x00 for multibyte I/O operations if
the MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first mode is active.
Serial Interface Port Pin Descriptions
Serial Clock (SCLK)
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
The serial clock pin synchronizes data to and from the device
and to run the internal state machines. The maximum frequency
of SCLK is 40 MHz. All data input is registered on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
CSB
SCLK
SDIO
SDO
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5
N
D3 D2 D1 D0
0 0 0
N
0
0
Chip Select (CSB)
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should
stay low during the entire communication cycle.
D7 D6 D5
N
D3 D2 D1 D0
0 0 0
N
Figure 53. Serial Register Interface Timing MSB-First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However, this
pin can be used as a bidirectional data line. The configuration
of this pin is controlled by Register 0x00, Bit 7. The default is
Logic 0, configuring the SDIO pin as unidirectional.
A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2
D4 D5 D6 D7
N N N
0
0
0
N
N
D0 D1 D2
D4 D5 D6 D7
N N N
0
0
0
Figure 54. Serial Register Interface Timing LSB-First
Serial Data Out (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the device
operates in a single bidirectional I/O mode, this pin does not
output data and is set to a high impedance state.
tDS
tSCLK
CSB
tPWH
tPWL
MSB/LSB TRANSFERS
SCLK
tDS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register Bit LSB_FIRST
(Register 0x00, Bit 6). The default is MSB-first (LSB-first = 0).
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
SDIO
Figure 55. Timing Diagram for SPI Register Write
When LSB-first = 0 (MSB-first) the instruction and data bit
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent data
bytes should follow from high address to low address. In MSB-first
mode, the serial port internal byte address generator decrements
for each data byte of the multibyte communication cycle.
CSB
SCLK
tDV
SDIO
SDO
DATA BIT n
DATA BIT n–1
Figure 56. Timing Diagram for SPI Register Read
Rev. A | Page 26 of 56
AD9776/AD9778/AD9779
SPI REGISTER MAP
Table 11.
Register
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Def.
Comm
0x00
00
SDIO
Bidirectional
LSB/MSB First
Software
Reset
Power-
Down
Mode
Auto
PLL Lock
Indicator
(Read
0x00
Power-
Down
Enable
Only)
Digital
Control
0x01
0x02
01
02
Filter Interpolation Factor<1:0>
Filter Modulation Mode<3:0>
Zero
Stuffing
Enable
0x00
0x00
Data Format
Dual/Interleaved
Data Bus Mode
Real Mode
Data
Inverse
Sinc
DATACLK
Invert
TxEnable
Invert
Q First
Clock
Delay
Enable
Enable
Sync
Control
0x03
0x04
0x05
03
04
05
Data Clock Delay Mode<1:0>
Data Clock Divide
Ratio<1:0>
Reserved
0x00
0x00
0x00
Data Clock Delay<3:0>
Output Sync Pulse Divide<2:0>
Sync Out
Delay<4>
Sync Out Delay<3:0>
Sync Input Delay<3:0>
Input Sync Pulse Frequency Ratio<2:0>
Sync Input
Delay<4>
0x06
0x07
06
07
Input Sync Pulse Timing Error Tolerance<3:0>
DAC Clock Offset<4:0>
0x00
0x00
Sync
Receiver
Enable
Sync Driver
Enable
Sync
Triggering
Edge
PLL
Control
0x08
0x09
08
09
PLL Band Select<5:0>
PLL VCO AGC
Gain<1:0>
0xCF
0x37
PLL Enable
PLL VCO Divider Ratio<1:0>
PLL Loop
Divide
PLL Bias Setting<2:0>
Ratio<1:0>
Misc
0x0A
10
PLL Control Voltage Range<2:0> (Read Only)
PLL Loop Bandwidth Adjustment<4:0>
0x38
Control
I DAC
Control
Register
0x0B
0x0C
11
12
I DAC Gain Adjustment<7:0>
0xF9
0x01
I DAC Sleep
I DAC Power
Down
I DAC Gain
Adjustment<9:8>
Aux DAC1 0x0D 13
Control
Register
Auxiliary DAC1 Data<7:0>
0x00
0x00
0x0E
14
Auxiliary
DAC1 Sign
Auxiliary DAC1
Current Direction
Auxiliary
Auxiliary DAC1
Data<9:8>
DAC1
Power-
Down
Q DAC
Control
Register
0x0F
0x10
15
16
Q DAC Gain Adjustment<7:0>
0xF9
0x01
Q DAC Sleep
Q DAC Power-
Down
Q DAC Gain
Adjustment<9:8>
Aux DAC2 0x11
17
18
Auxiliary DAC2 Data<7:0>
Auxiliary
DAC2
Power-
Down
0x00
0x00
Control
0x12
Auxiliary
DAC2 Sign
Auxiliary DAC2
Current Direction
Auxiliary DAC2
Data<9:8>
Register
0x13
to
0x18
19 to 24
25
Reserved
Interrupt
Register
0x19
Sync Delay IRQ
Sync
Delay
IRQ
Internal
Sync
Loopback
0x00
Enable
0x1A
to
26 to 31
Reserved
0x1F
Rev. A | Page 27 of 56
AD9776/AD9778/AD9779
Table 12. SPI Register Description
Address
Register Name
Reg. No. Bits Description
Function
Default
Comm Register
±±
ꢀ
SDIO bidirectional
±: use SDIO pin as input data only
1: use SDIO as both input and output data
±: first bit of serial data is MSB of data byte
1: first bit of serial data is LSB of data byte
Bit must be written with a 1, then ± to soft
reset SPI register map
±
±±
6
LSB/MSB first
±
±
±±
±±
5
4
Software reset
Power-down mode
±: all circuitry is active
1: disable all digital and analog circuitry,
only SPI port is active
±±
±±
3
1
Auto power-down enable
PLL lock (read only)
Controls auto power-down mode, see the
Power-Down and Sleep Modes section
±: PLL is not locked
±
1: PLL is locked
±
Digital Control Register
±1
ꢀ:6
Filter interpolation factor
±±: 1× interpolation
±±
±1: 2× interpolation
1±: 4× interpolation
11: 8× interpolation
±1
±1
5:2
±
Filter modulation mode
Zero stuffing
See Table 21 for filter modes
±: zero stuffing off
±±±±
±
1: zero stuffing on
±2
±2
±2
ꢀ
6
5
Data format
±: signed binary
1: unsigned binary
±: both input data ports receive data
1: Data Port 1 only receives data
±: enable Q path for signal processing
±
±
±
Dual/interleaved data bus mode
Real mode
1: disable Q path data (internal Q channel
clocks disabled, I and Q modulators
disabled)
±2
±2
4
3
DATACLK delay enable
Inverse sinc enable
See the Using Data Delay to Meet Timing
Requirements section.
±: inverse sinc filter disabled
1: inverse sinc filter enabled
±: output DATACLK same phase as internal
capture clock
±
±
±2
2
DATACLK invert
1: output DATACLK opposite phase as
internal capture clock
±2
±2
1
±
TxEnable invert
Q first
Inverts the function of TxEnable Pin 39, see
the Interleaved Data Mode section
±: first byte of data is always I data at
beginning of transmit
±
1: first byte of data is always Q data at
beginning of transmit
Sync Control Register
±3
±3
ꢀ:6
5:4
Data clock delay mode
Extra data clock divide ratio
±±: manual
Data clock output divider (see Table 22 for
divider ratio)
±±
±±
±3
±4
±4
±4
±5
±5
3:±
ꢀ:4
3:1
±
ꢀ:4
3:1
Reserved
±±±
±±±±
±±±
Data clock delay
Output sync pulse divide
Sync out delay
Sync out delay
Input sync pulse frequency
Sets delay of REFCLK in to DATACLK out
Sets frequency of SYNC_O pulses
Sync output delay, Bit 4
Sync output delay, Bits<3:±>
Input sync pulse frequency divider, see the
AN-822 application note
±
±±±
±5
±
Sync input delay
Sync input delay, Bit 4
±
Rev. A | Page 28 of 56
AD9776/AD9778/AD9779
Address
Register Name
Reg. No. Bits Description
Function
Default
Sync Control Register
±6
ꢀ:4
Sync input delay
See the Multiple DAC Synchronization
section for details on using these registers
to synchronize multiple DACs
±
±6
3:±
Input sync pulse timing error
tolerance
±
±ꢀ
±ꢀ
±ꢀ
±ꢀ
ꢀ
6
5
4:±
Sync receiver enable
Sync driver enable
Sync triggering edge
SYNC_I to input data sampling
clock offset
±
±
±
±
PLL Control
±8
±8
±9
ꢀ:2
1:±
ꢀ
PLL band select
VCO AGC gain control
PLL enable
VCO frequency range vs. PLL band select
value (see Table 18)
111±±1
Lower number (low gain) is generally better 11
for performance
±: PLL off, DAC rate clock supplied by
outside source
±
1: PLL on, DAC rate clock synthesized
internally from external reference clock via
PLL clock multiplier
±9
±9
6:5
4:3
PLL VCO divide ratio
PLL loop divide ratio
FVCO/fDAC
±± × 1
±1 × 2
1± × 4
11 × 8
fDAC/fREF
±± × 2
±1 × 4
1± × 8
11 × 16
Always set to ±1±
±9
±A
2:±
ꢀ:5
PLL bias setting
±1±
Misc Control
PLL control voltage range
±±± to 111, proportional to voltage at PLL
loop filter output, readback only
±A
±B
±C
4:±
ꢀ:±
ꢀ
PLL loop bandwidth adjustment
I DAC gain adjustment
I DAC sleep
See PLL Loop Filter Bandwidth section for
details
I DAC Control Register
(ꢀ:±) LSB slice of 1±-bit gain setting word
for I DAC
±: I DAC on
1: I DAC off
±: I DAC on
1: I DAC off
11111±±1
±
±C
6
I DAC power-down
±
±C
±D
±E
1:±
ꢀ:±
ꢀ
I DAC gain adjustment
Aux DAC1 gain adjustment
Aux DAC1 sign
(9:8) MSB slice of 1±-bit gain setting word
for I DAC
±1
Aux DAC1 Control
Register
(ꢀ:±) LSB slice of 1±-bit gain setting word for ±±±±±±±±
Aux DAC1
±: positive
1: negative
±E
±E
±E
6
Aux DAC1 current direction
Aux DAC1 power-down
±: source
1: sink
±
5
±: Aux DAC1 on
1: Aux DAC1 off
(9:8) MSB slice of 1±-bit gain setting word
for Aux DAC1
±
1:±
Aux DAC1 gain adjustment
±±
Rev. A | Page 29 of 56
AD9776/AD9778/AD9779
Address
Register Name
Reg. No. Bits Description
Function
Default
Q DAC Control Register ±F
ꢀ:±
Q DAC gain adjustment
(ꢀ:±) LSB slice of 1±-bit gain setting word for 11111±±1
Q DAC
1±
1±
1±
ꢀ
Q DAC sleep
±: Q DAC on
1: Q DAC off
±: Q DAC on
1: Q DAC off
(9:8) MSB slice of 1±-bit gain setting word
for Q DAC
±
6
Q DAC power-down
±
1:±
ꢀ:±
ꢀ
Q DAC gain adjustment
Aux DAC2 gain adjustment
Aux DAC2 sign
Aux DAC2 Control
Register
11
12
(ꢀ:±) LSB slice of 1±-bit gain setting word for ±±±±±±±±
Aux DAC2
±: positive
1: negative
12
12
12
6
Aux DAC2 current direction
Aux DAC2 power-down
±: source
1: sink
±
5
±: Aux DAC2 on
1: Aux DAC2 off
(9:8) MSB slice of 1±-bit gain setting word
for Aux DAC2
±
1:±
Aux DAC2 gain adjustment
±±
Interrupt Register
19
19
19
19
19
19
19
ꢀ
6
5
3
2
1
±
±
±
±
±
±
±
±
Sync delay IRQ
Readback, must write ± to clear
Sync delay IRQ enable
Internal sync loopback
Rev. A | Page 3± of 56
AD9776/AD9778/AD9779
INTERPOLATION FILTER ARCHITECTURE
Table 15. Half-Band Filter 3
The AD9776/AD9778/AD9779 can provide up to 8× interpola-
tion, or the interpolation filters can be entirely disabled. It is
important to note that the input signal should be backed off by
approximately 0.01 dB from full scale to avoid overflowing the
interpolation filters. The coefficients of the low-pass filters and
the inverse sinc filter are given in Table 13, Table 14, Table 15,
and Table 16. Spectral plots for the filter responses are shown in
Figure 57, Figure 58, and Figure 59.
Lower Coefficient
Upper Coefficient
Integer Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(ꢀ)
H(8)
H(15)
H(14)
H(13)
H(12)
H(11)
H(1±)
H(9)
−39
±
+2ꢀ3
±
−11±2
±
+4964
+8192
Table 13. Half-Band Filter 1
Lower Coefficient
Upper Coefficient
H(55)
H(54)
H(53)
H(52)
H(51)
H(5±)
H(49)
H(48)
H(4ꢀ)
H(46)
H(45)
H(44)
H(43)
H(42)
H(41)
H(4±)
H(39)
H(38)
H(3ꢀ)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(3±)
H(29)
Integer Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(ꢀ)
H(8)
−4
±
+13
±
−34
±
+ꢀ2
±
−138
±
+245
±
−4±8
±
+65±
±
−1±±3
±
+1521
±
Table 16. Inverse Sinc Filter
Lower Coefficient
Upper Coefficient
Integer Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(9)
H(8)
H(ꢀ)
H(6)
+2
−4
+1±
−35
+4±1
H(9)
10
0
H(1±)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(1ꢀ)
H(18)
H(19)
H(2±)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(2ꢀ)
H(28)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
−2315
±
+36ꢀ1
±
−6642
±
+2±,ꢀ55
+32,ꢀ68
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 57. 2× Interpolation, Low-Pass Response to 4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Table 14. Half-Band Filter 2
Lower Coefficient
Upper Coefficient
Integer Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(ꢀ)
H(8)
H(9)
H(1±)
H(11)
H(12)
H(23)
H(22)
H(21)
H(2±)
H(19)
H(18)
H(1ꢀ)
H(16)
H(15)
H(14)
H(13)
−2
±
+1ꢀ
±
−ꢀ5
±
+238
±
−66±
±
+253±
+4±96
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 58. 4× Interpolation, Low-Pass Response to 4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
Rev. A | Page 31 of 56
AD9776/AD9778/AD9779
10
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–4
–3
–2
–1
0
1
2
3
4
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
fOUT (× Input Data Rate)
Figure 59. 8× Interpolation, Low-Pass Response to 4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
Figure 62. Interpolation/Modulation Combination of −3 fDAC/8 Filter
10
0
With the interpolation filter and modulator combined, the
incoming signal can be placed anywhere within the Nyquist
region of the DAC output sample rate. When the input signal is
complex, this architecture allows modulation of the input signal
to positive or negative Nyquist regions (see Table 17).
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
The Nyquist regions of up to 4× the input data rate can be seen
in Figure 60.
–8 –7 –6 –5 –4 –3 –2 –1
1
2
3
4
5
6
7
8
–4×
–3×
–2×
–1×
DC
1×
2×
3×
4×
–4
–3
–2
–1
0
1
2
3
4
Figure 60. Nyquist Zones
fOUT (× Input Data Rate)
Figure 57, Figure 58, and Figure 59 show the low-pass response
of the digital filters with no modulation. By turning on the
modulation feature, the response of the digital filters can be
tuned to anywhere within the DAC bandwidth. As an example,
Figure 61 to Figure 67 show the nonshifted mode filter responses
(refer to Table 17 for shifted/nonshifted mode filter responses).
Figure 63. Interpolation/Modulation Combination of −2 fDAC/8 Filter
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 64. Interpolation/Modulation Combination of −1 fDAC/8 Filter
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 61. Interpolation/Modulation Combination of 4 fDAC/8 Filter
Rev. A | Page 32 of 56
AD9776/AD9778/AD9779
10
0
Shifted mode filter responses allow the pass band to be centered
around 0.5 fDATA, 1.5 fDATA, 2.5 fDATA, and 3.5 fDATA. Switching
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
to the shifted mode response does not modulate the signal.
Instead, the pass band is simply shifted. For example, picture
the response shown in Figure 67 and assume the signal in-band
is a complex signal over the bandwidth 3.2 fDATA to 3.3 fDATA. If
the even mode filter response is then selected, the pass band
becomes centered at 3.5 fDATA. However, the signal remains at
the same place in the spectrum. The shifted mode capability
allows the filter pass band to be placed anywhere in the DAC
Nyquist bandwidth.
The AD9776/AD9778/AD9779 are dual DACs with internal
complex modulators built into the interpolating filter response.
In dual channel mode, the devices expect the real and the
imaginary components of a complex signal at Digital Input
Port 1 and Digital Input Port 2 (I and Q, respectively). The DAC
outputs then represent the real and imaginary components of
the input signal, modulated by the complex carrier fDAC/2,
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 65. Interpolation/Modulation Combination of fDAC/8 Filter
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
f
DAC/4, or fDAC/8.
With Register 2, Bit 6 set, the device accepts interleaved data on
Port 1 in the I, Q, I, Q . . . sequence. Note that in interleaved
mode, the channel data rate at the beginning of the I and the Q
data paths are now half the input data rate because of the inter-
leaving. The maximum input data rate is still subject to the
maximum specification of the device. This limits the synthesis
bandwidth available at the input in interleaved mode.
–4
–3
–2
–1
0
1
2
3
4
With Register 0x02, Bit 5 (real mode) set, the Q channel and the
internal I and Q digital modulation are turned off. The output
spectrum at the I DAC then represents the signal at Digital
Input Port 1, interpolated by 1×, 2×, 4×, or 8×.
fOUT (× Input Data Rate)
Figure 66. Interpolation/Modulation Combination of
2 fDAC/8 Filter in Shifted Mode
10
0
The general recommendation is that if the desired signal is
within 0.4 × fDATA, the odd filter mode should be used. Outside
of this, the even filter mode should be used. In any situation, the
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
total bandwidth of the signal should be less than 0.8 × fDATA
.
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 67. Interpolation/Modulation Combination of
3 fDAC/8 Filter in Shifted Mode
Rev. A | Page 33 of 56
AD9776/AD9778/AD9779
Table 17. Interpolation Filter Modes, (Register 0x01, Bits<5:2>)
Nyquist
Zone
Pass
Filter
Mode
<5:2>
Interpolation
Factor <7:6>
Modulation
DC
Band
F_Low1
−±.±5
±.±125
±.±ꢀ5
±.13ꢀ5
±.2
±.2625
±.325
±.38ꢀ5
−±.55
−±.48ꢀ5
−±.425
−±.3625
−±.3
−±.23ꢀ5
−±.1ꢀ5
−±.1125
−±.1
±.±25
±.15
±.2ꢀ5
−±.6
−±.4ꢀ5
−±.35
−±.225
−±.2
±.±5
−±.ꢀ
−±.45
Center1
±
±.±625
±.125
±.18ꢀ5
±.25
±.3125
±.3ꢀ5
±.43ꢀ5
−±.5
−±.43ꢀ5
−±.3ꢀ5
−±.3125
−±.25
−±.18ꢀ5
−±.125
−±.±625
±
±.125
±.25
±.3ꢀ5
−±.5
−±.3ꢀ5
−±.25
−±.125
±
F_High1
+±.±5
±.1125
±.1ꢀ5
±.23ꢀ5
±.3
±.3625
±.425
±.48ꢀ5
−±.45
−±.38ꢀ5
−±.343
−±.2625
−±.2
−±.13ꢀ5
−±.±ꢀ5
−±.±125
+±.1
±.225
±.35
±.4ꢀ5
−±.4
−±.2ꢀ5
−±.15
−±.±25
+±.2
±.45
−±.3
−±.±5
Comments
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
4
4
4
2
2
2
2
±x±±
±x±1
±x±2
±x±3
±x±4
±x±5
±x±6
±x±ꢀ
±x±8
±x±9
±x±A
±x±B
±x±C
±x±D
±x±E
±x±F
±x±±
±x±1
±x±2
±x±3
±x±4
±x±5
±x±6
±x±ꢀ
±x±±
±x±1
±x±2
±x±3
1
In 8× interpolation;
BW (min) = ±.±3ꢀ5 × fDAC
BW (max) = ±.1 × fDAC
DC shifted
F/8
F/8 shifted
F/4
F/4 shifted
3F/8
3F/8 shifted
F/2
F/2 shifted
−3F/8
−3F/8 shifted
−F/4
−F/4 shifted
−F/8
−F/8 shifted
DC
DC shifted
F/4
F/4 shifted
F/2
F/2 shifted
−F/4
−F/4 shifted
DC
2
3
4
5
6
ꢀ
8
−8
−ꢀ
−6
−5
−4
−3
−2
−1
1
In 4× interpolation;
BW (min) = ±.±ꢀ5 × fDAC
BW (max) = ±.2 × fDAC
2
3
4
−4
−3
−2
−1
1
2
−2
−1
In 2× interpolation;
BW (min) = ±.15 × fDAC
BW (max) = ±.4 × fDAC
DC shifted
F/2
F/2 shifted
±.25
−±.5
−±.25
1 Frequency normalized to fDAC
.
Rev. A | Page 34 of 56
AD9776/AD9778/AD9779
10
0
INTERPOLATION FILTER MINIMUM AND
MAXIMUM BANDWIDTH SPECIFICATIONS
–10
–20
–30
–40
–50
–60
–70
–80
The AD977x uses a novel interpolation filter architecture that
allows DAC IF frequencies to be generated anywhere in the
spectrum. Figure 68 shows the traditional choice of DAC IF
output bandwidth placement. Note that there are no possible
filter modes in which the carrier can be placed near 0.5 × fDATA
1.5 × fDATA, 2.5 × fDATA, and so on.
,
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–4
–3
–2
–1
fOUT
ASSUMING 8
0
1
2
3
4
(×
Input Data Rate),
INTERPOLATION
×
Figure 70. Shifted Bandwidths Accessible with the Filter Architecture
With this filter architecture, a signal placed anywhere in the
spectrum is possible. However, the signal bandwidth is limited
by the input sample rate of the DAC and the specific placement
of the carrier in the spectrum. The bandwidth restriction
resulting from the combination of filter response and input
sample rate is often referred to as the synthesis bandwidth, since
this is the largest bandwidth that the DAC can synthesize.
–4
–3
–2
–1
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
0
1
2
3
4
Figure 68. Traditional Bandwidth Options for TxDAC Output IF
The maximum bandwidth condition exists if the carrier is
placed directly in the center of one of the filter pass bands. In
this case, the total 0.1 dB bandwidth of the interpolation filters
is equal to 0.8 × fDATA. As Table 17 shows, the synthesis band-
width as a fraction of DAC output sample rate drops by a factor
of 2 for every doubling of interpolation rate. The minimum
bandwidth condition exists, for example, if a carrier is placed at
0.25 × fDATA. In this situation, if the nonshifted filter response is
The filter architecture not only allows the interpolation filter
pass bands to be centered in the middle of the input Nyquist
zones (as explained in this section), but also allows the possi-
bility of a 3 × fDAC/8 modulation mode. With all of these filter
combinations, a carrier of given bandwidth can be placed
anywhere in the spectrum and fall into a possible pass band of
the interpolation filters. The possible bandwidths accessible
with the filter architecture are shown in Figure 69 and
Figure 70. Note that the shifted and nonshifted filter modes
are all accessible by programming the filter mode for the
particular interpolation rate.
enabled, the high end of the filter response cuts off at 0.4 × fDATA
,
thus limiting the high end of the signal bandwidth. If the shifted
filter response is enabled instead, then the low end of the filter
response cuts off at 0.1 × fDATA, thus limiting the low end of the
signal bandwidth. The minimum bandwidth specification that
applies for a carrier at 0.25 × fDATA is therefore 0.3 × fDATA. The
minimum bandwidth behavior is repeated over the spectrum
for carriers placed at ( n 0.25) × fDATA, where n is any integer.
10
0
–10
–20
–30
–40
–50
–60
–70
–80
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal.
It is a PMOS input differential pair powered from
the 1.8 V supply, therefore, it is important to maintain the
specified 400 mV input common-mode voltage. Each input
pin can safely swing from 200 mV p-p to 1 V p-p about the
400 mV common-mode voltage. While these input levels are
not directly LVDS-compatible, REFCLK can be driven by an
offset ac-coupled LVDS signal, as shown in Figure 71.
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
Figure 69. Nonshifted Bandwidths Accessible with the Filter Architecture
Rev. A | Page 35 of 56
AD9776/AD9778/AD9779
0.1μF
PLL Enabled (Register 0x09, Bit 7 = 1)
LVDS_P_IN
CLK+
50Ω
50Ω
The PLL enable switch shown in Figure 74 is connected to the
junction of the N1 dividers (PLL VCO divide ratio) and N2
dividers (PLL loop divide ratio). Divider N3 determines the
interpolation rate of the DAC, and the ratio N3/N2 determines
the ratio of reference clock/input data rate. The VCO runs
optimally over the range of 1.0 GHz to 2.0 GHz, so that N1
keeps the speed of the VCO within this range, although the
DAC sample rate can be lower. The loop filter components are
entirely internal and no external compensation is necessary.
V
= 400mV
CM
LVDS_N_IN
CLK–
0.1μF
Figure 71. LVDS REFCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 71. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, then ac-coupled, as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 72.
PLL Disabled (Register 0x09, Bit 7 = 0)
The PLL enable switch shown in Figure 74 is connected to the
reference clock input. The differential reference clock input is
the same as the DAC output sample rate. N3 determines the
interpolation rate.
0.1μF
50Ω
TTL OR CMOS
CLK INPUT
CLK+
0x0A (7:5)
ADC
CLK–
PLL CONTROL
VOLTAGE RANGE
50Ω
BAV99ZXCT
0x0A (4:0)
LOOP FILTER
BANDWIDTH
HIGH SPEED
DUAL DIODE
0x08 (7:2)
VCO RANGE
REFERENCE CLOCK
(PINS 5 AND 6)
INTERNAL
LOOP
FILTER
V
= 400mV
PHASE
DETECTION
CM
VCO
Figure 72. TTL or CMOS REFCLK Drive Circuit
A simple bias network for generating VCM is shown in
Figure 73. It is important to use CVDD18 and CGND for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and can
degrade DAC performance.
÷N2
÷N1
0x09 (4:3)
PLL LOOP
DIVIDE RATIO DIVIDE RATIO
0x09 (6:5)
PLL VCO
DAC
INTERPOLATION
RATE
÷N3
DATACLK OUT (PIN 37)
0x01 (7:6)
0x09 (7)
PLL ENABLE
V
= 400mV
CM
INTERNAL DAC SAMPLE
RATE CLOCK
CVDD18
1kΩ
Figure 74. Internal Clock Architecture
1nF
0.1μF
1nF
287Ω
CGND
Figure 73. REFCLK VCM Generator Circuit
INTERNAL PLL CLOCK MULTIPLIER/CLOCK
DISTRIBUTION
The internal clock structure on the devices allows the user to
drive the differential clock inputs with a clock at 1× or an
integer multiple of the input data rate or at the DAC output
sample rate. An internal PLL provides input clock multiplication
and provides all the internal clocks required for the interpolation
filters and data synchronization.
The internal clock architecture is shown in Figure 74. The
reference clock is the differential clock at Pin 5 and Pin 6. This
clock input can be run differentially or singled-ended by
driving Pin 5 with a clock signal and biasing Pin 6 to the
midswing point of the signal at Pin 5. The clock architecture
can be run in the following configurations:
Rev. A | Page 36 of 56
AD9776/AD9778/AD9779
Table 18. VCO Frequency Range vs. PLL Band Select Value
Typical PLL Lock Ranges
Typical PLL Lock Ranges
PLL Band Select
VCO Frequency Range in MHz
Typ at 25°C Typ over Temp
PLL Band Select
VCO Frequency Range in MHz
Typ at 25°C
Typ over Temp
fLOW
fHIGH
fLOW
fHIGH
fLOW
fHIGH
1184
11ꢀ1
1152
1138
1119
11±ꢀ
1±9±
1±ꢀ6
1±59
1±46
1±1ꢀ
989
fLOW
fHIGH
11ꢀ±
115ꢀ
1138
1124
11±6
1±93
1±ꢀ6
1±62
1±46
1±32
1±±4
9ꢀ6
111111 (63)
11111± (62)
1111±1 (61)
1111±± (6±)
111±11 (59)
111±1± 58)
111±±1 (5ꢀ)
111±±± (56)
11±111 (55)
11±11± (54)
11±1±1 (53)
11±1±± (52)
11±±11 (51)
11±±1± (5±)
11±±±1 (49)
11±±±± (48)
1±1111 (4ꢀ)
1±111± (46)
1±11±1 (45)
1±11±± (44)
1±1±11 (43)
1±1±1± (42)
1±1±±1 (41)
1±1±±± (4±)
1±±111 (39)
1±±11± (38)
1±±1±1 (3ꢀ)
1±±1±± (36)
1±±±11 (35)
1±±±1± (34)
1±±±±1 (33)
1±±±±± (32)
±11111 (31)
±1111± (3±)
±111±1 (29)
±111±± (28)
±11±11 (2ꢀ)
±11±1± (26)
±11±±1 (25)
±11±±± (24)
±1±111 (23)
±1±11± (22)
±1±1±1 (21)
±1±1±± (2±)
±1±±11 (19)
±1±±1± (18)
±1±±±1 (1ꢀ)
±1±±±± (16)
±±1111 (15)
Auto mode
2±56
Auto mode
±±111± (14)
±±11±1 (13)
±±11±± (12)
±±1±11 (11)
±±1±1± (1±)
±±1±±1 (9)
±±1±±± (8)
±±±111 (ꢀ)
±±±11± (6)
±±±1±1 (5)
±±±1±± (4)
±±±±11 (3)
±±±±1± (2)
±±±±±1 (1)
±±±±±± (±)
1116
11±6
1±86
1±ꢀ5
1±55
1±45
1±2ꢀ
1±16
998
98ꢀ
96±
933
9±8
113ꢀ
112ꢀ
11±6
1±95
1±ꢀ5
1±65
1±4ꢀ
1±34
1±16
1±±5
9ꢀꢀ
21ꢀ±
2113
2±93
2±ꢀ5
2±5ꢀ
2±3ꢀ
2±16
2±±3
1981
196±
1948
1923
19±3
1895
18ꢀ1
1853
1842
182±
18±4
1ꢀ9±
1ꢀ5ꢀ
1ꢀ38
1ꢀ±ꢀ
1689
1661
1641
1613
1595
15ꢀ±
1552
1525
15±9
1485
1469
1443
1429
14±5
139±
1368
1351
1331
1313
1255
12ꢀ5
1221
124±
1218
12±4
21±5
2138
2±81
2±61
2±43
2±26
2±±6
1986
19ꢀ2
1952
1931
192±
1895
18ꢀ4
186ꢀ
1844
1826
1815
1ꢀ94
1ꢀꢀ9
1ꢀ64
1ꢀ34
1ꢀ14
1684
1666
1639
161ꢀ
1592
15ꢀ2
1549
1528
15±4
148ꢀ
1464
144ꢀ
1423
14±ꢀ
1385
1369
135±
1332
1313
1295
124±
1259
12±ꢀ
1224
12±4
1189
2±±2
1982
1964
194ꢀ
192ꢀ
19±ꢀ
1894
18ꢀ2
1852
1841
1816
1ꢀ96
1ꢀ89
1ꢀ64
1ꢀ46
1ꢀ38
1ꢀ14
1ꢀ±±
1689
165ꢀ
1641
161±
159ꢀ
1568
1553
1525
1511
1484
14ꢀ±
1441
1429
14±3
139±
1362
1352
1325
1314
129±
12ꢀ6
1253
1239
1183
12±4
1151
11ꢀ1
1148
113ꢀ
2±48
2±29
2±1±
1992
19ꢀ1
1951
1936
1913
1892
1881
1855
1835
1828
18±3
1ꢀ84
1ꢀꢀ6
1ꢀ52
1ꢀ3ꢀ
1ꢀ26
1695
16ꢀ9
1649
1635
16±ꢀ
1592
1562
1548
1519
15±6
14ꢀ4
1463
1433
1422
1391
138±
1352
134±
1315
13±2
12ꢀꢀ
1264
12±5
122ꢀ
11ꢀ2
1193
11ꢀ±
1159
949
923
898
8ꢀ3
962
936
911
95±
925
899
883
859
VCO Frequency Ranges
Because the PLL band covers greater than a 2× frequency range,
there can be two options for the PLL band select: one at the low
end of the range and one at the high end of the range. Under
these conditions, the VCO phase noise is optimal when the user
selects the band select value corresponding to the high end of the
frequency range. Figure 75 shows how the VCO bandwidth and
the optimal VCO frequency varies with the band select value.
VCO Frequency Ranges over Temperature
The specifications given over temperature in Table 18 are for a
single part in a single lot. Part-to-part, and lot-to-lot, these
specifications can exhibit a mean shift of several register
settings. Systems should be designed to take this potential shift
into account to maintain optimal PLL performance.
PLL Loop Filter Bandwidth
The loop filter bandwidth of the PLL is programmed via SPI
Register 0x0A, Bits<4:0>. Changing these values switches
capacitors on the internal loop filter. No external loop filter
components are required. This loop filter has a pole at 0 (P1),
and then a zero (Z1) pole (P2) combination. Z1 and P2 occur
within a decade of each other. The location of the zero pole is
determined by Bits<4:0>. For a setting of 00000, the zero pole
occurs near 10 MHz. By setting Bits<4:0> to 11111, the Z1/P2
combination can be lowered to approximately 1 MHz. The
relationship between Bits<4:0> and the position of the zero pole
between 1 MHz and 10 MHz is linear. The internal components
are not low tolerance, however, and can drift by as much as 30%.
For optimal performance, the bandwidth adjustment
(Register 0x0A, Bits<4:0>) should be set to 11111 for all
operating modes with PLL enabled. The PLL bias settings
Rev. A | Page 3ꢀ of 56
AD9776/AD9778/AD9779
(Register 0x09, Bits<2:0>) should be set to 111. The PLL control
voltage (Register 0x0A, Bits<7:5>) is read back and is propor-
tional to the dc voltage at the internal loop filter output. With
the PLL bias settings given in this section, the readback from
the PLL control voltage should typically be 010, or possibly 001
or 011. Anything outside of this range indicates that the PLL is
not operating correctly.
external resistor is 10 kΩ, which sets up an IREFERENCE in the
resistor of 120 μA, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear
function of this resistor, a high precision resistor improves gain
matching to the internal matching specification of the devices.
Internal current mirrors provide a current-gain scaling, where
I DAC or Q DAC gain is a 10-bit word in the SPI port register
(Register 0x0A, Register 0x0B, Register 0x0E, and Register 0x0F).
The default value for the DAC gain registers gives an IFS of
approximately 20 mA, where IFS is equal to
60
56
52
48
44
40
36
32
28
24
20
16
12
8
1.2V
R
27
6
⎛
⎜
⎞
⎛
⎞
⎠
×
+
×DAC gain ×32
⎟
⎜
⎟
12 1024
⎝
⎝
⎠
AD9779
I DAC GAIN
I DAC
1.2V BAND GAP
VREF
I120
DAC FULL-SCALE
REFERENCE
CURRENT
CURRENT
SCALING
0.1μF
4
10kΩ
0
Q DAC
Q DAC GAIN
Figure 77. Reference Circuitry
F
(MHz)
VCO
Figure 75. Typical PLL Band Select vs. Frequency at 25°C
35
60
30
25
20
15
10
5
56
52
48
44
40
36
32
28
24
20
16
12
8
0
4
0
200
400
600
800
1000
0
DAC GAIN CODE
Figure 78. IFS vs. DAC Gain Code
F
(MHz)
VCO
Application of Auxiliary DACs in Single Sideband
Transmitter
Figure 76. Typical PLL Band Select vs. Frequency over Temperature
The AD977x has an autosearch feature that determines the
optimal settings for the PLL. To enable the autosearch mode, set
Register 0x08, Bits<7:2> to 11111b, and read back the value
from Register 0x08, Bits<7:2>. Autosearch mode is intended to
find the optimal PLL settings only, after which the same settings
should be applied in manual mode. It is not recommended that
the PLL be set to autosearch mode during regular operation.
Two auxiliary DACs are provided on the AD977x. The full-scale
output current on these DACs is derived from the 1.2 V band
gap reference and external resistor. The gain scale from the ref-
erence amplifier current IREFERENCE to the auxiliary DAC reference
current is 16.67 with the auxiliary DAC gain set to full scale
(10-bit values, SPI Register 0x0D and SPI Register 0x11), this
gives a full-scale current of approximately 2 mA for auxiliary
DAC1 and auxiliary DAC2. The auxiliary DAC outputs are not
differential. Only one side of the auxiliary DAC (P or N) is
active at one time. The inactive side goes into a high impedance
state (>100 kΩ). In addition, the P or N outputs can act as
current sources or sinks. The control of the P and N side for
both auxiliary DACs is via Register 0x0E and Register 0x10,
Bits<7:6>. When sourcing current, the output compliance
FULL-SCALE CURRENT GENERATION
Internal Reference
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
I120 (Pin 75). A simplified block diagram of the reference
circuitry is shown in Figure 77. The recommended value for the
Rev. A | Page 38 of 56
AD9776/AD9778/AD9779
voltage is 0 V to 1.6 V. When sinking current, the output
compliance voltage is 0.8 V to 1.6 V.
of the 3.3 V supply (mode and speed independent) in single
DAC mode is 102 mW/31 mA. In dual DAC mode, this is
182 mW/55 mA. Furthermore, when the PLL is enabled, it adds
90 mW/50 mA to the 1.8 V clock supply regardless of the mode
of the AD9779.
The auxiliary DACs can be used for local oscillator (LO) cancella-
tion when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
DAC-to-quadrature modulator interfaces are shown in Figure 79
and Figure 80. Often, the input common-mode voltage for the
modulator is much higher than the output compliance range of
the DAC, so that ac coupling or a dc level shift is necessary. If the
required common-mode input voltage on the quadrature
modulator matches that of the DAC, then the dc blocking
capacitors in Figure 79 can be removed. A low-pass or band-pass
passive filter is recommended when spurious signals from the
DAC (distortion and DAC images) at the quadrature modulator
inputs can affect the system performance. Placing the filter at the
location shown in Figure 79 and Figure 80 allows easy design of
the filter, as the source and load impedances can easily be
designed close to 50 ꢀ.
0.7
8×
INTERPOLATION
0.6
0.5
0.4
0.3
0.2
0.1
0
4
×
INTERPOLATION
4×
INTERPOLATION,
ZERO STUFFING
8
×
INTERPOLATION,
ZERO STUFFING
2×
INTERPOLATION,
ZERO STUFFING
2×
INTERPOLATION
1×
INTERPOLATION,
ZERO STUFFING
1× INTERPOLATION
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
Figure 81. Total Power Dissipation, I Data Only, Real Mode
QUADRATURE
MODULATOR V+
0.4
0.3
0.2
0.1
0
AD9779
AUX
DAC1
8× INTERPOLATION
4× INTERPOLATION
QUADRATURE
MODULATOR V+
0.1μF
AD9779
OPTIONAL
AUX
AD9779
I DAC
QUAD MOD
I INPUTS
PASSIVE
DAC2
FILTERING
2
×
×
INTERPOLATION
INTERPOLATION
0.1μF
25Ω TO 50Ω
0.1μF
0.1μF
OPTIONAL
AD9779
Q DAC
QUAD MOD
Q INPUTS
PASSIVE
FILTERING
1
25Ω TO 50Ω
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
Figure 79. Typical Use of Auxiliary DACs AC Coupling to
Quadrature Modulator
Figure 82. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,
Does Not Include Zero Stuffing
QUADRATURE
MODULATOR V+
0.08
AD9779
QUAD MOD
I OR Q INPUTS
AUX
DAC1 OR 2
0.06
8× INTERPOLATION
4× INTERPOLATION
OPTIONAL
PASSIVE
0.04
0.02
0
AD9779
I OR Q DAC
2× INTERPOLATION
FILTERING
25Ω TO 50Ω
25Ω TO 50Ω
1× INTERPOLATION
Figure 80. Typical Use of Auxiliary DACs DC Coupling to Quadrature
Modulator with DC Shift
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
POWER DISSIPATION
Figure 81 to Figure 89 show the power dissipation of the 1.8 V
and 3.3 V digital and clock supplies in single DAC and dual
DAC modes. In addition to this, the power dissipation/current
Figure 83. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,
Includes Modulation Modes, Does Not Include Zero Stuffing
Rev. A | Page 39 of 56
AD9776/AD9778/AD9779
0.125
0.100
0.075
0.050
0.025
0
0.075
8× INTERPOLATION, f
/8,
/4,
/2,
DAC
DAC
DAC
f
f
NO MODULATION
4× INTERPOLATION
ALL INTERPOLATION MODES
0.050
0.025
0
2× INTERPOLATION
1× INTERPOLATION,
NO MODULATION
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
Figure 87. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC
Mode, Does Not Include Zero Stuffing
Figure 84. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation
Modes and Zero Stuffing
0.075
1.0
8× INTERPOLATION, ALL
MODULATION MODES
8× INTERPOLATION,
0.9
ZERO STUFFING
4× INTERPOLATION,
ALL MODULATION
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
MODES
ALL INTERPOLATION MODES
0.050
0.025
0
2× INTERPOLATION,
ALL MODULATION MODES
2× INTERPOLATION,
ZERO STUFFING
4× INTERPOLATION,
ZERO STUFFING
1× INTERPOLATION,
ZERO STUFFING
1× INTERPOLATION
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
0
25 50 75 100 125 150 175 200 225 250 275 300
fDATA (MSPS)
Figure 88. Digital 3.3 V Supply, I and Q Data, Dual DAC Mode
Figure 85. Total Power Dissipation, Dual DAC Mode
0.8
0.7
0.6
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
8× INTERPOLATION, f
/8,
/4,
/2,
DAC
DAC
DAC
f
f
NO MODULATION
4× INTERPOLATION
0.5
0.4
0.3
0.2
0.1
0
2× INTERPOLATION
1× INTERPOLATION,
NO MODULATION
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
0
200
400
600
800
1000
1200
fDAC (MSPS)
Figure 86. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC
Mode, Does Not Include Zero Stuffing
Figure 89. Power Dissipation of Inverse Sinc Filter
Rev. A | Page 4± of 56
AD9776/AD9778/AD9779
POWER-DOWN AND SLEEP MODES
INTERLEAVED DATA MODE
The AD977x has a variety of power-down modes, so that the
digital engine, main TxDACs, or auxiliary DACs can be powered
down individually or together. Via the SPI port, the main TxDACs
can be placed in sleep or power-down mode. In sleep mode, the
TxDAC output is turned off, thus reducing power dissipation.
The reference remains powered on, however, so that recovery
from sleep mode is very fast. With the power-down mode bit
set (Register 0x00, Bit 4), all analog and digital circuitry, including
the reference, is powered down. The SPI port remains active in
this mode. This mode offers more substantial power savings
than sleep mode, but the turn-on time is much longer. The
auxiliary DACs also have the capability to be programmed into
sleep mode via the SPI port. The auto power-down enable bit
(Register 0x00, Bit 3) controls the power-down function for the
digital section of the devices. The auto power-down function
works in conjunction with the TXENABLE pin (Pin 39) according
to the following:
The TxEnable bit is dual function. In dual port mode, it is
simply used to power down the digital section of the devices. In
interleaved mode, the IQ data stream is synchronized to
TXENABLE. Therefore, to achieve IQ synchronization,
TXENABLE should be held low until an I data word is present at
the inputs to Data Port 1. If a DATACLK rising edge occurs
while TXENABLE is at a high logic level, IQ data becomes
synchronized to the DATACLK output. TXENABLE can remain
high and the input IQ data remains synchronized. To be
backwards-compatible with previous DACs from Analog
Devices, Inc. such as the AD9777 and AD9786, the user can
also toggle TXENABLE once during each data input cycle, thus
continually updating the synchronization. If TXENABLE is
brought low and held low for multiple REFCLK cycles, then the
devices flush the data in the interpolation filters, and shut down
the digital engine after the filters are flushed. The amount of
REFCLK cycles it takes to go into this power-down mode is
then a function of the length of the equivalent 2×, 4×, or 8×
interpolation filter. The timing of TXENABLE, I/Q select, filter
flush, and digital power-down are shown in Figure 91.
TXENABLE (Pin 39) =
0: autopower-down enable =
0: flush data path with 0s
1: flush data for multiple REFCLK cycles; then
automatically place the digital engine in power-down
state. DACs, reference, and SPI port are not affected.
INTERLEAVED
INPUT DATA
I1
Q1
I2
Q2
TxENABLE
or TXENABLE (Pin 39) =
1: normal operation
TxENABLE CAN REMAIN
HIGH OR TOGGLE FOR
I/Q SYNCHRONIZATION
FLUSHING
INTERPOLATION
FILTERS
POWER
DOWN DIGITAL
SECTION
As shown in Figure 90, the power dissipation saved by using the
power down mode is nearly proportional to the duty cycle of
the signal at the TXENABLE pin.
Figure 91. TXENABLE Function
The TXENABLE function can be inverted by changing the
status of Register 0x02, Bit 1. The other bit that controls IQ
ordering is the Q-first bit (Register 0x02, Bit 0). With the Q-first
bit reset to the default of 0, the IQ pairing that is latched is the
I1Q1, I2Q2, and so on. With IQ first set to 1, the first I data is
discarded and the pairing is I2Q1, I3Q2, and so on. Note that
with IQ-first set, the I data is still routed to the internal I
channel, the Q data is routed to the internal Q channel, and
only the pairing changes.
0.9
2× INT fDATA = 50MSPS
2× INT fDATA = 200MSPS
4× INT fDATA = 50MSPS
4× INT fDATA = 200MSPS
8× INT fDATA = 50MSPS
8× INT fDATA = 200MSPS
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TIMING INFORMATION
Figure 92 to Figure 95 show some of the various timing
possibilities when the PLL is enabled. The combination of the
settings of N2 and N3 from Figure 74 means that the reference
clock frequency can be a multiple of the actual input data rate.
Figure 92 to Figure 95 show, respectively, what the timing looks
like when N2/N3 = 1 and 2.
0
20
40
60
80
100
DUTY CYCLE (%)
Figure 90. Power Savings Based on Duty Cycle of TxEnable
If the TxEnable invert bit (Register 0x02, Bit 1) is set, the
function of this TXENABLE pin is inverted.
In interleaved mode, set-up and hold times of DATACLK out to
data in are the same as those shown in Figure 92 to Figure 95. It
is recommended that any toggling of TXENABLE occur
concurrently with the digital data input updating. In this way,
timing margins between DATACLK, TXENABLE, and digital
input data are optimized.
Rev. A | Page 41 of 56
AD9776/AD9778/AD9779
REFERENCE
CLOCK IN
DATA
CLOCK OUT
tSREFCLK
tSDATACLK
tHREFCLK
tHDATACLK
INPUT
DATA
Figure 92. Timing Specifications, PLL Enabled or Disabled, Interpolation = 1×
SYNC_IN
tH_SYNC
tS_SYNC
REFERENCE
CLOCK IN
DATA
CLOCK OUT
tHREFCLK
tHDATACLK
tSREFCLK
tSDATACLK
INPUT
DATA
Figure 93. Timing Specifications, PLL Enabled or Disabled, Interpolation = 2×
SYNC_IN
tH_SYNC
tS_SYNC
REFERENCE
CLOCK IN
DATA
CLOCK OUT
tSREFCLK
tSDATACLK
tHREFCLK
tHDATACLK
INPUT
DATA
Figure 94. Timing Specifications, PLL Enabled or Disabled, Interpolation = 4×
SYNC_IN
tH_SYNC
tS_SYNC
REFERENCE
CLOCK IN
DATA
CLOCK OUT
tSREFCLK
tSDATACLK
tHREFCLK
tHDATACLK
INPUT
DATA
Figure 95. Timing Specifications, PLL Enabled or Disabled, Interpolation = 8×
Rev. A | Page 42 of 56
AD9776/AD9778/AD9779
and must be no greater than DATACLK for proper
Specifications are given in Table 19 for the drift of input data set
up and hold time vs. temperature, as well as the data keep out
window (KOW). Note that although these specifications do
drift, the length of the keep out window, where input data is
invalid, changes very little over temperature.
synchronization. There is no limit on how slow the SYNC_I
signal can be driven. As long as the set up and hold timing
relationship between SYNC_I and REFCLK given in Table 19 is
met, the input data is latched on the immediate next rising edge
of REFCLK. Note that a rising edge of DATACLK out occurs
concurrently with the next REFCLK rising edge, after a short
propagation delay. Although this propagation delay is not
specified, input data setup and hold timing information is given
with respect to REFCLK in and DATACLK out in Figure 92 to
Figure 95. Also, note that in 1× interpolation, because there is
no phase ambiguity, there is no need to use the SYNC_I signal.
Table 19. AD9779 Timing Specifications vs. Temperature
Min
tS
(ns)
Min
tH
(ns)
Max
KOW
(ns)
Timing
Parameter
Temperature
−4±°C
+25°C
REFCLK to DATA
−±.8
−1.1
−1.3
+1.8
+2.1
+2.5
+2.2
+2.5
+2.9
−±.4
−±.ꢀ
−±.9
+1.±
+1.3
+1.4
+1.5
+1.3
+1.4
+1.5
+±.8
+85°C
Valid Timing Window
DATACLK to DATA −4±°C
In addition to the timing requirements of SYNC_I with respect
to REFCLK, it is important to understand that the valid timing
window for SYNC_I is limited by the internal DAC sample rate.
This is shown in Figure 96. When the tS and tH requirements are
met, the valid timing window for SYNC_I extends only as far as
one period of the internal DAC sample rate (minus tS and tH).
Failure to meet this timing specification can potentially result in
erroneous data being latched into the AD9779 digital inputs.
+25°C
+85°C
SYNC_I to
REFCLK
−4±°C to +85°C −±.2
SYNCHRONIZATION OF INPUT DATA TO DATACLK
OUTPUT (PIN 37)
As an example, if the AD9779 input data rate is 122.88 MSPS
and the REFCLK is the same, with the AD9779 in 4× interpola-
tion, the DAC sample rate is 1/491.52 MHz or about 2 ns. With
a tS of −0.2 ns and tH of 1.0 ns, this gives a valid timing window
for SYNC_I of
Synchronizing the input data bus to the DATACLK out signal is
achieved by meeting the timing relationships between DATACLK
and DATA timing specified in Table 19. If the user is synchro-
nizing the input data to the DATACLK out, the sync input
(SYNC_I) signal does not need to be applied and can be ignored
(connect to GND).
2 ns − 0.8 ns = 1.2 ns
SYNCHRONIZATION OF INPUT DATA TO THE
REFCLK INPUT (PIN 5 AND PIN 6) WITH PLL
ENABLED OR DISABLED
The timing window of the digital input data to REFCLK can be
moved in increments of one internal REFCLK cycle by using
the REFCLK OFFSET register (Register 0x7, Bits<4:0>).
Synchronizing the input data bus to the REFCLK input requires
the use of the SYNC_I input pins (Pin 13 and Pin 14). If the
SYNC_I input is not used, there is a phase ambiguity between
the DATACLK out and the REFCLK in. This ambiguity matches
the interpolation rate in which the AD9779, for example, is
currently operating. Because input data is latched on the rising
edge of DATACLK, it is impossible for the user to determine
onto which one of the multiple internal DACCLK edges (as an
example, one of four edges in 4× interpolation) the input data
actually latches. For the user to specifically determine the exact
edge of REFCLK on which the data is being latched, a rising
edge must be periodically applied to SYNC_I. The frequency of
the SYNC_I signal must be equal to fDAC/2N, N being an integer,
Because SYNC_I can be run at the same frequency as REFCLK
when the PLL is enabled, best practice suggests that in this con-
dition, REFCLK and SYNC_I originate from the same source.
This limits the variation in time between these two signals and
makes the overall timing budget easier to achieve. A slight delay
may be necessary on the REFCLK path in this configuration to
add more timing margin between REFCLK and SYNC_I (see
Table 19 for timing relationship).
REFCLK
tS
tH
tDAC_SAMPLE
tDAC_SAMPLE
SYNC_I
Figure 96. Valid Timing Relationship for SYNC_I to REFCLK
Rev. A | Page 43 of 56
AD9776/AD9778/AD9779
TEK RUN: 5.00GS/s
SAMPLE
Using Data Delay to Meet Timing Requirements
Δ
: 7.84nS
To meet strict timing requirements at input data rates of up to
250 MSPS, the AD977x has a fine timing feature. Fine timing
adjustments are made by programming values into the data
clock delay register (Register 0x04, Bits<7:4>). This register can
be used to add delay between the REFCLK in and the
@: 32.44nS
2
DATACLK out. Figure 97 shows the default delay present when
DATACLK delay is disabled. The disable function bit is found
in Register 0x02, Bit 4. Figure 98 shows the delay present when
DATACLK delay is enabled and set to 0000. Figure 99 indicates
the delay when DATACLK delay is enabled and set to 1111.
Note that the setup and hold times specified for data to
DATACLK are defined for DATACLK delay disabled.
1
CH1 1.00V
Ω
CH2 500mV
Ω
M2.00ns
CH1
420mV
Figure 99. Delay from REFCLK to DATACLK Out with DATACLK Delay = 1111
TEK RUN: 5.00GS/s
SAMPLE
The difference between the minimum delay shown in Figure 98
and the maximum delay shown in Figure 99 is the range
programmable using the DATACLK delay register. The delay
(in absolute time) when programming DATACLK delay
between 0000 and 1111 is a linear extrapolation between these
two figures. The typical delays per increment over temperature
are shown in Table 20.
Δ: 4.48nS
@: 40.28nS
2
Table 20. Data Delay Line Typical Delays Over Temperature
Delays
−40°C +25°C +85°C Unit
Delay Between Disabled and
Enabled
3ꢀ±
416
432
ps
1
Average Delay per Increment 1ꢀ1
183
19ꢀ
ps
CH1 1.00VΩ
CH2 500mVΩ M2.00ns
CH1
420mV
The frequency of DATACLK out depends on several program-
mable settings: interpolation, zero stuffing, and interleaved/
dual port mode, all of which have an effect on the REFCLK
frequency. The divisor function between REFCLK and
DATACLK is equal to the values shown in Table 21.
Figure 97. Delay from REFCLK to DATACLK with DATACLK Delay Disabled
TEK RUN: 5.00GS/s
SAMPLE
Δ
: 4.76nS
@: 35.52nS
Table 21. REFCLK to DATACLK Divisor Ratio
Interpolation Zero Stuffing
Input Mode
Divisor
2
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Dual port
Dual port
Dual port
Dual port
Interleaved
Interleaved
Interleaved
Interleaved
Dual port
Dual port
Dual port
Dual port
Interleaved
Interleaved
Interleaved
Interleaved
1
2
4
8
Invalid
1
2
4
2
4
8
16
1
2
4
8
1
CH1 1.00V
Ω
CH2 500mV
Ω
M2.00ns
CH1
420mV
Figure 98. Delay from REFCLK to DATACLK Out with DATACLK Delay = 0000
Rev. A | Page 44 of 56
AD9776/AD9778/AD9779
In addition to this divisor function, DATACLK can be divided
by up to an additional factor of 4, according to the state of the
DATACLK divide register (Register 0x03, Bits<5:4>). For more
details, see Table 22).
Necessary corrections can be made by adjusting DATACLK
delay and the DATACLK invert bit (Register 2, Bit 2).
DATACLK delay can then be swept to find the range over which
the timing is valid. The final value for data delay should be the
value that corresponds to the middle of the valid timing range.
If a valid timing range is not found during this sweep, the user
should invert the DATACLK invert bit and repeat the process.
Table 22. Extra DATACLK Divisor Ratio
Register 0x03, Bits<5:4>
Divider Ratio
±±
±1
1±
11
1
2
4
1
Multiple DAC Synchronization
The AD9779 has programmable features that allow the CMOS
digital data bus inputs and internal filters on multiple devices to
be synchronized. This means that the DATACLK output signal
on one AD9779 can be used to register the output data for a data
bus delivering data to multiple AD9779s. The details of this opera-
tion are given in the Analog Devices Application Note AN-822.
The maximum divisor resulting from the combination of the
values in Table 21, and the DATACLK divide register is 32.
Manual Input Timing Correction
Correction of input timing can be achieved manually. The
correction function is controlled by Register 0x03, Bits<7:6>.
The function is programmed as shown in Table 23.
Table 23. Input Timing Correction Mode
Register 0x03, Bits<7:6>
Function
±±
±1
1±
11
Error check disabled
Reserved
Reserved
Reserved
Rev. A | Page 45 of 56
AD9776/AD9778/AD9779
EVALUATION BOARD OPERATION
The AD977x evaluation board is designed to optimize the DAC
performance and the speed of the digital interface, yet remains
user friendly. To operate the board, the user needs a power
source, a clock source, and a digital data source. The user also
needs a spectrum analyzer or an oscilloscope to look at the DAC
output. The diagram in Figure 100 illustrates the test setup. A
sine or square wave clock works well as a clock source. The dc
offset on the clock is not a problem, since the clock is ac-coupled
on the evaluation board before the REFCLK inputs. All
necessary connections to the evaluation board are shown in
more detail in Figure 101.
The evaluation board comes with software that allows the user
to program the SPI port. Via the SPI port, the devices can be
programmed into any of its various operating modes. When
first operating the evaluation board, it is useful to start with a
simple configuration, that is, a configuration in which the SPI
port settings are as close as possible to the default settings. The
default software window is shown in Figure 102. The arrows
indicate which settings need to be changed for an easy first time
evaluation. Note that this implies that the PLL is not being used
and that the clock being used is at the speed of the DAC output
sample rate. For a more detailed description of how to use the
PLL, see the PLL Loop Filter Bandwidth section.
CLOCK
GENERATOR
ADAPTER
CABLES
CLKIN
SPI PORT
SPECTRUM
ANALYZER
DIGITAL
PATTERN
GENERATOR
AD9779
EVALUATION
BOARD
CLOCK IN
1.8V POWER SUPPLY
3.3V POWER SUPPLY
DATACLK OUT
Figure 100. Typical Test Setup
AUX33
DVDD18
DVDD33
CVDD18
AVDD33
J2
5V Supply
P4 Digital Input Connector
J1 CLOCK IN
MODULATOR
OUTPUT
S5 OUTPUT 1
JP4
JP15
JP8
+5V
JP14
AD9779
AD8349
JP3
JP16
JP2
GND
JP17
S6 OUTPUT 2
LOCAL OSC
INPUT
S7 DCLKOUT
ANALOG
DEVICES
AD9779/8/6
REV D
SPI PORT
Figure 101. AD977x Evaluation Board Showing All Connections
Rev. A | Page 46 of 56
AD9776/AD9778/AD9779
1. SET INTERPOLATION RATE
2. SET INTERPOLATION FILTER MODE
3. SET INPUT DATA FORMAT
4. SET DATACLK POLARITY TO MATCH INPUT TIMING
Figure 102. SPI Port Software Window
The default settings for the evaluation board allow the user to
view the differential outputs through a transformer that
converts the DAC output signal to a single-ended signal. On the
evaluation board, these transformers are designated T1A, T2A,
T3A, and T4A. There are also four common-mode transformers
on the board that are designated T1B, T2B, T3B, and T4B. The
recommended operating setup places the transformer and
common-mode transformer in series. A pair of transformers
and common-mode transformers are installed on each DAC
output, so that the pairs can be set up in either order. As an
example, for the frequency range of dc to 30 MHz, it is
recommended that the transformer be placed right after the
DAC. Above DAC output frequencies of 30 MHz, it is
recommended that the common-mode transformer is placed
right after the DAC outputs, followed by the transformer.
Rev. A | Page 4ꢀ of 56
AD9776/AD9778/AD9779
MODIFYING THE EVALUATION BOARD TO USE
THE AD8349 ON-BOARD QUADRATURE
MODULATOR
The evaluation board contains an Analog Devices AD8349
quadrature modulator. The AD977x and AD8349 provide an
easy-to-interface DAC/modulator combination that can be
easily evaluated on the evaluation board. To route the DAC
output signal to the quadrature modulator, the following
jumper settings must be made:
Unsoldered: JP14, JP15, JP16, JP17
Soldered: JP2, JP3, JP4, JP8
The DAC output area of the evaluation board is shown in
Figure 103. The jumpers that need to be changed to use the
AD8349 are circled. Also circled are the 5 V and GND
connections for the AD8349.
Figure 103. Photo of Evaluation Board, DAC Output Area
Rev. A | Page 48 of 56
AD9776/AD9778/AD9779
EVALUATION BOARD SCHEMATICS
Figure 104. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface
Rev. A | Page 49 of 56
AD9776/AD9778/AD9779
R10
50Ω
T2B
T1B
R7
T3A
T4A
S6
1
JP16
JP17
0Ω
1
3
6
4
1
3
6
4
3
2
1
4
6
3
2
1
4
6
2
R8
0Ω
P
S
P
S
R11
50Ω
ADTL1-12
T2A
ADTL1-12
T1A
TC1-1T
T3B
TC1-1T
T4B
R9
50Ω
R6
JP14
JP15
0Ω
6
4
1
6
4
1
4
6
3
1
4
6
3
1
2
3
2
3
R5
0Ω
2
S
P
S
P
1
R11
50Ω
S5
TC1-1T
TC1-1T
ADTL1-12
ADTL1-12
DGND;5
JP3
JP2
C62
0.1µF
C33
1nF
C34
1nF
D2N
D2P
DPWR33
JP4
JP8
C40
0.1µF
D1P
D1N
C61
1nF
C37
0.1µF
C38
0.1µF
R63
10Ω
C35
1nF
C18
1nF
C60
0.1µF
C24
1nF
C25
1nF
CR1
VAL
C39
0.1µF
C9
0.1µF
6.3V
C59
1nF
C10
0.1µF
CR2
C36
1nF
VAL
C8
C1
4.7µF
C2
4.7µF
10µF
R56
10Ω
VOLT
R64
1kΩ
R64
1kΩ
VOLT
C27
1nF
AVDD33
C58
C11
1nF
0.1µF
DVDD33
DVDD18
C57
0.1µF
C3
4.7µF
VOLT
C56
1nF
C29
1nF
C55
0.1µF
C12
0.1µF
C31
1nF
C30
1nF
C14
0.1µF
C13
0.1µF
+
C6
4.7µF
C4
4.7µF
C5
4.7µF
VOLT
VOLT
DVDD33
CVDD18
DVDD18
CLK_N
CLK_P
JP7
P2D15
S15
S2
R59
1
2
3
6
5
4
S16
1
22Ω
1
2
2
R58
22Ω
DPWR33
1
DPWR33
2
DATACLK
S7
1
U11
U10
Q
U10
Q
R26
22Ω
4
10
R32
C84
0.1µF
25Ω
4
5
3
2
1
3
1
2
5
11
13
12
9
JP18
PRE
PRE
Y
GND
A
NC
J
J
2
6
7
JP13
VCC
K
Q_
K
Q_
DPWR33
R26
22Ω
CLR
CLR
14
74LCX112
15
74LCX112
C78
SN74LVC1G34
4.7µF
VOLT
C7
4.7µF
VOLT
C15
1nF
C32
0.1µF
Figure 105. Evaluation Board, Rev. D, Circuitry Local to Devices
Rev. A | Page 5± of 56
AD9776/AD9778/AD9779
R15
20Ω
C80
2.1pF
C53
0.1µF
D1N
C64
17.2pF
C50
17.2pF
R20
40Ω
R17
150Ω
L10
55nH
AUX1_N
R4
150Ω
R19
300Ω
C81
2.1pF
JP13
AUX1_P
R12
150Ω
C63
17.2pF
L11
55nH
C52
17.2pF
R21
40Ω
R22
147.5Ω
D1P
R16
20Ω
MODULATED OUTPUT
J4
C47
100pF
1
VDDM
2
2
+
C41
10µF
10V
C73
0.1µF
C72
0.1µF
DGND2
DGND2
2
DGND2
VDDM
R14
1kΩ
JP1
2
DGND2
C51
0.1µF
LOCAL OSC OUTPUT
J5
C74
T4
100pF
1
1
2
3
5
4
2
2
S
P
DGND2
DGND2
C75
100pF
2
ETC1-1-13
DGND2
R24
20Ω
C83
2.1pF
C54
0.1µF
D2N
C44
17.2pF
C65
17.2pF
R60
40Ω
JP9
R25
150Ω
L10
55nH
JP10
AUX2_N
2
R2
150Ω
R27
300Ω
C82
2.1pF
JP13
DGND2
AUX2_P
R3
150Ω
C43
17.2pF
L11
55nH
C79
17.2pF
R61
40Ω
R62
147.5Ω
D2P
R23
20Ω
Figure 106. Evaluation Board, Rev. D, AD8349 Quadrature Modulator
CLK_P
CVDD18
C19
T2
0.1
μ
F
J1
CLKIN
C16
R28
25
R30
1k
4
5
3
2
1
DNB
Ω
Ω
R13
VAL
P
S
C17
0.1μF
R29
25
R31
300
Ω
Ω
C23
0.1μF
ETC1-1-13
CLK_N
Figure 107. Evaluation Board, Rev. D, DAC Clock Interface
Rev. A | Page 51 of 56
AD9776/AD9778/AD9779
P4
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
P4
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
P4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
P4
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
P4
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
CSB
SD1
SCLK
SD0
P2D0
P2D2
P2D4
P2D6
P2D8
P2D10
P2D12
P2D14
P2D1
P2D3
P2D5
P2D7
P2D9
P2D11
P2D13
P2D15
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
P1D0
P1D2
P1D4
P1D6
P1D8
P1D10
P1D12
P1D14
P1D1
P1D3
P1D5
P1D7
P1D9
P1D11
P1D13
P1D15
PKG_TYPE = MOLEX110
VAL
PKG_TYPE = MOLEX110
VAL
PKG_TYPE = MOLEX110
PKG_TYPE = MOLEX110
VAL
PKG_TYPE = MOLEX110
VAL
VAL
DGND
BLK
DGND1
BLK
Figure 108. Evaluation Board, Rev. D, Digital Input Buffers
5V
1
J2
2
U2
1
2
3
4
CVDD18_IN
JP19
P2
1
C86
1μF
C85
1μF
ADP3339-1-8
2
VAL
CNTERM_2P
U3
4
1
2
3
DVDD18_IN
JP20
C89
1μF
C88
1μF
ADP3339-1-8
U4
4
1
2
3
DVDD33_IN
AVDD33_IN
DPWR33_IN
JP21
JP22
JP23
C92
1μF
C91
1μF
ADP3339-3-3
U7
4
1
2
3
C93
1μF
C94
1μF
ADP3339-3-3
U8
4
1
2
3
C96
1μF
C97
1μF
ADP3339-3-3
Figure 109. Evaluation Board, On-Board Voltage Regulators
Rev. A | Page 52 of 56
AD9776/AD9778/AD9779
Figure 110. Evaluation Board, Rev. D, Top Silk Screen
Figure 111. Evaluation Board, Rev. D, Top Layer
Rev. A | Page 53 of 56
AD9776/AD9778/AD9779
Figure 112. Evaluation Board, Rev. D, Layer 2
Figure 113. Evaluation Board, Rev. D, Layer 3
Rev. A | Page 54 of 56
AD9776/AD9778/AD9779
Figure 114. Evaluation Board, Rev. D, Bottom Layer
Figure 115. Evaluation Board, Rev. D, Bottom Silkscreen
Rev. A | Page 55 of 56
AD9776/AD9778/AD9779
OUTLINE DIMENSIONS
16.00 BSC SQ
1.20
0.75
0.60
0.45
MAX
14.00 BSC SQ
100
1
76
75
76
100
75
1
SEATING
PLANE
PIN 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
51
25
25
26
50
50
26
0.20
0.09
1.05
1.00
0.95
6.50
NOM
7°
3.5°
0°
0.15
0.05
COPLANARITY
0.08
0.27
0.22
0.17
0.50 BSC
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
NOTES
2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 116. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9ꢀꢀ6BSVZ1
AD9ꢀꢀ6BSVZRL1
AD9ꢀꢀ8BSVZ1
AD9ꢀꢀ8BSVZRL1
AD9ꢀꢀ9BSVZ1
AD9ꢀꢀ9BSVZRL1
Temperature Range
−4±°C to +85°C
−4±°C to +85°C
−4±°C to +85°C
−4±°C to +85°C
−4±°C to +85°C
−4±°C to +85°C
Package Description
1±±-lead TQFP_EP
1±±-lead TQFP_EP
1±±-lead TQFP_EP
1±±-lead TQFP_EP
1±±-lead TQFP_EP
1±±-lead TQFP_EP
Package Option
SV-1±±-1
SV-1±±-1
SV-1±±-1
SV-1±±-1
SV-1±±-1
SV-1±±-1
AD9ꢀꢀ6-EB
AD9ꢀꢀ8-EB
AD9ꢀꢀ9-EBZ1
Evaluation Board
Evaluation Board
Evaluation Board
1 Z = RoHS Compliant Part.
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05361-0-3/07(A)
Rev. A | Page 56 of 56
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