AD9781BCPZRL7 [ADI]
IC PARALLEL, WORD INPUT LOADING, 14-BIT DAC, QCC72, 10 X 10 MM, ROHS COMPLIANT, MO-220VNND-3, LFCSP-72, Digital to Analog Converter;
| 型号： | AD9781BCPZRL7 |
| 厂家： | 
ADI |
| 描述： | IC PARALLEL, WORD INPUT LOADING, 14-BIT DAC, QCC72, 10 X 10 MM, ROHS COMPLIANT, MO-220VNND-3, LFCSP-72, Digital to Analog Converter 输入元件 转换器 |
| 文件： | 总32页 (文件大小：964K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 12-/14-/16-Bit, LVDS
Interface 600 MSPS DACs
AD9780/AD9781/AD9783
Preliminary Technical Data
FEATURES
GENERAL DESCRIPTION
High dynamic range, dual DAC parts
The AD9780/AD9781/AD9783 include pin-compatible, high
dynamic range, dual digital-to-analog converters (DACs) with
12-/14-/16-bit resolutions, and sample rates of up to 600 MSPS.
The devices include specific features for direct conversion
transmit applications, including gain and offset compensation,
and they interface seamlessly with analog quadrature
modulators such as the ADL5370.
Low noise and intermodulation distortion
Single carrier WCDMA ACLR = 80 dBc @ 61.44 MHz IF
Innovative switching output stage permits useable outputs
beyond Nyquist frequency
LVCMOS inputs with dual-port or optional interleaved
single-port operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. Some pin-programmable features are also
offered for those applications without a controller.
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, RoHS compliant, 72-lead LFCSP
PRODUCT HIGHLIGHTS
1. Low noise and intermodulation distortion (IMD) enables
high quality synthesis of wideband signals.
APPLICATIONS
Wireless infrastructure
2. Proprietary switching output for enhanced dynamic
performance.
WCDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications
LMDS/MMDS, point-to-point
RF signal generators, arbitrary waveform generators
3. Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
FUNCTIONAL BLOCK DIAGRAM
CLKP
CLKN
AD9783 DUAL LVDS DAC
IOUT1P
IOUT1N
16-BIT
I DAC
INTERFACE LOGIC
IOUT2P
IOUT2N
16-BIT
Q DAC
LVDS
INTERFACE
D(15:0)
GAIN
DAC
V
, V
IA IB
GAIN
DAC
AUX1P
AUX1N
OFFSET
DAC
INTERNAL
REFERENCE
AND
SERIAL
PERIPHERAL
INTERFACE
AUX2P
AUX2N
OFFSET
DAC
BIAS
Figure 1
Rev. PrG
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD9780/AD9781/AD9783
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
General Operation of the Serial Interface............................... 18
Instruction Byte.......................................................................... 18
MSB/LSB Transfers .................................................................... 19
Serial Interface Port Pin Descriptions ..................................... 19
SPI Register Map ............................................................................ 20
SPI Register Descriptions.............................................................. 21
SPI Port, RESET, and Pin Mode............................................... 23
Parallel Data Port Interface....................................................... 23
Optimizing the Parallel Port Timing....................................... 23
Driving the CLK Input .............................................................. 25
Full-Scale Current Generation ................................................. 25
DAC Transfer Function............................................................. 26
Analog Modes of Operation ..................................................... 26
Power Dissipation....................................................................... 27
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Digital Specifications ................................................................... 4
AC Specifications.......................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Serial Peripheral Interface......................................................... 18
Rev. PrG | Page 2 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.
Table 1.
AD9780
Typ
AD9781
Typ
AD9783
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
RESOLUTION
12
14
16
Bits
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current1
Output Compliance Range
Output Resistance
Gain DAC Monotonicity Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset
±±.13
±±.2ꢀ
±±.ꢀ
±1
±2
±4
LSB
LSB
–±.±±1
±
±2
2±.2
+±.±±1
–±.±±1
±
±2
2±.2
+±.±±1
–±.±±1
±
±2
+±.±±1
% FSR
% FSR
mA
V
MΩ
8.66
–1.±
31.66
+1.±
8.66
–1.±
31.66
+1.±
8.66
–1.±
2±.2 31.66
+1.±
1±
1±
1±
±.±4
1±±
3±
±.±4
1±±
3±
±.±4
1±±
3±
ppm/°C
ppm/°C
ppm/°C
Gain
Reference Voltage
AUX DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Range (Source)
Output Compliance Range (Sink)
Output Resistance
AUX DAC Monotonicity Guaranteed
REFERENCE
1±
1±
1±
+2
1.6
1.6
1
Bits
mA
V
V
MΩ
–2
±
±.8
+2
1.6
1.6
–2
±
±.8
+2
1.6
1.6
–2
±
±.8
1
1
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
1.2
ꢀ
1.2
ꢀ
1.2
ꢀ
V
kΩ
3.13
1.7±
3.3
1.8
3.47
1.9±
3.13
1.7±
3.3
1.8
3.47
1.9±
3.13
1.7±
3.3
1.8
3.47
1.9±
V
V
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
3.13
1.7±
3.3
1.8
3.47
1.9±
3.13
1.7±
3.3
1.8
3.47
1.9±
3.13
1.7±
3.3
1.8
3.47
1.9±
V
V
POWER CONSUMPTION
fDAC = ꢀ±± MSPS, IF = 2± MHz
fDAC = 6±± MSPS, IF = 1± MHz
Power-Down Mode
SUPPLY CURRENTS2
AVDD33
CVDD18
DVDD33
DVDD18
V × I
44±
3
V × I
ꢀ
V × I V × I
44±
V × I V × I
44±
mW
mW
mW
3
ꢀ
3
3ꢀ
ꢀꢀ
34
13
68
ꢀ8
38
1ꢀ
8ꢀ
ꢀꢀ
34
13
68
ꢀ8
38
1ꢀ
8ꢀ
ꢀꢀ
34
13
68
ꢀ8
38
1ꢀ
8ꢀ
mA
mA
mA
mA
1 Based on a 1± kΩ external resistor.
2 FDAC = ꢀ±± MSPS, FOUT = 2± MHz.
Rev. PrG | Page 3 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
DAC CLOCK INPUT (CLKP, CLKN)
Peak-to-Peak Voltage at CLKP and CLKN
Common-Mode Voltage
4±±
3±±
6±±
8±±
4±±
16±±
ꢀ±±
mV
mV
MSPS
Maximum Clock Rate
SERIAL PERIPHERAL INTERFACE (CMOS Interface)
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
4±
12.ꢀ
12.ꢀ
MHz
ns
ns
Minimum Pulse Width Low
DIGITAL INPUT DATA (LVDS Interface)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Input Differential Input Impedance,
Maximum LVDS Input Rate (Per DAC)
8±±
-1±±
16±±
+1±±
mV
mV
mV
Ω
2±
8±
6±±
12±
MSPS
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3.
AD9780
Min Typ
AD9781
Max Min Typ
AD9783
Max Min Typ
Parameter
Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 6±± MSPS, fOUT = 2± MHz
fDAC = 6±± MSPS, fOUT = 12± MHz
fDAC = 6±± MSPS, fOUT = 48± MHz (Mix Mode)
fDAC = 6±± MSPS, fOUT = ꢀ8± MHz (Mix Mode)
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 6±± MSPS, fOUT = 2± MHz
79
67
ꢀ8
ꢀ8
78
66
62
ꢀ6
8±
68
ꢀ9
6±
dBc
dBc
dBc
dBc
91
8±
6±.ꢀ
ꢀ8
93
7ꢀ
61.ꢀ
ꢀ9
86
79
66
ꢀ9
dBc
dBc
dBc
dBc
fDAC = 6±± MSPS, fOUT = 12± MHz
fDAC = 6±± MSPS, fOUT = 48± MHz (Mix Mode)
fDAC = 6±± MSPS, fOUT = ꢀ8± MHz (Mix Mode)
NOISE SPECTRAL DENSITY (NSD) One-Tone
fDAC = 6±± MSPS, fOUT = 4± MHz
fDAC = 6±± MSPS, fOUT = 12± MHz
fDAC = 6±± MSPS, fOUT = 48± MHz (Mix Mode)
fDAC = 6±± MSPS, fOUT = ꢀ8± MHz (Mix Mode)
−1ꢀ7
−1ꢀ4.ꢀ
−1ꢀ2
−1ꢀ2
−162
−1ꢀ6.ꢀ
−1ꢀ2
−1ꢀ1
−16ꢀ
−1ꢀ7
−1ꢀ3
−1ꢀ2
dBc
dBc
dBc
dBc
WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDAC = 491.ꢀ2 MSPS, fOUT = 2± MHz
fDAC = 491.ꢀ2 MSPS, fOUT = 8± MHz
fDAC = 491.ꢀ2 MSPS, fOUT = 411.ꢀ2 MHz
fDAC = 491.ꢀ2 MSPS, fOUT = 471.ꢀ2 MHz
−81
−8±
−71
−69
−82.ꢀ
−82.ꢀ
−68
−82
−81
−69
−7±
dBc
dBc
dBc
dBc
−69
Rev. PrG | Page 4 of 32
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
AD9780/AD9781/AD9783
Table 4.
THERMAL RESISTANCE
With
Parameter
Respect to
Rating
Thermal resistance tested using JEDEC standard 4-layer
thermal test board with no airflow.
AVDD33, DVDD33
AGND, DGND, −±.3 V to +3.6 V
CGND
Table 5.
Package Type
DVDD18, CVDD18
AGND, DGND, −±.3 V to +1.98 V
CGND
θJA
Unit
AGND
DGND
CGND
REFIO
DGND, CGND
AGND, CGND
AGND, DGND
AGND
−±.3 V to +±.3 V
−±.3 V to +±.3 V
−±.3 V to +±.3 V
−±.3 V to
AVDD33 + ±.3 V
CP-72-1 (Exposed Pad Soldered to PCB)
2ꢀ
°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
IOUT1P, IOUT1N, IOUT2P,
IOUT2N, AUX1P, AUX1N,
AUX2P, AUX2N
AGND
−1.± V to
AVDD33 + ±.3 V
D1ꢀ to D±
DGND
CGND
DGND
−±.3 V to
DVDD33 + ±.3 V
−±.3 V to
CVDD18 + ±.3 V
CLKP, CLKN
ESD CAUTION
CSB, SCLK, SDIO, SDO
–±.3 V to
DVDD33 + ±.3 V
Junction Temperature
Storage Temperature
+12ꢀ°C
−6ꢀ°C to +1ꢀ±°C
Rev. PrG | Page ꢀ of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D11P
1
2
3
4
5
6
7
8
9
54 FS ADJ
PIN 1
INDICATOR
53 RESET
52 CSB
51 SCLK
50 SDIO
49 SDO
48 DVSS
47 DVDD18
46 NC
AD9780
(TOP VIEW)
D11N 10
D10P 11
D10N 12
D9P 13
D9N 14
D8P 15
D8N 16
D7P 17
D7N 18
45 NC
44 NC
43 NC
42 NC
41 NC
40 NC
39 NC
38 D0N
37 D0P
NC = NO CONNECT
Figure 2. AD9780 Pin Configuration
Table 6. AD9780 Pin Function Descriptions
Pin No.
Mnemonic
CVDD18
CVSS
Description
1, 6
2, ꢀ
Clock Supply Voltage (1.8 V).
Clock Supply Return.
3, 4
CLKP, CLKN
DVSS
DVDD18
D11P, D11N
Differential DAC Sampling Clock Input.
Digital Common.
Digital Supply Voltage (1.8 V).
LVDS Data Input (MSB)
7, 28, 48
8, 47
9, 1±
11 to 24, 31 to 36 D1±P to D1P, D1±N toD1N LVDS Data Inputs.
2ꢀ, 26
27
29, 3±
37, 38
DCOP, DCON
DVDD33
DCIP, DCIN
D±P, D±N
NC
Differential Data Clock Output. LVDS clock at the DAC sample rate.
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
Differential Data Clock Input. LVDS clock aligned with input data.
LVDS Data Input (LSB).
39 to 46
No Connection. Leave these pins floating.
49
SDO
Serial Port Data Output.
ꢀ±
ꢀ1
SDIO
SCLK
Serial Port Data Input (4-Wire Mode). Bidirectional serial data line (3-wire mode).
Serial Port Clock Input.
ꢀ2
CSB
Serial Port Chip Select (Active Low).
ꢀ3
RESET
Chip Reset (Active High).
ꢀ4
FS ADJ
Full-Scale Current Output Adjust.
ꢀꢀ
REFIO
AVDD33
AVSS
Analog Reference Input/Output (1.2 V Nominal).
Analog Supply Voltage (3.3 V).
Analog Common.
ꢀ6, ꢀ7, 71, 72
ꢀ8, 61, 64, 67, 7±
ꢀ9
6±
62, 63
6ꢀ, 66
68
IOUT2P
IOUT2N
AUX2P,AUX2N
AUX1N,AUX1P
IOUT1N
IOUT1P
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
Differential Auxiliary DAC current output (Channel 2).
Differential Auxiliary DAC current output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
69
Rev. PrG | Page 6 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D13P
1
2
3
4
5
6
7
8
9
54 FS ADJ
PIN 1
INDICATOR
53 RESET
52 CSB
51 SCLK
50 SDIO
49 SDO
48 DVSS
47 DVDD18
46 NC
AD9781
(TOP VIEW)
D13N 10
D12P 11
D12N 12
D11P 13
D11N 14
D10P 15
D10N 16
D9P 17
45 NC
44 NC
43 NC
42 D0N
41 D0P
40 D1N
39 D1P
38 D2N
37 D2P
D9N 18
NC = NO CONNECT
Figure 3. AD9781 Pin Configuration
Table 7. AD9781 Pin Function Descriptions
Pin No.
Mnemonic
CVDD18
CVSS
Description
1, 6
2, ꢀ
Clock Supply Voltage (1.8 V).
Clock Supply Return.
3, 4
CLKP, CLKN
DVSS
DVDD18
D13P, D13N
Differential DAC Sampling Clock Input.
Digital Common.
Digital Supply Voltage (1.8 V).
LVDS Data Input (MSB).
7, 28, 48
8, 47
9, 1±
11 to 24, 31 to 4± D12P, D12N to D1P, D1N LVDS Data Inputs.
2ꢀ, 26
27
29, 3±
41, 42
DCOP,DCON
DVDD33
DCIP, DCIN
D±P, D±N
NC
Differential Data Clock Output. LVDS clock at the DAC sample rate.
Digital Input and Output pad ring supply voltage (3.3 V).
Differential Data Clock Input. LVDS clock aligned with input data.
LVDS Data Input (LSB).
43 to 46
No connection. Leave these pins floating.
49
SDO
Serial Port Data Output.
ꢀ±
ꢀ1
SDIO
SCLK
Serial Port Data Input (4-Wire Mode). Bidirectional serial data line (3-wire mode).
Serial Port Clock Input.
ꢀ2
CSB
Serial Port Chip Select (Active Low).
ꢀ3
RESET
Chip Reset (Active High).
ꢀ4
FS ADJ
Full-Scale Current Output Adjust.
ꢀꢀ
REFIO
AVDD33
AVSS
Analog Reference Input/Output (1.2 V nominal).
Analog Supply Voltage (3.3 V).
Analog Common.
ꢀ6, ꢀ7, 71, 72
ꢀ8, 61, 64, 67, 7±
ꢀ9
6±
62, 63
6ꢀ, 66
68
IOUT2P
IOUT2N
AUX2P,AUX2N
AUX1N,AUX1P
IOUT1N
IOUT1P
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
Differential Auxiliary DAC current output (Channel 2).
Differential Auxiliary DAC current output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
69
Rev. PrG | Page 7 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
CVDD18
CVSS
CLKP
CLKN
CVSS
1
2
3
4
5
6
7
8
9
54 FS ADJ
PIN 1
INDICATOR
53 RESET
52 CSB
51 SCLK
50 SDIO
49 SDO
48 DVSS
47 DVDD18
46 D0N
45 D0P
44 D1N
43 D1P
42 D2N
41 D2P
40 D3N
39 D3P
38 D4N
37 D4P
CVDD18
DVSS
DVDD18
D15P
D15N 10
D14P 11
D14N 12
D13P 13
D13N 14
D12P 15
D12N 16
D11P 17
D11N 18
AD9783
(TOP VIEW)
Figure 4. AD9783 Pin Configuration
Table 8. AD9783 Pin Function Descriptions
Pin No.
Mnemonic
CVDD18
CVSS
Description
1, 6
2, ꢀ
Clock Supply Voltage (1.8 V).
Clock Supply Return.
3, 4
CLKP, CLKN
DVSS
DVDD18
D1ꢀP, D1ꢀN
Differential DAC Sampling Clock Input.
Digital Common.
Digital Supply Voltage (1.8 V).
LVDS Data Input (MSB).
7, 28, 48
8, 47
9, 1±
11 to 24, 31 to 44 D14P, D14N to D1P, D1N LVDS Data Inputs.
2ꢀ, 26
27
29, 3±
4ꢀ, 46
DCOP, DCON
DVDD33
DCIP, DCIN
D±P, D±N
SDO
Differential Data Clock Output. LVDS clock at the DAC sample rate.
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
Differential Data Clock Input. LVDS clock aligned with input data.
LVDS Data Input (LSB).
49
Serial Port Data Output.
ꢀ±
ꢀ1
SDIO
SCLK
Serial Port Data Input (4-Wire Mode). Bidirectional serial data line (3-wire mode).
Serial Port Clock Input.
ꢀ2
CSB
Serial Port Chip Select (Active Low).
ꢀ3
RESET
Chip RESET (active High).
ꢀ4
FS ADJ
Full-Scale Current Output Adjust.
ꢀꢀ
REFIO
AVDD33
AVSS
Analog Reference Input/Output (1.2 V nominal).
Analog Supply Voltage (3.3 V).
Analog Common.
ꢀ6, ꢀ7, 71, 72
ꢀ8, 61, 64, 67, 7±
ꢀ9
6±
62, 63
6ꢀ, 66
68
IOUT2P
IOUT2N
AUX2P,AUX2N
AUX1N,AUX1P
IOUT1N
IOUT1P
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
Differential Auxiliary DAC Current Output (Channel 2).
Differential Auxiliary DAC Current Output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are ±s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
69
Rev. PrG | Page 8 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
TYPICAL PERFORMANCE CHARACTERISTICS
1.5
0.4
0.2
0
1.0
0.5
–0.2
–0.4
–0.6
0
–0.5
–1.0
–0.8
–1.0
–1.2
–1.4
–1.5
–2.0
–2.5
–1.6
0
0
0
16384
32768
CODE
49152
49152
49152
65535
65535
65535
0
0
0
16384
32768
CODE
49152
65535
65535
65535
Figure 5. AD9783 INL 85°C
Figure 8. AD9783 DNL 85°C
5
4
3
2
1
0
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1
–2
–3
–1.6
16384
32768
CODE
16384
32768
CODE
49152
Figure 6. AD9783 INL 25°C
Figure 9. AD9783 DNL 25°C
5
4
3
2
1
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
–2
–3
–1.0
16384
32768
CODE
16384
32768
CODE
49152
Figure 7. AD9783 INL −40°C
Figure 10. AD9783 DNL −40°C
Rev. PrG | Page 9 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
0.059
–0.060
–0.179
–0.297
–0.416
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
0
0
0
0
0
4096
8192
12288
16383
16383
4096
4096
8192
12288
16383
CODE
CODE
Figure 11. AD9781 INL 85°C
Figure 14. AD9781 DNL 20mA FS 85°C
0.1
0
0.6
0.4
0.2
–0.1
0
–0.2
–0.3
–0.2
–0.4
–0.6
–0.8
–1.0
–0.4
–0.5
0
4096
8192
12288
16383
4096
8192
12288
CODE
CODE
Figure 12. AD9781 INL −40°C
Figure 15. AD9781 DNL −40°C
0.2
0.2
0.1
0
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.6
0
1024
2048
3072
1024
2048
3072
4096
CODE
CODE
Figure 13. AD9780 INL −40°C
Figure 16. AD9780 INL 85°C
Rev. PrG | Page 1± of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
90
85
100
95
90
85
80
75
70
65
60
55
50
45
40
250MSPS
80
75
70
65
60
55
50
45
40
+25°C
400MSPS
–40°C
600MSPS
+85°C
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
0
30
60
90
120 150 180 210 240 270 300
fOUT (MHz)
Figure 17. AD9783 SFDR vs. FOUT Over FDAC in Baseband and Mix Modes
Figure 20. AD9783 SFDR vs. FOUT Over Temperature, 600 MSPS
100
95
100
95
90
85
80
75
70
65
60
55
50
45
40
250MSPS
90
85
20mA
80
75
70
65
60
55
50
45
40
30mA
600MSPS
400MSPS
10mA
0
30
60
90
120 150 180 210 240 270 300
fOUT (MHz)
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
Figure 18. AD9783 SFDR vs. FOUT Over Analog Output, 25°C, 600 MSPS
Figure 21. AD9783 IMD vs. FOUT Over FDAC in Baseband and Mix Modes
95
90
100
95
90
20mA
85
80
75
70
65
60
55
50
45
40
85
–3dBFS
80
30mA
75
70
10mA
65
–6dBFS
0dBFS
60
55
50
45
40
0
30
60
90
120 150 180 210 240 270 300
fOUT (MHz)
0
30
60
90
120 150 180 210 240 270 300
fOUT (MHz)
Figure 19. AD9783 SFDR vs. FOUT Over Digital Input Level, 25°C, 600 MSPS
Figure 22. AD9783 IMD vs. FOUT Over Analog Output, 25°C, 600 MSPS
Rev. PrG | Page 11 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
95
–140
–143
–146
–149
–152
–155
–158
–161
–164
–167
–170
0dBFS
90
–3dBFS
85
–6dBFS
80
75
70
65
60
55
50
45
40
250MSPS
400MSPS
600MSPS
0
30
60
90
120 150 180 210 240 270 300
fOUT (MHz)
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
Figure 23. AD9783 IMD vs. FOUT Over Digital Input Level, 25C, 600MSPS
Figure 26. AD9783 8-Tone NSD vs. FOUT Over FDAC Baseband and Mix Modes
95
90
85
–140
–143
–146
–40°C
80
–149
+85°C
–152
75
+25°C
70
–155
65
60
55
50
45
40
+85°C
–158
–40°C
+25°C
–161
–164
–167
–170
0
30
60
90
120 150 180 210 240 270 300
fOUT (MHz)
0
50
100
150
150
150
300
fOUT (MHz)
Figure 24. AD9783 IMD vs. FOUT Over Temperature, 600MSPS
Figure 27. AD9783 1-Tone NSD vs. FOUT Over Temperature, 600MSPS
–140
–140
–143
–146
–149
–152
–143
–146
–149
–152
–155
–158
–161
–164
–167
–170
250MSPS
400MSPS
–155
+25°C
600MSPS
–158
+85°C
–161
–164
–40°C
–167
–170
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
0
50
100
150
200
250
300
fOUT (MHz)
Figure 25. AD9783 1-Tone NSD vs. FOUT Over FDAC Baseband and Mix Modes
Figure 28. AD9783 8-Tone NSD vs. FOUT Over Temperature, 600MSPS
Rev. PrG | Page 12 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
–50
–55
–60
–50
–55
–60
–65
–70
–75
–80
–85
–90
491.52MSPS
–65
–70
–75
–80
–85
–90
0dB
245.76MSPS
–3dB
0
100
200
300
400
500
0
100
200
300
400
500
fOUT (MHz)
fOUT (MHz)
Figure 29. AD9783 ACLR For First Adjacent Band 1-Carrier WCDMA Baseband
and Mix Modes
Figure 32. AD9783 ACLR for First Adjacent Channel 2-Carrier WCDMA Over
Digital Input Level Baseband and Mix Modes, 491.52 MSPS
–50
–55
–60
–65
–50
–55
–60
–65
–70
–70
–3dB
245.76MSPS
491.52MSPS
–75
–75
–80
–85
–90
–80
0dB
–85
–90
0
100
200
300
400
500
0
100
200
300
400
500
fOUT (MHz)
fOUT (MHz)
Figure 30. AD9783 ACLR For Second Adjacent Band 1-Carrier WCDMA
Baseband and Mix Modes
Figure 33. AD9783 ACLR for Second Adjacent Channel 2-Carrier WCDMA
Over Digital Input Level Baseband and Mix Modes, 491.52 MSPS
–50
–55
–60
–65
–50
–55
–60
–65
245.76MSPS
491.52MSPS
–70
–75
–80
–85
–90
–70
–75
–80
–85
–90
–3dB
0dB
0
100
200
300
400
500
0
100
200
300
400
500
fOUT (MHz)
fOUT (MHz)
Figure 31. AD9783 ACLR For Third Adjacent Band 1-Carrier WCDMA
Baseband and Mix Modes
Figure 34. AD9783 ACLR for Third Adjacent Channel 2-Carrier WCDMA Over
Digital Input Level Baseband and Mix Modes, 491.52 MSPS
Rev. PrG | Page 13 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
–50
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–55
–60
–65
–70
–75
–80
–85
–90
0dB
NORMAL MODE
–3dB
MIX MODE
0
100
200
300
400
500
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
fOUT (MHz)
Figure 35. AD9783 ACLR for First Adjacent Channel 4-Carrier WCDMA Over
Digital Input Level Baseband and Mix Modes, 491.52 MSPS
Figure 38. Nominal Power In The Fundamental, 20 mA FS 600 MSPS
–50
–55
–60
0.8
0.6
0.4
–3dB
–65
0.2
0
–70
0dB
–0.2
–0.4
–0.6
–0.8
–75
–80
–85
–90
0
4096
8192
12288
16383
0
100
200
300
400
500
fOUT (MHz)
CODE
Figure 39. AD9781 INL 20 mA FS
Figure 36. AD9783 ACLR for Second Adjacent Channel 4-Carrier WCDMA
Over Digital Input Level Baseband and Mix Modes, 491.52 MSPS
0.1
0
–50
–55
–60
–0.1
–65
–70
–75
–80
–85
–90
–3dB
–0.2
–0.3
0dB
–0.4
–0.5
0
4096
8192
12288
16383
0
100
200
300
400
500
fOUT (MHz)
CODE
Figure 40. AD9781 DNL 20 mA FS
Figure 37. AD9783 ACLR for Third Adjacent Channel 4-Carrier WCDMA Over
Digital Input Level Baseband and Mix Modes, 491.52 MSPS
Rev. PrG | Page 14 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
100
95
90
85
80
75
70
65
60
55
50
45
40
–50
–55
–60
–65
–70
–75
–80
–85
–90
FIRST
ADJACENT
CHANNEL
THIRD
ADJACENT
SECOND
CHANNEL
ADJACENT
CHANNEL
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
0
100
200
300
400
500
fOUT (MHz)
Figure 41. AD9781 SFDR vs. FOUT in Baseband and Mix Modes, 600 MSPS
Figure 44. AD9781 ACLR For 1-Carrier WCDMA Baseband and Mix Modes,
491.52 MSPS
100
95
90
85
80
75
70
65
60
55
50
45
40
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
–0.6
0
1024
2048
3072
4096
CODE
Figure 42. AD9781 IMD vs. FOUT in Baseband and Mix Modes, 600 MSPS
Figure 45. AD9780 INL 20 mA FS
–140
–142
–144
–146
–148
–150
0.04
0.02
0
1-TONE
–152
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–154
–156
–158
–160
8-TONE
–162
–164
–166
–168
–170
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
0
1024
2048
3072
4096
CODE
Figure 43. AD9781 1-Tone, 8-Tone NSD vs. FOUT in Baseband and Mix Modes,
600 MSPS
Figure 46. AD9780 DNL, 20 mA FS
Rev. PrG | Page 1ꢀ of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
–140
–142
–144
–146
–148
–150
–152
–154
–156
–158
–160
–162
–164
–166
–168
–170
100
95
90
85
80
75
70
65
60
55
50
45
40
1-TONE
8-TONES
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
0
60
120 180 240 300 360 420 480 540 600
fOUT (MHz)
Figure 47. AD9780 SFDR vs. FOUT in Baseband and Mix Modes, 600 MSPS
Figure 49. AD9780 1-Tone, 8-Tone NSD vs. FOUT in Baseband and Mix Modes,
600 MSPS
100
95
90
85
80
75
70
65
60
55
50
45
40
–50
–55
–60
FIRST
–65
–70
–75
–80
–85
–90
ADJACENT
CHANNEL
SECOND
THIRD
ADJACENT
CHANNEL
ADJACENT
CHANNEL
0
100
200
300
400
500
600
0
100
200
300
400
500
fOUT (MHz)
fOUT (MHz)
Figure 48. AD9780 IMD vs. FOUT in Baseband and Mix Modes, 600 MSPS
Figure 50. AD9780 ACLR For 1-Carrier WCDMA Baseband and Mix Modes,
491.52 MSPS
Rev. PrG | Page 16 of 32
Preliminary Technical Data
TERMINOLOGY
AD9780/AD9781/AD9783
Power Supply Rejection
Linearity Error (Integral Nonlinearity or INL)
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero scale to full scale.
Settling Time
The time required for the output to reach and remain within a
specified error band around its final value, measured from the
start of the output transition.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal between dc and the
frequency equal to half the input data rate.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Total Harmonic Distortion (THD)
Offset Error
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the difference between the output
when all inputs are set to 1 and the output when all inputs are
set to 0.
Adjacent Channel Leakage Ratio (ACLR)
The ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect of
wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference drift, the drift is
reported in ppm per degree Celsius.
Rev. PrG | Page 17 of 32
AD9780/AD9781/AD9783
THEORY OF OPERATION
Preliminary Technical Data
The Phase 1 instruction byte defines whether the upcoming
data transfer is a read or write, the number of bytes in the data
transfer, and a reference register address for the first byte of the
data transfer. A logic high on the CSB pin followed by a logic
low resets the SPI port to its initial state and defines the start of
the instruction cycle. From this point, the next eight rising
SCLK edges define the eight bits of the instruction byte for the
current communication cycle.
The AD9780/AD9781/AD9783 combine many features to make
them very attractive for wired and wireless communications
systems. The dual DAC architecture facilitates easy interface to
common quadrature modulators when designing single
sideband transmitters. In addition, the speed and performance
of the devices allows wider bandwidths and more carriers to be
synthesized than in previously available products.
All features and options are software programmable through
the SPI port.
The remaining SCLK edges are for Phase 2 of the communication
cycle, which is the data transfer between the serial port control-
ler and the system controller. Phase 2 can be a transfer of 1, 2, 3,
or 4 data bytes as determined by the instruction byte. Using
multibyte transfers is usually preferred although single-byte
data transfers are useful to reduce CPU overhead or when only
a single register access is required.
SERIAL PERIPHERAL INTERFACE
SDO
AD9780
SPI
PORT
SDIO
SCLK
CSB
All serial port data is transferred to and from the device in
synchronization with the SCLK pin. Input data is always latched
on the rising edge of SCLK whereas output data is always valid
after the falling edge of SCLK. Register contents change
immediately upon writing to the last bit of each transfer byte.
Figure 51. SPI Port
The serial peripheral interface (SPI) port is a flexible,
synchronous serial communications port allowing easy
interface to many industry-standard microcontrollers and
microprocessors. The port is compatible with most
synchronous transfer formats including both the Motorola SPI®
and Intel® SSR protocols.
Anytime synchronization is lost, the device has the ability to
asynchronously terminate an I/O operation whenever the CSB
pin is taken to logic high. Any unwritten register content data is
lost if the I/O operation is aborted. Taking CSB low then resets the
serial port controller and restarts the communication cycle.
The interface allows read and write access to all registers that
configure the AD9780/AD9781/AD9783. Single or multiple
byte transfers are supported as well as MSB-first or LSB-first
transfer formats. Serial data input/output can be accomplished
through a single bidirectional pin (SDIO) or through two
unidirectional pins (SDIO/SDO).
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 9.
Table 9.
MSB
LSB
B0
The serial port configuration is controlled by Register 0x00,
Bits<7:6>. It is important to note that any change made to the
serial port configuration occurs immediately upon writing to
the last bit of this byte. Therefore, it is possible with a multibyte
transfer to write to this register and change the configuration in
the middle of a communication cycle. Care must be taken to
compensate for the new configuration within the remaining
bytes of the current communication cycle.
B7
B6
B5
B4
B3
B2
B1
R/W
N1
N±
A4
A3
A2
A1
A±
Bit 7, R/W, determines whether a read or a write data transfer
occurs after the instruction byte write. Logic high indicates a
read operation. Logic 0 indicates a write operation.
Bits<6:5>, N1 and N0, determine the number of bytes to be
transferred during the data transfer cycle. The bits decode as
shown in Table 10.
Use of a single-byte transfer when changing the serial port
configuration is recommended to prevent unexpected device
behavior.
Table 10. Byte Transfer Count
N1
N0
Description
GENERAL OPERATION OF THE SERIAL INTERFACE
±
±
1
1
±
1
±
1
Transfer one byte
Transfer two bytes
Transfer three bytes
Transfer four bytes
There are two phases to any communication cycle with the
AD9780/AD9781/AD9783: Phase1 and Phase 2. Phase 1 is the
instruction cycle, which writes an instruction byte into the
device. This byte provides the serial port controller with
information regarding Phase 2 of the communication cycle: the
data transfer cycle.
Rev. PrG | Page 18 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
Serial Port Data I/O (SDIO)
Bits<4:0>, A4, A3, A2, A1, and A0, determine which register is
accessed during the data transfer of the communications cycle.
For multibyte transfers, this address is a starting or ending
address depending on the current data transfer mode. For MSB-
first format, the specified address is an ending address or the
most significant address in the current cycle. Remaining
register addresses for multiple byte data transfers are generated
internally by the serial port controller by decrementing from
the specified address. For LSB-first format, the specified address
is a beginning address or the least significant address in the
current cycle. Remaining register addresses for multiple byte
data transfers are generated internally by the serial port
controller by incrementing from the specified address.
Data is always written into the device on this pin. However,
SDIO can also function as a bidirectional data output line. The
configuration of this pin is controlled by Register 0x00, Bit 7.
The default is Logic 0, which configures the SDIO pin as
unidirectional.
Serial Port Data Output (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. The configuration of this
pin is controlled by Register 0x00, Bit 7. If this bit is set to a
Logic 1, the SDO pin does not output data and is set to a high
impedance state.
MSB/LSB TRANSFERS
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register 0x00, Bit 6.
The default is Logic 0, which is MSB-first format.
CSB
SCLK
SDIO
SDO
When using MSB-first format (LSBFIRST = 0), the instruction
and data bit must be written from MSB to LSB. Multibyte data
transfers in MSB-first format start with an instruction byte that
includes the register address of the most significant data byte.
Subsequent data bytes are loaded into sequentially lower
address locations. In MSB-first mode, the serial port internal
address generator decrements for each byte of the multibyte
data transfer.
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5
D3 D2 D1 D0
0 0 0
N
N
0
0
D7 D6 D5
D3 D2 D1 D0
0 0 0
N
N
Figure 52. Serial Register Interface, MSB First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
When using LSB-first format (LSBFIRST = 1), the instruction
and data bit must be written from LSB to MSB. Multibyte data
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant data byte.
Subsequent data bytes are loaded into sequentially higher
address locations. In LSB-first mode, the serial port internal
address generator increments for each byte of the multibyte data
transfer.
A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2
D4 D5 D6 D7
N N N
0
0
0
N
N
D0 D1 D2
D4 D5 D6 D7
N N N
0
0
0
Figure 53. Serial Register Interface Timing LSB First
Use of a single-byte transfer when changing the serial port data
format is recommended to prevent unexpected device behavior.
–1
tS
fSCLK
CSB
SERIAL INTERFACE PORT PIN DESCRIPTIONS
tPWH
tPWL
Chip Select Bar (CSB)
SCLK
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communication lines. CSB must stay low during the entire
communication cycle. Incomplete data transfers are aborted
anytime the CSB pin goes high. SDO and SDIO pins go to a
high impedance state when this input is high.
tDS
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
SDIO
Figure 54. Timing Diagram for SPI Write Register
CSB
Serial Clock (SCLK)
The serial clock pin is used to synchronize data to and from the
device and to run the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is registered on
the rising edge of SCLK. All data is driven out on the falling
edge of SCLK.
SCLK
tDV
SDIO
SDO
DATA BIT N
DATA BIT N – 1
Figure 55. Timing Diagram for SPI Read Register
Rev. PrG | Page 19 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
SPI REGISTER MAP
Table 11.
Register Name
Addr Default Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI Control
±x±±
±x±2
±x±3
±x±4
±x±ꢀ
±x±6
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
SDIO_DIR
DATA
LSBFIRST
ONEPORT
PD_INPT
RESET
Data Control
Power Down
Setup and Hold
Timing Adjust
Seek
INVDCO
PD_DCO
SET<3:±>
PD_AUX2 PD_AUX1 PD_BIAS PD_CLK
HLD<3:±>
PD_DAC2 PD_DAC1
SAMP_DLY<4:±>
LVDS
Low
LVDS
High
SEEK
Mix Mode
±x±A
±x±B
±x±C
±x±±
±xF9
±x±1
DAC1MIX<1:±>
DAC2MIX<1:±>
DAC1FSC<9:8>
AUXDAC1<9:8>
DAC2FSC<9:8>
AUXDAC2<9:8>
DAC1 FSC
DAC1FSC<7:±>
DAC1 FSC MSBs
AUXDAC1
±x±D ±x±±
AUXDAC1<7:±>
AUXDAC1 MSB
DAC2 FSC
±x±E
±x±F
±x1±
±x11
±x12
±x1A
±x±±
±xF9
±x±1
±x±±
±x±±
±x±±
±x±±
±x±±
AUX1SGN AUX1DIR
DAC2FSC<7:±>
DAC2 FSC MSBs
AUXDAC2
AUXDAC2<7:±>
BISTCLR
AUXDAC2 MSB
BIST Control
AUX2SGN AUX2DIR
BISTEN
BISTRD
BIST Result 1 Low ±x1B
BIST Result 1 High ±x1C
BISTRES1<7:±>
BISTRES1<1ꢀ:8>
BISTRES2<7:±>
BISTRES2<1ꢀ:8>
VERSION<3:±>
BIST Result 2 Low ±x1D ±x±±
BIST Result 2 High
Hardware Version
±x1E
±x1F
±x±±
N/A
DEVICE<2:±>
Rev. PrG | Page 2± of 32
Preliminary Technical Data
SPI REGISTER DESCRIPTIONS
AD9780/AD9781/AD9783
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 12.
Register
Address Bit Name
Function
SPI Control
±x±±
7
SDIO_DIR
±, Operate SPI in 4-wire mode. The SDI pin operates as an input only pin.
1, Operate SPI in 3-wire mode. The SDI pin operates as a bidirectional data line.
±, MSB first per SPI Standard
6
LSBFIRST
1, LSB first per SPI Standard
Note: Only Change LSB/MSB order in single-byte instructions to avoid erratic behavior
due to bit order errors.
ꢀ
7
RESET
DATA
±, Execute Software reset of SPI and controllers, reload default register values except
register ±x±±.
1, Set Software reset, write ± on the next (or any following) cycle to release the reset.
Data
Control
±x±2
±x±3
±, DAC input data is two’s compliment binary format.
1, DAC input data is unsigned binary format.
1, Inverts the Data Clock Output. Used for adjusting timing of input data.
1, Power down Data Clock Output driver circuit.
1, Power Down Input..
4
7
6
ꢀ
4
3
2
1
±
INVDCO
Power
Down
PD_DCO
PD_INPT
PD_AUX2
PD_AUX1
PD_BIAS
PD_CLK
1, Power down AUX2 DAC
1, Power down AUX1 DAC.
1, Power down Voltage Reference Bias circuit.
1, Power down DAC Clock input circuit..
1, Power down DAC2
PD_DAC2
PD_DAC1
1, Power down DAC1.
Setup and
Hold
±x±4
7:4 SET<3:±>
4-bit value used to determine input data setup timing.
3:± HLD<3:±>
4-bit value used to determine input data hold timing.
Timing
Adjust
±x±ꢀ
±x±6
4:± SAMP_DLY<4:±> ꢀ-bit values used to optimally posiion input data relative to internal sampling clock.
Seek
2
1
±
LVDS High
LVDS Low
SEEK
One of the LVDS inputs is above the input voltage limits of the IEEE reduced link
specification
One of the LVDS inputs is below the input voltage limits of the IEEE reduced link
specification
Indicator bit used with LVDS_SET and LVDS_HLD to determine input data timing
margin.
Mix Mode
±x±A
3:2 DAC1MIX<1:±>
1:± DAC2MIX<1:±>
DAC1FSC<9:±>
±± – Selects Normal Mode, DAC2.
±1 – Selects Return to Zero mode, DAC2.
1± - Selects Return to Zero mode, DAC2.
11 – Selects Mix mode, DAC2.
±± – Selects Normal Mode, DAC1.
±1 – Selects Return to Zero mode, DAC1.
1± - Selects Return to Zero mode, DAC1.
11 – Selects Mix mode, DAC1.
DAC1 FSC
±x±B
±x±C
DAC1 Full-Scale 1± bit adjustment word.
±x3FF, Sets DAC Full-Scale Output Current to the maximum value of 31.68mA .
±x2±±, Sets DAC Full-Scale Output Current to the nominal value of 2±.±mA.
±x±±±, Sets DAC Full-Scale Output Current to the minimum value of 8.64mA.
Rev. PrG | Page 21 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
Register
Address Bit Name
Function
AUXDAC1
±x±D
±x±E
7:± AUXDAC1<9:±>
1:± AUXDAC1<9:8>
AUXDAC1 output current adjustment word.
±x3FF, Sets AUXDAC1 Output Current to 2.± mA.
±x2±±, Sets AUXDAC1 Output Current to 1.± mA.
±x±±±, Sets AUXDAC1 Output Current to ±.± mA.
±, AUX1_P output pin is active.
7
6
AUX1SGN
1, AUX1_N output pin is active.
AUX1DIR
±, Configures AUX1 DAC output to source current.
1, Configures AUX1 DAC output to sink current.
DAC2 Full-Scale 1± bit adjustment word.
±x3FF, Sets DAC Full-Scale Output Current to the maximum value of 31.68mA .
±x2±±, Sets DAC Full-Scale Output Current to the nominal value of 2±.±mA.
±x±±±, Sets DAC Full-Scale Output Current to the minimum value of 8.64mA.
AUX DAC2 output current adjustment word.
±, AUX2_P output pin is active.
DAC2 FSC
AUXDAC2
±x±F
±x1±
DAC2FSC<9:±>
±x11
±x12
7:± AUXDAC2<9:±>
7
AUX2SGN
1, AUX2_N output pin is active.
6
AUX2DIR
±, Configures AUX2 DAC output to source current.
1, Configures AUX1 DAC output to sink current.
±x3FF, Sets AUXDAC2 Output Current to 2.± mA.
±x2±±, Sets AUXDAC2 Output Current to 1.± mA.
±x±±±, Sets AUXDAC2 Output Current to ±.± mA.
1, Enables and starts Built In Self Test.
1, Transfers BIST result registers to SPI for readback.
1, Reset BIST logic and clear BIST result registers.
Sixteen bit result generated by BIST 1.
1:±
BIST Control ±x1A
7
6
ꢀ
BISTEN
BISTRD
BISTCLR
BIST Result1 ±x1B
±x1C
7:± BISTRES1<1ꢀ:±>
7:±
BIST Result2 ±x1D
±x1E
7:± BISTRES2<1ꢀ:±>
7:±
Sixteen bit result generated by BIST 2.
Hardware
Version
±x1F
7:4 VERSION<3:±>
3:± DEVICE<3:±>
Read only register. Indicates the version of the chip.
Read only register. Indicates the device type.
Rev. PrG | Page 22 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
other words, it should be implemented as a seventeenth DATA
line with an alternating (010101…) bit sequence.
SPI PORT, RESET, AND PIN MODE
In general, when the AD9780/AD9781/AD9783 are powered
up, an active high pulse applied to the RESET pin should follow.
This insures the default state of all control register bits. In
addition, once the RESET pin goes low, the SPI port can be
activated, so, CSB should be held high.
DATA[15:0]
I DAC
FF
RETIMING
AND
DEMUX
FF
Q DAC
For applications without a controller, the AD9780/AD9781/
AD9783 also supports pin mode operation, which allows some
functional options to be pin, selected without the use of the SPI
port. Pin mode is enabled anytime the RESET pin is held high.
In pin mode, the four SPI port pins take on secondary functions
as shown in Table 13.
DCLK_IN
DDCI
SET_DLY
HLD_DLY
SEEK
FF
DDSS
CLK
DSS
CLOCK
DISTRIBUTION
SMP_DLY
DCLK_OUT
Figure 56. AD9873 Digital Data Port
Table 13. SPI Pin Functions (Pin Mode)
Pin
Name
OPTIMIZING THE PARALLEL PORT TIMING
Pin Mode Function
Before outlining the procedure for determining the delay for
SMP (that is, the positioning of DSS with respect to the DATA
signals), it is worthwhile describing the simplified block
diagram of the digital data port. As can be seen in Figure 56, the
DATA signals are latched-in on the rising and falling edges of
DSS. From there, the data is demultiplexed and retimed before
being sent to the DACs.
SDIO
DATA (Register ±x±2, Bit 7), bit value (1/±) equals pin
state (high/low)
Enable Mix Mode, if CSB is high, Register ±x±A is set to
±x±ꢀ putting both DAC1 and DAC2 into mix mode
Enable full power-down, if SDO is high, Register ±x±3
is set to ±xFF
CSB
SDO
The DCLK_IN signal provides timing information about the
parallel data as well as indicating the destination (that is, I DAC
or Q DAC) of the data. A delayed version of DCI is generated
by a delay element, SET and is referred to as DDCI. DDCI is
sampled by a delayed version of the DSS signal, labeled as DDSS
in Figure 56. DDSS is simply DSS delayed by a period of time,
HLD. The pair of delays, SET and HLD allow accurate timing
information to be extracted from DCLK_IN. Increasing the
delay of the HLD block, results in DCLK_IN being sampled
later in it’s cycle. Increasing the delay of the SET block, results in
DCLK_IN being sampled earlier in it’s cycle. The result of this
sampling is stored and can be queried by reading the SEEK bit.
Since DSS and DCLK_IN are the same frequency, the SEEK bit
should be a constant value. By varying the SET and HLD delay
blocks and seeing the effect on the SEEK bit, the setup and hold
timing of DSS with respect to DCLK_IN (and hence, DATA)
can be measured.
PARALLEL DATA PORT INTERFACE
The parallel port data interface consists of 18 differential LVDS
signals, DCO, DCI, and the sixteen DATA lines (DATA[15:0]),
as shown in Figure 56. DCO is the output clock generated by
theAD9780/AD9781/AD9783 that is used to clock out the data
from the digital data engine. The DATA lines transmit the
multiplexed I and Q data words for the I and Q DACs
respectively. The DCI provides timing information about the
parallel data as well as signals the I/Q status of the data.
As shown in Figure 56, the incoming LVDS data is latched by an
internally generated clock referred to as the data sampling
signal (DSS). DSS is a delayed version of the main DAC clock
signal CLKP/CLKN. Optimal positioning of the rising and
falling edges of DSS with respect to the incoming DATA signals
results in the most robust transmission of the DAC data.
Positioning the edges of DSS with respect to the DATA signals
is achieved by selecting the value of a programmable delay
element, SMP. A procedure for determining optimal value of
SMP is given in the Optimizing the Parallel Port Timing
section.
0ps
2500ps
5000ps
7500ps
10000ps
t1
t2
t3
I0
Q0
I1
Q1
I2
Q2
DATA
In addition to properly positioning the DSS edges, maximizing
the opening of the eye in the DCLK_IN and DATA signals
improves the reliability of the data port interface. The two
sources of degradation that reduce the eye in the DCLK_IN and
DATA signals are the jitter on these signals and the skew
between them. Therefore, it is recommended that the
DCLK_IN
tHLD0
tHLD0
DSS
SAMPLE 1
SAMPLE 2
SAMPLE 3
SAMPLE 4
SAMPLE 5
SAMPLE 6
DCLK_IN be generated in the same manner as the DATA
signals with the same output driver and data line routing. In
Figure 57. Digital Data Timing
The incremental units of SET, HLD, and SMP are in units of
real time, not fractions of a clock cycle. The nominal step size
Rev. PrG | Page 23 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
for SET and HLD is 80 psec. The nominal step size for SMP is
160 ps. Note that the value of SMP refers to Register 5, Bits[4:0],
SET refers to Register 4, Bits[7:4], and HLD refers to Register 4,
Bits[3:0].
the position marked Orig, to the position marked New in
the figure.
9. After programming the calculated value of SMP,
verification that the sampling edge occurs in the middle of
the valid data window can be done as follows. Set both SET
and HLD to zero. Increment SET until the SEEK bit goes
low and record that value. Reset SET to zero. Increment
HLD until SEEK goes low and record that value. The
recorded values of SET and HLD should be within two unit
delays of each other if SMP was set correctly.
Use the following steps to ensure the AD9780/AD9781/AD9783
is configured for a valid sampling time of the DATA signals.
Generally speaking, the procedure begins by finding the point
in its cycle that DCI is sampled by the rising edge of DSS. Based
on this information, a value of SMP is programmed to establish
a new and improved sampling point. This new sampling point is
then double checked to make sure it is optimally set.
It should be noted that the values of SET and HLD should both
be a minimum of 4. If either value is lower than this, then you
should check for excessive jitter on your DCLK_IN line, and
that the frequency of DCLK_IN does not exceed the datasheet
maximum.
1. Set the values of SMP, SET, and HLD to zero. Read and
record the value of the SEEK bit.
2. With SMP and SET set to 0, increment the HLD until the
SEEK bit toggles and record the HLD value. This measures
the hold time as shown in figure 2.
3. With SMP and HLD set to 0, increment the SET until the
SEEK bit toggles and record the SET value. This measures
the set-up time as shown in Figure 57.
4. Using the values of SMP, HLD, and SET, the value of SMP
can now be determined.
Another consideration in the timing of the digital data port is
the propagation delay variation from DATACLK_OUT to
DATACLK_IN. If this varies significantly (more than 25% of
SET or HLD) over time due to temperature changes or other
effects, then repeat this timing calibration procedure
accordingly.
5. If SEEK = 1, and HLD and SET are within 2 counts of each
other, then the sampling edge is well positioned and it is
unnecesary to increase the SMP delay. Also, if SEEK = 1
and HLD and SET are both greater than 12, then there is a
sufficient timing margin and it is unneccesary to increase
the SMP delay.
0ns
5ns
10ns
15ns
t1
t4
t5
I4
t2
t3
DATA
I0
Q0
I1
Q1
I2
Q2
I3
Q3
DCLK_IN
tHLD0
tSET0
6. If SEEK = 1, and SET is more than two counts higher than
HLD, then your timing resembles that shown in Figure 58.
Program the value of SMP to be
ORIGINAL
DSS_ORIG
DSS_NEW
tHLD
tSET
tSMP_DLY
PER − 40 × (SET − HLD)
SMP =
NEW
160
Figure 58. Digital Data Timing Calibration
Where PER is the period of the DAC Clock (CLK) period
in picoseconds. This moves the sampling edge of DSS from
the position marked Orig, to the position marked New in
the figure.
0ns
5ns
10ns
15ns
t1
t2
t3
t4
t5
I4
DATA
I0
Q0
I1
Q1
I2
Q2
I3
Q3
7. If SEEK = 1, and HLD is more than two counts higher than
SET, then your timing resembles that shown in Figure 59.
Program the value of SMP to be
DCLK_IN
tHLD0
ORIGINAL
tSET0
DSS_ORIG
DSS_NEW
tHLD
(HLD − SET)
tSMP_DLY
tSET
SMP =
4
NEW
This moves the sampling edge of DSS from the position
marked Orig to the position marked New in the figure.
Figure 59. Digital Data Timing Calibration
8. If SEEK = 0, then your timing resembles that shown in
Figure 60. Program the value of SMP to be
PER + 80 × (HLD − SET)
SMP =
320
Where PER is the period of the DAC Clock (CLK) period
in picoseconds. This moves the sampling edge of DSS from
Rev. PrG | Page 24 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
V
= 400mV
0ns
5ns
10ns
15ns
CM
t1
t2
t3
t4
t5
I4
CVDD18
1kΩ
I0
Q0
I1
Q1
I2
Q2
I3
Q3
DATA
1nF
CGND
0.1µF
1nF
287Ω
DCLK_IN
tHLD0
tSET0
Figure 63. DACCLK VCM Generator Circuit
ORIGINAL
DSS_ORIG
DSS_NEW
tHLD
FULL-SCALE CURRENT GENERATION
Internal Reference
tSET
tSMP_DLY
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
FSADJ (Pin54). A simplified block diagram of the reference
circuitry is shown in Figure 64. The recommended value for the
external resistor is 10 kΩ, which sets up an IREFERENCE in the
resistor of 120 μA, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear
function of this resistor, a high precision resistor improves gain
matching to the internal matching specification of the devices.
Internal current mirrors provide a current-gain scaling, where I
DAC or Q DAC gain is a 10-bit word in the SPI port register.
The default value for the DAC gain registers gives a full-scale
current output (IFS) of approximately 20 mA, where IFS is equal
to:
NEW
Figure 60. Digital Data Timing Calibration
DRIVING THE CLK INPUT
The CLK input requires a low jitter differential drive signal. It is
a PMOS input differential pair powered from the 1.8 V supply,
therefore, it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. While these input levels are not directly LVDS-
compatible, CLK can be driven by an offset ac-coupled LVDS
signal, as shown in Figure 61.
0.1µF
LVDS_P_IN
CLKP
50Ω
50Ω
V
= 400mV
CM
IFS = (86.6 + (0.220 × DAC gain))×1000 / R
LVDS_N_IN
CLKN
0.1µF
Figure 61. LVDS DACCLK Drive Circuit
AD9783
If a clean sine clock is available, it can be transformer-coupled
to CLK, as shown in Figure 61. Use of a CMOS or TTL clock is
also acceptable for lower sample rates. It can be routed through
a CMOS to LVDS translator, then ac-coupled, as described in
this section. Alternatively, it can be transformer-coupled and
clamped, as shown in Figure 62.
I DAC GAIN
1.2V BAND GAP
I DAC
REFIO
CURRENT
SCALING
DAC FULL SCALE
REFERENCE CURRENT
0.1µF
FS ADJ
Q DAC
10kΩ
Q DAC GAIN
Figure 64. Reference Circuitry
0.1µF
50Ω
TTL OR CMOS
CLK INPUT
CLKP
35
30
25
20
15
10
5
CLKN
50Ω
BAV99ZXCT
HIGH SPEED
DUAL DIODE
V
= 400mV
CM
Figure 62. TTL or CMOS DACCLK Drive Circuit
A simple bias network for generating VCM is shown in
Figure 63. It is important to use CVDD18 and CGND for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and can
degrade the DAC’s performance.
0
256
512
768
1024
DAC GAIN CODE
Figure 65. IFS vs. DAC Gain Code
Rev. PrG | Page 2ꢀ of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
from dc to fDAC. Additionally, there is a second subtle effect on
the output spectrum. The shifted spectrum is also shaped by a
second Sinc function with a first null at 2 × fDAC. The reason for
this shaping is that the data is not continuously varying at twice
the clock rate, but is simply repeated.
DAC TRANSFER FUNCTION
Each DAC output of the AD9780/AD9781/AD9783 drives two
complementary current outputs, IOUTP and IOUTN. IOUTP provides
a near IFS when all bits are high. For example,
DAC CODE = 2N − 1,
In the return-to-zero mode, the output is set to mid-scale every
other half clock cycle. The output is similar to the DAC output
in normal mode except that the output pulses are half the width
and half the area. Because the output pulses have half the width,
the sinc function is scaled in frequency by two and has a first
null at 2 × fDAC. Because the area of the pulses is half that of the
pulses in normal mode, the output power is half the normal
mode output power.
where:
N = 12-/14-/16-bits for AD9780/AD9781/AD9783 respectively),
while IOUTN provides no current.
The current output appearing at IOUTP and IOUTN is a function of
both the input code and IFS and can be expressed as
IOUTP = (DAC DATA/2N) × IFS
IOUTN = ((2N − 1) − DAC DATA)/2N × IFS
where DAC DATA = 0 to 2N − 1 (decimal representation).
(1)
(2)
D
D
D
D
D
D
D
D
D
D
9 10
INPUT DATA
1
2
3
4
5
6
7
8
DAC CLK
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTP and IOUTN
should be connected to matching resistive loads (RLOAD) that are
tied to analog common (AVSS). The single-ended voltage
output appearing at the IOUTP and IOUTN pins is
4-SWITCH
DAC OUTPUT
t
t
(
fS MIX MODE)
VOUTP = IOUTP × RLOAD
VOUTN = IOUTN × RLOAD
(3)
(4)
4-SWITCH
DAC OUTPUT
(RETURN-TO-
ZERO MODE)
Note that to achieve the maximum output compliance of 1 V at
the nominal 20 mA output current, RLOAD must be set to 50 Ω.
Also note that the full-scale value of VOUTP and VOUTN should
not exceed the specified output compliance range to maintain
specified distortion and linearity performance.
Figure 66. Mix Mode and RZ DAC Waveforms
The functions that shape the output spectrums for the three
modes of operation; normal mode, mix mode and return-to-
zero mode, are shown in Figure 67. Switching between the
analog modes reshapes the sinc roll off inherent at the DAC
output. This ability to change modes in the AD9780/
AD9781/AD9783 make the parts suitable for direct IF
applications. The user can place a carrier anywhere in the first
three nyquist zones depending on the operating mode selected.
The performance and maximum amplitude in all three nyquist
zones is impacted by this sinc roll off depending on where the
carrier is placed, as shown in Figure 67.
There are two distinct advantages to operating the AD9780/
AD9781/AD9783 differentially. First, differential operation
helps cancel common-mode error sources associated with IOUTP
and IOUTN, such as noise, distortion, and dc offsets. Second, the
differential code dependent current and subsequent output
voltage (VDIFF) is twice the value of the single-ended voltage
output (VOUTP or VOUTN), providing 2× signal power to the load.
VDIFF = (IOUTP – IOUTN) × RLOAD
(5)
ANALOG MODES OF OPERATION
0
TheAD9780/AD9781/AD9783 utilizes a proprietery quad-
switch architecture that lowers the distortion of the DAC by
eliminating a code dependent glitch that occurs with
conventional dual-switch architectures. This architecture
eliminates the code dependent glitches, but creates a constant
glitch at a rate of 2 × fDAC. For communications systems and
other applications requiring good frequency domain
performance from the DAC, this is seldom problematic.
MIX
RZ
–10
NORMAL
–20
The quad-switch architecture also supports two additional
modes of operation; mix mode and return-to-zero mode. The
waveforms of these two modes are shown in Figure 66. In the
mix mode, the output is inverted every other half clock cycle.
This effectively chops the DAC output at the sample rate. This
chopping has the effect of frequency shifting the sinc roll-off
–30
–40
0
0.5
1.0
fS
1.5
2.0
(
)
Figure 67. Transfer Function for Each Analog Operating Mode
Rev. PrG | Page 26 of 32
Preliminary Technical Data
AD9780/AD9781/AD9783
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
Auxiliary DACS
Two auxiliary DACs are provided on the AD9780/AD9781/
AD9783. A functional diagram is shown in Figure 68. The
auxiliary DACs are current output devices with two output pins,
AUXP and AUXN. The active pin can be programmed to either
source or sink current. When either sinking or sourcing, the full-
scale current magnitude is 2 mA. The available compliance range at
the auxiliary DAC outputs depends on whether the output is
configured to a sink or source current. When sourcing current,
the compliance voltage is 0 V to 1.6 V but when sinking current
the output compliance voltage is reduced to 0.8 V to 1.6 V.
Either output can be used, but only one output of the AUX DAC
(P or N) is active at any time. The inactive pin is always in a high
impedance state (>100 kΩ).
0
100
200
300
400
500
600
CLOCK SPEED (MSPS)
Figure 70. Power Dissipation, I Data Only, Single DAC Mode
0mA
TO
0.200
2mA
AUXP
V
BIAS
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
AUXN
0mA
SINK
OR
SOURCE
POSITIVE
OR
TO
2mA
NEGATIVE
Figure 68. Auxiliary DAC Functional Diagram
In a single sideband transmitter application, the combination of
the input referred dc offset voltage of the quadrature modulator
and the DAC output offset voltage can result in local oscillator
(LO) feedthrough at the modulator output, which degrades
system performance. The auxiliary DACs can be used to
remove the dc offset and the resulting LO feedthrough. The
circuit configuration for using the auxiliary DACs for
performing dc offset correction depends on the details of the
DAC and modulator interface. An example of a dc-coupled
configuration with low-pass filtering is outlined in the
Figure 69.
DVDD18
CVDD
300
0
100
200
400
500
600
CLOCK SPEED (MSPS)
Figure 71. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply I Data
Only
0.200
0.175
0.150
QUADRATURE
MODULATOR V+
0.125
AVDD33
0.100
0.075
AD9783
AUX
DAC1 OR
DAC2
QUAD MOD
I OR Q INPUTS
0.050
DVDD3
0.025
0
OPTIONAL
PASSIVE
FILTERING
AD9783
DAC1 OR
DAC2
0
100
200
300
400
500
600
CLOCK SPEED (MSPS)
Figure 72. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply,
I Data Only
25Ω TO 50Ω
25Ω TO 50Ω
Figure 69. DAC DC Coupled to Quadrature Modulator with Passive DC Shift
POWER DISSIPATION
Figure 70 through Figure 75 show the power dissipation of the
part in single DAC and dual DAC modes.
Rev. PrG | Page 27 of 32
AD9780/AD9781/AD9783
Preliminary Technical Data
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
AVDD33
DVDD3
0
100
200
300
400
500
600
0
100
200
300
400
500
600
CLOCK SPEED (MSPS)
CLOCK SPEED (MSPS)
Figure 73. . Power Dissipation, I and Q Data Only, Dual DAC Mode
Figure 75. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply I and
Q Data Dual DAC Mode
0.200
0.175
0.150
0.125
0.100
0.075
DVDD18
0.050
CVDD
0.025
0
0
100
200
300
400
500
600
CLOCK SPEED (MSPS)
Figure 74. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply I and Q
Data Dual DAC Mode
Rev. PrG | Page 28 of 32
Preliminary Technical Data
OUTLINE DIMENSIONS
AD9780/AD9781/AD9783
0.30
0.60 MAX
55
10.00
BSC SQ
0.23
0.18
0.60 MAX
PIN 1
INDICATOR
72
1
54
PIN 1
INDICATOR
0.50
BSC
9.75
BSC SQ
4.70
BSC SQ
TOP VIEW
EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
18
19
37
36
0.80 MAX
0.65 TYP
9.00 REF
1.00
0.85
0.80
12° MAX
EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
0.05 MAX
0.02 NOM
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-3
Figure 76. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm, Very Thin Quad
(CP-72-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−4±°C to +8ꢀ°C
Package Description
72-Lead LFCSP
72-Lead LFCSP
72-Lead LFCSP
72-Lead LFCSP
72-Lead LFCSP
72-Lead LFCSP
Evaluation Board
Evaluation Board
Evaluation Board
Package Option
AD978±BCPZ1
AD978±BCPZRL71
AD9781BCPZ1
AD9781BCPZRL71
AD9783BCPZ1
AD9783BCPZRL71
AD978±-EB1
CP-72-1
CP-72-1
CP-72-1
CP-72-1
CP-72-1
CP-72-1
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
−4±°C to +8ꢀ°C
AD9781-EB1
AD9783-EB1
1 Z = RoHS Compliant Part.
Rev. PrG | Page 29 of 32
AD9780/AD9781/AD9783
NOTES
Preliminary Technical Data
Rev. PrG | Page 3± of 32
Preliminary Technical Data
NOTES
AD9780/AD9781/AD9783
Rev. PrG | Page 31 of 32
AD9780/AD9781/AD9783
NOTES
Preliminary Technical Data
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06936-0-9/07(PrG)
Rev. PrG | Page 32 of 32
相关型号：
AD9783BCPZRL7
IC PARALLEL, WORD INPUT LOADING, 16-BIT DAC, QCC72, 10 X 10 MM, ROHS COMPLIANT, MO-220VNND-3, LFCSP-72, Digital to Analog Converter
ADI
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