AD9831ASTZ-REEL [ADI]
DIRECT DIGITAL SYNTGESIZER WAVEFORM GENERATOR; 直接数字SYNTGESIZER波形发生器
| 型号： | AD9831ASTZ-REEL |
| 厂家： | 
ADI |
| 描述： | DIRECT DIGITAL SYNTGESIZER WAVEFORM GENERATOR |
| 文件： | 总16页 (文件大小：540K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DIRECT DIGITAL SYNTHESIZER,
WAVEFORM GENERATOR
a
AD9831
FEATURES
GENERAL D ESCRIP TIO N
3 V/ 5 V Pow er Supply
25 MHz Speed
On-Chip SINE Look-Up Table
On-Chip 10-Bit DAC
Parallel Loading
T his DDS device is a numerically controlled oscillator employ-
ing a phase accumulator, a sine look-up table and a 10-bit D/A
converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.
Pow erdow n Option
72 dB SFDR
125 m W (5 V) Pow er Consum ption
40 m W (3 V) Pow er Consum ption
Clock rates up to 25 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is effected
by loading registers through the parallel microprocessor
interface.
LQFP
48-Pin
A powerdown pin allows external control of a powerdown
mode. T he part is available in a 48-pin LQFP package.
APPLICATIONS
DDS Tuning
Digital Dem odulation
Similar DDS products can be found at
http://www.analog.com/DDS
.
FUNCTIO NAL BLO CK D IAGRAM
DVDD
DGND
AVDD
REFOUT
AGND
FS ADJUST REFIN
MCLK
FSELECT
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
COMP
IOUT
FREQ0 REG
FREQ1 REG
12
PHASE
ACCUMULATOR
(32-BIT)
SIN
10-BIT DAC
MUX
Σ
ROM
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
AD9831
MUX
SLEEP
RESET
PARALLEL REGISTER
TRANSFER CONTROL
MPU INTERFACE
D15
WR A0
A1
A2
D0
PSEL1
PSEL0
REV. B
2011
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc.,
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 Fax: 781.461.3113
(V = +3.3 V ؎ 10%; +5 V ؎ 10%; AGND = DGND = 0 V; T = TMIN to T ; REFIN =
1
DD
A
MAX
AD9831–SPECIFICATIONS REFOUT; R = 3.9 k⍀; R
LOAD = 300 ⍀ for IOUT unless otherwise noted)
SET
P aram eter
AD 9831A
Units
Test Conditions/Com m ents
SIGNAL DAC SPECIFICAT IONS
Resolution
10
25
4
5
1.5
Bits
Update Rate (fMAX
IOUT Full Scale
)
MSPS nom
mA nom
mA max
V max
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
±1
±0.5
LSB typ
LSB typ
DDS SPECIFICAT IONS2
Dynamic Specifications
Signal to Noise Ratio
50
–53
dB min
dBc max
fMCLK = 25 MHz, fOUT = 1 MHz
fMCLK = 25 MHz, fOUT = 1 MHz
fMCLK = 6.25 MHz, fOUT = 2.11 MHz
5 V Power Supply
T otal Harmonic Distortion
Spurious Free Dynamic Range (SFDR)3
Narrow Band (±50 kHz)
–72
–70
–50
–60
1
dBc min
dBc min
dBc min
dBc typ
ms typ
3 V Power Supply
Wide Band (±2 MHz)
Clock Feedthrough
Wake-Up T ime4
Powerdown Option
Yes
VOLT AGE REFERENCE
Internal Reference @ +25°C
T MIN to TMAX
1.21
1.21 ± 7%
10
Volts typ
Volts min/max
MΩ typ
REFIN Input Impedance
Reference T C
REFOUT Output Impedance
100
300
ppm/°C typ
Ω typ
LOGIC INPUT S
VINH, Input High Voltage
VINL, Input Low Voltage
IINH, Input Current
VDD – 0.9
V min
0.9
10
10
V max
µA max
pF max
CIN, Input Capacitance
POWER SUPPLIES
AVDD
DVDD
IAA
IDD
IAA + IDD
2.97/5.5
2.97/5.5
12
V min/V max
V min/V max
mA max
5 V Power Supply
5 V Power Supply
3 V Power Supply
5 V Power Supply
2.5 + 0.33/MHz mA typ
5
15
24
1
mA max
mA max
mA max
Low Power Sleep Mode6
1 MΩ Resistor Tied Between REFOUT and AGND
NOT ES
1Operating temperature range is as follows: A Version: –40°C to +85°C.
2100% production tested.
3fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.
4See Figure 11. T o reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.
5Measured with the digital inputs static and equal to 0 V or DVDD.
6T he Low Power Sleep Mode current is typically 2 mA when a 1 M Ω resistor is not tied between REFOUT and AGND.
T he AD9831 is tested with a capacitive load of 50 pF. T he part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenu-
ated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.
Specifications subject to change without notice.
R
SET
3.9kΩ
10nF
FS
ADJUST
REFOUT
REFIN
AVDD
10nF
COMP
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
12
IOUT
SIN
ROM
10-BIT DAC
300Ω
50pF
AD9831
Figure 1. Test Circuit with Which Specifications Are Tested
–2–
REV. B
AD9831
(V = +3.3 V ؎ 10%, +5 V ؎ 10%; AGND = DGND = 0 V, unless otherwise noted)
TIMING CHARACTERISTICS DD
Lim it at
TMIN to TMAX
(A Version)
P aram eter
Units
Test Conditions/Com m ents
t1
t2
t3
t4*
t4A
t5
t6
t7
t8
40
16
16
8
8
8
t1
5
3
8
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
MCLK Period
MCLK High Duration
MCLK Low Duration
WR Rising Edge to MCLK Rising Edge
WR Rising Edge After MCLK Rising Edge
WR Pulse Width
Duration between Consecutive WR Pulses
Data/Address Setup T ime
Data/Address Hold T ime
FSELECT , PSEL0, PSEL1 Setup T ime Before MCLK Rising Edge
FSELECT , PSEL0, PSEL1 Setup T ime After MCLK Rising Edge
RESET Pulse Duration
*
t9*
t9A
t10
*
t1
*See Pin Description section.
Guaranteed by design but not production tested.
t1
MCLK
t2
t4
t3
t5
t4A
WR
t6
Figure 2. Clock Synchronization Tim ing
t6
t5
WR
t8
t7
A0, A1, A2
DATA
VALID DATA
VALID DATA
Figure 3. Parallel Tim ing
MCLK
t9A
t9
FSELECT
PSEL0, PSEL1
VALID DATA
VALID DATA
VALID DATA
t10
RESET
Figure 4. Control Tim ing
REV. B
–3–
AD9831
ABSO LUTE MAXIMUM RATINGS*
(T A = +25°C unless otherwise noted)
P IN CO NFIGURATIO N
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating T emperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction T emperature . . . . . . . . . . . . . . . . +150°C
48 47 46 45 44 43 42 41 40 39 38 37
1
2
AGND
REFOUT
SLEEP
DVDD
36
35
34
33
32
31
30
29
28
27
26
25
AGND
RESET
A0
PIN 1
IDENTIFIER
3
4
A1
5
DVDD
A2
AD9831
TOP VIEW
(Not to Scale)
6
DGND
DB0
DB1
DGND
DB2
DB3
DB4
DVDD
7
MCLK
θJA T hermal Impedance . . . . . . . . . . . . . . . . . 75°C/W
Lead T emperature, Soldering
LQFP
8
WR
9
DVDD
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V
10
11
FSELECT
PSEL0
PSEL1 12
13 14 15 16 17 18 19 20 21 22 23 24
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NC = NO CONNECT
REV. B
–4–
AD9831
P IN D ESCRIP TIO N
Mnem onic
Function
P O WER SUP P LY
AVDD
Positive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between AVDD
and AGND. AVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.
AGND
DVDD
Analog Ground.
Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD
and DGND. DVDD can have a value of +5 V ± 10% or +3.3 V ± 10%.
DGND
Digital Ground.
ANALO G SIGNAL AND REFERENCE
IOUT
Current Output. T his is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
FS ADJUST
Full-Scale Adjust Control. A resistor (RSET ) is connected between this pin and AGND. T his determines the
magnitude of the full-scale DAC current. T he relationship between RSET and the full-scale current is as follows:
IOUTFULL-SCALE = 12.5 × VREFIN/RSET
VREFIN = 1.21 V nominal, RSET = 3.9 kΩ typical
REFIN
Voltage Reference Input. T he AD9831 can be used with either the on-board reference, which is available from pin
REFOUT , or an external reference. T he reference to be used is connected to the REFIN pin. T he AD9831
accepts a reference of 1.21 V nominal.
REFOUT
COMP
Voltage Reference Output. T he AD9831 has an on-board reference of value 1.21 V nominal. T he reference is
made available on the REFOUT pin. T his reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
Compensation pin. T his is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
D IGITAL INTERFACE AND CO NTRO L
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. T he
output frequency accuracy and phase noise are determined by this clock.
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one
MCLK cycle as to when control is transferred to the other frequency register. T o avoid any uncertainty, a change
on FSELECT should not coincide with an MCLK rising edge.
WR
Write, Edge-T riggered Digital Input. T he WR pin is used when writing data to the AD9831. T he data is loaded
into the AD9831 on the rising edge of the WR pulse. T his data is then loaded into the destination register on the
MCLK rising edge. T he WR pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. T he WR rising
edge should occur before an MCLK rising edge. T he data will then be loaded into the destination register on the
MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the destination
register will be loaded on the next MCLK rising edge.
D0–D15
A0–A2
Data Bus, Digital Inputs for destination registers.
Address Digital Inputs. T hese address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1 Phase Select Input. T he AD9831 has four phase registers. T hese registers can be used to alter the value being
input to the SIN ROM. T he contents of the phase register can be added to the phase accumulator output, the
inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1
are sampled on the rising MCLK edge. T herefore, these inputs need to be in steady state when an MCLK rising
edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase
register.
SLEEP
Low Power Control, active low digital input. SLEEP puts the AD9831 into a low power mode. Internal clocks
are disabled and the DAC’s current sources and REFOUT are turned off. T he AD9831 is re-enabled by taking
SLEEP high.
RESET
Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog
output of midscale.
REV. B
–5–
AD9831
TERMINO LO GY
Integr al Nonlinear ity
±2 MHz about the fundamental frequency. The narrow band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of ±50 kHz about the fundamental frequency.
T his is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. T he
endpoints of the transfer function are zero scale, a point 0.5
LSB below the first code transition (000 . . . 00 to 000 . . . 01)
and full scale, a point 0.5 LSB above the last code transition
(111 . . . 10 to 111 . . . 11). T he error is expressed in LSBs.
Clock Feedthr ough
T here will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9831’s output spectrum.
D iffer ential Nonlinear ity
T his is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Table I. Control Registers
Register
Size
D escription
Signal to (Noise + D istor tion)
FREQ0 REG
32 Bits
Frequency Register 0. T his de-
fines the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. T he signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (fMCLK/2) but exclud-
ing the dc component. Signal to (Noise + Distortion) is
dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. T he theoretical Signal to (Noise + Distortion) ratio
for a sine wave input is given by
FREQ1 REG
32 Bits
Frequency Register 1. T his de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
PHASE0 REG 12 Bits
PHASE1 REG 12 Bits
PHASE2 REG 12 Bits
PHASE3 REG 12 Bits
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the
output of the phase accumulator.
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
where N is the number of bits. T hus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the con-
tents of this register are added to
the output of the phase accumulator.
Total H ar m onic D istor tion
T otal Harmonic Distortion (T HD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9831, T HD is defined as
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the con-
tents of this register are added to
the output of the phase accumulator.
2
(V22 +V32 +V42 +V52 +V6
THD = 20 log
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the
output of the phase accumulator.
O utput Com pliance
T he output compliance refers to the maximum voltage which
can be generated at the output of the DAC to meet the specifi-
cations. When voltages greater than that specified for the
output compliance are generated, the AD9831 may not meet
the specifications listed in the data sheet.
Table II. Addressing the Control Registers
A2
A1
A0
D estination Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FREQ0 REG 16 LSBs
FREQ0 REG 16 MSBs
FREQ1 REG 16 LSBs
FREQ1 REG 16 MSBs
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
Spur ious Fr ee D ynam ic Range
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of the MCLK frequency are
present at the output of a DDS device. T he spurious free dy-
namic range (SFDR) refers to the largest spur or harmonic
which is present in the band of interest. T he wide band SFDR
gives the magnitude of the largest harmonic or spur relative to
the magnitude of the fundamental frequency in the bandwidth
Table III. Frequency Register Bits
D15
D 0
MSB
LSB
Table IV. P hase Register Bits
D15
X
D14
X
D13
X
D12
X
D11
D 0
MSB
LSB
REV. B
–6–
Typical Performance Characteristics–AD9831
25
20
15
10
5
–40
AVDD = DVDD = +3.3V
T
= +25°C
A
–45
–50
+5V
25MHz
–55
10MHz
–60
–65
–70
–75
–80
+3.3V
0
5
10
15
MCLK FREQUENCY – MHz
20
25
0
0.1
0.2
0.3
0.4
f
/f
OUT MCLK
Figure 5. Typical Current Consum ption vs. MCLK
Frequency
Figure 8. Wide Band SFDR vs. fOUT/fMCLK for Various
MCLK Frequencies
–50
60
f
/f
= 1/3
OUT MCLK
AVDD = DVDD = +3.3V
AVDD = DVDD = +3.3V
f
= f /3
OUT
MCLK
–55
–60
–65
–70
–75
–80
55
50
45
40
10
15
20
25
10
15
20
25
MCLK FREQUENCY – MHz
MCLK FREQUENCY – MHz
Figure 6. Narrow Band SFDR vs. MCLK Frequency
Figure 9. SNR vs. MCLK Frequency
–40
60
55
50
45
40
f
/f
= 1/3
OUT MCLK
AVDD = DVDD = +3.3V
AVDD = DVDD = +3.3V
–45
–50
–55
–60
–65
10MHz
25MHz
0
0.1
0.2
0.3
0.4
10
15
20
25
f
/f
MCLK FREQUENCY – MHz
OUT MCLK
Figure 7. Wide Band SFDR vs. MCLK Frequency
Figure 10. SNR vs. fOUT/fMCLK for Various MCLK
Frequencies
REV. B
–7–
AD9831–Typical Performance Characteristics
10
0
AVDD = DVDD = +2.97V
–10
–20
–30
–40
–50
–60
–70
7.5
5.0
2.5
0
–80
–90
–100
–40
–30
–20
–10
0
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
TEMPERATURE – °C
VBW 1kHz
Figure 11. Wake-Up Tim e vs. Tem perature
Figure 14. fMCLK = 25 MHz, fOUT = 3.1 MHz, Frequency
Word = 1FBE76C9
0
0
–10
–10
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–100
–100
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
VBW 1kHz
VBW 1kHz
Figure 12. fMCLK = 25 MHz, fOUT = 1.1 MHz, Frequency
Word = B439581
Figure 15. fMCLK = 25 MHz, fOUT = 4.1 MHz, Frequency
Word = 29FBE76D
0
0
–10
–10
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–100
–100
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
VBW 1kHz
VBW 1kHz
Figure 13. fMCLK = 25 MHz, fOUT = 2.1 MHz, Frequency
Word = 15810625
Figure 16. fMCLK = 25 MHz, fOUT = 5.1 MHz, Frequency
Word = 34395810
REV. B
–8–
AD9831
0
0
–10
–10
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–100
–100
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
VBW 1kHz
VBW 1kHz
Figure 17. fMCLK = 25 MHz, fOUT = 6.1 MHz, Frequency
Word = 3E76C8B4
Figure 19. fMCLK = 25 MHz, fOUT = 8.1 MHz, Frequency
Word = 52F1A9FC
0
0
–10
–10
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–100
–100
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
START 0Hz
RBW 300Hz
STOP 12.5MHz
ST 277 SEC
VBW 1kHz
VBW 1kHz
Figure 18. fMCLK = 25 MHz, fOUT = 7.1 MHz, Frequency
Word = 48B43958
Figure 20. fMCLK = 25 MHz, fOUT = 9.1 MHz, Frequency
Word = 5D2F1AA0
REV. B
–9–
AD9831
CIRCUIT D ESCRIP TIO N
Num er ical Contr olled O scillator + P hase Modulator
T he AD9831 provides an exciting new level of integration for
the RF/Communications system designer. T he AD9831 com-
bines the Numerical Controlled Oscillator (NCO), SINE Look-
Up T able, Frequency and Phase Modulators, and a Digital-to-
Analog Converter on a single integrated circuit.
T his consists of two frequency select registers, a phase accumu-
lator and four phase offset registers. T he main component of the
NCO is a 32-bit phase accumulator which assembles the phase
component of the output signal. Continuous time signals have a
phase range of 0 to 2π. Outside this range of numbers, the
sinusoid functions repeat themselves in a periodic manner. T he
digital implementation is no different. T he accumulator simply
scales the range of phase numbers into a multibit digital word.
T he phase accumulator in the AD9831 is implemented with 32
bits. T herefore, in the AD9831, 2π = 232. Likewise, the ∆Phase
term is scaled into this range of numbers 0 < ∆Phase < 232 – 1.
Making these substitutions into the equation above
T he internal circuitry of the AD9831 consists of three main
sections. T hese are:
Numerical Controlled Oscillator (NCO) + Phase Modulator
SINE Look-Up T able
Digital-to-Analog Converter
T he AD9831 is a fully integrated Direct Digital Synthesis
(DDS) chip. T he chip requires one reference clock, one low
precision resistor and eight decoupling capacitors to provide
digitally created sine waves up to 12.5 MHz. In addition to the
generation of this RF signal, the chip is fully capable of a broad
range of simple and complex modulation schemes. T hese
modulation schemes are fully implemented in the digital domain
allowing accurate and simple realization of complex modulation
algorithms using DSP techniques.
f = ∆Phase × fMCLK/232
where 0 < ∆Phase < 232
With a clock signal of 25 MHz and a phase word of 051EB852
hex
f = 51EB852 × 25 MHz/232 = 0.500000000465 MHz
T he input to the phase accumulator (i.e., the phase step) can be
selected either from the FREQ0 Register or FREQ1 Register
and this is controlled by the FSELECT pin. NCOs inherently
generate continuous phase signals, thus avoiding any output
discontinuity when switching between frequencies.
TH EO RY O F O P ERATIO N
Sine waves are typically thought of in terms of their magnitude
form a(t) = sin (ωt). However, these are nonlinear and not easy
to generate except through piece wise construction. On the
other hand, the angular information is linear in nature. T hat is,
the phase angle rotates through a fixed angle for each unit of
time. T he angular rate depends on the frequency of the signal
by the traditional rate of ω = 2πf.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit PHASE Registers. T he con-
tents of this register are added to the most significant bits of the
NCO. T he AD9831 has four PHASE registers, the resolution
of these registers being 2π/4096.
Sine Look-Up Table (LUT)
MAGNITUDE
T o make the output useful, the signal must be converted from
phase information into a sinusoidal value. Since phase informa-
tion maps directly into amplitude, a ROM LUT converts the
phase information into amplitude. T o do this, the digital phase
information is used to address a sine ROM LUT . Although the
NCO contains a 32-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 232 entries.
+1
0
–1
PHASE
2π
It is necessary only to have sufficient phase resolution in the
LUT s such that the dc error of the output waveform is domi-
nated by the quantization error in the DAC. T his requires the
look-up table to have two more bits of phase resolution than the
10-bit DAC.
0
Figure 21. Sine Wave
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that
period can be determined.
D igital-to-Analog Conver ter
T he AD9831 includes a high impedance current source 10-bit
DAC, capable of driving a wide range of loads at different
speeds. Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of a
single external resistor (RSET).
∆Phase = ωδt
Solving for ω
ω = ∆Phase/δt = 2πf
T he DAC is configured for single ended operation. T he load
resistor can be any value required, as long as the full-scale volt-
age developed across it does not exceed the voltage compliance
range. Since full-scale current is controlled by RSET , adjust-
ments to RSET can balance changes made to the load resistor.
However, if the DAC full-scale output current is significantly
less than 4 mA, the DAC’s linearity may degrade.
Solving for f and substituting the reference clock frequency for
the reference period (1/fMCLK = δt)
f = ∆Phase × fMCLK/2π
T he AD9831 builds the output based on this simple equation.
A simple DDS chip can implement this equation with three
major subcircuits.
REV. B
–10–
AD9831
D SP and MP U Inter facing
T he AD9831 has a parallel interface, with 16 bits of data being
loaded during each write cycle.
MCLK cycle introduced otherwise. When these inputs change
value, there will be a pipeline delay before control is transferred
to the selected register—there will be a pipeline delay before the
analog output is controlled by the selected register. T here is a
similar delay when a new word is written to a register. PSEL0,
PSEL1, FSELECT and WR have latencies of six MCLK cycles.
T he frequency or phase registers are loaded by asserting the WR
signal. T he destination register for the 16 bit data is selected
using the address inputs A0, A1 and A2. T he phase registers
are 12 bits wide so, only the 12 LSBs need to be valid—the
4 MSBs of the 16 bit word do not have to contain valid data.
Data is loaded into the AD9831 by pulsing WR low, the data
being latched into the AD9831 on the rising edge of WR. T he
values of inputs A0, A1 and A2 are also latched into the
AD9831 on the WR rising edge. T he appropriate destination
register is updated on the next MCLK rising edge. If the WR
rising edge coincides with the MCLK rising edge, there is an
uncertainty of one MCLK cycle regarding the loading of the
destination register—the destination register may be loaded
immediately or the destination register may be updated on the
next MCLK rising edge. T o avoid any uncertainty, the times
listed in the specifications should be complied with.
T he flow chart in Figure 22 shows the operating routine for the
AD9831. When the AD9831 is powered up, the part should be
reset using RESET. T his will reset the phase accumulator to
zero so that the analog output is at midscale. RESET does not
reset the phase and frequency registers. T hese registers will
contain invalid data and, therefore, should be set to zero by the
user.
T he registers to be used should be loaded, the analog output
being fMCLK/232 × FREG where FREG is the value loaded into
the selected frequency register. T his signal will be phase shifted
by the amount specified in the selected phase register (2π/4096
× PHASEREG where PHASEREG is the value contained in the
selected phase register). When FSELECT , PSEL0 and PSEL1
are programmed, there will be a pipeline delay of approximately
6 MCLK cycles before the analog output reacts to the change
on these inputs.
FSELECT , PSEL0 and PSEL1 are sampled on the MCLK
rising edge. Again, these inputs should be valid when an
MCLK rising edge occurs as there will be an uncertainty of one
RESET
DATA WRITE
FREG<0, 1> = 0
PHASEREG<0, 1, 2, 3> = 0
DATA WRITE
32
FREG<0> = f
FREG<1> = f
/f
*2
*2
OUT0 MCLK
32
/f
OUT1 MCLK
PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>
SELECT DATA SOURCES
SET FSELECT
SET PSEL0, PSEL1
WAIT 6 MCLK CYCLES
DAC OUTPUT
32 12
*t/2 + PHASEREG/2 )))
MCLK
V
= V
REFIN
*6.25*R
/R
(1 + SIN(2π(FREG*f
OUT
OUT SET*
YES
CHANGE PHASE?
NO
NO
NO
CHANGE F
?
OUT
YES
NO
CHANGE FREG?
YES
CHANGE PHASEREG?
YES
CHANGE FSELECT
CHANGE PSEL0, PSEL1
Figure 22. Flow Chart for AD9831 Initialization and Operation
REV. B
–11–
AD9831
device requiring an AGND to DGND connection, then the
ground planes should be connected at the AGND and DGND
pins of the AD9831. If the AD9831 is in a system where mul-
tiple devices require AGND to DGND connections, the
connection should be made at one point only, a star ground
point that should be established as close as possible to the
AD9831.
AP P LICATIO NS
T he AD9831 contains functions which make it suitable for
modulation applications. T he part can be used to perform
simple modulation such as FSK. More complex modulation
schemes such as GMSK and QPSK can also be implemented
using the AD9831. In an FSK application, the two frequency
registers of the AD9831 are loaded with different values; one
frequency will represent the space frequency while the other will
represent the mark frequency. T he digital data stream is fed to
the FSELECT pin which will cause the AD9831 to modulate
the carrier frequency between the two values.
Avoid running digital lines under the device as these will couple
noise onto the die. T he analog ground plane should be allowed
to run under the AD9831 to avoid noise coupling. T he power
supply lines to the AD9831 should use as large a track as is
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiat-
ing noise to other sections of the board. Avoid crossover of
digital and analog signals. T races on opposite sides of the board
should run at right angles to each other. T his will reduce the
effects of feedthrough through the board. A microstrip tech-
nique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes while signals are placed
on the other side.
T he AD9831 has four phase registers; this enables the part to
perform PSK. With phase shift keying, the carrier frequency is
phase shifted, the phase being altered by an amount which is
related to the bit stream being input to the modulator. T he
presence of four shift registers eases the interaction needed
between the DSP and the AD9831.
T he frequency and phase registers can be written to continu-
ously, if required. T he maximum update rate equals the
frequency of the MCLK. However, if a selected register is
loaded with a new word, there will be a delay of 6 MCLK cycles
before the analog output will change accordingly.
Good decoupling is important. T he analog and digital supplies
to the AD9831 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND respectively with 0.1 µF ceramic capacitors
in parallel with 10 µF tantalum capacitors. T o achieve the best
from the decoupling capacitors, they should be placed as close
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the
AVDD and DVDD of the AD9831, it is recommended that the
system’s AVDD supply be used. T his supply should have the
recommended analog supply decoupling between the AVDD
pins of the AD9831 and AGND and the recommended digital
supply decoupling capacitors between the DVDD pins and
DGND.
T he AD9831 is also suitable for signal generator applications.
With its low current consumption, the part is suitable for appli-
cations in which it can be used as a local oscillator. In addition,
the part is fully specified for operation with a +3.3 V ± 10%
power supply. T herefore, in portable applications where current
consumption is an important issue, the AD9831 is perfect.
Gr ounding and Layout
T he printed circuit board that houses the AD9831 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. T his facilitates the
use of ground planes which can be separated easily. A mini-
mum etch technique is generally best for ground planes as it
gives the best shielding. Digital and analog ground planes
should only be joined in one place. If the AD9831 is the only
Evaluation boards are available for the AD9832, the AD9833, and
the
, which are similar in functionality to the AD9831. For
AD9837
more information on these parts, visit
.
http://www.analog.com/DDS
REV. B
–12–
Data Sheet
AD9831
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.60
MAX
37
48
36
1
PIN 1
7.20
TOP VIEW
(PINS DOWN)
7.00 SQ
6.80
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 23. 48-Lead Low Profile Quad Flat Package (LQFP)
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9831ASTZ
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
ST-48
ST-48
AD9831ASTZ-REEL
1 Z = RoHS Compliant Part.
REVISION HISTORY
11/11—Rev. A to Rev. B
Deleted Figure 23; Renumbered Sequentially.............................13
Updated Outline Dimensions........................................................13
Changes to Ordering Guide...........................................................13
Deleted Figure 24 and Component List Section.........................14
Changes to Title and General Description Section ......................1
Changed TQFP to LQFP Throughout............................................1
Changes to Grounding and Layout Section.................................12
Deleted AD9831 Evaluation Board, Using the AD9831
Evaluation Board, Prototyping Area, XO vs. External Clock, and
Power Supply Sections....................................................................13
Rev. B | Page 13 of 16
AD9831
NOTES
Data Sheet
Rev. B | Page 14 of 16
Data Sheet
NOTES
AD9831
Rev. B | Page 15 of 16
AD9831
NOTES
Data Sheet
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10373-0-11/11(B)
Rev. B | Page 16 of 16
相关型号：
©2020 ICPDF网 联系我们和版权申明