AD9835BRU [ADI]
50 MHz CMOS Complete DDS; 50 MHz的CMOS DDS完成
| 型号： | AD9835BRU |
| 厂家： | 
ADI |
| 描述： | 50 MHz CMOS Complete DDS |
| 文件： | 总16页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 MHz CMOS
Complete DDS
a
AD9835
FEATURES
GENERAL DESCRIPTION
5 V Power Supply
50 MHz Speed
On-Chip COS Look-Up Table
On-Chip 10-Bit DAC
Serial Loading
The AD9835 is a numerically controlled oscillator employing
a phase accumulator, a COS Look-Up Table and a 10-bit
D/A converter integrated on a single CMOS chip. Modulation
capabilities are provided for phase modulation and frequency
modulation.
Power-Down Option
200 mW Power Consumption
16-Lead TSSOP
Clock rates up to 50 MHz are supported. Frequency accuracy
can be controlled to one part in 4 billion. Modulation is ef-
fected by loading registers through the serial interface. A
power-down bit allows the user to power down the AD9835 when
it is not in use, the power consumption being reduced to 1.75 mW.
The part is available in a 16-lead TSSOP package.
APPLICATIONS
DDS Tuning
Digital Demodulation
FUNCTIONAL BLOCK DIAGRAM
DVDD
DGND
AVDD
REFOUT
AGND
FS ADJUST REFIN
FSELECT
SELSRC
MCLK
BIT
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
COMP
IOUT
FSELECT
SYNC
FREQ0 REG
12
PHASE
COS
ROM
10-BIT
DAC
MUX
ACCUMULATOR
(32 BIT)
Σ
FREQ1 REG
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
AD9835
MUX
SYNC
SYNC
16-BIT DATA REGISTER
SYNC
SELSRC
8 MSBs
8 LSBs
DEFER REGISTER
CONTROL REGISTER
PSEL0
BIT
PSEL1
BIT
DECODE LOGIC
SERIAL REGISTER
FSELECT/PSEL REGISTER
PSEL1
PSEL0
FSYNC
SCLK
SDATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1998
(VDD = +5 V ؎ 5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT;
RSET = 3.9 k⍀; RLOAD = 300 ⍀ for IOUT, unless otherwise noted)
AD9835–SPECIFICATIONS1
Parameter
AD9835B
Units
Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
50
4
4.75
1.35
Bits
Update Rate (fMAX
)
MSPS nom
mA nom
mA max
V max
IOUT Full Scale
Output Compliance
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
±1
±0.5
LSB typ
LSB typ
DDS SPECIFICATIONS2
Dynamic Specifications
Signal-to-Noise Ratio
50
–52
dB min
dBc max
fMCLK = 50 MHz, fOUT = 1 MHz
fMCLK = 50 MHz, fOUT = 1 MHz
fMCLK = 6.25 MHz, fOUT = 2.11 MHz
Total Harmonic Distortion
Spurious Free Dynamic Range (SFDR)3
Narrow Band (±50 kHz)
Wide Band (±2 MHz)
Clock Feedthrough
–72
–50
–60
1
dBc min
dBc min
dBc typ
ms typ
Wake-Up Time
Power-Down Option
Yes
VOLTAGE REFERENCE
Internal Reference @ +25°C
1.21
V typ
T
MIN to TMAX
1.21 ± 7%
10
100
V min/max
MΩ typ
ppm/°C typ
Ω typ
REFIN Input Impedance
Reference TC
REFOUT Output Impedance
300
LOGIC INPUTS
V
INH, Input High Voltage
DVDD – 0.9
V min
VINL, Input Low Voltage
IINH, Input Current
CIN, Input Capacitance
0.9
10
10
V max
µA max
pF max
POWER SUPPLIES
fMCLK = 50 MHz
AVDD
DVDD
IAA
4.75/5.25
4.75/5.25
5
V min/V max
V min/V max
mA max
IDD
IAA + IDD
2.5 + 0.33/MHz
40
mA typ
mA max
4
Low Power Sleep Mode
0.35
mA max
NOTES
1Operating temperature range is as follows: B Version: –40°C to +85°C.
2100% production tested.
3fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, fOUT = 2.11 MHz.
4Measured with the digital inputs static and equal to 0 V or DVDD. The AD9835 is tested with a capacitive load of 50 pF. The part can be operated with higher
capacitive loads, but the magnitude of the analog output will be attenuated. See Figure 5.
Specifications subject to change without notice.
R
SET
3.9k⍀
10nF
FS
ADJUST
AVDD
10nF
REFOUT
REFIN
COMP
ON-BOARD
REFERENCE
FULL-SCALE
CONTROL
IOUT
12
10-BIT
DAC
COS
ROM
300⍀
50pF
AD9835
Figure 1. Test Circuit with Which Specifications Are Tested
–2–
REV. 0
AD9835
(V = +5 V ؎ 5%; AGND = DGND = 0 V, unless otherwise noted)
DD
TIMING CHARACTERISTICS
Limit at
TMIN to TMAX
(B Version)
Parameter
Units
Test Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
20
8
8
50
20
20
15
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
MCLK Period
MCLK High Duration
MCLK Low Duration
SCLK Period
SCLK High Duration
SCLK Low Duration
FSYNC to SCLK Falling Edge Setup Time
FSYNC to SCLK Hold Time
SCLK – 5
15
5
8
8
t9
t10
t11
Data Setup Time
Data Hold Time
FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
1
t11A
NOTES
1See Pin Description section.
Guaranteed by design but not production tested.
t1
MCLK
t2
t3
Figure 2. Master Clock
t5
t4
SCLK
t8
t7
t6
FSYNC
t10
t9
D15
D14
D2
D1
D0
D15
D14
SDATA
Figure 3. Serial Timing
MCLK
t11A
t11
FSELECT
PSEL0, PSEL1
VALID DATA
VALID DATA
VALID DATA
Figure 4. Control Timing
REV. 0
–3–
AD9835
ABSOLUTE MAXIMUM RATINGS*
TERMINOLOGY
(TA = +25°C unless otherwise noted)
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale, a point 0.5 LSB
below the first code transition (000 . . . 00 to 000 . . . 01)
and full scale, a point 0.5 LSB above the last code transition
(111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Differential Nonlinearity
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . .+150°C
TSSOP θJA Thermal Impedance . . . . . . . . . . . . . . . 158°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V
This is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. The signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (fMCLK/2) but exclud-
ing the dc component. Signal to (Noise + Distortion) is depen-
dent on the number of quantization levels used in the digitization
process; the more levels, the smaller the quantization noise.
The theoretical Signal to (Noise + Distortion) ratio for a sine
wave input is given by
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
where N is the number of bits. Thus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option*
Total Harmonic Distortion
Model
Total Harmonic Distortion (THD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9835, THD is defined as
AD9835BRU –40°C to +85°C
16-Lead TSSOP RU-16
*RU = Thin Shrink Small Outline Package (TSSOP).
2
(V22 +V32 +V42 +V52 +V6
)
THD = 20 log
PIN CONFIGURATION
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonic.
1
2
FS ADJUST
REFIN
16 COMP
15 AVDD
IOUT
14
3
4
REFOUT
DVDD
Output Compliance
AD9835
13 AGND
12 PSEL0
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifica-
tions. When voltages greater than that specified for the output
compliance are generated, the AD9835 may not meet the speci-
fications listed in the data sheet.
TOP VIEW
(Not to Scale)
5
6
DGND
MCLK
PSEL1
11
SCLK
7
8
10
9
FSELECT
FSYNC
SDATA
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of the MCLK frequency are
present at the output of a DDS device. The spurious free dy-
namic range (SFDR) refers to the largest spur or harmonic
present in the band of interest. The wideband SFDR gives the
magnitude of the largest harmonic or spur relative to the magni-
tude of the fundamental frequency in the bandwidth ±2 MHz
about the fundamental frequency. The narrow band SFDR gives
the attenuation of the largest spur or harmonic in a bandwidth of
±50 kHz about the fundamental frequency.
Clock Feedthrough
There will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9835’s output spectrum.
–4–
REV. 0
AD9835
PIN FUNCTION DESCRIPTIONS
Pin # Mnemonic
Function
ANALOG SIGNAL AND REFERENCE
1
FS ADJUST
Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines
the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is
as follows:
IOUTFULL-SCALE = 12.5 × VREFIN/RSET
V
REFIN = 1.21 V nominal, RSET = 3.9 kΩ typical
2
3
REFIN
Voltage Reference Input. The AD9835 can be used with either the onboard reference, which is available
from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin.
The AD9835 accepts a reference of 1.21 V nominal.
Voltage Reference Output. The AD9835 has an onboard reference of value 1.21 V nominal. The refer-
ence is made available on the REFOUT pin. This reference is used as the reference to the DAC by con-
necting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
REFOUT
14
16
IOUT
Current Output. This is a high impedance current source. A load resistor should be connected between
IOUT and AGND.
Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling
ceramic capacitor should be connected between COMP and AVDD.
COMP
POWER SUPPLY
4
DVDD
Positive Power Supply for the Digital Section. A 0.1 µF decoupling capacitor should be connected be-
tween DVDD and DGND. DVDD can have a value of +5 V ± 5%.
5
13
15
DGND
AGND
AVDD
Digital Ground.
Analog Ground.
Positive Power Supply for the Analog Section. A 0.1 µF decoupling capacitor should be connected be-
tween AVDD and AGND. AVDD can have a value of +5 V ± 5%.
DIGITAL INTERFACE AND CONTROL
6
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.
The output frequency accuracy and phase noise are determined by this clock.
7
8
9
SCLK
Serial Clock, Logic Input. Data is clocked into the AD9835 on each falling SCLK edge.
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
Data Synchronization Signal, Logic Input. When this input is taken low, the internal logic is informed
that a new word is being loaded into the device.
SDATA
FSYNC
10
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the
phase accumulator. The frequency register to be used can be selected using the pin FSELECT or the bit
FSELECT. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state
when an MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an
uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid
any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. When the bit is
being used to select the frequency register, the pin FSELECT should be tied to DGND.
11, 12 PSEL0, PSEL1 Phase Select Input. The AD9835 has four phase registers. These registers can be used to alter the value
being input to the COS ROM. The contents of the phase register are added to the phase accumula-
tor output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Alternatively, the
phase register to be used can be selected using bits PSEL0 and PSEL1. Like the FSELECT input,
PSEL0 and PSEL1 are sampled on the rising MCLK edge. Therefore, these inputs need to be in
steady state when an MCLK rising edge occurs or there is an uncertainty of one MCLK cycle as to
when control is transferred to the selected phase register. When the phase registers are being con-
trolled by the bits PSEL0 and PSEL1, the pins should be tied to DGND.
REV. 0
–5–
AD9835
Table I. Control Registers
Size Description
Table V. Commands
C3 C2 C1 C0 Command
Register
FREQ0 REG
32 Bits Frequency Register 0. This de-
fines the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
32 Bits Frequency Register 1. This de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
0
0
0
0
Write 16 Phase bits (Present 8 Bits + 8 Bits
in Defer Register) to Selected PHASE
REG.
0
0
0
0
0
1
1
0
Write 8 Phase bits to Defer Register.
FREQ1 REG
Write 16 Frequency bits (Present 8 Bits
+ 8 Bits in Defer Register) to Selected
FREQ REG.
0
0
0
1
1
0
1
0
Write 8 Frequency bits to Defer Register.
PHASE0 REG 12 Bits Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
Bits D9 (PSEL0) and D10 (PSEL1) are
used to Select the PHASE REG when
SELSRC = 1. When SELSRC = 0, the
PHASE REG is selected using the pins
PSEL0 and PSEL1 Respectively.
Bit D11 is used to select the FREQ REG
when SELSRC = 1. When SELSRC = 0,
the FREQ REG is selected using the pin
FSELECT.
This command is used to control the
PSEL0, PSEL1 and FSELECT bits
using only one write. Bits D9 and D10
are used to select the PHASE REG and
Bit 11 is used to select the FREQ REG
when SELSRC = 1. When SELSRC = 0,
the PHASE REG is selected using the
pins PSEL0 and PSEL1 and the FREQ
REG is selected using the pin FSELECT.
of this register are added to the
output of the phase accumulator.
PHASE1 REG 12 Bits Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the con-
0
0
1
1
0
1
1
0
tents of this register are added to the
output of the phase accumulator.
PHASE2 REG 12 Bits Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added to
the output of the phase accumulator.
PHASE3 REG 12 Bits Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the
output of the phase accumulator.
Table II. Addressing the Registers
0
1
1
1
Reserved. Configures the AD9835 for
Test Purposes.
A3
A2
A1
A0
Destination Register
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FREG0 REG 8 L LSBs
FREG0 REG 8 H LSBs
FREG0 REG 8 L MSBs
FREG0 REG 8 H MSBs
FREG1 REG 8 L LSBs
FREG1 REG 8 H LSBs
FREG1 REG 8 L MSBs
FREG1 REG 8 H MSBs
PHASE0 REG 8 LSBs
PHASE0 REG 8 MSBs
PHASE1 REG 8 LSBs
PHASE1 REG 8 MSBs
PHASE2 REG 8 LSBs
PHASE2 REG 8 MSBs
PHASE3 REG 8 LSBs
PHASE3 REG 8 MSBs
Table VI. Controlling the AD9835
D15 D14 Command
1 0
Selects source of Control for the PHASE and
FREQ Registers and Enables Synchronization. Bit
D13 is the SYNC Bit. When this bit is High, read-
ing of the FSELECT, PSEL0 and PSEL1 bits/pins
and the loading of the Destination Register with
data is synchronized with the rising edge of MCLK.
The latency is increased by 2 MCLK cycles when
SYNC = 1. When SYNC = 0, the loading of the
data and the sampling of FSELECT/PSEL0/PSEL1
occurs asynchronously. Bit D12 is the Select
Source Bit (SELSRC). When this bit Equals 1, the
PHASE/FREQ REG is Selected using the bits
FSELECT, PSEL0 and PSEL1. When SELSRC =
0, the PHASE/FREQ REG is Selected using the
pins FSELECT, PSEL0 and PSEL1.
Table III. 32-Bit Frequency Word
1
1
Sleep, Reset and Clear. D13 is the SLEEP bit. When
this bit equals 1, the AD9835 is powered down, inter-
nal clocks are disabled and the DAC's current sources
and REFOUT are turned off. When SLEEP = 0, the
AD9835 is powered up. When RESET (D12) = 1,
the phase accumulator is set to zero phase which
corresponds to an analog output of full scale. When
CLR (D11) = 1, SYNC and SELSRC are set to
zero. CLR automatically resets to zero.
16 MSBs
8 H MSBs 8 L MSBs
16 LSBs
8 H LSBs 8 L LSBs
Table IV. 12-Bit Frequency Word
4 MSBs (The 4 MSBs of the
8-Bit Word Loaded = 0)
8 LSBs
–6–
REV. 0
AD9835
Table VII. Writing to the AD9835 Data Registers
D15
C3
D14
C2
D13
C1
D12
C0
D11
A3
D10
A2
D9
A1
D8
A0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Table VIII. Setting SYNC and SELSRC
D15
1
D14
0
D13
D12
D11
X
D10
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
D3
D2
X
D1
X
D0
X
SYNC SELSRC
X
X
Table IX. Power-Down, Resetting and Clearing the AD9835
D15
1
D14
1
D13
D12
D11
D10
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
SLEEP RESET CLR
Typical Performance Characteristics
–64
0
AVDD = DVDD = +5V
f
/f
= 1/3
OUT MCLK
–66
–68
–70
–72
–74
–76
–2
–4
AVDD = DVDD = +5V
C
= 82pF
L
–6
–8
–10
–12
C
= 150pF
10
L
C
= 100pF
14
L
0
2
4
6
8
12
16
10
20
30
40
50
MCLK FREQUENCY – MHz
OUTPUT FREQUENCY – MHz
Figure 7. Narrow Band SFDR vs. MCLK Frequency
Figure 5. Signal Attenuation vs. Output Frequency for
Various Capacitive Load (RL = 300 Ω)
30
0
T
= +25؇C
f
/f
= 1/3
A
OUT MCLK
25
20
15
10
–10
–20
–30
–40
–50
–60
AVDD = DVDD = +5V
AVDD = DVDD = +5V
5
0
10
20
30
MCLK FREQUENCY – MHz
40
50
10
20
30
MCLK FREQUENCY – MHz
40
50
Figure 8. Wide Band SFDR vs. MCLK Frequency
Figure 6. Typical Current Consumption vs. MCLK Frequency
REV. 0
–7–
AD9835
–20
AVDD = DVDD = +5V
–30
–40
–50
–60
–70
–80
50MHz
30MHz
10MHz
0Hz
START
25MHz
STOP
ST 50 SEC
0.044 0.084 0.124 0.164 0.204 0.244 0.284 0.324 0.364
f
/f
OUT MCLK
RBW 1kHz
VBW 3kHz
Figure 9. Wide Band SFDR vs. fOUT/fMCLK for Various MCLK
Frequencies
Figure 12. fMCLK = 50 MHz, fOUT = 2.1 MHz. Frequency
Word = ACO8312
56
f
/f
= 1/3
OUT MCLK
55
54
53
52
51
50
AVDD = DVDD = +5V
10
20
30
MCLK FREQUENCY – MHz
40
50
0Hz
START
RBW 1kHz
25MHz
STOP
ST 50 SEC
VBW 3kHz
Figure 10. SNR vs. MCLK Frequency
Figure 13. fMCLK = 50 MHz, fOUT = 3.1 MHz. Frequency
Word = FDF3B64
70
10MHz
60
50
40
30
20
10
30MHz
50MHz
AVDD = DVDD = +5V
0.044 0.084 0.124 0.164 0.204 0.244
0.284 0.324 0.364
0Hz
START
25MHz
STOP
ST 50 SEC
f
/f
OUT MCLK
RBW 1kHz
VBW 3kHz
Figure 14. fMCLK = 50 MHz, fOUT = 7.1 MHz. Frequency
Word = 245AICAC
Figure 11. SNR vs. fOUT/fMCLK for Various MCLK
Frequencies
–8–
REV. 0
AD9835
0Hz
START
0Hz
START
25MHz
STOP
ST 50 SEC
25MHz
STOP
ST 50 SEC
RBW 1kHz
VBW 3kHz
RBW 1kHz
VBW 3kHz
Figure 15. fMCLK = 50 MHz, fOUT = 9.1 MHz. Frequency
Word = 2E978D50
Figure 17. fMCLK = 50 MHz, fOUT = 13.1 MHz. Frequency
Word = 43126E98
0Hz
START
RBW 1kHz
25MHz
STOP
ST 50 SEC
0Hz
START
25MHz
STOP
ST 50 SEC
VBW 3kHz
RBW 1kHz
VBW 3kHz
Figure 16. fMCLK = 50 MHz, fOUT = 11.1 MHz. Frequency
Word = 38D4FDF4
Figure 18. fMCLK = 50 MHz, fOUT = 16.5 MHz. Frequency
Word = 547AE148
REV. 0
–9–
AD9835
CIRCUIT DESCRIPTION
component of the output signal. Continuous time signals have a
phase range of 0 π to 2 π. Outside this range of numbers, the
sinusoid functions repeat themselves in a periodic manner. The
digital implementation is no different. The accumulator simply
scales the range of phase numbers into a multibit digital word.
The phase accumulator in the AD9835 is implemented with
32 bits. Therefore, in the AD9835, 2 π = 232. Likewise, the
∆Phase term is scaled into this range of numbers 0 < ∆Phase
< 232 – 1. Making these substitutions into the equation above
The AD9835 provides an exciting new level of integration for
the RF/Communications system designer. The AD9835 com-
bines the Numerical Controlled Oscillator (NCO), COS Look-Up
Table, Frequency and Phase Modulators, and a Digital-to-
Analog Converter on a single integrated circuit.
The internal circuitry of the AD9835 consists of three main
sections. These are:
Numerical Controlled Oscillator (NCO) + Phase Modulator
COS Look-Up Table
Digital-to-Analog Converter
f = ∆Phase × fMCLK/232
where 0 < ∆Phase < 232
The AD9835 is a fully integrated Direct Digital Synthesis (DDS)
chip. The chip requires one reference clock, one low precision
resistor and eight decoupling capacitors to provide digitally
created sine waves up to 25 MHz. In addition to the generation
of this RF signal, the chip is fully capable of a broad range of
simple and complex modulation schemes. These modulation
schemes are fully implemented in the digital domain allowing
accurate and simple realization of complex modulation algo-
rithms using DSP techniques.
The input to the phase accumulator (i.e., the phase step) can be
selected either from the FREQ0 Register or FREQ1 Register
and this is controlled by the FSELECT pin or the FSELECT
bit. NCOs inherently generate continuous phase signals, thus
avoiding any output discontinuity when switching between
frequencies.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit PHASE Registers. The con-
tents of this register are added to the most significant bits of the
NCO. The AD9835 has four PHASE registers, the resolution
of these registers being 2 π/4096.
THEORY OF OPERATION
Cos waves are typically thought of in terms of their magnitude
form a(t) = cos (ωt). However, these are nonlinear and not easy
to generate except through piece-wise construction. On the
other hand, the angular information is linear in nature. That is,
the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of ω = 2 πf.
COS Look-Up Table (LUT)
To make the output useful, the signal must be converted from
phase information into a sinusoidal value. Since phase informa-
tion maps directly into amplitude, a ROM LUT converts the
phase information into amplitude. To do this, the digital phase
information is used to address a COS ROM LUT. Although
the NCO contains a 32-bit phase accumulator, the output of the
NCO is truncated to 12 bits. Using the full resolution of the
phase accumulator is impractical and unnecessary as this would
require a look-up table of 232 entries.
MAGNITUDE
+1
0
It is necessary only to have sufficient phase resolution in the
LUTs such that the dc error of the output waveform is domi-
nated by the quantization error in the DAC. This requires the
look-up table to have two more bits of phase resolution than the
10-bit DAC.
–1
PHASE
2π
Digital-to-Analog Converter
The AD9835 includes a high impedance current source 10-bit
DAC, capable of driving a wide range of loads at different
speeds. Full-scale output current can be adjusted, for optimum
power and external load requirements, through the use of a
single external resistor (RSET).
0
Figure 19. Cos Wave
Knowing that the phase of a cos wave is linear and given a refer-
ence interval (clock period), the phase rotation for that period
can be determined.
The DAC is configured for single-ended operation. The load
resistor can be any value required, as long as the full-scale volt-
age developed across it does not exceed the voltage compliance
range. Since full-scale current is controlled by RSET, adjust-
ments to RSET can balance changes made to the load resistor.
However, if the DAC full-scale output current is significantly
less than 4 mA, the DAC’s linearity may degrade.
∆Phase = ωδt
Solving for ω
ω = ∆Phase/δt = 2 πf
Solving for f and substituting the reference clock frequency for
the reference period (1/fMCLK = δt)
DSP and MPU Interfacing
f = ∆Phase × fMCLK/2 π
The AD9835 has a serial interface, with 16 bits being loaded
during each write cycle. SCLK, SDATA and FSYNC are used
to load the word into the AD9835. When FSYNC is taken low,
the AD9835 is informed that a word is being written to the
device. The first bit is read into the device on the next SCLK
falling edge with the remaining bits being read into the device
on the subsequent SCLK falling edges. FSYNC frames the
16 bits; therefore, when 16 SCLK falling edges have occurred,
The AD9835 builds the output based on this simple equation.
A simple DDS chip can implement this equation with three
major subcircuits.
Numerical Controlled Oscillator and Phase Modulator
This consists of two frequency select registers, a phase accumu-
lator and four phase offset registers. The main component of the
NCO is a 32-bit phase accumulator which assembles the phase
–10–
REV. 0
AD9835
FSYNC should be taken high again. The SCLK can be con-
tinuous or, alternatively, the SCLK can idle high or low be-
tween write operations.
register (defer register) to the 16-bit data register and the
FSELECT/PSEL registers occur following a two-stage pipeline
delay which is triggered on the MCLK falling edge. The pipe-
line delay ensures that the data is valid when the transfer occurs.
Similarly, selection of the frequency/phase registers using the
FSELECT/PSEL pins is synchronized with the MCLK rising
edge when SYNC = 1. When SYNC = 0, the synchronizer is
bypassed.
When writing to a frequency/phase register, the first four bits
identify whether a frequency or phase register is being written
to, the next four bits contain the address of the destination
register while the 8 LSBs contain the data. Table II lists the
addresses for the phase/frequency registers while Table III lists
the commands.
Selecting the frequency/phase registers using the pins is
synchronized with MCLK internally also when SYNC = 1 to
ensure that these inputs are valid at the MCLK rising edge. If
times t11 and t11A are met, the inputs will be at steady state at
the MCLK rising edge. However, if times t11 and t11A are
violated, the internal synchronizing circuitry will delay the
instant at which the pins are sampled, ensuring that the inputs
are valid at the sampling instant.
Within the AD9835, 16-bit transfers are used when loading the
destination frequency/phase register. There are two modes for
loading a register—direct data transfer and a deferred data
transfer. With a deferred data transfer, the 8-bit word is loaded
into the defer register (8 LSBs or 8 MSBs). However, this data
is not loaded into the 16-bit data register so the destination
register is not updated. With a direct data transfer, the 8-bit
word is loaded into the appropriate defer register (8 LSBs or
8 MSBs). Immediately following the loading of the defer regis-
ter, the contents of the complete defer register are loaded into
the 16-bit data register and the destination register is loaded on
the next MCLK rising edge. When a destination register is
addressed, a deferred transfer is needed first, followed by a
direct transfer. When all 16 bits of the defer register contain
relevant data, the destination register can then be updated using
8-bit loading rather than 16-bit loading, i.e., direct data trans-
fers can be used. For example, after a new 16-bit word has
been loaded to a destination register, the defer register will also
contain this word. If the next write instruction is to the same
destination register, the user can use direct data transfers
immediately.
A latency is associated with each operation. When inputs
FSELECT/PSEL change value, there will be a pipeline delay
before control is transferred to the selected register—there will
be a pipeline delay before the analog output is controlled by
the selected register. When times t11 and t11A are met, PSEL0,
PSEL1 and FSELECT have latencies of six MCLK cycles when
SYNC = 0. When SYNC = 1, the latency is increased to
8 MCLK cycles. When times t11 and t11A are not met, the
latency can increase by one MCLK cycle. Similarly, there is a
latency associated with each write operation. If a selected
frequency/phase register is loaded with a new word, there is a
delay of 6 to 7 MCLK cycles before the analog output will
change (there is an uncertainty of one MCLK cycle regarding
the MCLK rising edge at which the data is loaded into the
destination register). When SYNC = 1, the latency will be 8 or
9 MCLK cycles.
When writing to a phase register, the 4 MSBs of the 16-bit word
loaded into the data register should be zero (the phase registers
are 12 bits wide).
The flowchart in Figure 20 shows the operating routine for the
AD9835. When the AD9835 is powered up, the part should be
reset. This will reset the phase accumulator to zero so that the
analog output is at full scale. To avoid spurious DAC outputs
while the AD9835 is being initialized, the RESET bit should be
set to 1 until the part is ready to begin generating an output.
Taking CLR high will set SYNC and SELSRC to 0 so that the
FSELECT/PSEL pins are used to select the frequency/phase
registers and the synchronization circuitry is bypassed. A write
operation is needed to the SYNC/SELSRC register to enable
the synchronization circuitry or to change control to the
FSELECT/PSEL bits. RESET does not reset the phase and
frequency registers. These registers will contain invalid data
and should therefore be set to a known value by the user. The
RESET bit is then set to 0 to begin generating an output. A
signal will appear at the DAC output 6 MCLK cycles after
RESET is set to 0.
To alter the entire contents of a frequency register, four write
operations are needed. However, the 16 MSBs of a frequency
word are contained in a separate register to the 16 LSBs. There-
fore, the 16 MSBs of the frequency word can be altered inde-
pendent of the 16 LSBs.
The phase and frequency registers to be used are selected using
the pins FSELECT, PSEL0 and PSEL1 or the corresponding
bits can be used. Bit SELSRC determines whether the bits or
the pins are used. When SELSRC = 0, the pins are used while
the bits are used when SELSRC = 1. When CLR is taken high,
SELSRC is set to 0 so that the pins are the default source.
Data transfers from the serial (defer) register to the 16-bit data
register, and the FSELECT and PSEL registers, occur following
the 16th falling SCLK edge. Transfer of the data from the 16-bit
data register to the destination register or from the FSELECT/
PSEL register to the respective multiplexer occurs on the next
MCLK rising edge. Since the SCLK and the MCLK are asyn-
chronous, an MCLK rising edge may occur while the data bits
are in transitional state, which will cause a brief spurious DAC
output if the register being written to is generating the DAC
output. To avoid such spurious outputs, the AD9835 contains
synchronizing circuitry. When the SYNC bit is set to 1, the
synchronizer is enabled and data transfers from the serial
The analog output is fMCLK/232 × FREG where FREG is the
value loaded into the selected frequency register. This signal
will be phase shifted by the amount specified in the selected
phase register (2 π/4096 × PHASEREG where PHASEREG is
the value contained in the selected phase register).
Control of the frequency/phase registers can be interchanged
from the pins to the bits.
REV. 0
–11–
AD9835
DATA WRITE**
32
32
FREG<0> = f
/f
*2
*2
OUT0 MCLK
FREG<1> = f
/f
OUT1 MCLK
PHASEREG <3:0> = DELTA PHASE<0, 1, 2, 3>
SELECT DATA SOURCES***
SET FSELECT
INITIALIZATION*
SET PSEL0, PSEL1
WAIT 6 MCLK CYCLES (8 MCLK CYCLES IF SYNC = 1)
DAC OUTPUT
32 12
*t/2 + PHASEREG/2 )))
MCLK
V
= V
*6.25*R
/R
*(1 + COS(2(FREG*f
OUT
REFIN
OUT SET
YES
CHANGE PHASE?
NO
NO
NO
CHANGE f
?
OUT
YES
NO
CHANGE FSELECT
CHANGE FREG?
YES
CHANGE PHASEREG?
YES
CHANGE PSEL0, PSEL1
Figure 20. Flowchart for AD9835 Initialization and Operation
INITIALIZATION*
DATA WRITE**
CONTROL REGISTER WRITE
SET SLEEP
DEFERRED TRANSFER WRITE
WRITE 8 BITS TO DEFER REGISTER
RESET = 1
CLR = 1
DIRECT TRANSFER WRITE
WRITE PRESENT 8 BITS AND 8 BITS IN
DEFER REGISTER TO DATA REGISTER
YES
SET SYNC AND/OR SELSRC TO 1
NO
CHANGE 16 BITS
NO
CONTROL REGISTER WRITE
YES
SYNC = 1
AND/OR
SELSRC = 1
YES
WRITE ANOTHER WORD TO THIS
REGISTER?
CHANGE 8 BITS ONLY
NO
WRITE A WORD TO ANOTHER REGISTER
WRITE INITIAL DATA
32
32
FREG<0> = f
/f
*2
*2
OUT0 MCLK
FREG<1> = f
/f
OUT1 MCLK
PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>
Figure 22. Data Writes
SET PINS OR FREQUENCY/PHASE REGISTER WRITE
SET FSELECT, PSEL0 AND PSEL1
SELECT DATA SOURCES***
CONTROL REGISTER WRITE
SLEEP = 0
RESET = 0
CLR = 0
NO
FSELECT/PSEL PINS BEING USED?
YES
SELSRC = 0
Figure 21. Initialization
SELSRC = 1
SET PINS
SET FSELECT
SET PSEL0
SET PSEL1
FREQUENCY/PHASE REGISTER WRITE
SET FSELECT
SET PSEL0
SET PSEL1
Figure 23. Selecting Data Sources
–12–
REV. 0
AD9835
APPLICATIONS
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the
AVDD and DVDD of the AD9835, it is recommended that the
system’s AVDD supply be used. This supply should have the
recommended analog supply decoupling between the AVDD
pins of the AD9835 and AGND and the recommended digital
supply decoupling capacitors between the DVDD pins and
DGND.
The AD9835 contains functions that make it suitable for
modulation applications. The part can be used to perform
simple modulation such as FSK. More complex modulation
schemes such as GMSK and QPSK can also be implemented
using the AD9835. In an FSK application, the two frequency
registers of the AD9835 are loaded with different values; one
frequency will represent the space frequency while the other will
represent the mark frequency. The digital data stream is fed to
the FSELECT pin, which will cause the AD9835 to modulate
the carrier frequency between the two values.
Interfacing the AD9835 to Microprocessors
The AD9835 has a standard serial interface that allows the part
to interface directly with several microprocessors. The device
uses an external serial clock to write the data/control informa-
tion into the device. The serial clock can have a frequency of
20 MHz maximum. The serial clock can be continuous or it
can idle high or low between write operations. When data/
control information is being written to the AD9835, FSYNC
is taken low and held low while the 16 bits of data are being
written into the AD9835. The FSYNC signal frames the 16 bits
of information being loaded into the AD9835.
The AD9835 has four phase registers; this enables the part to
perform PSK. With phase shift keying, the carrier frequency is
phase shifted, the phase being altered by an amount that is
related to the bit stream being input to the modulator. The
presence of four shift registers eases the interaction needed
between the DSP and the AD9835.
The AD9835 is also suitable for signal generator applications.
With its low current consumption, the part is suitable for
applications in which it can be used as a local oscillator.
AD9835-to-ADSP-21xx Interface
Figure 24 shows the serial interface between the AD9835 and
the ADSP-21xx. The ADSP-21xx should be set up to operate
in the SPORT Transmit Alternate Framing Mode (TFSW = 1).
The ADSP-21xx is programmed through the SPORT control
register and should be configured as follows: Internal clock
operation (ISCLK = 1), Active low framing (INVTFS = 1),
16-bit word length (SLEN = 15), Internal frame sync signal
(ITFS = 1), Generate a frame sync for each write operation
(TFSR = 1). Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled. The data is
clocked out on each rising edge of the serial clock and clocked
into the AD9835 on the SCLK falling edge.
Grounding and Layout
The printed circuit board that houses the AD9835 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes which can be separated easily. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should only be
joined in one place. If the AD9835 is the only device requiring
an AGND to DGND connection, then the ground planes
should be connected at the AGND and DGND pins of the
AD9835. If the AD9835 is in a system where multiple devices
require AGND to DGND connections, the connection should
be made at one point only, a star ground point that should be
established as close as possible to the AD9835.
ADSP-2101/
AD9835
ADSP-2103
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD9835 to avoid noise coupling. The power
supply lines to the AD9835 should use as large a track as is
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals
such as clocks should be shielded with digital ground to avoid
radiating noise to other sections of the board. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This will reduce
the effects of feedthrough through the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes while signals are placed
on the other side.
TFS
DT
FSYNC
SDATA
SCLK
SCLK
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. ADSP-2101/ADSP-2103-to-AD9835 Interface
AD9835-to-68HC11/68L11 Interface
Figure 25 shows the serial interface between the AD9835 and
the 68HC11/68L11 microcontroller. The microcontroller is
configured as the master by setting bit MSTR in the SPCR to 1
and, this provides a serial clock on SCK while the MOSI output
drives the serial data line SDATA. Since the microcontroller
does not have a dedicated frame sync pin, the FSYNC signal is
derived from a port line (PC7). The setup conditions for cor-
rect operation of the interface are as follows: the SCK idles high
between write operations (CPOL = 0), data is valid on the SCK
falling edge (CPHA = 1). When data is being transmitted to the
AD9835, the FSYNC line is taken low (PC7). Serial data from
the 68HC11/68L11 is transmitted in 8-bit bytes with only eight
Good decoupling is important. The analog and digital supplies
to the AD9835 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to
AGND and DGND respectively with 0.1 µF ceramic capacitors
in parallel with 10 µF tantalum capacitors. To achieve the best
from the decoupling capacitors, they should be placed as close
REV. 0
–13–
AD9835
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data into the AD9835,
PC7 is held low after the first eight bits are transferred and a
second serial write operation is performed to the AD9835. Only
after the second eight bits have been transferred should FSYNC
be taken high again.
The frame sync signal is available on pin SC2 but, it needs to be
inverted before being applied to the AD9835. The interface to
the DSP56000/DSP56001 is similar to that of the DSP56002.
DSP56002
AD9835
SC2
STD
FSYNC
SDATA
68HC11/68L11
AD9835
SCK
SCLK
FSYNC
SDATA
PC7
MOSI
SCK
SCLK
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 27. AD9835-to-DSP56002 Interface
AD9835 Evaluation Board
ADDITIONAL PINS OMITTED FOR CLARITY
The AD9835 Evaluation Board allows designers to evaluate the
high performance AD9835 DDS Modulator with a minimum of
effort.
Figure 25. 68HC11/68L11-to-AD9835 Interface
AD9835-to-80C51/80L51 Interface
Figure 26 shows the serial interface between the AD9835 and
the 80C51/80L51 microcontroller. The microcontroller is oper-
ated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK
of the AD9835 while RXD drives the serial data line SDATA.
The FSYNC signal is again derived from a bit programmable
pin on the port (P3.3 being used in the diagram). When data is
to be transmitted to the AD9835, P3.3 is taken low. The
80C51/80L51 transmits data in 8-bit bytes thus, only eight
falling SCLK edges occur in each cycle. To load the remaining
eight bits to the AD9835, P3.3 is held low after the first eight
bits have been transmitted and a second write operation is initi-
ated to transmit the second byte of data. P3.3 is taken high
following the completion of the second write operation. SCLK
should idle high between the two write operations. The 80C51/
80L51 outputs the serial data in a format which has the LSB
first. The AD9835 accepts the MSB first (the 4 MSBs being the
control information, the next 4 bits being the address while the
8 LSBs contain the data when writing to a destination register).
Therefore, the transmit routine of the 80C51/80L51 must take
this into account and rearrange the bits so that the MSB is out-
put first.
To prove that this device will meet the user’s waveform synthe-
sis requirements, the user only requires a 5 V power supply, an
IBM-compatible PC and a spectrum analyzer along with the
evaluation board. The evaluation setup is shown below.
The DDS Evaluation kit includes a populated, tested AD9835
printed circuit board along with the software that controls the
AD9835 in a Windows® environment.
IBM-COMPATIBLE PC
PARALLEL PORT
CENTRONICS
PRINTER CABLE
AD9835.EXE
AD9835 EVALUATION
BOARD
Figure 28. AD9835 Evaluation Board Setup
Using the AD9835 Evaluation Board
The AD9835 Evaluation kit is a test system designed to simplify
the evaluation of the AD9835. Provisions to control the AD9835
from the printer port of an IBM-compatible PC are included
along with the necessary software. An application note is also
available with the evaluation board which gives information on
operating the evaluation board.
80C51/80L51
AD9835
FSYNC
SDATA
P3.3
RXD
Prototyping Area
An area is available on the evaluation board where the user can
add additional circuits to the evaluation test set. Users may
want to build custom analog filters for the output or add buffers
and operational amplifiers to be used in the final application.
TXD
SCLK
ADDITIONAL PINS OMITTED FOR CLARITY
XO vs. External Clock
Figure 26. 80C51/80L51 to AD9835 Interface
The AD9835 can operate with master clocks up to 50 MHz. A
50 MHz oscillator is included on the evaluation board. How-
ever, this oscillator can be removed and an external CMOS
clock connected to the part, if required.
AD9835-to-DSP56002 Interface
Figure 27 shows the interface between the AD9835 and the
DSP56002. The DSP56002 is configured for normal mode
asynchronous operation with a Gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated inter-
nally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0
= 0) and the frame sync signal will frame the 16 bits (FSL = 0).
Power Supply
Power to the AD9835 Evaluation Board must be provided ex-
ternally through the pin connections. The power leads should be
twisted to reduce ground loops.
Windows is a registered trademark of Microsoft Corporation.
–14–
REV. 0
AD9835
1
DVDD
C1
0.1F
AVDD
C2
0.1F
2
3
4
SCLK
SDATA
AVDD
C3
4
15
DVDD
FSYNC
10nF
DVDD AVDD
5
6
7
16
2
C6
0.1F
J1
COMP
REFIN
REFIN
20
4
6
16
14
9
7
8
9
SCLK
SDATA
FSYNC
SCLK
8
LK4
9
3
1
SDATA
REFOUT
10
C4
10nF
J2
J3
11
DVDD
C7
AVDD
FSYNC
11
12
1 10 19
U2
C8
10F
C9
C10
10F
FSADJUST
0.1F
0.1F
13
14
15
R5
3.9k⍀
U1
AD9835
R2
R1
R3
16
17
PSEL1
10k⍀ 10k⍀ 10k⍀
IOUT
11
14
18
PSEL1
PSEL0
FSELECT
MCLK
IOUT
LK1
PSEL0
19
20
12
10
R6
300⍀
LK2
FSELECT
21
LK3
22
23
6
DGND
AGND
13
24
25
26
5
DVDD
SW
27
28
29
MCLK
30
31
DVDD
C5
R4
50⍀
32
33
0.1F
DVDD
34
U3
35
36
OUT
XTAL1
DGND
Figure 29. Evaluation Board Layout
Integrated Circuits
Links
XTAL1
U1
U2
OSC XTAL 50 MHz
AD9835 (16-Lead TSSOP)
74HCT244 Buffer
LK1–LK3
LK4
Three Pin Link
Two Pin Link
Switch
Capacitors
C1, C2
C3, C4
C5, C6, C7, C9
C8, C10
SW
End Stackable Switch (SDC Double
Throw)
0.1 µF Ceramic Chip Capacitor
10 nF Ceramic Capacitor
0.1 µF Ceramic Capacitor
10 µF Tantalum Capacitor
Sockets
MCLK, PSEL0,
PSEL1, FSELECT,
IOUT, REFIN
Subminiature BNC Connector
Resistors
R1–R3
R4
R5
R6
10 kΩ Resistor
50 Ω Resistor
3.9 kΩ Resistor
300 Ω Resistor
Connectors
J1
J2, J3
36-Pin Edge Connector
PCB Mounting Terminal Block
REV. 0
–15–
AD9835
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Thin Shrink Small Outline Package (TSSOP)
(RU-16)
0.201 (5.10)
0.193 (4.90)
16
9
8
1
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0256 0.0118 (0.30)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
(0.65)
0.0075 (0.19)
BSC
–16–
REV. 0
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