AD9841AJSTZ [ADI]
Complete 10-bit, 20 MHz CCD Signal Processor with PxGA™;
| 型号： | AD9841AJSTZ |
| 厂家： | 
ADI |
| 描述： | Complete 10-bit, 20 MHz CCD Signal Processor with PxGA™ CD |
| 文件： | 总23页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 20 MSPS
CCD Signal Processors
a
AD9841A/AD9842A
PRODUCT DESCRIPTION
FEATURES
The AD9841A and AD9842A are complete analog signal proces-
sors for CCD applications. Both products feature a 20 MHz
single-channel architecture designed to sample and condition
the outputs of interlaced and progressive scan area CCD arrays.
The AD9841A/AD9842A’s signal chain consists of an input
clamp, correlated double sampler (CDS), Pixel Gain Amplifier
(PxGA), digitally controlled variable gain amplifier (VGA),
black level clamp, and A/D converter. The AD9841A offers 10-bit
ADC resolution, while the AD9842A contains a true 12-bit
ADC. Additional input modes are provided for processing analog
video signals.
20 MSPS Correlated Double Sampler (CDS)
4 dB ꢀ 6 dB 6-Bit Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit (9841) or 12-Bit (9842) 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
The AD9841A and AD9842A operate from a single 3 V power
supply, typically dissipate 78 mW, and are packaged in a 48-
lead LQFP.
FUNCTIONAL BLOCK DIAGRAM
HD
VD
AVDD
AVSS
PBLK
CLPOB
CLP
COLOR
STEERING
DRVDD
DRVSS
4dB ꢀ 6dB
2dB–36dB
VGA
PxGA
CDS
CCDIN
10/12
2:1
MUX
ADC
DOUT
CLP
6
VRT
VRB
BANDGAP
REFERENCE
CLPDM
AUX1IN
OFFSET
DAC
10
2:1
MUX
BUF
INTERNAL
BIAS
CML
AUX2IN
8
CONTROL
REGISTERS
CLP
DVDD
DVSS
DIGITAL
INTERFACE
INTERNAL
TIMING
AD9841A/AD9842A
SHP
SHD DATACLK
SL
SCK
SDATA
PxGA is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2001
AD9841A/AD9842A–SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
GENERAL SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
–20
–65
+85
+150
°C
°C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver
2.7
3.6
V
POWER CONSUMPTION
Normal Operation
Power-Down Modes
Fast Recovery Mode
Standby
(Specified Under Each Mode of Operation)
30
5
1
mW
mW
mW
Total Power-Down
MAXIMUM CLOCK RATE
20
10
MHz
A/D CONVERTER (AD9841A)
Resolution
Bits
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Data Output Coding
0.4
2.0
1.0
1.0
LSB
Bits Guaranteed
V
10
Straight Binary
A/D CONVERTER (AD9842A)
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
12
12
Bits
LSB
Bits Guaranteed
V
0.5
Full-Scale Input Voltage
2.0
Data Output Coding
Straight Binary
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
2.0
1.0
V
V
Specifications subject to change without notice.
(DRVDD = 2.7 V, C = 20 pF unless otherwise noted.)
DIGITAL SPECIFICATIONS
L
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
V
V
µA
µA
pF
0.6
10
10
10
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
VOH
VOL
2.2
V
V
0.5
Specifications subject to change without notice.
–2–
REV. 0
AD9841A/AD9842A
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless other-
wise noted.)
AD9841A CCD-MODE SPECIFICATIONS
Parameter
OWER CONSUMPTION
Min
Typ
Max
Unit
mW
Notes
P
78
See TPC 1 for Power Curves
MAXIMUM CLOCK RATE
20
MHz
CDS
Gain
0
500
dB
Allowable CCD Reset Transient1
Max Input Range Before Saturation1
Max CCD Black Pixel Amplitude1
mV
V p-p
mV
See Input Waveform in Footnote 1
PxGA Gain at 4 dB
1.0
200
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
1.0
1.6
V p-p
V p-p
Steps
PxGA Gain at 4 dB
At Any PxGA Gain
Gain Control Resolution
64
Gain Monotonicity
Guaranteed
Gain Range (Two’s Complement Coding)
Min Gain (PxGA Gain Code 32)
Max Gain (PxGA Gain Code 31)
See Figure 28 for PxGA Gain Curve
–2
10
dB
dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
1.6
2.0
V p-p
V p-p
Steps
Gain Control Resolution
1024
Gain Monotonicity
.
Guaranteed
Gain Range
Low Gain (VGA Gain Code 91)
Max Gain (VGA Gain Code 1023)
See Figure 29 for VGA Gain Curve
Measured at ADC Output
2
36
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
256
Steps
Min Clamp Level
Max Clamp Level
0
LSB
LSB
63.75
SYSTEM PERFORMANCE
Gain Accuracy, VGA Code 91 to 10232
PxGA Gain Accuracy
Min Gain (PxGA Register Code 32)
Max Gain (PxGA Code 31)
Peak Nonlinearity, 500 mV Input Signal
Peak Nonlinearity, 800 mV Input Signal
Total Output Noise
Specifications Include Entire Signal Chain
Use Equations on Page 19 to Calculate Gain
–0.5
+0.5
–1
11
0
+1
13
dB
dB
%
%
LSB rms
dB
VGA Gain Fixed at 2 dB (Code 91)
VGA Gain Fixed at 2 dB (Code 91)
12 dB Gain Applied
8 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
12
0.1
0.4
0.2
40
Power Supply Rejection (PSR)
Measured with Step Change on Supply
POWER-UP RECOVERY TIME
Fast Recovery Mode
Reference Standby Mode
Total Shutdown Mode
Power-Off Condition
Normal Clock Signals Applied
0.1
1
3
ms
ms
ms
ms
15
NOTES
1Input Signal Characteristics defined as follows:
500mV TYP
RESET TRANSIENT
200mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
2PxGA gain fixed at 4 dB.
Specifications subject to change without notice.
–3–
REV. 0
AD9841A/AD9842A–SPECIFICATIONS
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = fSHP = fSHD = 20 MHz, unless
AD9842A CCD-MODE SPECIFICATIONS otherwise noted)
Parameter
OWER CONSUMPTION
Min
Typ
Max
Unit
mW
Notes
P
78
See TPC 1 for Power Curves
MAXIMUM CLOCK RATE
20
MHz
CDS
Gain
0
500
dB
Allowable CCD Reset Transient1
Max Input Range Before Saturation1
Max CCD Black Pixel Amplitude1
mV
V p-p
mV
See Input Waveform in Footnote 1
PxGA Gain at 4 dB
1.0
200
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
1.0
1.6
V p-p
V p-p
Steps
Gain Control Resolution
64
Gain Monotonicity
Guaranteed
Gain Range (Two’s Complement Coding)
Min Gain (PxGA Gain Code 32)
Max Gain (PxGA Gain Code 31)
See Figure 28 for PxGA Gain Curve
–2
10
dB
dB
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
1.6
2.0
V p-p
V p-p
Steps
Gain Control Resolution
1024
Gain Monotonicity
Guaranteed
Gain Range
Low Gain (VGA Gain Code 91)
Max Gain (VGA Gain Code 1023)
See Figure 29 for VGA Gain Curve
Measured at ADC Output
2
36
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
256
Steps
Min Clamp Level
Max Clamp Level
0
255
LSB
LSB
SYSTEM PERFORMANCE
Gain Accuracy, (VGA Code 91 to 1023)2
PxGA Gain Accuracy
Min Gain (PxGA Register Code 32)
Max Gain (PxGA Code 31)
Peak Nonlinearity, 500 mV Input Signal
Specifications Include Entire Signal Chain
Use Equations on Page 19 to Calculate Gain
–0.5
+0.5
–1
11
0
+1
13
dB
dB
%
LSB rms
dB
VGA Gain Fixed at 2 dB (Code 91)
VGA Gain Fixed at 2 dB (Code 91)
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with step change on supply
12
0.1
0.6
40
Total Output Noise
Power Supply Rejection (PSR)
POWER-UP RECOVERY TIME
Fast Recovery Mode
Reference Standby Mode
Total Shutdown Mode
Power-Off Condition
Normal Clock Signals Applied
0.1
1
3
ms
ms
ms
ms
15
NOTES
1Input Signal Characteristics defined as follows:
500mV TYP
RESET TRANSIENT
200mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
2PxGA gain fixed at 4 dB.
Specifications subject to change without notice.
–4–
REV. 0
AD9841A/AD9842A
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
AUX1-MODE SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
mW
POWER CONSUMPTION
MAXIMUM CLOCK RATE
60
20
MHz
INPUT BUFFER
Gain
0
dB
Max Input Range
1.0
2.0
V p-p
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
V p-p
Steps
1023
0
36
dB
dB
Max Gain
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.)
AUX2-MODE SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
mW
POWER CONSUMPTION
MAXIMUM CLOCK RATE
INPUT BUFFER
60
20
MHz
(Same as AUX1-MODE)
512
VGA
Max Output Range
Gain Control Resolution
Gain (Selected Using VGA Gain Register)
Min Gain
2.0
V p-p
Steps
0
18
dB
dB
Max Gain
ACTIVE CLAMP (AD9841A)
Clamp Level Resolution
Clamp Level (Measured at ADC Output)
Min Clamp Level
256
Steps
0
LSB
LSB
Max Clamp Level
63.75
ACTIVE CLAMP (AD9842A)
Clamp Level Resolution
Clamp Level (Measured at ADC Output)
Min Clamp Level
256
Steps
0
255
LSB
LSB
Max Clamp Level
Specifications subject to change without notice.
–5–
REV. 0
AD9841A/AD9842A
(CL = 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
TIMING SPECIFICATIONS
Serial Timing in Figures 21–24.)
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK Hi/Low Pulsewidth
SHP Pulsewidth
tCONV
tADC
tSHP
tSHD
tCDM
tCOB
tS1
48
20
7
7
4
2
0
20
50
25
12.5
12.5
10
20
12.5
25
3.0
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth1
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
tS2
tID
Inhibited Clock Period
tINH
10
ns
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
tOD
tH
14.5
7.6
9
16
ns
ns
Cycles
7.0
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
NOTES
1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
ORDERING GUIDE
Temperature
ABSOLUTE MAXIMUM RATINGS
With
Package
Description
Package
Option
Respect
To
Model
Range
Parameter
Min Max
Unit
AD9841AJST –20°C to +85°C
Thin Plastic
Quad Flatpack
(LQFP)
Thin Plastic
Quad Flatpack
(LQFP)
ST-48
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
AVSS
DVSS
DRVSS –0.3 +3.9
–0.3 +3.9
–0.3 +3.9
V
V
V
V
V
V
V
V
AD9842AJST –20°C to +85°C
ST-48
Digital Outputs
DRVSS –0.3 DRVDD + 0.3
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK DVSS
DVSS
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 DVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
150
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-4, CCDIN
Junction Temperature
Lead Temperature
(10 sec)
DVSS
AVSS
AVSS
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
V
°C
°C
300
θ
JA = 92°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9841A/AD9842A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. 0
AD9841A/AD9842A
PIN CONFIGURATIONS
48 47 46 45 44 43 42 41 40 39 38 37
48 47 46 45 44 43 42 41 40 39 38 37
1
2
1
2
NC
NC
(LSB) D0
36
35
34
33
32
31
30
29
28
27
26
25
36
35
34
33
32
31
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
PIN 1
IDENTIFIER
PIN 1
IDENTIFIER
D1
3
3
D2
(LSB) D0
D1
4
4
D3
5
5
D4
D2
AD9841A
TOP VIEW
(Not to Scale)
AD9842A
TOP VIEW
(Not to Scale)
6
6
D3
D5
NC
NC
7
7
D6
D4
30
29
28
27
26
25
CCDIN
BYP2
CCDIN
BYP2
8
8
D5
D7
D8
9
9
D6
BYP1
BYP1
10
11
12
10
11
12
D7
D9
AVDD1
AVSS
AVSS
AVDD1
AVSS
AVSS
D10
D8
(MSB) D9
(MSB) D11
13 14 15 16 17 18 19 20 21 22 23 24
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin Number
Name
Type
Description
1, 2
3–12
1–12
13
14
15, 41
16
17
18
19
20
NC
NC
DO
DO
P
P
P
Internally Not Connected (AD9841A ONLY)
Digital Data Outputs (AD9841A ONLY)
Digital Data Outputs (AD9842A ONLY)
Digital Output Driver Supply
Digital Output Driver Ground
Digital Ground
Digital Data Output Latch Clock
Digital Supply
Horizontal Drive. Used with VD for Color Steering Control
Preblanking Clock Input
Black Level Clamp Clock Input
CDS Sampling Clock for CCD’s Reference Level
CDS Sampling Clock for CCD’s Data Level
Input Clamp Clock Input
Vertical Drive. Used with HD for Color Steering Control
Analog Ground
D0–D9
D0–D11
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
HD
PBLK
CLPOB
SHP
SHD
CLPDM
VD
AVSS
AVDD1
BYP1
BYP2
CCDIN
NC
DI
P
DI
DI
DI
DI
DI
DI
DI
P
21
22
23
24
25, 26, 35
27
28
29
30
31
32
33
34
36
37
38
39
40
42
43
44
P
Analog Supply
AO
AO
AI
NC
AO
P
AI
AI
AO
AO
AO
P
DI
NC
DI
NC
DI
DI
DI
Internal Bias Level Decoupling
Internal Bias Level Decoupling
Analog Input for CCD Signal
Internally Not Connected
Internal Bias Level Decoupling
Analog Supply
BYP4
AVDD2
AUX2IN
AUX1IN
CML
VRT
VRB
DVDD2
THREE-STATE
NC
STBY
NC
SL
SDATA
SCK
Analog Input
Analog Input
Internal Bias Level Decoupling
A/D Converter Top Reference Voltage Decoupling
A/D Converter Bottom Reference Voltage Decoupling
Digital Supply
Digital Output Disable. Active High
May be tied high or low. Do not leave floating.
Standby Mode, Active High. Same as Serial Interface
Internally Not Connected. May be Tied High or Low
Serial Digital Interface Load Pulse
Serial Digital Interface Data
45
46
47
48
Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
REV. 0
–7–
AD9841A/AD9842A
DEFINITIONS OF SPECIFICATIONS
in LSB, and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship 1 LSB
= (ADC Full Scale/2N codes) when N is the bit resolution of the
ADC. For the AD9842A, 1 LSB is 500 µV, and for the AD9841A,
1 LSB is 2 mV.
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every code
must have a finite width. No missing codes guaranteed to 12-bit
resolution indicates that all 4096 codes, respectively, must be
present over all operating conditions.
POWER SUPPLY REJECTION (PSR)
PEAK NONLINEARITY
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD984xA’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD984x from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately gained up
to fill the ADC’s full-scale range.
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from when a sampling edge is applied to the AD984xA
until the actual sample of the input signal is held. Both SHP and
SHD sample the input signal during the transition from low to
high, so the internal delay is measured from each clock’s rising
edge to the instant the actual internal sample is taken.
TOTAL OUTPUT NOISE
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
EQUIVALENT INPUT CIRCUITS
DVDD
ACVDD
330ꢀ
60ꢀ
ACVSS
ACVSS
DVSS
Figure 1. Digital Inputs—SHP, SHD, DATACLK, CLPOB,
CLPDM, HD, VD, PBLK, SCK, SL
Figure 3. CCDIN (Pin 30)
DRVDD
DVDD
DATA
DVDD
DVDD
DATA IN
THREE-
STATE
330ꢀ
DOUT
DATA OUT
RNW
DVSS
DVSS
DVSS
DRVSS
DVSS
Figure 2. Data Outputs—D0–D9 (D11)
Figure 4. SDATA (Pin 47)
–8–
REV. 0
Typical Performance Characteristics–
AD9841A/AD9842A
0.5
100
90
80
70
60
0.25
0
V
= 3.3V
DD
V
V
= 3.0V
= 2.7V
DD
DD
–0.25
–0.5
50
40
5
10
15
20
0
500
1000 1500 2000
2500 3000 3500 4000
SAMPLE RATE – MHz
TPC 4. AD9842A Typical DNL Performance
TPC 1. AD9841A/AD9842A Power vs. Sample Rate
0.5
15
0.25
0
10
5
–0.25
–0.5
0
400
0
200
600
800
1000
0
200
400
600
800
1000
VGA GAIN CODE – LSB
TPC 2. AD9841A Typical DNL Performance
TPC 5. AD9842A Output Noise vs. VGA Gain
4
3
2
1
0
0
400
VGA GAIN CODE – LSB
200
600
800
1000
TPC 3. AD9841A Output Noise vs. VGA Gain
REV. 0
–9–
AD9841A/AD9842A
CCD-MODE AND AUX MODE TIMING
CCD
SIGNAL
N
N+1
N+2
N+9
N+10
tID
tID
SHP
tS1
tS2
tCP
SHD
tINH
DATACLK
tOD
tH
OUTPUT
DATA
N–10
N–9
N–8
N–1
N
NOTES:
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 5. CCD-Mode Timing
HORIZONTAL
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
DUMMY PIXELS
EFFECTIVE PIXELS
BLANKING
CCD
SIGNAL
CLPOB
CLPDM
PBLK
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
Figure 6. Typical CCD-Mode Line Clamp Timing
N+9
N
N+1
N+8
tID
N+2
VIDEO
SIGNAL
tCP
DATACLK
tOD
tH
OUTPUT
DATA
N–10
N–9
N–8
N–1
N
Figure 7. AUX-Mode Timing
–10–
REV. 0
AD9841A/AD9842A
PIXEL GAIN AMPLIFIER (PxGA) TIMING
FRAME n
FRAME n+1
VD
0101...
LINE 2
0101...
LINE 0
2323...
LINE 1
0101...
LINE 2
0101...
LINE 0
2323...
LINE 1
LINE m–1
LINE m
LINE m–1
LINE m
HD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
5 PIXEL MIN
VD
HD
3ns MIN
GAIN0
3ns MIN
SHP
GAIN3
GAINX
GAIN1
GAIN0
GAINX
GAIN2
PxGA GAIN
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing
EVEN FIELD
ODD FIELD
VD
0101...
LINE 2
0101...
LINE 0
2323...
LINE 1
0101...
LINE 0
2323...
LINE 1
0101...
LINE 2
LINE m–1
LINE m
LINE m–1
LINE m
HD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
VD
HD
5 PIXEL MIN
3ns MIN
3ns MIN
SHP
PxGA
GAIN
GAINX
GAIN0
GAIN1
GAIN0
GAIN2
GAIN3
GAINX
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
Figure 11. PxGA Mode 2 (Interlace) Detailed Timing
REV. 0
–11–
AD9841A/AD9842A
LINE n
LINE n+1
VD
012012012...
...01201
012012012...
HD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
5 PIXEL MIN
VD
HD
5 PIXEL MIN
3ns MIN
SHP
GAIN1
GAIN2
GAIN0
GAIN0
GAIN1
GAINX
GAIN0
GAINX
PxGA GAIN
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.
Figure 13. PxGA Mode 3 (3-Color) Detailed Timing
LINE n
LINE n+1
VD
HD
01230123012...
...01230
012301230123...
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
5 PIXEL MIN
VD
HD
5 PIXEL MIN
3ns MIN
SHP
GAIN1
GAIN2
GAIN0
GAIN0
GAIN1
GAINX
GAIN0
GAINX
PxGA GAIN
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.
Figure 15. PxGA Mode 4 (4-Color) Detailed Timing
–12–
REV. 0
AD9841A/AD9842A
ODD FIELD
VD
HD
EVEN FIELD
0101...
2323...
2323...
LINE 0
0101...
LINE 1
2323...
LINE 1
0101...
LINE 0
LINE m–1
LINE m–1
LINE 2
LINE m
LINE 2
LINE m
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 16. PxGA Mode 5 (VD Selected) Frame/Line Gain Register Sequence
VD
HD
5 PIXEL MIN
3ns MIN
GAIN0
3ns MIN
SHP
GAIN3
GAINX
GAIN1
GAIN0
GAINX
GAIN2
PxGA GAIN
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 2323.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL REPEAT EITHER 0101... (EVEN) OR 2323 ... (ODD).
Figure 17. PxGA Mode 5 (VD Selected) Detailed Timing
FRAME n
FRAME n+1
VD
HD
1212...
LINE 1
1212...
LINE 1
0101...
LINE 2
0101...
LINE 0
0101...
LINE 2
0101...
LINE 0
LINE m–1
LINE m
LINE m–1
LINE m
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
Figure 18. PxGA Mode 6 (Mosaic Repeat) Frame/Line Gain Register Sequence
5 PIXEL MIN
VD
HD
3ns MIN
GAIN0
3ns MIN
SHP
GAINX
GAIN1
GAIN0
GAINX
GAIN1
GAIN2
PxGA GAIN
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 1212.
Figure 19. PxGA Mode 6 (Mosaic Repeat) Detailed Timing
REV. 0
–13–
AD9841A/AD9842A
VD
HD
3ns MIN
3ns MIN
SHP
GAIN0
GAIN3
GAIN1
GAIN2
GAIN0
PxGA GAIN
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. VD = 0 AND HD = 0 SELECTS GAIN0.
3. VD = 0 AND HD = 1 SELECTS GAIN1.
4. VD = 1 AND HD = 0 SELECTS GAIN2.
5. VD = 1 AND HD = 1 SELECTS GAIN3.
Figure 20. PxGA Mode 7 (User-Specified) Detailed Timing
–14–
REV. 0
AD9841A/AD9842A
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. AD9841A/AD9842A Internal Register Map
Register
Name
Address
A0 A1 A2 D0
Data Bits
D3 D4
D1
D2
D5
D6
D7
D8
D9
D10
Operation
0
0
0
Channel Select Power-Down
CCD/AUX1/2 Modes
Software OB Clamp
0*
1**
0*
0*
0*
Reset
On/Off
VGA Gain
Clamp Level
Control
1
0
1
0
1
1
0
0
0
LSB
LSB
MSB
X
X
X
X
MSB
X
Color Steering Mode
Selection
PxGA
Clock Polarity Select for
0*
0*
Three-
State
On/Off SHP/SHD/CLP/DATA
PxGA Gain0
PxGA Gain1
PxGA Gain2
PxGA Gain3
0
1
0
1
0
0
1
1
1
1
1
1
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
*
Internal use only. Must be set to zero.
**Must be set to one.
RNW
0
TEST BIT
SDATA
A0
A1
A2
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDS
tDH
SCK
SL
tLS
tLH
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 21. Serial Write Operation
RNW
1
TEST BIT
0
SDATA
SCK
A0
A1
0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDS
tDH
tDV
tLS
tLH
SL
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON
SCK FALLING EDGES.
Figure 22. Serial Readback Operation
REV. 0
–15–
AD9841A/AD9842A
11 BITS
OPERATION
10 BITS
8 BITS
10 BITS
CONTROL
6 BITS
PxGA GAIN0
6 BITS
PxGA GAIN1
6 BITS
PxGA GAIN2
6 BITS
PxGA GAIN3
ACG GAIN CLAMP LEVEL
RNW A0
A1 A2
...
...
...
...
...
...
...
...
SDATA
SCK
0
0
0
0
0
D9 D0
D10 D0
D9
D7 D0
D0
D5 D0
D0
D5
D0
D5
D5
D0
...
...
...
...
...
...
...
...
2
3
4
5
6
16 17
26 27
34 35
44 45
50 51
56 57
62 63
68
1
SL
...
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
Figure 23. Continuous Serial Write Operation to All Registers
PxGA GAIN3
PxGA GAIN2
PxGA GAIN1
D2
PxGA GAIN0
D2 D3
A2
1
RNW A0
A1
0
...
...
0
0
D3
D4
D5
D0
D5
D5
0
D0
D1
D4
D5
D0
D1
D0
SDATA
SCK
...
...
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
23
24
29
SL
...
Figure 24. Continuous Serial Write Operation to All PxGA Gain Registers
Table II. Operation Register Contents (Default Value x000)
Optical Black Clamp
D5
Reset
D4
Power-Down Modes
D3 D2
Channel Selection
D1 D0
D10 D9 D8 D7 D6
0
*
0
*
0
*
1
**
0
*
0
1
Enable Clamping
Disable Clamping
0 Normal
1 Reset All Registers
to Default
0
0
1
1
0
1
0
1
Normal Power
Fast Recovery
Standby
0
0
1
1
0
1
0
1
CCD Mode
AUX1 Mode
AUX2 Mode
Test Only
Total Power-Down
*Must be set to zero.
**Set to one.
Table III. VGA Gain Register Contents (Default Value x096)
MSB
D9
LSB
D0
D10
D8
D7
D6
D5
D4
D3
D2
D1
Gain (dB)
X
0
0
0
1
0
•
1
1
1
1
1
2.0
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
35.965
36.0
–16–
REV. 0
AD9841A/AD9842A
Table IV. AD9841A Clamp Level Register Contents (Default Value x080)
MSB
D7
LSB
D0
D10
D9
D8
D6
D5
D4
D3
D2
D1
Clamp Level (LSB)
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0.25
0.5
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
63.5
63.75
Table V. AD9842A Clamp Level Register Contents (Default Value x080)
MSB
D7
LSB
D0
D10
D9
D8
D6
D5
D4
D3
D2
D1
Clamp Level (LSB)
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
•
•
•
•
•
•
254
255
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
Table VI. Control Register Contents (Default Value x000)
Data Out
D9
DATACLK
D8 D7 D6
CLP/PBLK
D5
SHP/SHD
D4
PxGA
D3**
Color Steering Modes
D2 D1 D0
D10
X
0 Enable
1 Three-State
0* 0* 0 Rising Edge Trigger 0 Active Low 0 Active Low 0 Disable 0
0
0
1
1
0
0
1
1
0 Steering Disabled
1 Mosaic Separate
0 Interlace
1 3-Color
0 4-Color
1 VD Selected
0 Mosaic Repeat
1 User Specified
1 Falling Edge Trigger 1 Active High 1 Active High 1 Enable
0
0
0
1
1
1
1
*Must be set to zero.
**When D3 = 0 (PxGA disabled) the PxGA gain is fixed to 4 dB.
Table VII. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000)
MSB
D5
LSB
D0
D10
D9
D8
D7
D6
D4
D3
D2
D1
Gain (dB)*
X
X
X
X
X
0
1
1
1
1
1
+10.0
•
•
•
•
•
•
0
1
0
1
0
1
0
1
0
1
0
1
+4.3
+4.0
•
•
•
•
•
•
1
0
0
0
0
0
–2.0
*Control Register Bit D3 must be set High (PxGA Enable) to use the PxGA Gain Registers.
REV. 0
–17–
AD9841A/AD9842A
CIRCUIT DESCRIPTION AND OPERATION
effect of a gain change on the system black level, usually called
the “gain step.” Another advantage of removing this offset at
the input stage is to maximize system headroom. Some area
CCDs have large black level offset voltages, which, if not cor-
rected at the input stage, can significantly reduce the available
headroom in the internal circuitry when higher VGA gain set-
tings are used.
The AD9841A and AD9842A signal processing chain is shown
in Figure 25. Each processing step is essential in achieving a
high-quality image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc-
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V, to be compatible with the 3 V single supply of
the AD984xA.
Horizontal timing is shown in Figure 6. It is recommended
that the CLPDM pulse be used during valid CCD dark pixels.
CLPDM may be used during the optical black pixels, either
together with CLPOB or separately. The CLPDM pulse should
be a minimum of 4 pixels wide.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low-frequency noise. The timing
shown in Figure 5 illustrates how the two CDS clocks, SHP
and SHD, are used to sample the reference level and data level
of the CCD signal respectively. The CCD signal is sampled on
the rising edges of SHP and SHD. Placement of these two clock
signals is critical in achieving the best performance from the CCD.
An internal SHP/SHD delay (tID) of 3 ns is caused by internal
propagation delays.
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to “multiplex” its gain value
on a pixel-to-pixel basis. This allows lower output color pixels to
be gained up to match higher output color pixels. Also, the PxGA
may be used to adjust the colors for white balance, reducing the
amount of digital processing that is needed. The four different gain
values are switched according to the “Color Steering” circuitry.
Seven different color steering modes for different types of CCD
color filter arrays are programmed in the AD984xA’s Control
Register. For example, Mosaic Separate steering mode accom-
modates the popular “Bayer” arrangement of Red, Green, and
Blue filters (see Figure 26).
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded
black reference pixels. Unlike some AFE architectures, the
AD984xA removes this offset in the input stage to minimize the
VD
3
PxGA MODE
SELECTION
COLOR
STEERING
HD
2
GAIN0
GAIN1
GAIN2
GAIN3
PxGA GAIN
REGISTERS
4:1
MUX
DC RESTORE
CDS
INTERNAL
6
V
REF
2V FULL SCALE
2dB TO 36dB
VGA
0.1ꢁF
10/12
CCDIN
10-/12-BIT
ADC
DOUT
PxGA
–2dB TO +10dB
CLPOB
OPTICAL BLACK
CLAMP
8-BIT
DAC
INPUT OFFSET
CLAMP
10
CLPDM
DIGITAL
FILTERING
VGA GAIN
REGISTER
8
CLAMP LEVEL
REGISTER
Figure 25. AD9841A/AD9842A CCD-Mode Block Diagram
–18–
REV. 0
AD9841A/AD9842A
is needed to match a 1 V input signal with the ADC full-scale
range of 2 V. When compared to 1 V full-scale systems (such as
ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB.
MOSAIC SEPARATE COLOR
STEERING MODE
CCD: PROGRESSIVE BAYER
Gr LINE0
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
R
Gb
R
Gr
B
R
Gb
R
LINE1
B
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “linear-in-
dB” characteristic. From code 512 to code 1023, the curve follows
a “linear-in-dB” shape. The exact VGA gain can be calculated
for any Gain Register value by using the following two equations:
Gr
B
Gr
B
LINE2
Gb
Gb
Figure 26. CCD Color Filter Example: Progressive Scan
Code Range Gain Equation (dB)
CCD: INTERLACED BAYER
EVEN FIELD
VD SELECTED COLOR
STEERING MODE
0–511
512 –1023
Gain = 20 log10 ([658 + code]/[658 – code]) – 0.4
Gain = (0.0354)(code) – 0.4
Gr LINE0
Gr LINE1
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
R
R
R
R
Gr
Gr
Gr
Gr
R
R
R
R
As shown in the CCD Mode Specifications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 91 to 1023. The
Gain Accuracy Specifications also include the PxGA gain of 4 dB,
for a total gain range of 6 dB to 40 dB.
Gr
Gr
LINE2
ODD FIELD
36
30
24
18
12
6
Gb
B
Gb
B
LINE0
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
Gb
Gb
B
B
Gb
Gb
B
B
Gb
B
Gb
B
Figure 27. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD
Selected mode should be used with this type of CCD (see Fig-
ure 27). The Color Steering performs the proper multiplexing of
the R, G, and B gain values (loaded into the PxGA gain regis-
ters), and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the PxGA Timing section. The PxGA gain for each of the four
channels is variable from –2 dB to +10 dB, controlled in 64 steps
through the serial interface. The PxGA gain curve is shown in
Figure 28.
0
0
127
255
383
511
639
767
895
1023
VGA GAIN REGISTER CODE
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low-frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the Clamp Level
Register. Any value between 0 LSB and 64 LSB (AD9841A)
or 255 LSB (AD9842A) may be programmed, with 8-bit resolu-
tion. The resulting error signal is filtered to reduce noise, and
the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the post processing, the AD984xA’s optical black
clamping may be disabled using Bit D5 in the Operation Register
(see Serial Interface Timing and Internal Register Description
section). When the loop is disabled, the Clamp Level Register
may still be used to provide programmable offset adjustment.
10
8
6
4
2
0
-2
32
40
48
56
0
8
16
24
31
(011111)
(100000)
PxGA GAIN REGISTER CODE
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase, and the ability to track
low-frequency variations in the black level will be reduced.
Figure 28. PxGA Gain Curve
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with 4 dB from the PxGA stage, the total gain range
for the AD984xA is 6 dB to 40 dB. The minimum gain of 6 dB
REV. 0
–19–
AD9841A/AD9842A
A/D Converter
Figure 29). The VGA gains up the signal level with respect to
the 0.4 V bias level. Signal levels above the bias level will be
further increased to a higher ADC code, while signal levels below
the bias level will be further decreased to a lower ADC code.
The AD9841A and AD9842A use high-performance ADC archi-
tectures, optimized for high speed and low power. Differential
Nonlinearity (DNL) performance is typically better than 0.5 LSB,
as shown in TPCs 2 and 4. Instead of the 1 V full-scale range
used by the earlier AD9801 and AD9803 products from Analog
Devices, the AD984xA ADCs use a 2 V input range. Better
noise performance results from using a larger ADC full-scale
range (see TPCs 3 and 5).
AUX2 Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 31 shows the circuit
configuration for using the AUX2 channel input (Pin 34). A
external 0.1 µF blocking capacitor is used with the on-chip video
clamp circuit, to level-shift the input signal to a desired refer-
ence level. The clamp circuit automatically senses the most
negative portion of the input signal, and adjusts the voltage
across the input capacitor. This forces the black level of the
input signal to be equal to the value programmed into the Clamp
Level register (see Serial Interface Register Description). The VGA
provides gain adjustment from 0 dB to 18 dB. The same VGA
Gain register is used, but only the 9 MSBs of the gain register
are used (see Table VIII.)
AUX1 Mode
For applications that do not require CDS, the AD9841A/AD9842A
can be configured to sample ac-coupled waveforms. Figure 30
shows the circuit configuration for using the AUX1 channel
input (Pin 36). A single 0.1 µF ac-coupling capacitor is needed
between the input signal driver and the AUX1IN pin. An on-chip
dc-bias circuit sets the average value of the input signal to
approximately 0.4 V, which is referenced to the midscale code
of the ADC. The VGA Gain register provides a gain range of 0 dB
to 36 dB in this mode of operation (see VGA Gain Curve,
0.4V
0.8V
??V
0dB TO 36dB
5kꢀ
0.1ꢁF
AUX1IN
INPUT SIGNAL
VGA
ADC
MIDSCALE
10
0.4V
0.4V
VGA GAIN
REGISTER
Figure 30. AUX1 Circuit Configuration
VGA GAIN
REGISTER
9
0dB TO 18dB
BUFFER
AUX2IN
VIDEO
SIGNAL
ADC
VGA
0.1ꢁF
CLAMP LEVEL
VIDEO CLAMP
CIRCUIT
LPF
CLAMP LEVEL
REGISTER
8
Figure 31. AUX2 Circuit Configuration
Table VIII. VGA Gain Register Used for AUX2-Mode
MSB
D9
LSB
D0
D10
D8
D7
D6
D5
D4
D3
D2
D1
Gain (dB)
X
0
1
X
0
X
0
X
0
X
0
•
X
0
X
0
X
0
X
0
X
0
0.0
0.0
•
•
•
•
1
•
1
1
1
1
1
1
1
1
1
18.0
–20–
REV. 0
AD9841A/AD9842A
APPLICATIONS INFORMATION
digital conversion. The AD984xA’s digital output data is then
processed by the image processing ASIC. The internal regis-
ters of the AD984xA—used to control gain, offset level, and other
functions—are programmed by the ASIC or microprocessor
through a 3-wire serial digital interface. A system timing gen-
erator provides the clock signals for both the CCD and the AFE.
The AD9841A and AD9842A are complete Analog Front End
(AFE) products for digital still camera and camcorder appli-
cations. As shown in Figure 32, the CCD image (pixel) data is
buffered and sent to the AD984xA analog input through a series
input capacitor. The AD984xA performs the dc restoration,
CDS, gain adjustment, black level correction, and analog-to-
DIGITAL
OUTPUTS
AD984xA
ADC
CCD
V
OUT
0.1ꢁF
OUT
DIGITAL IMAGE
PROCESSING
ASIC
SERIAL
INTERFACE
CCDIN
REGISTER
DATA
BUFFER
CDS/CLAMP
TIMING
V-DRIVE
CCD
TIMING
TIMING
GENERATOR
Figure 32. AD984xA System Applications Diagram
3V
ANALOG SUPPLY
0.1ꢁF
1.0ꢁF
3
SERIAL
INTERFACE
1.0ꢁF
0.1ꢁF
48 47 46 45 44 43 42 41 40 39 38 37
NC
NC
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
1
2
36
35
34
33
32
31
30
29
28
27
26
25
PIN 1
IDENTIFIER
0.1ꢁF
0.1ꢁF
(LSB) D0
D1
3
3V
ANALOG SUPPLY
4
D2
5
D3
NC
AD9841A
6
D4
TOP VIEW
CCDIN
BYP2
7
CCD SIGNAL
(Not to Scale)
D5
0.1ꢁF
8
D6
BYP1
0.1ꢁF
0.1ꢁF
9
D7
AVDD1
AVSS
AVSS
10
11
12
D8
(MSB) D9
3V
ANALOG SUPPLY
0.1ꢁF
10
DATA
OUTPUTS
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
3V
DRIVER
SUPPLY
0.1ꢁF
8
CLOCK
INPUTS
0.1ꢁF
3V
ANALOG SUPPLY
Figure 33. AD9841A Recommended Circuit Configuration for CCD-Mode
REV. 0
–21–
AD9841A/AD9842A
3V
ANALOG SUPPLY
0.1ꢁF
1.0ꢁF
1.0ꢁF
0.1ꢁF
3
SERIAL
INTERFACE
48 47 46 45 44 43 42 41 40 39 38 37
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
1
2
36
35
34
33
32
31
30
29
28
27
26
25
PIN 1
IDENTIFIER
0.1ꢁF
0.1ꢁF
3V
3
ANALOG SUPPLY
4
5
NC
AD9842A
6
TOP VIEW
CCDIN
BYP2
7
CCD SIGNAL
(Not to Scale)
0.1ꢁF
8
BYP1
0.1ꢁF
0.1ꢁF
9
AVDD1
AVSS
AVSS
10
11
12
3V
(MSB) D11
ANALOG SUPPLY
0.1ꢁF
12
DATA
OUTPUTS
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
3V
DRIVER
SUPPLY
0.1ꢁF
8
CLOCK
INPUTS
0.1ꢁF
3V
ANALOG SUPPLY
Figure 34. AD9842A Recommended Circuit Configuration for CCD-Mode
Internal Power-On Reset Circuitry
the lowest possible impedance path between the power and bypass
pins and their respective ground pins. All decoupling capaci-
tors should be located as close as possible to the package pins. A
single clean power supply is recommended for the AD9841A/AD9842A,
but a separate digital driver supply may be used for DRVDD
(Pin 13). DRVDD should always be decoupled to DRVSS (Pin
14), which should be connected to the analog ground plane.
Advantages of using a separate digital driver supply include using a
lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing
digital power dissipation, and reducing potential noise coupling.
If the digital outputs (Pins 3–12) must drive a load larger than
20 pF, buffering is recommended to reduce digital code transi-
tion noise. Alternatively, placing series resistors close to the
digital output pins may also help reduce noise.
After power-on, the AD9842A will automatically reset all inter-
nal registers and perform internal calibration procedures. This
takes approximately 1 ms to complete. During this time, normal
clock signals and serial write operations may occur. However,
serial register writes will be ignored until the internal reset
operation is completed. Pin 43 (formerly RSTB on the AD9842A
non-A) is no longer used for the reset operation. Toggling Pin
43 in the AD9842A will have no effect.
Grounding and Decoupling Recommendations
As shown in Figures 33 and 34, a single ground plane is recom-
mended for the AD9841A/AD9842A. This ground plane should be
as continuous as possible, particularly around Pins 25 through
39. This will ensure that all analog decoupling capacitors provide
–22–
REV. 0
AD9841A/AD9842A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead LQFP
(ST-48)
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
12
25
0ꢂ
MIN
13
24
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
0.057 (1.45)
0.053 (1.35)
7ꢂ
0ꢂ
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. 0
–23–
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