AD9847AKSTRL [ADI]
IC SPECIALTY CONSUMER CIRCUIT, PQFP48, 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48, Consumer IC:Other;
| 型号： | AD9847AKSTRL |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQFP48, 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48, Consumer IC:Other 驱动器 CD |
| 文件： | 总28页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit 40 MSPS CCD Signal Processor
with Integrated Timing Driver
a
AD9847
FEATURES
GENERAL DESCRIPTION
Correlated Double Sampler (CDS)
–2 dB to +10 dB Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 40 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver
Precision Timing™ Core with 500 ps
Resolution at 40 MSPS
The AD9847 is a highly integrated CCD signal processor for
digital still camera applications. The AD9847 includes a com-
plete analog front end with A/D conversion, combined with
a programmable timing driver. The Precision Timing core allows
adjustment of high speed clocks with approximately 500 ps
resolution at clock speeds of 40 MHz.
The AD9847 is specified at pixel rates of 40 MHz. The analog
front end includes black level clamping, CDS, PxGA, VGA, and a
10-bit A/D converter. The timing driver provides the high speed
CCD clock drivers for RG and H1–H4. Operation is programmed
using a 3-wire serial interface.
On-Chip 5 V Horizontal and RG Drivers
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Packaged in a space-saving 48-lead LQFP, the AD9847 is speci-
fied over an operating temperature range of –20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VRT VRB
VREF
4 ꢀ 6dB
2dB TO 36dB
VGA
10
DOUT
CDS
ADC
PxGA
CCDIN
CLAMP
CLAMP
INTERNAL
CLOCKS
CLPOB
CLPDM
PBLK
CLI
RG
PRECISION
TIMING
CORE
HORIZONTAL
DRIVERS
4
H1–H4
SYNC
GENERATOR
INTERNAL
REGISTERS
AD9847
HD
VD
SL
SCK SDATA
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc.
–SPECIFICATIONS
AD9847
GENERAL SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
–20
–65
+85
+150
°C
°C
MAXIMUM CLOCK RATE
40
MHz
POWER SUPPLY VOLTAGE
Analog (AVDD1, 2, 3)
Digital1 (DVDD1) H1–H4
Digital2 (DVDD2) RG
Digital3 (DVDD3) D0–D11
Digital4 (DVDD4) All Other Digital
2.7
3.0
3.0
3.6
5.5
5.5
V
V
V
V
V
3.0
3.0
POWER DISSIPATION
DVDD1 (@ 5 V, 100 pF H Loading, 40 MSPS)
DVDD2 (@ 5 V, 20 pF RG Loading, 40 MSPS)
DVDD1 (@ 3 V, 100 pF H Loading, 40 MSPS)
DVDD2 (@ 3 V, 20 pF H Loading, 40 MSPS)
AVDD1, 2, 3, DVDD3, 4 (@ 3 V, 40 MSPS)
Total Shutdown Mode
450
45
180
15
200
1
mW
mW
mW
mW
mW
mW
Specifications subject to change without notice.
(TMIN to TMAX, AVDD1 = DVDD3, DVDD4 = 2.7 V, DVDD1, DVDD2 = 5.25 V, CL = 20 pF, unless
DIGITAL SPECIFICATIONS otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
V
V
µA
µA
pF
0.6
10
10
10
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
VOH
VOL
2.2
V
V
0.5
CLI INPUT
High Level Input Voltage
(AVDD1, 2 + 0.5 V)
Low Level Input Voltage
VIH–CLI
VIL–CLI
1.85
V
V
0.85
RG AND H-DRIVER OUTPUTS
High Level Output Voltage
(DVDD1, 2 – 0.5 V)
Low Level Output Voltage
VOH
VOL
4.75
V
V
0.5
Maximum Output Current (Programmable)
Maximum Load Capacitance
24
100
mA
pF
Specifications subject to change without notice.
–2–
REV. A
AD9847
(TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.)
ANALOG SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Notes
CDS
Gain
0
500
dB
Allowable CCD Reset Transient*
Max Input Range before Saturation*
Max CCD Black Pixel Amplitude*
mV
V p-p
mV
1.0
150
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
1.0
1.6
V p-p
V p-p
Steps
64
Guaranteed
Min Gain (32)
Med Gain (0)
Max Gain (31)
–2
4
10
dB
dB
dB
Med Gain (4 dB) Is Default Setting
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
1.6
2.0
V p-p
V p-p
Steps
1024
Guaranteed
Low Gain (91)
Max Gain (1023)
2
36
dB
dB
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
256
Steps
Measured at ADC Output
Min Clamp Level (0)
Max Clamp Level (255)
0
LSB
LSB
63.75
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
10
Bits
LSB
0.4
Guaranteed
2.0
1.0
Full-Scale Input Voltage
V
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
2.0
1.0
V
V
SYSTEM PERFORMANCE
Specifications Include Entire
Signal Chain
Gain Accuracy
Gain Includes 4 dB Default PxGA
Low Gain (91)
Max Gain (1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
5
6
7
dB
dB
%
LSB rms
dB
38
0.2
0.25
40
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with Step Change on Supply
*Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
1V MAX
150mV MAX
INPUT
OPTICAL
SIGNAL RANGE
BLACK PIXEL
Specifications subject to change without notice.
–3–
REV. A
AD9847
(C to 29 pF, fCLI = 40 MHz, Serial Timing in Figures 3a and 3b, unless otherwise noted.)
TIMING SPECIFICATIONS
Parameter
L
Symbol
Min
Typ
Max
Unit
MASTER CLOCK (CLI)
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI to Internal Pixel
Period Position
tCLI
tADC
25
12.5
ns
ns
tCLIDLY
6
ns
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth
CLPOB Pulsewidth*
tCDM
tCOB
4
2
10
20
Pixels
Pixels
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge
tS1
10
ns
DATA OUTPUTS
Output Delay from Programmed Edge
Pipeline Delay
tOD
6
9
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
–4–
REV. A
AD9847
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package . . . . . . . . . . . . . . . . . . . JA = 92°C/W
AVDD1, 2, 3 to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V
DVDD1, 2 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +5.5 V
DVDD3, 4 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V
Digital Outputs to DVSS3 . . . . . . . . –0.3 to DVDD3 + 0.3 V
CLPOB, CLPDM, BLK to DVSS4 . –0.3 to DVDD4 + 0.3 V
CLI to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
SCK, SL, SDATA to DVSS4 . . . . . –0.3 to DVDD4 + 0.3 V
VRT, VRB to AVSS . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
BYP1–3, CCDIN to AVSS . . . . . . . . –0.3 to AVDD + 0.3 V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (10 sec) . . . . . . . . . . . . . . . . . . . . . . 300°C
ORDERING GUIDE
Package
Temperature
Range
Package
Option
Model
Description
AD9847AKST
–20°C to +85°C
Thin Plastic Quad Flatpack (LQFP)
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9847 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–5–
AD9847
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
(LSB) D0
D1
36
35
34
33
32
31
30
29
28
27
26
25
SL
PIN 1
IDENTIFIER
REFT
D2
D3
REFB
CMLEVEL
AVSS3
AVDD3
D4
AD9847
DVSS3
DVDD3
D5
TOP VIEW
BYP3
CCDIN
(Not to Scale)
D6
BYP2
D7 10
BYP1
11
D8
AVDD2
AVSS2
12
(MSB) D9
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic
Type*
1–5
6
7
8–12
13, 14
15
16
17, 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
D0–D4
DVSS3
DVDD3
D5–D9
H1, H2
DVSS1
DVDD1
H3, H4
DVSS2
RG
DVDD2
AVSS1
CLI
AVDD1
AVSS2
AVDD2
BYP1
BYP2
CCDIN
BYP3
AVDD3
AVSS3
CMLEVEL
REFB
REFT
SL
DO
P
P
DO
DO
P
P
DO
P
DO
P
P
Data Outputs
Digital Ground 3—Data Outputs
Digital Supply 3—Data Outputs
Data Outputs (D9 I MSB)
S
Horizontal Clocks (to CCD)
Digital Ground 1—H Drivers
Digital Supply 1—H Drivers
Horizontal Clocks (to CCD)
Digital Ground 1—RG Driver
Reset Gate Clock (to CCD)
Digital Supply 2—RG Driver
Analog Ground 1
Master Clock Input
Analog Supply 1
Analog Ground 2
Analog Supply 2
Bypass Pin (0.1 µF to AVSS)
Bypass Pin (0.1 µF to AVSS)
Analog Input for CCD Signal
Bypass Pin (0.1 µF to AVSS)
Analog Supply 3
DI
P
P
P
AO
AO
AI
AO
P
P
Analog Ground 3
AO
AO
AO
DI
DI
DI
DI
DI
DI
DI
DI
DI
P
Internal Bias Level Decoupling (0.1 µF to AVSS)
Reference Bottom Decoupling (1.0 µF to AVSS)
Reference Top Decoupling (1.0 µF to AVSS)
3-Wire Serial Load (from µP)
3-Wire Serial Data Input (from µP)
3-Wire Serial Clock (from µP)
Optical Black Clamp Pulse
Dummy Black Clamp Pulse
HCLK Blanking Pulse
Preblanking Pulse
Vertical Sync Pulse
SDI
SCK
CLPOB
CLPDM
HBLK
PBLK
VD
HD
Horizontal Sync Pulse
DVSS4
DVDD4
NC
Digital Ground 4—VD, HD, CLPOB, CLPDM, HBLK, PBLK, SCK, SL, SDATA
Digital Supply 4—VD, HD, CLPOB, CLPDM, HBLK, PBLK, CK, SL
Internally Not Connected
46
47, 48
P
NC
*Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
–6–
REV. A
AD9847
Equivalent Input/Output Circuits
AVDD2
DVDD4
R
330ꢁ
AVSS2
AVSS2
DVSS4
Circuit 1. CCDIN (Pin 29)
Circuit 4. Digital Inputs (Pins 36–44)
AVDD1
DVDD1
DATA
330ꢁ
25kꢁ
CLI
1.4V
OUTPUT
ENABLE
AVSS1
Circuit 2. CLI (Pin 23)
DVSS1
DVDD4
DVDD3
Circuit 5. H1–H4 and RG (Pins 13, 14, 17, 18, 20)
DATA
THREE-
STATE
DOUT
DVSS4
DVSS3
Circuit 3. Data Outputs D0–D9 (Pins 1–5, 8–12)
Typical Performance Characteristics
0.50
4
3
2
1
0
0.25
0
–0.25
–0.50
0
200
400
600
800
1000
0
200
400
600
800
1000
VGA GAIN CODE – LSB
TPC 1. Typical DNL
TPC 2. Output Noise vs. VGA Gain Setting
REV. A
–7–
AD9847
SYSTEM OVERVIEW
V-DRIVER
Figures 1a and 1b show the typical system application diagrams
for the AD9847. The CCD output is processed by the AD9847’s
AFE circuitry, which consists of a CDS, PxGA, VGA, black
level clamp, and A/D converter. The digitized pixel information is
sent to the digital image processor chip, where all post-processing
and compression occurs. To operate the CCD, CCD timing param-
eters are programmed into the AD9847 from the image processor
through the 3-wire serial interface. From the system master clock,
CLI, provided by the image processor, the AD9847 generates
the high speed CCD clocks and all internal AFE clocks. All
AD9847 clocks are synchronized with VD and HD.
V1–V4, VSG1–VSG8, SUBCK
H1–H4, RG
DOUT
CLPOB
CLPDM
CCDIN
DIGITAL IMAGE
PROCESSING
ASIC
CCD
AD9847
INTEGRATED
AFE + TD
PBLK
HBLK
HD, VD
CLI
SERIAL
INTERFACE
V-DRIVER
Figure 1b. Typical Application (External Mode)
V1–V4, VSG1–VSG8, SUBCK
Figure 2 shows the horizontal and vertical counter dimensions for
the AD9847. All internal horizontal clocking is programmed using
these dimensions to specify line and pixel locations.
H1–H4, RG
DOUT
CCDIN
CCD
AD9847
INTEGRATED
AFE + TD
MAXIMUM FIELD DIMENSIONS
DIGITAL IMAGE
PROCESSING
ASIC
HD, VD
CLI
12-BIT HORIZONTAL = 4096 PIXELS MAX
12-BIT VERTICAL = 4096 LINES MAX
SERIAL
INTERFACE
Figure 1a. Typical Application (Internal Mode)
Figure 1a shows the AD9847 used in internal mode, in which all
the horizontal pulses (CLPOB, CLPDM, PBLK, and HBLK)
are programmed and generated internally. Figure 1b shows the
AD9847 operating in external mode, in which the horizontal
pulses are supplied externally by the image processor.
The H-drivers for H1–H4 and RG are included in the AD9847,
allowing these clocks to be directly connected to the CCD. The
AD9847 supports H-drive voltage of 5 V.
Figure 2. Vertical and Horizontal Counters
–8–
REV. A
AD9847
SERIAL INTERFACE TIMING
SDATA
A0
A1
tDS
A2
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
XX
XX
A3
tDH
SCK
tLS
tLH
SL
VD
SL UPDATED
VD/HD UPDATED
HD
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS.
3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED.
4. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
Figure 3a. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
...
...
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
D0
D1
D2
D3
D4
D5
D0
A3
D1
D2
SCK
SL
...
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 6-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA-WORD (ALL SIX BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
Figure 3b. Continuous Serial Write Operation
COMPLETE REGISTER LISTING
Table I. SL Updated Registers
Register
Register
Description
Description
oprmode
ctlmode
AFE Operation Modes
AFE Control Modes
h1drv
h2drv
H1 Drive Current
H2 Drive Current
preventpdate
readback
vdhdpol
Prevents Loading of VD-Updated Registers
Enables Serial Register Readback Mode
VD/HD Active Polarity
h3drv
h4drv
rgpol
H3 Drive Current
H4 Drive Current
RG Polarity
fieldval
Internal Field Pulse Value
rgposloc
rgnegloc
rgdrv
shpposloc
shdposloc
RG Positive Edge Location
RG Negative Edge Location
RG Drive Current
SHP Sample Location
SHD Sample Location
hblkretime
tgcore_rstb
h12pol
h1posloc
h1negloc
Retimes the H1 hblk to Internal Clock
Reset Bar Signal for Internal TG Core
H1/H2 Polarity Control
H1 Positive Edge Location
H1 Negative Edge Location
NOTES
All addresses and default values are expressed in hexadecimal.
All registers are VD/HD updated as shown in Figure 3a, except for those that are SL updated.
REV. A
–9–
AD9847
Accessing a Double-Wide Register
clpdmscp3 register, the contents of Address 0x81 must be
written first, followed by the contents of Address 0x82. The
register will be updated after the completion of the write to
Register 0x82, either at the next SL rising edge or the next
VD/HD falling edge.
There are many double-wide registers in the AD9847, e.g.,
oprmode, clpdmtog1_0, and clpdmscp3, and so on. These regis-
ters are configured into two consecutive 6-bit registers with the
least significant six bits located in the lower of the two addresses
and the remaining most significant bits located in the higher of
the two addresses. For example, the six LSBs of the clpdmscp3
register, clpdmscp3[5:0], are located at address 0x81. The most
significant six bits of the clpdmscp3 register, clpdmscp3[11:6],
are located at Address 0x82. The following rules must be fol-
lowed when accessing double-wide registers:
3. A single write to the lower of the two consecutive addresses
of a double-wide register that is not followed by a write to the
higher address of the registers is not permitted. This will not
update the register.
4. A single write to the higher of the two consecutive addresses of a
double-wide register that is not preceded by a write to the lower
of the two addresses is not permitted. Although the write to the
higher address will update the full double-wide register, the
lower six bits of the register will be written with an indetermi-
nate value if the lower address was not written to first.
1. When accessing a double-wide register, BOTH addresses
must be written to.
2. The lower of the two consecutive addresses for the double-
wide register must be written to first. In the example of the
Bit
Content
Default
Value
Address
Width
Register Name
Register Description
AFE Registers # Bits 56
00
01
02
03
04
05
06
07
08
09
0A
[5:0]
[1:0]
[5:0]
[3:0]
[5:0]
[1:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
6
2
6
4
6
2
6
6
6
6
6
00
00
16
02
00
02
00
00
00
00
00
oprmode[5:0]
oprmode[7:6]
ccdgain[5:0]
ccdgain[9:6]
refblack[5:0]
refblack[7:6]
ctlmode
pxga gain0
pxga gain1
pxga gain2
pxga gain3
AFE Operation Mode (See AFE Register Breakdown)
VGA Gain
Black Clamp Level
Control Mode (See AFE Register Breakdown)
PxGA Color 0 Gain
PxGA Color 1 Gain
PxGA Color 2 Gain
PxGA Color 3 Gain
Miscellaneous/Extra # Bits 26
0F
[5:0]
6
00
INITIAL2
See Recommended Power Up Sequence Section. Should be
set to “4” decimal (000100).
16
17
18
19
1B
1C
[0]
1
6
6
1
6
1
00
00
00
00
00
00
out_cont
Output Control (0 = Make All Outputs DC Inactive)
Serial Data Update Control (Sets the line within the field
for serial data update to occur)
Prevent the Update of the VD/HD Updated Registers
DOUT Phase Control
Disable CCDIN DC Restore Circuit During PBLK
(1 = Disable)
[5:0]
[5:0]
[0]
[5:0]
[0]
update[5:0]
update[11:6]
preventupdate
doutphase
disablerestore
1D
1E
[0]
[0]
1
1
00
01
vdhdpol
fieldval
VD/HD Active Polarity (0 = Low Active, 1 = High Active)
Internal Field Pulse Value (0 = Next Field Odd,
1 = Next Field Even)
1F
20
[0]
[5:0]
1
6
00
00
hblkretime
INITIAL1
Re-Sync hblk to h1 Clock
See Recommended Power Up Sequence. Should be set to
“53” decimal (110101).
26
[0]
1
00
tgcore_rstb
TG Core Reset_Bar (0 = Hold TG Core in Reset,
1 = Resume Normal Operation)
–10–
REV. A
AD9847
Bit
Default
Address Content Width Value
Register Name
Register Description
CLPDM # Bits 146
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
[0]
[0]
[0]
1
1
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
0
2
6
6
2
6
6
2
6
6
2
01
00
01
2C
00
35
00
01
3E
02
16
03
00
3F
3F
3F
3F
01
3F
3F
3F
3F
00
00
3F
3F
00
3F
3F
00
3F
3F
00
clpdmdir
clpdmpol
clpdmspol0
CLPDM Internal/External (0 = Internal, 1 = External)
CLPDM External Active Polarity (0 = Low Active, 1 = High Active)
Sequence #0: Start Polarity for CLPDM
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
clpdmtog1_0[5:0]
clpdmtog1_0[11:6]
clpdmtog2_0[5:0]
clpdmtog2_0[11:6]
clpdmspol1
clpdmtog1_1[5:0]
clpdmtog1_1[11:6]
clpdmtog2_1[5:0]
clpdmtog2_1[11:6]
clpdmspol2
clpdmtog1_2[5:0]
clpdmtog1_2[11:6]
clpdmtog2_2[5:0]
clpdmtog2_2[11:6]
clpdmspol3
clpdmtog1_3[5:0]
clpdmtog1_3[11:6]
clpdmtog2_3[5:0]
clpdmtog2_3[11:6]
clpdmscp0
Sequence #0: Toggle Position 1 for CLPDM
Sequence #0: Toggle Position 2 for CLPDM
Sequence #1: Start Polarity for CLPDM
Sequence #1: Toggle Position 1 for CLPDM
Sequence #1: Toggle Position 2 for CLPDM
Sequence #2: Start Polarity for CLPDM
Sequence #2: Toggle Position 1 for CLPDM
Sequence #2: Toggle Position 2 for CLPDM
Sequence #3: Start Polarity for CLPDM
Sequence #3: Toggle Position 1 for CLPDM
Sequence #3: Toggle Position 2 for CLPDM
CLPDM Sequence-Change-Position #0 (Hardcoded to 0)
CLPDM Sequence Pointer for SCP #0
CLPDM Sequence-Change-Position #1
7A
7B
7C
7D
7E
7F
80
81
82
83
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
clpdmsptr0
clpdmscp1[5:0]
clpdmscp1[11:6]
clpdmsptr1
clpdmscp2[5:0]
clpdmscp2[11:6]
clpdmsptr2
clpdmscp3[5:0]
clpdmscp3[11:6]
clpdmsptr3
CLPDM Sequence Pointer for SCP #1
CLPDM Sequence-Change-Position #2
CLPDM Sequence Pointer for SCP #2
CLPDM Sequence-Change-Position #3
CLPDM Sequence Pointer for SCP #3
REV. A
–11–
AD9847
Bit
Default
Value
Address
Content Width
Register Name
Register Description
CLPOB # Bits 146
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
[0]
[0]
[0]
1
1
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
0
2
6
6
2
6
6
2
6
6
2
01
00
01
0E
00
2B
00
01
2B
06
3F
3F
00
3F
3F
3F
3F
01
3F
3F
3F
3F
00
03
01
00
01
02
00
00
37
03
03
clpobdir
clpobpol
clpobpol0
CLPOB Internal/External (0 = Internal, 1 = External)
CLPOB External Active Polarity (0 = Low Active, 1 = High Active)
Sequence #0: Start Polarity for CLPOB
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
clpobtog1_0[5:0]
clpobtog1_0[11:6]
clpobtog2_0[5:0]
clpobtog2_0[11:6]
clpobpol1
clpobtog1_1[5:0]
clpobtog1_1[11:6]
clpobtog2_1[5:0]
clpobtog2_1[11:6]
clpobspol2
clpobtog1_2[5:0]
clpobtog1_2[11:6]
clpobtog2_2[5:0]
clpobtog2_2[11:6]
clpobspol3
clpobtog1_3[5:0]
clpobtog1_3[11:6]
clpobtog2_3[5:0]
clpobtog2_3[11:6]
clpobscp0
Sequence #0: Toggle Position 1 for CLPOB
Sequence #0: Toggle Position 2 for CLPOB
Sequence #1: Start Polarity for CLPOB
Sequence #1: Toggle Position 1 for CLPOB
Sequence #1: Toggle Position 2 for CLPOB
Sequence #2: Start Polarity for CLPOB
Sequence #2: Toggle Position 1 for CLPOB
Sequence #2: Toggle Position 2 for CLPOB
Sequence #3: Start Polarity for CLPOB
Sequence #3: Toggle Position 1 for CLPOB
Sequence #3: Toggle Position 2 for CLPOB
CLPOB Sequence-Change-Position #0 (Hardcoded to 0)
CLPOB Sequence Pointer for SCP #0
CLPOB Sequence-Change-Position #1
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
clpobsptr0
clpobscp1[5:0]
clpobscp1[11:6]
clpobsptr1
clpobscp2[5:0]
clpobscp2[11:6]
clpobsptr2
clpobscp3[5:0]
clpobscp3[11:6]
clpobsptr3
CLPOB Sequence Pointer for SCP #1
CLPOB Sequence-Change-Position #2
CLPOB Sequence Pointer for SCP #2
CLPOB Sequence-Change-Position #3
CLPOB Sequence Pointer for SCP #3
–12–
REV. A
AD9847
Bit
Default
Address Content Width Value
HBLK # Bits 147
Register Name
Register Description
A4
A5
A6
[0]
[0]
[0]
1
1
1
01
00
01
hblkdir
hblkpol
hblkextmask
HBLK Internal/External (0 = Internal, 1 = External)
HBLK External Active Polarity (0 = Low Active, 1 = High Active)
HBLK External Masking Polarity (0 = Mask H1 and H3 Low,
1 = Mask H1 and H3 High)
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
[0]
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
0
2
6
6
2
6
6
2
6
6
2
01
3E
00
0D
06
01
38
00
3C
02
00
3F
3F
3F
3F
01
3F
3F
3F
3F
00
00
3F
3F
00
3F
3F
00
3F
3F
00
hblkmask0
Sequence #0: Masking Polarity for HBLK
Sequence #0: Toggle Low Position for HBLK
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
hblktog1_0[5:0]
hblktog1_0[11:6]
hblkbtog2_0[5:0]
hblkbtog2_0[11:6]
hblkmask1
hblktog1_1[5:0]
hblktog1_1[11:6]
hblktog2_1[5:0]
hblktog2_1[11:6]
hblkmask2
hblktog1_2[5:0]
hblktog1_2[11:6]
hblktog2_2[5:0]
hblktog2_2[11:6]
hblkmask3
hblktog1_3[5:0]
hblktog1_3[11:6]
hblktog2_3[5:0]
hblktog2_3[11:6]
hblkscp0
Sequence #0: Toggle High Position for HBLK
Sequence #1: Masking Polarity for HBLK
Sequence #1: Toggle Low Position for HBLK
Sequence #1: Toggle High Position for HBLK
Sequence #2: Masking Polarity for HBLK
Sequence #2: Toggle Low Position for HBLK
Sequence #2: Toggle High Position for HBLK
Sequence #3: Masking Polarity for HBLK
Sequence #3: Toggle Low Position for HBLK
Sequence #3: Toggle High Position for HBLK
HBLK Sequence-Change-Position #0 (Hardcoded to 0)
HBLK Sequence Pointer for SCP #0
HBLK Sequence-Change-Position #1
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
hblksptr0
hblkscp1[5:0]
hblkscp1[11:6]
hblksptr1
hblkscp2[5:0]
hblkscp2[11:6]
hblksptr2
hblkscp3[5:0]
hblkscp3[11:6]
hblksptr3
HBLK Sequence Pointer for SCP #1
HBLK Sequence-Change-Position #2
HBLK Sequence Pointer for SCP #2
HBLK Sequence-Change-Position #3
HBLK Sequence Pointer for SCP #3
REV. A
–13–
AD9847
Bit
Default
Value
Address Content Width
Register Name
Register Description
PBLK # Bits 146
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
[0]
[0]
[0]
1
1
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
0
2
6
6
2
6
6
2
6
6
2
01
00
01
3D
00
2A
06
00
2A
06
3F
3F
00
3F
3F
3F
3F
01
3F
3F
3F
3F
00
02
01
00
01
02
00
00
37
03
02
pblkdir
pblkpol
pblkspol0
PBLK Internal/External (0 = Internal, 1 = External)
PBLK External Active Polarity (0 = Low Active, 1 = High Active)
Sequence #0: Start Polarity for PBLK
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
pblktog1_0[5:0]
pblktog1_0[11:6]
pblkbtog2_0[5:0]
pblkbtog2_0[11:6]
pblkspol1
pblktog1_1[5:0]
pblktog1_1[11:6]
pblktog2_1[5:0]
pblktog2_1[11:6]
pblkspol2
pblktog1_2[5:0]
pblktog1_2[11:6]
pblktog2_2[5:0]
pblktog2_2[11:6]
pblkspol3
pblktog1_3[5:0]
pblktog1_3[11:6]
pblktog2_3[5:0]
pblktog2_3[11:6]
pblkscp0
Sequence #0: Toggle Position 1 for PBLK
Sequence #0: Toggle Position 2 for PBLK
Sequence #1: Start Polarity for PBLK
Sequence #1: Toggle Position 1 for PBLK
Sequence #1: Toggle Position 2 for PBLK
Sequence #2: Start Polarity for PBLK
Sequence #2: Toggle Position 1 for PBLK
Sequence #2: Toggle Position 2 for PBLK
Sequence #3: Start Polarity for PBLK
Sequence #3: Toggle Position 1 for PBLK
Sequence #3: Toggle Position 2 for PBLK
PBLK Sequence-Change-Position #0 (Hardcoded to 0)
PBLK Sequence Pointer for SCP #0
PBLK Sequence-Change-Position #1
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
pblksptr0
pblkscp1[5:0]
pblkscp1[11:6]
pblksptr1
pblkscp2[5:0]
pblkscp2[11:6]
pblksptr2
pblkscp3[5:0]
pblkscp3[11:6]
pblksptr3
PBLK Sequence Pointer for SCP #1
PBLK Sequence-Change-Position #2
PBLK Sequence Pointer for SCP #2
PBLK Sequence-Change-Position #3
PBLK Sequence Pointer for SCP #3
H1–H4, RG, SHP, SHD # Bits 53
E5
E6
E7
E8
[0]
1
6
6
3
00
00
20
03
h1pol
H1/H2 Polarity Control (0 = No Inversion, 1 = Inversion)
H1 Positive Edge Location
H1 Negative Edge Location
H1 Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
H2 Drive Strength
H3 Drive Strength
H4 Drive Strength
RG Polarity Control (0 = No Inversion, 1 = Inversion)
RG Positive Edge Location
RG Negative Edge Location
[5:0]
[5:0]
[2:0]
h1posloc
h1negloc
h1drv
E9
[2:0]
[2:0]
[2:0]
[0]
[5:0]
[5:0]
[2:0]
3
3
3
1
6
6
3
03
03
03
00
00
10
02
h2drv
h3drv
h4drv
rgpol
rgposloc
rgnegloc
rgdrv
EA
EB
EC
ED
EE
EF
RG Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
SHP (Positive) Edge Sampling Location
SHD (Positive) Edge Sampling Location
F0
F1
[5:0]
[5:0]
6
6
24
00
shpposloc
shdposloc
–14–
REV. A
AD9847
Bit
Content
Default
Value
Address
Width
Register Name
Register Description
Serial Address:
AFE Register Breakdown
oprmode
[7:0]
8'h0
8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]}
[1:0]
2'h0
2'h1
2'h2
2'h3
powerdown[1:0]
Full Power
Fast Recovery
Reference Standby
Total Shutdown
[2]
[3]
[4]
[5]
[6]
[7]
disblack
Disable Black Loop Clamping (High Active)
Test Mode—Should Be Set Low
Test Mode—Should Be Set High
Test Mode—Should Be Set Low
Test Mode—Should Be Set Low
Test Mode—Should Be Set Low
test mode
test mode
test mode
test mode
test mode
ctlmode
[5:0]
6'h0
Serial Address: 8'h06 {cltmode[5:0]}
[2:0]
3'h0
3'h1
3'h2
3'h3
3'h4
3'h5
3'h6
3'h7
ctlmode[2:0]
Off
Mosaic Separate
VD Selected/Mosaic Interlaced
Mosaic Repeat
Three-Color
Three-Color II
Four-Color
Four-Color II
[3]
[4]
enablepxga
outputlat
Enable PxGA (High Active)
Latch Output Data on Selected DOUT Edge
Leave Output Latch Transparent
ADC Outputs Are Driven
ADC Outputs Are Three-Stated
1'h0
1'h1
1'h0
1'h1
[5]
tristateout
PRECISION TIMING HIGH SPEED TIMING
Timing Resolution
GENERATION
The Precision Timing core uses a 1ϫ master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel clock
frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Therefore, the edge resolution of the Precision Timing core is
(tCLI /48). For more information on using the CLI input, see the
Applications Information section.
The AD9847 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for generating
the timing used for both the CCD and the AFE, the reset gate RG,
horizontal drivers H1–H4, and the SHP/SHD sample clocks.
A unique architecture makes it routine for the system designer to
optimize image quality by providing precise control over the hori-
zontal CCD readout and the AFE correlated double sampling.
P[12]
P[24]
P[36]
POSITION
CLI
P[0]
P[48]=P[0]
...
tCLIDLY
...
1 PIXEL
PERIOD
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6 ns TYP).
Figure 4. High Speed Clock Resolution from CLI Master Clock Input
REV. A
–15–
AD9847
High Speed Clock Programmability
The edge location registers are 6 bits wide, but there are only 48
valid edge locations available. Therefore, the register values are
mapped into four quadrants, with each quadrant containing 12 edge
locations. Table III shows the correct register values for the
corresponding edge locations. Figure 6 shows the range and
default locations of the high speed clock signals.
Figure 5 shows how the high speed clocks RG, H1–H4, SHP,
and SHD are generated. The RG pulse has programmable rising
and falling edges and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising and
falling edges and polarity control. The H2 and H4 clocks are
always inverses of H1 and H3, respectively. Table II summarizes
the high speed timing registers and their parameters.
(3)
(4)
CCD SIGNAL
(1)
(5)
(2)
RG
(6)
H1/H3
H2/H4
NOTES
PROGRAMMABLE CLOCK POSITIONS:
(1) RG RISING EDGE AND (2) FALLING EDGE
(3) SHP AND (4) SHD SAMPLE LOCATION
(5) H1/H3 RISING EDGE POSITION AND (6) FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)
Figure 5. High Speed Clock Programmable Locations
Table II. H1–H4, RG, SHP, SHD Timing Parameters
Register Name
Length
Range
Description
POL
POSLOC
1b
6b
High/Low
0–47 Edge Location
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
Positive Edge Location for H1, H3, and RG
Sample Location for SHP, SHD
NEGLOC
DRV
6b
3b
0–47 Edge Location
0–7 Current Steps
Negative Edge Location for H1, H3, and RG
Drive Current for H1–H4 and RG Outputs (3.5 mA per Step)
Table III. Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
I
II
III
IV
0 to 11
0 to 11
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
12 to 23
24 to 35
36 to 47
16 to 27
32 to 43
48 to 59
–16–
REV. A
AD9847
P[48] = P[0]
P[0]
P[24]
P[36]
P[12]
POSITION
PIXEL
PERIOD
RGf[12]
RGr[0]
RG
Hf[24]
Hr[0]
H1/H3
SHP[28]
SHD[48]
tS1
CCD SIGNAL
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE.
Figure 6. High Speed Clock Default and Programmable Locations
H-Driver and RG Outputs
tRISE
In addition to the programmable timing positions, the AD9847
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver current can be adjusted for optimum rise/fall
time into a particular load by using the DRV registers. The RG
drive current is adjustable using the RGDRV register. Each 3-bit
DRV register is adjustable in 3.5 mA increments, with the mini-
mum setting of 0 equal to OFF or three-state and the maximum
setting of 7 equal to 24.5 mA.
H1/H3
H2/H4
tPD << tRISE
tPD
H1/H3
FIXED CROSSOVER VOLTAGE
H2/H4
Figure 7. H-Clock Inverse Phase Relationship
As shown in Figure 7, the H2/H4 outputs are inverses of H1/H3.
The internal propagation delay resulting from the signal inversion
is less than 1 ns, which is significantly less than the typical rise
time driving the CCD load. This results in a H1/H2 crossover
voltage at approximately 50% of the output swing. The crossover
voltage is not programmable.
Digital Data Outputs
The AD9847 data output phase is programmable using the
DOUTPHASE register. Any edge from 0 to 47 may be programmed,
as shown in Figure 8.
P[12]
P[0]
P[24]
P[48] = P[0]
P[36]
CLI
1 PIXEL PERIOD
tOD
DOUT
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
Figure 8. Digital Output Phase Adjustment
REV. A
–17–
AD9847
HORIZONTAL CLAMPING AND BLANKING
and second toggle positions of the pulse. All three signals are
active low and should be programmed accordingly. Up to four
individual sequences can be created for each signal.
The AD9847’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. As with the vertical
timing generation, individual sequences are defined for each
signal and are then organized into multiple regions during image
readout. This allows the dark pixel clamping and blanking patterns
to be changed at each stage of the readout, in order to accom-
modate different image transfer timing and high speed line shifts.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 10 is similar to
CLPOB, CLPDM, and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and the stop positions of the blanking period. Additionally, there
is a polarity control, HBLKMASK, that designates the polarity of
the horizontal clock signals H1–H4 during the blanking period.
Setting HBLKMASK high will set H1 = H3 = low and H2 =
H4 = high during the blanking, as shown in Figure 11. Up to
four individual sequences are available for HBLK.
Individual CLPOB, CLPDM, and PBLK Sequences
The AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure 9. These three signals are indepen-
dently programmed using the registers in Table IV. SPOL is the
start polarity for the signal, and TOG1 and TOG2 are the first
. . .
HD
(2)
(3)
. . .
CLPOB
CLPDM
PBLK
(1)
CLAMP
CLAMP
NOTES
PROGRAMMABLE SETTINGS:
(1) START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
(2) FIRST TOGGLE POSITION
(3) SECOND TOGGLE POSITION
Figure 9. Clamp and Preblank Pulse Placement
. . .
. . .
HD
(2)
(1)
BLANK
BLANK
HBLK
NOTES
PROGRAMMABLE SETTINGS:
(1) FIRST TOGGLE POSITION = START OF BLANKING
(2) SECOND TOGGLE POSITION = END OF BLANKING
Figure 10. Horizontal Blanking (HBLK) Pulse Placement
Table IV. CLPOB, CLPDM, PBLK Individual Sequence Parameters
Register Name
Length
Range
Description
SPOL
TOG1
TOG2
1b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Starting Polarity of Clamp and Blanking Pulses for Sequences 0–3
First Toggle Position within the Line for Sequences 0–3
Second Toggle Position within the Line for Sequences 0–3
Table V. HBLK Individual Sequence Parameters
Register Name
Length
Range
Description
HBLKMASK
HBLKTOG1
HBLKTOG2
1b
12b
12b
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)
First Toggle Position within the Line for Sequences 0–3
Second Toggle Position within the Line for Sequences 0–3
–18–
REV. A
AD9847
. . .
HD
. . .
HBLK
H1/H3
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1)
. . .
H1/H3
H2/H4
. . .
Figure 11. HBLK Masking Control
Horizontal Sequence Control
PBLK, and HBLK each have a separate set of SCP. For example,
CLPOBSCP1 will define Region 0 for CLPOB, and in that region
any of the four individual CLPOB sequences may be selected
with the CLPOBSPTR registers. The next SCP defines a new
region, and in that region each signal can be assigned to a different
individual sequence. The sequence control registers are summarized
in Table VI.
The AD9847 uses sequence change positions (SCP) and sequence
pointers (SPTR) to organize the individual horizontal sequences.
Up to four SCPs are available to divide the readout into four
separate regions, as shown in Figure 12. The SCP 0 is always
hard-coded to line 0, and SCP1–3 are register programmable.
During each region bounded by the SCP, the SPTR registers
designate which sequence is used by each signal. CLPOB, CLPDM,
SINGLE FIELD (1 VD INTERVAL)
SEQUENCE CHANGE OF POSITION #0
(V-COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 0
CLAMP AND PBLK SEQUENCE REGION 1
SEQUENCE CHANGE OF POSITION #1
SEQUENCE CHANGE OF POSITION #2
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 3
SEQUENCE CHANGE OF POSITION #3
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
Figure 12. Clamp and Blanking Sequence Flexibility
Table VI. Horizontal Sequence Control Parameters for CLPOB, CLPDM, PBLK, and HBLK
Register Name
Length
Range
Description
SCP1–SCP3
SPTR0–SPTR3
12b
2b
0–4095 Line Number
0–3 Sequence Number
CLAMP/BLANK SCP to Define Horizontal Regions 0–3
Sequence Pointer for Horizontal Regions 0–3
REV. A
–19–
AD9847
H-Counter Synchronization
circuitry by first writing “110101” or “53” decimal to the
INITIAL1 Register (Address x020). Finally, write “000100”
or “4” decimal to the INITIAL2 Register (Address x00F).
The H-Counter reset occurs on the sixth CLI rising edge following
the HD falling edge. The PxGA steering is synchronized with the
reset of the internal H-Counter (see Figure 13).
4. Write a “1” to the PREVENTUPDATE Register (Address x019).
This will prevent the updating of the serial register data.
POWER-UP PROCEDURE
Recommended Power-Up Sequence
When the AD9847 is powered up, the following sequence is
recommended (refer to Figure 14 for each step).
5. Write to the desired registers to configure high speed timing
and horizontal timing.
6. Write a “1” to the OUT_CONT Register (Address x016).
This will allow the outputs to become active after the next
VD/HD rising edge.
1. Turn on power supplies for AD9847.
2. Apply the master clock input CLI, VD, and HD.
7. Write a “0” to the PREVENTUPDATE Register (Address x019).
This will allow the serial information to be updated at the
next VD/HD falling edge.
3. The Precision Timing core must be reset by writing a “0” to the
TGCORE_RSTB Register (Address x026) followed by writ-
ing a “l” to the TGCORE_RSTB Register. This will start the
internal timing core operation. Next, initialize the internal
8. The next VD/HD falling edge allows register updates to occur,
including OUT_CONT, which enables all clock outputs.
VD
3ns MIN
HD
H-COUNTER
RESET
3ns MIN
CLI
H-COUNTER
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
2
0
3
1
4
0
5
1
6
0
7
1
8
0
9
1
10 11 12 14 15
0
2
1
3
2
2
3
3
5
3
4
2
(PIXEL COUNTER)
PxGA GAIN
REGISTER
X
0
1
0
1
0
NOTES
1. INTERNAL H-COUNTER IS RESET ON THE SIXTH CLI RISING EDGE FOLLOWING THE HD FALLING EDGE.
2. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
3. VD FALLING EDGE SHOULD OCCUR ONE CLOCK CYCLE BEFORE HD FALLING EDGE FOR PROPER PxGA LINE SYNCHRONIZATION.
Figure 13. H-Counter Synchronization
VDD
(INPUT)
CLI
(INPUT)
tPWR
SERIAL
WRITES
1V
***
***
***
***
VD
ODD FIELD
1 H
EVEN FIELD
(OUTPUT)
HD
(OUTPUT)
H2/H4
DIGITAL
OUTPUTS
H1/H3, RG
CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS
UPDATED AT VD/HD EDGE
Figure 14. Recommended Power-Up Sequences
–20–
REV. A
AD9847
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9847 signal processing chain is shown in Figure 15.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data.
Another advantage of removing this offset at the input stage is to
maximize system headroom. Some area CCDs have large black
level offset voltages, which, if not corrected at the input stage, can
significantly reduce the available headroom in the internal circuitry
when higher VGA gain settings are used.
DC Restore
To reduce the large dc offset of the CCD output signal, a
dc-restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to approxi-
mately 1.5 V, to be compatible with the 3 V analog supply of the
AD9847.
Horizontal timing examples are shown on the last page of the
Applications Information section. It is recommended that the
CLPDM pulse be used during valid CCD dark pixels. CLPDM
may be used during the optical black pixels, either together with
CLPOB or separately. The CLPDM pulse should be a minimum
of four pixels wide.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the video
information and reject low frequency noise. The timing shown
in Figure 6 illustrates how the two internally generated CDS
clocks, SHP and SHD, are used to sample the reference level and
data level of the CCD signal, respectively. The placement of the
SHP and SHD sampling edges is determined by the setting of
the SHPPOSLOC and SHDPOSLOC registers located at
Addresses 0xF0 and 0xF1, respectively. Placement of these two
clock signals is critical in achieving the best performance from
the CCD.
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to “multiplex” its gain value
on a pixel-to-pixel basis (see Figure 17). This allows lower out-
put color pixels to be gained up to match higher output color
pixels. Also, the PxGA may be used to adjust the colors for white
balance, reducing the amount of digital processing that is needed.
The four different gain values are switched according to the
Color Steering circuitry. Seven different color steering modes
for different types of CCD color filter arrays are programmed
in the AD9847 AFE Register, ctlmode, at Address 0x06
(see Figures 16a to 16g for timing examples). For example,
Mosaic Separate steering mode accommodates the popular
“Bayer” arrangement of red, green, and blue filters (see Figure 18).
Input Clamp
A line-rate input clamping circuit is used to remove the CCD’s
optical black offset. This offset exists in the CCD’s shielded black
reference pixels. The AD9847 removes this offset in the input
stage to minimize the effect of a gain change on the system black
level, usually called the “gain step.”
0.1F
1.0F 1.0F
CML
REFB REFT
1.0V
2.0V
AVDD
2
DC RESTORE
1.5V
INTERNAL
BIASING
AD9847
INTERNAL
V
REF
DOUT
PHASE
SHP
SHD
2V FULL SCALE
–2dB TO +10dB
0dB TO 36dB
0.1F
OUTPUT
DATA
LATCH
10
CCDIN
10-BIT
ADC
VGA
DOUT
CDS
PxGA
10
CLPDM
OPTICAL BLACK
CLAMP
8-BIT
DAC
VGA GAIN
REGISTER
INPUT OFFSET
CLAMP
PBLK
CLPOB
8
0.1F
DIGITAL
BYP1
BYP 2
BYP 3
FILTER
0.1F
0.1F
CLAMP LEVEL
REGISTER
DOUT
PHASE
CLPDM
SHD
CLPOB PBLK
SHP
PRECISION
TIMING
GENERATION
V-H
TIMING
GENERATION
Figure 15. Analog Front End Block Diagram
REV. A
–21–
AD9847
ODD FIELD
EVEN FIELD
FLD
VD
HD
PxGA GAIN
REGISTER
0
0
X
X
1
0
1
1
0
1
2
3
2
3
0
1
0
1
2
3
2
3
0
1
0
1
0
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “0101” AND “2323” LINES.
3. FLD STATUS IS IGNORED.
Figure 16a. Mosaic Separate Mode
ODD FIELD
EVEN FIELD
FLD
VD
HD
PxGA GAIN
REGISTER
0
2
X
X
1
0
1
3
2
3
0
1
0
1
0
1
0
1
2
3
2
3
2
3
2
3
0
NOTES
1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.
2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “2323“ LINE.
3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER “0” (FLD = ODD) OR “2” (FLD = EVEN).
Figure 16b. Mosaic Interlaced Mode
ODD FIELD
EVEN FIELD
FLD
VD
HD
PxGA GAIN
REGISTER
X
X
1
0
1
1
0
1
0
0
1
2
1
2
0
1
0
1
1
2
1
2
0
1
0
1
0
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “0101” AND “1212” LINES.
3. ALL FIELDS WILL HAVE THE SAME PxGA GAIN STEERING PATTERN (FLD STATUS IS IGNORED).
Figure 16c. Mosaic Repeat Mode
ODD FIELD
EVEN FIELD
FLD
VD
HD
PxGA GAIN
REGISTER
0
0
X
X
1
2
0
1
2
0
0
1
2
0
0
1
2
0
0
1
2
0
0
1
2
0
0
NOTES
1. EACH LINE FOLLOWS “012012” STEERING PATTERN.
2. VD AND HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO “0.”
3. FLD STATUS IS IGNORED.
Figure 16d. Three-Color Mode
–22–
REV. A
AD9847
ODD FIELD
EVEN FIELD
FLD
VD
HD
PxGA GAIN
REGISTER
0
0
X
X
1
2
0
1
2
0
2
1
0
2
0
1
2
0
2
1
0
2
0
1
2
0
0
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “012012” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER, STEERING BETWEEN “012012” AND “210210” LINES.
3. FLD STATUS IS IGNORED.
Figure 16e. Three-Color Mode II
ODD FIELD
EVEN FIELD
FLD
VD
HD
PxGA GAIN
REGISTER
0
0
X
X
1
2
3
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
0
NOTES
1. EACH LINE FOLLOWS “01230123” STEERING PATTERN.
2. VD AND HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO GAIN REGISTER “0.”
3. FLD STATUS IS IGNORED.
Figure 16f. Four-Color Mode
ODD FIELD
FLD
EVEN FIELD
VD
HD
PxGA GAIN
REGISTER
0
0
X
X
1
2
3
1
2
3
2
3
0
1
0
1
2
3
2
3
0
1
0
1
2
3
0
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “01230123” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “01230123” AND “23012301” LINES.
3. FLD STATUS IS IGNORED.
Figure 16g. Four-Color Mode II
REV. A
–23–
AD9847
10
8
VD
CONTROL
REGISTER
BITS D0–D2
PxGA STEERING
MODE
SELECTION
COLOR
STEERING
CONTROL
3
HD
SHP/SHD
2
GAIN0
6
GAIN1
GAIN2
GAIN3
PxGA GAIN
REGISTERS
4:1
MUX
4
6
2
PxGA
VGA
CDS
0
Figure 17. PxGA Block Diagram
–2
32
40
48
58
0
8
16
24
31
(100000)
(011111)
CCD: PROGRESSIVE BAYER
MOSAIC SEPARATE COLOR
STEERING MODE
PxGA GAIN REGISTER CODE
Figure 19. PxGA Gain Curve
Variable Gain Amplifier
R
Gb
R
Gr
B
R
Gb
R
Gr
B
LINE0
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1...
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN0, GAIN1, GAIN0, GAIN1...
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with 4 dB from the PxGA stage, the total gain range
for the AD9847 is 6 dB to 40 dB. The minimum gain of 6 dB is
needed to match a 1 V input signal with the ADC full-scale
range of 2 V. When compared to 1 V full-scale systems (such as
ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB.
Gr
B
Gr
B
Gb
Gb
Figure 18a. CCD Color Filter Example: Progressive Scan
The VGA gain curve is divided into two separate regions. When
the VGA gain register code is between 0 and 511, the curve follows
a (1 + x)/(1 – x) shape, which is similar to a linear-in-dB character-
istic. From code 512 to code 1023, the curve follows a linear-in-dB
shape. The exact VGA gain can be calculated for any gain register
value by using the following two equations:
CCD: INTERLACED BAYER
EVEN FIELD
VD SELECTED COLOR
STEERING MODE
R
R
R
R
Gr
Gr
Gr
Gr
R
R
R
R
Gr
Gr
Gr
Gr
LINE0
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1...
GAIN0, GAIN1, GAIN0, GAIN1...
GAIN0, GAIN1, GAIN0, GAIN1...
Code Range Gain Equation (dB)
0–511
512–1023
Gain = 20 log10 ([658 ϩ code] / [658 – code]) – 0.4
Gain = (0.0354)(code) – 0.04
ODD FIELD
36
30
24
18
12
6
Gb
Gb
Gb
Gb
B
B
B
B
Gb
Gb
Gb
Gb
B
B
B
B
LINE0
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN2, GAIN3, GAIN2, GAIN3...
GAIN2, GAIN3, GAIN2, GAIN3...
Figure 18b. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD selected
mode should be used with this type of CCD (see Figure 18b).
The color steering performs the proper multiplexing of the R, G,
and B gain values (loaded into the PxGA gain registers) and is
synchronized by the user with vertical (VD) and horizontal (HD)
sync pulses. For more detailed information, see the PxGA Timing
section. The PxGA gain for each of the four channels varies from
–2 dB to +10 dB, controlled in 64 steps through the serial inter-
face. The PxGA gain curve is shown in Figure 19.
0
0
127
255
383
511
639
767
895
1023
VGA GAIN REGISTER CODE
Figure 20. VGA Gain Curve (Gain from PxGA Not Included)
–24–
REV. A
AD9847
Optical Black Clamp
APPLICATIONS INFORMATION
External Circuit Configuration
The optical black clamp loop is used to remove residual offsets in
the signal chain and to track low frequency variations in the CCD’s
black level. During the optical black (shielded) pixel interval on
each line, the ADC output is compared with a fixed black level
reference, selected by the user in the clamp level register. The
value can be programmed between 0 LSB and 63.75 LSB with
8-bit resolution. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the post processing, the AD9847 optical black
clamping may be disabled using Bit D2 in the OPRMODE
register. When the loop is disabled, the clamp level register may
still be used to provide programmable offset adjustment.
The AD9847 recommended circuit configuration for external
mode is shown in Figure 21. All signals should be carefully
routed on the PCB to maintain low noise performance. The CCD
output signal should be connected to Pin 29 through a 0.1 µF
capacitor. The CCD timing signals H1–H4 and RG should be
routed directly to the CCD with minimum trace lengths, as shown
in Figures 22a and 22b. The digital outputs and clock inputs are
located on Pins 1–12 and Pins 36–44 and should be connected
to the digital ASIC, away from the analog and CCD clock signals.
The CLI signal from the ASIC may be routed under the package
to Pin 23. This will help separate the CLI signal from the H1–H4
and RG signal routing.
Grounding and Decoupling Recommendations
As shown in Figure 21, a single ground plane is recommended
for the AD9847. This ground plane should be as continuous as
possible, particularly around Pins 25 – 35. This will ensure that
all analog decoupling capacitors provide the lowest possible
impedance path between the power and bypass pins and their
respective ground pins. All decoupling capacitors should be located
as close as possible to the package pins. Placing series resistors
close to the digital output pins (Pins 1–12) may help reduce
digital code transition noise. If the digital outputs must drive a
load larger than 20 pF, buffering is recommended to minimize
additional noise.
The CLPOB pulse should be placed during the CCD’s optical
black pixels. It is recommended that the CLPOB pulse duration
be at least 20 pixels wide to minimize clamp noise. Shorter pulse-
widths may be used, but clamp noise may increase, and the
ability to track low frequency variations in the black level will be
reduced. See the section on Horizontal Clamping and Blanking
and also the Applications Information section for timing examples.
A/D Converter
The AD9847 uses a high performance 10-bit ADC architecture,
optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.4 LSB. The ADC
uses a 2 V input range. Better noise performance results from
using a larger ADC full-scale range. See TPC 1 and TPC 2 for
typical linearity and noise performance plots for the AD9847.
Power supply decoupling is very important in achieving low noise
performance. Figure 21 shows the local high frequency decoupling
capacitors, but additional capacitance is recommended for lower
frequencies. Additional capacitors and ferrite beads can further
reduce noise.
0.1ꢂF
CLOCK
6
3V
DIGITAL
SUPPLY
INPUTS
SERIAL
3
INTERFACE
1ꢂF
48 47 46 45 44 43 42 41 40 39 38 37
SL
(LSB) D0
1
1ꢂF
36
35
34
33
32
31
30
29
28
27
26
25
D1
PIN 1
IDENTIFIER
REFT
2
3
D2
REFB
CMLEVEL
AVSS3
AVDD3
BYP3
0.1ꢂF
D3
4
0.1ꢂF
D4
DVSS3
3V
0.1ꢂF
5
3V
DRIVER
SUPPLY
ANALOG
SUPPLY
AD9847
TOP VIEW
(Not to Scale)
6
DVDD3
D5
7
CCDIN
BYP2
CCD
8
D6
SIGNAL
9
0.1ꢂF
D7
BYP1
10
11
12
3V
ANALOG
SUPPLY
D8
AVDD2
AVSS2
(MSB) D9
0.1ꢂF
10
DATA
OUTPUTS
13 14 15 16 17 18 19 20 21 22 23 24
0.1ꢂF 0.1ꢂF
0.1ꢂF
H DRIVER
SUPPLY
CLOCK
INPUT
3V
ANALOG
RG DRIVER
SUPPLY
SUPPLY
0.1ꢂF
0.1ꢂF
0.1ꢂF
5
HIGH-SPEED
CLOCKS
Figure 21. Recommended Circuit Configuration for External Mode
–25–
REV. A
AD9847
CCDIN
29
AD9847
AD9847
ASIC
LPF
17
18
H4
13
H1
14
H2
20
23
H3
RG
CLI
1nF
MASTER
CLOCK
SIGNAL
OUT
Figure 23b. CLI Connection, AC-Coupled
Internal Mode Circuit Configuration
H2
H1
RG
CCD IMAGER
The AD9847 may be used in internal mode using the circuit
configuration of Figure 24. Internal mode uses the same circuit as
Figure 21, except that the horizontal pulses (CLPOB, CLPDM,
PBLK, and HBLK) are internally generated in the AD9847.
These pins may be grounded when internal mode is used. Only
the HD and VD signals are required from the ASIC.
Figure 22a. CCD Connections (2 H-Clock)
CCDIN
29
AD9847
2
HD/VD
INPUTS
13
H1
14
H2
17
H3
18
H4
20
RG
SIGNAL
OUT
42
40
44 43
41
39
H1
H2
RG
CCD IMAGER
AD9847
H2
H1
Figure 24. Internal Mode Circuit Configuration
Figure 22b. CCD Connections (4 H-Clock)
Driving the CLI Input
The AD9847’s master clock input (CLI) may be used in two
different configurations, depending on the application. Figure 23a
shows a typical dc-coupled input from the master clock source.
When the dc-coupled technique is used, the master clock signal
should be at standard 3 V CMOS logic levels. As shown in
Figure 23b, a 1000 pF ac-coupling capacitor may be used between
the clock source and the CLI input. In this configuration, the CLI
input will self-bias to the proper dc voltage level of approximately
1.4 V. When the ac-coupled technique is used, the master clock
signal can be as low as 500 mV in amplitude.
TIMING EXAMPLES FOR DIFFERENT SEQUENCES
2
SEQUENCE 2
V
SEQUENCE 3
10
SEQUENCE 2
AD9847
H
48
4
ASIC
23
CLI
28
MASTER
CLOCK
Figure 25. Typical CCD
Figure 23a. CLI Connection, DC-Coupled
–26–
REV. A
AD9847
Timing Examples (continued)
DUMMY
CCDIN
INVALID PIXELS
VERT SHIFT
INVALID PIXELS
VERT SHIFT
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
CLPDM
Figure 26. Sequence 1: Vertical Blanking
EFF. PIXELS
OPTICAL BLACK
OPTICAL BLACK
VERT SHIFT DUMMY
CCDIN
SHP
VERT SHIFT
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
CLPDM
Figure 27. Sequence 2: Vertical Optical Black
EFF. PIXELS
OPTICAL BLACK
DUMMY OB
OPTICAL BLACK
VERT SHIFT
EFFECTIVE PIXELS
CCDIN
VERT SHIFT
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
CLPDM
Figure 28. Sequence 3: Effective Pixels
REV. A
–27–
AD9847
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
0.20
0.09
7.00
BSC
TOP VIEW
(PINS DOWN)
VIEW A
7ꢃ
3.5ꢃ
0ꢃ
0.15
0.05
25
12
SEATING
PLANE
24
0.08 MAX
13
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90ꢃ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Revision History
Location
Page
1/03—Data Sheet changed from REV. 0 to REV. A.
Change to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Change to Register Description Table – HBLK # Bits 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to Recommended Power Sequence section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
–28–
REV. A
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