AD9851BRSZ [ADI]
CMOS 180 MHz DDS/DAC Synthesizer; CMOS 180 MHz的DDS / DAC频率合成器
| 型号： | AD9851BRSZ |
| 厂家： | 
ADI |
| 描述： | CMOS 180 MHz DDS/DAC Synthesizer |
| 文件： | 总24页 (文件大小：749K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDS/DAC Synthesizer
Multiplier
GND
+V
S
On-Chip High Performance 10-Bit DAC and High Speed
Comparator with Hysteresis
OUT
32-Bit FrequencyTuningWord
Simplifi ed Control Interface: Parallel or Serial
Asynchronous Loading Format
5-Bit Phase Modulation and Offset Capability
Comparator Jitter <80 ps p-p @ 20 MHz
2.7V to 5.25V Single-Supply Operation
Power-Down Function, 4 mW @ 2.7 V
Ultrasmall 28-Lead SSOP Packaging
AD9851
DAC R
SET
REF
6 REFCLK
CLOCK IN
MULTIPLIER
10-BIT
DAC
ANALOG
OUT
HIGH SPEED
DDS
MASTER
RESET
PHASE
AND
CONTROL
WORDS
32-BIT
TUNING
WORD
ANALOG
IN
FREQUENCY
UPDATE/DATA
REGISTER
FREQUENCY/PHASE
DATA REGISTER
CLOCK OUT
RESET
WORD LOAD
CLOCK
CLOCK OUT
DATA INPUT REGISTER
SERIAL
LOAD
COMPARATOR
PARALLEL
LOAD
1 BIT
40 LOADS
8 BITS
5 LOADS
Frequency/Phase-Agile SineWave Synthesis
Clock Recovery and Locking Circuitry for Digital
FREQUENCY, PHASE
AND CONTROL DATA INPUT
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications in Communications
CW, AM, FM, FSK, MSK ModeTransmitter
The AD9851 contains an internal high speed comparator that
can be configured to accept the (externally) filtered output of the
DAC to generate a low jitter output pulse.
The AD9851 is a highly integrated device that uses advanced
DDS technology, coupled with an internal high speed, high
performance D/A converter, and comparator, to form a digitally
programmable frequency synthesizer and clock generator func-
tion. When referenced to an accurate clock source, the AD9851
generates a stable frequency and phase-programmable digitized
analog output sine wave. This sine wave can be used directly as
a frequency source, or internally converted to a square wave for
agile-clock generator applications. The AD9851’s innovative
high speed DDS core accepts a 32-bit frequency tuning word,
which results in an output tuning resolution of approximately
0.04 Hz with a 180 MHz system clock. The AD9851 contains
a unique 6REFCLK Multiplier circuit that eliminates the
need for a high speed reference oscillator. The 6
Multiplier has minimal impact on SFDR and phase noise char-
acteristics. The AD9851 provides five bits of programmable
phase modulation resolution to enable phase shifting of its
output in increments of 11.25°.
The frequency tuning, control, and phase modulation words are
asynchronously loaded into the AD9851 via a parallel or serial
loading format. The parallel load format consists of five iterative
loads of an 8-bit control word (byte). The first 8-bit byte controls
output phase, 6REFCLK Multiplier, power-down enable and
loading format; the remaining bytes comprise the 32-bit frequency
tuning word. Serial loading is accomplished via a 40-bit serial data
stream entering through one of the parallel input bus lines. The
AD9851 uses advanced CMOS technology to provide this break-
through level of functionality on just 555 mW of power dissipation
(5 V supply), at the maximum clock rate of 180 MHz.
The AD9851 is available in a space-saving 28-lead SSOP,
surface-mount package that is pin-for-pin compatible with the
popular AD9850 125 MHz DDS. It is specified to operate over
the extended industrial temperature range of –40°C to +85°C
at >3.0 V supply voltage. Below 3.0 V, the specifications apply
over the commercial temperature range of 0°C to 85°C.
REV.D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
1
(VS 5%, RSET , 6REFCLK Multiplier Disabled, External Reference
Clock = 180 MHz, except as noted.)
Typ
Temp
CLOCK INPUT CHARACTERISTICS
Frequency Range (6
REFCLK Multiplier Disabled)
5.0 V Supply
3.3 V Supply
2.7 V Supply
Full
IV
1
125
MHz
Frequency Range (6
5.0 V Supply
3.3 V Supply
2.7 V Supply
Duty Cycle
REFCLK Multiplier Enabled)
Full
0°C to 85°C
IV
IV
V
5
5
30
MHz
MHz
M
16.66
Duty Cycle (6
REFCLK Multiplier Enabled)
Input Resistance
25°C
1
Minimum SwitchingThresholds2
Logic 1, 5.0 V Supply
25°C
25°C
IV
IV
3.5
V
V
Logic 1, 3.3 V Supply
Logic 0, 5.0 V Supply
Logic 0, 3.3 V Supply
1.5
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
25°C
25°C
I
I
–10
+10
0.75
% FS
µA
LSB
Integral Nonlinearity
Residual Phase Noise, 5.2 MHz, 1 kHz Offset
PLL Off
25°C
25°C
V
I
–132
dBc/Hz
Output Impedance
Voltage Compliance Range
Wideband Spurious-Free Dynamic Range
1.1 MHz Analog Out (DC to 72 MHz)
20.1 MHz Analog Out (DC to 72 MHz)
40.1 MHz Analog Out (DC to 72 MHz)
50.1 MHz Analog Out (DC to 72 MHz)
70.1 MHz Analog Out (DC to 72 MHz)
Narrowband Spurious-Free Dynamic Range
1.1 MHz (±50 kHz)
–0.5
+1.5
V
25°C
25°C
25°C
IV
IV
IV
60
51
42
64
55
43
dBc
dBc
dBc
25°C
25°C
25°C
V
V
V
85
85
85
dBc
dBc
dBc
1.1 MHz (±200 kHz)
40.1 MHz (±50 kHz)
40.1 MHz (±200 kHz)
70.1 MHz (±50 kHz)
70.1 MHz (±200 kHz)
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Bias Current
InputVoltage Range
25°C
25°C
IV
500
pF
k
µA
V
IV
0
5
Logic 1Voltage 5V Supply
Logic 1Voltage 3.3V Supply
Logic 1Voltage 2.7V Supply
Logic 0Voltage
Continuous Output Current
Hysteresis
Propagation Delay
25°C
25°C
25°C
25°C
25°C
VI
VI
IV
IV
IV
4.8
2.3
V
V
mA
ns
ns
20
7
7
Toggle Frequency (1V p-p Input SineWave)
Rise/FallTime, 15 pF Output Load
Output Jitter (p-p)3
ps (p-p)
CLOCK OUTPUT CHARACTERISTICS
Output Jitter (Clock Generator Configuration,
40 MHz 1V p-p Input SineWave)
25°C
Full
V
IV
250
50 ± 10
ps (p-p)
%
Clock Output Duty Cycle
REV. D
Typ
Temp
4
tWH, tWL (W_CLK Min PulseWidth High/Low)
DS, tDH (Data toW_CLK Setup and HoldTimes)
tFH, tFL (FQ_UD Min PulseWidth High/Low)
CD (REFCLK Delay After FQ_UD)5
tFD (FQ_UD Min Delay AfterW_CLK)
CF (Output Latency from FQ_UD)
Frequency Change
Full
Full
Full
IV
IV
IV
3.5
7
7
ns
ns
ns
Full
Full
IV
IV
18
13
SYSCLK
Cycles
SYSCLK
Cycles
ns
Phase Change
tRH (CLKIN Delay After RESET Rising Edge)
RL (RESET Falling Edge After CLKIN)
tRR (Recovery from RESET)
Full
Full
IV
IV
3.5
2
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
µs
tRS (Minimum RESETWidth)
Full
Full
25°C
IV
IV
V
5
tOL (RESET Output Latency)
13
Wake-UpTime from Power-Down Mode6
5
Logic 1Voltage, 5V Supply
Logic 1Voltage, 3.3V Supply
Logic 1Voltage, 2.7V Supply
Logic 0Voltage
Logic 1 Current
Logic 0 Current
Rise/FallTime
Input Capacitance
25°C
25°C
25°C
25°C
I
3.5
2.0
V
V
µA
µA
ns
pF
IV
I
IV
12
100
POWER SUPPLY
S6 Current @:
62.5 MHz Clock, 2.7V Supply
100 MHz Clock, 2.7V Supply
62.5 MHz Clock, 3.3V Supply
125 MHz Clock, 3.3V Supply
62.5 MHz Clock, 5V Supply
125 MHz Clock, 5V Supply
180 MHz Clock, 5V Supply
Power Dissipation @ :
25°C
25°C
25°C
25°C
VI
VI
VI
VI
30
35
50
110
35
45
65
130
mA
mA
mA
mA
62.5 MHz Clock, 5V Supply
62.5 MHz Clock, 3.3V Supply
62.5 MHz Clock, 2.7V Supply
100 MHz Clock, 2.7V Supply
125 MHz Clock, 5V Supply
125 MHz Clock, 3.3V Supply
180 MHz Clock, 5V Supply
DISS Power-Down Mode @:
5V Supply
25°C
25°C
25°C
25°C
VI
VI
VI
VI
250
85
365
555
325
95
450
650
mW
mW
mW
mW
25°C
25°C
VI
VI
17
4
55
20
mW
mW
2.7V Supply
NOTES
1+VS collectively refers to the positive voltages applied to DVDD, PVCC, and AVDD.Voltages applied to these pins should be of the same potential.
2Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages.This specifies the p-p signal level and dc offset needed when the
clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0V dc offset.
3The comparator’s jitter contribution to any input signal.This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more output
jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic signals (spur’s,
noise), slower slew rate, and low comparator overdrive.
4Timing of input signals FQ_UD,WCLK, RESET are asynchronous to the reference clock; however, the presence of a reference clock is required to implement those
functions. In the absence of a reference clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable until a refer-
ence clock is restored.Very high speed updates of frequency/phase word will require FQ_UD andWCLK to be externally synchronized with the external reference clock to
ensure proper timing.
5Not applicable when 6REFCLK Multiplier is engaged.
6Assumes no capacitive load on DACBP (Pin 17).
Specifications subject to change without notice.
Maximum JunctionTemperature
StorageTe
S
OperatingTe
Digital Inputs S
LeadTemperature (10 sec) Soldering
JA Thermal Impedance
DAC Output Current
– 100% ProductionTested.
III – SampleTested Only.
IV – Parameter is guaranteed by design and characterization
testing.
Parameter is a typical value only.
VI – Devices are 100% production tested at 25°C and guaran-
teed by design and characterization testing for industrial
operating temperature range.
Absolutemaximumratingsarelimitingvalues,tobeappliedindividually,andbeyond
which the serviceability of the circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied. Exposure of absolute maximum
rating conditions for extended periods of time may affect device reliability.
Temperature Range
Package Description
Package Option
Shrink Small Outline (SSOP)
Shrink Small Outline (SSOP)
Evaluation Board Frequency Synthesizer
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9851 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Application Note: Users are cautioned not to apply digital input signals prior to power-up of this device.
Doing so may result in a latch-up condition.
REV. D
1
2
28
27
26
25
24
D3
D2
D4
D5
3
D1
D6
4
LSB D0
PGND
D7 MSB/SERIAL LOAD
DGND
5
6
23 DVDD
PVCC
AD9851
TOP VIEW
(Not to Scale)
7
22
21
W CLK
FQ UD
REFCLOCK
AGND
AVDD
RESET
IOUT
8
9
20 IOUTB
10
11
12
13
14
19
18
17
16
15
AGND
AVDD
DACBP
VINP
R
SET
VOUTN
VOUTP
VINN
4–1,
8-Bit Data Input.The data port for loading the 32-bit frequency and 8-bit phase/control words. D7 = MSB;
D0 = LSB. D7, Pin 25, also serves as the input pin for 40-bit serial data word.
REFCLK Multiplier Ground Connection.
REFCLK Multiplier Positive SupplyVoltage Pin.
Word Load Clock. Rising edge loads the parallel or serial frequency/phase/control words asynchronously
into the 40-bit input register.
W_CLK
FQ_UD
Frequency Update. A rising edge asynchronously transfers the contents of the 40-bit input register to be
acted upon by the DDS core. FQ_UD should be issued when the contents of the input register are known
to contain only valid, allowable data.
Reference Clock Input. CMOS/TTL-level pulse train, direct or via the 6REFCLK Multiplier. In direct
mode, this is also the SYSTEM CLOCK. If the 6REFCLK Multiplier is engaged, then the output of the
multiplier is the SYSTEM CLOCK.The rising edge of the SYSTEM CLOCK initiates operations.
Analog Ground.The ground return for the analog circuitry (DAC and Comparator).
Positive supply voltage for analog circuitry (DAC and Comparator, Pin 18) and bandgap voltage reference,
10, 19
11, 18
SET
SET connection—nominally a 3.92 kresistor to ground for 10 mA out.This sets
the DAC full-scale output current available from IOUT and IOUTB. RSET
Voltage Output Negative.The comparator’s complementary CMOS logic level output.
Voltage Output Positive.The comparator’s true CMOS logic level output.
Voltage Input Negative.The comparator’s inverting input.
Voltage Input Positive.The comparator’s noninverting input.
DAC Bypass Connection.This is the DAC voltage reference bypass connection normally NC (NO
CONNECT) for optimum SFDR performance.
The complementary DAC output with same characteristics as IOUT except that IOUTB = (full-scale
output–IOUT). Output load should equal that of IOUT for best SFDR performance.
The true output of the balanced DAC. Current is sourcing and requires current-to-voltage
conversion, usually a resistor or transformer referenced to GND. IOUT = (full-scale output–IOUTB).
Master Reset pin; active high; clears DDS accumulator and phase offset register to achieve 0 Hz and 0°
output phase. Sets programming to parallel mode and disengages the 6REFCLK Multiplier. Reset does
not clear the 40-bit input register. On power-up, asserting RESET should be the first priority before pro-
gramming commences.
Positive supply voltage pin for digital circuitry.
Digital Ground.The ground return pin for the digital circuitry.
REV. D
AD9851–Typical Performance Characteristics
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
RBW = 5kHz
VBW = 5kHz
SWT = 7.2s
RF ATT = 20dB
REF LVL = –7dBm
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2AP
2AP
1.1MHz
CENTER
20kHz/
200kHz
SPAN
0Hz
START
7.2MHz/
72MHz
STOP
TPC 4. Narrowband (1.1 ± 0.1 MHz) output SFDR
for a 1.1 MHz fundamental output signal. System
TPC 1. Wideband (dc to 72 MHz) output SFDR for
a 1.1 MHz fundamental output signal. System
clock =180 MHz (6
S = 5 V.
REFCLK multiplier engaged),
clock = 180 MHz (6
S = 5 V.
REFCLK multiplier engaged),
0
0
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
RBW = 5kHz
VBW = 5kHz
SWT = 7.2s
RF ATT = 20dB
REF LVL = –7dBm
–10
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–20
–30
–40
–50
–60
–70
–80
–90
–100
2AP
2AP
40.1MHz
CENTER
20kHz/
200kHz
SPAN
0Hz
START
7.2MHz/
72MHz
STOP
TPC 2. Wideband (dc to 72 MHz) output SFDR for
a 40.1 MHz fundamental output signal. System
TPC 5. Narrowband (40.1 ± 0.1 MHz) output SFDR
for a 40.1 MHz fundamental output signal. System
clock = 180 MHz (6
VS = 5 V.
REFCLK multiplier engaged),
clock = 180 MHz (6
VS = 5 V.
REFCLK multiplier engaged),
0
0
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
RBW = 5kHz
VBW = 5kHz
SWT = 7.2s
RF ATT = 20dB
REF LVL = –7dBm
–10
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–20
–30
–40
–50
–60
–70
–80
–90
–100
2AP
2AP
70.1MHz
CENTER
20kHz/
200kHz
SPAN
0Hz
7.2MHz/
72MHz
STOP
START
TPC 6. Narrowband (70.1 ± 0.1 MHz) output SFDR
for a 70.1 MHz fundamental output signal. System
TPC 3. Wideband (dc to 72 MHz) output SFDR for
a 70.1 MHz fundamental output signal. System
clock = 180 MHz (6
S = 5 V.
REFCLK multiplier engaged),
clock = 180 MHz (6
VS = 5 V.
REFCLK multiplier engaged),
REV. D
Tek Run 4.00GS/s
Sample
T
Tek Run 4.00GS/s
Sample
T
[
]
[
]
: 208ps
: 280ps
@ : 1.940ns
@ : 2.668ns
1
1
M 12.5ns Ch 1
D 200ps Runs After
–200mV
M 12.5ns Ch 1
D 200ps Runs After
–200mV
Ch1 200mV
Ch1 200mV
TPC 7. Typical CMOS comparator p-p output jitter with
TPC 9. Typical CMOS comparator p-p output
jitter with the AD9851 configured as a clock
generator, DDS fOUT = 70.1 MHz, VS = 5 V, system
clock = 180 MHz, 70 MHz LPF. Graph details
the center portion of a rising edge with scope
in delayed trigger mode, 200 ps/div. Cursors
show 280 ps p-p jitter.
the AD9851 configured as a clock generator, DDS fOUT
10.1 MHz, VS = 5 V, system clock = 180 MHz, 70 MHz LPF.
Graph details the center portion of a rising edge with
scope in delayed trigger mode, 200 ps/div. Cursors show
208 ps p-p jitter.
Tek Run 4.00GS/s
Sample
T
[
]
–100
AD9851 PHASE NOISE
: 204ps
@ : 3.672ns
–115
–120
–125
–130
–135
–140
–145
1
100
1k
10k
100k
M 12.5ns Ch 1
D 200ps Runs After
–200mV
Ch1 200mV
FREQUENCY OFFSET – Hz
TPC 8. Typical CMOS comparator p-p output jitter with the
AD9851 configured as a clock generator, DDS fOUT = 40.1 MHz,
S = 5 V, system clock = 180 MHz, 70 MHz LPF. Graph details
the center portion of a rising edge with scope in delayed
trigger mode, 200 ps/div. Cursors show 204 ps p-p jitter.
TPC 10. Output Phase Noise (5.2 MHz AOUT), 6
Multiplier Enabled, System Clock = 180 MHz, Reference
Clock = 30 MHz
REFCLK
REV. D
Tek Stop 2.50GS/s
2227 Acgs
T
[
]
–120
–125
–130
–135
–140
–145
–150
AD9851 RESIDUAL PHASE NOISE
: 2.3ns
@ : 103.6ns
C1 Fall
2.33ns
1
–155
100
1k
10k
100k
M 20.0ns Ch 1
D 5.00ns Runs After
252mV
Ch1 100mV
FREQUENCY OFFSET – Hz
TPC 14. Comparator FallTime, 15 pF Load
TPC 11. Output Residual Phase Noise (5.2 MHz AOUT), 6
REFCLK Multiplier Disabled, System Clock = 180 MHz, Ref-
erence Clock = 180 MHz
120
75
110
100
90
FUNDAMENTAL OUTPUT =
SYSTEM CLOCK/3
70
V
= +5V
S
65
80
V
= +3.3V
60
55
S
70
60
V
= +3.3V
V
= +5V
S
S
50
50
45
40
30
0
10
20
30
40
50
60
70
10
20
40
60
80 100 120 140 160 180
ANALOG OUTPUT FREQUENCY – MHz
SYSTEM CLOCK FREQUENCY – MHz
TPC 12. Spurious-free dynamic range (SFDR) is generally
a function of the DAC analog output frequency. Analog
output frequencies of 1/3 the system clock rate are consid-
ered worst case. Plotted below are typical worst case SFDR
numbers for various system clock rates.
output frequency at 180 MHz system clock (upper
trace) and 125 MHz system clock (lower trace)
Tek Stop 2.50GS/s
22 Acgs
T
[
]
120
100
: 2.0ns
@ : 105.2ns
C1 Rise
2.03ns
80
60
40
V = +5V
S
1
V
= +3.3V
S
20
0
M 20.0ns Ch 1
D 5.00ns Runs After
252mV
0
20
40
60
80
100
120
140
160
180
Ch1 100mV
SYSTEM CLOCK – MHz
TPC 13. Comparator RiseTime, 15 pF Load
clock frequency
REV. D
70
65
600
500
1.1MHz
60
55
50
400
300
200
V
= +3.3V
S
40.1MHz
V
= +5V
S
70.1MHz
45
40
100
0
5
10
MAXIMUM DAC I
15
– mA
20
0
20
40
60
80
100
120
140
160
INPUT FREQUENCY – MHz
OUT
TPC 17. Effect of DAC maximum output current on
wideband (0 to 72 MHz) SFDR at three representa-
tive DAC output frequencies: 1.1 MHz, 40.1 MHz,
TPC 18. Minimum p-p input signal needed to tog-
gle the AD9851 comparator output. Comparator
input is a sine wave compared with a fixed volt-
age threshold. Use this data in addition to sin(x)/x
rolloff and any filter losses to determine whether
adequate signal is being presented to the AD9851
comparator.
and 70.1 MHz. VS = 5 V, 180 MHz system clock (6
REFCLK multiplier disabled). Currents are set using
appropriate values of R
REV. D
8
8
I
I/Q MIXER
AND
LOW-PASS
FILTER
AD9059
DUAL
8-BIT ADC
Rx
RF IN
DIGITAL
DEMODULATOR
Rx BASEBAND
DIGITAL DATA OUT
Q
VCA
AGC
ADC CLOCK FREQUENCY
LOCKED TO
Tx CHIP/SYMBOL/PN RATE
ADC ENCODE
180MHz
OR 30MHz
AD9851
32
CLOCK
GENERATOR
CHIP/SYMBOL/PN
RATE DATA
REFERENCE
CLOCK
Figure 1. Chip Rate Clock Generator Application in a Spread Spectrum Receiver
LOW-PASS
IOUT
FILTER
100k
100k
100
470pF
200
200
8-BIT PARALLEL DATA,
OR 1-BIT 40 SERIAL DATA,
RESET, W CLK AND FQ UD
MICROPROCESSOR
7TH ORDER ELLIPTICAL
DATA
BUS
OR
70MHz LOW PASS
MICROCONTROLLER
200 IMPEDANCE
IOUTB
VOLTAGE HERE = CENTER POINT
OF SINE WAVE (0.5V TYPICALLY)
USING PASSIVE AVERAGING CIRCUIT
AD9851
0 TO 1V p-p
SINE WAVE
180MHz OR 30MHz
REFERENCE
CLOCK
CMOS
OUTPUTS
QOUT
QOUTB
R
SET
3.9k
Figure 2. Basic Clock Generator Configuration
REFERENCE
IOUT and IOUTB are equally loaded with 100 . Two 100 k
resistors sample each output and average the two voltages.The
result is filtered with the 470 pF capacitor and applied to one
comparator input as a dc switching threshold. The filtered DAC
sine wave output is applied to the other comparator input.The
comparator will toggle with nearly 50% duty cycle as the sine
wave alternately traverses the center point threshold.
CLOCK
RF
PHASE
COMPARATOR
LOOP
FILTER
FREQUENCY
VCO
OUT
FILTER
REF CLK IN
AD9851
DDS
PROGRAMMABLE
DIVIDE-BY-N FUNCTION
(WHERE N = 2 /TUNING WORD)
32
RF
TUNING
WORD
IF FREQUENCY
FILTER
FREQUENCY
OUT
IN
Figure 5. Digitally Programmable Divide-by-N
Function in PLL
FILTER
REFERENCE
CLOCK
AD9851
DDS
TUNING
WORD
AD9851/FSPCB
8-BIT
EVALUATION
BOARD
ADSP-2181
BUS
DATA
BUS
EZ-KIT LITE
DSP
DAC
OUT
INPUT/
ADSP-2181
DSP
PROCESSOR
OUTPUT
DECODE
LOGIC
AD9851
DDS
FM RF
OUTPUT
for Frequency Mixing/Multiplying
REFERENCE
CLOCK
REF
OSC
AD1847
L & R
AUDIO IN
STEREO
AD9851
DDS
TUNING
WORD
CODEC
FILTER
Figure 6. High Quality, All Digital RF Frequency
Modulation
RF
PHASE
LOOP
FILTER
FREQUENCY
OUT
VCO
COMPARATOR
High quality, all digital RF frequency modulation generation with
in Analog Devices’ application note AN-543. It uses an image of
the DDS output as illustrated in Figure 8.
DIVIDE-BY-N
Figure 4. Frequency/Phase-Agile Reference for PLL
REV. D
W CLK #1
The differential DAC output connection in Figure 9 enables
reduction of common-mode signals and allows highly reactive
filters to be driven without a filter input termination resistor (see
above single-ended example, Figure 8). A 6 dB power advantage
is obtained at the filter output as compared with the single-ended
example, since the filter need not be doubly terminated.
W CLK IOUT
AD9851
#1
FQ UD
RESET
W CLK #1
FQ UD
FQ UD
90
PHASE
MICROPROCESSOR
OR
DIFFERENCE
8-BIT DATA BUS
RESET
REF
CLOCK
MICROCONTROLLER
DIFFERENTIAL
TRANSFORMER COUPLED
RESET
RESET
FQ UD
IOUT
OUTPUT
21
W CLK #2
FILTER
REFERENCE
CLOCK
50
AD9851
AD9851
DDS
#2
W CLK
W CLK #2
20
50
1:1 TRANSFORMER
Figure 7. Application Showing Synchronization of
Two AD9851 DDSs to Form a Quadrature Oscillator
i.e., MINI-CIRCUITS T1–1T
After a common RESET command is issued, separate W_CLKs
allow independent programming of each AD9851 40-bit input reg-
ister via the 8-bit data bus or serial input pin. A common FQ_UD
pulse is issued after programming is completed to simultaneously
engage both oscillators at their specified frequency and phase.
Figure 9. Differential DAC Output Connection for
Reduction of Common-Mode Signals
SET input is driven by an external DAC (Figure 10)
to provide amplitude modulation or fixed, digital amplitude control
of the DAC output current. Full description of this application is
Information. An Analog Devices' application note for the AD9850,
AN-423, describes another method of amplitude control using
an enhancement mode MOSFET that is equally applicable to
BANDPASS
AMPLIFIER
FILTER
240MHz
IOUT
AD9851
6
50
50
30MHz
CLOCK
AD9851
SPECTRUM
FINAL OUTPUT
SPECTRUM
REFCLK multiplier of the AD9851 is engaged,
the 125 MHz clocking source shown in Figure 10 can be reduced
by a factor of six.
FUNDAMENTAL
F
+ F
O
C
F
– F
O
F
+ F
O
C
C
IMAGE
IMAGE
IMAGE
F
BANDPASS
FILTER
CLK
60 120
FREQUENCY – MHz
180 240
240
FREQUENCY – MHz
Figure 8. Deriving a High Frequency Output Signal
from the AD9851 by Using an Alias or Image Signal
+5V
+5V
+5V
DIFFERENTIAL
TRANSFORMER COUPLED
OUTPUT
20mA
MAX
330
200
DATA
GENERATOR
e.g., DG-2020
4k
12
9
21
10-BIT DAC
AD9731
IOUT
10 BITS
R
SET
50
AD9851
DDS
–5V
20
IOUT
125MHz
50
1:1 TRANSFORMER
CONTROL
DATA
COMPUTER
Figure 10.The AD9851 RSET Input Being Driven by an External DAC
REV. D
–11
REFERENCE
CLOCK
DDS CIRCUITRY
N
D/A
CONVERTER
PHASE
ACCUMULATOR
AMPLITUDE/SINE
CONV ALGORITHM
CLOCK
OUT
LP
COMPARATOR
TUNING WORD SPECIFIES
OUTPUT FREQUENCY AS A
FRACTION OF REF CLOCK
FREQUENCY
IN DIGITAL
DOMAIN
F
SIN (X)/ ENVELOPE
OUT
= ()F/F
C
F
–F
O
C
F
+F
O
2F –F
C
C
O
F
C
2F +F
3F –F
C O
C
O
0Hz
(DC)
20MHz
80MHz
1ST IMAGE
120MHz
2ND IMAGE
180MHz
3RD IMAGE
220MHz
4TH IMAGE
280MHz
5TH IMAGE
100MHz
SYSTEM CLOCK FREQUENCY
Figure 12. Output Spectrum of a Sampled Sin(x)/x Signal
value of the 32-bit phase accumulator to the 10-bit quantized
amplitude that is passed to the DAC.This unique algorithm uses a
much-reduced ROM look-up table and DSP to perform this func-
tion.This contributes to the small size and low power dissipation of
The AD9851 uses direct digital synthesis (DDS) technology,
in the form of a numerically controlled oscillator (NCO), to
generate a frequency/phase-agile sine wave. The digital sine
wave is converted to analog form via an internal 10-bit high
speed D/A converter. An on-board high speed comparator
is provided to translate the analog sine wave into a low-jitter
TTL/CMOS-compatible output square wave. DDS technol-
ogy is an innovative circuit architecture that allows fast and
precise manipulation of its output word, under full digital con-
trol. DDS also enables very high resolution in the incremental
selection of output frequency. The AD9851 allows an output
frequency resolution of approximately 0.04 Hz at an 180 MSPS
clock rate with the option of directly using the reference clock or
by engaging the 6REFCLK multiplier. The AD9851’s out-
put waveform is phase-continuous from one output frequency
change to another.
The relationship between the output frequency, system clock, and
tuning word of the AD9851 is determined by the expression:
fOUT = (Phase
System Clock)/232
= decimal value of 32-bit frequency tuning word.
System Clock = direct input reference clock (in MHz) or 6
input clock (in MHz) if the 6REFCLK multiplier is engaged.
fOUT = frequency of the output signal in MHz.
The digital sine wave output of the DDS core drives the internal
high speed 10-bit D/A converter that will construct the sine wave
in analog form.This DAC has been optimized for dynamic per-
formance and low glitch energy, which results in the low spurious
and jitter performance of the AD9851.The DAC can be operated
in either the single-ended (Figures 2 and 8) or differential output
configuration (Figures 9 and 10). DAC output current and RSET
values are determined using the following expressions:
The basic functional block diagram and signal flow of the
AD9851 configured as a clock generator is shown in Figure 11.
The DDS circuitry is basically a digital frequency divider function
whose incremental resolution is determined by the frequency of
the system clock, and N (number of bits in the tuning word). The
phase accumulator is a variable-modulus counter that increments
the number stored in it each time it receives a clock pulse. When
the counter reaches full-scale it wraps around, making the phase
accumulator’s output phase-continuous. The frequency tuning
word sets the modulus of the counter, which effectively determines
the size of the increment ( Phase) that will be added to the value
in the phase accumulator on the next clock pulse. The larger
the added increment, the faster the accumulator wraps around,
which results in a higher output frequency.
I
R
OUT = 39.93/RSET
= 39.93/IOUT
Since the output of the AD9851 is a sampled signal, its output
spectrum follows the Nyquist sampling theorem. Specifically,
its output spectrum contains the fundamental plus aliased sig-
nals (images) that occur at integer multiples of the system clock
frequency ± the selected output frequency. A graphical repre-
sentation of the sampled spectrum, with aliased images, is shown
in Figure 12. Normal usable bandwidth is considered to extend
from dc to 1/2 the system clock.
The AD9851 uses an innovative and proprietary angle rotation
algorithm that mathematically converts the 14-bit truncated
REV. D
In the example shown in Figure 12, the system clock is 100 MHz
and the output frequency is set to 20 MHz. As can be seen, the
aliased images are very prominent and of a relatively high energy
level as determined by the sin(x)/x rolloff of the quantized
D/A converter output. In fact, depending on the f/system clock
relationship, the first aliased image can equal the fundamental
amplitude (when fOUT = 1/2 system clock). A low-pass filter is
generally placed between the output of the D/A converter and the
input of the comparator to suppress the jitter-producing effects
of nonharmonically related aliased images and other spurious
signals. Consideration must be given to the relationship of the
selected output frequency, the system clock frequency, and alias
frequencies to avoid unwanted output anomalies.
signals’ overall phase noise. As an example, an oscillator with
–100 dBc phase noise operating at 180 MHz would appear as a
–125 dB contribution to DDS overall phase noise for a 10 MHz
output. Engaging the 6REFCLK multiplier has generally been
found to increase overall output phase noise.This increase is due
(15.5 dB) phase gain transfer function of the
REFCLK multiplier, as well as noise generated internally by
the clock multiplier circuit. By using a low phase noise reference
clock input to the AD9851, users can be assured of better than
–100 dBc/Hz phase noise performance for output frequencies
up to 50 MHz at offsets from 1 kHz to 100 kHz.
Programming the AD9851
The AD9851 contains a 40-bit register that stores the 32-bit
frequency control word, the 5-bit phase modulation word,
REFCLK multiplier, enable, and the power-down func-
tion. This register can be loaded in parallel or serial mode. A
logic high engages functions; for example, to power-down the
IC (sleep mode), a logic high must be programmed in that bit
will find only a slight change in programming the AD9851,
specifically, data[0] of W0 (parallel load) and W32 (serial load)
REFCLK multiplier enable bit that needs
to be set high to enable or low to disable the internal reference
clock multiplier.
Images need not be thought of as useless by-products of a
DAC. In fact, with bandpass filtering around an image and
some amount of post-filter amplification, the image can become
the primary output signal (see Figure 8). Since images are not
harmonics, they retain a 1:1 frequency relationship to the fun-
damental output.That is, if the fundamental is shifted 1 kHz,
then the image is also shifted 1 kHz.This relationship accounts
for the frequency stability of an image, which is identical to that
of the fundamental. Users should recognize that the lower image
of an image pair surrounding an integer multiple of the system
clock will move in a direction opposite to that of the funda-
mental. Images of an image pair located above an integer multiple
of the system clock will move in the same direction as a fundamen-
Note: setting data[1] high in programming wordW0 (parallel
mode) or wordW33 high in serial mode is not allowed (see
Tables I and III).This bit controls a factory test mode that will
cause abnormal operation in the AD9851 if set high. If erro-
neously entered (as evidenced by Pin 2 changing from an input
pin to an output signal), an exit is provided by asserting RESET.
Unintentional entry to the factory test mode can occur if an
FQ_UD pulse is sent after initial power-up and RESET of the
AD9851. Since RESET does not clear the 40-bit input register,
this will transfer the random power-up values of the input register
to the DDS core.The random values may invoke the factory test
mode or power-down mode. Never issue an FQ_UD command if
the 40-bit input register contents are unknown.
The frequency band where images exist is much richer in spu-
rious signals and, therefore, more hostile in terms of SFDR.
Users of this technique should empirically determine what fre-
quencies are usable if their SFDR requirements are demanding.
A good rule-of-thumb for applying the AD9851 as a clock gen-
erator is to limit the fundamental output frequency to 40% of
reference clock frequency to avoid generating aliased signals that
are too close to the output band of interest (generally dc—
highest selected output frequency) to be filtered.This practice
will ease the complexity and cost of the external filter require-
ment for the clock generator application.
In the default parallel load mode, the 40-bit input register is loaded
using an 8-bit bus. W_CLK is used to load the register in five
iterations of eight bytes. The rising edge of FQ_UD transfers the
contents of the register into the device to be acted upon and resets
the word address pointer to W0. Subsequent W_CLK rising edges
load 8-bit data, starting at W0 and then move the word pointer
to the next word. After W0 through W4 are loaded, additional
W_CLK edges are ignored until either a RESET is asserted or an
FQ_UD rising edge resets the address pointer to W0 in prepara-
tion for the next 8-bit load. See Figure 13.
The reference clock input of the AD9851 has a minimum limi-
REFCLK multiplier engaged and
5 MHz with multiplier engaged. The device has internal circuitry
that senses when the clock rate has dropped below the minimum
and automatically places itself in the power-down mode. In this
mode, the on-chip comparator is also disabled. This is important
information for those who may wish to use the on-chip compara-
tor for purposes other than squaring the DDS sine wave output.
When the clock frequency returns above the minimum threshold,
the device resumes normal operation after 5 µs (typically). This
shutdown mode prevents excessive current leakage in the dynamic
registers of the device.
In serial load mode, forty subsequent rising edges of W_CLK will
shift and load the 1-bit data on Pin 25 (D7) through the 40-bit
register in shift-register fashion. Any further W_CLK rising edges
after the register is full will shift data out causing data that is left in
the register to be out-of-sequence and corrupted. The serial mode
must be entered from the default parallel mode (see Figure 17).
Data is loaded beginning with W0 and ending with W39. One
parallel word (W0)—xxxxx011—that
serial word immediately after entering the serial mode to prevent
unintended engaging of the 6REFCLK multiplier or entry into
The impact of reference clock phase noise in DDS systems is
actually reduced, since the DDS output is the result of a division
of the input frequency. The amount of apparent phase noise
reduction, expressed in dB, is found using 20 log fOUTCLK
OUT is the fundamental DDS output frequency and f
the system clock frequency. From this standpoint, using the high-
est system clock input frequency makes good sense in reducing the
effects of reference clock phase noise contribution to the output
REV. D
4. Output = 10 MHz (for 180 MHz system clock)
the factory test mode. Exit from serial mode to parallel mode is
only possible using the RESET command.
In parallel mode, user would program the 40-bit control word
(composed of five 8-bit loads) as follows:
The function assignments of the data and control words are shown
in Tables I and III; the detailed timing sequence for updating the
output frequency and/or phase, resetting the device, engaging the
REFCLK multiplier, and powering up/down, are shown in
the timing diagrams of Figures 13 through 20. As a programming
example for the following DDS characteristics:
REFCLK multiplier engaged
3. Powered-up mode selected
If in serial mode, load the 40 bits starting from the LSB location
ofW4 in the above array, loading from right to left, and ending
Table I. 8-Bit Parallel-Load Data/ControlWord Functional Assignment
Data[7]
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
Phase–b4 (MSB)
Phase–b0 (LSB)
Logic 0
Multiplier
Freq–b24
Freq–b16
Freq–b8
Freq–b31 (MSB)
Freq–b23
Freq–b15
Freq–b30
Freq–b22
Freq–b14
Freq–b6
Freq–b29
Freq–b21
Freq–b13
Freq–b5
Freq–b28
Freq–b20
Freq–b12
Freq–b4
Freq–b27
Freq–b19
Freq–b11
Freq–b3
Freq–b26
Freq–b18
Freq–b10
Freq–b2
Freq–b25
Freq–b17
Freq–b9
Freq–b1
Freq–b7
Freq–b0 (LSB)
This bit is always Logic 0 unless invoking the serial mode (see Figure 17). After serial mode is entered, this data bit must be set back to Logic 0 for proper operation.
SYSCLK
tCD
DATA
W0
W1
W2
W3
W4
tWL
tDS
tDH
tWH
W CLK
tFD
t
FQ UD
t
A
VALID DATA
OUT
OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD
AND IS ASYNCHRONOUS WITH REFERENCE CLOCK
Figure 13. Parallel Load Frequency/Phase UpdateTiming Sequence
Note:To updateW0 it is not necessary to loadW1 throughW4. Simply loadW0 and assert FQ_UD.To updateW1, reloadW0 thenW1—users do not have random access to
programming words.
Table II. Timing Specifications
Symbol
DS
DH
WH
WL
CD
FH
FL
Data SetupTime
W_CLK High
W_CLK Low
REFCLK Delay after FQ_UD
FQ_UD High
FQ_UD Low
FQ_UD Delay afterW_CLK
Output Latency from FQ_UD
Frequency Change
Phase Change
FD
CF
18 SYSCLK Cycles
13 SYSCLK Cycles
Specification does not apply when the 6 REFCLK multiplier is engaged.
REV. D
SYSCLK
RESET
tRL
tRR
tRH
tRS
tOL
A
COS (0 )
OUT
SYMBOL
DEFINITION
CLK DELAY AFTER RESET RISING EDGE 3.5ns*
MIN SPEC
tRH
tRL
tRR
tRS
tOL
RESET FALLING EDGE AFTER CLK
RECOVERY FROM RESET
MINIMUM RESET WIDTH
3.5ns*
2 SYSCLK CYCLES
5 SYSCLK CYCLES
13 SYSCLK CYCLES
RESET OUTPUT LATENCY
*SPECIFICATIONS DO NOT APPLY WHEN THE REF CLOCK MULTIPLIER IS ENGAGED
Figure 14. Master ResetTiming Sequence
Note:The timing diagram above shows the minimal amount of reset time needed before writing to the device. However, the master reset does not have to be synchronous to
the SYSCLK if the minimal time is not required.
Results of Reset, Figure 14
Entry to the serial mode, see Figure 17, is via the parallel mode,
which is selected by default after a RESET is asserted. One needs
only to program the first eight bits (wordW0) with the sequence
xxxxx011 as shown in Figure 17 to change from parallel to serial
mode.TheW0 programming word may be sent over the 8-bit
data bus or hardwired as shown in Figure 18. After serial mode
is achieved, the user must follow the programming sequence of
Figure 19.
– Phase accumulator zeroed such that the output = 0 Hz (dc)
– Phase offset register set to 0 such that DAC IOUT = full-scale
output and IOUTB = zero mA output
– Internal programming address pointer reset toW0
– Power-down bit reset to 0 (power-down disabled)
– 40-bit data input register is NOT cleared
reference clock multiplier is disabled
– Parallel programming mode selected by default
DATA (W0)
XXXXX011
DATA (W0)
W CLK
XXXXX10X
W CLK
FQ UD
FQ UD
ENABLE
SERIAL MODE
SYSCLK
Figure 17. Serial Load Enable Sequence
DAC
Note: After serial mode is invoked, it is best to immediately write
a valid 40-bit serial word (see Figure 19), even if it is all zeros,
followed by a FQ_UD rising edge to flush the residual data left in
the DDS core. A valid 40-bit serial word is any word whereW33
is Logic 0.
STROBE
INTERNAL CLOCKS
DISABLED
Figure 15. Parallel Load Power-Down Sequence/
Internal Operation
1
2
3
4
D3
D2
D1
D0
D4 28
D5 27
D6 26
D7 25
DATA (W0)
XXXXX00X
AD9851
W CLK
10k
+V
SUPPLY
FQ UD
SYSCLK
Figure 18. Hardwired xxxxx011 Configuration for
Serial Load Enable Word W0 in Figure 17
INTERNAL CLOCKS
ENABLED
Figure 16. Parallel Load Power-Up Sequence (to
Recover from Power-Down)/Internal Operation
REV. D
Figure 20 shows a normal 40-bit serial word load sequence with
W33 always set to Logic 0 andW34 set to Logic 1 or Logic 0
to control the power-down function. The logic states of the
remaining 38 bits are unimportant and are marked with an X,
indicating “don’t care” status.To power down, setW34 = 1. To
power up from a powered down state, changeW34 to Logic 0.
Wake-up from power-down mode requires approximately 5 µs.
DATA
W39
W0
W1
W2
W3
FQ UD
W CLK
Note:The 40-bit input register of the AD9851 is fully program-
mable while in the power-down mode.
Figure 19. Serial Load Frequency/Phase Update Sequence
W34 = 1
OR 0
Table III. 40-Bit Serial LoadWord Functional Assignment
DATA (7) –
FQ UD
W35 = X
W0 = X W33 = 0
W38 = X W39 = X
W0
Freq–b0 (LSB)
Freq–b1
W1
W2
W3
Freq–b2
Freq–b3
W CLK
W4
W5
Freq–b4
Freq–b5
40 W_CLK RISING EDGES
W6
W7
Freq–b6
Freq–b7
Figure 20. Serial Load Power-Down\Power-Up Sequence
W8
Freq–b8
W9
Freq–b9
Freq–b10
V
V
DD
DD
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
W38
W39
Freq–b11
Freq–b12
Freq–b13
Freq–b14
Freq–b15
Freq–b16
Freq–b17
Freq–b18
Freq–b19
Freq–b20
Freq–b21
Freq–b22
Freq–b23
Freq–b24
Freq–b25
Freq–b26
Freq–b27
Freq–b28
Freq–b29
Freq–b30
Freq–b31 (MSB)
6REFCLK Multiplier Enable
Logic 0
Power-Down
Phase–b0 (LSB)
Phase–b1
VINP/
VINN
IOUT
IOUTB
a. DAC Output
c. Comparator Input
V
V
DD
DD
DIGITAL
OUT
DIGITAL
IN
b. Comparator Output
d. Digital Input
Figure 21. I/O Equivalent Circuits
Phase–b2
Phase–b3
Phase–b4 (MSB)
This bit is always Logic 0.
REV. D
been given to the low-pass filter design. Primary considerations
were input and output impedances (200 ) and a very steep roll-
off characteristic to attenuate unwanted, nearby alias signals.The
high impedance of the filter allows the DAC to develop 1 V p-p
(with 10 mA) across the two 200 resistors at the input and
output of the filter. This voltage is entirely sufficient to opti-
mally drive the AD9851 comparator. This filter was designed
with the assumption that the AD9851 DDS is at full clock
speed (180 MHz). If this is not the case, filter specifications
may need to change to achieve proper attenuation of anticipated
alias signals. BNC connectors allow convenient observation
of the comparator CMOS output and input, as well as that of
the DAC. No reference oscillator is provided for reasons stated
above. This model allows easy evaluation of the AD9851 as
a frequency and phase-agile CMOS output clock source (see
Figure 24 for electrical schematic).
(Figures 22 through 25 andTPCs 1 and 2) represent typical
implementations of the AD9851 and exemplify the use of high
frequency/high resolution design and layout practices.The print-
ed circuit board that contains the AD9851 should be a multilayer
board that allows dedicated power and ground planes.The power
and ground planes should (as much as possible) be free of etched
traces that cause discontinuities in the planes. It is recommended
that the top layer of the board also contain an interspatial ground
plane that makes ground available without vias for the surface-
mount devices. If separate analog and digital system ground
planes exist, they should be connected together at the AD9851
evaluation board for optimum performance.
Avoid running digital lines under the device as these will couple
unnecessary noise onto the die. The power supply lines to the
AD9851 should use as large a trace as possible to provide a low-
impedance path and reduce the effects of switching currents on
the power supply line. Fast switching signals like clocks should
use microstrip, controlled impedance techniques where pos-
sible. Avoid crossover of digital and analog signal paths. Traces
on opposite sides of the board should run at right angles to each
Jitter Reduction Note
The AD9851/CGPCB has a wideband DDS fundamental output,
dc to 70 MHz, and the on-chip comparator has even more band-
width.To optimize low jitter performance users should consider
bandpass filtering of the DAC output if only a narrow bandwidth
is required.This will reduce jitter caused by spurious, nonhar-
monic signals above and below the desired signal. Lowering
the appliedVDD helps in reducing comparator switching noise
by reducing T of the comparator outputs. For optimum
jitter performance, users should avoid the very busy digital envi-
ronment of the on-chip comparator and opt for an external, high
speed comparator.
Good power supply decoupling is also an important consid-
eration. The analog (AVDD) and digital (DVDD) supplies
to the AD9851 are independent and separately pinned out to
minimize coupling between analog and digital sections of the
device. All analog and digital supply pins should be decoupled
to AGND and DGND, respectively, with high quality ceramic
chip capacitors. To achieve best performance from the decou-
pling capacitors, they should be placed as close as possible to
the device. In systems where a common supply is used to drive
both the AVDD and DVDD supplies of the AD9851, it is rec-
ommended that the system’s AVDD supply be used.
Both versions of the AD9851 evaluation boards are designed
to interface to the parallel printer port of a PC. The operating
software (C++) runs under Microsoft® ® (Windows
3.1 and Windows 95); Windows NT® not supported and pro-
vides a user-friendly and intuitive format for controlling the
functionality and observing the performance of the device.
The 3.5-in disk provided with the evaluation board contains
an executable file that displays the AD9851 function-selection
screen. The evaluation board may be operated with 3.0 V or
5 V supplies. Evaluation boards are configured at the factory
for an external clock input. If the optional on-board crystal
clock source is installed, resistor R2 (50 ) must be removed.
Analog Devices applications engineering support is available to
answer additional questions on grounding and PCB layout. Call
evaluation boards facilitate easy implementation of the device for
bench-top analysis and serve as a reference for PCB layout.
EVALUATION BOARD INSTRUCTIONS
Required Hardware/Software
The AD9851/FSPCB is intended for applications where the
device will primarily be used as a frequency synthesizer.This
version is optimized for connection of the AD9851 internal D/A
converter output to a 50 spectrum analyzer input.The internal
comparator of the AD9851 is made available for use via wire hole
access.The comparator inputs are externally pulled to opposing
voltages to prevent comparator chatter due to floating inputs.The
DDS DAC output is unfiltered and no reference oscillator is pro-
vided.This is done in recognition of the fact that many users may
find an oscillator to be a liability rather than an asset. See Figure 22
Personal computer operating inW
(does not supportWindows NT)
Printer port, 3.5-in floppy drive, mouse, and Centronics com-
patible printer cable, 3V to 5V voltage supply
Crystal clock oscillator or high frequency signal generator (sine
wave output) with dc offset capability
Setup
Copy the contents of the AD9851 disk onto the host PCs hard
drive. (There are two files,WIN9851.EXE version 1.x and
Bwcc.dll.) Connect the printer cable from the computer to the
evaluation board. Use a good quality cable as some cables do not
connect every wire that the printer port supports.
The AD9851/CGPCB is intended for applications using the
device as a CMOS output clock generator. It connects the
AD9851 DAC output to the internal comparator input via a
single-ended, 70 MHz low pass, 7th order, elliptic filter. To
minimize output jitter of the comparator, special attention has
REV. D
Apply power to AD9851 evaluation board.The AD9851 is pow-
ered separately from the other active components on the board
used to power the CMOS latches, optional crystal oscillator and
pull-up resistors. Both 5V and DUT +V may be tied together for
ease of operation without adverse affects.The AD9851 may be
powered with 2.7V to 5.25V.
Other operational modes (Frequency Sweeping, Sleep, Serial
Input) are available. Frequency sweeping allows the user to
enter a start and stop frequency and to specify the frequency
step size. Sweeping begins at the start frequency, proceeds to
the stop frequency in a linear manner, reverses direction, and
sweeps back to the start frequency repeatedly.
Note: For those who may be operating multiple AD9851 eval-
uation boards from one computer, a MANUAL FREQUENCY
UPDATE option exists. By eliminating the automatic issuance
of an FQ_UD, the user can load the 40-bit input registers of
multiple AD9851s without transferring that data to the inter-
nal accumulators. When all input registers are loaded, a single
FREQUENCY UPDATE pulse can be issued to all AD9851s.
A block diagram of this technique is shown in the AD9851 data
sheet as a quadrature oscillator application.This single pulse
synchronizes all the units so that their particular phases and
frequencies take effect simultaneously. Proper synchronization
requires that each AD9851 be clocked by the same reference
being programmed. RESET command ensures identical states.
When manual frequency update is selected, a new box labeled
FREQUENCY UPDATE will appear just above the frequency
sweeping menu. Clicking the box initiates a single FQ_UD pulse.
install a suitable crystal clock oscillator with CMOS output levels
atY1. A sine wave signal generator may be used as a clock source
at frequencies >50 MHz by dc offsetting the output signal to
1/2 the supply voltage to the AD9851.This method requires a
minimum of 2V p-p signal and disabling of the 6
Multiplier function.
Locate the file calledWIN9851.EXE and execute that program.
The computer monitor should show a control panel that allows
operation of the AD9851 evaluation board by use of a mouse.
Operation
On the control panel locate the box labeled COMPUTER I/O.
Click the correct parallel printer port for the host computer
and then click theTEST box. A message will appear indicating
whether the selection of output port is correct. Choose other
ports as necessary to achieve a correct port setting.
Note: RESET can be used to synchronize multiple oscillators.
If several oscillators have already been programmed at various
phases or frequencies, issuance of a RESET pulse will set their
outputs to 0 Hz and 0 phase. By issuing a common FQ_UD, the
previously programmed information in the 40-bit input registers
will transfer once again to the DDS core and take effect in 18
clock cycles. This is due to the fact that RESET does not affect
the contents of the 40-bit input register in any way.
Click the MASTER RESET button.This will reset the part to
0 Hz, 0° phase, parallel programming mode. The output from the
DAC IOUT should be a dc voltage equal to the full-scale output
of the AD9851 (1V for the AD9851/CGPCB and 0.5V for the
AD9851/FSPCB), while the DAC IOUTB should be 0V for both
RESET should always be the first command to the
AD9851 following power-up
Locate the CLOCK SECTION and place the cursor in the
FREQUENCY box. Enter the clock frequency (in MHz) that
will be applied to the reference clock input of the AD9851.
reference clock multiplier is to be engaged—a check mark
will appear when engaged. When the reference clock multiplier
is engaged, software will multiply the value entered in the fre-
quency box by 6; otherwise, the value entered is the value used.
Click the LOAD button or press the enter key.
The AD9851/FSPCB provides access into and out of the on-chip
comparator via test point pairs (each pair has an active input and
a ground connection). The two active inputs are labeled TP1
and TP2. The unmarked hole next to each labeled test point is a
ground connection. The two active outputs are labeled TP5 and
TP6. Adjacent to those test points are unmarked ground connec-
tions. To prevent unwanted comparator chatter when not in use,
the two inputs are pulled either to ground or +V via 1 k
The AD9851/CGPCB provides BNC inputs and outputs asso-
ciated with the on-chip comparator and an onboard, 7th order,
input /output Z, elliptic 70 MHz low-pass filter. Jumper-
ing (soldering a wire) E1 to E2, E3 to E4, and E5 to E6 connects
the onboard filter and the midpoint switching voltage to the
comparator. Users may elect to insert their own filter and com-
parator threshold voltage by removing the jumpers and inserting
a filter between J7 and J6 and providing a comparator threshold
voltage at E1.
Move the cursor to the OUTPUT FREQUENCY box and type
in the desired frequency (in MHz). Click the LOAD button or
press the enter key.The BUS MONITOR section of the control
panel will show the 32-bit frequency word and 8-bit phase/
control word. Upon completion of this step, the AD9851 output
should be active at the programmed frequency/phase.
Changing the output phase is accomplished by clicking the down
and then clicking the LOAD button. Note: clicking the load but-
tons of the clock frequency box, the output frequency box, or the
phase box will automatically initiate a reloading of all three boxes
and issuance of a FQ_UD (frequency update) pulse. To bypass
this automatic reloading and frequency update sequence, refer to
Use of the XTAL oscillator socket on the evaluation board to sup-
ply the clock to the AD9851 requires the removal R2 (a 50 chip
resistor) unless the oscillator can drive a 50 load. The crystal
oscillator should be either TTL or CMOS (preferably) compatible.
REV. D
J1
C36CPRX
U2
74HCT574
1
2
3
4
5
6
7
8
AD9851/FSPCB
FREQUENCY
RRSET
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
8D
7D
6D
5D
4D
3D
2D
1D
8Q
D0
D1
D2
D3
D4
D5
D6
D7
SYNTHESIZER
7Q
6Q
5Q
4Q
3Q
2Q
1Q
EVALUATION BOARD
J2
J3
J4
+V
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
D3
D2
D1
D0
D4 28 D4
27
BANANA
JACKS
D5
D5
+5V
GND
U1
AD9851
D6 26 D6
D7 25 D7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CK
OE
PGND
24
23
22
21
20
19
18
17
16
15
GND
+V
DGND
DVDD
RESET
IOUT
GND
+V
11
1
PVCC
STROBE
W CLK
FQ UD
REFCLOCK
WCLK
FQUD
CLKIN
GND
RESET
J6
FFQUD
DAC OUT
TO 50
R4
IOUTB
AGND
AVDD
DACBP
VINP
50
R5
25
10 AGND
GND
+V
R1
AVDD
+V 11
3.9k
10mA
RESET
R
12
13
NC
SET
U3
74HCT574
VOUTN
TP5
TP6
TP7
TP8
TP1
TP2
TP3
TP4
14 VOUTP
VINN
9
8
7
6
5
4
3
2
12
13
14
15
16
17
18
19
COMPARATOR
INPUTS
8D
7D
6D
5D
4D
3D
2D
1D
8Q
RRESET
WWCLK
FFQUD
RESET
WCLK
FQUD
GND
GND
GND
GND
7Q
6Q
5Q
4Q
3Q
2Q
1Q
NC = NO CONNECT
J5
RRESET
CHECK
R5
1k
CLKIN
+V
R2
50
R7
REMOVE WHEN
USING Y1
1k
WWCLK
CHECK
GND
CK
5V
14
OE
11
1
V
CC
STROBE
XTAL
OSC
STROBE
8
OUT
Y1
(OPTIONAL)
GND
7
+V
5V
+V
5V
C2
0.1F
C3
0.1F
C4
0.1F
C5
0.1F
C8
0.1F
C9
0.1F
C10
0.1F
C6
10F
C7
10F
MOUNTING HOLES
5V
H1
#6
H2
#6
H3
#6
H4
#6
R8
2.2k
R9
2.2k
R10
2.2k
R3
2.2k
STROBE
WWCLK
FFQUD
RRESET
Figure 22. FSPCB Electrical Schematic
REV. D
23a. FSPCBTop Layer
23c. FSPCB Ground Plane
23b. FSPCB Power Plane
23d. FSPCB Bottom Layer
Figure 23. FSPCB Evaluation Board 4-Layer PCB Layout Patterns
AD9851/FSPCB Evaluation Board Parts List—GSO 0516(A)
1 Amp 552742-1, 36-Pin Plastic, Right Angle,
PC Mount, Female
1 Banana Jack–Color Not Important
Yellow Banana Jack
Decoupling Capacitors
7 Size 1206 Chip Capacitor, 0.1 µF
J1
J2
J3
J4
C2–C5,
C6, C7
Tantalum Capacitors, 10 µF
1 Black Banana Jack
2 BNC Coax. Connector, PC Mount
GSO 0516(A)
4 AMP 5-330808-6, Open-Ended Pin Socket
2 #2-56 Hex Nut (to Fasten J1)
(to Fasten J1)
J5, J6
Chip Resistor, Size 1206
Chip Resistor, Size 1206
Chip Resistor, Size 1206
Chip Resistor, Size 1206
R2, R4
R3, R8,
R9, R10
R6, R7
Chip Resistor, Size 1206
Integrated Circuits
1 AD9851 Direct Digital Synthesizer, Surface-mount
2 74HCT574AN HCMOS Octal Flip-Flop,
4 #4-40 Hex Nut (to Fasten Standoffs to Board)
Through-Hole Mount
U2, U3
REV. D
AD9851/CGPCB
CLOCK GENERATOR
EVALUATION BOARD
(SSOP PACKAGE)
J2
J3
J4
+V
TO BYPASS ON BOARD FILTER
1. REMOVE E6 TO E5 JUMPER
2. INSTALL APPROPRIATE R12 FOR IOUT TERMINATION
BANANA
JACKS
5V
J7
BNC
GND
70MHz ELLIPTICAL LOW-PASS FILTER
R12
7TH ORDER 200 Z
D3
D2
D1
D0
1
D3
D2
D1
D0
D4 28 D4
27
L1
L2
L3
2
3
4
5
6
7
8
9
D5
D5
470nH
390nH
390nH
U1
AD9851
D6 26 D6
D7 25 D7
E6 E5
C12
1pF
C14
5.6pF
C16
4.7pF
PGND
24
23
22
21
20
19
18
17
16
15
GND
+V
DGND
DVDD
RESET
IOUT
GND
+V
R6
200
R7
200
R4
100k
C11
22pF
C13
33pF
C15
22pF
C17
22pF
PVCC
W CLK
FQ UD
REFCLOCK
WCLK
FQUD
CLKIN
GND
RESET
R5
100k
IOUTB
AGND
AVDD
DACBL
VINP
R8
100
10 AGND
GND
+V
R1
AVDD
+V 11
3.9k
10mA
RESET
R
12
13
NC
SET
J6
VOUTN
J8
14 VOUTP
BNC
VINN
C1
470pF
NC = NO CONNECT
J9
E1
E2
E4
E3
BNC
J5
J1
CLKIN
C36CPR2
U2
74HCT574
12
R2
1
2
3
4
5
6
7
8
50
REMOVE WHEN
USING Y1
RRSET
9
8
7
6
5
4
3
2
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
D0
D1
D2
D3
D4
D5
D6
D7
13
14
15
16
17
18
19
5V
14
V
CC
XTAL
8
Y1
OSC
OUT
(OPTIONAL)
9
GND
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CK
OE
11
1
+V
5V
STROBE
FFQUD
+V
5V
C7
C2
0.1F
C3
C4
0.1F
C5
0.1F
C8
0.1F
C9
0.1F
C10
0.1F
0.1F
C6
10F
10F
U3
74HCT574
9
8
7
6
5
4
3
2
12
8D
7D
6D
5D
4D
3D
2D
1D
8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
RRESET
WWCLK
FFQUD
RESET
WCLK
FQUD
13
14
15
16
17
18
19
RRESET
CHECK
MOUNTING HOLES
5V
H1
#6
H2
#6
H3
#6
H4
#6
R9
2.2k
R10
2.2k
R11
2.2k
R3
2.2k
CK
OE
RRESET
FFQUD
WWCLK
STROBE
11
1
WWCLK
CHECK
STROBE
STROBE
Figure 24. CGPCB Electrical Schematic
REV. D
25a. CGPCBTop Layer
25c. CGPCB Power Plane
25b. CGPCB Ground Plane
25d. CGPCB Bottom Layer
Figure 25. FSPCB Evaluation Board 4-Layer PCB Layout Patterns
REV. D
CGPCB Evaluation Board Parts List—GSO 0515(B)
1 Amp 552742-1, 36-Pin Plastic, Right Angle,
PC Mount, Female
1 Banana Jack—Color Not Important
Yellow Banana Jack
J1
J2
J3
1 Black Banana Jack
5 BNC Coax. Connector, PC Mount
J4
J5, J6, J7,
J8, J9
GSO 0515(B)
4 AMP 5-330808-6, Open-Ended Pin Socket
2 #2-56 Hex Nut (to Fasten J1)
(to Fasten J1)
4 #4-40 Hex Nut (to Fasten Stand-Offs to Board)
Decoupling Capacitors
1 Size 1206 Chip Capacitor, 470 pF
7 Size 1206 Chip Capacitor, 0.1 µF
C2–C5,
C6, C7
Tantalum Capacitors, 10 µF
Chip Resistor, Size 1206
Chip Resistor, Size 1206
Chip Resistor, Size 1206
R3, R9,
R10, R11
R4, R5
R6, R7
Chip Resistor, Size 1206
Chip Resistor, Size 1206
Chip Resistor, Size 1206
1 Dummy Resistor (for Optional Installation)
Filter Capacitors (70 MHz 7-Pole Elliptic Filter)
3 22 pF Chip Capacitor, Size 1206
C11, C15,
1 1 pF Chip Capacitor, Size 1206
1 33 pF Chip Capacitor, Size 1206
1 5.6 pF Chip Capacitor, Size 1206
1 4.7 pF Chip Capacitor, Size 1206
Inductors (70 MHz 7-Pole Elliptic Filter)
1 470 nH Chip Inductor, Coil Craft 1008CS
2 390 nH Chip Inductor, Coil Craft 1008CS
L2, L3
Integrated Circuits
1 AD9851 Direct Digital Synthesizer,
2 74HCT574AN HCMOS Octal Flip-Flop,
Through-Hole Mount
U2, U3
REV. D
28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
10.50
10.20
9.90
28
15
5.60 8.20
5.30 7.80
5.00 7.40
14
1
1.85
0.10
COPLANARITY
1.75
1.65
2.00 MAX
0.25
0.09
8
4
0
0.95
0.75
0.55
0.38
0.22
0.65
BSC
0.05
MIN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-150AH
Revision History
Page
1/04—Data Sheet changed from REV. C to REV. D
Renumbered figures andTPCs
Updated ORDERING GUIDE
Updated OUTLINE DIMENSIONS
REV. D
相关型号：
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