AD9887AKSZ140 [ADI]
IC SPECIALTY CONSUMER CIRCUIT, PQFP160, LEAD FREE, PLASTIC, MS-022DD-1, MQFP-160, Consumer IC:Other;
| 型号： | AD9887AKSZ140 |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQFP160, LEAD FREE, PLASTIC, MS-022DD-1, MQFP-160, Consumer IC:Other 商用集成电路 |
| 文件： | 总40页 (文件大小：775K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Interface for
Flat Panel Displays
a
AD9887
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Analog Interface
140 MSPS Maximum Conversion Rate
330 MHz Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
500 ps p-p PLL Clock Jitter at 140 MSPS
3.3 V Power Supply
Full Sync Processing
Midscale Clamp
ANALOG
INTERFACE
REF
REFOUT
REFIN
R
OUTA
8
8
8
8
8
R
CLAMP
A/D
A/D
A/D
AIN
R
OUTB
G
OUTA
8
4:2:2 Output Format Mode
G
AIN
CLAMP
CLA
G
B
Digital (DVI 1.0 Compatible) Interface
112 MHz Operation (1 Pixel/Clock Mode)
High Skew Tolerance of One Full Input Clock
Sync Detect for “Hot Plugging”
B
8
OUTA
B
B
AIN
OUTB
DATACK
HSOUT
2
APPLICATIONS
HSYNC
VSYNC
COAST
CLAMP
CKINV
CKEXT
FILT
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
SYNC
8
VSOUT
PROCSSING
ANOCK
GRATION
R
OUTA
SOGOUT
8
8
8
8
8
2
R
OUTB
S
CDT
G
OUTA
Micro Displays
M
U
X
E
S
Digital TV
G
OUTB
L
S
B
OUTA
SERIAL REGISTER
AND
B
OUTB
A
A
1
0
POWER MANAGEMENT
GENERAL DESCRIPTION
DATACK
HSOUT
VSOUT
SOGOUT
DE
The AD9887 offers designers the flexibility of a dual
digital interface for flat panel displays (FPDs) on a sin
Both interfaces are optimized for excellent imagality su
display resolutions up to SXGA (1280 × 10at 75 Hz). Either he
analog or the digital interface can be seled by .
DIGITAL
INTERFACE
R
8
8
OUTA
8
8
R
OUTB
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
G
8
8
OUTA
Analog Interface
G
For ease of design and to minimit, the AD988s a fully
integrated interface solution foThe AD97 includes an
analog interface with a 140 with internal 1.25 V
reference, PLL to generate a pixSYNC, program-
mable gain, offset, and clamp contr provides only a
3.3 V power supplyut, anYNC. Three-state
CMOS outputs mfrom 2.5 V to 3.3 V.
OUTB
B
DVI
RECEIVER
8
8
OUTA
8
B
OUTB
2
DATACK
DE
HSYNC
VSYNC
R
TERM
The AD9887’s ones a pixel clock from HSYNC.
Pixel clock output ge from 12 MHz to 140 MHz.
PLL clock jitter is 5typical at 140 MSPS. When a
COAST signal is presented, the PLL maintains its output fre-
quency in the absence of HSYNC. A sampling phase adjustment is
provided. Data, HSYNC and Clock output phase relationships are
maintained. The PLL can be disabled and an external clock input
provided as the pixel clock. The AD9887 also offers full sync pro-
cessing for composite sync and sync-on-green applications.
AD9887
Digital Interface
The AD9887 contains a Digital Video Interface (DVI 1.0) compat-
ible receiver. This receiver supports displays ranging from VGA
to SXGA (25 MHz to 112 MHz). The receiver operates with
true color (24-bit) panels in 1 or 2 pixel(s)/clock mode, and also
features an intrapair skew tolerance up to one full clock cycle.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. The analog interface
is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9887 is pro-
vided in a 160-lead MQFP surface mount plastic package and is
specified over the 0°C to 70°C temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD9887–SPECIFICATIONS
(V = 3.3 V, V = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.)
ANALOG INTERFACE
D
DD
Test
AD9887KS-100
AD9887KS-140
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
8
8
Bits
DC ACCURACY
Differential Nonlinearity
25°C
Full
25°C
Full
I
VI
I
VI
VI
0.5
+1.15/–1.0
+1.15/–1.0
1.40
0.5
+1.25/–1.0
+1.25/–1.0
1.4
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
0.5
0.5
1.75
2.5
Full
Guaranteed
Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Full
Full
25°C
25°C
Full
Full
Full
Full
VI
VI
V
IV
IV
VI
VI
VI
0.5
0.5
V p-p
V p-p
ppm/°C
µA
1.0
1.0
135
150
Input Bias Current
1
1
50
8.0
56
1
1
50
8.0
56
µA
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
7
mV
% FS
% FS
44
50
44
50
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
Full
Full
VI
V
1.20
1.25
5
1.30
0
1.25
50
1.30
V
ppm/°C
SWITCHING PERFORMANCE1
Maximum Conversion Rate
Minimum Conversion Rate
Clock to Data Skew, tSKEW
tBUFF
tSTAH
tDHO
tDAL
tDAH
Full
Full
Full
Full
Full
Full
Full
Full
Ful
F
Full
5°C
ull
ull
VI
IV
IV
VI
VI
V
VI
VI
V
IV
IV
IV
100
140
MSPS
MSPS
ns
1
+2.0
10
+2.0
–0
4.7
4.0
0
4.0
250
4.0
15
–0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
µs
µs
µs
µs
µs
tDSU
tSTASU
tSTOSU
ns
µs
µs
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock
PLL Jitter
110
110
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
100
140
12
12
400
15
7002
10002
400
15
7003
10003
Sampling Phase Tem
DIGITAL INPUTS
Input Voltage, High (VIH
Input Voltage, Low (VIL)
Input Current, High (VIH
Input Current, Low (VIL)
Input Capacitance
)
Full
Full
Full
Full
25°C
VI
VI
IV
IV
V
2.6
2.6
V
V
µA
µA
pF
0.8
–1.0
1.0
0.8
–1.0
1.0
)
3
3
DIGITAL OUTPUTS
Output Voltage, High (VOH
)
Full
Full
VI
VI
2.4
45
2.4
45
V
V
Output Voltage, Low (VOL
Duty Cycle
)
0.4
55
0.4
55
DATACK, DATACK
Output Coding
Full
IV
50
Binary
50
Binary
%
–2–
REV. 0
AD9887
Test
AD9887KS-100
AD9887KS-140
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
Full
Full
Full
25°C
25°C
25°C
Full
IV
IV
IV
V
V
V
3.0
2.2
3.0
3.3
3.3
3.3
140
34
15
170
18
3.6
3.6
3.6
3.0
2.2
3.0
3.3
3.3
3.3
155
48
16
215
18
3.6
3.6
3.6
V
V
V
mA
mA
mA
mA
mA
P
VD Supply Voltage
ID Supply Current (VD)
IDD Supply Current (VDD
4
)
IPVD Supply Current (PVD
)
Total Supply Current4
VI
VI
258
25
258
25
Power-Down Supply Current
Full
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)5
(Without Harmonics)
25°C
25°C
25°C
25°C
Full
V
V
V
V
V
330
2
1.5
46
45
330
2
5
45
MHz
ns
ns
dB
dB
f
IN = 40.7 MHz
Crosstalk
Full
V
V
60
30
60
30
dBc
THERMAL CHARACTERISTICS
θ
JA Junction-to-Ambient6
Thermal Resistance
°C/W
NOTES
1Drive Strength = 11.
2VCO Range = 01, Charge Pump Current = 001, PLL Divider = 1693.
3VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1600.
4DEMUX = 1, DATACK and DATACK Load = 10 pF, Data Load = 5
5Using external pixel clock.
6Simulated typical performance with package mounted to a 4-layer
Specifications subject to change without notice.
–3–
REV. 0
AD9887–SPECIFICATIONS
(V = 3.3 V, V = 3 V, Clock = Maximum)
DIGITAL INTERFACE
D
DD
Test
AD9887KS
Parameter
Conditions
Level
Min
Typ
Max
Unit
RESOLUTION
8
Bits
DC DIGITAL I/O SPECIFICATIONS
High-Level Input Voltage, (VIH
)
VI
VI
VI
VI
IV
IV
IV
IV
IV
2.6
2.4
V
V
V
V
V
V
V
V
µA
Low-Level Input Voltage, (VIL)
High-Level Output Voltage, (VOH
0.8
)
Low-Level Output Voltage, (VOL
Input Clamp Voltage, (VCINL
Input Clamp Voltage, (VCIPL
Output Clamp Voltage, (VCONL
Output Clamp Voltage, (VCOPL
)
0.4
)
)
(ICL = –18 mA)
(ICL = +18 mA)
(ICL = –18 mA)
(ICL = +18 mA)
(High Impedance)
GND – 0.8
VDD + 0.8
GND – 0.8
VDD + 0.8
+10
)
)
Output Leakage Current, (IOL
)
–
DC SPECIFICATIONS
Output High Drive
Output Drive = High
Output Drive = Med
Output Drive = Low
Output Drive = High
Output Drive = Med
Output Drive = Low
Output Drive = High
Output Drive = Med
Output Drive = Low
Output Drive = h
Output Drive = M
OutpuLow
IV
IV
IV
IV
IV
IV
I
IV
IV
IV
IV
IV
13
8
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mV
(IOHD) (VOUT = VOH
)
–9
–7
–5
25
12
8
–25
–19
–8
(IOLD) (VOUT = VOL
)
(VOHC) (VOUT = VOH
DATACK Low Drive
)
(VOLC) (VOUT = VOL
)
Differential Input Voltage Single-Ended Amplitude
75
800
3.6
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
IV
3.0
3.3
V
Minimor 2 Pixels per
Clock Mode
IV
IV
V
2.2
3.0
3.3
3.3
274
38
3.6
3.6
V
V
mA
mA
PVD Supply Voltage
VD Supply Current (Typical Pattern)1
VDD Supply Current (Typical Pattern)1,
V
P
VD Supply Current (Typical Patte
V
VI
V
V
V
21
mA
mA
mA
mA
mA
mA
mA
Total Supply Current (Typical Pat
VD Supply Current (Worst-Case Patte
VDD Supply Current (WoPattern
PVD Supply Current (ern)2
Total Supply Currenern)2, 4
362
280
75
21
400
13
VI
VI
Power-Down Supply
25
AC SPECIFICATIONS
Intrapair (+ to –) Differential Input Skew (TDPS
Channel-to-Channel Differential Input Skew (TCCS
)
IV
IV
360
1.0
ps
)
Clock
Period
ns
ns
ns
ns
ns
ns
ns
Low-to-High Transition Time for Data and
Output Drive = High; CL = 10 pF
Output Drive = Med; CL = 7 pF
Output Drive = Low; CL = 5 pF
Output Drive = High; CL = 10 pF
Output Drive = Med; CL = 7 pF
Output Drive = Low; CL = 5 pF
Output Drive = High; CL = 10 pF
Output Drive = Med; CL = 7 pF
Output Drive = Low; CL = 5 pF
IV
IV
IV
IV
IV
IV
IV
IV
IV
2.0
3.0
3.4
1.3
1.9
2.5
2.7
3.0
3.3
Controls (DLHT
)
Low-to-High Transition Time for DATACK (DLHT
)
High-to-Low Transition Time for Data and
Controls (DHLT
)
ns
ns
–4–
REV. 0
AD9887
Test
Level
AD9887KS
Typ
Parameter
Conditions
Min
Max
Unit
AC SPECIFICATIONS (continued)
High-to-Low Transition Time for DATACK (DHLT
)
Output Drive = High; CL =10 pF
Output Drive = Med; CL = 7 pF
Output Drive = Low; CL = 5 pF
IV
IV
IV
IV
IV
1.4
1.7
2.1
+2.0
55
ns
ns
ns
ns
% of
Period
High
MHz
MHz
Clock to Data Skew, tSKEW
Duty Cycle, tDCYCLE
–0.5
45
DATACK Frequency (FCIP) (1 Pixel/Clock)
DATACK Frequency (FCIP) (2 Pixels/Clock)
VI
IV
20
10
112
56
NOTES
1The typical pattern contains a gray scale area, Output Drive = High.
2The worst-case pattern contains a black and white checkerboard pattern, Output Drive = High.
3The setup and hold times with respect to the DATACK rising edge are the same as the falling edge.
41 Pixel/clock mode, DATACK and DATACK Load = 10 pF, Data Load = 5 pF.
ABSOLUTE MAXIMUM RATINGS
*
EXPLANAN OF TEST LEVELS
VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . .
Maximum Case Temperature . . . . . . . . . . . . . . . . .
*Stresses above those listed under Absolute Maximum Ratings ma
nent damage to the device. This is a stress rating only; functional op
device at these or any other conditions outside of those d in th
sections of this specification is not implied. Exposure bsolute maximum rs
for extended periods may affect device reliability.
Test Lel
Explanation
I
II
100% production tested.
10% production tested at 25°C and sample
sted at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and charac-
terization testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed
by design and characterization testing.
III
V
V
VI
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option
Mo
AD988
887K
7/PC
0°C to 70°C
0°C to 70°C
25°C
Plastic Quad Flatpack
Plastic Quad Flatpack
Evaluation Board
S-160
S-160
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9887 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–5–
REV. 0
AD9887
PIN CONFIGURATION
1
V
120
119
118
117
116
115
114
113
1
110
109
108
10
105
R
R
V
DD
MIDSC
PIN 1
IDENTIFIER
2
GND
GREEN A<7>
GREEN A<6>
GREEN A<5>
GREEN A<4>
GREEN A<3>
GREEN A<2>
GREEN A<1>
GREEN A<0>
AIN
3
R
V
CLAMP
4
V
D
5
GND
6
V
V
D
D
7
8
GND
GND
G
G
G
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
V
MIDSC
AIN
V
DD
GND
GREEN B<7>
GREEN B<6>
GREEN B<5>
GREEN B<4>
GREEN B<3>
GREEN B<2>
GREEN B<1>
GREEN B<0>
V
CP
SIN
D
GND
V
D
104
103
102
101
100
99
V
D
GND
GND
B
V
MIDSC
AD9887
TOP VIEW
(Not to Scale)
V
B
DD
AIN
GND
BLUE A<7>
BLUE A<6>
BLUE A<5>
BLUE A<4>
BLUE A<3>
BLUE A<2>
BLUE A<1>
BLUE A<0>
B
V
CLAMP
98
V
D
97
GND
96
V
D
95
GND
CKINV
CLAMP
SDA
SCL
A0
A1
PV
PV
GND
94
93
92
91
V
90
DD
GND
BLUE B<7>
BLUE B<6>
BLUE B<5>
BLUE B<4>
BLUE B<3>
BLUE B<2>
BLUE B<1>
BLUE B<0>
89
88
D
87
D
86
85
GND
84
COAST
CKEXT
HSYNC
VSYNC
83
82
81
NC =
–6–
REV. 0
AD9887
Table I. Complete Pinout List
P
in
Type
Pin
Name
Pin
Number Interface
Function
Value
Analog Video
Inputs
RAIN
GAIN
BAIN
Analog Input for Converter R
Analog Input for Converter G
Analog Input for Converter B
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
119
110
100
Analog
Analog
Analog
External
Sync/Clock
Inputs
HSYNC
VSYNC
SOGIN
CLAMP
COAST
CKEXT
CKINV
Horizontal SYNC Input
Vertical SYNC Input
Input for Sync-on-Green
Clamp Input (External CLAMP Signal)
PLL COAST Signal Input
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V COS
3.3 CMOS
82
81
108
93
84
83
94
Analog
Analog
Analog
Analog
Analog
Analog
Analog
External Pixel Clock Input (to Bypass the PLL) to VDD or Ground
ADC Sampling Clock Invert
Sync Outputs
HSOUT
VSOUT
SOGOUT
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
Sync on Green Slicer Output
3CM
3.3 OS
3.3 V OS
139
8
140
Both
Both
Analog
Voltage
Reference
REFOUT
REFIN
Internal Reference Output (Bypass with 0.1 µF to Ground
Reference Input (1.25 V 10%)
1.25 V
.25 V 10%
126
125
Analog
Analog
Clamp Voltages
R
MIDSCV
Red Channel Midscale Clamp Voltage Output
Red Channel Midscale Clamp Voltage Input
Green Channel Midscale Clamp Voltage Out
Green Channel Midscale Clamp Voltage Input
Blue Channel Midscale Clamp Voltage Output
Blue Channel Midscale Clamp Voltage Input
120
118
111
109
101
99
Analog
Analog
Analog
Analog
Analog
Analog
RCLAMP
GMIDSC
GCLAMP
BMIDSC
V
V
V
V
V
0.0 to 0.75 V
0.0 V to 0.75 V
0.0 V to 0.75 V
BCLAMP
PLL Filter
FILT
Connection for External Filter Coonents for Internal PLL
78
Analog
Power Supply
VD
Analog Power Supply
Output Power Supply
PLL Power Supply
Ground
3.3 V 10%
3.3 V 10%
3.3 V 10%
0 V
Both
Both
Both
Both
VDD
PVD
GND
Serial Port
(2-Wire
Serial Interface) A0
A1
SDA
SCL
Serial Port Data I/O
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
92
91
90
89
Both
Both
Both
Both
Serial Port DClock ()
Serial PoAddress Input 1
Serial PAddret 2
Data Outputs
Red B[7:0]
Green B[7:0]
Blue B[7:0]
Red A[7:0]
Green A[7:0]
Blue A[7:0]
Port B/Odutputs of nverter “Red,” Bit 7 Is the MSB
B/Odd Outputs of onverter “Green,” Bit 7 Is the MSB
Odd Ouof Converter “Blue,” Bit 7 Is the MSB
Outputs of Converter “Red,” Bit 7 Is the MSB
Outputs of Converter “Green,” Bit 7 Is the MSB
Outputs of Converter “Blue,” Bit 7 Is the MSB
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
153–160 Both
13–20
33–40
Both
Both
143–150 Both
3–10
23–30
Both
Both
Data Clock
Outputs
D
Dput Clock for the Analog and Digital Interface
Data Output Clock Complement for the Analog Interface Only
3.3 V CMOS
3.3 V CMOS
134
135
Both
Both
Sync Detect
Sync Detect Output
3.3 V CMOS
136
Both
Scan Function
S
SCA
SCANCLK
Input for SCAN Function
Output for SCAN Function
Clock for SCAN Function
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
129
45
50
Both
Both
Both
No Connect
NC
These Pins Should be Left Unconnected
71–73
Both
Digital Video
Data Inputs
Rx0
Rx0–
Rx1
Rx1–
Rx2
Rx2–
+
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
62
63
59
60
56
57
Digital
Digital
Digital
Digital
Digital
Digital
+
+
Digital Input Channel 2 Complement
Digital Video
Clock Inputs
Rxc+
Rxc–
Digital Data Clock True
Digital Data Clock Complement
65
66
Digital
Digital
Data Enable
Control Bits
RTERM
DE
Data Enable
3.3 V CMOS
3.3 V CMOS
137
Digital
Digital
Digital
CTL[0:3]
RTERM
Decoded Control Bits
Sets Internal Termination Resistance
46–49
53
–7–
REV. 0
AD9887
DESCRIPTIONS OF PINS SHARED BETWEEN ANALOG
AND DIGITAL INTERFACES
Data Clock Outputs
DATACK
Data Output Clock
HSOUT
Horizontal Sync Output
DATACK
Data Output Clock Complement
A reconstructed and phase-aligned version of
the video HSYNC. The polarity of this output
can be controlled via a serial bus bit. In analog
interface mode the placement and duration
are variable. In digital interface mode the
placement and duration are set by the graphics
transmitter.
Just like the data outputs, the data clock out-
puts are shared between the two interfaces.
They also behave differently depending on
which interface is active. Refer to the sections
on the two interfaces to determine how these
pins behave.
Various
SCDT
VSOUT
Vertical Sync Output
Chip Active/Inactive Detect Output
The separated VSYNC from a composite
signal or a direct pass through of the VSYNC
input. The polarity of this output can be con-
trolled via a serial bus bit. The placement and
duration in all modes is set by the graphics
transmitter.
The logic for the SDT pin is [analog interface
HSYNC detectn] OR digital interface DE
detection]. She ST pin will switch to
logic LOW undconditis, when nei-
ther inface is actor wn the chip is in
full iower-down e. The data outputs
are automcally three-stated when SCDT is
LOW. This can be read by a controller in
order to determe periods of inactivity.
Serial Port (2-Wire)
SDA
SCL
A0
Serial Port Data I/O
Serial Port Data Clock
Serial Port Address Input 1
Serial Port Address Input 2
SCAN Fuion
SCANIN
Data Inpfor SCAN Function
A1
For a full description of the 2-wire serial regis-
ter and how it works, refer to the Control
Register section.
ata n be loaded serially into the 48-bit
SN register through this pin, clocking it in
with the SCANCLK pin. It then comes out of
the 48 data outputs in parallel. This function
is useful for loading known data into a graph-
ics controller chip for testing purposes.
Data Outputs
RED A
RED B
GREEN A
GREEN B
BLUE A
Data Output, Red Channel, Port A/Even
Data Output, Red Channel, Port B/Odd
Data Output, Green Channel, Port A/Ev
Data Output, Green Channel, B/Odd
Data Output, Blue Channelort A/Even
Data Output, Blue Channel, oOdd
NOUT
SCANCLK
Data Output for SCAN Function
The data in the 48-bit SCAN register can be
read through this pin. Data is read on a FIFO
basis and is clocked via the SCANCLK pin.
BLUE B
Data Clock for SCAN Function
The main data outpuit 7 is the MSB
These outputs are etween wo
interfaces and bto which
interface is activections on the
two interfaces for mtion on how
these ohave.
This pin clocks the data through the SCAN
register. It controls both data input and data
output.
–8–
REV. 0
AD9887
Table II. Analog Interface Pin List
Pin Type
Pin Name
Function
Value
Pin No.
Analog Video Inputs
RAIN
GAIN
BAIN
HSYNC
VSYNC
SOGIN
CLAMP
COAST
CKEXT
Analog Input for Converter R
Analog Input for Converter G
Analog Input for Converter B
Horizontal SYNC Input
Vertical SYNC Input
Sync-on-Green Input
Clamp Input (External CLAMP Signal)
PLL COAST Signal Input
External Pixel Clock Input (to Bypass Internal PLL)
or 10 kΩ to VDD
ADC Sampling Clock Invert
HSYNC Output (Phase-Aligned with DATACK and DATACK
VSYNC Output (Asynchronous)
Sync-on-Green Slicer Output or Raw HSYNC Output
Internal Reference Output (bypass with 0.1 µF to gr
Reference Input (1.25 V 10%)
Voltage output equal to the RED converter mscale voltage.
During midscale clamping, the RED Input is amped to this pin.
Voltage output equal to the GREEN corter micale voltage.
During midscale clamping, the GREEN Inis mped to this pin.
Voltage output equal to the BLUE convertedscale ltage.
During midscale clamping, the BLUE Input is md to this pin.
Connection for External FiltComponents for Inernal PLL
Main Power Supply
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
119
110
100
82
81
108
93
External
Sync/Clock
Inputs
84
83
CKINV
3.3 V CMOS
V CMOS
3.3 V COS
.3 V MOS
V
1.25 V 10%
0.5 V 50%
0.0 V to 0.75 V
0.5 V 50%
0.0 V to 0.75 V
0.5 V 50%
0.0 V to 0.75 V
94
Sync Outputs
HSOUT
VSOUT
SOGOUT
REFOUT
REFIN
139
138
140
126
125
120
118
111
109
101
99
Voltage Reference
Clamp Voltages
RMIDSC
V
R
CLAMPV
GMIDSC
GCLAMP
V
V
B
MIDSCV
BCLAMP
FILT
VD
PVD
VDD
GND
V
PLL Filter
Power Supply
78
3.3 V 5%
3.3 V 5%
3.3 V or 2.5 V 5%
0 V
PLL Power Supply (Nonally 3.3
Output Power Sup
Ground
PIN FUNCTION DETAILS (ANALOG INTERFACE
Inputs
Polarity = 0, the falling edge of HSYNC is
used. When HSYNC Polarity = 1, the rising
edge is active.
RAIN
GAIN
BAIN
Analog Input for RED hanne
Analog Input for GREEN hannel
Analog Input UE Channel
The input includes a Schmitt trigger for noise
immunity, with a nominal input threshold
of 1.5 V.
High-impat accept the RED,
GREEN, al graphics signals,
respectively. Fthree channels are
idd can for any colors, but
gned r convenient reference.
:2 formatting in a YUV appli-
hannel must be connected to
tut, U must be connected to the
Electrostatic Discharge (ESD) protection
diodes will conduct heavily if this pin is driven
more than 0.5 V above the maximum toler-
ance voltage (3.3 V), or more than 0.5 V
below ground.
VSYNC
SOGIN
Vertical Sync Input
This is the input for vertical sync.
Sync-on-Green Input
B
AIN input, and V must be connected to the
AIN input.
R
This input is provided to assist with processing
signals with embedded sync, typically on the
GREEN channel. The pin is connected to a
high-speed comparator with an internally
generated threshold, which is set to 0.15 V
above the negative peak of the input signal.
They accommodate input signals ranging
from 0.5 V to 1.0 V full scale. Signals should
be ac-coupled to these pins to support clamp
operation.
HSYNC
Horizontal Sync Input
This input receives a logic signal that estab-
lishes the horizontal timing reference and
provides the frequency reference for pixel
clock generation.
When connected to an ac-coupled graphics
signal with embedded sync, it will produce a
noninverting digital output on SOGOUT.
When not used, this input should be left
unconnected. For more details on this func-
tion and how it should be configured, refer to
the Sync-on-Green section.
The logic sense of this pin is controlled by
serial register 0Fh Bit 7 (HSYNC Polarity).
Only the leading edge of HSYNC is active,
the trailing edge is ignored. When HSYNC
–9–
REV. 0
AD9887
CLAMP
External Clamp Input (Optional)
This pin should be exercised only during blanking
intervals (typically vertical blanking) as it may
produce several samples of corrupted data during
the phase shift.
This logic input may be used to define the
time during which the input signal is clamped
to the reference dc level, (ground for RGB or
midscale for YUV). It should be exercised
when the reference dc level is known to be
present on the analog input channels, typically
during the back porch of the graphics signal.
The CLAMP pin is enabled by setting control
bit EXTCLMP to 1, (the default power-up is 0).
When disabled, this pin is ignored and the
clamp timing is determined internally by
counting a delay and duration from the trailing
edge of the HSYNC input. The logic sense of
this pin is controlled by CLAMPOL. When
not used, this pin must be grounded and
EXTCLMP programmed to 0.
CKINV should be grounded when not used.
Outputs
DRA7-0
Data Output, Red Channel, Port A
Data Output, Red Channel, Port B
Data Output, Green Channel, Port A
Data Output, Green Channel, Port B
Data Output, Blue hannel, Port A
Data Output, ue Chael, Port B
These are the mdaoutputs. Bit 7 is the MSB.
DRB7-0
DGA7-0
DGB7-0
DBA7-0
DBB7-0
Each cnnel has twports. hen the part is
opersingle-chanode (DEMUX = 0),
all data aresented to Port A, and Port B is
placed in a hiimpedance state.
COAST
Clock Generator Coast Input (Optional)
This input may be used to cause the pixel clock
generator to stop synchronizing with HSYNC
and continue producing a clock at its current
frequency and phase. This is useful when
processing signals from sources that fail to
produce horizontal sync pulses when in the
vertical interval. The COAST signal is generally
not required for PC-generated signals. Appli-
cations requiring COAST can do so through
the internal COAST found in the SYNC
processing engine.
Programming DEMUX to 1 established dual-
cnnel mode, wherein alternate pixels are
resenteto Port A and Port B of each chan-
nel. Tse will appear simultaneously, two
presented at the time of every second
input pixel, when PAR is set to 1 (parallel
mode). When PAR = 0, pixel data appear
alternately on the two ports, one new sample
with each incoming pixel (interleaved mode).
In dual channel mode, the first pixel after
HSYNC is routed to Port A. The second pixel
goes to Port B, the third to A, etc.
The logic sense of this pin is controlled
COAST Polarity.
When not used, this pin may e grounded and
COAST Polarity programmto 1,
HIGH and COAST Polarity ammed 0.
COAST Polarity defs to 1 at power-.
The delay from pixel sampling time to output is
fixed. When the sampling time is changed by
adjusting the PHASE register, the output timing is
shifted as well. The DATACK, DATACK, and
HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
CKEXT
External Clock Iional)
This pin may ban external
clock to the AD98f the clock
internarated YNC.
DATACK
Data Output Clock
DATACK
Data Output Clock Complement
It iogramming EXTCLK to 1.
Whck is used, all other internal
funcormally. When unused, this
pin shoto VDD or to GROUND, and
EXTCLK programmed to 0. The clock phase
adjustment still operates when an external clock
source is used.
Differential data clock output signals to be
used to strobe the output data and HSOUT
into external logic.
They are produced by the internal clock gen-
erator and are synchronous with the internal
pixel sampling clock.
When the AD9887 is operated in single-chan-
nel mode, the output frequency is equal to the
pixel sampling frequency. When operating in
dual channel mode, the clock frequency is one-
half the pixel frequency.
CKINV
Sampling Clock Inversion (Optional)
This pin may be used to invert the pixel
sampling clock, which has the effect of
shifting the sampling phase 180°. This is in
support of Alternate Pixel Sampling mode,
wherein higher-frequency input signals (up
to 280 Mpps) may be captured by first sam-
pling the odd pixels, then capturing the even
pixels on the subsequent frame.
When the sampling time is changed by adjusting
the PHASE register, the output timing is shifted
as well. The Data, DATACK, DATACK, and
HSOUT outputs are all moved, so the timing
relationship among the signals is maintained.
–10–
REV. 0
AD9887
Either or both signals may be used, depend-
ing on the timing mode and interface design
employed.
Power Supply
VD
Main Power Supply
These pins supply power to the main elements
of the circuit. It should be filtered to be as
quiet as possible.
HSOUT
Horizontal Sync Output
A reconstructed and phase-aligned version of
the Hsync input. Both the polarity and dura-
tion of this output can be programmed via
serial bus registers.
VDD
Digital Output Power Supply
These supply pins are identified separately
from the VD pins so special care can be taken
to minimize output noise transferred into the
sensitive analog circuitry.
By maintaining alignment with DATACK,
DATACK, and Data, data timing with
respect to horizontal sync can always be
determined.
If the AD9887 s interfacing with lower-
voltage logicVDD may be connected to a
lower supy voltag(as low as 2.2 V) for
compatity.
SOGOUT
Sync-On-Green Slicer Output
This pin can be programmed to output
either the output from the Sync-On-Green
slicer comparator or an unprocessed but
delayed version of the HSYNC input. See
the Sync Block Diagram to view how this
pin is connected.
PVD
Clk Gener PoweSupply
most sensitortion of the AD9887 is
the ck generation circuitry. These pins
provide wer to the clock PLL and help the
user desigor optimal performance. The
designer should provide noise-free power to
these pins.
(Note: The output from this pin is the sliced
SOG, without additional processing from the
AD9887.)
GND
ound
Analog Interface
REFOUT
The ground return for all circuitry on chip.
It is recommended that the application circuit
board have a single, solid ground plane.
Internal Reference Output
Output from the internal 1.25 V bandgap refer-
ence. This output is intended to drive r
light loads. It can drive the AD9887
Input directly, but should be exter
ered if it is used to drive other load
THERY OF OPERATION (INTERFACE DETECTION)
Active Interface Detection and Selection
The AD9887 includes circuitry to detect whether or not an
interface is active.
The absolute accuracy of is utput i
and the temperature coficient is 50 ppm,
which is adequate for ost 988appli-
cations. If higher accuracy is requi, an
external referey be employeinstead.
For detecting the analog interface, the circuitry monitors the
presence of HSYNC, VSYNC, and Sync-on-Green. The result of
the detection circuitry can be read from the 2-wire serial inter-
face bus at address 11H Bits 7, 6, and 5 respectively. If one of
these sync signals disappears, the maximum time it takes for the
circuitry to detect it is 100 ms.
If an exterused, connect this
pin to grouµF capacitor.
There are two stages for detecting the digital interface. The first
stage searches for the presence of the digital interface clock.
The circuitry for detecting the digital interface clock is active
even when the digital interface is powered down. The result of
this detection stage can be read from the 2-wire serial interface
bus at address 11H Bit 4. If the clock disappears, the maximum
time it takes for the circuitry to detect it is 100 ms. The second
stage attempts to detect DE on the digital interface. Detection is
accomplished when 32 DEs have been counted. DE can only be
detected when the digital interface is powered up, so it is not
always active. The DE detection circuitry is one of the logic
inputs used to set the SyncDT output pin (Pin 136). The logic
for the SyncDT pin is [DE detect] OR [HSYNC detect].
REFIN
Reference Inpu
e inpuccepts the master refer-
r all AD9887 internal circuitry
. It may be driven directly by
pin. Its high impedance pre-
senty light load to the reference source.
This pin should always be bypassed to Ground
with a 0.1 µF capacitor.
FILT
External Filter Connection
For proper operation, the pixel clock genera-
tor PLL requires an external filter. Connect
the filter shown Figure 7 to this pin. For
optimal performance, minimize noise and
parasitics on this node.
There is an override for the automatic interface selection. It is
the AIO bit (Active Interface Override). When the AIO bit is set
to Logic 0, the automatic circuitry will be used. When the AIO
bit is set to Logic 1, the AIS bit will be used to determine the
active interface rather than the automatic circuitry.
–11–
REV. 0
AD9887
Power Management
and the power-down bit to determine the correct power state.
In a given power mode not all circuitry in the inactive interface
is powered down completely. When the digital interface is
active, the bandgap reference and HSYNC detect circuitry is not
powered down. When the analog interface is active, the digital
interface clock detect circuit is not powered down. Table IV
summarizes how the AD9887 determines which power mode to
be in and what circuitry is powered on/off in each of these
modes. The power-down command has priority, followed by the
active interface override, and then the automatic circuitry.
The AD9887 is a dual interface device with shared outputs.
Only one interface can be used at a time. For this reason, the
chip automatically powers down the unused interface. When
the analog interface is being used, most of the digital interface
circuitry is powered down and vice-versa. This helps to minimize
the AD9887 total power dissipation. In addition, if neither inter-
face has activity on it, the chip powers down both interfaces.
The AD9887 uses the activity detect circuits, the active inter-
face bits in the serial registers, the active interface override bits,
Table III. Interface Selection Controls
Analog
Interface Detect
Digital
Interface Detect AIS
Active
Interface
AIO
Description
1
X
0
0
1
1
X
0
1
0
0
0
1
X
Analog
Digital
None
Force the analog ierface e.
Force the digitaterface acti
Neither interce detected. Bh interfaces are
powered down and tSyncDT pin gets set to Logic 0.
The dial interface waetected. Power down the
analinterface.
Tnalog nterface was detected. Power down the
digitrface.
Both infaces re detected. The analog interface has
0
X
X
X
1
Digital
Analog
Analog
Digital
priority.
Both interfaces were detected. The digital interface has
priority
Table IV. Pode Descriptions
In
Analo
Digit
ve
Active
Power- Intface Interface Interface Interface
Mode
Down1
Dect2
t3
Override Select
Powered On or Comments
Soft Power-Down (Seek Mode)
1
0
0
0
0
0
X
X
X
Serial Bus, Digital Interface Clock Detect,
Analog Interface Activity Detect, SOG,
Bandgap Reference
Serial Bus, Digital Interface, Analog Interface
Activity Detect, SOG, Outputs, Bandgap
Reference
Serial Bus, Analog Interface, Digital Interface
Clock Detect, SOG, Outputs, Bandgap
Reference
Digital Interface On
1
0
Analog Interface On
Serial Bus Arbitrated In
Serial Bus Arbitrated Inte
Override to Analog Interface
Override to Digital Interface
Absolute Power-Down
1
1
0
1
1
X
X
X
1
1
X
X
X
0
0
1
1
X
0
1
0
1
X
Same as Analog Interface On Mode
Same as Digital Interface On Mode
Same as Analog Interface On Mode
Same as Digital Interface On Mode
Serial Bus
NOTES
1Power-down is controlled via bit 0 in serial bus Register 12h.
2Analog Interface Detect is determined by OR-ing Bits 7, 6, and 5 in serial bus Register 11h.
3Digital Interface Detect is determined by Bit 4 in serial bus Register 11h.
–12–
REV. 0
AD9887
THEORY OF OPERATION AND DESIGN GUIDE
(ANALOG INTERFACE)
General Description
The AD9887 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The device is ideal for implementing a computer
interface in HDTV monitors or as the front end to high-
performance video scan converters.
HSYNC, VSYNC Inputs
The AD9887 receives a horizontal sync signal and uses it to
generate the pixel clock and clamp timing. It is possible to operate
the AD9887 without applying HSYNC (using an external clock,
external clamp) but a number of features of the chip will be
unavailable, so it is recommended that HSYNC be provided.
This can be either a sync signal directly from the graphics
source, or a preprocessed TTL or CMOS level signal.
Implemented in a high-performance CMOS process, the inter-
face can capture signals with pixel rates of up to 140 MHz and,
with an Alternate Pixel Sampling mode, up to 280 MHz.
The HSYNC input includes a Schmitt trigger buffer and is capable
of handling signals with long rise times, with superior noise
immunity. In typical PC-based graphic systems, the sync signals
are simply TTL-level drivers feeding unshielded wires in the
monitor cable. As such, no ternation is required or desired.
The AD9887 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control,
and output data formatting. All controls are programmable via
a 2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensi-
tive to the physical and electrical environment.
When the VSYNC input is ected ahe source for VSYNC, it is
used for COAST generatians passed through to the
VSOUT pin.
Serial Control P
The serial contl pordesigned for 3.3 V logic. If there are
5 V drivers n the bus, te pins should be protected with
150 Ω sers resistors placed tween the pull-up resistors and
the inpt pins.
With a typical power dissipation of less than 725 mW and an
operating temperature range of 0°C to 70°C, the device requires
no special environmental considerations.
Input Signal Handling
Output gl Handlig
The AD9887 has three high-impedance analog input pins for
the Red, Green, and Blue channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
The digitautputs e designed and specified to operate from a
3.3 V power (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-lead D connector, or BNC conne
The AD9887 should be located as close as practical t
input connector. Signals should be routed via matched
traces (normally 75 Ω) to the IC input pins.
amping
RCmping
To ditize the incoming signal properly, the dc offset of the
nput must be adjusted to fit the range of the on-board A/D
converters.
At that point the signal should be resistively inated
to the signal ground return) and capacitivy coupled to the
AD9887 inputs through 47 nF capacitorTheapaors
form part of the dc restoration circuit.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. The white level will then be
approximately 1.0 V. Some common RGB line amplifier boxes
use emitter-follower buffers to split signals and increase drive
capability. This introduces a 700 mV dc offset to the signal, which
is removed by clamping for proper capture by the AD9887.
In an ideal world of perfectly matpedancehest per-
formance can be obtained with le signal bandwidth.
The wide bandwidth inputs o30 MHz) can
track the input signal continuous from one pixel
level to the next, and the png a long, flat pixel
time. In many sys, therre mismatches, reflec-
tions, and noise, in excessive ringing and
distortion of the iThis makes it more difficult
to establish a sampat provides good image quality.
It has been shown that all inductor in series with the input
is effective in rolling off the input bandwidth slightly, and pro-
viding a high quality signal over a wider range of conditions.
Using a Fair-Rite #2508051217Z0 High-Speed Signal Chip
Bead inductor in the circuit of Figure 1 gives good results in
most applications.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. Originating
from CRT displays, the electron beam is “blanked” by sending a
black level during horizontal retrace to prevent disturbing the
image. Most graphics systems maintain this format of sending a
black level between active video lines.
An offset is then introduced which results in the A/D converters
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In systems with embedded sync, a blacker-than-black signal
(HSYNC) is produced briefly to signal the CRT that it is time
to begin a retrace. For obvious reasons, it is important to avoid
47nF
R
AIN
AIN
RGB
INPUT
G
B
AIN
75⍀
Figure 1. Analog Input Interface Circuit
REV. 0
–13–
AD9887
clamping on the tip of HSYNC. Fortunately, there is virtually
always a period following HSYNC called the back porch where
a good black reference is provided. This is the time when clamp-
ing should be done.
R
R
V
MIDSC
V
CLAMP
0.1F
G
G
V
MIDSC
The clamp timing can be established by exercising the CLAMP
pin at the appropriate time (with EXTCLMP = 1). The polarity
of this signal is set by the Clamp Polarity bit.
V
CLAMP
0.1F
B
V
MIDSC
An easier method of clamp timing employs the AD9887 internal
clamp timing generator. The Clamp Placement register is pro-
grammed with the number of pixel clocks that should pass after
the trailing edge of HSYNC before clamping starts. A second
register (Clamp Duration) sets the duration of the clamp.
These are both 8-bit values, providing considerable flexibility in
clamp generation. The clamp timing is referenced to the trailing
edge of HSYNC, the back porch (black reference) always follows
HSYNC. A good starting point for establishing clamping is to
set the clamp placement to 08h (providing eight pixel periods
for the graphics signal to stabilize after sync) and set the clamp
duration to 14h (giving the clamp 20 pixel periods to reestablish
the black reference).
B
V
CLAMP
0.1F
Figure 2. Typical Clamp Configration for RBG/YUV
Applications
Gain and Offset Control
The AD9887 can accommoate iignals wh inputs rang-
ing from 0.5 V to 1.0 V fl scale. Tull-sce range is set in
three 8-bit registers (Rain, Green and Blue Gain).
A code of 0 establishes a mium input range of 0.5 V; 255
corresponds withe maximuange of 1.0 V. Note that
increasing the ain setting results ian image with less contrast.
The value of the external input coupling capacitor affects the per-
formance of the clamp. If the value is too small, there can be an
amplitude change during a horizontal line time (between clamping
intervals). If the capacitor is too large, it will take excessively long for
the clamp to recover from a large change in incoming signal offset.
The recommended value (47 nF) results in recovery from a step error
of 100 mV to within 1/2 LSB in 10 lines using a clamp duration of
20 pixel periods on a 60 Hz SXGA signal.
The offset ntrol ifts the entire input range, resulting in a
change in imrightnesThree 7-bit registers (Red Offset,
Green Offset, Be Ofet) provide independent settings for
ach channel.
Toffset contrls provide a 63 LSB adjustment range. This
range connted with the full-scale range, so if the input range
doublrom 0.5 V to 1.0 V) then the offset step size is also
bled (from 2 mV per step to 4 mV per step).
YUV Clamping
YUV signals are slightly different from RGB signals in tha
dc reference level (black level in RGB signals) will be at the
midpoint of the U and V video signal. For thesignals it ca
be necessary to clamp to the midscale range ohe A/D -
verter range (80h) rather than bottom of the Aerter
range (00h).
e 3 illustrates the interaction of gain and offset controls.
magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero-scale level.
Clamping to midscale rather than gn be accished
by setting the clamp select bits in gister. Each of
the three converters has its own set they can be
clamped to either midscale or ground ntly. These bits
are located in Register 0e Bits
OFFSET = 7Fh
OFFSET = 3Fh
1.0
The midscale referenach A/D converter clamps
to is provided indepeMIDSCV, GMIDSCV, and
OFFSET = 00h
B
MIDSCV pins. Each coave its own midscale refer-
ence because both offset ant and gain adjustment for
each converter will affect the dc level of midscale.
0.5
OFFSET = 7Fh
During clamping, the Y and V converters are clamped to their
respective midscale reference input. These inputs are pins
OFFSET = 3Fh
0.0
B
CLAMPV, and RCLAMPV for the U and V converters respectively.
The typical connections for both RGB and YUV clamping are
shown below in Figure 2. Note: if midscale clamping is not
required, all of the midscale voltage outputs should still be con-
nected to ground through a 0.1 µF capacitor.
OFFSET = 00h
00h
FFh
GAIN
Figure 3. Gain and Offset Control
–14–
REV. 0
AD9887
PIXEL CLOCK
INVALID SAMPLE TIMES
Sync-on-Green
The Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level from the incoming video signal with a
negative peak detector. Second, it sets the Sync trigger level
(nominally 150 mV above the negative peak). The exact trigger
level is variable and can be programmed via register 11H. The
Sync-on-Green input must be ac-coupled to the green analog
input through its own capacitor as shown in Figure 4. The value
of the capacitor must be 1 nF 20%. If Sync-on-Green is not
used, this connection is not required and SOGIN should be left
unconnected. (Note: The Sync-on-Green signal is always nega-
tive polarity.) Please refer to the Sync Processing section for more
information.
Figure 5. PixSampling Times
47nF
R
B
AIN
Any jitter in the clock reds threcision with which the
sampling time can be dtermiand mualso be subtracted
from the stable pixeme.
47nF
47nF
AIN
G
AIN
Considerable cahaeen taken in he design of the AD9887’s
clock generation circuit minimize jitter. As indicated in Fig-
ure 6, the ock jitter of the D9887 is less than 6% of the total
pixel tiin all operating modes, making the reduction in the
valid mpling me due to jitter negligible.
SOGIN
1nF
Figure 4. Typical Clamp Configuration for RGB/YUV
Applications
Clock Generation
The PLL aracterics are determined by the loop filter
design, by tPLcharge pump current and by the VCO range
setting. The lofilter design is illustrated in Figure 7. Recom-
mended settings of VCO range and charge pump current for
SA staard display modes are listed in Table VII.
A Phase Locked Loop (PLL) is employed to generate the pixel
clock. The HSYNC input provides a reference frequency for the
PLL. A Voltage Controlled Oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the
PLL divide value (Registers 01H and 02H) and phase co
with the Hsync input. Any error is used to shift the V
quency and maintain lock between the two signals.
PV
D
C
Z
0.039F
3.3k⍀
C
0.0039F
P
R
Z
The stability of this clock is a very important element
ing the clearest and most stable image. Durich pix
there is a period when the signal is slewinrom the old pixel
amplitude and settling at its new value. Tn ths ime
when the input voltage is stable, before the nal must ew to a
new value (see Figure 5). The rathe slewing timo the
stable time is a function of the h of the phics DAC
and the bandwidth of the tr(cable and termi-
nation). It is also a function of tate. Clearly, if the
dynamic characteristics of the sysn fixed, the slewing
and settling times fixed. time must be sub-
tracted from the d, leaving the stable period. At
higher pixel freqcycle time is shorter, and the
stable pixel time br as well.
FILT
Figure 7. PLL Loop Filter Detail
Four programmable registers are provided to optimize the per-
formance of the PLL. These registers are:
1. The 12-Bit Divisor Register. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock fre-
quencies in the range of 12 MHz to 140 MHz. The Divisor
Register controls the exact multiplication factor. This register
may be set to any value between 221 and 4095. (The divide
ratio that is actually used is the programmed divide ratio
plus one.)
14
12
10
8
2. The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO Range register sets this operating range.
Because there are only four possible regions, only the two
least-significant bits of the VCO Range register are used.
The frequency ranges for the lowest and highest regions
are shown in Table V.
6
4
2
0
PIXEL CLOCK – MHz
Figure 6. Pixel Clock Jitter vs. Frequency
–15–
REV. 0
AD9887
Table V. VCO Frequency Ranges
3. The 3-Bit Charge Pump Current Register. This register
allows the current that drives the low pass loop filter to be
varied. The possible current values are listed in Table VI.
provides 32 phase-shift steps of 11.25° each. The Hsync
signal with an identical phase shift is available through the
HSOUT pin. Phase adjustment is still available if the pixel
clock is being provided externally.
Pixel Clock
Range (MHz)
KVCO Gain
(MHz/V)
PV1
PV0
0
0
1
1
0
1
0
1
12–35
35–70
70–110
110–140
150
150
150
180
4. The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sam-
pling point within a clock cycle. The Phase Adjust register
Table VI. Charge Pump Current/Control Bits
The COAST allows the PLL to continue to run at the same
frequency, in the absence of the inming Hsync signal. This
may be used during the vertical nc period, or any other
time that the Hsync signal inavaille. The polarity of
the COAST signal may be set ougthe Coast Polarity Bit.
Also, the polarity of the sync sl may set through the
HSYNC polarity Bf not usinutatic polarity
detection, the HNnd COAST olarity bits should
be set to match the Polaof their respective signals.
Ip2
Ip1
Ip0
Current (A)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
100
150
250
350
500
750
1500
Table VII. Recommended VCO Range and Charge Pump Current Sgs for andard Display Formats
Horizontl
Refresh
Rate (Hz)
Frequency
(kHz)
Pixel Rate
(MH)
Standard
Resolution
VCORNGE
CURRENT
VGA
640 × 480
60
72
75
85
.175
31.500
31.500
36.000
00
00
00
00
101
101
110
110
SVGA
XGA
800 × 600
56
60
72
5
35.1
7.9
1
6.9
53.7
36.000
40.000
50.000
49.500
56.250
00
01
01
01
01
101
101
101
101
110
1024 × 768
85
48.4
56.5
60.0
64.0
68.3
65.000
75.000
78.750
85.500
94.500
01
10
10
10
10
110
101
101
101
101
SXGA
UXGA
12
1600 × 1200
60
75
85
64.0
80.0
91.1
108.000
135.000
157.500*
10
11
10
110
110
110
60
65
70
75
85
75.0
81.3
87.5
93.8
106.3
162.000*
175.500*
189.000*
202.500*
229.500*
10
10
10
10
11
110
110
110
110
110
*Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.
–16–
REV. 0
AD9887
OFFSET
7
GAIN
8
SCANCLK
SCANIN
REF
DAC
DAC
tSU = 3ns
tHOLD = 0ns
IN
8
ADC
x1.2
CLAMP
Figure 11. SCAN Setup and Hold
V
OFF
Alternate Pixel Sampling Mode
A Logic 1 input on Clock Invert CKINV, Pin 94) inverts the
nominal ADC clock. CKINV n be switched between frames
to implement the alternate el samng mode. This allows
higher effective image resoln tbe achieved at lower pixel
rates but with lower frme rate
Figure 8. ADC Block Diagram (Single Channel Output)
1V
On one frame, onen pixels arized. On the subsequent
frame, odd pixs are mpled. By reconstructing the entire
frame in the graphics conller, a complete image can be recon-
structed. his is very similathe interlacing process that is
employd in brodcast television systems, but the interlacing is
verticnsteaof horizontal. The frame data is still presented to
the displthe full esired refresh rate (usually 60 Hz) so no
flicker artifaare dded.
V
OFF
0.5V
(128 CODES)
V
OFF
(128 CODES)
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
O
O
O
O
O
O
O
O
O
O
O
E
E
E
E
E
E
E
E
E
E
E
0V
0V
Figure 9. Relationship of Offset Range to Input
SCAN Function
The SCAN function is intended as a pseudo JTAG f
manufacturing test of the board. The ordinary operati
AD9887 is disabled during SCAN.
To enable the SCAN function, set regir 14hto 1. To
SCAN in data to all 48 digital outputs, a48 seribits of
data and 48 clocks (typically 5 Mmax of 20 MH) to the
SCANIN and SCANCLK pins rely. The is shifted
in on the rising edge of SCt serial bit shifted
in will appear at the RED A<r one clock cycle.
After 48 clocks, the first bit is se way to the BLU
B<0>. The 48th bbe at ED A<7> output. If
SCANCLK continles, the data will continue to be
shifted from REB<0> and will come out of the
Figure 12. Odd and Even Pixels in a Frame
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
O 1
SCANOUT pin as the falling edge of SCANCLK
This is illustrated i0. A setup time (tSU) of 3 ns
should be plenty and no hold time (tHOLD) is required (≥ 0 ns).
This is illustrated in Figure 11.
.
Figure 13. Odd Pixels from Frame 1
SCANCLK
SCANIN
BIT 1
BIT 2
BIT 3
BIT 2
BIT 47
BIT 46
BIT 48
BIT 47
X
RED A<7>
BIT 1
BIT 3
BIT 48
BIT 1
X
X
X
BIT 2
X
X
X
BLUE B<0>
SCANOUT
X
X
BIT 1
BIT 2
X
X
X
Figure 10. SCAN Timing
–17–
REV. 0
AD9887
PXLCLK
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
ANY OUTPUT
SIGNAL
DATA OUT
DATACK
(OUTPUT)
tSKEW
tDCYCLE
tPER
Figure 17. Analog Output Timing
Hsync Timing
Figure 14. Even Pixels from Frame 2
Horizontal sync is processed in the AD9887 to eliminate
ambiguity in the timing of the leadindge with respect to the
phase-delayed pixel clock and data
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2 O 1 E 2
The Hsync input is used as a renco generate the pixel
sampling clock. The samplinphasbe adjusd, with respect
to Hsync, through a full 60° in 32 eps vthe Phase Adjust
register (to optimize thl sampling tiDisplay systems use
Hsync to align memoy and play write cycles, so it is important
to have a stable ming relatihip between Hsync output
(HSOUT) andata clock (DATK).
Three thihappeto Horizontal Sync in the AD9887. First,
the polarity Hnc input s determined and will thus have a
known output arity. e known output polarity can be pro-
grammed either ahigh or active low (Register 04H, Bit 4).
ond, HSOUT is aligned with DATACK and data outputs.
Th, the duran of HSOUT (in pixel clocks) is set via Regis-
ter 07HSUT is the sync signal that should be used to drive
rest oe display system.
Figure 15. Combine Frame Output from Graphics Controller
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3
O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3 E 2 O 3
t Timing
ost computer systems, the Hsync signal is provided con-
uously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
In some systems, however, Hsync is disturbed during the Verti-
cal Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embed Sync-On-Green (SOG), Hsync includes
equalization pulses or other distortions during Vsync. To avoid
upsetting the clock generator during Vsync, it is important to
ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it will attempt to lock to this new frequency, and will
have changed frequency by the end of the Vsync period. It will
then take a few lines of correct Hsync timing to recover at the
beginning of a new frame, resulting in a “tearing” of the image
at the top of the display.
Figure 16. Subsequent Frame from Controller
Timing (Analog Interface)
The following timing diagrams on of the
AD9887 analog interface in all clocart estab-
lishes timing by having the sample thands to the pixel
digitized when the leadiHSYNcurs sent to the
“A” data port. In Due, the next sample is sent
to the “B” port. Fututernated between the “A”
and “B” data ports. In l Mode, data is only sent
to the “A” data port, anport is placed in a high
impedance state.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally.
Coast can be provided by the graphics controller or it can be
internally generated by the AD9887 Sync processing engine.
–18–
REV. 0
AD9887
RGB
P0
P1
P2
P3
P4
P5
P6
P7
IN
HSYNC
PxCK
HS
5-PIPE DELAY
ADCCK
DATACK
D0
D1
D2
D3
D4
D5
D6
D7
D
OUTA
HSOUT
Figure 18. Single Channel Mode (Analog Intce)
RGB
IN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PxCK
HS
5-PIPE DELAY
ADCCK
DATACK
D
OUTA
2
D4
D6
HSOUT
Figure 19. Single Channel ode, 2 Pixels/Clock (Even Pixels) (Analog Interface)
P0 P7
RGB
IN
H
5.5-PIPE DELAY
ADCCK
DATACK
D
D1
D3
D5
D7
OUTA
HSOUT
Figure 20. Single Channel Mode, 2 Pixels/Clock (Odd Pixels) (Analog Interface)
–19–
REV. 0
AD9887
RGB
P0
P1
P2
P3
P4
P5
P6
P7
IN
HSYNC
PxCK
HS
3-PIPE DELAY
ADCCK
DATACK
D
OUTA
OUTB
D0
D2
D4
D6
D
D1
D3
D5
D7
HSOUT
Figure 21. Dual Channel Mode, Interleaved Outputs (Analog Interfa), Outphase = 1
RGB
P0
P1
P2
P3
P4
P5
P6
P7
IN
HSYNC
PxCK
HS
7-PIPE DELAY
ADCCK
DATACK
D
D2
D4
D6
D0
OUTA
D
OUTB
D3
D5
D7
D1
HSOUT
Figure el Mode, Parallel Outputs (Analog Interface), Outphase = 1
P4 P5 P6 P7
RGB
HSY
PxCK
HS
3-PIPE DELAY
ADCCK
DATACK
D
D0
D4
OUTA
D
D2
D6
OUTB
HSOUT
Figure 23. Dual Channel Mode, Interleaved Outputs, 2 Pixels/Clock (Even Pixels) (Analog Interface), Outphase = 1
–20–
REV. 0
AD9887
RGB
IN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PxCK
HS
5-PIPE DELAY
ADCCK
DATACK
D
D
D1
D5
OUTA
OUTB
D3
D7
HSOUT
Figure 24. Dual Channel Mode, Interleaved Outputs, 2 Pixels/Clock (Odd Pixel(Analog Interface), Outphase = 1
P0 P1 P2 P3 P4 P5 P6 P7
RGB
IN
HSYNC
PxCK
HS
7-PIPE DELAY
ADCCK
DATACK
D
D0
D2
D4
D6
OUTA
D
OUTB
HSOUT
Figure 25. Dual Crallel Outputs, 2 Pixels/Clock (Even Pixels) (Analog Interface), Outphase = 1
P2 P3 P5 P6 P7
Px
HS
7.5-PIPE DELAY
ADCCK
DATACK
D
D1
D3
D5
D7
OUTA
D
OUTB
HSOUT
Figure 26. Dual Channel Mode, Parallel Outputs, 2 Pixels/Clock (Odd Pixels) (Analog Interface), Outphase = 1
–21–
REV. 0
AD9887
P0
P1
P2
P3
P4
P5
P6
P7
RGBIN
HSYNC
PXCK
HS
6-PIPE DELAY
ADCCK
DATACK
GOUTA
Y0
Y1
V0
Y2
U2
Y3
V2
Y4
U4
Y5
V4
Y6
ROUTA
HSOUT
U0
V6
Figure 27. 4:2:2 Output Mode
Table VIII. Digital Interface Pin ist
Function
Pin Type
Pin Name
Value
Pin No.
Digital Video Data Inputs
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
RxC+
RxC–
RTERM
Digital Input Channel 0 True
Digital Input Chann0 Complement
Digital Input Channel True
Digital Input Channel 1 mplemt
Digital Inpu2 Tr
Digital Inwo’s Complement
Digital D
Digital Dlement
Col Pin the Internal
Termination Resistance
Data
62
63
59
60
56
57
65
66
53
Digital Video Clock Inputs
Termination Control
Outputs
DE
HSYNC
VSYN
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
137
139
138
46–49
YNC Oput
VSYNC tput
CT1, DecControl Bit Outputs
C
Power Supply
VD
ain Power Supply
PLL Power Supply
Output Power Supply
Ground Supply
3.3 V 5%
3.3 V 5%
3.3 V or 2.5 V 5%
0 V
PVD
Ground Supply
0 V
–22–
REV. 0
AD9887
DIGITAL INTERFACE PIN DESCRIPTIONS
Digital Video Data Inputs
THEORY OF OPERATION (DIGITAL INTERFACE)
Capturing of the Encoded Data
The first step in recovering the encoded data is to capture the
raw data. To accomplish this, the AD9887 employs a high-speed
Phase Locked Loop (PLL), to generate clocks capable of
oversampling the data at the correct frequencies. The data
capture circuitry continuously monitors the incoming data during
horizontal and vertical blanking times (when DE is low), and
independently selects the best sampling phase for each data
channel. The phase information is stored and used until the next
blanking period (one video line).
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
Positive Differential Input Video Data (Channel 0)
Negative Differential Input Video Data (Channel 0)
Positive Differential Input Video Data (Channel 1)
Negative Differential Input Video Data (Channel 1)
Positive Differential Input Video Data (Channel 2)
Negative Differential Input Video Data (Channel 2)
These six pins receive three pairs of differential,
low voltage swing input pixel data from a digital
graphics transmitter.
Data Frames
The digital interface data is capred in groups of 10 bits each,
called a data frame. During e active data period, each frame is
made up the nine encoded eo dbits and one dc balancing
bit. The data capture bock res this dserially, but out-
puts each frame in pallel 10-biords
Digital Video Clock Inputs
RxC+
Positive Differential Input Video Clock
RxC–
Negative Differential Input Video Clock
These two pins receive the differential, low voltage
swing input pixel clock from a digital graphics
transmitter.
Special Characrs
During periods of horizal or vertical blanking time (when
DE is low)he digital transtter will transmit special characters.
The AD887 wilreceive these characters and use them to set the
video me bndaries and the phase recovery loop for each
channel. e are fospecial characters that can be received.
They are uto idtify the top, bottom, left side, and right side
of each video e. The data receiver can differentiate these
special characters from active data because the special characters
ve a diffnt number of transitions per data frame.
Termination Control
RTERM
Internal Termination Set Pin
This pin is used to set the termination resistance
for all of the digital interface high-speed inputs. To
set, place a resistor of value equal to 10× the desired
input termination resistance between this pin (Pin
53) and ground supply. Typically, the value of this
resistor should be 500 Ω.
ChResynchronization
Outputs
The purpose of the channel resynchronization block is to resyn-
chronize the three data channels to a single internal data clock.
Coming into this block, all three data channels can be on differ-
ent phases of the three times oversampling PLL clock (0°, 120°,
and 240°). This block can resynchronize the channels from a
worst-case skew of one full input period (8.93 ns at 112 MHz).
DE
Data Enable Output
This pin outputs the state of data enable
The AD9887 decodes DE from inco
stream of data. The DE signwill be HIGH d
ing active video and will be OW wre is no
active video.
Data Decoder
Power Supply
The data decoder receives frames of data and sync signals from
the data capture block (in 10-bit parallel words), and decodes
them into groups of eight RGB/YUV bits, two control bits, and
a data enable bit (DE).
VD
Main Power Sup
It should be as ed as possible.
PVD
PLL Power Supply
It shoiet anfiltered as possible.
Outply
VDD
The ata and clock outputs. It can
run at 5 V.
–23–
REV. 0
AD9887
GENERAL TIMING DIAGRAMS (DIGITAL INTERFACE)
TIMING MODE DIAGRAMS (DIGITAL INTERFACE)
80%
80%
INTERNAL
ODCLK
T
ST
20%
20%
DATACK
DE
D
D
LHT
LHT
Figure 28. Digital Output Rise and Fall Time
FIRST
PIXEL
SECOND
PIXEL
THIRD
PIXEL
FOURTH
PIXEL
QE[23:0]
QO[23:0]
T
, R
CIP
CIP
T
, R
CIH
CIH
Figure 32. 1 Pixel per Clok (DATACK Inverted)
T
, R
CIL
CIL
INTERNAL
ODCLK
T
S
Figure 29. Clock Cycle/High/Low Times
DATACK
DE
QE[23:0]
QO[23:0]
R
R
R
X0
X1
X2
V
= 0V
DIFF
FIRST
PIXEL
ECOND
PIXEL
THIRD
PIXEL
FOURTH
PIXEL
V
= 0V
DIFF
T
CCS
gure . 1 Pixels per Clock (DATACK Inverted)
Figure 30. Channel-to-Channel Skew Timing
RNAL
DCLK
DATACK
(INTERNAL)
T
ST
DATACK
DATA OUT
DE
QE[23:0]
QO[23:0]
DATACK
(PIN)
FIRST PIXEL
THIRD PIXEL
tSKEW
Figure 31. DVI Ou
SECOND PIXEL
FOURTH PIXEL
Figure 34. 2 Pixel per Clock
INTERNAL
ODCLK
T
ST
DATACK
DE
FIRST PIXEL
THIRD PIXEL
QE[23:0]
SECOND PIXEL
FOURTH PIXEL
QO[23:0]
Figure 35. 2 Pixels per Clock (DATACK Inverted)
–24–
REV. 0
AD9887
2-Wire Serial Register Map
The AD9887 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is
employed to write and read the Control Registers through the 2-line serial interface port.
Table IX. Control Register Map
Read and
Hex
Address
Write or
Read Only
Default
Value
Register
Name
Bits
Function
00H
RO
7:0
Chip Revision Bits 7 through 4 represent functional revisions to the analog interface.
Bits 3 through 0 represent nonfunctional related revisions.
Revision 0 = 0000 0000
01H
R/W
7:0
01101001
PLL Div MSB This register is for Bits [11:4] of thPLL divider. Larger values mean
the PLL operates at a faster ratehis reger should be loaded first
whenever a change is needed. (s wiive the PLL more time to
lock.) See Note 1.
02H
03H
R/W
R/W
7:4
7:2
1101****
PLL Div LSB Bits [7:4] LSBs of the divider woSNote 1.
1*******
*01*****
VCO/CPMP
Bit 7—Must be set o 1 for per device operation.
Bits [6:5] VCRange. Selects O frequency range. (See PLL
description.
***001**
10000***
10000000
10000000
00100000
10000
Bits [4:2harge mp Current. Varies the current that drives the
low-pass fi. ee PLL scription.)
04H
05H
06H
07H
08H
R/W
R/W
R/W
R/W
R/W
7:3
7:0
7:0
7:0
7:0
Phase Adjust
ADC Clock phadjtment. Larger values mean more delay.
(1 LSB = T/32)
Clamp
Placemen
Pes the Clamsignal an integer number of clock periods after the trail-
ing e of tHsync signal.
Cla
Du
umbef clock periods that the Clamp signal is actively clamping.
Hsyts the number of pixel clocks that HSOUT will remain active.
Pulsew
ain
Controls ADC input range (Contrast) of each respective channel.
Bigger values give less contrast.
09H
0AH
0BH
R/W
R/W
R/W
7:0
7:
7:1
00000
0
GrGain
Blue Gain
Red Offset
Controls dc offset (Brightness) of each respective channel. Bigger
values decrease brightness.
0CH
0DH
0EH
R/W
R/W
R/W
1000*
1000000*
1*******
Green Offset
Blue Offset
Mode
Control 1
Bit 7—Channel Mode. Determines Single Channel or Dual Channel
Output Mode. (Logic 0 = Single Channel Mode, Logic 1 = Dual
Channel Mode.)
*1******
**0*****
***0****
****0***
Bit 6—Output Mode. Determine Interleaved or Parallel Output Mode.
(Logic 0 = Interleaved Mode, Logic 1 = Parallel Mode.)
Bit 5—OUTPHASE. Determines which port outputs the first data byte
after Hsync. (Logic 0 = B Port, Logic 1 = A Port.)
Bit 4—Hsync Output polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync.)
Bit 3—Vsync Output Invert. (Logic 0 = Invert, Logic 1 = No Invert.)
–25–
REV. 0
AD9887
Table IX. Control Register Map (continued)
Register
Read and
Write or
Read Only
Hex
Address
Default
Value
Bits
Name
Function
0FH
R/W
7:0
1*******
*1******
**0*****
PLL and
Bit 7—HSYNC Polarity. Indicates the polarity of incoming HSYNC
Clamp Control signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.)
Bit 6—Coast Polarity. Changes polarity of external COAST signal.
(Logic 0 = Active Low, Logic 1 = Active High.)
Bit 5—Clamp Function. Chooses between HSYNC for Clamp signal
or another external signal to be used for clamping. (Logic 0 = HSYNC,
Logic 1 = Clamp.)
***1****
****0***
Bit 4—Clamp Polarity. Valid only with extnal CLAMP signal. (Logic 0 =
Active Low, Logic 1 selects Active Hig
Bit 3—EXTCLK. Shuts down the PLnd lows the use of an external
clock to drive the part. (Logic = use inal PLLogic 1 = bypass-
ing of the internal PLL.)
*****0**
******0*
*******0
Bit 2—Red Clamp SelecLo0 selects clap to ground. Logic 1
selects clamp to midscale (voltage Pin 120).
Bit 1—Green ClaSelect—Logic 0 ects clamp to ground. Logic 1
selects clamp to idscale voltage at Pin 111).
Bit 0—Blue Cp Sct—Logic 0 selects clamp to ground. Logic 1
selects clamp to ale (vole at Pin 101).
10H
R/W
7:2
0*******
*0******
Mode
Control 2
Bit 7—Clk Inv: Data cutput invert. (Logic 0 = Not Inverted,
Lo1 = Inverted.) (Digital Interface Only.)
Bit 6—x Select: lects either 1 or 2 pixels per clock mode.
gic 0 = pixlock, Logic 1 = 2 pixels/clock.) (Digital Interface
**11****
—Output Drive: Selects between high, medium, and low
drive strength. (Logic 11 or 10 = High, 01 = Medium, and
ow.)
****0***
*****1**
Bit 3—PDO: High Impedance Outputs. (Logic 0 = Normal, Logic
1 = High Impedance.)
Bit 2—Sync Detect (SyncDT) Polarity. This bit sets the polarity
for the SyncDT output pin. (Logic 1 = Active High, Logic 0 =
Active Low.)
11H
RO
7:1
ync Detect/
Active
Bit 7—Analog Interface Hsync Detect. It is set to Logic 1 if Hsync
is present on the analog interface; otherwise it is set to Logic 0.
Interface
Bit 6—Analog Interface Sync-on-Green Detect. It is set to Logic 1
if sync is present on the green video input; otherwise it is set to 0.
Bit 5—Analog Interface Vsync Detect. It is set to Logic 1 if Vsync
is present on the analog interface; otherwise it is set to Logic 0.
Bit 4—Digital Interface Clock Detect. It is set to Logic 1 if the
clock is present on the digital interface; otherwise it is set to Logic 0.
Bit 3—AI: Active Interface. This bit indicates which interface is
active. (Logic 0 = Analog Interface, Logic 1 = Digital Interface.)
Bit 2—AHS: Active Hsync. This bit indicates which analog HSYNC
is being used. (Logic 0 = HSYNC Input Pin, Logic 1 = HSYNC
from Sync-on-Green.)
Bit 1—AVS: Active Vsync. This bit indicates which analog VSYNC
is being used. (Logic 0 = VSYNC input pin, Logic 1 = VSYNC from
sync separator.)
–26–
REV. 0
AD9887
Table IX. Control Register Map (continued)
Default Register
Read and
Write or
Hex
Address Read Only Bits Value
Name
Function
12H
R/W
7:0
0*******
Active
Interface
Bit 7—AIO: Active Interface Override. If set to Logic 1, the user
can select the active interface via Bit 6. If set to Logic 0, the active
interface is selected via Bit 3 in Register 11H.
*0******
Bit 6—AIS: Active Interface Select. Logic 0 selects the analog inter-
face as active. Logic 1 selects the digital interface as active. Note:
The indicated interface will be active only if Bit 7 is set to Logic 1
or if both interfaces are active (Bits 6 or 7 and 4 = Logic 1 in
Register 11H.)
**0*****
***0****
Bit 5—Active Hsync Override. set to Lic 1, the user can select
the Hsync to be used via Bit 4set Logic 0, the active interface
is selected via Bit 2 in Rester 11
Bit 4—Active Hsync ct. Logic 0 ecHsync as the active
sync. Logic 1 selecSynn-Green as he active sync. Note: The
indicated Hsync will be usenly if Bit 5 is set to Logic 1 or if
both syncs aractive (Bits 6, 7 Logic 1 in Register 11H.)
****0***
*****0**
Bit 3—Ace VsynOverride. If set to Logic 1, the user can select
the Vsyno be ed via Bit 2. If set to Logic 0, the active interface
is selected vt 1 in Rister 11H.
Bit 2—Active Vnc lect. Logic 0 selects Raw Vsync as the
output Vsync. Lo1 selects Sync Separated Vsync as the output
nc. Note: The indicated Vsync will be used only if Bit 3 is set
to ic 1.
******0*
*******1
Bit 1—st Select. Logic 0 selects the coast input pin to be used for
PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
0—PWRDN. Full Chip Power-Down, active low. (Logic 0 =
ll Chip Power-Down, Logic 1 = Normal.)
13H
14H
R/W
R/W
7:0
7:
0010000
Sync
ar
Thresd
Sync Separator Threshold—Sets the number of clocks the sync
separator will count to before toggling high or low. This should be
set to some number greater than the maximum Hsync or equaliza-
tion pulsewidth.
*
**0*
Control Bits
Bit 4—Must be set to 1 for proper operation.
Bit 3—Must be set to 0 for proper operation.
Bit 2—Scan Enable. (Logic 0 = Not Enabled, Logic 1 = Enabled.)
Bit 1—Coast Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 6 in Register 0Fh.)
*******0
Bit 0—Hsync Polarity Override. (Logic 0 = Polarity determined by
chip, Logic 1 = Polarity set by Bit 7 in Register 0Fh.)
15H
16H
RO
7:5
7:2
Polarity Status Bit 7—Hsync Input Polarity Status. (Logic 1 = Active High,
Logic 0 = Active Low.)
Bit 6—Vsync Output Polarity Status. (Logic 0 = Active High,
Logic 1 = Active Low.)
Bit 5—Coast Input Polarity Status. (Logic 1 = Active High,
Logic 0 = Active Low.)
R/W
10111***
******1*
Control Bits 2 Bits [7:3]—Sync-On-Green Slicer Threshold
Bit 1—Must be set to 0 for proper operation.
17H
18H
19H
1AH
R/W
R/W
R/W
R/W
7:0
7:0
7:0
7:0
00000000
00000000
00000000
11111111
Pre-Coast
Sets the number of Hsyncs that coast goes active prior to Vsync.
Sets the number of Hsyncs that coast goes active following Vsync.
Must be set to default for proper operation.
Post-Coast
Test Register
Test Register
Must be set to 01000001 for proper operation.
–27–
REV. 0
AD9887
Table IX. Control Register Map (continued)
Register
Read and
Write or
Hex
Default
Value
Address
Read Only
Bits
7:0
Name
Function
1BH
R/W
R/W
00000000
Test Register
4:2:2 Control
Must be set to 00010000 for proper operation.
1CH
7:0
000001**
******1*
*******1
Bits [7:2]—Must be set to 011011** for proper operation.
Bit 1—Must be set to default for proper operation.
Bit 0—Output Format Mode Select
Logic 1 = 4:4:4 mode
Logic 0 = 4:2:2 mode
1DH
1EH
RO
RO
RO
7:0
7:0
7:0
Test Register
Test Register
Test Register
Reserved for future use.
Reserved for future use.
Reserved for future use.
1FH
NOTE
1The AD9887 only updates the PLL divide ratio when the LSBs are written to (Register 02h).
–28–
REV. 0
AD9887
The PLL gives the best jitter performance at high fre-
quencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL actu-
ally operates at a higher frequency but then divides down
the clock rate afterwards. Table X shows the pixel rates
for each VCO range setting. The PLL output divisor is
automatically selected with the VCO range setting.
2-WIRE SERIAL CONTROL REGISTER DETAIL
CHIP IDENTIFICATION
00
7–0 Chip Revision
Bits 7 through 4 represent functional revisions to the
analog interface. Changes in these bits will generally
indicate that software and/or hardware changes will be
required for the chip to work properly. Bits 3 through 0
represent nonfunctional related revisions and are reset to
0000 whenever the MSBs are changed. Changes in these
bits are considered transparent to the user.
Table X. VCO Ranges
VCORNGE
Pixel Rate Range
PLL DIVIDER CONTROL
00
01
10
11
12–35
370
0–110
110–0
01
7–0 PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
The PLL derives a pixel clock from the incoming Hsync
signal. The pixel clock frequency is then divided by an
integer value, such that the output is phase-locked to
Hsync. This PLLDIV value determines the number of
pixel times (pixels plus horizontal blanking overhead) per
line. This is typically 20% to 30% more than the number
of active pixels in the display.
The power-up efault valis = 0
03
4–2 CURECharge PuCurrent
Three bits that eslish the current driving the loop filter
in thlock generat
TabXI. Charge Pump Currents
The 12-bit value of the PLL divider supports divide ratios
from 221 to 4095. The higher the value loaded in this
register, the higher the resulting clock frequency with
respect to a fixed Hsync frequency.
CUENT
Current (A)
000
001
010
0
00
101
110
111
50
100
150
250
350
500
750
1500
VESA has established some standard timing specifications,
which will assist in determining the value for PL
a function of horizontal and vertical display res
and frame rate (Table VII).
However, many computer systems do not confor
cisely to the recommendations, and tse numbers s
be used only as a guide. The displasystem ufacturer
should provide automatic or manuafor omizing
PLLDIV. An incorrectly set PLLDIV will usually oduce
one or more vertical noise he displgreater
the error, the greater the s produced.
See Table VII for the recommended CURRENT settings.
The power-up default value is CURRENT = 001.
04
7–3 Clock Phase Adjust
A five-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25° shift
in sampling phase.
The power-up default V is 1693
(PLLDIVM = 69h, PLLD).
The power-up default value is 16.
The AD988full e ratio only when the
LSBs are co this register by itself will not
trigger an
CLAMP TIMING
05 7–0 Clamp Placement
02
7–4 PLL DiSBs
The four least signicant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
An eight-bit register that sets the position of the internally
generated clamp.
When EXTCLMP = 0, a clamp signal is generated inter-
nally, at a position established by the clamp placement and
for a duration set by the clamp duration. Clamping is
started (Clamp Placement) pixel periods after the trailing
edge of Hsync. The clamp placement may be programmed
to any value between 1 and 255. A value of 0 is not
supported.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9887 updates the full divide ratio only when this
register is written.
CLOCK GENERATOR CONTROL
03
7 TEST Set to One
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
03
6–5 VCO Range Select
Two bits that establish the operating range of the clock
generator.
When EXTCLMP = 1, this register is ignored.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
–29–
REV. 0
AD9887
06
7–0 Clamp Duration
0C
7–1 Green Channel Offset Adjust
An 8-bit register that sets the duration of the internally
generated clamp.
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
When EXTCLMP = 0, a clamp signal is generated inter-
nally, at a position established by the clamp placement
and for a duration set by the clamp duration. Clamping is
started (clamp placement) pixel periods after the trailing
edge of Hsync, and continues for (clamp duration) pixel
periods. The clamp duration may be programmed to any
value between 1 and 255. A value of 0 is not supported.
0D 7–1 Blue Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
MODE CONTROL 1
0E
7
Channel Mode
A bit that determines whether all pixels are presented to a
single port (A), or alternating pixels are demultiplexed to
Ports A and B.
For the best results, the clamp duration should be set to
include the majority of the black reference signal time that
follows the Hsync signal trailing edge. Insufficient clamp-
ing time can produce brightness changes at the top of the
screen, and a slow recovery from large changes in the
Average Picture Level (APL), or brightness.
Table XII. Chael ModSettings
DEMUX
Funcion
0
1
Aata Goes tor
lteate Pixels Go Port A and Port B
When EXTCLMP = 1, this register is ignored.
Hsync Pulsewidth
07 7–0 Hsync Output Pulsewidth
When DEUX = 0, Port outputs are in a high-impedance
state. e maximum data rte for single port mode is
100 Hz. Thiming diagrams show the effects of this option.
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by the
internally generated, phase-adjusted PLL feedback clock.
The AD9887 then counts a number of pixel clocks equal
to the value in this register. This triggers the trailing edge
of the Hsync output, which is also phase-adjusted.
The poup defavalue is 1.
0E
6
Output od
A bit that demines whether all pixels are presented to
Port A and Port B simultaneously on every second
ATArising edge, or alternately on port A and Port B
ocessive DATACK rising edges.
INPUT GAIN
08
7–0 Red Channel Gain Adjust
Table XIII. Output Mode Settings
An 8-bit word that sets the gain of the RED chan
The AD9887 can accommodate input signwith a
full-scale range of between 0.5 V and 1.5 p-p. Setting
REDGAIN to 255 corresponds to an inrange V.
A REDGAIN of 0 establishes an input raf 0.5 V
Note that INCREASING REDGresults in the pire
having LESS CONTRAST (t signal fewer
of the available converter ce 3.
PARALLEL
Function
0
1
Data Is Interleaved
Data Is Simultaneous On Every Other
Data Clock
When in single port mode (DEMUX = 0), this bit is ig-
nored. The timing diagrams show the effects of this option.
09
7–0 Green Channel Gain A
An 8-bit word that sehe gain EEN channel.
See REDGAIN (
The power-up default value is PARALLEL = 1.
0E
5
Output Port Phase
One bit that determines whether even pixels or odd pixels
go to Port A.
0A
7–0 Blue Chat
An 8-bit word tof the BLUE channel.
See REDGAIN (
Table XIV. Output Port Phase Settings
INPUT OFFSET
0B 7–1 Red Channel Offset Adjust
OUTPHASE
First Pixel After Hsync
0
1
Port B
Port A
A 7-bit offset binary word that sets the dc offset of the RED
channel. One LSB of offset adjustment equals approximately
one LSB change in the ADC offset. Therefore, the absolute
magnitude of the offset adjustment scales as the gain of the
channel is changed. A nominal setting of 63 results in the
channel nominally clamping the back porch (during the
clamping interval) to Code 00. An offset setting of 127
results in the channel clamping to Code 63 of the ADC. An
offset setting of 0 clamps to code –63 (off the bottom of
the range). Increasing the value of Red Offset DECREASES
the brightness of the channel.
In normal operation (OUTPHASE = 1), when operating
in dual-port output mode (DEMUX = 1), the first sample
after the Hsync leading edge is presented at Port A. Every
subsequent ODD sample appears at Port A. All EVEN
samples go to Port B.
When OUTPHASE = 0, these ports are reversed and the
first sample goes to Port B.
–30–
REV. 0
AD9887
When DEMUX = 0, this bit is ignored as data always
comes out of only Port A.
Active LOW means that the clock generator will ignore Hsync
inputs when COAST is LOW, and continue operating at the
same nominal frequency until COAST goes HIGH.
0E
4
HSYNC Output Polarity
One bit that determines the polarity of the HSYNC out-
put and the SOG output. Table XV shows the effect of
this option. SYNC indicates the logic state of the sync pulse.
Active HIGH means that the clock generator will ignore
Hsync inputs when COAST is HIGH, and continue operat-
ing at the same nominal frequency until COAST goes LOW.
This function needs to be used along with the COAST
polarity override bit (Register 14, Bit 1).
Table XV. HSYNC Output Polarity Settings
The power-up default value is CSTPOL = 1.
Setting
SYNC
0F
0F
0F
5 Clamp Input Signal Source
A bit that determines the source of clamp timing.
0
1
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
The default setting for this register is 1. (This option
works on both the analog and digital interfaces.)
Table XIX. Clamp put Sigl Source Settings
EXTCLMP
Fun
0E
3
VSYNC Output Invert
0
1
Internalleated Clamp
Externally-Povided Clamp Signal
One bit that inverts the polarity of the VSYNC output.
Table XVI shows the effect of this option.
A 0 ables the clatiming circuitry controlled by
CPLACE and CLDUR. The clamp position and dura-
n is cnted from the leading edge of Hsync.
Table XVI. VSYNC Output Polarity Settings
Setting
VSYNC Output
A ables thexternal CLAMP input pin. The three
chans arclamped when the CLAMP signal is
active. e polarity of CLAMP is determined by the
CLAMPOL bit.
0
1
Invert
No Invert
The default setting for this register is 1. (This option
works on both the analog and digital interfaces.)
Thpower-up default value is EXTCLMP = 0.
0F
7
HSYNC Input Polarity
CLAMP Input Signal Polarity
A bit that must be set to indicate the polarity of t
signal that is applied to the PLL HSYNC inpu
A bit that determines the polarity of the externally pro-
vided CLAMP signal.
Table XVII. HSYNC Input Polarity ttgs
Table XX. CLAMP Input Signal Polarity Settings
HSPOL
Function
EXTCLMP
Function
0
1
Active LOW
Active H
0
1
Active LOW
Active HIGH
Active LOW is the traoing Hsync pulse.
All timing is based on the of Hsync, which is
the FALLING The rishas no effect.
A Logic 0 means that the circuit will clamp when CLAMP
is HIGH, and it will pass the signal to the ADC when
CLAMP is LOW.
Active HIGom thtraditional Hsync, with a
positive-goians that timing will be based on
the leading which is now the RISING edge.
A Logic 1 means that the circuit will clamp when CLAMP
is LOW, and it will pass the signal to the ADC when
CLAMP is HIGH.
The device will if this bit is set incorrectly, but the
internally generated clamp position, as established by
CLPOS, will not be placed as expected, which may gener-
ate clamping errors.
The power-up default value is CLAMPOL = 1.
3
External Clock Select
A bit that determines the source of the pixel clock.
The power-up default value is HSPOL = 1.
Table XXI. External Clock Select Settings
0F
6 COAST Input Polarity
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
EXTCLK
Function
0
1
Internally Generated Clock
Externally Provided Clock Signal
Table XVIII. COAST Input Polarity Settings
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided Hsync.
CSTPOL
Function
0
1
Active LOW
Active HIGH
–31–
REV. 0
AD9887
A Logic 1 enables the external CKEXT input pin. In this
mode, the PLL Divide Ratio (PLLDIV) is ignored. The
clock phase adjust (PHASE) is still functional.
of a single port (even port only), at the full data rate or
out of two ports (both even and odd ports), at one-half
the full data rate per port. A Logic 0 selects 1 pixel per
clock (even port only). A Logic 1 selects 2 pixels per clock
(both ports). See the Digital Interface Timing Diagrams,
Figures 29 to 32, for a visual representation of this function.
Note: This function operates exactly like the DEMUX
function on the analog interface.
The power-up default value is EXTCLK = 0.
0F
2
Red Clamp Select
A bit that determines whether the red channel is clamped
to ground or to midscale. For RGB video, all three chan-
nels are referenced to ground. For YcbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 118, RCLAMPV.
Table XXVI. Pix Select Settings
Pix Select
Function
0
1
1 Pixel per ock
2 Pixels r Clock
Table XXII. Red Clamp Select Settings
Clamp
Function
The default for this register 1 pixel pclock.
0
1
Clamp to Ground
Clamp to Midscale (Pin 118)
10
5, 4 Output Dri
These two bits lehe drive strth for the high-speed
digital outputs (all doutput and clock output pins).
Higher dre strength ress in faster rise/fall times and in
general akes it easier to capure data. Lower drive strength
resuin slor rise/fall times and helps to reduce EMI
and dtagenerad power supply noise. The exact
timing sficatiofor each of these modes are specified
in Table VI
The default setting for this register is 0.
1 Green Clamp Select
A bit that determines whether the green channel is clamped
to ground or to midscale.
0F
Table XXIII. Green Clamp Select Settings
Clamp
Function
Table XVII. Output Drive Strength Settings
0
1
Clamp to Ground
Clamp to Midscale (Pin 109)
B
Bit 4
Result
1
1
0
1
0
X
High Drive Strength
Medium Drive Strength
Low Drive Strength
The default setting for this register is 0.
0 Blue Clamp Select
A bit that determines whether the blue cnnel is clampe
to ground or to midscale.
0F
The default for this register is 11, high drive strength. (This
option works on both the analog and digital interfaces.)
Table XXIV. Blue Clamp Select Settings
10
3 PDO—Power-Down Outputs
A bit that can put the outputs in a high impedance mode.
This applies only to the 48 data output pins and the two
data clock output pins.
Clamp
Function
0
1
Clamp to G
Clamp to Mid9)
Table XXVIII. Power-Down Output Settings
The default settster is 0.
CKINV
Function
MODE CONTROL 2
10 Clk Inv Data Ock Invert
0
1
Normal Operation
Three-State
7
A control bit for the inversion of the output data clocks,
(Pins 134, 135). This function works only for the digital
interface. When not inverted, data is output on the rising
edge of the data clock. See timing diagrams to see how
this affects timing.
The default for this register is 0. (This option works on
both the analog and digital interfaces.)
10
2
Sync Detect Polarity
This pin controls the polarity of the Sync Detect output
pin (Pin 136).
Table XXV. Clock Output Invert Settings
Table XXIX. Sync Detect Polarity Settings
Clk Inv
Function
0
1
Not Inverted
Inverted
Polarity
Function
0
1
Activity = Logic 1 Output
Activity = Logic 0 Output
The default for this register is 0, not inverted.
10 Pix Select
6
The default for this register is 0. (This option works on
both the analog and digital interfaces.)
This bit selects either 1 or 2 pixels per clock mode for the
digital interface. It determines whether the data comes out
–32–
REV. 0
AD9887
SYNC DETECTION AND CONTROL
11 Analog Interface HSYNC Detect
Digital interface detection is determined by Bit 4 in this
register. If both interfaces are detected, the user can
determine which has priority via Bit 6 in register 12H.
The user can override this function via Bit 7 in Register 12H.
If the override bit is set to Logic 1, then this bit will be
forced to whatever the state of Bit 6 in Register 12H is set to.
7
This bit is used to indicate when activity is detected on
the HSYNC input pin (Pin 82). If HSYNC is held high or
low, activity will not be detected.
Table XXX. HSYNC Detection Results
Table XXXIV. Active Interface Results
Bits 7, 6,
Detect
Function
0
1
No Activity Detected
Activity Detected
or 5
Bit 4
(Digital
(Analog
Detection) Detection) Override
AI
Figure 38 shows where this function is implemented.
6 Analog Interface Sync-on-Green Detect
0
0
0
Soft
11
Power-Down
(Seek Mode)
1
This bit is used to indicate when sync activity is detected
on the Sync-on-Green input pin (Pin 108).
0
1
1
X
1
X
0
0
1
0
Table XXXI. Sync-on-Green Detection Results
Bit 6 in 12H
Bit 6 in 12H
Detect
Function
A0 means Analog Interfae.
= 1 meDigital Interface.
ovde bit is in Register 12H, Bit 7.
0
1
No Activity Detected
Activity Detected
Figure 38 shows where this function is implemented.
11
2
AS—Ace HSYNC
This bsed to determine which HSYNC should be
used for the analog interface, the HSYNC input or Sync-
on-Geen. It uses Bits 7 and 6 in this register for inputs
in etermining which should be active. Similar to the previ-
us bit, if both HSYNC and SOG are detected the user
can determine which has priority via Bit 4 in Register
12H. The user can override this function via Bit 5 in
Register 12H. If the override bit is set to Logic 1, this
bit will be forced to whatever the state of Bit 4 in Register
12H is set to.
Warning: If no sync is present on the green video input,
normal video may still trigger activity.
11
11
11
5
Analog Interface VSYNC Detect
This bit is used to indicate when activity is detec
the VSYNC input pin (Pin 81). If VSYNC is h
low, activity will not be detected.
Table XXXII. VSYNC Detection Rus
Detect
Function
0
1
No Activity Detected
Activity d
Table XXXV. Active HSYNC Results
Bit 7
(HSYNC
Detect)
Bit 6
(SOG
Detect)
Figure 38 shows where plemented.
Digital Interface Cloc
Override
AHS
4
This bit is useate wivity is detected on
the digital input.
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
Bit 4 in 12H
1
0
Bit 4 in 12H
Bit 4 in 12H
Table XXXIIIace Clock Detection Results
Detect
nction
AHS = 0 means use the HSYNC pin input for HSYNC.
AHS = 1 means use the SOG pin input for HSYNC.
The override bit is in Register 12H, Bit 5.
0
1
No Activity Detected
Activity Detected
11
1
AVS—Active VSYNC
The sync processing block diagram shows where this
function is implemented.
This bit is used to determine which VSYNC should be
used for the analog interface; the VSYNC input or output
from the sync separator. If both VSYNC and composite
SOG are detected, VSYNC will be selected. The user can
override this function via Bit 3 in Register 12H. If the
override bit is set to Logic 1, this bit will be forced to what-
ever the state of Bit 2 in Register 12H is set to.
3
Active Interface
This bit is used to indicate which interface should be
active, analog, or digital. It checks for activity on the
analog interface and for activity on the digital interface,
then determines which should be active according to
Table XXXIV. Specifically, analog interface detection
is determined by OR-ing Bits 7, 6, and 5 in this register.
–33–
REV. 0
AD9887
Table XXXVI. Active VSYNC Results
Table XL. Active HSYNC Select Settings
Bit 5
Select
Result
(VSYNC
Detect)
0
1
HSYNC Input
Sync-on-Green Input
Override
AVS
0
1
X
0
0
1
0
1
The default for this register is 0.
3 Active VSYNC Override
Bit 2 in 12H
12
This bit is used to override the automatic VSYNC selection
(Bit 1 in Register 11H). To override, set this bit to Logic 1.
When overriding, the active interface is set via Bit 2 in
this register.
AVS = 1 means Sync separator.
AVS = 0 means VSYNC input.
The override bit is in Register 12H, Bit 3.
12
12
12
12
7
AIO—Active Interface Override
This bit is used to override the automatic interface selec-
tion (Bit 3 in Register 11H). To override, set this bit to
Logic 1. When overriding, the active interface is set via
Bit 6 in this register.
Table XLI. Active VYNC Orride Settings
Override
Result
0
1
Auetermines Ave VSYNC
ver, Bit 2 Deternes the Active VSYNC
Table XXXVII. Active Interface Override Settings
AIO
Result
The defafor this regisis 0.
2 Ave VSYC Select
This t is ud to select the active VSYNC when the
overridis set (B3).
0
1
Autodetermines the Active Interface
Override, Bit 6 Determines the Active Interface
12
The default for this register is 0.
AIS—Active Interface Select
Table XLII. tive VSYNC Select Settings
6
This bit is used under two conditions. It is used to select
the active interface when the override bit is set (Bit 7).
Alternately, it is used to determine the active interface
when not overriding but both interfaces are detecte
Select
Result
0
1
VSYNC Input
Sync Separator Output
Table XXXVIII. Active Interface Select Settings
The default for this register is 0.
1 COAST Select
This bit is used to select the active COAST source. The
choices are the COAST input pin or VSYNC. If VSYNC
is selected, the additional decision of using the VSYNC
input pin or the output from the sync separator needs to
be made (Bits 3, 2).
2
AIS
Result
0
1
Analog Interface
Digital Interface
The default for this register i
Active Hsync Override
5
Table XLIII. COAST Select Settings
This bit is used to override the sync selection
(Bit 2 in Register 1overrthis bit to Logic
1. When overridHsyns set via Bit 4 in
this register.
Select
Result
0
1
COAST Input Pin
VSYNC (See Above Text)
Table XXXIync Override Settings
The default for this register is 0.
0 PWRDN
This bit is used to put the chip in full power-down. This
powers down both interfaces. See the section on Power
Management for details of which blocks are actually
powered down. Note, the chip will be unable to detect
incoming activity while fully powered-down.
Override
Result
12
0
1
Autodetermines the Active Interface
Override, Bit 4 Determines the Active Interface
The default for this register is 0.
Active Hsync Select
4
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 5). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
Table XLIV. Power-Down Settings
Select
Result
0
1
Power-Down
Normal Operation
The default for this register is 1.
–34–
REV. 0
AD9887
DIGITAL CONTROL
13 7:0 Sync Separator Threshold
Table XLVIII. Detected HSYNC Input Polarity Status
Hsync Polarity
Status
This register is used to set the responsiveness of the sync
separator. It sets how many pixel clock pulses the sync
separator must count to before toggling high or low. It
works like a low-pass filter to ignore Hsync pulses in order
to extract the Vsync signal. This register should be set to
some number greater than the maximum Hsync pulsewidth.
Result
0
1
Hsync Polarity is Negative.
Hsync Polarity is Positive.
15
15
16
6
VSYNC Output Polarity Status
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the polarity
of the Vsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 38).
The default for this register is 32.
CONTROL BITS
14
2
Scan Enable
This register is used to enable the scan function. When
enabled, data can be loaded into the AD9887 outputs
serially with the scan function. The scan function utilizes
three pins (SCANIN, SCANOUT, and SCANCLK). These
pins are described in Table I.
Table XLIX. DetecteVSYNC Input Polarity Status
Vsync Polarity
Status
Res
0
1
Vsync Pity is Active Low.
Vsync Polarity is Active High.
Table XLV. Scan Enable Settings
Scan Enable
Result
5
oast Input PolarStatus
his bit ports the status of the coast input polarity
ectn circuit. It can be used to determine the polar-
ity he coasnput. The detection circuit’s location is
shown thSync Processing Block Diagram (Figure 38).
0
1
Scan Function Disabled
Scan Function Enabled
The default for scan enable is 0 (disabled).
1 Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going
the PLL.
14
14
15
Table L. Detected Coast Input Polarity Status
ast Polarity
Status
Result
0
1
Coast Polarity is Negative.
Coast Polarity is Positive.
Table XLVI. Coast Input Polarity Override S
Override Bit
Result
7–3 Sync-on-Green Slicer Threshold
0
1
Coast Polarity Dermbhip
Coast Polarity Determined by er
This register allows the comparator threshold of the
Sync-on-Green slicer to be adjusted. This register adjusts
the comparator threshold in steps of 10 mV. A setting of zero
results in a 330 mV threshold. The setting of 31 results in
a 10 mV threshold.
The default for coast porride is polarity
determined by chip).
0
HSYNC Input Polarit
The default setting is 23 and corresponds to a threshold
value of 70 mV.
This register is overrnternal circuitry that
determines f the ync signal going into
the PLL.
17
18
7–0 Pre-Coast
This register allows the Coast signal to be applied prior
to the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
Table XLVIIput Polarity Override Settings
Override Bit
Result
The default is 0.
0
1
Hsync Polarity Determined by Chip
Hsync Polarity Determined by User
7–0 Post-Coast
This register allows the coast signal to be applied follow-
ing to the Vsync signal. This is necessary in cases where
post-equalization pulses are present. The step size for this
control is one Hsync period.
The default for Hsync polarity override is 0 (polarity
determined by chip).
7
HSYNC Input Polarity Status
This bit reports the status of the Hsync input polarity
detection circuit. It can be used to determine the polarity
of the Hsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 38).
The default is 0.
19
7–0 Test Register
Must be set to default.
1A
7–0 Test Register
Must be set to 41H for proper operation.
–35–
REV. 0
AD9887
1B
1C
1C
7–0 Test Register
Must be set to 10H for proper operation.
eighth bit). The R/W bit indicates the direction of data transfer,
read from (1) or write to (0) the slave device. If the transmitted
slave address matches the address of the device (set by the state of
the SA1-0 input pins in Table LIII, the AD9887 acknowledges by
bringing SDA LOW on the 9th SCL pulse. If the addresses do not
match, the AD9887 does not acknowledge.
7–2 Test Bits
Must be set to 6FH for proper operation.
1
Output Format Mode Select
A bit that configures the output data in 4:2:2 mode. This
mode can be used to reduce the number of data lines used
from 24 down to 16 for applications using YUV, YCbCr,
or YPbPr graphics signals. A timing diagram for this mode is
shown on page 22. Recommended input and output con-
figurations are shown in Table LI. In 4:2:2 mode, the red
and blue channels can be interchanged to help satisfy
board layout or timing requirements, but the green channel
must be configured for Y.
Table LIII. Serial Port Addresses
Bit 7
A6
(MSB)
Bit 6 Bit 5
Bit 4
A3
Bit 3
A2
Bit 2
A1
Bit 1
A0
A5
A4
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
0
1
Table LI. 4:2:2 Output Mode Select
Data Transfer via Senterface
For each byte of datread written, the MSB is the first bit of
the sequence.
Select
Output Mode
1
1
4:4:4
4:2:2
If the AD988does not acknowlege the master device during a
write sequce, thDA remains HIGH so the master can
generate a stsial. If the master device does not acknowledge
the AD9887 dg a resequence, the AD9887 interprets this
as “end of data.” hSDA remains HIGH so the master can
erate a stop signal.
Table LII. 4:2:2 Input/Output Configuration
Input
Output
Format
Channel
Connection
Red
Green
Blue
V
Y
U
U/V
Y
Wrig data to pecific control registers of the AD9887 requires
hat thbiddress of the control register of interest be written
r the sve address has been established. This control register
ess is the base address for subsequent write operations. The
address autoincrements by one for each byte of data written
r the data byte intended for the base address. If more bytes
are transferred than there are available addresses, the address will
not increment and remain at its maximum value of 1Dh. Any base
address higher than 1Dh will not produce an acknowledge signal.
High Impedance
1C
1–0 Test Bits
Must be set to default.
2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface control interface is prUp to ur
AD9887 devices may be connected to the 2-wire serial intece,
with each device having a unique ad
Data is read from the control registers of the AD9887 in a similar
manner. Reading requires two data transfer operations:
The 2-wire serial interface compL) and a bidi-
rectional data (SDA) pin. The Ananterface acts
as a slave for receiving and transmitver the serial
interface. When the seriis noe, the logic levels
on SCL and SDA are external pull-up resistors.
The base address must be written with the R/W bit of the slave
address byte LOW to set up a sequential read operation.
Reading (the R/W bit of the slave address byte HIGH) begins at
the previously established base address. The address of the read
register autoincrements after each byte is transferred.
Data received or tranDA line must be stable for
the duration of the positpulse. Data on SDA must
change only when SCL is LSDA changes state while SCL
is HIGH, the serial interface interprets that action as a start or
stop sequence.
To terminate a read/write sequence to the AD9887, a stop sig-
nal must be sent. A stop signal comprises a LOW-to-HIGH
transition of SDA while SCL is HIGH.
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first generat-
ing a stop signal to terminate the current communication. This
is used to change the mode of communication (read, write)
between the slave and master without releasing the serial inter-
face lines.
There are five components to serial bus operation:
• Start Signal
• Slave Address Byte
• Base Register Address Byte
• Data Byte to Read or Write
• Stop Signal
Serial Interface Read/Write Examples
Write to one control register
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
When the serial interface is inactive (SCL and SDA are HIGH)
communications are initiated by sending a start signal. The start
signal is a HIGH-to-LOW transition on SDA while SCL is
HIGH. This signal alerts all slaved devices that a data transfer
sequence is coming.
➥Data byte to base address
➥Stop signal
The first eight bits of data transferred after a start signal comprising
a 7-bit slave address (the first seven bits) and a single R/W bit (the
–36–
REV. 0
AD9887
SDA
SCL
t
BUFF
t
t
DSU
DHO
t
STOSU
t
STASU
t
STAH
t
DAL
t
DAH
Figure 36. Serial Port Read/Write Timing
Write to four consecutive control registers
➥Start signal
➥Slave Address byte (R/W bit = LOW)
THEORY OF OPERATION (SYNC PROCESSING)
This section is devoted to the bic operation of the sync process-
ing engine (refer to Figure 37 ync Pressing Block Diagram).
➥Base Address byte
Sync Slicer
➥Data byte to base address
➥Data byte to (base address + 1)
➥Data byte to (base address + 2)
➥Data byte to (base address + 3)
➥Stop signal
The purpose of the syc slicer extrathe sync signal from
the green graphics nnel. A syngl is not present on all
graphics systemonlose with “sc-on-green.” The sync
signal is extracted from green channel in a two step process.
First, the G input is claed to its negative peak (typically
0.3 V bow the lack level). Next, the signal goes to a compara-
tor wa trier level that is 0.15 V above the clamped level.
The “slisync is tically a composite sync signal containing
both Hsync nd Vnc.
Read from one control register
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Start signal
Sync Separato
➥Slave Address byte (R/W bit = HIGH)
➥Data byte from base address
➥Stop signal
A sync separator extracts the Vsync signal from a composite
c signIt does this through a low-pass filter-like or integrator-
like ation. It works on the idea that the Vsync signal stays
active for a much longer time than the Hsync signal, so it rejects
any signal shorter than a threshold value, which is somewhere
between an Hsync pulsewidth and a Vsync pulsewidth.
Read from four consecutive control registers
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Start signal
The sync separator on the AD9887 is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.) The basic idea is that the counter counts
up when Hsync pulses are present. But since Hsync pulses are
relatively short in width, the counter only reaches a value of N
before the pulse ends. It then starts counting down eventually
reaching 0 before the next Hsync pulse arrives. The specific
value of N will vary for different video modes, but will always be
less than 255. For example with a 1 µs width Hsync, the counter
will only reach 5 (1 µs/200 ns = 5). Now, when Vsync is present
on the composite sync the counter will also count up. However,
since the Vsync signal is much longer, it will count to a higher
number M. For most video modes, M will be at least 255. So,
Vsync can be detected on the composite sync signal by detecting
when the counter counts to higher than N. The specific count
that triggers detection (T) can be programmed through the
serial register (0fh).
➥Slave Address byte (R/W bit = HIG
➥Data byte from base address
➥Data byte from (base addres
➥Data byte from (base add
➥Data byte from (base a
➥Stop signal
SDA
BIT 7 BIT BIT T 2
BIT 1 BIT 0
ACK
SCL
Figure 37. Serial erface—Typical Byte Transfer
Table LIV. Control of the Sync Block Muxes via the
Serial Register
Control
Bit
Once Vsync has been detected, there is a similar process to detect
when it goes inactive. At detection, the counter first resets to 0,
then starts counting up when Vsync goes away. Similar to the
previous case, it will detect the absence of Vsync when the
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is detected to
be absent, the counter resets to 0 and begins the cycle again.
Mux
Nos.
Serial Bus
Control Bit State
Result
1 and 2
12H: Bit 4
12H: Bit 1
12H: Bit 2
0
1
0
1
0
1
0
1
Pass Hsync
Pass Sync-on-Green
Pass Coast
Pass Vsync
Pass Vsync
Pass Sync Separator Signal
Pass Digital Interface Signals
Pass Analog Interface Signals
3
4
5, 6, and 7 11H: Bit 3
–37–
REV. 0
AD9887
ACTIVITY
DETECT
SYNC STRIPPER
SYNC SEPARATOR
INTEGRATOR
NEGATIVE PEAK
CLAMP
COMP
SYNC
VSYNC
1/S
SOG
MUX 1
HSYNC IN
SOG OUT
PLL
ACTIVITY
DETECT
POLARITY
DETECT
HSYNC OUT
PIXEL OCK
HSYNC
HSYNC OUT
CLOCK
GENERATOR
MUX 2
MUX 3
COAST
COAST
POLARITY
DETECT
9887
VSYNC IN
VSYNC OUT
ACTIVITY
DETECT
POLARITY
DETECT
MUX 4
Figure 38. Sync Processing lock Diram
PCB LAYOUT RECOMMENDATIONS
placig a series ferrite bead prior to the 75 Ω termination
or is helpful in filtering out excess noise. Specifically, the
used was the # 2508051217Z0 from Fair-Rite, but each
plication may work best with a different bead value. Alternately,
placing a 100 Ω to 120 Ω resistor between the 75 Ω termination
resistor and the input coupling capacitor can also be beneficial.
The AD9887 is a high-performance, high-speed analog d
As such, to get the maximum performance out of the pa
important to have a well laid-out board. The follois a g
for designing a board using the AD9887.
Analog Interface Inputs
Using the following layout techniques on the graphics inpus
extremely important:
Digital Interface Inputs
Each differential input pair (RXO+, RXO–, RXC+, RXC–, etc.)
should be routed together using 50 Ω strip line routing tech-
niques and should be kept as short as possible. No other
components should be placed on these inputs; for example, no
clamping diodes. Every effort should also be made to route
these signals on a single layer (component layer) with no vias.
Minimize the trace length runnincs inputs. This
is accomplished by placing the As possible to
the graphics VGA connector. Long ingths are unde-
sirable because they will ore nm the board and
other external sources
Power Supply Bypassing
Place the 75 Ω termins close to the AD9887
chip as possible. Any alength between the termi-
nation resistors and the ihe AD9887 increases the
magnitude of reflections, which will corrupt the graphics signal.
It is recommended to bypass each power supply pin with a
0.1 µF capacitor. The exception is in the case where two or
more supply pins are adjacent to each other. For these group-
ings of powers/grounds, it is only necessary to have one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the AD9887,
as that interposes resistive vias in the path.
Use 75 Ω matched impedance traces. Trace impedances other
than 75 Ω will also increase the chance of reflections.
The AD9887 has very high input bandwidth, (330 MHz). While
this is desirable for acquiring a high resolution PC graphics
signal with fast edges, it means that it will also capture any high
frequency noise present. Therefore, it is important to reduce the
amount of noise that gets coupled to the inputs. Avoid running
any digital traces near the analog inputs.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make the
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
Due to the high bandwidth of the AD9887, sometimes low-pass
filtering the analog inputs can help to reduce noise. (For many
applications, filtering is unnecessary.) Experiments have shown
–38–
REV. 0
AD9887
It is particularly important to maintain low noise and good
stability of PVD (the clock generator supply). Abrupt changes in
PVD can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful attention
to regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog cir-
cuitry groups (VD and PVD).
PLL
Place the PLL loop filter components as close to the FILT pin
as possible.
Do not place any digital or other high-frequency traces near
these components.
Use the values suggested in the data sheet with 10% tolerances
or less.
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by regu-
lating the analog supply, or at least PVD, from a different, cleaner
power source (for example, from a 12 V supply).
Outputs (Both Data and Clocks)
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, which require
more current that causes more internal digital noise.
Shorter traces reduce the possility of reflections.
Adding a series resistor of ve 50 Ω00 Ω can suppress reflec-
tions, reduce EMI, and reduthcurrent spikes inside of the
AD9887. If series resisrs are uplace em as close to the
AD9887 pins as pble (try not advias or extra length to
the output trace n orto get the rsistors closer).
It is also recommended to use a single ground plane for the
entire board. Experience has repeatedly shown that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller, and long ground loops can result.
If possible, mit the capance that each of the digital outputs
drives to ss than 10 pF. Tcan easily be accomplished by
keepintraces srt and by connecting the outputs to only one
deviceoadg the outputs with excessive capacitance will
increase turrent nsients inside of the AD9887 creating
more digital ise n its power supplies.
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommended to at least place a single ground
plane under the AD9887. The location of the split should be at
the receiver of the digital outputs. For this case it is even more
important to place components wisely because the current loops
will be much longer (current takes the path of least resistance).
An example of a current loop:
Digital Inputs
he digital puts on the AD9887 were designed to work with
3V sials.
Any oise that gets onto the Hsync input trace will add jitter to
he system. Therefore, minimize the trace length and do not run
any digital or other high-frequency traces near it.
P
LA
Voltage Reference
Bypass with a 0.1 µF capacitor. Place as close to the AD9887
pin as possible. Make the ground connection as short as possible.
REFOUT is easily connected to REFIN with a short trace. Avoid
making this trace any longer than it needs to be.
When using an external reference, the REFOUT output, while
unused, still needs to be bypassed with a 0.1 µF capacitor in
order to avoid ringing.
Figure 39. Example nt Loop
–39–
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AD9887
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
160-Lead MQFP
(S-160)
1.238 (31.45)
1.228 (31.20) SQ
1.219 (30.95)
1.106 (28.10)
1.102 (28.00) SQ
1.098 (27.90)
0.160 (4.07)
MAX
0.041 (1.03)
0.035 (0.88)
0.029 (0.73)
120
121
81
80
0.998
(25.3
BSQ
TOP VIEW
(PINS DOWN)
SEATING
PLANE
PIN 1
0.004 (0.10)
MAX
4
4
160
1
0.010 (0.25)
MIN
0.026 (0.65)
0.015 (0.3
0.012 (0.30) WIDTH
0.009 (0.22)
BSC
*
0.145 (3.67)
0.135 (3.42)
0.125 (3.17)
LEAD PITCH
*THE ACTUAL POSITION OF EACH LEAD WITHIN 0.0047 (0.12) FRM ITS
IDEAL POSITION WHEN MEASURED IN THATERAL DIRECON.
CENTER FIGURES ARE TYPICAL UNLESS ORWISE NO
CONTROLLING DIMENSIONS ALLIMETEINCH ENSIONS
ARE ROUNDED-OFF MILLIMENTS ERENCE
ONLY AND ARE NOT APPE IN DE.
–40–
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相关型号：
AD9887AKSZ170
IC SPECIALTY CONSUMER CIRCUIT, PQFP160, LEAD FREE, PLASTIC, MS-022DD-1, MQFP-160, Consumer IC:Other
ADI
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