AD9942BBCZRL [ADI]
Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core; 双通道， 14位CCD信号处理器具有精密Timing⑩核心
| 型号： | AD9942BBCZRL |
| 厂家： | 
ADI |
| 描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 文件： | 总36页 (文件大小：649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual-Channel, 14-Bit CCD Signal Processor
with Precision Timing™ Core
AD9942
FEATURES
GENERAL DESCRIPTION
40 MHz correlated double sampler (CDS)
The AD9942 is a highly integrated dual-channel CCD signal
0 dB to 18 dB, 9-bit variable gain amplifier (VGA)
40 MSPS analog-to-digital converter (ADC)
Optical black clamp (CLPOB) with variable level control
Complete on-chip timing driver
Precision Timing core with <550 ps resolution
On-chip 3 V horizontal and RG drivers
4-phase H-clock mode
processor for digital still camera applications. Each channel is
specified at pixel rates of up to 40 MHz. The AD9942 consists of
a complete analog front end with analog-to-digital conversion,
combined with a programmable timing driver. The Precision
Timing core allows high speed clocks to be adjusted with
550 ps resolution.
The analog front end uses black level clamping and includes a
VGA, a 40 MSPS ADC, and a CDS. The timing driver provides
the high speed CCD clock drivers for RG_A and RG_B, as well
as the H1A to H4A and H1B to H4B outputs. The 6-wire serial
interface is used to program the AD9942.
100-lead, 9 mm × 9 mm, CSP_BGA package
APPLICATIONS
Signal processor for dual-channel CCD outputs
Digital still cameras
Digital video cameras
High speed digital imaging applications
Available in a space-saving, 9 mm × 9 mm, CSP_BGA package,
the AD9942 is specified over an operating temperature range of
−25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT_A REFB_A
REFT_B REFB_B
AD9942
VREF_A
VREF_B
14
14
DOUT_A
DOUT_B
ADC
CDS
VGA
VGA
CCDIN_A
CCDIN_B
0dB
0dB
~
18dB
18dB
CLAMP
CLAMP
~
ADC
CDS
INTERNAL CLOCKS
RG_A
RG_B
PRECISION
TIMING
CORE
CLI_A
CLI_B
HORIZONTAL
DRIVERS
4
4
H1A TO H4A
H1B TO H4B
SCK_A
SCK_B
SYNC
GENERATOR
INTERNAL
REGISTERS
HD_A VD_A HD_B VD_B
SL_A
SL_B
SDATA_A SDATA_B
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD9942
TABLE OF CONTENTS
Features .............................................................................................. 1
High Speed Clock Programmability........................................ 19
H Driver and RG Outputs......................................................... 21
Digital Data Outputs.................................................................. 21
Channel A and Channel B Horizontal Clamping and Blanking ....22
Individual CLPOB and PBLK Sequences................................ 22
Individual HBLK Sequences..................................................... 22
Channel A and Channel B Special HBLK Patterns.................... 24
Horizontal Sequence Control................................................... 24
H-Counter Synchronization ..................................................... 25
Channel A and Channel B Power-Up Procedure....................... 26
Channel A and Channel B Analog Front End Operation......... 27
DC Restore .................................................................................. 27
Correlated Double Sampler ...................................................... 27
Channel A and Channel B Variable Gain Amplifier ............. 28
Channel A and Channel B ADC .............................................. 28
Channel A and Channel B CLPOB.......................................... 28
Channel A and Channel B Digital Data Outputs................... 28
Applications Information.............................................................. 29
Circuit Configuration................................................................ 29
Grounding/Decoupling Recommendations........................... 29
Driving the CLI Input................................................................ 31
Horizontal Timing Sequence Example.................................... 31
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 33
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
General Specifications ................................................................. 3
Digital Specifications ................................................................... 4
Analog Specifications................................................................... 5
Channel-to-Channel Specifications........................................... 6
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 11
Equivalent Input/Output Circuits ................................................ 12
Typical Performance Characteristics ........................................... 13
System Overview ............................................................................ 14
Serial Interface Timing .................................................................. 15
Complete Register Listing ......................................................... 16
Channel A and Channel B Precision Timing............................... 19
High Speed Timing Generation ............................................... 19
Timing Resolution...................................................................... 19
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Changes to Table 3............................................................................ 5
Changes to Table 13........................................................................ 17
Change to Channel A and Channel B
Variable Gain Amplifier Section............................................... 28
Updated Outline Dimensions....................................................... 33
1/05—Revision 0: Initial Version
Rev. A | Page 2 of 36
AD9942
SPECIFICATIONS
GENERAL SPECIFICATIONS
X = A, B.
Table 1.
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
−25
−65
40
+85
+150
°C
°C
MAXIMUM CLOCK RATE
POWER SUPPLY VOLTAGE
AVDD_X, TCVDD_X (AFE, Timing Core)
HVDD_X (H1X to H4X Drivers)
RGVDD_X (RG_X Driver)
DRVDD_X (D0 to D13 Drivers)
DVDD_X (Digital)
MHz
2.7
2.7
2.7
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
V
V
V
V
V
POWER DISSIPATION FOR EACH CHANNEL
(40 MHz, 3 V Supplies, 100 pF H1X to H4X Loading, 10 pF RG_X Loading)
Power from AVDD_X
Power from TCVDD_X
Power from HVDD_X1
Power from RGVDD_X
Power from DRVDD_X
Power from DVDD_X
Total Shutdown Mode
110
33
160
13
15
40
2
mW
mW
mW
mW
mW
mW
mW
1 Total HVDD_X Power = [(CLOAD) × (HVDD_X) × (Pixel Frequency)] × (HVDD_X) × (Number of Horizontal Outputs Used).
Rev. A | Page 3 of 36
AD9942
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD_X = DVDD_X = DRVDD_X = HVDD_X = RGVDD_X = 2.7 V, CL = 20 pF, unless otherwise noted.
X = A, B.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
VIH
VIL
IIH
IIL
CIN
2.1
V
V
μA
μA
pF
0.6
10
10
10
Input Capacitance
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
CLI INPUT
VOH
VOL
2.2
V
V
0.5
High Level Input Voltage (TCVDD_X/2 + 0.5 V)
Low Level Input Voltage
VIH − CLI
VIL − CLI
1.85
2.2
V
V
0.85
0.5
RG_X AND H1X TO H4X DRIVER OUTPUTS
High Level Output Voltage (RGVDD_X – 0.5 V and HVDD_X – 0.5 V)
Low Level Output Voltage
VOH
VOL
V
V
Maximum Output Current (Programmable)
Maximum Load Capacitance
30
mA
pF
100
Rev. A | Page 4 of 36
AD9942
ANALOG SPECIFICATIONS
TMIN to TMAX, AVDD_X = DVDD_X = 3.0 V, fCLI = 40 MHz, typical timing specifications, unless otherwise noted. X = A, B.
Table 3.
Parameter
Min
Typ
Max
Unit
Notes
CDS
Gain
0
dB
Allowable CCD Reset Transient1
Max Input Range Before Saturation
Max CCD Black Pixel Amplitude
500
mV
V p-p
mV
1.0
100
Measured at 12 dB VGA gain
(Typ = 70 mV at 15 dB and 50 mV at 18 dB)
VARIABLE GAIN AMPLIFIER (VGA_X)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
1.0
2.0
V p-p
V p-p
Steps
512
Guaranteed
Gain Range
Min Gain (Code 0)
Max Gain (Code 511)
CLPOB
0
18
dB
dB
Clamp Level Resolution
Clamp Level
256
Steps
4 LSB/step
Measured at ADC output
Min Clamp Level
Max Clamp Level
0
1023
LSB
LSB
CHN_A AND CHN_B ADC
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT_X)
Reference Bottom Voltage (REFB_X)
SYSTEM PERFORMANCE
VGA Gain Accuracy
−1.0
0.5
Guaranteed
2.0
+1.0
LSB
V
2.0
1.0
V
V
Specifications include entire signal chain
Min Gain (Code 0)
−0.5
17.5
0
+0.5
18.5
dB
dB
%
LSB rms
dB
Max Gain (Code 511)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
18
0.15
3
12 dB gain applied
AC grounded input, 6 dB gain applied
Measured with step change on supply
Power Supply Rejection (PSR)
50
1 Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
100mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT SIGNAL RANGE
Rev. A | Page 5 of 36
AD9942
CHANNEL-TO-CHANNEL SPECIFICATIONS
TMIN to TMAX, AVDD_X = DVDD_X = 3.0 V, fCLI = 40 MHz, typical timing specifications, unless otherwise noted. X = A, B.
Table 4.
Parameter
Min
Typ
Max
Unit
Notes
CHANNEL A/CHANNEL B OUTPUT
CODE MATCHING ERROR1
<1.0%
VGA = 6 dB, 12 dB, and 18 dB conditions.
CROSSTALK ERROR
VGA = 6 dB, 12 dB, and 18 dB conditions.
Channel A to Channel B
−84
−84
dB
dB
Full-scale step applied to Channel A while
measuring response on Channel B.
Full-scale step applied to Channel B while
measuring response on Channel A.
Channel B to Channel A
1 Matching error calculated using a ramp input applied to Channel A and Channel B simultaneously. Typical Channel A/Channel B error is <1.0% at each output code.
Rev. A | Page 6 of 36
AD9942
TIMING SPECIFICATIONS
CL = 20 pF, fCLI = 40 MHz, serial timing in Figure 14 and Figure 15, unless otherwise noted. X = A, B.
Table 5.
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK (CLI_X) (See Figure 16)
CLI_X Clock Period
CLI_X High/Low Pulse Width
Delay from CLI_X to Internal Pixel Period Position (See Figure 16)
CLPOB_X PULSE WIDTH (Programmable)1
SAMPLE CLOCKS (See Figure 17)
SHP_X Rising Edge to SHD_X Rising Edge
DATA OUTPUTS (See Figure 19 and Figure 20)
Output Delay from Programmed Edge
Pipeline Delay
25.0
10.0
ns
ns
ns
tADC
tCLIDLY
tCOB
12.5
6
15.0
2
20
Pixels
tS1
11.2
12.5
ns
tOD
6
11
ns
Cycles
SERIAL INTERFACE
Maximum SCK_X Frequency
SL_X to SCK_X Setup Time
SCK to SL_X Hold Time
SDATA_X Valid to SCK_X Rising Edge Setup
SCK_X Falling Edge to SDATA_X Valid Hold
SCK_X Falling Edge to SDATA_X Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Rev. A | Page 7 of 36
AD9942
ABSOLUTE MAXIMUM RATINGS
Table 6. Ratings (X = A, B)
Parameter
AVDD_X and TCVDD_X to AVSS_X
HVDD_X and RGVDD_X to
HVSS_X and RGVSS_X
DVDD_X and DRVDD_X to
DVSS_X and DRVSS_X
Any VSS_X to Any VSS_X
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
Digital Outputs to DRVSS_X
SCK_X, SL_X, and SDATA_X to
DVSS_X
−0.3 V to DRVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
THERMAL RESISTANCE
100-lead, 9 mm × 9 mm, CSP_BGA package: θJA = 38.3°C/W1
RG_X to RGVSS_X
H1X to H4X to HVSS_X
REFT_X, REFB_X, and CCDIN_X to
AVSS_X
−0.3 V to RGVDD + 0.3 V
−0.3 V to HVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
1 θJA is measured using a 4-layer PCB with the exposed paddle soldered to the
board.
Junction Temperature
Lead Temperature (10 sec)
150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 8 of 36
AD9942
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 CORNER
INDEX AREA
1
2
3
4
5
6
7
8
9 10
A
B
C
D
E
F
G
H
J
K
AD9942
TOP VIEW
(Not to Scale)
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Ball Location
Mnemonic
Type1
DI
DI
DI
AO
AO
AI
DO
DO
DO
DO
DO
P
P
P
P
P
P
P
P
P
Description
B2
SL_A
6-Wire Serial Load for Channel A
6-Wire Serial Data for Channel A
6-Wire Serial Clock for Channel A
Reference Top Decoupling for Channel A (decouple with 1.0 μF to AVSS_A)
Reference Bottom Decoupling for Channel A (decouple with 1.0 μF to AVSS_A)
Analog Input for Channel A CCD Signal (connect through series 0.1 μF capacitor)
CCD Horizontal Clock 1 for Channel A
CCD Horizontal Clock 2 for Channel A
CCD Horizontal Clock 3 for Channel A
CCD Horizontal Clock 4 for Channel A
CCD Reset Gate Clock for Channel A
Digital Driver Ground for Channel A
Digital Driver Supply for Channel A
H1A to H4A Driver Ground for Channel A
H1A to H4A Driver Supply for Channel A
RG_A Driver Ground for Channel A
C2
D2
C1
D1
A1
F4
SDATA_A
SCK_A
REFT_A
REFB_A
CCDIN_A
H1A
F3
H2A
D4
D3
B4
H3A
H4A
RG_A
J2
K3
E3
E4
C3
C4
B3
A4
B1
A2
F2
F1
E2
DRVSS_A
DRVDD_A
HVSS_A
HVDD_A
RGVSS_A
RGVDD_A
TCVSS_A
TCVDD_A
AVSS_A
AVDD_A
DVSS_A
DVDD_A
VD_A
RG_A Driver Supply for Channel A
Analog Ground for Channel A Timing Core
Analog Supply for Channel A Timing Core
Analog Ground for Channel A
Analog Ground for Channel A
Digital Ground for Channel A
Digital Supply for Channel A
Vertical Sync Pulse for Channel A
Horizontal Sync Pulse for Channel A
6-Wire Serial Load for Channel B
6-Wire Serial Data for Channel B
6-Wire Serial Clock for Channel B
Reference Top Decoupling for Channel B (decouple with 1.0 μF to AVSS_B)
Reference Bottom Decoupling for Channel B (decouple with 1.0 μF to AVSS_B)
Analog Input for Channel B CCD Signal (connect through series 0.1 μF capacitor)
CCD Horizontal Clock 1 for Channel B
P
P
P
DI
DI
DI
DI
DI
AO
AO
AI
E1
HD_A
B8
SL_B
C8
D8
C7
D7
A7
F10
F9
SDATA_B
SCK_B
REFT_B
REFB_B
CCDIN_B
H1B
DO
DO
DO
H2B
CCD Horizontal Clock 2 for Channel B
CCD Horizontal Clock 3 for Channel B
D10
H3B
Rev. A | Page 9 of 36
AD9942
Ball Location
D9
B10
J8
K9
E9
E10
C9
C10
B9
A10
B7
A8
Mnemonic
H4B
RG_B
Type1
DO
DO
P
P
P
P
P
P
P
P
P
P
P
P
DI
DI
DI
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
Description
CCD Horizontal Clock 4 for Channel B
CCD Reset Gate Clock for Channel B
Digital Driver Ground for Channel B
Digital Driver Supply for Channel B
H1B to H4B Driver Ground for Channel B
H1B to H4B Driver Supply for Channel B
RG_B Driver Ground for Channel B
RG_B Driver Supply for Channel B
Analog Ground for Channel B Timing Core
Analog Supply for Channel B Timing Core
Analog Ground for Channel B
Analog Ground for Channel B
Digital Ground for Channel B
Digital Supply for Channel B
Vertical Sync Pulse for Channel B
Horizontal Sync Pulse for Channel B
Master Clock Input for Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
DRVSS_B
DRVDD_B
HVSS_B
HVDD_B
RGVSS_B
RGVDD_B
TCVSS_B
TCVDD_B
AVSS_B
AVDD_B
DVSS_B
DVDD_B
VD_B
HD_B
CLI_A
D0_A
D1_A
D2_A
D3_A
D4_A
D5_A
D6_A
D7_A
D8_A
D9_A
D10_A
D11_A
D12_A
D13_A
GND
F8
F7
E8
E7
A3
G1
H1
J1
K1
G2
H2
K2
G3
H3
J3
K4
J4
H4
G4
Data Output Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
Data Output Channel A
Ground Connection
A5, B5, C5, D5, E5,
F5, G5, H5, J5, K5,
A6, B6, C6, D6, E6,
F6, G6, H6, J6, K6
A9
G7
H7
J7
CLI_B
D0_B
D1_B
D2_B
D3_B
D4_B
D5_B
D6_B
D7_B
D8_B
D9_B
D10_B
D11_B
D12_B
D13_B
DI
Master Clock Input for Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
Data Output Channel B
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
K7
G8
H8
K8
G9
H9
J9
K10
J10
H10
G10
1 AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power.
Rev. A | Page 10 of 36
AD9942
TERMINOLOGY
Differential Nonlinearity (DNL)
Power Supply Rejection (PSR)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore,
every code must have a finite width. No missing codes
guaranteed to 12-bit resolution indicates that all 4096 codes
must be present over all operating conditions.
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
Matching Error
The matching error refers to the Channel A to Channel B
mismatch after post-ADC correction calibration has been
applied to remove gain error between Channel A and
Channel B.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9942 from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1 LSB
and 0.5 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage
of the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
Crosstalk
The crosstalk is measured while applying a full-scale step to
one channel and measuring the interference on the opposite
channel.
Interference (LSB)
⎛
⎞
⎜
⎜
⎟
⎟
Crosstalk (dB) = 20 × log
16,384
⎝
⎠
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
1 LSB = (ADC full scale/2n codes)
where n is the bit resolution of the ADC. For the AD9942,
1 LSB is approximately 122.0 μV.
Rev. A | Page 11 of 36
AD9942
EQUIVALENT INPUT/OUTPUT CIRCUITS
X = A, B.
DVDD
AVDD
330Ω
R
AVSS
AVSS
DVSS
Figure 3. CCDIN_X
Figure 6. Digital Inputs
HVDD OR RGVDD
DATA
AVDD
ENABLE
DOUT
330Ω
25kΩ
CLI
+
1.4V
HVSS OR RGVSS
AVSS
Figure 7. H1X to H4X and RG_X
Figure 4. CLI_X
DVSS
DRVDD
DATA
THREE-STATE
DOUT
DVSS
DRVSS
Figure 5. Data Outputs D0_X to D13_X
Rev. A | Page 12 of 36
AD9942
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.015
1.010
1.005
1.000
0.995
–25°C +25°C
0.5
0
+85°C
–0.5
–1.0
0
4000
8000
12000
16000
2000
4000
6000
8000 10000 12000 14000 16000
ADC OUTPUT CODE
ADC OUTPUT CODE
Figure 8. DNL for Channel A and Channel B
Figure 10. Noncalibrated Channel A/Channel B Ratio
10
5
0
–5
–10
–15
–20
2000
4000
6000
8000 10000 12000 14000 16000
DAC OUTPUT CODE
Figure 9. INL Performance for Channel A and Channel B
Rev. A | Page 13 of 36
AD9942
SYSTEM OVERVIEW
MAXIMUM FIELD DIMENSIONS
V DRIVER
V1 > Vx, VSG1 > VSGx, SUBCK
H1A TO H4A, RG_A
H1B TO H4B, RG_B
12-BIT HORIZONTAL = 4096 PIXELS MAX
DOUT
CCDIN_A
AD9942
CCD
DIGITAL IMAGE
PROCESSING
ASIC
CCDIN_B
INTEGRATED
AFE + TD
12-BIT VERTICAL = 4096 LINES MAX
HD_A, VD_A,
HD_B, VD_B
CLI_A, CLI_B
SERIAL
INTERFACE
Figure 11. Typical Application
Figure 12. Vertical and Horizontal Counters
Figure 11 shows the typical system application diagram for the
AD9942. The CCD output is processed by the AD9942 AFE
circuitry, which consists of a CDS, a VGA, a CLPOB, and an
ADC. The digitized pixel information is sent to the digital
image processor chip, where all postprocessing and
compression occurs. To operate the CCD, CCD timing param-
eters are programmed from the image processor to the AD9942
through the 6-wire serial interface. From the system master
clock, CLI, which is provided by the image processor, the device
generates the high speed CCD clocks and internal AFE clocks.
All AD9942 clocks are synchronized with VD_X and HD_X.
The CLPOB is programmed and generated internally.
The H drivers for H1A to H4A, H1B to H4B, RG_A, and RG_B
are included in the AD9942, allowing these clocks to be directly
connected to the CCD. An H driver voltage of 3 V is supported
in the AD9942.
Figure 12 shows the horizontal and vertical counter dimensions
for the device. All internal horizontal clocking is programmed
using these dimensions to specify line and pixel locations.
MAX VD LENGTH IS 4095 LINES
VD_X
MAX HD LENGTH IS 4095 PIXELS
HD_X
CLI_X
Figure 13. Maximum VD_X/HD_X Dimensions
Rev. A | Page 14 of 36
AD9942
SERIAL INTERFACE TIMING
All of the AD9942 internal registers are accessed through a
6-wire serial interface. Each register consists of an 8-bit address
and a 24-bit data-word. Both the 8-bit address and the 24-bit
data-word are written starting with the LSB. To write to each
register, a 32-bit operation is required, as shown in Figure 14.
Although many registers are less than 24 bits wide, all 24 bits
must be written for each register. If the register is only 16 bits
wide, then the upper 8 bits can be filled with 0s during the serial
write operation. If fewer than 24 bits are written, the register is
not updated with new data.
Figure 15 shows a more efficient way to write to the registers by
using the AD9942 address auto-increment capability. In this
method, the lowest desired address is written first, followed by
multiple 24-bit data-words. Each new 24-bit data-word is
written automatically to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. The address auto-increment function can
be used, starting with any register location, to write to as few as
two registers or to as many as the entire register space.
8-BIT ADDRESS
24-BIT DATA
...
SDATA_X
SCK_X
SL_X
A0
A1
A2
A4
A5
A6
tDH
A7
D1
D2
D3
D21 D22 D23
A3
D0
tDS
...
1
2
3
4
5
6
7
8
9
10
11
12
30
31
32
tLS
tLH
...
...
SL UPDATED
VD/HD UPDATED
VD_X
HD_X
...
NOTES
1. X = A, B.
2. INDIVIDUAL SDATA_X BITS ARE LATCHED UPON SCK_X RISING EDGES.
3. ALL 32 BITS MUST BE WRITTEN: 8 BITS FORADDRESS AND 24 BITS FOR DATA.
4. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USEDTO COMPLETE THE 24-BIT DATA LENGTH.
5. NEW DATA IS UPDATED AT EITHER THE SL_X RISING EDGE ORAT THE HD_X FALLING EDGE AFTER THE NEXT VD_X FALLING EDGE.
6. VD_X/HD_X UPDATE POSITION CAN BE DELAYED TO ANY HD_X FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
Figure 14. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
...
...
...
...
SDATA_X
SCK_X
SL_X
A0
A1
A2
A4
A5
A6
A7
D0
D1
D22 D23
D0
D1
D22 D23 D0
A3
D1
D2
...
...
...
58
59
33
34
55
56
57
1
2
3
4
5
6
7
8
9
10
31
32
...
...
NOTES
1. X = A, B.
2. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
3. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
4. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
5. SL_X IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
6. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
Figure 15. Continuous Serial Write Operation
Rev. A | Page 15 of 36
AD9942
COMPLETE REGISTER LISTING
In Table 8 through Table 16, note the following:
•
•
•
All addresses and default values are expressed in hexadecimal format.
All registers are VD_X/HD_X updated as shown in Figure 14, except for the registers indicated in Table 8, which are SL_X updated.
Each channel is programmed independently using the 5-wire serial interface. Both channels can be programmed with the same
register values by tying the SL_A and SL_B signals together and the SDATA_A and SDATA_B signals together.
Table 8. Updated Registers upon Rising Edge of SL_X
Register
Description
OPRMODE
CTLMODE
AFE operation modes
AFE control modes
SW_RESET
Software reset bit
TGCORE _RSTB
PREVENTUPDATE
VDHDEDGE
FIELDVAL
HBLKRETIME
H1CONTROL
RGCONTROL
DRVCONTROL
SAMPCONTROL
DOUTPHASE
Reset bar signal for internal TG core
Prevents update of registers
VD/HD active edge
Resets internal field pulse
Retimes the HBLK to internal clock
H1 polarity control
RG signal control polarity
Drive-strength control
SHP/SHD sample control
DOUT phase control
Table 9. CHN_A and CHN_B AFE Register Map
Address Data Bit Content Default (Hex)
Name
Description
00
01
02
03
04
05
[11:0]
[9:0]
[7:0]
[11:0]
[17:0]
[17:0]
4
0
80
4
0
OPRMODE
TESTMODE
CLAMP LEVEL
CTLMODE
TESTMODE
TESTMODE
AFE operation modes (see Table 15).
Internal test mode. Should always be set = 0.
CLPOB level.
AFE control modes (see Table 16).
Test operation only. Set = 0.
Test operation only. Set = 0.
0
Table 10. CHN_A and CHN_B Miscellaneous Register Map
Address Data Bit Content Default (Hex)
Name
Description
10
11
12
13
14
[0]
[0]
[0]
[11:0]
[0]
0
0
0
0
0
SW_RST
Software reset.1 = reset all registers to default, then self-clear back to 0.
OUT_CONTROL Output control. 0 = make all dc outputs inactive.
TGCORE_RSTB Timing core reset bar. 0 = reset TG core; 1 = resume operation.
UPDATE
PREVENTUPDA Prevents the update of the VD-updated registers. 1 = prevent update.
TE
Serial update. Sets the line (HD) within the field to update serial data.
15
16
17
[0]
0
0
0
VDHDEDGE
VD/HD active edge.
0 = falling edge triggered; 1 = rising edge triggered.
Field value sync.
0 = next field 0; 1 = next field 1; 2/3 = next field 2.
[1:0]
[0]
FIELDVAL
HBLKRETIME
Retime HBLK to internal H1 clock. Preferred setting is 1. Setting to 1 adds
one cycle delay to HBLK toggle positions.
18
19
1A
E8
[1:0]
[0]
[0]
[2:0]
[11:3]
0
0
0
TEST MODE
TEST MODE
TEST MODE
TEST MODE
VGAGAIN
Internal test mode. Should always be set = 0.
Internal test mode. Should always be set = 0.
Internal test mode. Should always be set = 0.
Internal test mode. Should always be set = 0.
VGA gain control.
0
Rev. A | Page 16 of 36
AD9942
Table 11. CHN_A and CHN_B CLPOB Register Map
Address Data Bit Content Default (Hex) Name
Description (the CLPOBSCP0 Always Starts at Line 0)
20
21
22
23
24
25
26
27
28
[3:0]
F
CLPOBPOL
Start polarities for CLPOB Sequences 0, 1, 2, and 3.
[23:0]
[23:0]
[23:0]
[23:0]
[7:0]
[11:0]
[11:0]
[11:0]
FFFFFF
FFFFFF
FFFFFF
FFFFFF
00
FFF
FFF
FFF
CLPOBTOG_0
CLPOBTOG_1
CLPOBTOG_2
CLPOBTOG_3
CLPOBSPTR
CLPOBSCP1
CLPOBSCP2
CLPOBSCP3
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
CLPOB sequence pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
CLPOB sequence—Change Position 1.
CLPOB sequence—Change Position 2.
CLPOB sequence—Change Position 3.
Table 12. PBLK Register Map
Address Data Bit Content
Default (Hex)
F
Name
Description (the PBLKSCP0 Always Starts at Line 0)
Start polarities for PBLK Sequences 0, 1, 2, and 3.
30
31
32
33
34
35
36
37
38
[3:0]
PBLKPOL
[23:0]
[23:0]
[23:0]
[23:0]
[7:0]
[11:0]
[11:0]
[11:0]
FFFFFF
FFFFFF
FFFFFF
FFFFFF
00
FFF
FFF
FFF
PBLKTOG_0
PBLKTOG_1
PBLKTOG_2
PBLKTOG_3
PBLKSPTR
PBLKSCP1
PBLKSCP2
PBLKSCP3
Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
PBLK Sequence Pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
PBLK sequence—Change Position 1.
PBLK sequence—Change Position 2.
PBLK sequence—Change Position 3.
Table 13. HBLK Register Map
Address Data Bit Content
Default (Hex)
0
0
1
F
Name
Description (the HBLKSCP0 Always Starts at Line 0)
Test mode. Always set = 0 if accessed.
Test mode. Always set = 0 if accessed.
Test mode. Always set = 1 if accessed.
HBLK internal masking polarity. 0 = mask H1 low; 1 = mask H1 high.
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
[0]
[0]
[0]
[3:0]
TESTMODE
TESTMODE
TESTMODE
HBLKMASK
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[7:0]
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
FFFFFF
00
HBLKTOG12_0 Sequence 0. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
HBLKTOG34_0 Sequence 0. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
HBLKTOG56_0 Sequence 0. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
HBLKTOG12_1 Sequence 1. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
HBLKTOG34_1 Sequence 1. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
HBLKTOG56_1 Sequence 1. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
HBLKTOG12_2 Sequence 2. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
HBLKTOG34_2 Sequence 2. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
HBLKTOG56_2 Sequence 2. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
HBLKTOG12_3 Sequence 3. Toggle Position 1 [11:0] and Toggle Position 2 [23:12].
HBLKTOG34_3 Sequence 3. Toggle Position 3 [11:0] and Toggle Position 4 [23:12].
HBLKTOG56_3 Sequence 3. Toggle Position 5 [11:0] and Toggle Position 6 [23:12].
HBLKSPTR
HBLKSCP1
HBLKSCP2
HBLKSCP3
HBLK sequence pointers for Region 0 [1:0], 1 [3:2], 2 [5:4], and 3 [7:6].
HBLK sequence—Change Position 1.
HBLK sequence—Change Position 2.
[11:0]
[11:0]
[11:0]
FFF
FFF
FFF
HBLK sequence—Change Position 3.
Rev. A | Page 17 of 36
AD9942
Table 14. CHN_A and CHN_B H1 to H4, RG, SHP, SHD Register Map
Address Data Bit Content
Default (Hex)
Name
Description
60
61
62
[12:0]
[12:0]
[14:0]
01001
H1CONTROL
H1 signal control. Polarity [0] (0 = inversion; 1 = no inversion).
H1 positive edge location [6:1].
H1 negative edge location [12:7].
RG signal control. Polarity [0] (0 = inversion; 1 = no inversion).
RG positive-edge location [6:1].
RG negative-edge location [12:7].
00801
0
RGCONTROL
DRVCONTROL
Drive-strength control for H1X [2:0], H2X [5:3], H3X [8:6], H4X [11:9],
and RG_X [14:12].
Drive-current values: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.2 mA, 5 = 21.5 mA, 6 = 25.8 mA, 7 = 30.1 mA.
63
64
[11:0]
[5:0]
00024
0
SAMPCONTROL SHP/SHD sample control. SHP sampling location [5:0]. SHD sampling
location [11:6].
DOUTPHASE
DOUT phase control.
Table 15. CHN_A and CHN_B AFE Operation Register Detail
Address Data Bit Content
Default (Hex)
Name
Description
00
[1:0]
[2]
[3]
[4]
[5]
[7:6]
[8]
[9]
0
1
0
0
0
0
0
0
0
PWRDOWN
CLPENABLE
CLPSPEED
FASTUPDATE
PBLK_LVL
TEST MODE
DCBYP
0 = normal operation; 1 = reference standby; 2/3 = total power-down.
0 = disable CLPOB; 1 = enable CLPOB.
0 = select normal CLPOB settling; 1 = select fast CLPOB settling.
0 = ignore VGA update; 1 = very fast clamping when VGA is updated.
DOUT value during PBLK; 0 = blank to zero; 1 = blank to clamp level.
Internal test mode. Should always be set = 3.
0 = enable dc restore circuit; 1 = bypass dc restore circuit during PBLK.
Test operation only. Set = 0.
TESTMODE
TESTMODE
[11:10]
Test operation only. Set = 0.
Table 16. CHN_A and CHN_B AFE Control Register Detail
Address Data Bit Content
Default (Hex)
Name
Description
03
[1:0]
[2]
[3]
[4]
[5]
0
1
0
0
0
TESTMODE
TESTMODE
Test operation only. Set = 0.
Test operation only. Set = 0.
DOUTDISABLE 0 = data outputs are driven; 1 = data outputs are three-stated.
DOUTLATCH
GRAYENCODE
0 = latch data outputs with DOUT phase; 1 = output latch transparent.
0 = binary encode data outputs; 1 = gray encode data outputs.
Rev. A | Page 18 of 36
AD9942
CHANNEL A AND CHANNEL B PRECISION TIMING
HIGH SPEED TIMING GENERATION
HIGH SPEED CLOCK PROGRAMMABILITY
The AD9942 generates flexible, high speed timing signals using
the Precision Timing core for both channels. This core is the
foundation for generating the timing used for both the CCD
and the AFE, the reset gate RG_X, the horizontal drivers H1X
to H4X, and the SHP/SHD sample clocks. A unique architecture
makes it routine for the system designer to optimize image
quality by providing precise control over the horizontal CCD
readout and the AFE correlated double sampling.
Figure 17 shows how the high speed clocks, RG_X, H1X to
H4X, SHP, and SHD, are generated. The RG_X pulse has
programmable rising and falling edges and can be inverted
using the polarity control. The horizontal clock, H1, has
programmable rising and falling edges and polarity control.
The H2 clock is always the inverse of the H1 clock. Table 17 sum-
marizes the high speed timing registers and their parameters.
Each edge location setting is six bits wide, but only 48 valid edge
locations are available. Therefore, the register values are
mapped into four quadrants, with each quadrant containing
12 edge locations. Table 18 shows the correct register values for
the corresponding edge locations.
TIMING RESOLUTION
The Precision Timing core uses a 1× master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 16 illustrates how the internal timing
core divides the master clock period into 48 steps or edge
positions. Therefore, the edge resolution of the Precision Timing
core is (tCLI/48). For more information on using the CLI input,
see the Applications Information section.
POSITION
CLI_X
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
...
tCLIDLY
...
1 PIXEL
PERIOD
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI_X INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6ns TYP).
Figure 16. High Speed Clock Resolution from CLI
3
CCD SIGNAL
4
1
5
2
RG_X
6
H1X/H3X
H2X/H4X
PROGRAMMABLE CLOCK POSITIONS:
1
RG_X RISING EDGE.
RG_X FALLING EDGE.
SHP SAMPLE LOCATION.
SHD SAMPLE LOCATION.
H1X/H3X RISING EDGE POSITION.
H1X/H3X FALLING EDGE POSITION (H2X/H4X ARE INVERSE OF H1X/H3X).
2
3
4
5
6
Figure 17. High Speed Clock Programmable Locations
Rev. A | Page 19 of 36
AD9942
Table 17. Channel A and Channel B H1X to H4X CONTROL, RG_X CONTROL, DRVCONTROL,
and SAMPCONTROL Register Parameters
Length
(Bit)
Parameter
Range
Description
Polarity
1
6
6
6
3
6
High/low
Polarity control for H1X and RG_X (0 = no inversion; 1 = inversion).
Positive-edge location for H1X, H3X, and RG_X.
Negative-edge location for H1X and RG_X.
Sampling location for SHP and SHD.
Drive current for H1X to H4X and RG_X outputs, 0 to 7 steps of 4.1 mA each.
Phase location of data outputs with respect to pixel period.
Positive Edge
Negative Edge
Sample Location
Drive Control
DOUT Phase
0 to 47 edge locations
0 to 47 edge locations
0 to 47 sample locations
0 to7 current steps
0 to 47 edge locations
Table 18. Channel A and Channel B Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
I
II
III
IV
0 to 11
12 to 23
24 to 35
36 to 47
0 to 11
16 to 27
32 to 43
48 to 59
Rev. A | Page 20 of 36
AD9942
As shown in Figure 18, the H2X/H4X outputs are inverses of
H DRIVER AND RG OUTPUTS
H1X. The internal propagation delay resulting from the signal
inversion is less than l ns, which is significantly less than the
typical rise time driving the CCD load. This results in a
H1X/H2X crossover voltage at approximately 50% of the output
swing. The crossover voltage is not programmable.
In addition to the programmable timing positions, the AD9942
features on-chip output drivers for the RG_X and H1X to H4X
outputs. These drivers are powerful enough to drive the CCD
inputs directly. The H-driver and RG-driver currents can be
adjusted for optimum rise and fall time into a particular load by
using the DRVCONTROL register (Address 0x62). The
DRVCONTROL register is divided into five 3-bit values, each
adjustable in 4.1 mA increments. The minimum setting of 0 is
equal to off, or three-state, and the maximum setting of 7 is
equal to 30.1 mA.
DIGITAL DATA OUTPUTS
The AD9942 data output phase is programmable using the
DOUTPHASE register (Address 0x64). Any edge from 0 to 47
can be programmed, as shown in Figure 19. The pipeline delay
for the digital data output is shown in Figure 20.
H1X/H3X
tRISE
H2X/H4X
tPD << tRISE
tPD
H1X/H3X
H2X/H4X
FIXED CROSSOVER VOLTAGE
Figure 18. H-Clock Inverse Phase Relationship
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
CLI_X
1 PIXEL PERIOD
tOD
DOUT
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
Figure 19. Digital Output Phase Adjustment
VD_X
HD_X
CLI_X
H-COUNTER
RESET
H COUNTER
(PIXEL COUNTER)
X
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
10 11 12 14 15
0
1
2
3
NOTES
1. INTERNAL H COUNTER IS RESET SEVEN CLI_X CYCLES AFTER THE HD_X FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI_X RISING EDGE IS COINCIDENT WITH HD_X FALLING EDGE.
Figure 20. Pipeline Delay for Channel A and Channel B Digital Data Output
Rev. A | Page 21 of 36
AD9942
CHANNEL A AND CHANNEL B HORIZONTAL CLAMPING AND BLANKING
The AD9942 horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual
sequences are defined for each signal, which are then organized
into multiple regions during image readout. This allows the
dark pixel clamping and blanking patterns to be changed at
each stage of the readout to accommodate different image
transfer timing and high speed line shifts.
INDIVIDUAL HBLK SEQUENCES
The HBLK programmable timing, shown in Figure 22, is similar
to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, there is
a polarity control, HBLKMASK, which designates the polarity
of the horizontal clock signal H1 during the blanking period.
Setting HBLKMASK high sets H1 low and H2 high during the
blanking, as shown in Figure 23. Up to four individual
sequences are available for HBLK.
INDIVIDUAL CLPOB AND PBLK SEQUENCES
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 21. These two signals are independently
programmed using the parameters shown in Table 19. The start
polarity, first toggle position, and second toggle position are
fully programmable for each signal. The CLPOB and PBLK
signals are active low and should be programmed accordingly.
Up to four individual sequences can be created for each signal.
Table 19. Channel A and Channel B CLPOB and PBLK Individual Sequence Parameters
Length
(Bit)
Parameter
Range
Description
Polarity
Toggle Position 1
Toggle Position 2
1
12
12
High/low
0 to 4095 pixel locations
0 to 4095 pixel locations
Starting polarity of CLPOB and PBLK pulses for Sequences 0 to 3.
First toggle position within the line for Sequences 0 to 3.
Second toggle position within the line for Sequences 0 to 3.
Rev. A | Page 22 of 36
AD9942
...
...
HD
2
3
CLPOB
PBLK
1
ACTIVE
ACTIVE
PROGRAMMABLE SETTINGS:
1
START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
FIRST TOGGLE POSITION.
SECOND TOGGLE POSITION.
2
3
Figure 21. CLPOB and PBLK Pulse Placement
...
...
HD_X
HBLK
1
2
BLANK
BLANK
PROGRAMMABLE SETTINGS:
1
FIRST TOGGLE POSITION = START OF BLANKING.
SECOND TOGGLE POSITION = END OF BLANKING.
2
Figure 22. HBLK Pulse Placement
...
...
HD_X
HBLK
H1X/H3X
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
...
H1X/H3X
H2X/H3X
...
Figure 23. HBLK Masking Control
Rev. A | Page 23 of 36
AD9942
CHANNEL A AND CHANNEL B SPECIAL HBLK PATTERNS
Six toggle positions are available for HBLK. Typically, only two
of the toggle positions are used to generate the standard HBLK
interval. However, the additional toggle positions can be used to
generate special HBLK patterns, as shown in Figure 24. The
pattern in this example uses all six toggle positions to generate
two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
into four separate regions, as shown in Figure 25. The SCP0 is
always hard-coded to Line 0, and SCP1 to SCP3 are register
programmable. During each region bounded by the SCP, the
SPTR registers designate which sequence is used by each signal.
CLPOB, PBLK, and HBLK each have a separate set of SCPs. For
example, CLPOBSCP1 defines Region 0 for CLPOB, and in that
region any of the four CLPOB sequences can be selected with
the CLPOBSPTR register. The next SCP defines a new region,
in which each signal can be assigned to a different individual se-
quence. The sequence control registers are detailed in Table 21.
HORIZONTAL SEQUENCE CONTROL
The AD9942 uses sequence change positions (SCPs) and
sequence pointers (SPTRs) to organize the individual horizontal
sequences. Up to four SCPs are available to divide the readout
TOG1
TOG2
TOG3
TOG4
TOG5
TOG6
HBLK
H1X/H3X
H2X/H4X
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
Figure 24. Generating Special HBLK Patterns
SINGLE FIELD (1 VD INTERVAL)
SEQUENCE CHANGE OF POSITION 0
(V COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 0
CLAMP AND PBLK SEQUENCE REGION 1
SEQUENCE CHANGE OF POSITION 1
SEQUENCE CHANGE OF POSITION 2
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 3
SEQUENCE CHANGE OF POSITION 3
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
Figure 25. CLPOB and PBLK Sequence Flexibility
Rev. A | Page 24 of 36
AD9942
Table 20. Channel A and Channel B HBLK Individual Sequence Parameters
Length
(Bit)
Parameter
Range
Description
HBLKMASK
1
High/low
Masking polarity for H1 for Sequences 0 to 3 (0 = low; 1 = high).
First toggle position within the line for Sequences 0 to 3.
Second toggle position within the line for Sequences 0 to 3.
Third toggle position within the line for Sequences 0 to 3.
Fourth toggle position within the line for Sequences 0 to 3.
Fifth toggle position within the line for Sequences 0 to 3.
Sixth toggle position within the line for Sequences 0 to 3.
Toggle Position 1
Toggle Position 2
Toggle Position 3
Toggle Position 4
Toggle Position 5
Toggle Position 6
12
12
12
12
12
12
0 to 4095 pixel locations
0 to 4095 pixel locations
0 to 4095 pixel locations
0 to 4095 pixel locations
0 to 4095 pixel locations
0 to 4095 pixel locations
Table 21. Channel A and Channel B Horizontal Sequence Control Registers for CLPOB, PBLK, and HBLK
Length
(Bit)
Register
SCP
SPTR
Range
Description
12
2
0 to 4095 line numbers
0 to 3 sequence numbers
CLPOB/PBLK/HBLK SCP to define Horizontal Regions 0 to 3.
Sequence pointer for Horizontal Regions 0 to 3.
Table 22. Channel A and Channel B External HBLK Register Parameters
Register
Length (Bit)
Range
Description
HBLKDIR
HBLKPOL
HBLKEXTMASK
1
1
1
High/low
High/low
High/low
Specifies HBLK internally generated or externally supplied. 0 = internal; 1 = external.
External HBLK active polarity. 0 = active low; 1 = active high.
External HBLK masking polarity. 0 = mask H1 low; 1 = mask H1 high.
H-COUNTER SYNCHRONIZATION
The H-counter reset occurs seven CLI cycles after the HD falling edge.
VD_X
HD_X
CLI_X
H-COUNTER
RESET
H COUNTER
(PIXEL COUNTER)
X
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
9
10 11 12 14 15
0
1
2
3
NOTES
1. INTERNAL H COUNTER IS RESET SEVEN CLI_X CYCLES AFTER THE HD_X FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI_X RISING EDGE IS COINCIDENT WITH HD_X FALLING EDGE.
Figure 26. H-Counter Synchronization
Rev. A | Page 25 of 36
AD9942
CHANNEL A AND CHANNEL B POWER-UP PROCEDURE
When the AD9942 is powered up, the following sequence is
recommended for Channel A and Channel B (see Figure 27 for
each step).
5. Write a 1 to the PREVENTUPDATE register (Address 0x14).
This prevents an update of the serial register data.
6. Write to the desired registers to configure high speed
timing and horizontal timing.
1. Turn on the power supplies for the AD9942.
2. Apply the master clock input, CLI_X, VD_X, and HD_X.
7. Write a 3 to the [7:6] TESTMODE register (Address 0x00).
See Table 15.
3. Although the AD9942 contains an on-chip power-on reset,
a software reset of the internal registers is recommended.
Write a 1 to the SW_RST register (Address 0x10), which
resets all the internal registers to their default values. This
bit is self-clearing and is automatically reset to 0.
8. Write a 1 to the OUT_CONTROL register (Address 0x11).
This allows the outputs to become active after the next
VD_X/HD_X rising edge.
9. Write a 0 to the PREVENTUPDATE register (Address 0x14).
This allows the serial information to be updated at the
next VD_X/HD_X falling edge. The next VD_X/HD_X
falling edge allows register updates, including updates of
OUT_CONTROL, to occur which enables all clock outputs.
4. Reset the Precision Timing core by writing a 0 to the
TGCORE_RSTB register (Address 0x12), then write a l to
the TGCORE_RSTB register. This starts the internal
timing core operation.
VDD
1
(INPUT)
CLI_X
(INPUT)
2
tPWR
3
4
5
6
7
8
SERIAL
WRITES
9
1V
...
...
...
VD_X
(OUTPUT)
ODD FIELD
EVEN FIELD
1H
2
...
HD_X
(OUTPUT)
H2X/H4X
DIGITAL
OUTPUTS
H1X/H3X, RG_X
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS
UPDATED AT VD/HD EDGE
Figure 27. Recommended Power-Up Sequence
Rev. A | Page 26 of 36
AD9942
CHANNEL A AND CHANNEL B ANALOG FRONT END OPERATION
The AD9942 signal processing chain is shown in Figure 28.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 17 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and the CCD signal level, respectively. The placement of
the SHP and SHD sampling edges is determined by the setting
of the SAMPCONTROL register located at Address 0x63.
Placement of these two clock signals is critical for achieving the
best performance from the CCD.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCDIN_X signal to
approximately 1.5 V to be compatible with the 3 V supply
voltage of the AD9942.
1.0µF 1.0µF
REFB_X
REFT_X
1.0V 2.0V
DC RESTORE
1.5V
AD9942
INTERNAL
V
REF
DOUT
PHASE
SHP
2V FULL SCALE
SHD
0dB ~ 18dB
OUTPUT
DATA
LATCH
14
CCDIN_X
ADC
DOUT
CDS
VGA1
1.0µF
OPTICAL BLACK
CLAMP
DAC
VGA GAIN
REGISTERS
CLPOB PBLK
DIGITAL
FILTER
DOUT
PHASE
8
SHP SHD
CLPOB PBLK
CLAMP LEVEL
REGISTER
PRECISION
V-H
TIMING
TIMING
GENERATION
GENERATION
Figure 28. Channel A and Channel B Analog Front End Functional Block Diagram
Rev. A | Page 27 of 36
AD9942
CHANNEL A AND CHANNEL B
VARIABLE GAIN AMPLIFIER
CHANNEL A AND CHANNEL B CLPOB
The CLPOB loop is used to remove residual offsets in the signal
chain and to track low frequency variations in the CCD black
level. During the optical black (OB), or shielded, pixel interval
on each line, the ADC output is compared with a fixed black
level reference, selected by the user in the CLAMP LEVEL
register. The value can be programmed between 0 LSB and 255
LSB in 256 steps. The resulting error signal is filtered to reduce
noise, and the correction value is applied to the ADC input
through a digital-to-analog converter. Typically, the CLPOB
loop is turned on once per horizontal line, but this loop can be
updated more slowly to suit a particular application. If external
digital clamping is used during postprocessing, the AD9942
CLPOB can be disabled using Bit D2 in the OPRMODE register.
The CLAMP LEVEL register can be used to provide program-
mable offset adjustment even when the loop is disabled.
The VGA stage provides a gain range of 0 dB to 18 dB, pro-
grammable with 9-bit resolution through the serial digital
interface. A minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value by
using the equation
Gain (dB) = (0.035 × VGAGAIN Code)
where the code range is 0 to 511.
20
18
16
14
12
10
8
The CLPOB pulse should be placed during the CCD’s OB pixel
region. It is recommended that the CLPOB pulse duration be at
least 20 pixels wide to minimize clamp noise. Shorter pulse widths
can be used, but clamp noise might increase and the ability to
track low frequency variations in the black level is reduced. See
the Channel A and Channel B Horizontal Clamping and
Blanking section and the Applications Information section for
timing examples.
6
4
2
0
CHANNEL A AND CHANNEL B
DIGITAL DATA OUTPUTS
0
50
100 150 200 250 300 350 400 450 500
GAIN CODE (Decimal)
Figure 29. VGA Gain Curve
The AD9942 digital output data is latched using the
DOUTPHASE register value, as shown in Figure 28. (Output
data timing is shown in Figure 19 and Figure 20.) It is also possible
to leave the output latches transparent, so that the data outputs
are valid immediately from the ADC. Programming the AFE
Control Register Bit D4 to 1 sets the output latches transparent.
The data outputs can also be disabled (three-stated) by setting
the AFE Control Register Bit D3 to 1.
CHANNEL A AND CHANNEL B ADC
The AD9942 uses a high performance ADC architecture, opti-
mized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB. The ADC
uses a 2 V input range. See Figure 8 and Figure 9 for typical
linearity and noise performance plots for the AD9942.
The data output coding is typically straight binary, but the
coding can be changed to gray coding by setting the AFE
Control Register Bit D5 to 1.
Rev. A | Page 28 of 36
AD9942
APPLICATIONS INFORMATION
CIRCUIT CONFIGURATION
GROUNDING/DECOUPLING RECOMMENDATIONS
The AD9942 recommended circuit configuration is shown in
Figure 30. Achieving good image quality from the AD9942
requires careful attention to the printed circuit board (PCB)
layout. All signals should be routed to maintain low noise
performance. The CCD_A and CCD_B output signals should
be directly routed to Pins A1 and A7, respectively, through a
0.1 μF capacitor. The master clock, CLI_X, should be carefully
routed to Pins A3 and A9 to minimize interference with the
CCDIN_X, REFT_X, and REFB_X signals.
As Figure 30 shows, a single ground plane is recommended
for the AD9942. This ground plane should be as continuous
as possible, particularly around the P-, AI-, and A-type pins,
to ensure that all analog decoupling capacitors provide the
lowest possible impedance path between the power and bypass
pins and their respective ground pins. All high frequency
decoupling capacitors should be located as close as possible
to the package pins.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There should also be
a 4.7 μF or larger bypass capacitor for each main supply—that
is, the AVDD_X, RGVDD_X, HVDD_X, and DRVDD_X—
although this is not necessary for each individual pin. In most
applications, it is easier to share the supply for RGVDD_X and
HVDD_X, which can be done as long as the individual supply
pins are separately bypassed. A separate 3 V supply can be used
for DRVDD_X, but this supply pin should still be decoupled to
the same ground plane as the rest of the chip. A separate ground
for DRVSS_X is not recommended.
The digital outputs and clock inputs should be connected to the
digital ASIC away from the analog and CCD clock signals.
Placing series resistors close to the digital output pins may help
to reduce digital code transition noise. If the digital outputs
must drive a load larger than 20 pF, buffering is recommended
to minimize additional noise. If the digital ASIC can accept gray
code, the AD9942 outputs can be selected to output data in gray
code format using the Control Register Bit D5. Gray coding
helps reduce potential digital transition noise compared with
binary coding.
The H1X to H4X and RG_X traces should have low inductance
to avoid excessive distortion of the signals. Heavier traces are
recommended because of the large transient current demand on
H1X to H4X from the capacitive load of the CCD. If possible,
physically locate the AD9942 closer to the CCD to reduce the
inductance on these lines. As always, the routing path should be
as direct as possible from the AD9942 to the CCD.
The reference bypass pins (REFT_X, REFB_X) should be
decoupled to ground as close as possible to their respective pins.
The analog input capacitor (CCDIN_X) should also be located
close to the pin.
The GND connections should be tied to the lowest impedance
ground plane on the PCB. Performance does not degrade if
several of these GND connections are left unconnected for
routing purposes.
The CLI_X and CCDIN_X PCB traces should be carefully
matched in length and impedance to achieve optimal channel-
to-channel matching performance.
Rev. A | Page 29 of 36
AD9942
3V ANALOG SUPPLY
RG_A OUTPUT
RG_A DRIVER SUPPLY
+
+
3V ANALOG SUPPLY
RG_B OUTPUT
RG_B DRIVER
SUPPLY
4.7µF
4.7µF
COMMON MASTER CLOCK INPUT
3V ANALOG SUPPLY
+
4.7µF
COMMON MASTER CLOCK INPUT
3V ANALOG
SUPPLY
+
0.1µF
4.7µF
CCDIN_A
REFB_A
REFT_A
SL_A
AVSS_B
CCDIN_B
REFB_B
REFT_B
SL_B
CHN_A CCD
SIGNAL
A1
D1
C1
B2
C2
D2
E1
E2
E4
E3
F4
F3
D4
D3
F1
F2
G1
H1
J1
B7
A7
D7
C7
B8
C8
D8
E7
E8
E10
E9
F10
F9
0.1µF
1.0µF
1.0µF
CHN_B CCD
SIGNAL
0.1µF
1.0µF
1.0µF
SERIAL
INTERFACE
FOR CHN_A
SDATA_A
SCK_A
HD_A
SDATA_B
SCK_B
HD_B
SERIAL
3
HD COMMON INPUT
VD COMMON INPUT
INTERFACE
FOR CHN_B
VD_A
HD COMMON INPUT
VD COMMON INPUT
H1A TO H4A
DRIVER
HVDD_A
HVSS_A
H1A
VD_B
H1B TO H4B
DRIVER
SUPPLY
4.7µF
0.1µF
4
HVDD_B
HVSS_B
H1B
SUPPLY
0.1µF
4.7µF
H1A TO H4A
OUTPUTS
H2A
4
H1B TO H4B
OUTPUTS
H3A
H2B
AD9942
H4A
H3B
D10
D9
F7
DVDD_A
DVSS_A
D0_A (LSB)
D1_A
H4B
3V ANALOG
SUPPLY
0.1µF
DVDD_B
DVSS_B
3V ANALOG
SUPPLY
0.1µF
F8
D0_B (LSB)
D1_B
G7
H7
J7
D2_A
D3_A
D2_B
K1
G2
H2
K2
G3
H3
D4_A
D3_B
K7
G8
H8
K8
G9
D5_A
D4_B
D6_A
D5_B
D7_A
D6_B
D8_A
D7_B
14
14
CHN_A DATA
OUTPUTS
CHN_B DATA
OUTPUTS
3V
DRIVER
3V
DRIVER
Figure 30. Recommended Circuit Configuration
Rev. A | Page 30 of 36
AD9942
DRIVING THE CLI INPUT
The AD9942 CLI can be used in two configurations, depending
on the application. Figure 31 shows a typical dc-coupled input
from the master clock source. When the dc-coupled technique
is used, the master clock signal should be at standard 3 V CMOS
logic levels. As shown in Figure 32, a 1000 pF ac coupling
capacitor can be used between the clock source and the CLI input.
In this configuration, the CLI input performs a self-bias to the
proper dc voltage level of approximately 1.4 V. When the ac-
coupled technique is used, the master clock signal can be as
low as 500 mV in amplitude.
10 OB lines at the front of the readout and 2 at the back of the
readout. The horizontal direction has 4 OB pixels in the front
and 48 in the back.
To configure the AD9942 horizontal signals for this CCD, three
sequences can be used. Figure 34 shows the first sequence to be
used during vertical blanking. During this time, there are no
valid OB pixels from the sensor, so the CLPOB signal is not
used. PBLK can be enabled during this time because no valid
data is available.
Figure 35 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines to
stabilize the clamp loop of the AD9942.
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 33 shows an example CCD configuration. The horizontal
register contains 28 dummy pixels, which occur on each line
clocked from the CCD. In the vertical direction, there are
Figure 36 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB signal.
AD9942
AD9942
CLI_X
LPF
CLI_X
ASIC
ASIC
1nF
MASTER CLOCK
MASTER CLOCK
Figure 31. CLI Connection, DC-Coupled
Figure 32. CLI Connection, AC-Coupled
SEQUENCE 2 (OPTIONAL)
2 VERTICAL OB LINES
USE SEQUENCE 3
EFFECTIVE IMAGE AREA
V
10 VERTICAL OB LINES
USE SEQUENCE 2
H
48 OB PIXELS
4 OB PIXELS
HORIZONTAL CCD REGISTER
28 DUMMY PIXELS
Figure 33. Example CCD Configuration
Rev. A | Page 31 of 36
AD9942
SEQUENCE 1: VERTICAL BLANKING LINES
CCDIN INVALID PIX
VERTICAL SHIFT
DUMMY
INVALID PIXELS
VERT SHIFT
SHP
SHD
H1X/H3X
H2X/H4X
HBLK
CLPOB
Figure 34. Horizontal Sequence During Vertical Blanking
SEQUENCE 2: VERTICAL OPTICAL BLACK LINES
OPTICAL
BLACK
VERTICAL SHIFT
DUMMY
OPTICAL BLACK
CCDIN
VERT SHIFT
SHP
SHD
H1X/H3X
H2X/H4X
HBLK
CLPOB
Figure 35. Horizontal Sequences During Vertical OB Pixels
SEQUENCE 3: EFFECTIVE PIXEL LINES
OPTICAL
BLACK
OPTICAL
BLACK
OPTICAL BLACK
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
VERT SHIFT
CCDIN
SHP
SHD
H1X/H3X
H2X/H4X
HBLK
CLPOB
Figure 36. Horizontal Sequences During Effective Pixels
Rev. A | Page 32 of 36
AD9942
OUTLINE DIMENSIONS
A1 CORNER
INDEX AREA
9.10
9.00 SQ
8.90
10
9
8
7
6
5
4
3
2 1
A
B
C
D
E
F
BALL A1
PAD CORNER
7.20
BSC SQ
TOP VIEW
G
H
J
K
0.80 BSC
DETAIL A
1.40 MAX
DETAIL A
0.65 MIN
0.25 MIN
COPLANARITY
0.12
0.55
0.50
0.45
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-205-AB.
Figure 37. 100-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9942BBCZ1
AD9942BBCZRL1
−25°C to +85°C
−25°C to +85°C
100-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
100-Lead Chip Scale Package Ball Grid Array [CSP_BGA]
BC-100-1
BC-100-1
1 Z = Pb-free part.
Rev. A | Page 33 of 36
AD9942
NOTES
Rev. A | Page 34 of 36
AD9942
NOTES
Rev. A | Page 35 of 36
AD9942
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05240-0-8/06(A)
Rev. A | Page 36 of 36
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