AD9957 [ADI]
1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC; 1 GSPS正交数字上变频器W / 18位IQ数据路径和14位DAC型号: | AD9957 |
厂家: | ADI |
描述: | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
文件: | 总38页 (文件大小:618K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
1 GSPS Quadrature Digital Upconverter
w/18-Bit IQ Data Path and 14-Bit DAC
AD9957
PRELIMINARY TECHNICAL DATA
FEATURES
GENERAL DESCRIPTION
1GSPS internal clock speed (up to 400MHz analog out)
Integrated 1GSPS 14-bit DAC
The AD9957 functions as a universal I/Q modulator and agile
upconverter for communications systems where cost, size,
power consumption and dynamic performance are critical. The
AD9957 integrates a high speed Direct Digital Synthesizer
(DDS), a high performance, high speed 14-bit digital to analog
converter (DAC), clock multiplier circuitry, digital filters and
other DSP functions onto a single chip. It provides for base
band up-conversion for data transmission in a wired or wireless
communications system.
250 MHz I/Q data throughput rate
Phase noise ≤ –123 dBc/Hz (400 MHz carrier)
Excellent dynamic performance >80 dB narrowband SFDR
8 Programmable Profiles for shift keying
SIN(X)/(X) Correction (Inverse SINC filter)
Reference Clock Multiplier
Internal oscillator for a single crystal operation
Software and hardware controlled power-down
Integrated RAM
The AD9957 is the third offering in a family of a quadrature
digital upconverters (QDUCs), which includes the AD9857 and
AD9856. It offers performance gains in operating speed, power
consumption and spectral performance. Unlike its predeces-
sors, it also supports a 16-bit serial input mode for I/Q base
band data. The device can alternatively be programmed to op-
erate as a single-tone sinusoidal source or as an interpolating
DAC.
Phase modulation capability
Multichip synchronization
Easy interface to Blackfin™ SPORT
Interpolation factors from 4x to 252x
Test tone circuitry
Interpolation DAC Mode
Gain control DAC
Internal divider allows references up to 2 GHz
1.8V & 3.3V Power Supplies
100 Lead TQFP package
The Reference Clock input circuitry includes a crystal oscillator,
a high speed divide-by-two input, and a low noise PLL for mul-
tiplication of the reference clock frequency.
APPLICATIONS
HFC Data, Telephony & Video Modems
Wireless Base Station Transmission
Broadband Communications Transmissions
Internet Telephony
The user interface to the control functions includes a serial port
easily configured to interface to the SPORT of the Blackfin DSP
and profile pins which enable fast and easy shift keying of any
signal parameter (phase, frequency, and amplitude).
Figure 1: Basic Block Diagram
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
AD9957
PRELIMINARY TECHNICAL DATA
TABLE OF CONTENTS
REFCLK: External Interface..............................19
Serial Programming.......................................... 21
Control Interface—Serial I/O..............................21
General Operation of the Serial Interface..........21
Instruction Byte ....................................................22
Serial Interface Port Pin Description..................22
MSB/LSB Transfers .............................................22
RAM IO via Serial Port .......................................23
RAm control Modes .............................................23
BAseband input scaling with RAM.....................23
I and q input data from ram................................23
Register Map and Descriptions......................... 24
REGISTER MAP .................................................24
Electrical Specifications ..................................... 3
Absolute Maximum Ratings ............................... 6
Pin Configuration ............................................... 7
Pin Description.................................................... 8
Modes of Operation........................................... 10
Quadrature Modulation Mode........................... 10
BlackFin Interface Mode .................................... 10
Signal Processing (QDUC & BFI modes) ...........11
PDCLK Pin ................................................................ 11
TxEnable Pin.............................................................. 11
Input Data Assembler.................................................12
Inverse CCI Filter.......................................................13
Fixed interpolator (4x)................................................13
Programmable Interpolating Filter .............................14
Quadrature Modulator................................................15
DDS Core...................................................................15
Inverse SINC Filter ....................................................15
Output Scale Factor (OSF).........................................15
14-Bit DAC ................................................................15
Auxiliary DAC...........................................................16
REGISTER DESCRIPTIONS ............................32
Control Function Register #1 (CFR1) ........................32
Control Function Register #2 (CFR2) ........................33
Control Function Register #3 (CFR3) ........................35
Auxilliary DAC Control Register...............................36
IO Update Rate Register.............................................36
QDUC RAM Segment Registers (QRSR0, QRSR1)..36
QRSRX<47:32> RAM Segment Address Ramp Rate
................................................................................36
Frequency Tuning Word Register (FTW)...................36
Phase Offset Word Register (POW)............................36
Amplitude Scale Factor (ASF) ...................................36
QDUC Profile X Register (QDUC-PXR)/..................36
Single Tone Profile X Register (ST-PXR) ..................36
Interpolating DAC Mode.................................... 16
Single-Tone Mode ................................................ 17
Amplitude Scale Factor (ASF)...................................17
I/O_UPDATE Pin.......................................................17
REFCLK Input.................................................. 19
REFCLK PLL...................................................... 19
REFCLK PLL with Crystal................................ 19
REVISION HISTORY
Revision PrA (5/25/05): Initial Version of Preliminary Datasheet
Revision PrB (9/30/05): Register map, pinout, pin description added
Revision PrC (12/06/05): Register map completed, pinout updated.
Revision PrD (2/27/06) Further progress
Revision PrE (3/31/06) Incorporated Marketing review comments
Rev. PrF | Page 2 of 38
PRELIMINARY TECHNICAL DATA
ELECTRICAL SPECIFICATIONS
AD9957
Table 1. Unless otherwise noted, AVDD, DVDD = 1.8V ꢀ%, DAC_VDD, DVDD_I/O = 3.3 V ꢀ%, RSET = 10kΩ, External
Reference Clock Frequency = 2ꢀ MHz. 40x REFLCK multiplier engaged.
Parameter
Min
Typ
Max
Unit
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled, Divider Disabled
REFCLK Multiplier Disabled, Divider Enabled
REFCLK Multiplier Enabled at 8×
REFCLK Multiplier Enabled at 64×
REFCLK Multiplier Enabled at 127×
XTAL frequency on REFCLK inputs
Input Capacitance
1
1000
2000
125
35
7.9
30
MHz
MHz
MHz
MHz
MHz
MHz
pF
52.5
6.5
3.3
20
3
Input Impedance
Duty Cycle
1.5
50
kΩ
%
Duty Cycle with REFCLK Multiplier Enabled
REFCLK Input Voltage Swing
REFCLK Input Power1
35
100
–15
65
1000
+3
%
mV pk-pk
dBm
0
DAC OUTPUT CHARACTERISTICS
Full Scale Output Current
Gain Error
10
–10
20
30
+10
0.6
mA
%FS
μA
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
1
2
5
LSB
LSB
pF
Residual Phase Noise @ 1 kHz Offset, 400 MHz AOUT
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled @ 127×
REFCLK Multiplier Enabled @ 64×
REFCLK Multiplier Enabled @ 8×
AC Voltage Compliance Range
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fout = 50 MHz
fout = 104 MHz
fout = 209 MHz
fout = 315 Mhz
fout = 403 MHz
–123
TBD
–105
–115
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
V
-0.5V
0.5V
TBD
TBD
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
TWO TONE INTERMODULATION DISTORTION (IMD)
fout = fout + 1.25 MHz
fout = 50 MHz
fout = 104 MHz
fout = 209 MHz
fout = 315 Mhz
TBD
TBD
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
fout = 403 MHz
NOISE SPECTRAL DENSITY (NSD) Single Tone
fout = 50 MHz
fout = 104 MHz
fout = 209 MHz
fout = 315 Mhz
TBD
TBD
TBD
TBD
TBD
dBm / Hz
dBm / Hz
dBm / Hz
dBm / Hz
dBm / Hz
fout = 403 MHz
Rev. PrF | Page 3 of 38
AD9957
PRELIMINARY TECHNICAL DATA
Parameter
Min
Typ
Max
Unit
NOISE SPECTRAL DENSITY (NSD) Continued
Eight Tone, 500KHz Tone Spacing
fout = 50 MHz
fout = 104 MHz
fout = 209 MHz
TBD
TBD
TBD
TBD
TBD
dBm / Hz
dBm / Hz
dBm / Hz
dBm / Hz
dBm / Hz
fout = 315 Mhz
fout = 403 MHz
MODULATOR CHARACTERISTICS (260MHz AOUT
Input Data: 10MS/s, QPSK, 4x Oversampled
I/Q Offset
55
65
0.4
dB
%
Error Vector Magnitude
1
Input Data: 10MS/s GMSK 4x Oversampled
I/Q Offset
Error Vector Magnitude
Input Data: 10MS/s 256-QAM 4x Oversampled
I/Q Offset
Error Vector Magnitude
TBD
TBD
TBD
TBD
dB
%
TBD
TBD
TBD
TBD
dB
%
Adjacent Channel Leakage Ratio (ACLR)
WCDMA with 3.84MHz BW, 5MHz Channel Spacing
fDAC=1GSPS, fOUT=200MHz
fDAC=1GSPS, fOUT=400MHz
TIMING CHARACTERISTICS
79
74
dB
dB
Parallel Data Bus
Maximum Frequency
250
2
2
4
0
MS/s
ns
ns
ns
ns
Minimum TxEnable Pulse Width Low
Minimum TxEnable Pulse Width High
Minimum Data Setup Time (TxEnable to PDClk)
Minium Data Hold Time (PDClk rising edge to data change)
Serial Control Bus
Maximum Frequency
25
2
Mbps
ns
ns
ns
ns
Minimum Clock Pulse Width Low
Minimum Clock Pulse Width High
Maximum Clock Rise/Fall Time
Minimum Data Setup Time DVDD_I/O = 3.3 V
Minimum Data Hold Time
7
7
3
0
ns
Maximum Data Valid Time
Wake-Up Time2
25
ns
Minimum Reset Pulse Width High
I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, PS0, PS1 to SYNCCLK Hold Time
Latency
5
4
0
SYSCLK Cycles3
ns
ns
I/O UPDATE to Frequency Change Propagation Delay
I/O UPDATE to Phase Offset Change Propagation Delay
I/O UPDATE to Amplitude Change Propagation Delay
CMOS LOGIC INPUTS
24
24
16
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
Logic 1 Voltage
2.2
V
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
0.8
12
12
V
3
2
μA
μA
pF
Rev. PrF | Page 4 of 38
PRELIMINARY TECHNICAL DATA
AD9957
Parameter
Min
Typ
Max
Unit
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage
Logic 0 Voltage
2.8
V
V
0.4
XTAL OUTPUT BUFFER SPECS
Logic 1 Voltage
1.6
V
Logic 0 Voltage
Output Current
TBD
TBD
V
mA
POWER CONSUMPTION
DVDD_I/O(3.3V) current consumption (QDUC mode)
DVDD(1.8V) current consumption (QDUC mode)
AVDD(3.3V) current consumption (QDUC mode)
AVDD(1.8V) current consumption (QDUC mode)
Single Tone Mode
Continuous Modulation 255x Interpolation
Continuous Modulation 4x Interpolation
Burst Modulation (25%) 255x Interpolation
Burst Modulation (25%) 4x Interpolation
Full-Sleep Mode
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
mW
500
TBD
TBD
TBD
TBD
TBD
150
1000
TBD
TBD
TBD
TBD
TBD
Inverse Sinc Filter Power Consumption
1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will
reduce the phase noise performance of the device.
2 Wake-up time refers to the recovery from analog power-down modes.
3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the ex-
ternal reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor.
If the reference clock multiplier and divider are not used, the SYSCLK frequency is the same as the external reference clock frequency.
Figure 2 Equivalent Input/Output (I/O) Circuits
Rev. PrF | Page 5 of 38
AD9957
PRELIMINARY TECHNICAL DATA
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Maximum Junction Temperature
AVDD(1.8V), DVDD(1.8V) supplies
150°C
2 V
AVDD(3.3V), DVDD_I/O(3.3V) supplies 4V
Digital Input Voltage)
Digital Output Current
Storage Temperature
Operating Temperature
Lead Temperature (10 sec Soldering)
θJA
–0.7 V to +4V
5 mA
–65°C to +150°C
–40°C to +85°C
300°C
38°C/W
θJC
15°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD Caution
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features pro-
prietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electro-
static discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or
loss of functionality.
Rev. PrF | Page 6 of 38
PRELIMINARY TECHNICAL DATA
AD9957
PIN CONFIGURATION
Rev. PrF | Page 7 of 38
AD9957
PRELIMINARY TECHNICAL DATA
PIN DESCRIPTION
Pin #
Mnemonic
I/O
Description
1, 24, 61, 72,
86, 87, 93, 97-
100
NC
Not Connected. Allow device pin to float.
2
PLL_LOOP_FILTER
AVDD (1.8V)
I
I
I
I
PLL loop filter compensation pin.
3, 6, 89, 92
74-77, 83
Analog Core VDD: 1.8V Analog Supply.
Analog DAC VDD: 3.3V Analog Supply.
Digital Core VDD: 1.8V Digital Supply.
AVDD (3.3V)
17, 23, 30, 47,
57, 64
DVDD (1.8V)
11, 15, 21, 28,
45, 56, 66
DVDD_I/O (3.3V)
AGND
I
I
Digital Input/Output VDD: 3.3V Digital Supply.
Analog Ground.
4, 5, 73, 78,
79, 82, 85, 88,
96
13, 16,22,
29,46,58,62,63
65
DGND
I
Digital Ground.
7
SYNC_IN+
I
Digital input (rising edge active). Synchronization signal from external master to
synchronize internal sub-clocks.
8
SYNC_IN-
I
Digital input (rising edge active). Synchronization signal from external master to
synchronize internal sub-clocks.
9
SYNC_OUT+
SYNC_OUT-
O
O
O
I
Digitaloutput (rising edge active). Synchronization signal from internal device sub-
clocks to synchronize external slave devices.
10
12
14
18
Digitaloutput (rising edge active). Synchronization signal from internal device sub-
clocks to synchronize external slave devices.
SYNC_SMP_ERR
MASTER _RESET
EXT_PWR_DWN
Digital output (active high). Sync sample error: A high on this pin indicates that the
AD9957 did not receive a valid sync signal on SYNC_I+/SYNC_I-.
Digital Input (active high). Master reset: clears all memory elements and sets registers
to default values.
I
Digital input (active high). External Power Down: A high level on this pin initates the
currently programmed power down mode. Please see the Power Down Modes section
of this document for further details. If unused, tie to ground.
19
20
PLL_LOCK
CCI_OVFL
D<17:0>
O
O
I
Digital output (active high). PLL_Lock: A high indicates the clock multiplier PLL has
acquired lock to the reference clock input.
Digital output (active high). CCI Overflow: A high indicates a CCI filter overflow. This
pin will remain high until the CCI overflow condition is cleared.
25-27, 31-39,
42-44, 48-50
Parallel data input bus (active high). These pins provide the interleaved 18 bit digital I
& Q vectors for the modulator to upconvert.
42
43
40
41
41
SPORT I-DATA
SPORT Q-DATA
PDCLK/TSCLK
TxENABLE
FS
I
In Blackfin interface mode, this pin serves as the I-data serial input.
I
In Blackfin interface mode, this pin serves as the Q-data serial input.
O
I
Digital output (clock) Parallel Data Clock see Signal Processing section for details
Digital input (active high). Transmit enable: see Signal Processing section for details
I
In Blackfin interface mode, this pin serves as the FS Input, to receive the RFS OUTPUT
signal from the ADSP BF533
51
ISFC
I
Digital input (active high). Input Scaling Function Control: Control for the RAM
amplitude scaling function. When this function is engaged, a high sweeps the
amplitude from the beginning RAM address to the end. A low sweeps the amplitude
from the end RAM address to the beginning.
52-54
55
PROFILE <2:0>
SYNC_CLK
I
Digital inputs (active high). Profile select pins: used to select one of eight
phase/frequency profiles for the DDS core (single-tone or carrier tone). Changing the
state of one of these pins will transfer the current contents of all I/O buffers to the
corresponding registers. State changes should be setup to the IO_SYNC_CLK pin.
O
Digital output (clock). Outputs System clock/4. The I/O_UPDATE and PROFILE<2:0>
pins should be setup to the rising edge of this signal.
Rev. PrF | Page 8 of 38
PRELIMINARY TECHNICAL DATA
AD9957
59
60
I/O_UPDATE
OSK
I
I
Digital input (active high). Input/Output update: A high on this pin transfers the
contents of the I/O buffers to the corresponding internal registers.
Digital input (active high). Output shaped keying: When the OSK features (manual or
automatic), this device controls the OSK function. In manual mode, it toggles the
multiplier between 0 (low) and the programmed amplitude scale factor (high). In
automatic mode, a low sweeps the amplitude down to zero, a high sweeps the
amplitude up to the amplitude scale factor.
67
SDIO
I/O
Digital input/output (active high). Serial data input/output: this pin can be either uni-
directional or bidirectional (default), depending on configuration settings. In
bidirectional serial port mode, this pin acts as the serial data input and output. In
unidirectional, it is an input only.
68
69
SDO
O
O
Digital output (active high). Serial Data output: this pinis only active in unidirectional
serial data mode. In this mode, it functions as the output. In bidirectional mode, this
pin is not operational and should be left floating.
SCLK
Digital clock (rising edge on write, falling edge on read). Serial data clock: this pin
provides the serial data clock for the control data path. Write operations to the
AD9957 use the rising edge. Readback operations from the AD9957 use the falling
edge.
70
71
CS
I
I
Digital input (active low) Chip Select: Bringing this pin low enables the AD9957 to
detect serial clock rising/falling edges. Bringing this pin high will cause the AD9957 to
ignore input on the serial data pins.
I/O_RESET
Digital input (active high) I/O Reset: Rather than resetting the entire device during a
failed communication cycle, when brought high this pin will reset the state machine of
the serial port controller and clear any I/O buffers that have been written since the last
I/O Update. When unused, tie this pin to ground to avoid accidental resets.
80
81
84
90
IOUT
O
O
O
I
Analog output (current mode): Open source DAC complementary output source.
Connect through 50Ω to AGND.
IOUT
Analog output (current mode): Open source DAC output source. Connect through
50Ω to AGND.
DAC_RSET
REF_CLK
Analog reference pin: programs the DAC output full scale reference current. Attach a
10KΩ resistor to AGND.
Analog input(active high): Reference CLK input. Can be driven by either an external
oscillator or a simple crystal when the internal oscillator is engaged.
91
94
CLK
I
Analog input(active high): Reference CLK input
REF_
XTAL_OUT
O
Analog output (active high). Crystal Output: Provides the output of the internal
oscillator’s response to a crystal.
95
XTAL_SEL
O
Crystal Select: selects the reference clock input mode when using the on-
chip PLL. Pulling this pin low allows the user to provide a reference clock
input to the PLL from an external source. Pulling this pin high enables
the on-chip XTAL buffer and allows the user to drive the reference input
clock with a crystal
Rev. PrF | Page 9 of 38
AD9957
PRELIMINARY TECHNICAL DATA
MODES OF OPERATION
to the AD9957. One 18-bit I word and one 18-bit Q word to-
gether comprise one internal sample. Each sample propagates
along the internal data pathway in parallel fashion.
The AD9957 has three basic operating modes:
• Quadrature modulation mode (default)
• Interpolating DAC mode
• Single-tone mode
The DDS core provides a quadrature (sine and cosine) local
oscillator signal to the quadrature modulator, where the I and Q
data are multiplied by the respective phase of the carrier and
summed together, producing a quadrature-modulated data
stream. This data stream is routed through Inverse SINC filter
(optionally) and the output scaling multiplier and then applied
to the 14-bit DAC which produces the quadrature-modulated
analog output signal. Note: The profile and I/O_UPDATE pins
are also synchronous to the PDCLK.
The active mode is selected via the QDUC Operating mode bits
(CFR1 <25:24>). The Inverse SINC filter is available in all three
modes.
QUADRATURE MODULATION MODE
A block diagram of the AD9957 operating in the quadrature
modulation mode is shown in Figure 3. In quadrature modula-
tion mode, both I and Q data paths are active and the parallel
data clock (PDCLK) serves to synchronize the input of I/Q data
Quadrature
Modulator
IS
AD9957
Halfband
AUX
DAC
(8-b)
0
1
8
Inv.
CCI
DAC
Gain
CCI
Filters
(1x -63x)
I
(4x)
DAC
Rset
cos( t+
)
)
3
1
PW
18
0
1
Iout
Iout
DA C
I/Q In
DDS
0
2
(14 -b)
FTW
x
sin(x)
sin( t+
OSF
Habd
1
0
Q
Inv.
CCI
C
Inverse
Sinc Filter
Fte
(16x)
4x
QS
0
Parallel Data
Tim ing &
PDClk
TxEn
0
1
Internal Clock Timing & Control
Clock
Multiplier
1
2
2
Control
RefClk
RefClk
Programming
Registers
Seria l I/O
Port
Po wer
Down
RAM
Control
FTW
PW
I Q
IS QS
OSF
3
2
2
2
Figure 3: Quadrature Modulation Mode
(unlike parallel operation, which uses 18-bit words). The
BlackFin Interface mode includes an additional pair of half
band filters in both the I and Q signal paths, increasing the in-
terpolation of the base band data by 4x relative to the normal
quadrature modulation mode.
BLACKFIN INTERFACE MODE
A subset of the quadrature modulation mode is the BlackFin
Interface (BFI) mode, which is shown in Figure 4. In this mode
a separate I and Q serial bit stream is applied to the base band
data port. The serial input provides for 16-bit I and Q words
Rev. PrF | Page 10 of 38
PRELIMINARY TECHNICAL DATA
AD9957
Quadrature
Modulator
IS
Halfband
AUX
DAC
(8-b)
Halfband
Filters
(4x)
8
0
Filters
Inv.
CCI
DAC
Gain
CCI
F
(4x)
(1x -63x)
1
I
O
R
M
A
T
T
E
R
DAC
Rset
cos( t+
)
)
3
1
PW
Fixed
Interpolators
I In
0
1
Iout
Iout
Programmable
Interpolators
DA C
DDS
0
2
(14 -b)
Q In
FTW
x
sin(x)
sin( t+
OSF
Halfband
Filters
(4x)
1
0
Q
Inv.
CCI
CC I
(1x - 63x)
Halfband
Filters
(4x)
Inverse Sinc
Filter
QS
0
Serial Data
Timing and
Control
PDClk
TxEn
0
1
Internal Clock Timing & Control
Clock
Multiplier
1
2
2
RefClk
RefClk
Programming
Registers
Serial I/O
Port
Po wer
Down
RAM
Control
FTW
PW
I Q
IS QS
OSF
3
2
2
2
Figure 4: Quadrature Modulation Mode -- BlackFin Interface
SIGNAL PROCESSING (QDUC & BFI MODES)
To better understand the operation of the AD9957 it is helpful
to follow the signal path in quadrature modulation mode from
the parallel data port to the output of the DAC, examining the
function of each block (refer to Figure 4).
TxEnable Pin
The rising edge of the TxENABLE signal is used to synchronize
the device. While TxENABLE is in the Logic 0 state, the device
ignores the data applied to the parallel port allowing the inter-
nal data path to be flushed by forcing zeros down the I and Q
data pathways. On the rising edge of TxENABLE, the device is
ready for the first I word. The first I word is latched into the
device coincident with the rising edge of PDCLK. The next
rising edge of PDCLK latches in a Q word, etc., until
All timing within the AD9957 is provided by the internal sys-
tem clock (SYSCLK) signal, which is generated from the timing
source provided to the REFCLK pins.
PDCLK Pin
The timing of input data supplied to the AD9957 is easily facili-
tated with the PDCLK output pin, which serves as a data clock
timing source. In QDUC mode, PDCLK controls the timing of
the 18-bit parallel input port. In BFI mode, PDCLK controls
the timing of the dual serial input port. The PDCLK is provided
as a continuous clock (i.e., always active). However, even
though the PDCLK output is active by default, it can be disabled
via the Enable PDCLK bit in the register map.
TxENABLE is set to a Logic 0 state by the user.
It is important that the user ensure an even number of PDCLK
intervals are observed during any given TxENABLE period. The
device must capture both an I and a Q sample before the data is
processed along the signal chain.
In BFI mode, operation of the TxENABLE pin is similar except
that instead of the rising edge marking the first "I word", it
marks the first I (and Q) bit in a serial frame.
In QDUC mode, the AD9957 expects alternating I and Q data
words at the parallel port (see Figure 5). Each rising edge of
PDCLK captures one 16-bit word; that is, two PDCLK cycles
per I/Q pair.. In BFI mode, the AD9957 expects two serial bit
streams each segmented into 16-bit words with each rising edge
of PDCLK indicating a new bit. In either case, the output clock
rate is fDATA as explained in the Input Data Assembler section.
It is important that the user ensure a multiple of 16 PDCLK
cycles are observed during any given TxENABLE period. The
device must capture a full 16-bit I and Q sample before the data
is processed along the signal chain.
The timing relationship between TxENABLE, PDCLK, and
Rev. PrF | Page 11 of 38
AD9957
PRELIMINARY TECHNICAL DATA
DATA is shown in Figure 5 and Figure 6.
TxENABLE
tDS
tDH
PDCLK
tDS
I
Q
I
Q
1
I
Q
N
D<13:0>
0
0
1
N
tDH
Figure 5. 18-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode
Table 3. Parallel Data Bus Timing
Symbol
tDS
tDH
Definition
Minimum
Data Setup Time
Data Hold Time
4 ns
0 ns
Figure 6: Dual Serial I/Q Bitstream Timing Diagram – BFI mode
Table 4: Serial Data Bus Timing
Symbol
tDS
tDH
Definition
Minimum
TBD
TBD
Data Setup Time
Data Hold Time
Input Data Assembler
When device is programmed to operate in BFI mode, the 18-bit
parallel input is converted to a dual serial input. That is, one
pin is assigned as the serial input for the "I" words and one pin
is assigned as the serial input for the "Q" words. The other 16
pins are not used in the BFI mode. Furthermore, each I and Q
word has 16-bit resolution (as compared with 18-bit resolution
in the non-BFI mode). In BFI mode, fDATA is the bit rate of the I
and Q data streams and is given by:
The input to the AD9957 is an 18-bit parallel data port in quad-
rature modulation mode (or a dual serial data port in the BFI
mode). It is assumed that two consecutive 18-bit words repre-
sent the real (I) and imaginary (Q) parts of a complex number
that has the form I+jQ. The 18-bit words are supplied to the
input of the AD9957 at a rate of:
fSYSCLK
(QDUC mode)
fDATA
=
fSYSCLK
2R
(BFI mode)
fDATA
=
R
Where fSYSCLK is the sample rate of the DAC and R is the interpo-
lation factor of the programmable interpolation filter.
Encoding and pulse shaping of symbols must be implemented
before the data is presented to the input of the AD9957. Data
Rev. PrF | Page 12 of 38
PRELIMINARY TECHNICAL DATA
AD9957
delivered to the input of the AD9957 may be formatted as either
twos-complement or unsigned binary (see the Data Format bit
in the register map). Furthermore, in BFI mode, the order of
the bit sequence can be set to either "MSB First" or "LSB First"
(via the BlackFin Bit Order bit in the register map).
Fixed interpolator (4x)
This block is a fixed 4× rate interpolator. It is implemented as a
cascade of two half-band filters. Together, the two half-band
filters provide a factor of four increase in the sampling rate,
while preserving the spectrum of the base band signal applied at
the input. Both half-band filters are linear phase filters, so that
virtually no phase distortion is introduced within the pass band
of the filters. Their combined insertion loss is 0.01 dB, thus
preserving the relative amplitude of the input signal.
Inverse CCI Filter
The inverse CCI (cascaded comb integrator) filter precompen-
sates the data to offset the slight attenuation gradient imposed
by the CCI filter (see the Programmable (2× to 63×) CCI Inter-
polating filter section). Data entering the first half-band filter
occupies a maximum band width of one-half fIQ as defined by
Nyquist (where fIQ is the sample rate at the input of the first
half-band filter). This is shown graphically in Figure 7.
The half-band filters are designed so that their composite per-
formance yields a usable pass band of 40% of the input sample
rate (0.2 on the frequency scale below). Within that pass band,
the ripple does not exceed 0.002 dB. The stop band extends
from 60% to 200% of the input sample rate (0.3 to 1.0 on the
frequency scale) and offers a minimum of 85 dB attenuation.
Figure 8 and Figure 9 show the composite response of the two
half-band filters.
If the CCI filter is employed, the inband attenuation gradient
could pose a problem for those applications requiring an ex-
tremely flat pass band. For example, if the spectrum of the data
as supplied to the AD9957 occupies a significant portion of the
one-half fDATA region, the higher frequencies of the data spec-
trum receives slightly more attenuation than the lower frequen-
cies (the worst-case overall droop from f=0 to ½fDATA is < 0.8
dB). The Inverse CCI filter has a response characteristic that is
the inverse of the CCI filter response over the ½fIQ region.
10
0
0.2
–10
–20
0.3
–30
–40
–50
–60
–70
–80
–85
–90
–100
–110
–120
–130
–140
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
FREQUENCY
Figure 8. Half-Band 1 and 2 Frequency Response; Frequency
Relative to HB1 Output Sample Rate
0.010
0.008
0.006
0.004
0.002
0
Figure 7. CCI Filter Response
The product of the two responses yields in an extremely flat
pass band ( 0.05 dB over the base band Nyquist band width),
thereby eliminating the inband attenuation gradient introduced
by the CCI filter. The cost is a slight attenuation of the input
signal of approximately 0.5 dB for a CCI interpolation rate of 2
and 0.8 dB for interpolation rates of 3 to 63.
–0.002
–0.004
–0.006
–0.008
–0.010
0
0.05
0.10
0.15
0.20
0.25
The Inverse CCI filter can be bypassed using the appropriate bit
in the register map. Even if it is enabled, it is automatically by-
passed if the CCI interpolation rate is 1×. When the Inverse
CCI filter is bypassed, power to the stage is turned off to reduce
power consumption.
RELATIVE FREQUENCY (HB1 OUTPUT SAMPLE RATE = 1)
Figure 9. Combined Half-Band 1 and 2 Pass Band Detail;
Frequency Relative to HB1 Output Sample Rate
Rev. PrF | Page 13 of 38
AD9957
PRELIMINARY TECHNICAL DATA
Knowledge of the frequency response of the half-band filters is
essential to understanding their impact on the spectral proper-
ties of the input signal. This is especially true when using the
quadrature modulator to upconvert a base band signal contain-
ing complex data symbols that have been pulse shaped.
Typical spectrum of a random symbol sequence
Nyquist
Band Width
To better understand this concept, consider that a complex
symbol is represented by a real (I) and imaginary (Q) compo-
nent. Thus, two digital words are required to represent a single
complex sample of the form: I+jQ. The sample rate associated
with a sequence of complex symbols will be referred to as fSYM-
BOL. If pulse shaping is applied to the symbols, then the sample
rate must necessarily be increased by some integer factor, M (a
consequence of the pulse shaping process). This new sample
rate with be referred to as fIQ, and is related to the symbol rate
by:
f
½fSYMBOL
fSYMBOL
2fSYMBOL
3fSYMBOL
Raised cosine
spectral mask
= 1
= 0
= 0.5
Sample rate for 2x
oversampled pulse shaping
f
½fSYMBOL
fSYMBOL
2fSYMBOL
4fSYMBOL
Half-band filter
response
fIQ = MfSYMBOL
Thus, fIQ is the rate at which complex samples must be supplied
to the input of the first half-band filter in both the "I" and "Q"
signal paths. NOTE: This rate is not to be confused with the rate
at which parallel data is supplied to the AD9957( fDATA ), which is
equal to 2fIQ.
Input sample rate of 1st
half-band filter
Output sample rate of 1st
half-band filter
f
0.4fIQ ½ fIQ
fIQ
2fIQ
Figure 10. Effect of the Excess Band width Factor (α)
Typically, pulse shaping is applied to the base band symbols via
a filter having a raised cosine response. In such cases, an excess
band width factor (α) is used to modify the band width of the
data where 0 ≤ α ≤ 1. A value of 0 causes the data band width to
correspond to ½fSYMBOL, while a value of 1 causes the data band
width to be extended to fSYMBOL. Figure 10 illustrates the rela-
tionship between α, the band width of the raised cosine re-
sponse, and the response of the first half-band filter.
The responses in Figure 10 are shown for the specific case of
M=2 (the interpolation factor for the pulse shaping operation).
In cases for which M>2, the location of the fIQ point on the half-
band response portion of the diagram shifts to the right, as it
must remain aligned with the corresponding MfSYMBOL point on
the frequency axis of the raised cosine spectral diagram. How-
ever, if fIQ shifts to the right, so does the half-band response,
proportionally.
The result is that the raised cosine spectral mask always lies
within the flat portion (DC to 0.4fIQ) of the pass band response
of the first half-band filter, regardless of the choice of α so long
as M>2. Therefore, for M>2, the first half-band filter has abso-
lutely no negative impact on the spectrum of the base band
signal when raised cosine pulse shaping is employed. However,
for the case of M=2, a problem can arise. This is highlighted by
the shaded area in the tail of the α=1 trace on the raised cosine
spectral mask diagram. Notice that this portion of the raised
cosine spectral mask extends beyond the flat portion of the
half-band response and will cause unwanted amplitude and
phase distortion as the signal passes through the first half-band
filter. To avoid this, simply ensure that α≤0.6 when M=2.
Programmable Interpolating Filter
The Programmable Interpolator is implemented as a CCI filter
with a low-pass frequency characteristic. It is programmable by
a 6-bit control word, giving a range of 2× to 63× interpolation.
Rev. PrF | Page 14 of 38
PRELIMINARY TECHNICAL DATA
AD9957
The Programmable Interpolator is bypassed when programmed
for an interpolation factor of 1. When bypassed, power to the
stage is removed and the Inverse CCI filter (see above) is also
bypassed, because its compensation is not needed in this case.
I/Q data. The DDS output is tuned using registers accessed via
the serial programming port. This allows for both precise tun-
ing of the carrier frequency and the ability to change frequency
instantaneously.
The output of the Programmable Interpolator is the data from
the 4× interpolator further upsampled by the CCI filter, ac-
cording to the rate chosen by the user. This results in the input
data being upsampled by a factor of 8× to 252× in steps of 4.
The equation relating output frequency (fOUT) of the AD9957
digital modulator to the frequency tuning word (FTW) and the
system clock (fSYSCLK) is
FTW
⎛
⎜
⎞
⎟
(4)
fOUT
=
f
SYSCLK
232
The transfer function of the CCI interpolating filter is
⎝
⎠
5
R−1
where FTW is a decimal number from 0 to 2,147,483,647
(231−1).
⎛
⎜
⎞
⎟
H( f ) =
e−j(2πfk)
(1)
∑
k=0
⎝
⎠
Solving for FTW yields:
where R is the programmed interpolation factor, and f is the
frequency relative to SYSCLK.
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
fOUT
(5)
32
⎜
FTW = round 2
Quadrature Modulator
fSYSCLK
The digital quadrature modulator stage shifts the frequency of
the base band spectrum of the incoming data stream up to the
desired carrier frequency (this process is known as up-
conversion).
The round() function means to round the result to the nearest
integer. For example, for fOUT = 41 MHz and fSYSCLK = 122.88
MHz, then FTW = 1,433,053,867 (556AAAAB hex).
Inverse SINC Filter
At this point the base band data, which was delivered to the
device at an I/Q sample rate of fIQ, has been upsampled to a rate
equal to the frequency of SYSCLK, making the data sampling
rate equal to the sampling rate of the carrier signal.
The sampled carrier data stream is the input to the digital-to-
analog converter (DAC) integrated onto the AD9957. The
DAC output spectrum is shaped by the characteristic sin(x)/x
(or SINC) envelope, due to the intrinsic zero-order hold effect
associated with DAC-generated signals. The SINC envelope is
well known and can be compensated for. This envelope restora-
tion function is provided by the Inverse SINC filter that pre-
cedes the DAC. By default, the filter is bypassed. It is enabled
via a bit in the register map. The inverse SINC function is im-
plemented as an FIR filter. It’s response characteristic is the
exact inverse of the SINC response. The Inverse SINC filter pre-
distorts the data prior to its arrival at the DAC. The correction
is only accurate for output frequencies up to approximately 40%
of SYSCLK. NOTE: The inverse SINC filter exhibits ~3.5dB of
insersion loss.
The frequency of the carrier signal is controlled numerically by
a Direct Digital Synthesizer (DDS). The DDS generates the de-
sired carrier frequency from the internal reference clock
(SYSCLK) very precisely. The carrier is applied to the I and Q
multipliers in quadrature fashion (90° phase offset) and
summed, yielding a data stream that represents the quadrature
modulated carrier.
The modulation is done digitally avoiding the phase offset, gain
imbalance and crosstalk issues commonly associated with ana-
log modulators. Note that the modulated “signal” is a number
stream sampled at the rate of SYSCLK, the same rate at which
the DAC is clocked.
Output Scale Factor (OSF)
Output amplitude is controlled using an 8-bit digital multiplier.
The 8-bit multiplier value is called the Output Scale Factor
(OSF) and is programmed via the appropriate control registers.
It is available for each of the eight profiles. The LSB weight is 2–
7, which yields a multiplier range of 0 to 1.9921875 (2-2-7). The
gain extends to nearly a factor of 2 to provide a means to over-
come the intrinsic loss through the modulator when operating
in the quadrature modulation mode. NOTE: Programming the
8-bit multiplier to unity gain (80h) bypasses the stage and reduces
power consumption.
The orientation of the modulated signal with respect to the
carrier is controlled by a spectral invert bit. This bit resides in
each of the four profile registers. By default, the time domain
output of the quadrature modulator takes the form:
(2)
I(t) × cos
When the spectral invert bit asserted, it becomes:
I(t) × cos ωt + Q(t) × sin ωt
DDS Core
(
ωt
)
− Q(t) × sin
(
ωt
)
(3)
(
)
( )
14-Bit DAC
The AD9957 incorporates an integrated 14-bit current-output
DAC. The output current is delivered as a balanced signal using
The Direct Digital Synthesizer (DDS) block generates the sine
and cosine carrier reference signals that digitally modulate the
Rev. PrF | Page 15 of 38
AD9957
PRELIMINARY TECHNICAL DATA
two outputs. The use of balanced outputs reduces the amount of
common-mode noise at the DAC output, increasing signal-to-
noise ratio. An external resistor (RSET) connected between the
DAC_RSET pin and the DAC ground (AGND_DAC) establishes
a reference current. The full-scale output current of the DAC
(IOUT) is produced as a scaled version of the reference current
(see the Auxiliary DAC section that follows).
the appropriate register map location sets IOUT according to the
following equation:
86.4
CODE
⎛
⎜
⎞
⎟
(6)
IOUT
=
1+
RSET
96
⎝
⎠
Where RSET is the value of the RSET resistor (in ohms) and CODE
is the 8-bit value supplied to the auxiliary DAC (default is 127).
For example, with RSET=10,000 and CODE=127, then
Proper attention should be paid to the load termination to keep the
output voltage within the specified compliance range, as voltages
developed beyond this range will cause excessive distortion and
might even damage the DAC output circuitry.
IOUT=20.07mA.
INTERPOLATING DAC MODE
A block diagram of the AD9957 operating in the interpolating
DAC mode is shown in Figure 11; grayed out items are inactive.
In this mode, the Q data path, DDS and modulator are all dis-
abled; only the I data path is active.
Auxiliary DAC
The full scale output current of the main DAC (IOUT) is con-
trolled by an 8-bit auxiliary DAC. An 8-bit code word stored in
AD9957: Interpolating DAC Mode
I
Halfband
Filters
(4x)
AUX
DAC
(8-b)
0
1
8
Inv.
CCI
DAC
Gain
CCI
(1x -63x)
DAC
Rset
cos(ωt+θ)
DDS
3
1
0
2
1
0
θ
PW
1
θ
18
0
1
I
Iout
Iout
DAC
(14-b)
I/Q In
F
ω
Q
x
R
0
sin(x)
sin(ωt+θ)
Halfband
Filters
(4x)
1
0
FTW
Inv.
CCI
CCI
(1x -63x)
Freq.
Ramp
Logic
OSF
R
0
Parallel Data
Timing &
Control
0
1
PDClk
TxEn
Internal Clock Timing & Control
Clock
Multiplier
1
2
2
RefClk
RefClk
Programming
Registers
Serial I/O
Port
Power
Down
RAM
Control
I
Q θ G F
3
2
2
2
Figure 11: Interpolating DAC Mode
interpolation rate. The interpolation hardware processes the
signal, by effectively performing an over-sample with zero-
stuffing operation. However, the original input spectrum re-
mains intact and the images that would otherwise occur from
the sample rate conversion process are suppressed by the inter-
polation signal chain.
As in the quadrature modulation mode, the PDCLK pin func-
tions as a clock which serves to synchronize the input of data to
the AD9957. The PDCLK rate is given below. Note that it oper-
ates at a rate that is half of that for the quadrature modulation
mode.
fSYSCLK
(Interpolating DAC mode)
fDATA
=
The PDCLK pin is an output and serves as a data clock timing
source. The output clock rate is fDATA as explained in the Input
Data Assembler section. Each PDCLK rising edge latches a data
word into the I data path.
4R
Because no modulation takes place, the spectrum of the data
supplied at the parallel port remains at base band. However, a
sample rate conversion takes place based on the programmed
Rev. PrF | Page 16 of 38
PRELIMINARY TECHNICAL DATA
AD9957
The timing relationship between TxENABLE, PDCLK, and
DATA is shown in Figure 12.
TxENABLE
tDS
tDH
PDCLK
tDS
I
I
I
I
I
I
D<13:0>
0
1
2
3
K – 1
K
tDH
Figure 12. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode
SINGLE-TONE MODE
AD9957: Single-Tone Mode
I
Halfband
Filters
(4x)
AUX
DAC
(8-b)
0
1
8
Inv.
CCI
DAC
Gain
CCI
(1x -63x)
DAC
Rset
cos(ωt+θ)
DDS
3
1
0
2
1
0
θ
PW
1
I
θ
18
0
1
Iout
Iout
DAC
(14-b)
I/Q In
F
ω
Q
x
R
0
sin(x)
sin(ωt+θ)
Halfband
Filters
(4x)
1
0
FTW
Inv.
CCI
CCI
(1x - 63x)
Freq.
R
Ramp
Logic
Q
0
Parallel Data
Timing &
Control
0
1
PDClk
TxEn
Internal Clock Timing & Control
Clock
Multiplier
1
2
2
RefClk
RefClk
Programming
Registers
Serial I/O
Port
Power
Down
RAM
Control
I
Q θ G F
3
2
2
2
Figure 13: Single-Tone Mode
plier range of 0 to 1.99993896484375 (1-2-14).
A block diagram of the AD9957 operating in the single-tone
mode is shown in Figure 13; grayed out items are inactive. In
this mode, both I and Q data paths are disabled from the 18-bit
parallel data port up to and including the modulator. The in-
ternal DDS core produces a signal whose frequency depends on
the programmed tuning word. The user may select either the
cosine (default) or sine output of the DDS. The sinusoid at the
DDS output can be scaled via a 14-bit amplitude scale factor
(ASF) and optionally routed through the Inverse SINC filter.
In addition to the ability to generate single tone signals in this
mode, the AD9957 can also provide 2-, 4-, or 8-level modula-
tion of frequency, phase, or amplitude by means of the eight
available profile registers and the Profile<0:2> pins.
I/O_UPDATE Pin
In the single-tone mode, the I/O_UPDATE pin serves as a sig-
nal update strobe. Frequency, phase and amplitude control
words for the DDS are programmed via the serial port (see the
Control Register description). The serial port is an asynchro-
nous interface; the I/O_UPDATE pin allows for synchroniza-
tion of the AD9957 output with external circuitry when new
frequency, phase, or amplitude values are programmed into the
on-chip profile registers. A rising edge initiates transfer of the
Amplitude Scale Factor (ASF)
Output amplitude is controlled by a 14-bit digital multiplier
called the Amplitude Scale Factor (ASF), which is programmed
via the appropriate control registers. It is available for each of
the eight profiles. The LSB weight is 2–14, which yields a multi-
Rev. PrF | Page 17 of 38
AD9957
PRELIMINARY TECHNICAL DATA
programmed data for the selected profile (see the Profile sec-
tion), thus resuming the frequency synthesis process with the
new values. NOTE: The transfer of programmed data from the
programming registers to the internal hardware is also accom-
plished by switching between profiles.
Rev. PrF | Page 18 of 38
PRELIMINARY TECHNICAL DATA
REFCLK INPUT
AD9957
must be selected. The VCO range is selected by programming
the VCO SEL bits, CFR3 <26:24>.. The charge pump current is
programmed through the ICP bits, CFR3<21:19>. See the regis-
ter map for Tables showing the available settings
The AD9957 supports a few methods for generating the internal
system clock. An on-chip oscillator circuit is available for initi-
ating a low frequency reference signal by connecting a crystal to
the clock input pins. The system clock may also be generated
using the internal, PLL-based reference clock multiplier, allow-
ing the part to operate with a low frequency clock source while
still providing a high update rate for the DDS and DAC. Using
the clock multiplier can impact the output phase noise charac-
teristics - for best phase noise performance, a clean, stable clock
with a high slew is required. A clock of frequency higher than
the maximum allowable clock rate can be used if the REFCLK
input divide by 2 is enabled using the REFCLK input divider
enable bit CFR3<15>.
Whenever the PLL clock multiplier is enabled or the multiplica-
tion value changed, the PLL must reacquire lock. Once lock is
achieved, the LOCK_DETECT signal will be output on pin 19.
While the PLL is out of lock, transmission in the QDUC is
gated off.
REFCLK PLL WITH CRYSTAL
The on-chip oscillator for crystal operation is enabled using
XTAL_SEL (pin 95). The XTAL_SEL pin is an analog input,
operating on 1.8V logic. With the on-chip oscillator enabled,
connecting an external crystal across the REF_CLK and
REF_CLKB inputs produces a low frequency reference clock.
The range of frequencies supported is listed in the specification
table.
REFCLK PLL
Enabling the PLL (via the PLL Enable Bit, CFR3<8>) allows
multiplication of the reference clock frequency. The multiplica-
tion factor in the clock multiplier is set by bits CFR3 <7:1> with
values ranging from 8 to 10 and 12 to 127 (decimal). Pro-
gramming CFR3<7:1> for values less than 8 or 11 is not valid
and will cause unpredictable device performance. The system
clock rate with the clock multiplier enabled is equal to the refer-
ence clock rate times the multiplication factor. When using the
clock multiplier, the correct VCO and charge pump current
A buffer outputs a regenerated REFCLK/crystal oscillator signal
on the XTAL_OUT pin (pin 94). Harmonic interference effects
may be mitigated using DRV slew rate control bits
CFR3<31:30>.
Table 5 summarizes the clock mode options. See the Register
Table/Map section for more detail.
System Clock
XTAL_SEL
Pin (95)
CFR1<7:1> PLL, Bits = M
12 ≤ M ≤ 127, or
8 ≤ M ≤ 10
PLL Enabled (CFR3<15>
(fSYS CLK
)
Min/Max Freq. Range (MHz)
High = 1.8 V logic
Yes CFR3<15>=1
fSYS CLK = fOSC × M
500 < fSYSCLK < 1000
High = 1.8 V logic
Low
M < 8, M=11, or
M > 127
12 ≤ M ≤ 127 or
8 ≤ M ≤ 10
No
fSYS CLK = FOSC
20 < fSYSCLK < 30
Yes CFR3<15> = 1
fSYS CLK = FREF CLK × M
500 < fSYSCLK < 1000
Low
M < 8, M=11, or
M > 127
No
fSYS CLK = FREF CLK
0 < fSYS CLK < 1000
Table 5 Clock Mode Options
REFCLK: EXTERNAL INTERFACE
1:1
BALUN
μF
μF
0.1
CLK
PIN 90
The reference clock input circuitry has two modes of operation.
The first mode configures it as an input buffer. In this mode, the
reference clock must be ac-coupled to the input due to internal
dc biasing. This mode supports either differential or single-
ended configurations. If single-ended mode is desired, CLKB
(Pin 91) should be decoupled to AVDD or AGND via a 0.1 μF
capacitor. The next three figures exemplify common reference
clock configurations for the AD9957.
REFERENCE
CLOCK
SOURCE
Ω
50
0.1
CLK
PIN 91
05252-032
Figure 14
The reference clock inputs can also support an LVPECL or
PECL driver as the reference clock source.
Rev. PrF | Page 19 of 38
AD9957
PRELIMINARY TECHNICAL DATA
μF
μF
0.1
CLK
PIN 90
22pF
LVPECL/
PECL
DRIVER
CLK
PIN 90
TERMINATION
25MHz
XTAL
CLK
PIN 91
CLK
PIN 91
0.1
05252-033
22pF
Figure 15
05252-034
For external crystal operation, both clock inputs must be dc-
coupled via the crystal leads and bypassed. Figure 16 shows the
configuration for using a crystal.
Figure 16
Rev. PrF | Page 20 of 38
PRELIMINARY TECHNICAL DATA
AD9957
SERIAL PROGRAMMING
There are two phases to a communication cycle with the AD9957.
Phase 1 is the instruction cycle, which is the writing of an instruc-
tion byte into the AD9957, coincident with the first eight SCLK
rising edges. The instruction byte provides the AD9957 serial port
controller with information regarding the data transfer cycle, which
is Phase 2 of the communication cycle. The Phase 1 instruction
byte defines whether the upcoming data transfer is read or write
and the serial address of the register being accessed
CONTROL INTERFACE—SERIAL I/O
The AD9957 serial port is a flexible, synchronous serial communi-
cations port allowing easy interface to many industry standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the Mo-
torola 6905/11 SPI and Intel 8051 SSR protocols.
The interface allows read/write access to all registers that configure
the AD9957. MSB first or LSB first transfer formats are supported.
In addition, the AD9957’s serial interface port can be configured as
a single pin I/O (SDIO), which allows a two-wire interface or two
unidirectional pins for in/out (SDIO/SDO), which enables a three
wire interface. Two optional pins (IORESET and CSB) enable
greater flexibility for system design-in of the AD9957.
The first eight SCLK rising edges of each communication cycle are
used to write the instruction byte into the AD9957. The remaining
SCLK edges are for Phase 2 of the communication cycle. Phase 2 is
the actual data transfer between the AD9957 and the system con-
troller. The number of bytes transferred during Phase 2 of the
communication cycle is a function of the register being accessed.
For example, when accessing the Control Function Register #2,
which is four bytes wide, Phase 2 requires that four bytes be trans-
ferred. If accessing the Amplitude Scale Factor Register, which is
two bytes wide, Phase 2 requires that two bytes be transferred. After
transferring all data bytes per the instruction, the communication
cycle is completed.
With the AD9957, the Instruction Byte specifies read/write opera-
tion and register address. Serial operations on the AD9957 occur
only at the register level, not the byte level due to the lack of byte
address space in the Instruction Byte.
For the AD9957, the serial port controller recognizes the register
address in the Instruction Byte and expects that all bytes of that
register will be accessed, otherwise, the serial port controller will be
out of sequence for the next write routine. However, one way to
write less bytes than required is to use the IORESET feature. The
IORESET function can be used to abort an IO operation and reset
the pointer in the serial port controller. After an IORESET, the next
byte will be the instruction byte. Every byte that is written prior to
the IORESET is preserved. Partial bytes are not preserved.
At the completion of any communication cycle, the AD9957 serial
port controller expects the next 8 rising SCLK edges to be the in-
struction byte of the next communication cycle.
All data input to the AD9957 is registered on the rising edge of
SCLK. All data is driven out of the AD9957 on the falling edge of
SCLK.
The Figures below are useful in understanding the general opera-
tion of the AD9957 Serial Port.
GENERAL OPERATION OF THE SERIAL INTERFACE
INSTRUCTION CYCLE
CS
DATA TRANSFER CYCLE
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
SDIO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Serial Port Writing Timing—Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
SDO
I
I
I
I
I
I
I
I
0
DON'T CARE
7
6
5
4
3
2
1
D
D
D
D
D
D
D
D
O0
O7
O6
O5
O4
O3
O2
O1
Rev. PrF | Page 21 of 38
AD9957
PRELIMINARY TECHNICAL DATA
3-Wire Serial Port Read Timing—Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Serial Port Write Timing—Clock Stall High
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
O0
7
6
5
4
3
2
1
0
O7
O6
O5
O4
O3
O2
O1
2-Wire Serial Port Read Timing—Clock Stall High
SDIO — Serial Data I/O. Data is always written into the
AD9957/10 on this pin. However, this pin can be used as a bi-
directional data line. Bit 7 of register address 0h controls the con-
figuration of this pin. The default is logic zero, which configures the
SDIO pin as bi-directional.
INSTRUCTION BYTE
The instruction byte contains the following information as shown
in the table below:
Instruction Byte Information
SDO — Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In the
case where the AD9957/10 operates in a single bi-directional I/O
mode, this pin does not output data and is set to a high impedance
state.
MSB
D6
Dꢀ
D4
D3
D2
D1
LSB
R/W
b
x
x
A4
A3
A2
A1
A0
R/-Wb—Bit 7 of the instruction byte determines whether a read or
write data transfer will occur after the instruction byte write. Logic
high indicates read operation. Logic zero indicates a write opera-
tion.
IORESET — Synchronizes the I/O port state machines without
affecting the addressable registers contents. An active high input on
the IORESET pin causes the current communication cycle to abort.
After IORESET returns low (Logic 0) another communication cycle
may begin, starting with the instruction byte write.
X, X—Bits 6 and 5 of the instruction byte are don’t care.
A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte deter-
mine which register is accessed during the data transfer portion of
the communications cycle.
MSB/LSB TRANSFERS
The AD9957/10 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the Control Function Register #1 <0>
bit. The default value of Control Function Register #1 <0> bit is low
(MSB first). When Control Function Register #1 <0> bit is set high,
the AD9957/10 serial port is in LSB first format. The instruction
byte must be written in the format indicated by Control Function
Register #1 <0> bit. That is, if the AD9957/10 is in LSB first mode,
the instruction byte must be written from least significant bit to
most significant bit.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK — Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9957/10 and to run the internal state ma-
chines. SCLK maximum frequency is 10 MHz.
CSB — Chip Select Bar. Active low input that allows more than one
device on the same serial communications line. The SDO and
SDIO pins will go to a high impedance state when this input is
high. If driven high during any communications cycle, that cycle is
suspended until CS is reactivated low. Chip Select can be tied low
in systems that maintain control of SCLK.
For MSB first operation, the serial port controller will generate the
most significant byte (of the specified register) address first fol-
lowed by the next lesser significant byte addresses until the IO op-
Rev. PrF | Page 22 of 38
PRELIMINARY TECHNICAL DATA
AD9957
eration is complete. All data written to (read from) the AD9957/10
must be (will be) in MSB first order. If the LSB mode is active, the
serial port controller will generate the least significant byte address
first followed by the next greater significant byte addresses until the
IO operation is complete. All data written to (read from) the
AD9957/10 must be (will be) in LSB first order.
tiplies the baseband data by nearly 1.0 (0.FFFF equates to .99985).
Invoke the input Data Scaling Mode using the RAM enable bit and
the RAM QDUC Evaluation bit, while in QDUC or interpolating
DAC mode. The Input Scale Factor Control (ISFC) pin is used to
start and stop the RAM controller. Two 48-bit registers are dedi-
cated for controlling the RAM segmentation and ramp rates. See
the QDUC RAM Segment #0 (QRSR0) and the QDUC RAM Seg-
ment #1 (QRSR1) registers in the register map.
RAM IO VIA SERIAL PORT
Accessing the RAM via the serial port is identical to any other se-
rial IO operation except that the number of bytes transferred is
determined by the address space between the beginning address
and the final address as specified in the current RAM Segment
Control Word (RSCW). The final address describes the most sig-
nificant word address for all IO transfers and the beginning address
specifies the least significant address.
I AND Q INPUT DATA FROM RAM
In the QDUC mode, the RAM can be configured to supply IQ data.
The RAM is partitioned as two 16-bit words. The two words are
routed to the baseband data pathway.
One word is routed to the "I" channel and the other word is
routed to the "Q" channel. This will allow the user to easily
generate a customized modulation waveform composed of up
to 1024 I/Q samples without the need for external support cir-
cuitry to supply data to the parallel input port. This feature is
an attempt to simplify the user’s design/debug process when the
device is incorporated into a new product design.
RAM IO supports MSB/LSB first operation. When in MSB first
mode, the first data byte will be for the most significant byte of the
memory address described by the final address with the remaining
three bytes making up the lesser significant bytes of that address.
The remaining bytes come in most significant to least significant,
destined for RAM addresses generated in descending order until
the final four bytes are written into the address specified as the
beginning address. When in LSB first mode, the first data byte will
be for the least significant byte of the memory (specified by the
beginning address) with the remaining three bytes making up the
greater significant bytes of that address. The remaining bytes come
in least significant to most significant, destined for RAM addresses
generated in ascending order until the final four bytes are written
into the memory address described by the final address. Of course,
the bit order for all bytes is least significant to most significant first
when in the LSB first bit is set. When the LSB first bit is cleared
(default) the bit order for all bytes is most significant to least sig-
nificant.
Synchronizing Multiple AD99ꢀ7s Devices
The AD9957 product includes circuitry that enables multiple
AD9957 products to be automatically synchronized to one an-
other. Multiple devices are considered synchronized when the
state of the clock generation state machines are identical for all
parts. Multiple part synchronization can be achieved by a sim-
ple connection of LVDS outputs on the master device to the
LVDS inputs of the slave device(s). Devices are configured as
master and slaves through programming bits, accessible via the
serial port.
RAM CONTROL MODES
BASEBAND INPUT SCALING WITH RAM
Pipeline Matching of the FTW, Phase Offset,
and Output Scaling
In QDUC and DAC interpolation modes, the baseband data may
be scaled via the 18x16 bit multiplier(s)(IS,QS), whose multiplicand
is driven by the RAM. This function offers the customer a means
of performing an arbitrary amplitude ramp up/down of the base-
band data. The ramp profile is generated at the input sample rate
and interpolated up to the DAC sample rate through the baseband
signal chain in the same manner as the I/Q data, significantly re-
ducing power dissipation.
The AD9957 offers a feature that enables the simultaneous applica-
tion of changes in frequency, phase and amplitude to be applied in
a manner that allows these parameters to be synchronized to the
specific pipe delays of the preceding logic blocks. This feature is
controllable via the serial port and is activated by writing the Match
Pipe Delays Active bit to a logic one.
Output Shaped On-Off Keying modes
In this configuration, the 32-bit RAM words are partitioned into
two 16-bit words. The data being used as a scale factor for the I/Q
words supplied by the user to the 18-bit parallel port. The RAM
words are accessed at the IQ sample rate (output rate of the data
assembler logic).
Auto and Manual shaped On-Off keying modes are supported.
AUTO mode generates a linear scale factor at a rate determined by
the Amplitude Ramp Rate Register (ARR), controlled by an exter-
nal pin (OSK). MANUAL mode allows the user to directly control
the output amplitude by writing the scale factor value into the Am-
plitude Scale Factor Register (ASFR).
The scale factor, driven from the RAM, is an unsigned value. All
zeros multiplies the baseband data by 0 (decimal) and FFFFh mul-
Rev. PrF | Page 23 of 38
AD9957
PRELIMINARY TECHNICAL DATA
REGISTER MAP AND DESCRIPTIONS
REGISTER MAP
Register
Name (Serial
Address)
Bit
Range
Bit 7
(MSB)
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value OR
Profile
Control
Function
Register 1
<31:24>
<23:16>
RAM
Enable
OPEN
RAM QDUC
Evaluation
OPEN
QDUC Operating Mode
00h
Manual
OSK
Inverse Sinc
Filter Enable
Clear CCI
Internal Profile Control
Enable Sine
Output
00h
CFR1
External
Control
(00h)
<15:8>
<7:0>
OPEN
Auto-Clear
Phase
Accum
OPEN
Clear Phase
Accum
Load ARR
@ I/O
update
Output
Shaped
Keying
Enable
Auto
00h
00h
00h
Output
Shaped
Keying
Digital
Power
Down
DAC Power
Down
Clock
Input
Power
Down
Aux DAC
Power Down
External
Power
Down
Mode
Auto
Power
Down
Enable
SDIO Input
Only
LSB First
Control
Function
Register 2
(CFR2)
<31:24> BlackFin
Interface
BlackFin Bit
Order
Black Fin
Early
OPEN
Mode
Active
Frame
Sync
Enable
(01h)
<23:16>
Internal
IO
Update
Active
Enable IO
Update
Clock
OPEN
Read
Effective
FTW
40h
<15:8>
<7:0>
IO Update Rate Control
PDCLK
Rate
Control
Data Format
OPEN
Enable
PDCLK
PDCLK
Clock
Invert
TxEnable
Invert
Q First Data
Pairing
08h
20h
Matched
Latency
Enable
Data
Assembler
Hold Last
Value
Sync
Sample
Error
FM Gain
Mask
Control
Function
Register 3
<31:24>
<23:16>
<15:8>
DRV0<1:0>
OPEN
OPEN
VCO SEL <2:0>
OPEN
1Fh
3Fh
40h
ICP<2:0>
REFCLK
Input
Divider
OPEN
PLL Enable
(CFR3)
(02h)
Disable
<7:0>
N:<6:0>
OPEN
00h
Auxilliary
DAC Control
Register
<31:24>
<23:16>
<15:8>
<7:0>
OPEN
00h
00h
00h
FFh
OPEN
OPEN
(03h)
FSC<7:0>
Rev. PrF | Page 24 of 38
PRELIMINARY TECHNICAL DATA
AD9957
Register
Name
(Serial
Bit Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bitꢀ
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value OR
Profile
Address)
IO Update
Rate
Register
<31:24>
<23:16>
<15:8>
IO Update Rate <31:24>
IO Update Rate <23:16>
IO Update Rate <15:8>
IO Update Rate <7:0>
FFh
FFh
(04h)
FFh
<7:0>
FFh
QDUC
RAM
Segment
Register #0
(05h)
<47:40>
<39:32>
<31:24>
<23:16>
RAM Segment 0 Address Ramp Rate <15:8>
RAM Segment 0 Address Ramp Rate <7:0>
RAM Segment 0 Final Address <9:2>
OPEN
ISFC0
ISFC0
ISFC0
ISFC0
RAM Segment 0 Final
Address <1:0>
<15:8>
<7:0>
RAM Segment 0 Beginning Address <9:2>
ISFC0
ISFC0
RAM Segment 0
OPEN
RAM Segment 0 Mode Control <2:0>
Beginning Address <1:0>
QDUC
RAM
Segment
Register #1
(06h)
<47:40>
<39:32>
<31:24>
<23:16>
RAM Segment 1 Address Ramp Rate <15:8>
RAM Segment 1 Address Ramp Rate <7:0>
RAM Segment 1 Final Address <9:2>
OPEN
ISFC1
ISFC1
ISFC1
ISFC1
RAM Segment 1 Final
Address <1:0>
<15:8>
<7:0>
RAM Segment 1 Beginning Address <9:2>
ISFC1
ISFC1
RAM Segment 1
OPEN
RAM Segment 1 Mode Control <2:0>
Beginning Address <1:0>
FTW
Register
(07h)
<31:24>
<23:16>
<15:8>
<7:0>
Frequency Tuning Word <31:24>
Frequency Tuning Word <23:16>
Frequency Tuning Word <15:8>
Frequency Tuning Word <7:0>
00h
00h
00h
00h
POW
Register
(08h)
<15:8>
<7:0>
Phase Offset Word <15:8>
Phase Offset Word <7:0>
00h
00h
ASF
Register
(09h)
<31:24>
<23:16>
<15:8>
<7:0>
Amplitude Ramp Rate <15:8>
Amplitude Ramp Rate <7:0>
Amplitude Scale Factor <13:6>
00h
00h
00h
00h
Amplitude Scale Factor <5:0>
Amplitude Ramp Rate
Speed Control <1:0>
Rev. PrF | Page 25 of 38
AD9957
PRELIMINARY TECHNICAL DATA
Register
Name
(Serial
Bit Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bitꢀ
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Value
Address)
Multi-Chip
Sync
Register
<31:24>
Sync Window Delay <3:0>
Sync
Enable
Sync
Driver
Enable
Sync
Polarity
Internal
Sync Loop
Enable
00h
(0Ah)
<23:16>
<15:8>
<7:0>
System Clock Offset<5:0>
Output Sync Pulse Delay <4:0>
Input Sync Pulse Delay <4:0>
OPEN
00h
00h
00h
00h
00h
00h
000
OPEN
OPEN
<23:16>
<15:8>
<7:0>
Falling Sweep Ramp Rate Word <7:0>
Rising Sweep Ramp Rate Word <15:8>
Rising Sweep Ramp Rate Word <7:0>
QDUC
Profile 0
Register
<63:56>
CCI Interpolation Rate
Spectral
Invert
Inverse
CCI Bypass
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Output Scale Factor #0
000
000
000
000
000
000
000
001
Phase Offset Word #0 <15:8>
(0Eh)
Phase Offset Word #0 <7:0>
Frequency Tuning Word #0 <31:24>
Frequency Tuning Word #0 <23:16>
Frequency Tuning Word #0 <15:8>
Frequency Tuning Word #0 <7:0>
<7:0>
QDUC
Profile 1
Register
<63:56>
CCI Interpolation Rate
Spectral
Invert
Inverse
CCI Bypass
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
<7:0>
Output Scale Factor #1
001
001
001
001
001
001
001
Phase Offset Word # 1 <15:8>
Phase Offset Word #1 <7:0>
(0Fh)
Frequency Tuning Word #1 <31:24>
Frequency Tuning Word #1 <23:16>
Frequency Tuning Word #1 <15:8>
Frequency Tuning Word #1 <7:0>
Rev. PrF | Page 26 of 38
PRELIMINARY TECHNICAL DATA
AD9957
Register
Name
(Serial
Bit Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Profile Pins
(PS2 -
>PS0)
Address)
QDUC
Profile 2
Register
<63:56>
CCI Interpolation Rate
Spectral
Invert
Inverse
CCI Bypass
010
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Output Scale Factor #2
010
010
010
010
010
010
010
011
Phase Offset Word #2 <15:8>
(10h)
Phase Offset Word #2 <7:0>
Frequency Tuning Word #2 <31:24>
Frequency Tuning Word #2 <23:16>
Frequency Tuning Word #2 <15:8>
Frequency Tuning Word #2 <7:0>
<7:0>
QDUC
Profile 3
Register
<63:56>
CCI Interpolation Rate
Spectral
Invert
Inverse
CCI Bypass
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Output Scale Factor #3
011
011
011
011
011
011
011
100
Phase Offset Word # 3 <15:8>
Phase Offset Word #3 <7:0>
(11h)
Frequency Tuning Word #3 <31:24>
Frequency Tuning Word #3 <23:16>
Frequency Tuning Word #3 <15:8>
Frequency Tuning Word #3 <7:0>
<7:0>
QDUC
Profile 4
Register
<63:56>
CCI Interpolation Rate
Spectral
Invert
Inverse
CCI Bypass
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
<7:0>
Output Scale Factor #4
100
100
100
100
100
100
100
Phase Offset Word #4 <15:8>
(12h)
Phase Offset Word #4 <7:0>
Frequency Tuning Word #4 <31:24>
Frequency Tuning Word #4 <23:16>
Frequency Tuning Word #4 <15:8>
Frequency Tuning Word #4 <7:0>
Rev. PrF | Page 27 of 38
AD9957
PRELIMINARY TECHNICAL DATA
Register
Name
(Serial
Bit Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Profile Pins
(PS2 -
>PS0)
Address)
QDUC
Profile 5
Register
<63:56>
CCI Interpolation Rate
Spectral
Invert
Inverse
CCI Bypass
101
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Output Scale Factor #5
101
101
101
101
101
101
101
110
Phase Offset Word # 5 <15:8>
Phase Offset Word #5 <7:0>
(13h)
Frequency Tuning Word #5 <31:24>
Frequency Tuning Word #5 <23:16>
Frequency Tuning Word #5 <15:8>
Frequency Tuning Word #5 <7:0>
<7:0>
QDUC
Profile 6
Register
<63:56>
CCI Interpolation Rate
Spectral
Invert
Inverse
CCI Bypass
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Output Scale Factor #6
110
110
110
110
110
110
110
111
Phase Offset Word #6 <15:8>
(14h)
Phase Offset Word #6 <7:0>
Frequency Tuning Word #6 <31:24>
Frequency Tuning Word #6 <23:16>
Frequency Tuning Word #6 <15:8>
Frequency Tuning Word #6 <7:0>
<7:0>
QDUC
Profile 7
Register
<63:56>
CCI Interpolation Rate
Spectral
Invert
Inverse
CCI Bypass
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
<7:0>
Output Scale Factor #7
111
111
111
111
111
111
111
Phase Offset Word # 7 <15:8>
Phase Offset Word #7 <7:0>
(15h)
Frequency Tuning Word #7 <31:24>
Frequency Tuning Word #7 <23:16>
Frequency Tuning Word #7 <15:8>
Frequency Tuning Word #7 <7:0>
Rev. PrF | Page 28 of 38
PRELIMINARY TECHNICAL DATA
AD9957
Register
Name
(Serial
Bit Range
(Internal
Address)
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Profile Pins
(PS2 -
>PS0)
Address)
RAM (16h)
<31:0>
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
RAM [1023:0] <31:0>
Amplitude Scale Factor #0 <13:8>
Amplitude Scale Factor #0 <7:0>
***
000
000
000
000
000
000
000
000
001
001
001
001
001
001
001
001
010
010
010
010
010
010
010
010
QDUC
Single Tone
Profile 0
OPEN
Register
Phase Offset Word #0 <15:8>
Phase Offset Word #0 <7:0>
(0Eh)
Frequency Tuning Word #0 <31:24>
Frequency Tuning Word #0 <23:16>
Frequency Tuning Word #0 <15:8>
Frequency Tuning Word #0 <7:0>
<7:0>
QDUC
Single Tone
Profile 1
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
OPEN
Amplitude Scale Factor #1 <13:8>
Amplitude Scale Factor #1 <7:0>
Phase Offset Word #1 <15:8>
Register
(0Fh)
Phase Offset Word #1 <7:0>
Frequency Tuning Word #1 <31:24>
Frequency Tuning Word #1 <23:16>
Frequency Tuning Word #1 <15:8>
Frequency Tuning Word #1 <7:0>
<7:0>
QDUC
Single Tone
Profile 2
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
OPEN
Amplitude Scale Factor #2 <13:8>
Amplitude Scale Factor #2 <7:0>
Phase Offset Word #2 <15:8>
Register
(10h)
Phase Offset Word #2 <7:0>
Frequency Tuning Word #2 <31:24>
Frequency Tuning Word #2 <23:16>
Frequency Tuning Word #2 <15:8>
Frequency Tuning Word #2 <7:0>
<7:0>
Rev. PrF | Page 29 of 38
AD9957
PRELIMINARY TECHNICAL DATA
Register
Name
(Serial
Bit Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Profile Pins
(PS2 -
>PS0)
Address)
QDUC
Single Tone
Profile 3
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
OPEN
OPEN
OPEN
Amplitude Scale Factor #3 <13:8>
011
011
011
011
011
011
011
011
100
100
100
100
100
100
100
100
101
101
101
101
101
101
101
101
Amplitude Scale Factor #3 <7:0>
Phase Offset Word #3 <15:8>
Register
(11h)
Phase Offset Word #3 <7:0>
Frequency Tuning Word #3 <31:24>
Frequency Tuning Word #3 <23:16>
Frequency Tuning Word #3 <15:8>
Frequency Tuning Word #3 <7:0>
<7:0>
QDUC
Single Tone
Profile 4
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Amplitude Scale Factor #4 <13:8>
Amplitude Scale Factor #4 <7:0>
Phase Offset Word #4 <15:8>
Register
(12h)
Phase Offset Word #4 <7:0>
Frequency Tuning Word #4 <31:24>
Frequency Tuning Word #4 <23:16>
Frequency Tuning Word #4 <15:8>
Frequency Tuning Word #4 <7:0>
<7:0>
QDUC
Single Tone
Profile 5
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
Amplitude Scale Factor #5 <13:8>
Amplitude Scale Factor #5 <7:0>
Phase Offset Word #5 <15:8>
Register
(13h)
Phase Offset Word #5 <7:0>
Frequency Tuning Word #5 <31:24>
Frequency Tuning Word #5 <23:16>
Frequency Tuning Word #5 <15:8>
Frequency Tuning Word #5 <7:0>
<7:0>
Rev. PrF | Page 30 of 38
PRELIMINARY TECHNICAL DATA
AD9957
Register
Name
(Serial
Bit Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Profile Pins
(PS2 -
>PS0)
Address)
QDUC
Single Tone
Profile 6
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
OPEN
Amplitude Scale Factor #6 <13:8>
110
110
110
110
110
110
110
110
111
111
111
111
111
111
111
111
Amplitude Scale Factor #6 <7:0>
Phase Offset Word #6 <15:8>
Register
(14h)
Phase Offset Word #6 <7:0>
Frequency Tuning Word #6 <31:24>
Frequency Tuning Word #6 <23:16>
Frequency Tuning Word #6 <15:8>
Frequency Tuning Word #6 <7:0>
<7:0>
QDUC
Single Tone
Profile 7
<63:56>
<55:48>
<47:40>
<39:32>
<31:24>
<23:16>
<15:8>
OPEN
Amplitude Scale Factor #7 <13:8>
Amplitude Scale Factor #7 <7:0>
Phase Offset Word #7 <15:8>
Register
(15h)
Phase Offset Word #7 <7:0>
Frequency Tuning Word #7 <31:24>
Frequency Tuning Word #7 <23:16>
Frequency Tuning Word #7 <15:8>
Frequency Tuning Word #7 <7:0>
<7:0>
Rev. PrF | Page 31 of 38
AD9957
PRELIMINARY TECHNICAL DATA
REGISTER DESCRIPTIONS
Control Function Register #1 (CFR1)
CFR1<21>: Clear CCI bit.
The CFR1 is comprised of four bytes located in address 00h.
When CFR1<21> = 0 (default), the CCI filter operates
normally.
CFR1<31>: RAM Enable bit.
When CFR1<31>= 0 (default), disables the RAM putting
it in the lowest power state (unless being written to via
the serial port).
When CFR1<21> = 1, The CCI filter is asynchronously
cleared.
CFR1<20:17>: Internal Profile Control bits.
When CFR1<31> = 1, enables the RAM.
CFR1<30:29>: OPEN. Always leave these bits clear.
CFR1<28>: RAM QDUC Evaluation Enable bit.
These bits cause the Profile Bits to be ignored and put
the device into an automatic “profile loop sequence” that
allows the user to implement a frequency/phase compos-
ite sweep that runs without external inputs.
When CFR1<28> = 0 (default), The RAM QDUC
evaluation mode of the device is inactive.
CFR1<16>: Sine Enable bit.
When CFR1<16> = 0 (default), the angle-to-amplitude
conversion logic outputs a COSINE function.
When CFR1<28> = 1, The RAM QDUC evaluation
mode is activated, if the RAM Enable bit is set. When in
the RAM QDUC Evaluation mode the input data port is
disengaged form the signal processing path and the
RAM drives the I and Q data at the IQ sample rate.
When CFR1<16> = 1, the angle-to-amplitude conver-
sion logic outputs a SINE function.
CFR1<1ꢀ:14>: OPEN. Always leave these bits clear.
CFR1<27:26>: OPEN. Always leave these bits clear.
CFR1<2ꢀ:24>: QDUC Operating Mode bits.
The CFR1<25:24> bits set the mode of operation:
CFR1<13>: Auto Clear Phase Accumulator
When CFR1<13> = 0 (default), ), the accumulation
function is not interrupted.
CFR1<2ꢀ:24>
00 (default)
Mode of Operation
Quadrature Modulation
Single Tone
When CFR1<13> = 1, this bit automatically and syn-
chronously clears (loads zeros into) the phase accumula-
tor for one cycle upon receipt of the I/O UPDATE se-
quence indicator.
01
1x
CFR1<12>: OPEN. Always leave this bit clear.
Interpolating DAC
CFR1<11>: Clear Phase Accumulator
CFR1<23>: Manual OSK External Control.
When CFR1<11> = 0 (default), the phase accumulator
functions as normal.
Note, this bit is ignored unless manual OSK mode is se-
lected using CFR1<9:8>.
When CFR1<11> = 1, the phase accumulator memory
element is asynchronously cleared.
When CFR1<23> = 0 (default), the manual OSK mode
does not require the use of the OSK input pin to operate.
CFR1<10>: Load Amplitude Rate Register @ IOUpdate
When CFR1<23> = 1, the manual OSK mode uses the
OSK input pin. See pin description.
When CFR1<10> = 0 (default), the amplitude ramp rate
timer is loaded only upon timeout (timer ==1); it is not
loaded due to an I/O UPDATE input signal (or change
in profile).
CFR1<22>: Inverse Sinc Enable bit.
When CFR1<22> = 0 (default), the inverse sinc filter is
inactive - the local clock is stopped to save power. The
input data is passed directly to the output of the filter.
When CFR1<10> = 1, the amplitude ramp rate timer is
loaded upon timeout (timer ==1) or at the time of an
I/O UPDATE input signal (or change in profile).
When CFR1<22> = 1, the inverse sinc filter is enabled
and operational.
CFR1<9>: Output Shaped Keying Enable
Rev. PrF | Page 32 of 38
PRELIMINARY TECHNICAL DATA
AD9957
CFR1<9> = 0 (default), disables Shaped On-Off Keying.
The clocks to this function are stopped for power sav-
ings.
matically switches into its low power mode.
CFR1<1>: SDIO Input Only
CFR1<1> = 0 (default), configures the SDIO pin for bi-
directional operation (2-wire serial programming
mode).
CFR1<9> = 1, enables Shaped On-Off Keying.
CFR1<8> sets the mode of operation.
CFR1<8>: Automatic Output Shaped Keying Enable
If CFR1<9> is clear, this bit is ignored.
CFR1<1> = 1, configures the serial data I/O pin (SDIO)
as an input only pin (3-wire serial programming mode).
CFR1<8> = 0 enables MANUAL Shaped On-Off Keying.
CFR1<8> = 1 enables AUTO Shaped On-Off Keying.
CFR1<7>: Digital Power Down
CFR1<0>: LSB First
CFR1<0> = 0 (default), sets MSB first format.
CFR1<0> = 1, sets LSB first format.
Control Function Register #2 (CFR2)
CFR2<31>: BlackFin Interface Mode Active bit.
CFR1<7> = 0 (default), enables the digital circuitry.
CFR1<7> = 1, disables the digital circuitry, putting it in
its’ lowest power dissipation state.
When CFR2<31>= 0 (default), the parallel input data
port operates as described in the data assembler section
of this document.
CFR1<6>: DAC Power Down
CFR1<6> = 0 (default), enables the DAC Circuitry.
When CFR2<31> = 1, the AD9957 data port is config-
ured for direct connection to the BlackFin SPORT inter-
face. See the BlackFin Interface section of this document
for details.
CFR1<6> = 1, disables the DAC Circuitry, putting it in a
low power dissipation state.
CFR1<ꢀ>: Clock Input Power Down
CFR2<30>: BlackFin Bit Order bit.
CFR1<5> = 0 (default), enables the Clock Input Cir-
cuitry.
This bit is ignored if the AD9957 is not operating in the
BlackFin Interface Mode (see CFR2<31>).
CFR1<5> = 1, disables the Clock Input Circuitry putting
it in a low power dissipation state.
CFR2<30>= 0 (default) sets MSB first format.
CFR2<30> = 1 sets LSB first format.
CFR1<4>: Open
CFR2<29>: BlackFin Early Frame Sync Enable bit.
CFR1<3>: External Power Down Mode
This bit is ignored if the AD9957 is not operating in the
BlackFin Interface Mode (see CFR2<31>).
When CFR1<3> = 0 (default) the external power down
mode selected is “fast recovery power down”. In this
mode, when the EXTPWRDWN input pin is high, the
digital logic and the DAC digital logic are powered
down. The DAC bias circuitry, comparator, PLL, oscilla-
tor, and clock input circuitry is NOT powered down.
When CFR2<29>= 0 (default), the frame sync signal is
expected by the AD9957 to be co-incident with the first
data bit transmitted. (‘Late frame sync operation’ in the
Blackfin documentation).
When CFR1<3> = 1, the external power down mode se-
lected is “full power down”. In this mode, when the
EXTPWRDWN input pin is high, all functions are pow-
ered down including the DAC and PLL, which take a
significant amount of time to power up.
When CFR2<29> = 1, the frame sync signal is expected
by the AD9957 to be one cycle preceding the first data
bit transmitted. (‘Early frame sync operation’ in the
Blackfin documentation). Also, for continuous data
transmission, the early frame sync bit will be co-incident
with the last bit of the previous word transmitted.
CFR1<2>: Automatic Power Down
CFR2<28:2ꢀ>: Open. Leave these bits clear
CFR2<24>: Single Tone Profile Enable bit.
When CFR2<24>= 0 (default), direct modulation of
CFR1<2> = 0 (default), disables automatic power down.
When CFR1<2> = 1 when TX ENABLE is de-asserted
for a sufficiently long period of time the device auto-
Rev. PrF | Page 33 of 38
AD9957
PRELIMINARY TECHNICAL DATA
amplitude via the profile registers is not possible.
PDCLK pin is equal to the input data rate.
When CFR2<24> = 1, direct modulation of amplitude
via the profile registers is possible, depending upon other
chip configurations.
When CFR2<13> = 1, the rate out of the PDCLK pin is
equal to one half the input data rate. This provides in-
sight into the phase of the signal processing clock, rela-
tive to the input data rate. See the Data Assembler sec-
tion of the functional description for details.
CFR2<23>: Internal IO Update Active bit.
When CFR2<23>= 0 (default), the IO Update feature is
controlled externally through the I/O_UPDATE pin, which
is configured as an input..
CFR2<12>: Data Format bit.
When CFR2<12>= 0 (default), data received is treated as
‘twos complement’.
When CFR2<23> = 1, the IO Update feature is controlled
internally via a down counter. The I/O_UPDATE pin, is
configured as an output to signal the user to when IO up-
dates have occurred.
When CFR2<12> = 1, data received is treated as ‘offset
binary’. The MSB of the data word is inverted before be-
ing sent to the signal processing logic.
CFR2<22>: Enable IO SYNC CLK bit.
CFR2<11>: Enable PDCLK bit
CFR2<22>= 1 (default), activates the IOSYNCCLK pin.
When CFR2<22> = 0, the IOSYNCCLK pin is pulled low.
CFR2<21:17>: OPEN. Always leave these bits clear.
CFR2<16>: Read Effective FTW bit
CFR2<11> = 0 pulls the PDCLK pin low.
CFR2<11>= 1 (default) activates PDCLK pin.
CFR2<10>: PDCLK Invert bit
When CFR2<10>= 0 (default), the PDCLK pin is in phase
with the clock that samples the data into the part.
When CFR2<16>= 0 (default, a serial IO read instruc-
tion reads hex address 07h (FTW register), the serial
port reads back the register at hex address 07h.
When CFR2<10> = 1, the PDCLK pin is in inverted from
the clock that samples the data into the part.
When CFR2<16> = 1, a serial IO read instruction reads
hex address 07h (FTW register), the serial port reads
back the active FTW.
CFR2<9>: TxEnable Invert bit
When CFR2<9>= 0 (default), a logic 1 on the TxEnable pin
indicates I data and a logic 0 on the TxEnable pin indicates
Q data, if the user is employing a continuous timing style on
the TxEnable pin. For burst timing style, if the TxEnable In-
vert bit is cleared, a logic 1 on the TxEnable pin enables the
AD9957 to transmit data and a logic zero indicates no fur-
ther data is to be transmitted.
CFR2<1ꢀ:14>: IO Update Rate Control bits.
These bits are ignored if Internal IO Update is not
activated using bit CFR2<23>
The CFR2<15:14> bits set the clock rate for the IO Up-
date down counter. The table below indicates the clock
rate divisor
When CFR2<9> = 1, a logic 1 on the TxEnable pin indi-
cates Q data and a logic 0 on the TxEnable pin indicates I
data, if the user is employing a continuous timing style on
the TxEnable pin. For burst timing style, if the TxEnable In-
vert bit is set, a logic 0 on the TxEnable pin enables the
AD9957 to transmit data and a logic one indicates no fur-
ther data is to be transmitted.
CFR2<1ꢀ:14>
IO SYNC
CLK
Divisor
00
01
10
11
1
2
4
8
CFR2<8>: Q First Data Pairing bit
When CFR2<8>= 0 (default), I data precedes Q data in the
assembly of the I/Q data pair that is processing in the
QDUC signal chain.
When CFR2<8> = 1, Q data precedes I data in the assembly
of the I/Q data pair that is processing in the QDUC signal
chain.
CFR2<13>: PDCLK Rate Control bit.
CFR2<7>: Matched Latency bit.
When CFR2<13>= 0 (default), the rate out of the
Rev. PrF | Page 34 of 38
PRELIMINARY TECHNICAL DATA
AD9957
When CFR2<7>= 0 (default), the Frequency Tuning Word,
Phase Offset and Amplitude Scalar pipe delays are mini-
mized. The output will reflect amplitude changes before it
reflects phase changes, and phase changes before it reflects
frequency changes.
CFR3<21:19>: Charge Pump Current Bits
As per the table below, these bits set the charge pump
output current.
CFR3<21:19>
Charge Pump Current (μA)
When CFR2<7> = 1, the Frequency Tuning Word, Phase
Offset and Amplitude Scalar pipe delays are implemented
such that the simultaneous application of changes in fre-
quency, phase and amplitude are reflected on the output si-
multaneously too.
000
001
010
011
100
101
110
111
200
225
250
CFR2<6>: Data Assembler Holds Last Value bit
275
When CFR2<6>= 0 (default), the data port drives logic ze-
ros onto the signal processing data path when transmission
is disabled.
300
325
350
When CFR2<6> = 1, the data port holds the last data word
registered when transmission is disabled.
375
CFR2<ꢀ>: Sync Sample Error Mask bit
CFR2<ꢀ>= 0 disables the SYNC_SMP_ERR pin.
CFR2<ꢀ> = 1 (default) enables the SYNC_SMP_ERR pin.
CFR2<3:0>: FM Gain bits.
Table 6 Charge Pump Output Current Settings
CFR3<18:16>: OPEN. Leave these bits clear
CFR3<1ꢀ>: REFCLK Input Divider Disable bit.
When operating the device in single tone mode and FM
modulation is selected via the Data Port Destination bits, if
the Single Tone Data Port Enable bit is set, these bits are
used to select one of 16 possible 16-bit ranges relative to the
32-bit DDS tuning word.
When CFR3<1ꢀ> = 0 The AD9957 REFCLK input divider
is bypassed. The internal sysclk fed to the device (or the
clock multiplier) equals the REFCLK rate
When CFR3<1ꢀ> = 1 (default) The AD9957 REFCLK input
divider is enabled (to ÷2). The internal sysclk fed to the de-
vice (or the clock multiplier) is equal to ½ the REFCLK rate.
Control Function Register #3 (CFR3)
CFR3<31:30>: DRV0 (XTAL_OUT) control bits.
CFR3<14>: OPEN
These bits set the drive strength of the buffered reference
clock output on pin 93.
This bit is used strictly for testing, leave SET.
CFR3<13:9>: OPEN
00 = OFF (default)
01 = Low drive strength
10 = Mid drive strength
11 = High drive strength
These bits are used for testing; leave CLEAR.
CFR3<8>: PLL Enable bit.
CFR3<29:27>: Open. Leave these bits clear.
When CFR3<8>= 0 (default). The AD9957 reference clock
rate equals the DAC clock sampling rate. The PLL is by-
passed and the clock multiplier is powered down.
CFR3<26:24>: VCO Selection Bits.
As per the table below, these bits set the VCO for the appro-
priate range.
When CFR3<8> = 1, The AD9957 reference clock rate
times the PLL Multiplier bit (integer equivalent) equals the
DAC clock sampling rate.
Bits
000
001
010
011
100
101
11x
Min
Max
420MHz
485MHz
560MHz
655MHz
830MHz
920MHz
485MHz
560MHz
655MHz
830MHz
920MHz
1000MHz
CFR3<7:1>: REFCLK Multiplier bits.
These bits make up the 8-bit word that is the multiplication
factor used by the PLL Clock Multiplier circuitry. The
decimal equivalent of the binary value of these bits is the
multiplication factor. Only certain values are valid (See Ta-
PLL WILL NOT FUNCTION
Rev. PrF | Page 35 of 38
AD9957
PRELIMINARY TECHNICAL DATA
ble 4). If the PLL is enabled (CFR3<8>), a valid value must
be programmed here for proper PLL operation. If the PLL
is disabled, these bits are ignored.
This 3 bit word specifies the behavior the RAM con-
troller follows when stepping through the Segment ac-
cording to the following table. Note, the behavior in-
dicated refers to the RAM address itself, not necessar-
ily the data stored and sent to the QDUC.
CFR3<0>: REFCLK input doubler active bit
When CFR3<0>= 0 (default) the reference clock is fed di-
rectly to the PFD.
QSRX<2:0>
RAM Mode
When CFR3<0> = 1, the reference clock is doubled in fre-
quency prior to being fed to the PFD.
000
001
010
011
Direct Switch (Beginning Address only)
Ramp Up
Auxilliary DAC Control Register
These 8 bits control the auxiliary DAC that modulates the full
scale current of the Tx DAC. For a default DAC_Rset value of
10K, these bits modulate the DAC output full scale current be-
tween 8.66mA and 31.66mA, with each LSB representing ap-
proximately 90ꢀA of resolution.
Bidirectional Ramp (ramp up, ramp down)
Continuous Bidirectional (ramp up, ramp
down, ramp up, etc)
100
Continous recirculate (Ramp up from
beginning to final address, then immediately
return to beginning address and repeat).
IO Update Rate Register
This register sets the interval for the down counter which di-
vides the system clock down to an internal I/O update interval
period. When the internal I/O Update mode is disabled, this
register is ignored. Each LSB represents one SYNC_CLK cycle,
so the interval for an internal I/O update rate varies between 1
and 2^32( 4,294,967,296) sync_clock cycles, where a sync_clock
cycle is ¼ of a system clock cycle.
101, 110,
111
Not Used
Frequency Tuning Word Register (FTW)
This register sets the frequency tuning word of the DDS core,
which is either the output frequency (single tone mode) or the
carrier frequency (modulator mode). When the
Phase/Frequency/Amplitude Profiles are enabled, this register
serves no function.
QDUC RAM Segment Registers (QRSR0, QRSR1)
These registers program the behavior of the internal RAM con-
troller for when the RAM is configured to drive QDUC data or
drive the input scalars. QRSR0 feeds data to the I-channel and
QRSR1 feeds data to the Q-channel. These registers serve no
function when the AD9957 is programmed to be in single-tone
mode.
Phase Offset Word Register (POW)
This register controls the phase offset of the DDS core in either
the output frequency (single tone mode) or the carrier fre-
quency (modulator mode). When the
QRSRX<47:32> RAM Segment Address Ramp Rate
Phase/Frequency/Amplitude Profiles are enabled, this register
serves no function.
This 16 bit word controls the period between QDUC
RAM segment steps. Each LSB in this word weights
the delay by 1 SYNC_CLK cycle (which is ¼ the sys-
tem clock rate).
Amplitude Scale Factor (ASF)
This register controls the digital multiplier (amplitude scale
factor) inside the DDS core itself. It does not affect the digital
multiplier immediately prior to the DAC . In automatic OSK
mode, this controls the ramp rate and final value of the ampli-
tude ramping function. In manual OSK mode, only the Ampli-
tude Scale Factor is used, the Amplitude Ramp Rate is ‘don’t
care’. When the Phase /Frequency /Amplitude Profiles are en-
abled, this register serves no function.
QRSRX<31:22> RAM Segment Final Address
This 10 bit word specifies the final address location in
the RAM where the data profile is stored.
QRSRX<21:16> OPEN
QRSRX<1ꢀ:6> RAM Segment Beginning Address
QDUC Profile X Register (QDUC-PXR)/
Single Tone Profile X Register (ST-PXR)
This 10 bit word specifies the beginning address loca-
tion in the RAM where the data profile is stored.
There are 8 special purpose registers which reside at addresses
h’0E to h’15. These registers can take on one of three roles: they
can either be QDUC Profile Registers, RAM Profile Registers or
Single Tone Profile Registers.
QRSRX<ꢀ:3> OPEN
QSRX<2:0> RAM Segment Mode Control
Rev. PrF | Page 36 of 38
PRELIMINARY TECHNICAL DATA
AD9957
First and foremost, the part will use these registers as QDUC
Profile registers if the part is in quadrature modulator mode
CFR1<25:24> = 00.
Rev. PrF | Page 37 of 38
AD9957
PRELIMINARY TECHNICAL DATA
OUTLINE DIMENSIONS
16.00 BSC SQ
1.20
MAX
0.75
0.60
0.45
14.00 BSC SQ
100
1
76
75
76
75
100
1
PIN 1
EXPOSED
PAD
5.00 SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
BOTTOM VIEW
(PINS UP)
51
51
25
25
26
50
50
26
3.5°
0°
0.08 MAX
COPLANARITY
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
0.15
0.05
SEATING
PLANE
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE AD9957 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO V . IT IS RECOMMENDED THAT NO PCB SIGNAL
EE
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A V PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
EE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
ORDERING GUIDE
Model
Temperature
Range
Package Description
Package
Outline
AD9957BSVZ
AD9957BSVZ-
REEL13
–40°C to +105°C
–40°C to +105°C
48-Lead Thin Plastic Quad Flat Package, Exposed Pad (TQFP_EP)
48-Lead Thin Plastic Quad Flat Package, Exposed Pad (TQFP_EP), 1000
Device, 13-Inch Reel
AD9957/PCBZ
Evaluation Board
Rev. PrF | Page 38 of 38
相关型号:
AD9957BSVZ-REEL13
IC SPECIALTY TELECOM CIRCUIT, QFP48, PLASTIC, MS-026-AED-HD, TQFP-48, Telecom IC:Other
ADI
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