AD9975ABST [ADI]
Broadband Modem Mixed-Signal Front End; 宽带调制解调器混合信号前端
| 型号： | AD9975ABST |
| 厂家： | 
ADI |
| 描述： | Broadband Modem Mixed-Signal Front End |
| 文件： | 总20页 (文件大小：1142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Broadband Modem
a
Mixed-Signal Front End
AD9975
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Low Cost, 3.3 V-CMOS, Mixed Signal, Front End
Converter for Broadband Modems
10-Bit D/A Converter (TxDAC+®)
50 MSPS Input Word Rate
2
؋
Interpolating Low-Pass Transmit Filter 100 MSPS DAC Output Update Rate
Wide (21 MHz) Transmit Bandwidth
Power-Down Modes
10-Bit, 50 MSPS A/D Converter
Fourth Order LPF with Selectable Cutoff Frequency
Dual Mode Programmable Gain Amplifier
Internal Clock Multiplier (PLL)
Two Auxiliary Clock Outputs
AD9975
TXEN
RXEN
TX+
10
10
K
TxDAC+
TX–
TXCLK
RXCLK
CLK1
CLK2
ADIO[9:0]
CLK-GEN
OSCIN
XTAL
48-Lead LQFP Package
RX+
RX–
10
ADC
LPF
PGA
PGA
APPLICATIONS
Powerline Networking
Home Phone Networking
3
3
AGC[2:0]
SPORT
REGISTER
CONTROL
GENERAL DESCRIPTION
The filter cutoff frequency can also be tuned or bypassed where
filter requirements differ. The 10-bit ADC uses a multistage
differential pipeline architecture to achieve excellent dynamic
performance with low power consumption.
The AD9975 is a single-supply, broadband modem, mixed
signal, front end (MxFE™) IC. The device contains a transmit
path interpolation filter and DAC and a receive path PGA,
LPF, and ADC required for a variety of broadband modem
applications. Also on-chip is a PLL clock multiplier that pro-
vides all required clocks from a single crystal or clock input.
The digital transmit and receive ports are multiplexed onto a
10-bit databus and have individual TX/RX clocks and TX/RX
enable lines. This interface connects directly to Homelug 1.0
PHY/MAC chips from Intellon and Conexant.
The TxDAC+ uses a digital 2× interpolation low-pass filter to
oversample the transmit data and ease the complexity of analog
reconstruction filtering. The transmit path bandwidth is 21 MHz
when sampled at 100 MSPS. The 10-bit DAC provides differen-
tial current outputs. The DAC full-scale current can be adjusted
from 2 to 20 mA by a single resistor, providing 20 dB of additional
gain range.
The AD9975 is available in a space-saving 48-lead LQFP pack-
age. The device is specified over the commercial (–40°C to
+85°C) temperature range.
The receive path consists of a PGA, LPF, and ADC. The program-
mable gain amplifier (PGA) has two modes of operation. One
mode allows programming through the serial port and provides a
gain range from –6 dB to +36 dB in 2 dB steps. The other mode
allows the gain to be controlled through an asynchronous 3-pin
port and offers a gain range from 0 dB to 48 dB in 8 dB steps
with the use of an external gain stage. The receive path LPF
cutoff frequency can be selected to either 12 MHz or 26 MHz.
TxDAC+ is a registered trademark and MxFE is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(VS = 3.3 V ؎10%, FOSCIN = 50 MHz, FDAC = 100 MHz, Gain = –6 dB,
AD9975–SPECIFICATIONS RSET = 4.02 k⍀, 100 ⍀ DAC Load.)
Test
Temp Level
Parameter
Min
Typ
Max
Unit
OSC IN CHARACTERISTICS
Frequency Range
Duty Cycle
Input Capacitance
Input Impedance
Full
I
II
III
III
10
40
50
60
MHz
%
pF
25°C
25°C
25°C
50
3
100
MΩ
CLOCK OUTPUT CHARACTERISTICS
CLKA Jitter (FCLKA Derived from PLL)
CLKA Duty Cycle
25°C
25°C
II
III
14
50
ps rms
%
5
TX CHARACTERISTICS
2× Interpolation Filter Characteristics
TX Path Latency, 2× Interpolation
Pass-Band Flatness 0 MHz to 20.7 MHz
Stop-Band Rejection @ 29.3 MHz
TxDAC
Full
Full
Full
II
II
II
30
0.8
35
FDAC Cycles
dB
dB
Resolution
Conversion Rate
Full-Scale Output Current
Full
Full
Full
II
II
II
10
10
Bits
MHz
mA
10
2
100
20
Voltage Compliance Range (TX+ or TX– AVSS) Full
II
II
II
III
II
III
III
–0.5
–5.5
0
+1.5
+5.0
TBD
V
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
25°C
25°C
25°C
25°C
25°C
25°C
2
2
0.5
%FS
µA
LSB
LSB
pF
1
Output Capacitance
5
Phase Noise @ 1 kHz Offset, 10 MHz Signal
Signal-to-Noise and Distortion (SINAD)
5 MHz Analog Out (20 MHz BW)
Wideband SFDR (to Nyquist, 50 MHz max)
5 MHz Analog Out
Narrowband SFDR (3 MHz Window)
5 MHz Analog Out
–100
–60.6
–76.2
dBc/Hz
25°C
25°C
25°C
II
III
III
dB
dBc
25°C
25°C
III
III
–77.9
–77
dBc
dBFS
IMD (f1 = 6.25 MHz, f2 = 7.8125 MHz)
RX PATH CHARACTERISTICS (LFP Bypassed)
Resolution
Conversion Rate
Pipeline Delay, ADC Clock Cycles
Dynamic Performance (AIN = –0.5 dBFS, f = 5 MHz)
@ FOSCIN = 50 MHz, RX LPF Bypassed
Signal-to-Noise and Distortion Ratio (SINAD)
Effective Number of Bits (ENOB)
Signal-to-Noise Ratio (SNR)
N/A
Full
N/A
N/A
II
N/A
10
Bits
MHz
Cycles
10
50
5.5
Full
Full
Full
Full
Full
III
III
III
III
III
–56.6
9.1
–59.2
–60.1
–66
dB
Bits
dB
dB
dB
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
RX PATH GAIN/OFFSET
Minimum Programmable Gain
Maximum Programmable Gain
Narrow Band Rx LPF or Rx LPF Bypassed
Wideband Rx LPF
Gain Step Size
Gain Step Accuracy
25°C
I
–6
dB
25°C
25°C
25°C
25°C
Full
I
I
I
II
II
II
+36
+30
2
0.4
1.0
0.8
dB
dB
dB
dB
dB
dB
Gain Range Error
Absolute Gain Error, PGA Gain = 0 dB
Full
RX PATH INPUT CHARACTERISTICS
Input Voltage Range (Gain = –6 dB)
Input Capacitance
Differential Input Resistance
Input Bandwidth (–3 dB) (Rx LPF Bypassed)
Input Referred Noise (at +36 dB Gain with Filter) 25ºC
Input Referred Noise (at –6 dB Gain with Filter)
Common-Mode Rejection
Full
III
III
III
III
III
III
III
4
4
270
50
16
684
40
Vppd
pF
Ω
MHz
µV rms
µV rms
dB
25°C
25°C
25°C
25ºC
25ºC
–2–
REV. 0
AD9975
Test
Temp Level
Parameter
Min
Typ
Max
Unit
RX PATH LPF (Low Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 22 MHz
Pass-Band Ripple
Full
Full
Full
Full
Full
III
III
III
II
12
7
20
1.0
30
MHz
%
dB
dB
ns
Group Delay Variation
II
Settling Time (to 1% FS, Min to Max Gain Change) 25°C
II
I
150
–61
ns
dBc
Total Harmonic Distortion at Max Gain (THD)
Full
RX PATH LPF (High Cutoff Frequency)
Cutoff Frequency
Cutoff Frequency Variation
Attenuation @ 35 MHz
Pass-Band Ripple
Group Delay Variation
Settling Time (to 1% FS, Min to Max Gain Change) 25°C
Total Harmonic Distortion at Max Gain (THD)
Full
Full
Full
Full
Full
III
III
III
II
II
II
26
7
20
1.2
15
80
–61
MHz
%
dB
dB
ns
ns
dBc
Full
I
RX PATH DIGITAL HPF
Latency (ADC Clock Source Cycles)
Roll-Off in Stop Band
1
6
Cycle
dB/Octave
Hz
–3 dB Frequency
fADC /400
POWER-DOWN/DISABLE TIMING
Power-Down Delay (Active-to-Power-Down)
DAC
Interpolator
Power-Up Delay (Power-Down-to-Active)
25°C
25°C
II
II
200
200
ns
ns
DAC
PLL
ADC
PGA
25°C
25°C
25°C
25°C
25°C
25°C
Full
II
II
II
II
II
II
III
10
10
1000
1
1
200
5
µs
µs
µs
µs
LPF
Interpolator
Minimum RESET Pulsewidth Low (tRL
µs
ns
)
fOSCIN Cycles
ADIO PORT INTERFACE
Maximum Input Word Rate
25°C
25°C
25°C
25°C
25°C
I
100
3.0
0
MHz
ns
ns
ns
ns
TX-Data Setup Time (tSU
TX-Hold Hold Time (tHD
)
)
II
II
II
II
RX-Data Valid Time(tVT
RX-Data Hold Time (tHT
)
)
3.0
1.5
REV. 0
–3–
AD9975
SPECIFICATIONS (continued)
Parameter
Test
Temp Level
Min
Typ
Max
Unit
SERIAL CONTROL BUS
Maximum SCLK Frequency (fSCLK
)
Full
Full
Full
Full
Full
Full
Full
II
II
II
II
II
II
II
25
18
18
MHz
ns
ns
µs
ns
ns
ns
Clock Pulsewidth High (tPWH
)
Clock Pulsewidth Low (tPWL
Clock Rise/Fall Time
Data/Chip-Select Setup Time (tDS
)
10
20
)
25
0
Data Hold Time (tDH
Data Valid Time (tDV
)
)
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
25°C
25°C
25°C
25°C
25°C
II
II
II
II
VDRVDD – 0.7
V
V
µA
µA
pF
0.4
12
12
III
3
CMOS LOGIC OUTPUTS (1 mA Load)
Logic “1” Voltage
Logic “0” Voltage
Full
25°C
Full
II
II
II
VDRVDD – 0.6
1.5
V
V
ns
0.4
2.5
Digital Output Rise/Fall Time
POWER SUPPLY
All Blocks Powered Up
I
S_TOTAL (Total Supply Current)
Digital Supply Current (IDRVDD + IDVDD
Clock Supply Current (ICLKVDD
Analog Supply Current (IAVDD
25°C
25°C
25°C
25°C
I
210
22.5
5.5
227
mA
mA
mA
mA
)
III
III
III
)
)
182
Power Consumption of Functional Blocks
Rx LPF
ADC and SPGA
Rx Reference
Interpolator
DAC
PLL-A
25°C
25°C
25°C
25°C
25°C
25°C
III
III
III
III
III
III
110
55
2
20
18
22
mA
mA
mA
mA
mA
All Blocks Powered Down
IS_TOTAL (Total Supply Current)
Digital Supply Current (IDRVDD + IDVDD
25°C
25°C
25°C
25°C
I
21
10
0
27
mA
mA
mA
mA
)
III
III
III
Clock Supply Current (ICLKVDD
Analog Supply Current (IAVDD
)
)
11
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Power Supply (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V
Analog Inputs . . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature . . . . . . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
*Absolute Maximum Ratings are limiting values to be applied individually and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect
device reliability.
I. Devices are 100% production tested at 25°C and guaranteed
by design and characterization testing for the commercial
operating temperature range (–40°C to +85°C).
II. Parameter is guaranteed by design and/or characterization
testing.
III. Parameter is a typical value only.
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP
θ
θ
JA = 57ºC/W
JC = 28ºC/W
–4–
REV. 0
AD9975
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ST-48
AD9975ABST
AD9975ABSTEB
AD9975ABSTRL
–40ºC to +85ºC
–40ºC to +85ºC
–40ºC to +85ºC
48-Lead LQFP
AD9975 EVAL Board
AD9975ABST Reel
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9975 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTION
PIN CONFIGURATION
Pin No.
Mnemonic
Function
1
2
3
4
OSC IN
SENABLE
SCLK
SDATA
AVDD
Crystal Oscillator Inverter Input
Serial Bus Enable Input
Serial Bus Clock Input
Serial Bus Data I/O
Analog 3.3 V Power Supply
Analog Ground
OSC IN
1
2
3
4
5
6
7
8
9
36 DRVSS
35 DRVDD
34 RXBOOST/SDO
33 CLKOUT2
32 RXCLK
31 TXCLK
30 TXEN
SENABLE
SCLK
SDATA
AVDD
AVSS
TX+
5, 38, 47
6, 9, 39, 42, AVSS
43, 46
AD9975
48-PIN LQFP
TOP VIEW
(Not to Scale)
7
8
10
Tx+
Tx–
FS ADJ
Transmit DAC + Output
Transmit DAC – Output
DAC Full-Scale Output Current
Adjust with External Resistor
DAC Band Gap Decoupling Node
Power Supply for CLKOUT1
Digital Ground
TX–
29 RXEN
AVSS
28 ADIO0
FS ADJ 10
REFIO 11
27 ADIO1
11
12
13
REFIO
CLKVDD
DVSS
26 ADIO2
CLKVDD 12
25 ADIO3
14
15–17
18
19–28
29
30
DVDD
Digital 3.3 V Power Supply
AGC Control Inputs
Auxiliary Clock Output
Digital Data I/O Port
ADIO Direction Control Input
TX Path Enable
AGC[2:0]
CLKOUT1
ADIO[9:0]
RXEN
TXEN
31
32
33
TXCLK
RXCLK
CLKOUT2
ADIO Sample Clock Input
ADIO Request Clock Input
Auxiliary Clock Output
34
RXBOOST/
SDO
External Gain Control Output/
Serial Data Output
35
36
37
DRVDD
DRVSS
RESET
Digital I/O 3.3 V Power Supply
Digital I/O Ground
Reset Input
40, 41
44
REFB, REFT ADC Reference Decoupling Node
Rx+
Receive Path + Input
45
Rx–
Receive Path – Input
48
XTAL
Crystal Oscillator Inverter Output
REV. 0
–5–
AD9975
DEFINITIONS OF SPECIFICATIONS
Clock Jitter
The clock jitter is a measure of the intrinsic jitter of the PLL
generated clocks. It is a measure of the jitter from one rising
edge of the clock with respect to another edge of the clock nine
cycles later.
Offset Error
First transition should occur for an analog value 1/2 LSB above
negative full scale. Offset error is defined as the deviation of the
actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur for an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last
code transitions and the ideal difference between first and last
code transitions.
Differential Nonlinearity Error (DNL, No Missing Codes)
An ideal converter exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to 10-bit resolution indicate that all 1024 codes,
respectively, must be present over all operating ranges.
Integral Nonlinearity Error (INL)
Input Referred Noise
Linearity error refers to the deviation of each individual code from
a line drawn from “negative full scale” through “positive full
scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
The rms output noise is measured using histogram techniques.
The ADC output code’s standard deviation is calculated in LSB
and converted to an equivalent voltage. This results in a
noise figure that can directly be referred to the RX input of
the AD9975.
Signal-to-Noise and Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the measured input signal
to the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Phase Noise
Single-sideband phase noise power density is specified relative
to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from
the carrier. Phase noise can be measured directly on a generated
single tone with a spectrum analyzer that supports noise marker
measurements. It detects the relative power between the carrier
and the offset (1 kHz) sideband noise and takes the resolution
bandwidth (rbw) into account by subtracting 10 log(rbw). It also
adds a correction factor that compensates for the implementation
of the resolution bandwidth, log display, and detector characteristic.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number
of bits. Using the following formula,
N = (SINAD – 1.76) dB/6.02
it is possible to get a measure of performance expressed as N,
the effective number of bits.
Output Compliance Range
Signal-to-Noise Ratio (SNR)
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation, resulting in nonlinear per-
formance, or breakdown.
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
The difference, in dB, between the rms amplitude of the DAC’s
output signal (or ADC’s input signal) and the peak spurious
signal over the specified bandwidth (Nyquist bandwidth, unless
otherwise noted).
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Power Supply Rejection
Pipeline Delay (Latency)
The number of clock cycles between conversion initiation and
the associated output data being made available.
Power supply rejection specifies the converter’s maximum
full-scale change when the supplies are varied from nominal to
minimum and maximum specified voltages.
–6–
REV. 0
Typical Performance Characteristics–AD9975
10
0
0
INTERPOLATION FILTER
–10
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–30
–40
–50
–60
–70
–80
–90
–100
INCLUDING
SIN(X)/X
0
5
10
15
20
25
30
35
40
45
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
FREQUENCY – MHz
F
SAMPLE
TPC 1. 2 × Low-Pass Interpolation Filter
TPC 4. Single Tone Spectral Plot @ fDATA = 50 MSPS,
f
OUT = 11 MHz, 2 × LPF
10
0
10
0
INTERPOLATION FILTER
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
INCLUDING
SIN(X)/X
–100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
10.0 1.02 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0
F
– MHz
FREQUENCY – MHz
S
TPC 2. 2 × Band-Pass Interpolation Filter, FS/2
Modulation, Adjacent Image Preserved
TPC 5. Dual Tone Spectral Plot @ fDATA = 50 MSPS,
fOUT = 6.7 MHz and 7.3 MHz, 2 × LPF
0
–70
–72
–10
–20
–74
–76
–78
THIRD ORDER
HARMONIC
–30
–40
–50
–60
–70
–80
–90
–100
–80
–82
–84
SECOND ORDER
HARMONIC
–86
–88
–90
0
5
10
15
20
25
30
35
40
45
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
FREQUENCY – MHz
FREQUENCY – MHz
TPC 3. Single Tone Spectral Plot @ fDATA = 50 MSPS,
TPC 6. Harmonic Distortion vs. fOUT @fDATA = 50 MSPS
fOUT = 5 MHz, 2 × LPF
REV. 0
–7–
AD9975
10
35
30
25
20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10.003 10.004 10.005 10.006 10.007 10.008 10.009 10.010 10.011 10.012 10.013
192
208
224
240
255
FREQUENCY – MHz
TUNINGTARGET – Decimal
TPC 7. Phase Noise Plot @fDATA 50 MSPS,
TPC 10. FC vs. Tuning Target, FADC = 50 MHz,
LPF = Wideband Rx Filter
f
OUT = 10 MHz, 2 × LPF
10
0
20
18
16
14
12
10
–10
–20
–30
–40
–50
–60
–70
192
208
224
240
255
3
5
7
9
11
13
15
17
19
21
23
TUNINGTARGET – Decimal
FREQUENCY – MHz
TPC 11. FC vs. Tuning Target, FADC = 50 MHz,
LPF = Narrowband Rx Filter
TPC 8. “In-Band” Multitone Spectral Plot
@fDATA = 50 MSPS, fOUT = k × 195 kHz, 2 × LPF
10
0.60
0
–10
–20
–30
–40
–50
–60
–70
0.40
0.20
0
–0.20
–0.40
–0.60
–0.80
1
11
21
31
41
51
61
71
81
91
101
FREQUENCY – MHz
–6 –4 –2
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
VGA GAIN – dB
TPC 9. “Wide-Band” Multitone Spectral Plot
@fDATA = 50 MSPS, fOUT = k × 195 kHz, 2 × LPF
TPC 12. PGA Gain Error vs. Gain
–8–
REV. 0
AD9975
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
5dB/Div
REF 0dB
LOG MAG
–3.0dB
24.1MHz
0
–6 –4 –2
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36
VGA GAIN – dB
1MHz
10MHz
100MHz
TPC 13. PGA Gain Step vs. Gain
TPC 16. Rx LPF Group Delay, LPF = Narrowband
Rx Filter, FADC = 50 MHz, Tuning Target = 255
5dB/Div REF 0dB
5 ns/Div
DELAY
REF 0s
33.9ns
LOG MAG
–3.0dB
12.1MHz
22.1MHz
0
0
1MHz
10MHz
100MHz
1MHz
10MHz
100MHz
TPC 17. Rx LPF Group Delay, LPF = Wideband Rx
Filter, FADC = 50 MHz, Tuning Target = 255
TPC 14. Rx LPF Frequency Response, LPF =
Narrowband Rx Filter, FADC = 50 MHz,
Tuning Target = 255
10ns/Div REF 0s
DELAY
70.1ns
9.9MHz
5dB/Div
LOG MAG
123.5 kHz
REF 0dB
0
–3.00dB
0
1MHz
10MHz
100MHz
10kHz
100kHz
1MHz
TPC 15. Rx LPF Frequency Response, LPF =
Wideband Rx Filter, FADC = 50 MHz,
Tuning Target = 255
TPC 18. Rx HPF Frequency Response, FADC = 50 MHz
REV. 0
–9–
AD9975
4000
3800
3600
3400
3200
3000
2800
2600
60
59
58
57
56
55
2400
1
45
50
20
25
30
35
40
5
9
13
17
21
25
29
33
37
F
– MHz
ADC CLOCK CYCLES
S
TPC 19. Rx Path Settling, 1/2 Scale Rising Step with
Gain Change, LPF FC = 26 MHz, FADC = 50 MHz
TPC 22. Rx Path SNR vs. FADC, FIN = 5 MHz,
Gain = –6 dB, Rx LPF Bypassed
4000
3800
3600
3400
3200
3000
2800
2600
2400
–55
–60
–65
45
50
20
25
30
35
40
1
5
9
13
17
21
25
29
33
37
F
– MHz
ADC CLOCK CYCLES
S
TPC 20. Rx Path Settling, 1/2 Scale Falling Step with
Gain Change, LPF FC = 26 MHz, FADC = 50 MHz
TPC 23. Rx Path THD vs. FADC, FIN = 5 MHz,
Gain = –6 dB, Rx LPF Bypassed
9.5
9.3
9.1
8.9
9.50
9.25
9.00
8.75
8.50
8.7
8.5
0
2
4
6
8
10
12
14
16
18
20
45
50
20
25
30
35
40
F
– MHz
F
– MHz
IN
S
TPC 24. Rx Path ENOB vs. FIN, FADC = 50 MHz,
Gain = –6 dB, Rx LPF Bypassed
TPC 21. Rx Path ENOB vs. FADC, FIN = 5 MHz,
Gain = –6 dB, Rx LPF Bypassed
–10–
REV. 0
AD9975
58
57
–50
–55
56
55
54
–60
–65
53
52
–70
–75
51
50
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
F
– MHz
F
– MHz
IN
IN
TPC 25. Rx Path SNR vs. FIN, FADC = 50 MHz,
Gain = –6 dB, Rx LPF Bypassed
TPC 26. Rx Path THD vs. FIN, FADC = 50 MHz,
Gain = –6 dB, Rx LPF Bypassed
REV. 0
–11–
AD9975
TRANSMIT PATH
of L is programmed through the serial interface port and can be
set to 1, 2, 4, or 8. The transmit path expects a new input sample
at the ADIO interface at a rate of fDAC/2 if the interpolation
filter is being used. If the interpolation filter is bypassed, the
transmit path expects a new input sample at the ADIO interface
at a rate of fDAC.
The AD9975 transmit path consists of a digital interface port,
a bypassable 2× interpolation filter, and a transmit DAC. The
clock signals required by these blocks are generated by the inter-
nal PLL. The block diagram below shows the interconnection
between the major functional components of the transmit path.
INTERPOLATION FILTER
D/A CONVERTER
The interpolation filter can be programmed to run at a 2×
upsampling ratio in either a low-pass filter or band-pass filter
mode. The transfer functions of these two modes are shown in
TPC 1 and TPC 2, respectively. The y-axes of the figures show
the magnitude response of the filters in dB, and the x-axes show
the frequency normalized to FDAC. The top trace of the plot shows
the discrete time transfer function of the interpolation filter. The
bottom trace shows the TX path transfer function including the
sin(x)/x transfer function of the DAC. In addition to the two
upsampling modes, the interpolation filter can be programmed
into a pass-through mode if no interpolation filtering is desired.
The AD9975 DAC provides differential output current on the
TX+ and TX– pins. The values of the output currents are comple-
mentary, meaning they will always sum to IFS, the full-scale
current of the DAC. For example, when the current from TX+
is at full scale, the current from TX– is zero. The two currents
will typically drive a resistive load that will convert the output
currents to a voltage. The TX+ and TX– output currents are
inherently ground seeking and should each be connected to
matching resistors, RL, that are tied directly to AGND.
The full-scale output current of the DAC is set by the value of
the resistor placed from the FS ADJ pin to AGND. The rela-
tionship between the resistor, RSET, and the full-scale output
current is governed by the following equation:
The table below shows the following parameters as a function of
the mode in which it is programmed.
Latency – The number of clock cycles from the time a digital
impulse is written to the DAC until the peak value is output at
the TX+ and TX– Pins.
IFS = 39.4 / RSET
The full-scale current can be set from 2 to 20 mA. Generally, there
is a trade-off between DAC performance and power consumption.
The best DAC performance will be realized at an IFS of 20 mA.
However, the value of IFS adds directly to the overall current
consumption of the device.
Flush – The number of clock cycles from the time a digital
impulse is written to the DAC until the output at the TX+ and
TX– Pins settles to zero.
F
PASS – The frequency band over which the pass-band ripple is
The single-ended voltage outputs appearing at the TX+ and
TX– nodes are:
less than the stated magnitude (i.e., 0.1 dB or 1.0 dB).
F
STOP – The frequency band over which the stop-band attenuation
VTX+ = ITX+ × RL
VTX– = ITX– × RL
is greater than the stated magnitude (i.e., 40 dB or 50 dB).
Note that the full-scale voltage of VTX+ and VTX– should not
exceed the maximum output compliance range of 1.5 V to pre-
vent signal compression. To maintain optimum distortion and
linearity performance, the maximum voltages at VTX+ and VTX–
should not exceed 0.5 V.
Table I. Interpolation Filters vs. Mode
Register 7[7:4]
0x1
0x5
Mode
2× LPF
2× BPF, Adj. Image
30
Latency, FDAC Clock Cycles 30
The single-ended full-scale voltage at either output node will be:
Flush, FDAC Clock Cycles
FPASS, 0.1 dB
FPASS, 1.0 dB
FSTOP, 40 dB
FSTOP, 50 dB
48
48
<0.204
<0.207
<0.296
<0.302
>0.296, <0.704
>0.293, <0.707
>0.204, <0.796
<0.198, >0.802
VFS = IFS × RL
The differential voltage, VDIFF, appearing across VTX+ and VTX– is:
VDIFF = (ITX+ – ITX– )× RL
and
DPLL-A CLOCK DISTRIBUTION
VDIFF _FS = IFS × RL
Figure 1 shows the clock signals used in the transmit path. The
DAC sampling clock, fDAC, is generated by DPLL-A. fDAC has a
frequency equal to L × fOSCIN, where L is the PLL clock multiplier
value and fOSCIN is the frequency of the input to PLL-A. The value
It should be noted that the differential output impedance of the
DAC is 2 × RL and any load connected across the two output
resistors will load down the output voltage accordingly.
–12–
REV. 0
AD9975
RECEIVE PATH DESCRIPTION
There are two pass band settings for the LPF. Within each pass
band, the filters are tunable over about a 15% frequency range.
The formula for the cutoff frequency is:
The receive path consists of a two stage PGA, a continuous
time, 4-pole LPF, an ADC, and a digital HPF. Also working
in conjunction with the receive path is an offset correction
circuit and a digital phase-locked loop. Each of these blocks
will be discussed in detail in the following sections.
FC = FADC × 64 / (64 + Target)
Where Target is the decimal value programmed as the tuning
target in Register 5.
PROGRAMMABLE GAIN AMPLIFIER
This filter may also be bypassed. In this case, the bandwidth of
the RX path will be gain dependent and will be around 50 MHz
at the highest gain settings.
The PGA has a programmable gain range from –6 dB to +36 dB
if the narrower (approximately 12 MHz) LPF bandwidth is selected,
or if the LPF is bypassed. If the wider (approximately 29 MHz)
LPF bandwidth is selected, the gain range is –6 dB to +30 dB.
The PGA is comprised of two sections, a continuous time PGA
(CPGA), and a switched capacitor PGA (SPGA). The CPGA
has possible gain settings of 0, 6, 12, 18, 24 and 30. The SPGA
has possible gain settings of –6 dB, –4 dB, –2 dB, 0 dB, +2 dB,
+4 dB, and +6 dB. Table II shows how the gain is distributed
for each programmed gain setting.
ADC
The AD9975’s analog-to-digital converter implements pipelined
multistage architecture to achieve high sample rates while consum-
ing low power. The ADC distributes the conversion over several
smaller A/D subblocks, refining the conversion with progressively
higher accuracy as it passes the results from stage to stage. As a
consequence of the distributed conversion, ADCs require a small
fraction of the 2n comparators used in a traditional n-bit flash-
type A/D. A sample-and-hold function within each of the stages
permits the first stage to operate on a new input sample while the
remaining stages operate on preceding samples. Each stage of
the pipeline, excluding the last, consists of a low resolution
Flash A/D connected to a switched capacitor DAC and interstage
residue amplifier (MDAC). The residue amplifier amplifies the
difference between the reconstructed DAC output and the flash
input for the next stage in the pipeline. One bit of redundancy is
used in each one of the stages to facilitate digital correction of
flash errors. The last stage simply consists of a Flash A/D.
The CPGA input appears at the device RX+ and RX– input pins.
The input impedance of this stage is nominally 270 Ω differential
and is not gain dependent. It is best to ac-couple the input signal
to this stage and let the inputs self-bias. This will lower the
offset voltage of the input signal, which is important at higher
gains, since any offset will lower the output compliance range of
the CPGA output. When the inputs are driven by direct coupling,
the dc level should be AVDD/2. However, this could lead to
larger dc offsets and reduce the dynamic range of the RX path.
There are two modes for selecting the RX path gain. The first
mode is to program the PGA through the serial port. A 5-bit
word determines the gain with a resolution of 2 dB per step.
More detailed information about this mode is included in the
Register Programming Definitions section of this data sheet.
SHA
GAIN
SHA
GAIN
AINP
AINN
A/D
The second mode sets the gain through the asynchronous
AGC[2:0] pins. These three pins set the PGA gain and state of
the RXBOOST pin according to Table II.
A/D
D/A
A/D
D/A
Table II. AGC[2:0] Gain Mapping
Rx
CORRECTION LOGIC
AGC
[2:0]
Path
Gain
CPGA
Gain
SPGA
Gain
Figure 1. ADC Theory of Operation
RXBOOST
The digital data outputs of the ADC are represented in straight
binary format. They saturate to full scale or zero when the input
signal exceeds the input voltage range.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
–6
–6
2
10
2
10
18
26
–6
–6
–6
0
–6
0
0
0
8
10
8
10
6
8
0
0
0
0
1
1
1
1
The maximum value will be output from the ADC when the
RX+ input is 1 V or more greater than the RX– input. The mini-
mum value will be output from the ADC when the RX– input is
1 V or more greater than the RX+ input. This results in a full-scale
ADC voltage of 2 Vppd.
12
18
The data can be translated to straight binary data format by
simply inverting the most significant bit.
LOW-PASS FILTER
The timing of the interface is fully described in the Digital Inter-
face Port Timing section.
The low-pass filter (LPF) is a programmable, three-stage, fourth
order low-pass filter. The first real pole is implemented within
the CPGA. The second filter stage implements a complex pair
of poles. The last real pole is implemented in a buffer stage that
drives the SPGA.
REV. 0
–13–
AD9975
DIGITAL HPF
AGC PROGRAMMING
Following the ADC, there is a bypassable digital HPF. The
response is a single pole IIR HPF. The transfer function is
approximately:
The gain in the receive path can be programmed in two ways.
The default method is through the AGC[2:0] pins. In this mode,
the gain is achieved using a combination of internal and external
gain. The external gain is controlled by the RXBOOST output
pin, which is determined by the decode of the 3-bit AGC gain value.
H(z) = (Z – 0.99994)/(Z – 0.98466)
where the sampling period is equal to the ADC clock period.
This results in a 3 dB frequency approximately 1/400th of the
ADC sampling rate. The transfer function of the digital HPF with
an ADC sample rate of 50 MSPS is plotted in TPC 23.
DIGITAL INTERFACE PORT OPERATION
The digital interface port is a 10-bit bidirectional bus shared in
burst fashion between the transmit path and receive path. The
MxFE acts as a slave to the digital ASIC, accepting two input
enable signals, TXEN and RXEN, as well as two input clock
signals, TXCLK and RXCLK. Because the sampling clocks for
the DAC and ADC are derived internally from the OSC IN
signal, it is required that the TXCLK and RXCLK signals are
exactly the same frequency as the OSC IN signal. The phase
relationships between the TXCLK, RXCLK, and OSC IN signal
are arbitrary.
The digital HPF introduces a 1 ADC clock cycle latency. If the
HPF function is not desired, the HPF can be bypassed and the
latency will not be incurred.
CLOCK AND OSCILLATOR CIRCUITRY
The AD9975 generates all internally required clocks from a single
clock source. This source can be supplied in one of two ways.
The first method uses the on-chip oscillator by connecting a
fundamental frequency quartz crystal between the OSC IN (Pin 1)
and XTAL (Pin 48) with parallel resonant load capacitors as
specified by the crystal manufacturer. Alternatively, a TTL-level
clock applied to OCS IN with the XTAL pin left unconnected
can overdrive the internal oscillator circuit.
In order to add flexibility to the digital interface port, there are
several programming options available. The data input format is
straight binary by default. It is possible to independently change
the data format of the transmit path and receive path to twos
complement. Also, the clock timing can be independently changed
on the transmit and receive paths by selecting either the rising
or falling clock edge as the validating/sampling edge of the clock.
The digital interface port can also be programmed into a three-
state output mode allowing it to be connected onto a shared bus.
The PLL has a frequency capture range between 10 MHz and
50 MHz.
AGC TIMING CONSIDERATIONS
When implementing the AGC timing loop, it is important to
consider the delay and settling time of the RX path in response
to a change in gain. Figure 2 shows the delay the receive signal
experiences through the blocks of the RX path. Whether the gain
is programmed through the serial port or via the AGC[2:0] pins,
the gain takes effect immediately with the delays shown in Figure 2.
When gain changes do not involve the CPGA, the new gain will
be evident in samples after about 7 ADC clock cycles. When the
gain change does involve the CPGA, it takes an additional 45 ns
to 70 ns due to the propagation delays of the buffer, LPF and PGA.
Table VI in the Register Programming section details the PGA
programming map.
The timing of the interface is fully described in the Digital Inter-
face Port Timing section.
CLOCK DISTRIBUTION
The DAC sampling clock, fDAC, is generated by the internal
digital phase-locked loop (DPLL). fDAC has a frequency equal to
L × fOSCIN, where fOSCIN is the internal signal generated either by
the crystal oscillator when a crystal is connected between the
OSC IN and XTAL pins or by the clock that is fed into the
OSC IN pin, and L is the multiplier programmed through the
serial port. L can have the values of 1, 2, 4, or 8.
When the interpolation filter is enabled (either 2× LPF or 2× BPF
is selected), the data rate is upsampled by a factor of two. In this
case, the transmit path expects a new data input word at the rate
of fDAC/2. When the interpolation filter is bypassed, the transmit
path expects a new input word at the same frequency as DAC
sampling clock, fDAC. Therefore, in terms of fOSCIN, the TXCLK
frequency should be:
GAIN REGISTER
5ns
DECODE LOGIC
fTXCLK = L × fOSCIN /K
where K is the interpolation factor. The interpolation factor, K, is
equal to 2 when the interpolator is enabled and is equal to 1 when
the interpolator is bypassed.
BUFFER
10ns
DIGITAL HPF
1 CLK CYCLE
SHA
A/D
LPF
PGA
10ns
5 CLK CYCLE 1/2 CLK CYCLE
25ns OR 50ns
The ADC sampling clock is derived from fOSCIN and a new
output sample is available every fOSCIN clock cycle. The ADC
sampling lock can be programmed to be equal to fOSCIN if desired.
The timing of the digital interface port is illustrated in the
Figures 3 and 4.
Figure 2. AGC Loop Timing
–14–
REV. 0
AD9975
DIGITAL INTERFACE PORT TIMING
Table III. Instruction Byte Bit Definitions
The ADIO[9:0] bus accepts input data-words into the transmit
path when the TXEN pin is high, the RXEN pin is low, and a
clock is present on the TXCLK pin. Figure 3 illustrates the
transmit path input timing.
MSB
I7
LSB
I6
I5
I4
I3
I2
I1
I0
R/W N1
N0
A4
A3
A2
A1
A0
tSU
Bit I7 – R/W
TXCLK
This bit determines whether a read or a write data transfer will
occur after the instruction byte write. Logic high indicates a read
operation, and Logic 0 indicates a write operation.
TXEN
tHD
ADIO[9:0]
TX0
TX1
TX2
TX3
TX4
Bits I6:I5 – N1:N0
These two bits determine the number of bytes to be transferred
during the data transfer cycle. The bit decodes are shown in
Table IV.
RXEN
Figure 3. Transmit Data Input Timing Diagram
It should be noted that to clear the transmit path input buffers,
an additional six clock cycles on the TXCLK input are required
after TXEN goes low. The interpolation filters will be “flushed”
with zeros if the clock signal into the TXCLK pin is present for
48 clock cycles after TXEN goes low (the data on the ADIO
bus being irrelevant over this interval).
Table IV. N1:N0 Bit Map
N1:N0
Description
0:0
0:1
1:0
1:1
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
The output from the receive path will be driven onto the
ADIO[9:0] bus when the RXEN pin is high, and a clock is present
on the RXCLK pin. When both TXEN and RXEN are low, the
ADIO[9:0] bus is three-stated. Figure 4 illustrates the receive
path output timing.
Bits I4:I0 - A4:A0
These bits determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The remaining
register addresses are generated by the AD9975.
tVT
RXCLK
Serial Interface Port Pin Description
SCLK—Serial Clock
tHT
RXEN
The serial clock pin is used to synchronize data transfers to and
from the AD9975 and to run the internal state machines. SCLK
maximum frequency is 25 MHz. All data transmitted to the
AD9975 is sampled on the rising edge of SCLK. All data read
from the AD9975 is validated on the rising edge of SCLK and is
updated on the falling edge.
ADIO[9:0]
RX0
RX1
RX2
RX3
Figure 4. Receive Data Output Timing Diagram
SENABLE—Serial Interface Enable
SERIAL INTERFACE FOR REGISTER CONTROL
The serial port is a 3-wire serial communications port consisting
of a clock (SCLK), chip select (SENABLE), and a bidirectional
data (SDATA) signal. The interface allows read/write access to
all registers that configure the AD9975 internal parameters.
Single or multiple byte transfers are supported as well as MSB
first or LSB first transfer formats.
The SENABLE Pin is active low. It enables the serial communi-
cation to the device. SENABLE select should stay low during
the entire communication cycle. All input on the serial port is
ignored when SENABLE is inactive.
SDATA—Serial Data I/O
The signal on this line is sampled on the first eight rising edges
of SCLK after SENABLE goes active. Data is then read from or
written to the AD9975 depending on what was read.
General Operation of the Serial Interface
Serial communication over the serial interface can be from 1 byte
to 5 bytes in length. The first byte is always the instruction byte.
The instruction byte establishes whether the communication is
going to be a read or write access, the number of data bytes to be
transferred, and the address of the first register to be accessed.
The instruction byte transfer is complete immediately upon the
eighth rising edge of SCLK after SENABLE is asserted. Likewise,
the data registers change immediately upon writing to the eighth
bit of each data byte.
Figures 5 and 6 show the timing relationships between the three
SPI signals.
tDS
tSCLK
SENABLE
tPWH
tPWL
SCLK
Instruction Byte
The instruction byte contains the information shown in Table III.
tHT
tDS
SDATA
INSTRUCTION BIT 7
INSTRUCTION BIT 6
Figure 5. Timing Diagram Register Write to AD9975
REV. 0
–15–
AD9975
Figures 7a and 7b show how the serial port words are built for
each of these modes.
SCLK
tDV
INSTRUCTION CYCLE
DATATRANSFER CYCLE
SDATA
INSTRUCTION BIT n
INSTRUCTION BIT n–1
SENABLE
SCLK
Figure 6. Timing Diagram Register Read from AD9975
R/W I6
I5
(n)
I4
I3
I2
I1
I0
D7
D6
D6
D7
n
SDATA
(n)
n
n
n
MSB/LSB Transfers
The AD9975 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
bit order is controlled by the SPI LSB First Bit (Register 0, Bit 6).
The default value is 0, MSB first. Multibyte data transfers in
MSB format can be completed by writing an instruction byte
that includes the register address of the last address to be accessed.
The AD9975 will automatically decrement the address for each
successive byte required for the multibyte communication cycle.
Figure 7a. Serial Register Interface Timing MSB First
INSTRUCTION CYCLE
DATATRANSFER CYCLE
SENABLE
SCLK
I0
I1
I2
I3
I4 I5
I6
(n)
R/W D0
D1
D2
D6
D7
n
SDATA
(n)
0
0
0
n
Figure 7b. Serial Register Interface Timing LSB First
When the SPI LSB First Bit (Register 0, Bit 6) is set high, the
serial port interprets both instruction and data bytes LSB first.
Multibyte data transfers in LSB format can be completed by
writing an instruction byte that includes the register address of
the first address to be accessed. The AD9975 will automatically
increment the address for each successive byte required for the
multibyte communication cycle.
Notes on Serial Port Operation
The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all regis-
ters except Register 0 are set to their default values. Register 0
will remain at the last value sent, with the exception that the
Software Reset Bit will be set to 0.
Table V. Register Layout
Address
(hex)
Default
(hex)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
00
Select 4-Wire LSB/MSB Software
00
R/W
SPORT
First
Reset
01
Power-
Down
PLL-A
Power-
Down
DAC
Power-Down Power-Down Power-
Interpolators RX Reference Down ADC Receive Filter
and SPGA and CPGA
Power-Down 00
R/W
02
03
00
01
R/W
R/W
ADC Clock
Source
PLL-A (xL)
Multiplier [1:0]
OSC IN/2
04
RX LPF
Tuning
Update
Disable
RX LPF
Tuning
Update in Correction Bypass
Progress
RX Path RX Digital Fast ADC
Wideband RX Enable
RX LPF
Bypass
01
R/W
DC Offset HPF
Sampling
LPF
1-Pole
RX LPF
05
06
RX LPF Filter Tuning Target [7:0]
80
00
R/W
R/W
RXBOOST
Active Low
RXBOOST PGA Gain
Setting
RX PGA Gain [4:0]
through
Register
07
08
0F
TX Interpolation Filter Select
Sample TX TX Data
on Falling Input Twos
TXCLKIN Complement
10
00
00
R/W
R/W
R
CLK-B Equal CLK-A
to OSC IN/4 Equal
CLK-B
Output
CLK-A Three-State
ADC Output RX Data
on Falling Output Twos
Output
Disable
RX Port
to OSC IN Disable
RXCLK
Complement
Version [3:0]
–16–
REV. 0
AD9975
The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE went active. On every eighth rising edge of SCLK, a
byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9975 are not simultaneously
updated but occur sequentially. For this reason, it is recom-
mended that single byte transfers be used when changing the
SPI configuration or performing a software reset.
Bit 1,0: PLL-A Multiplier
Bits 1 and 0 determine the multiplication factor (L) for PLL-A
and the DAC sampling clock frequency, FDAC. FDAC = L × FCLKIN
Bit 1,0
.
0,0: L = 1
0,1: L = 2
1,0: L = 4
1,1: L = 8
Bit 6: ADC Clock Source OSC IN/2
REGISTER PROGRAMMING DEFINITIONS
Register 0, RESET/SPI Configuration
Setting Bit 6 high selects the the OSC IN clock signal divided by
2 as the ADC sampling clock source. Setting Bit 6 low selects
the OSC IN clock to be used directly as the ADC sampling
clock source. The best ADC performance is achieved by using
an external crystal or by driving the OSC IN pin with a low jitter
clock source.
Bit 5: Software Reset
Setting this bit high resets the chip. The PLLs will relock to the
input clock and all registers (except Register 0x0, Bit 6) revert
to their default values. Upon completion of the reset, Bit 5 is
reset to 0.
Register 4, Receive Filter Selection
The content of the interpolator stage is not cleared by software
or hardware resets. It is recommended to “flush” the transmit
path with zeros before transmitting data.
The AD9975 receive path has a continuous time 4-pole LPF
and a 1-pole digital HPF. The 4-pole LPF has two selectable
cutoff frequencies. Additionally, the filter can be tuned around
those two cutoff frequencies. These filters can also be bypassed
to different degrees as described below.
Bit 6: LSB/MSB First
Setting this bit high causes the serial port to send and receive
data least significant bit (LSB) first. The default low state con-
figures the serial port to send and receive data most significant
bit (MSB) first.
The continuous time 4-pole low-pass filter is automatically
calibrated to one of two selectable cutoff frequencies. The cutoff
frequency, Fcutoff, is described as a function of the ADC sampling
frequency FADC and can be influenced 15% by the RX filter
tuning target word in Register 5.
Bit 7: Select 4-Wire SPORT
Setting this bit high puts the serial port into a four-line mode.
The SCLK and SENABLE retain their normal functions,
SDATA becomes an input only line, and the RXBOOST/SDO
pin becomes the serial port output. When in 4-wire mode, the
data on the RXBOOST/SDO pin will change on the falling edge
of SCLK and should be sampled on the rising edge of SCLK.
F
= FADC × 64 / 64 + Target
(
)
cutoff_low
F
= FADC ×158 / 64 + Target
(
)
cutoff_ high
Bit 0: RX LPF Bypass
Setting this bit high bypasses the 4-pole LPF. The filter is auto-
matically powered down when this bit is set.
Register 1, Power-Down
Bit 0: Power-Down Receive Filter and CPGA
Setting this bit high powers down and bypasses the RX LPF
and continuous time programmable gain amplifier.
Bit 1: Enable 1-Pole RX LPF
The AD9975 can be configured with a 1-pole filter when the
4-pole receive low-pass filter is bypassed. The 1-pole filter is
untrimmed and subject to cutoff frequency variations of 20%.
Bit 1: Power-Down ADC and SPGA
Setting this bit high powers down the ADC and the switched
capacitor programmable gain amplifier (SPGA).
Bit 2: Wideband RX LPF
This bit selects the nominal cutoff frequency of the 4-pole LPF.
Setting this bit high selects a nominal cutoff frequency of 28.8 MHz.
When the wideband filter is selected, the RX path gain is limited
to 30 dB.
Bit 2: Power-Down RX Reference
Setting this bit high powers down the ADC reference. This bit
should be set if an external reference is applied.
Bit 3: Fast ADC Sampling
Bit 3: Power-Down Interpolators
Setting this bit increases the quiescent current in the SVGA block.
This may provide some performance improvement when the ADC
sampling frequency is greater than 40 MSPS.
Setting this bit high powers down the transmit digital interpolator.
It does not clear the content of the data path.
Bit 4: Power-Down DAC
Setting this bit high powers down the transmit DAC.
Bit 4: RX Digital HPF Bypass
Setting this bit high bypasses the 1-pole digital HPF that follows
the ADC. The digital filter must be bypassed for ADC sampling
above 50 MSPS.
Bit 5: Power-Down PLL-A
Setting this bit high powers down the on-chip phase-locked loop
that generates the transmit path clocks and the auxiliary clock
CLK-A. When powered down, the CLK-A output goes to a high
impedance state.
Bit 5: RX Path DC Offset Correction
Writing a 1 to this bit triggers an immediate receive path offset
correction and reads back 0 after the completion of the offset
correction.
Register 3, Clock Source Configuration
The AD9975 contains a programmable PLL referred to as PLL-A.
The output of the PLL is used to generate the internal clocks for
the TX path and the auxiliary clock, CLK-A.
Bit 6: RX LPF Tuning Update in Progress
This bit indicates when receive filter calibration is in progress.
The duration of a receive filter calibration is about 500 µs.
Writing to this bit has no effect.
REV. 0
–17–
AD9975
Bit 7: RX LPF Tuning Update Disable
Table VI. PGA Programming Map
Setting this bit high disables the automatic background receive
filter calibration. The AD9975 automatically calibrates the
receive filter on reset and every few (~2) seconds thereafter to
compensate for process and temperature variation, power supply,
and long term drift. Programming a 1 to this bit disables this
function. Programming a 0 triggers an immediate first calibration
and enables the periodic update.
RX Path
Gain [4:0]
RX Path
Gain
CPGA
Gain
SPGA
Gain
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12*
0x13*
0x14*
0x15*
–6
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
24
0
0
0
0
0
0
6
6
–6
–4
–2
0
2
4
0
2
4
0
2
4
0
2
4
0
2
4
Register 5, Receive Filter Tuning Target
This register sets the filter tuning target as a function of FOSCIN
See Register 4 description.
.
Register 6, RX Path Gain Adjust
The AD9975 uses a combination of a continuous time PGA
6
12
12
12
18
18
18
24
24
24
24/30
24/30
24/30
24/30
(CPGA) and a switched capacitor PGA (SPGA) for a gain range
of –6 dB to +36 dB with a resolution of 2 dB. The RX path gain
can be programmed over the serial interface by writing to the
RX path Gain Adjust Register or directly using the GAIN and
MSB aligned TX[5:1] Bits. The register default value is 0x00 for
the lowest gain setting (–6 dB). The register always reads back the
actual gain setting irrespective of which of the two programming
modes was used.
26
28
30/30
30/32
30/34
30/36
Bits [4:0]: RX PGA Gain
6/0
6/2
6/4
6/6
Table VI describes the gains and how they are achieved as a
function of the RX path adjust bits. It should be noted that the
value of these bits will read back the actual gain value to which
the PGA is set. If Bit 5 of this register is low, then the value read
back will be that set by the AGC[2:0] Pins.
*When the wideband RX filter bit is set high, the RX path gain is limited to 30 dB.
The first of the two values refers to the mode when the lower RX LPF cutoff
frequency is chosen, or when the RX LPF filter is bypassed.
Bit 5: PGA Gain Set through Register
Setting this bit high will result in the RX path gain being set by
writing to the PGA Gain Control Register. Default is zero, which
selects writing the gain through the AGC[2:0] pins in conjunction
with the RXBOOST pin.
Register 7, Transmit Path Settings
Bit 0: TX Data Input Twos Complement
Setting this bit high changes the TX path input data format to
twos complement. When this bit is low, the TX data format is
straight binary.
Bit 6: RXBOOST
This bit is read-only. It reflects the level of the RXBOOST pin.
Bit 1: Sample TX Data on Falling TXCLKIN
If Bit 1 is set high, the TX path data will be sampled on the
falling edge of TXCLKIN. When this bit is low, the data will be
sampled on the rising edge of TXCLKIN.
Bit 7: RXBOOST Active Low
Setting this bit high results in the value mapped to the RXBOOST
pin by the AGC inputs being inverted.
Bit 4 to Bit 7: Interpolation Filter Select
Bits 4 to 7 define the interpolation filter characteristic and inter-
polation rate.
Bits 7:4;
0x1; see TPC 1. 2ϫ Interpolation, LPF.
0x2; Interpolation Bypass.
0x5; see TPC 2. 2ϫ Interpolation, BPF, Adj image.
The interpolation factor has a direct influence on the rate at
which the TX path will read the input data-words from the input
buffer. When the interpolation filter has been bypassed, the data
will be read out of the buffer at a rate of FOSCIN ϫ L. When the
interpolator is configured to run in either of the 2ϫ interpola-
tion modes, the data will be read out of the buffer at a rate of
0.5 ϫ FOSCIN ϫ L.
Register 8, Receiver and Clock Output Settings
Bit 0: Rx Data Output Twos Complement
Setting this bit high changes the RX path input data format to
twos complement. When this bit is low, the RX data format is
straight binary.
–18–
REV. 0
AD9975
Bit 1: ADC Output on Falling RXCLK
Power Planes and Decoupling
If Bit 1 is set high, the TX path data will be sampled on the falling
edge of RXCLK. When this bit is low, the data will be sampled on
the rising edge of RXCLK.
The AD9975 evaluation board demonstrates a good power supply
distribution and decoupling strategy. The board has four layers;
two signal layers, one ground plane, and one power plane. The
power plane is split into a 3VDD section, which is used for the
3 V digital logic circuits; a DVDD section, which is used to supply
the digital supply pins of the AD9975; an AVDD section, which
is used to supply the analog supply pins of the AD9975; and a
VANLG section, which supplies the higher voltage analog com-
ponents on the board. The 3VDD section will typically have the
highest frequency currents on the power plane and should be
kept the furthest from the MxFE and analog sections of the board.
The DVDD portion of the plane brings the current used to power
the digital portion of the MxFE to the device. This should be
treated similar to the 3VDD power plane and be kept from
going underneath the MxFE or analog components. The MxFE
should largely sit on the AVDD portion of the power plane.
Bit 3: Three-State RX Port
This bit sets the receive output RX[5:0] into a high impedance
three-state mode. It allows for sharing the bus with other devices.
Bit 4: CLK-A Output Disable
Setting Bit 4 high fixes the CLK-A output to a Logic 0 output level.
Bit 5: CLK-B Output Disable
Setting Bit 5 high fixes the CLK-A output to a Logic 0 output level.
Bit 6: CLK-A Equal to OSC IN
Setting Bit 6 high sets the CLK-A output signal frequency equal
to the OSC IN signal frequency. Otherwise, the CLK-A output
frequency is equal to FOSCIN × L.
Bit 7: CLK-B Equal to OSC IN/4
The AVDD and DVDD power planes may be fed from the same
low noise voltage source; however, they should be decoupled
from each other to prevent the noise generated in the DVDD
portion of the MxFE from corrupting the AVDD supply. This
can be done by using ferrite beads between the voltage source and
DVDD and between the source and AVDD. Both DVDD and
AVDD should have a low ESR, bulk decoupling capacitor on the
MxFE side of the ferrite as well as a low ESR, ESL decoupling
capacitors on each supply pin (i.e., the AD9975 requires five
power supply decoupling caps, one each on Pins 5, 38, 47, 14, and
35). The decoupling caps should be placed as close to the MxFE
supply pins as possible. An example of the proper decoupling is
shown in the AD9975 evaluation board schematic.
Setting Bit 7 high sets the CLKB output signal frequency equal
to the OSC IN/4 signal frequency. Otherwise, the CLKB output
frequency is equal to OSC IN/2.
Register F, Die Revision
This register stores the die revision of the chip. It is a read-only
register.
PCB DESIGN CONSIDERATIONS
Although the AD9975 is a mixed signal device, the part should
be treated as an analog component. The digital circuitry on-chip
has been specially designed to minimize the impact that the
digital switching noise will have on the operation of the analog
circuits. Following the power, grounding, and layout recom-
mendations in this section will help you get the best performance
from the MxFE.
Ground Planes
In general, if the component placing guidelines discussed earlier
can be implemented, it is best to have at least one continuous
ground plane for the entire board. All ground connections should
be made as short as possible. This will result in the lowest imped-
ance return paths and the quietest ground connections.
Component Placement
If the three following guidelines of component placement are
followed, chances for getting the best performance from the
MxFE are greatly increased. First, manage the path of return cur-
rents flowing in the ground plane so that high frequency switching
currents from the digital circuits do not flow on the ground plane
under the MxFE or analog circuits. Second, keep noisy digital
signal paths and sensitive receive signal paths as short as possible.
Third, keep digital (noise generating) and analog (noise suscep-
tible) circuits as far away from each other as possible.
If the components cannot be placed in a manner that would keep
the high frequency ground currents from traversing under the
MxFE and analog components, it may be necessary to put current
steering channels into the ground plane to route the high frequency
currents around these sensitive areas. These current steering
channels should be made only when and where necessary.
Signal Routing
In order to best manage the return currents, pure digital circuits
that generate high switching currents should be closest to the
power supply entry. This will keep the highest frequency return
current paths short and prevent them from traveling over the
sensitive MxFE and analog portions of the ground plane. Also,
these circuits should be generously bypassed at each device that
will further reduce the high frequency ground currents. The
MxFE should be placed adjacent to the digital circuits such that
the ground return currents from the digital sections will not flow
in the ground plane under the MxFE. The analog circuits should
be placed furthest from the power supply.
The digital RX and TX signal paths should be kept as short as
possible. Also, the impedance of these traces should have a con-
trolled impedance of about 50 Ω. This will prevent poor signal
integrity and the high currents that can occur during undershoot
or overshoot caused by ringing. If the signal traces cannot be kept
shorter than about 1.5 inches, then series termination resistors
(33 Ω to 47 Ω) should be placed close to all signal sources. It is
a good idea to series terminate all clock signals at their source
regardless of trace length.
The receive RX+/RX– signals are the most sensitive signals on the
entire board. Careful routing of these signals is essential for good
receive path performance. The RX+/RX– signals form a differential
pair and should be routed together as a pair. By keeping the traces
adjacent to each other, noise coupled onto the signals will appear
as common mode and will be largely rejected by the MxFE receive
input. Keeping the driving point impedance of the receive signal low
and placing any low-pass filtering of the signals close to the MxFE
will further reduce the possibility of noise corrupting these signals.
The AD9975 has several pins that are used to decouple sensitive
internal nodes. These pins are REFIO, REFB, and REFT. The decou-
pling capacitors connected to these points should have low ESR
and ESL. These capacitors should be placed as close to the MxFE
as possible and be connected directly to the analog ground plane.
The resistor connected to the FS ADJ pin should also be placed
close to the device and connected directly to the analog ground plane.
REV. 0
–19–
AD9975
OUTLINE DIMENSIONS
48-Lead Plastic Quad Flatpack [LQFP]
1.4 mm Thick
(ST-48)
Dimensions shown in millimeters
1.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.45
9.00 BSC
37
48
36
1
SEATING
PLANE
1.45
1.40
1.35
0.20
0.09
7.00
BSC
TOP VIEW
(PINS DOWN)
VIEW A
7؇
3.5؇
0؇
0.15
0.05
25
12
SEATING
PLANE
24
0.08 MAX
13
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90؇ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
–20–
REV. 0
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