AD9983AKSTZ-1401 [ADI]
High Performance 8-Bit Display Interface; 高性能8位显示器接口
| 型号： | AD9983AKSTZ-1401 |
| 厂家： | 
ADI |
| 描述： | High Performance 8-Bit Display Interface |
| 文件： | 总44页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance
8-Bit Display Interface
AD9983A
Preliminary Technical Data
FEATURES
FUNCTIONAL BLOCK DIAGRAM
8-bit analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
AD9983A
8
AUTO OFFSET
AUTO GAIN
Pr/RED
Pr/RED
8
IN1
IN0
2:1
MUX
8-BIT
ADC
Cb/Cr/RED
CLAMP
CLAMP
CLAMP
PGA
PGA
PGA
OUT
8
8
AUTO OFFSET
AUTO GAIN
Y/GREEN
Y/GREEN
8
8
IN1
2:1
MUX
8-BIT
ADC
Y/GREEN
OUT
IN0
AUTO OFFSET
AUTO GAIN
External clock input
Regenerated Hsync output
Pb/BLUE
Pb/BLUE
IN1
2:1
MUX
8-BIT
ADC
Cb/BLUE
OUT
IN0
Programmable output high impedance control
Hsyncs per Vsync counter
Sync-on-green pulse filter
HSYNC1
HSYNC0
2:1
MUX
DATACK
SOGOUT
SYNC
VSYNC0
VSYNC1
2:1
MUX
Pb-free package
PROCESSING
O/E FIELD
HSOUT
PLL
POWER
MANAGEMENT
SOGIN1
SOGIN0
2:1
MUX
APPLICATIONS
VSOUT/A0
Advanced TVs
EXTCK/COAST
CLAMP
Plasma display panels
LCDTV
HDTV
REFHI
FILT
VOLTAGE
REFS
REFLO
SDA
SCL
SERIAL REGISTER
RGB graphics processing
LCD monitors and projectors
Scan converters
Figure 1.
GENERAL DESCRIPTION
The AD9983A is a complete 8-bit, 170 MSPS, monolithic
analog interface optimized for capturing YPbPr video and RGB
graphics signals. Its 170 MSPS encode rate capability and full
power analog bandwidth of 300 MHz support all HDTV video
modes up to 1080p as well as graphics resolutions up to UXGA
(1600 x 1200 at 60 Hz).
sampling clock phase adjustment is provided. Output data,
sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore
the signal reference levels and to automatically calibrate out any
offset differences between the three channels. The auto channel-
to-channel gain matching feature can be enabled to minimize
any gain mismatches between the three channels.
The AD9983A includes a 170 MHz triple ADC with an internal
reference, a PLL, and programmable gain, offset, and clamp
control. The user provides only a 1.8 V power supply and an
analog input. Three-state CMOS outputs can be powered from
1.8 V to 3.3 V.
The AD9983A also offers full sync processing for composite
sync and sync-on-green applications. A clamp signal is
generated internally or may be provided by the user through the
CLAMP input pin.
The AD9983A on-chip PLL generates a sample clock from the
tri-level sync (for YPbPr video) or the horizontal sync (for RGB
graphics). Sample clock output frequencies range from 10 MHz
to 170 MHz. With internal coast generation, the PLL maintains
its output frequency in the absence of sync input. A 32-step
Fabricated in an advanced CMOS process, the AD9983A is
provided in a space-saving 80-lead, Pb-free, LQFP surface-
mount plastic package or a 64-lead LFCSP package, and is
specified over the 0°C to 70°C temperature range.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD9983A
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
2-Wire Serial Control Port............................................................ 22
Data Transfer via Serial Interface............................................. 22
2-Wire Serial Register Map ........................................................... 24
2-Wire Serial Control Registers.................................................... 30
Chip Identification..................................................................... 30
PLL Divider Control .................................................................. 30
Clock Generator Control .......................................................... 30
Phase Adjust................................................................................ 30
Input Gain ................................................................................... 31
Input Offset ................................................................................. 31
Hsync Controls........................................................................... 31
Vsync Controls ........................................................................... 32
Coast and Clamp Controls........................................................ 33
SOG Control ............................................................................... 34
Input and Power Control........................................................... 35
Output Control........................................................................... 36
Sync Processing .......................................................................... 37
Detection Status.......................................................................... 37
Polarity Status ............................................................................. 38
Hsync Count ............................................................................... 38
Test Registers............................................................................... 38
PCB Layout Recommendations.................................................... 40
Analog Interface Inputs............................................................. 40
Outputs (Both Data and Clocks).............................................. 41
Digital Inputs .............................................................................. 41
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Specifications..................................................................................... 3
Analog Interface Characteristics ................................................ 3
Absolute Maximum Ratings............................................................ 5
Explanation of Test Levels........................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Theory of Operation ...................................................................... 11
Digital Inputs .............................................................................. 11
Analog Input Signal Handling.................................................. 11
Hsync and Vsync Inputs............................................................ 11
Serial Control Port ..................................................................... 11
Output Signal Handling............................................................. 11
Clamping ..................................................................................... 11
Gain and Offset Control............................................................ 12
Sync-on-Green............................................................................ 13
Reference Bypassing................................................................... 13
Clock Generation ....................................................................... 14
Sync Processing........................................................................... 16
Power Management.................................................................... 19
Timing Diagrams........................................................................ 19
Hsync Timing ............................................................................. 20
Coast Timing............................................................................... 21
Output Formatter ....................................................................... 21
Rev. PrA | Page 2 of 44
Preliminary Technical Data
AD9983A
SPECIFICATIONS
ANALOG INTERFACE CHARACTERISTICS
VD = 1.8 V, VDD = 3.3 V, PVD = 1.8 V, DAVDD = 1.8 V, ADC clock = maximum conversion rate, full temperature range = 0°C to 70°C.
Table 1.
AD9983AKSTZ-140
AD9983AKCPZ-140
AD9983AKSTZ-170
AD9983AKCPZ-170
Test
Level
1
Temp
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Number of bits
LSB Size
8
8
Bits
% of Full Scale
0.391
0.391
DC ACCURACY
Differential Nonlinearity
25°C
Full
25°C
Full
I
VI
I
VI
VI
0.8
1.0
0.9
1.0
LSB
LSB
Integral Nonlinearity
+2.25/−1.8 +2.5/−2.0 LSB
+2.65/−3.0
LSB
No Missing Codes2
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Full
Full
Full
25°C
25°C
Full
Full
Full
VI
VI
V
IV
IV
VI
VI
0.5
0.5
V p–p
V p–p
ppm/°C
μA
μA
% FS
% FS
1.0
1.0
125
125
Input Bias Current
1
1
1
1
Input Full-Scale Matching
Offset Adjustment Range
1
1
50
50
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Clock to Data Skew tSKEW
tBUFF
tSTAH
tDHO
tDAL
tDAH
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
VI
IV
IV
IV
IV
140
170
MSPS
MSPS
ns
μs
μs
μs
μs
μs
ns
10
2.0
10
2.0
−0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
140
−0.5
4.7
4.0
0
4.7
4.0
250
4.7
4.0
170
tDSU
tSTASU
tSTOSU
μs
μs
Maximum PLL Clock Rate
Minimum PLL Clock Rate
Jitter
MHz
MHz
pS p-p
pS p-p
pS/°C
10
10
7003
15
9253
Sampling Phase Tempco
DIGITAL INPUTS
15
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
Full
Full
Full
Full
25°C
VI
VI
V
V
V
1.0
1.0
V
V
μA
μA
pF
0.8
−1.0
1.0
0.8
−1.0
1.0
2
2
Rev. PrA | Page 3 of 44
AD9983A
Preliminary Technical Data
AD9983AKSTZ-140
AD9983AKCPZ-140
AD9983AKSTZ-170
AD9983AKCPZ-170
Test
Level
1
Temp
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
Duty Cycle, DATACK
Output Coding
Full
Full
Full
VI
VI
IV
VDD − 0.1
45
VDD − 0.1
45
V
V
%
0.1
55
0.1
55
50
Binary
50
Binary
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
Full
Full
Full
Full
IV
IV
IV
IV
V
1.7
1.7
1.7
1.7
1.8
3.3
1.8
1.8
250
31
1.9
3.47
1.9
1.755
1.7
1.7
1.8
3.3
1.8
1.8
255
34
1.9
3.47
1.9
V
V
V
V
mA
mA
mA
mA
mW
mA
mW
DAVDD Supply Voltage
VD Supply Current (ID)
VDD Supply Current (IDD)
PVD Supply Current (IPVD)
DAVDD Supply Current (IDAVDD)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Crosstalk
1.9
1.7
1.9
25°C
25°C
25°C
25°C
Full
V
V
9
9
V
16
19
VI
VI
VI
710
740
Full
Full
10
18
10
18
25°C
Full
V
V
300
60
300
60
MHz
dBc
1 See the Explanation of Test Levels section.
2 Guaranteed by design, not production tested.
3 Jitter measurements taken at UXGA with recommended PLL settings.
Rev. PrA | Page 4 of 44
Preliminary Technical Data
AD9983A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
EXPLANATION OF TEST LEVELS
Rating
I. 100% production tested.
VD
1.98 V
VDD
PVD
DAVDD
Analog Inputs
REFHI
REFLO
Digital Inputs
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
3.6 V
1.98 V
1.98 V
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
VD to 0.0 V
VD to 0.0 V
VD to 0.0 V
5 V to 0.0 V
20 mA
−25°C to + 85°C
−65°C to + 150°C
150°C
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
THERMAL RESISTANCE
150°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3. Thermal Resistance
Package Type
80-lead LQFP
64-lead LFCSP
θJA
35
35
θJC
16
16
Unit
°C/W
°C/W
ESD CAUTION
Rev. PrA | Page 5 of 44
AD9983A
Preliminary Technical Data
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
V
(1.8V)
BLUE 1
D
PIN 1
INDICATOR
2
3
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
B
BLUE 2
BLUE 3
BLUE 4
BLUE 5
BLUE 6
BLUE 7
GND
AIN0
GND
4
B
AIN1
5
V
(1.8V)
D
6
G
AIN0
GND
SOGIN0
7
8
AD9983A
TOP VIEW
(Not to Scale)
9
V
(1.8V)
V
(3.3V)
D
DD
10
11
12
13
14
15
16
17
18
19
20
G
NC
NC
AIN1
GND
SOGIN1
(1.8V)
GREEN 0
GREEN 1
GREEN 2
GREEN 3
GREEN 4
GREEN 5
GREEN 6
GREEN 7
V
D
R
AIN0
GND
R
AIN1
PWRDN
REFLO
NC
REFHI
DAV (1.8V)
DD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC = NO CONNECT
Figure 2. 80-Lead LQFP Pin Configuration
Rev. PrA | Page 6 of 44
Preliminary Technical Data
AD9983A
64
58
63 62 61 60 59
57 56 55 54 53
51 50 49
52
48
O/E FIELD
1
2
3
4
5
6
GREEN 7
GREEN 6
GREEN 5
GREEN 4
GREEN 3
GREEN 2
GREEN 1
GREEN 0
NC
PIN 1
INDICATOR
47 REFHI
46
45
44
43
REFLO
PWRDN
R
AIN1
R
AIN0
AD9983A
42
41
V
D
7
8
TOP VIEW
SOGIN1
(Not to Scale)
40
39
38
G
9
AIN1
V
D
10
11
NC
SOGIN0
BLUE 7
BLUE 6
37
G
12
AIN0
36
35
34
V
D
BLUE 5 13
B
14
15
BLUE 4
BLUE 3
AIN1
B
AIN0
33
V
D
BLUE 2 16
17 18 19 20 21 22 23 24 25 26 27 28
30 31 32
29
NC = NO CONNECT
Figure 3. 64-Lead LFCSP Pin Configuration
Table 4. Complete Pinout List
Pin Number
80-Lead LQFP 64-Lead LFCSP
Pin Type
Mnemonic
RAIN0
RAIN1
GAIN0
GAIN1
Function
Value
Inputs
14
16
6
43
44
37
40
34
35
26
24
27
25
38
41
28
29
28
45
Channel 0 Analog Input for Converter R
Channel 1 Analog Input for Converter R
Channel 0 Analog Input for Converter G
Channel 1 Analog Input for Converter G
Channel 0 Analog Input for Converter B
Channel 1 Analog Input for Converter B
Horizontal Sync Input for Channel 0
Horizontal Sync Input for Channel 1
Vertical Sync Input for Channel 0
Vertical Sync Input for Channel 1
Input for Sync-on-Green Channel 0
Input for Sync-on-Green Channel 1
External Clock Input
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
10
2
4
70
68
71
69
8
BAIN0
BAIN1
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
EXTCK
CLAMP
COAST
PWRDN
12
721
73
721
17
External Clamp Input Signal
External PLL Coast Signal Input
Power-Down Control
Rev. PrA | Page 7 of 44
AD9983A
Preliminary Technical Data
Pin Number
Pin Type
80-Lead LQFP
64-Lead LFCSP
54 to 61
1 to 8
11 to 18
52
Mnemonic
RED [7:0]
GREEN [7:0]
BLUE [7:0]
DATACK
Function
Value
Outputs
28 to 35
42 to 49
54 to 61
25
Outputs of Converter R, Bit 9 is the MSB
Outputs of Converter G, Bit 9 is the MSB
Outputs of Converter B, Bit 9 is the MSB
Data Output Clock
Hsync Output Clock (Phase-Aligned with
DATACK)
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
23
50
HSOUT
222
24
21
78
49
51
48
31
VSOUT
SOGOUT
O/E FIELD
FILT
Vsync Output Clock
Sync-on-Green Slicer Output
Odd/Even Field Output
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
References
Connection for External Filter Components for
Internal PLL
18
20
46
47
REFLO
REFHI
Connection for External Capacitor for Input
Amplifier
Connection for External Capacitor for Input
Amplifier
Power Supply
1, 5, 9, 13
26, 38, 52, 64
74, 76, 79
41
3, 7, 11, 15, 39, 40,
53, 65, 75, 77, 80
33, 36, 39, 42
21, 53
30, 32
VD
VDD
PVD
DAVDD
GND
Analog Power Supply
Output Power Supply
PLL Power Supply
Digital Logic Power Supply
Ground
1.8 V
1.8 V or 3.3 V
1.8 V
1.8 V
0 V
64
Control
66
67
222
22
23
49
SDA
SCL
A0
Serial Port Data I/O
Serial Port Data Clock (100 kHz maximum)
Serial Port Address Input
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
1 EXTCK and COAST share the same pin.
2 VSOUT and A0 share the same pin.
Rev. PrA | Page 8 of 44
Preliminary Technical Data
AD9983A
Table 5. Pin Function Descriptions
Mnemonic
Function
Description
RAIN0
Analog Input for the Red
Channel 0
Analog Input for the Green
Channel 0
Analog Input for the Blue
Channel 0
These are high impedance inputs that accept the red, green, and blue channel graphics
signals, respectively. The three channels are identical and can be used for any colors,
but colors are assigned for convenient reference. They accommodate input signals
ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to
support clamp operation. See Figure 4 and Figure 5.
GAIN0
BAIN0
RAIN1
Analog Input for the Red
Channel 1
GAIN1
Analog Input for the Green
Channel 1
BAIN1
Analog Input for the Blue
Channel 1
HSYNC0
HSYNC1
Horizontal Sync Input
Channel 0
Horizontal Sync Input
Channel 1
These inputs receive a logic signal that establishes the horizontal timing reference and
provides the frequency reference for pixel clock generation. The logic sense of this pin
can be automatically determined by the chip or manually controlled by Serial Register
0x12, Bits[5:4] (Hsync polarity). Only the leading edge of Hsync is used by the PLL; the
trailing edge is used in clamp timing. When Hsync polarity = 0, the falling edge of
Hsync is used. When Hsync polarity = 1, the rising edge is active. The input includes a
Schmitt trigger for noise immunity.
VSYNC0
VSYNC1
Vertical Sync Input Channel 0
Vertical Sync Input Channel 1
These are the inputs for vertical sync and provide timing information for generation of
the field (odd/even) and internal Coast generation. The logic sense of this pin can be
automatically determined by the chip or manually controlled by Serial Register 0x14,
Bits[5:4] (Vsync polarity).
SOGIN0
SOGIN1
Sync-on-Green Input
Channel 0
Sync-on-Green Input
Channel 1
These inputs process signals with embedded sync, typically on the green channel. The
pin is connected to a high speed comparator with an internally generated threshold.
The threshold level can be programmed in 8 mV steps to any voltage between 8 mV
and 256 mV above the negative peak of the input signal. The default voltage threshold
is 128 mV. When connected to an ac-coupled graphics signal with embedded sync, it
produces a noninverting digital output on SOGOUT. This is usually a composite sync
signal, containing both vertical and horizontal sync information that must be separated
before passing the horizontal sync signal for Hsync processing. When not used, this
input should be left unconnected. For more details on this function and how it should
be configured, refer to the Sync-on-Green section.
CLAMP
External Clamp Input
(Optional)
This logic input can be used to define the time during which the input signal is
clamped to ground or midscale. It should be exercised when the reference dc level is
known to be present on the analog input channels, typically during the back porch of
the graphics signal. The CLAMP pin is enabled by setting the control bit clamp function
to 1, (Register 0x18, Bit 4; default is 0). When disabled, this pin is ignored and the clamp
timing is determined internally by counting a delay and duration from the trailing edge
of the Hsync input. The logic sense of this pin can be automatically determined by the
chip or controlled by clamp polarity Register 0x1B, Bits[7:6]. When not used, this pin
may be left unconnected (there is an internal pull-down resistor) and the clamp
function programmed to 0.
EXTCK/COAST
External Clock
EXTCK allows the insertion of an external clock source rather than the internally
generated, PLL locked clock. EXTCK is enabled by programming Register 0x03, Bit 2 to 1.
This pin is shared with the Coast function, which does not affect EXTCK functionality.
Coast Input to Clock
Generator (Optional)
COAST can be used to cause the pixel clock generator to stop synchronizing with Hsync
and continue producing a clock at its current frequency and phase. This is useful when
processing signals from sources that fail to produce Hsync pulses during the vertical
interval. The coast signal is generally not required for PC-generated signals. The logic
sense of this pin can be determined automatically or controlled by Coast polarity
(Register 0x18, Bits[7:6]). When not used and EXTCK not used, this pin may be grounded
and Coast polarity programmed to 1. Input Coast polarity defaults to1 at power-up. This
pin is shared with the EXTCK function, which does not affect coast functionality. For
more details on EXTCK, see the description in this section.
PWRDN
Power-Down Control
This pin can be used along with Register 0x1E, Bit 3 for manual power-down control.
If manual power-down control is selected (Register 0x1E, Bit 4) and this pin is not used,
it is recommended to set the pin polarity (Register 0x1E, Bit 2) to active high and
hardwire this pin to ground with a 10 kΩ resistor.
Rev. PrA | Page 9 of 44
AD9983A
Preliminary Technical Data
Mnemonic
Function
Description
REFLO, REFHI
Input Amplifier Reference
REFLO and REFHI are connected together through a 10 μF capacitor. These are used for
stability in the input ADC circuitry. See Figure 6.
FILT
External Filter Connection
Horizontal Sync Output
For proper operation, the pixel clock generator PLL requires an external filter. Connect the
filter shown in Figure 7 to this pin. For optimal performance, minimize noise and parasitics
on this node. For more information, see the PCB Layout Recommendations section.
HSOUT
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and
duration of this output can be programmed via serial bus registers. By maintaining
alignment with DATACK and Data, data timing with respect to Hsync can always be
determined.
VSOUT/A0
Vertical Sync Output
Pin shared with A0, serial port address. This can be either a separated Vsync from a
composite signal or a direct pass through of the Vsync signal. The polarity of this output can
be controlled via a serial bus bit. The placement and duration in all modes can be set by the
graphics transmitter or the duration can be set by Register 0x14, Bit 1 and Register 0x15,
Bits[7:0]. This pin is shared with the A0 function, which does not affect Vsync Output
functionality. For more details on A0, see the description in the Serial Control Port section.
Serial Port Address Input 0
Pin shared with VSOUT. This pin selects the LSB of the serial port device address,
allowing two Analog Devices parts to be on the same serial bus. A high impedance
external pull-up resistor enables this pin to be read at power-up as 1, or a high
impedance, external pull-down resistor enables this pin to be read at power-up as a 0
and not interfere with the VSOUT functionality.
SOGOUT
Sync-On-Green Slicer
Output
This pin outputs one of four possible signals (controlled by Register 0x1D, Bits[1:0]): raw
SOG, raw Hsync, regenerated Hsync from the filter, or the filtered Hsync. See Figure 9 to
view how this pin is connected. Other than slicing off SOG, the output from this pin
gets no additional processing on the AD9983A. Vsync separation is performed via the
sync separator.
O/E FIELD
Odd/Even Field Bit for
Interlaced Video
This output will identify whether the current field (in an interlaced signal) is odd or even.
SDA
Serial Port Data I/O
Data I/O for the I2C® serial port.
Clock for the I2C serial port.
SCL
Serial Port Data Clock
RED [7:0]
GREEN [7:0]
BLUE [7:0]
Data Output, Red Channel
Data Output, Green Channel
Data Output, Blue Channel
The main data outputs. Bit 9 is the MSB. The delay from pixel sampling time to output is
fixed. When the sampling time is changed by adjusting the phase register, the output
timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
DATACK
Data Clock Output
This is the main clock output signal used to strobe the output data and HSOUT into
external logic. Four possible output clocks can be selected with Register 0x20, Bits[7:6].
Three of these are related to the pixel clock (pixel clock, 90° phase-shifted pixel clock
and 2× frequency pixel clock). They are produced either by the internal PLL clock
generator or EXTCK and are synchronous with the pixel sampling clock. The fourth
option for the data clock output is an internally generated 1⁄2x pixel clock.
The sampling time of the internal pixel clock can be changed by adjusting the phase
register (Register 0x04). When this is changed, the pixel related DATACK timing is also
shifted. The data, DATACK, and HSOUT outputs are all moved so that the timing
relationship among the signals is maintained.
VD (1.8 V)
Main Power Supply
These pins supply power to the main elements of the circuit. They should be as quiet
and filtered as possible.
VDD (1.8 V to 3.3 V)
Digital Output Power Supply A large number of output pins (up to 29) switching at high speed (up to 170 MHz)
generates a lot of power supply transients (noise). These supply pins are identified
separately from the VD pins, so special care can be taken to minimize output noise
transferred into the sensitive analog circuitry. If the AD9983A is interfacing with lower
voltage logic, VDD can be connected to a lower supply voltage (as low as 1.8 V) for
compatibility.
PVD (1.8 V)
Clock Generator Power
Supply
The most sensitive portion of the AD9983A is the clock generation circuitry. These pins
provide power to the clock PLL and help the user design for optimal performance. The
designer should provide quiet, noise-free power to these pins.
DAVDD (1.8 V)
GND
Digital Input Power Supply
Ground
This supplies power to the digital logic.
The ground return for all circuitry on-chip. It is recommended that the AD9983A be
assembled on a single solid ground plane, with careful attention to ground current paths.
Rev. PrA | Page 10 of 44
Preliminary Technical Data
THEORY OF OPERATION
AD9983A
47nF
R
AIN
RGB
INPUT
G
B
The AD9983A is a fully integrated solution for capturing analog
RGB or YPbPr signals and digitizing them for display on
advanced TVs, flat panel monitors, projectors, and other types
of digital displays. Implemented in a high performance CMOS
process, the interface can capture signals with pixel rates of up
to 170 MHz.
AIN
AIN
75Ω
Figure 4. Analog Input Interface Circuit
HSYNC AND VSYNC INPUTS
The interface also accepts Hsync and Vsync signals, which are
used to generate the pixel clock, clamp timing, coast and field
information. These can be either a sync signal directly from the
graphics source, or a preprocessed TTL- or CMOS-level signal.
The AD9983A includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface (I2C). Full integration of these sensitive
analog functions makes system design straightforward and less
sensitive to the physical and electrical environment.
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no
termination is required.
With a typical power dissipation of less than 900 mW and an
operating temperature range of 0°C to 70°C, the device requires
no special environmental considerations.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic; however, it is
tolerant of 5 V logic signals. Refer to the 2-Wire Serial Control
Port section.
DIGITAL INPUTS
All digital inputs on the AD9983A operate to 3.3 V CMOS
levels. The following digital inputs are 5 V tolerant (that is, applying
5 V to them does not cause any damage.): HSYNC0, HSYNC1,
VSYNC0, VSYNC1, SOGIN0, SOGIN1, SDA, SCL and CLAMP.
OUTPUT SIGNAL HANDLING
The digital outputs operate from 1.8 V to 3.3 V (VDD).
ANALOG INPUT SIGNAL HANDLING
CLAMPING
The AD9983A has six high impedance analog input pins for the
red, green, and blue channels. They accommodate signals
ranging from 0.5 V to 1.0 V p-p.
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board ADCs.
Signals are typically brought onto the interface board with a
DVI-I connector, a 15-pin D connector, or RCA connectors.
The AD9983A should be located as close as possible to the
input connector. Signals should be routed using matched-
impedance traces (normally 75 Ω) to the IC input pins.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground, black is at 300 mV, and white is at approximately 1.0 V.
Some common RGB line amplifier boxes use emitter-follower
buffers to split signals and increase drive capability. This
introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9983A.
At the input pins the signal should be resistively terminated
(75 Ω to the signal ground return) and capacitively coupled to
the AD9983A inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced that results in the ADC producing a
black output (Code 0x00) when the known black input is
present. The offset then remains in place when other signal
levels are processed, and the entire signal is shifted to eliminate
offset errors.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The wide bandwidth inputs of the AD9983A
(300 MHz) can track the input signal continuously as it moves
from one pixel level to the next and can digitize the pixel during
a long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. A small inductor in series with the input is
effective in rolling off the input bandwidth slightly and
providing a high quality signal over a wider range of conditions.
Using a Fair-Rite #2508051217Z0-High Speed, Signal Chip
Bead Inductor in the circuit shown in Figure 4 provides good
results in most applications.
Rev. PrA | Page 11 of 44
AD9983A
Preliminary Technical Data
In most PC graphics systems, black is transmitted between
active video lines. With CRT displays, when the electron beam
has completed writing a horizontal line on the screen (at the
right side), the beam is deflected quickly to the left side of the
screen (called horizontal retrace) and a black signal is provided
to prevent the beam from disturbing the image.
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
the three converters has its own selection bit so that they can be
clamped to either midscale or ground independently. These bits
are located in Register 0x18, Bits[3:1]. The midscale reference
voltage is internally generated for each converter.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. Because the input is not at black level at this
time, it is important to avoid clamping during Hsync. Fortu-
nately, there is usually a period following Hsync, called the back
porch, where a good black reference is provided. This is the
time when clamping should be done.
GAIN AND OFFSET CONTROL
The AD9983A contains three PGAs, one for each of the three
analog inputs. The range of the PGA is sufficient to accom-
modate input signals with inputs ranging from 0.5 V to 1.0 V
full scale. The gain is set in three 7-bit registers (red gain [0x05],
green gain [0x07], blue gain [0x09]). For each register, a gain
setting of 0 corresponds to the highest gain, while a gain setting
of 127 corresponds to the lowest gain. Note that increasing the
gain setting results in an image with less contrast.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time with clamp source
(Register 0x18, Bit 4) = 1. The polarity of this signal is set by
the clamp polarity bit, (Register 0x1B, Bits[7:6]).
The offset control shifts the analog input, resulting in a change
in brightness. Three 9-bit registers red offset [Register 0x0B and
Register 0x0C], green offset [Register 0x0D and Register 0x0E],
and blue offset [Register 0x0F and Register 0x10] provide
independent settings for each channel. Note that the function of
the offset register depends on whether auto-offset is enabled
(Register 0x1B, Bit 5).
A simpler method of clamp timing employs the AD9983A
internal clamp timing generator. The clamp placement register
(Register 0x19) is programmed with the number of pixel
periods that should pass after the trailing edge of Hsync
before clamping starts. A second register, clamp duration,
(Register 0x1A) sets the duration of the clamp. These are both
8-bit values, providing considerable flexibility in clamp
generation. The clamp timing is referenced to the trailing edge
of Hsync because, though Hsync duration can vary widely, the
back porch (black reference) always follows Hsync. A good
starting point for establishing clamping is to set the clamp
placement to 0x04 (providing 4 pixel periods for the graphics
signal to stabilize after sync) and set the clamp duration to
0x28 (giving the clamp 40 pixel periods to reestablish the
black reference).
If manual offset is used, seven bits of the offset registers (for the
red channel Register 0x0B, Bits[6:0]) control the absolute offset
added to the channel. The offset control provides 63 LSBs of
adjustment range, with 1 LSB of offset corresponding to 1 LSB
of output code.
Automatic Offset
In addition to the manual offset adjustment mode, the
AD9983A also includes circuitry to automatically calibrate the
offset for each channel. By monitoring the output of each ADC
during the back porch of the input signals, the AD9983A can
self-adjust to eliminate any offset errors in its own ADC
channels and any offset errors present on the incoming graphics
or video signals.
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this
capacitor affects the performance of the clamp. If it is too small,
there will be a significant amplitude change during a horizontal
line time (between clamping intervals). If the capacitor is too
large, it will take too long for the clamp to recover from a large
change in incoming signal offset. The recommended value
(47 nF) results in recovering from a step error of 100 mV to
within 1 LSB in 30 lines with a clamp duration of 20 pixel
periods on a 85 Hz XGA signal.
To activate the auto-offset mode, set Register 0x1B, Bit 5 to 1.
Next, the target code registers (Register 0x0B through
Register 0x10) must be programmed. The values programmed
into the target code registers should be the output code desired
from the AD9983A ADCs, which are generated during the back
porch reference time. For example, for RGB signals, all three
registers are normally programmed to Code 2, while for YPbPr
signals the green (Y) channel is normally programmed to Code
2 and the blue and red channels (Pb and Pr) are normally set to
128. The target code registers have nine bits per channel and are
in twos complement format. This allows any value between –256
and +255 to be programmed. Although any value in this range
can be programmed, the AD9983A offset range may not be able
to reach every value. Intended target code values range from
(but are not limited to) –40 to –1 and 1 to 40 when ground
clamping and 88 to 168 when midscale clamping. Note that a
target code of 0 is not valid.
YPbPr Clamping
YPbPr graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) of color
difference signals is at the midpoint of the video signal rather
than at the bottom. The three inputs are composed of
luminance (Y) and color difference (Pb and Pr) signals. For
color difference signals, it is necessary to clamp to the midscale
range of the ADC range (512) rather than to the bottom of the
ADC range (0), while the Y channel is clamped to ground.
Rev. PrA | Page 12 of 44
Preliminary Technical Data
AD9983A
Negative target codes are included in order to duplicate a fea-
ture that is present with manual offset adjustment. The benefit
that is being mimicked is the ability to easily adjust brightness
on a display. By setting the target code to a value that does not
correspond to the ideal ADC range, the end result is an image
that is either brighter or darker. A target code higher than ideal
results in a brighter image. A target code lower than ideal
results in a darker image.
Automatic Gain Matching
The AD9983A includes circuitry to match the gains between
the three channels to within 1% of each other. Matching the
gains of each channel is necessary in order to achieve good
color balance on a display. On products without this feature,
gain matching is achieved by writing software that evaluates the
output of each channel, calculates gain mismatches, then writes
values to the gain registers of each channel to compensate. With
the auto gain matching function, this software routine is no
longer needed. To activate auto gain matching, set Register 0x3C,
Bit 2 to Bit 1.
The ability to program a target code gives a large degree of
freedom and flexibility. In most cases all channels are set to
either 1 or 128, but the flexibility to select other values allows
for the possibility of inserting intentional skews between
channels. It also allows the ADC range to be skewed so that
voltages outside of the normal range can be digitized. For
example, setting the target code to 40 allows the sync tip, which
is normally below black level, to be digitized and evaluated.
Auto gain matching has similar timing requirements to auto
offset. It requires 16 data clock cycles to perform its function,
starting immediately after the end of the clamp pulse. Unlike
auto offset it does not require that these 16 clock cycles occur
during the back porch reference time, although that is what is
recommended. During auto gain matching operation, the data
outputs of the AD9983A are frozen (held at the value they had
just prior to operation). The auto gain matching function can be
programmed to run continuously or on a one-time basis (see
Auto Gain Matching Hold section, Register 0x2C, Bit 3). In
continuous mode, the update frequency can be programmed
(Register 0x1B, Bit 4 and Bit 3). Continuous operation with
updates every 64 Hsyncs is recommended.
The internal logic for the auto-offset circuit requires 16 data
clock cycles to perform its function. This operation is executed
immediately after the clamping pulse. Therefore, it is important
to end the clamping pulse signal at least 16 data clock cycles
before active video. This is true whether using the AD9983A
internal clamp circuit or an external clamp signal. The auto-
offset function can be programmed to run continuously or on a
one-time basis (see auto-offset hold, Register 0x2C, Bit 4). In
continuous mode, the update frequency can be programmed
(Register 0x1B, Bits[4:3]). Continuous operation with updates
every 64 Hsyncs is recommended.
SYNC-ON-GREEN
The sync-on-green inputs (SOGIN0, SOGIN1) operate in two
steps. First, they set a baseline clamp level off of the incoming
video signal with a negative peak detector. Second, they set the
sync trigger level to a programmable (Register 0x1D, Bits[7:3])
level (typically 128 mV) above the negative peak. The sync-on-
green inputs must be ac-coupled to the green analog input
through their own capacitors. The value of the capacitors must
be 1 nF 20%. If sync-on-green is not used, this connection is
not required. The sync-on-green signal always has negative
polarity.
A guideline for basic auto-offset operation is shown in Table 6
and Table 7.
Table 6. RGB Auto-Offset Register Settings
Register
Value Comments
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x18, Bits[3:1]
0x02
0x00
0x02
0x00
0x02
0x00
000
Sets red target to 4
Must be written
Sets green target to 4
Must be written
Sets blue target to 4
Must be written
47nF
R
B
AIN
47nF
47nF
1nF
AIN
Sets red, green, and blue
channels to ground clamp
G
AIN
0x1B, Bits[5:3]
110
Selects update rate and
enables auto-offset.
SOGIN
Figure 5. Typical Input Configuration
Table 7. PbPr Auto-Offset Register Settings
REFERENCE BYPASSING
Register
Value Comments
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x18 Bits[3:1]
0x40
0x00
0x02
0x00
0x40
0x00
101
Sets Pr (red) target to 128
Must be written
Sets Y (green) target to 4
Must be written
Sets Pb (blue) target to 128
Must be written
REFLO and REFHI are connected to each other by a 10 μF
capacitor. These references are used by the input ADC circuitry.
REFHI
10µF
REFLO
Sets Pb, Pr to midscale clamp
and Y to ground clamp
0x1B, Bits[5:3]
110
Selects update rate and
enables auto-offset
Figure 6. Input Amplifier Reference Capacitors
Rev. PrA | Page 13 of 44
AD9983A
Preliminary Technical Data
Four programmable registers are provided to optimize the
performance of the PLL. These registers are the 12-Bit Divisor
Register, the 2-Bit VCO Range Register, the 3-Bit Charge Pump
Current Register, and the 5-Bit Phase Adjust Register.
CLOCK GENERATION
A PLL is used to generate the pixel clock. The Hsync input pro-
vides a reference frequency to the PLL. A voltage controlled
oscillator (VCO) generates a much higher pixel clock frequency.
The pixel clock is divided by the PLL divide value (Register 0x01
and Register 0x02) and phase-compared with the Hsync input.
Any error is used to shift the VCO frequency and maintain lock
between the two signals.
The 12-Bit Divisor Register.
The input Hsync frequencies can accommodate any Hsync as
long as the product of the Hsync and the PLL divisor falls
within the operating range of the VCO. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock
frequencies in the range of 10 MHz to 170 MHz. The divisor
register controls the exact multiplication factor. This register
may be set to any value between 2 and 4095 as long as the
output frequency is within range.
The stability of this clock is a very important element in
providing the clearest and most stable image. During each pixel
time, there is a period during which the signal slews from the
old pixel amplitude and settles at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (see Figure 7). The ratio of the slewing time
to the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate.
Clearly, if the dynamic characteristics of the system remain
fixed, then the slewing and settling time is likewise fixed. This
time must be subtracted from the total pixel period, leaving the
stable period. At higher pixel frequencies, the total cycle time is
shorter and the stable pixel time also becomes shorter.
The 2-Bit VCO Range Register
To improve the noise performance of the AD9983A, the VCO
operating frequency range is divided into four overlapping
regions. The VCO range register sets this operating range. The
frequency ranges for the four regions are shown in Table 8.
Table 8. VCO Frequency Ranges
Pixel Clock
PV1 PV0 Range (MHz)
KVCO
Gain (MHz/V)
PIXEL CLOCK
INVALID SAMPLE TIMES
0
0
1
1
0
1
0
1
10 to 21
21 to 42
42 to 84
84 to 170
150
150
150
150
The 3-Bit Charge Pump Current Register.
This register varies the current that drives the low pass loop
filter. The possible current values are listed in Table 9.
Table 9. Charge Pump Current/Control Bits
Ip2
Ip1
Ip0
Current (μA)
0
0
0
50
Figure 7. Pixel Sampling Times
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
100
150
250
350
500
750
1500
Any jitter in the clock reduces the precision with which the
sampling time can be determined and must also be subtracted
from the stable pixel time. Considerable care has been taken in
the design of the AD9983A clock generation circuit to
minimize jitter. The clock jitter of the AD9983A is low in all
operating modes, making the reduction in the valid sampling
time due to jitter negligible.
The 5-Bit Phase Adjust Register
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting. The
loop filter design is shown in Figure 8. Recommended settings
of the VCO range and charge pump current for VESA standard
display modes are listed in Table 10.
The phase of the generated sampling clock can be shifted to
locate an optimum sampling point within a clock cycle. The
phase adjust register provides 32 phase-shift steps of 11.25°
each. The Hsync signal with an identical phase shift is available
through the HSOUT pin. Phase adjust is still available if an
external pixel clock is used. The COAST pin or the internal
coast is used to allow the PLL to continue to run at the same
frequency in the absence of the incoming Hsync signal or
during disturbances in Hsync (such as from equalization
pulses). This can be used during the vertical sync period or at
any other time that the Hsync signal is unavailable.
PV
D
C
C
Z
P
8.2nF
82nF
R
Z
1.5kΩ
FILT
Figure 8. PLL Loop Filter Detail
Rev. PrA | Page 14 of 44
Preliminary Technical Data
AD9983A
The polarity of the coast signal may be set through the coast
polarity register (Register 0x18, Bits[6:5]). Also, the polarity of
the Hsync signal can be set through the Hsync polarity register
(Register 0x12, Bits[5:4]). For both Hsync and coast, a value of 1
is active high. The internal coast function is driven off the
Vsync signal, which is typically a time when Hsync signals may
be disrupted with extra equalization pulses.
Table 10. Recommended VCO Range and Charge Pump and Current Settings for Standard Display Formats
Refresh Rate
(Hz)
Horizontal
VCO
Range
VCO Gear
Current (R0x36[0])
Standard Resolution
Frequency (kHz) Pixel Rate (MHz) PLL Divider
VGA
640 × 480
60
72
75
85
56
60
72
75
85
60
70
75
80
85
31.500
37.700
37.500
43.300
35.100
37.900
48.100
46.900
53.700
48.400
56.500
60.000
64.000
68.300
64.000
80.000
91.100
75.000
15.750
31.470
15.625
31.250
45.000
33.750
33.750
67.500
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
157.500
162.000
13.510
27.000
13.500
27.000
74.250
74.250
74.250
148.500
800
832
840
832
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
11
11
11
00
00
00
00
10
10
10
11
101
100
100
100
100
101
101
101
110
100
101
101
101
110
110
110
110
110
101
101
101
101
101
101
101
101
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
SVGA
800 × 600
1024
1056
1040
1056
1048
1344
1328
1312
1336
1376
1688
1688
1728
2160
858
858
864
864
1650
2200
2200
2200
XGA
1024 × 768
SXGA
1280 × 1024 60
75
85
UXGA
TV
1600 × 1200 60
480i
480p
576i
576p
720p
1035i
1080i
1080p
30
60
30
60
60
30
60
60
Rev. PrA | Page 15 of 44
AD9983A
Preliminary Technical Data
AD9983A
HSYNC
SELECT
CHANNEL
SELECT
HSYNC0
HSYNC1
MUX
ACTIVITY
DETECT
POLARITY
DETECT
HSYNC FILTER
MUX
AND
REGENERATOR
FILTERED
HSYNC
REGENERATED
HSYNC
ACTIVITY
DETECT
POLARITY
DETECT
SYNC SLICER
SOGIN0
SOGIN1
MUX
MUX
ACTIVITY
DETECT
SET
MUX
SOGOUT
SYNC SLICER
POLARITY
ACTIVITY
DETECT
VSYNC0
VSYNC1
SYNC
PROCESSOR
AND
ACTIVITY
DETECT
POLARITY
DETECT
VSYNC FILTER
VSOUT/A0
O/E FIELD
HSYNC/VSYNC
COUNTER
REG 0x26, 0x27
ACTIVITY
DETECT
POLARITY
DETECT
SET
POLARITY
HSYNC
SET
HSOUT
COAST
POLARITY
MUX
PLL CLOCK
GENERATOR
EXTCK/COAST
SET
POLARITY
DATACK
Figure 9. Sync Processing Block Diagram
•
•
•
The Hsync regenerator is used to recreate a clean, although
not low jitter, Hsync signal that can be used for mode
detection and counting Hsyncs per Vsync.
SYNC PROCESSING
The inputs of the sync processing section of the AD9983A are
combinations of digital Hsyncs and Vsyncs, analog sync-on-
green, or sync-on-Y signals, and an optional external coast
signal. From these signals it generates a precise, jitter-free clock
from its PLL; an odd/even field signal; HSOUT and VSOUT
signals; a count of Hsyncs per Vsync; and a programmable
SOGOUT. The main sync processing blocks are the sync slicer,
sync separator, Hsync filter, Hsync regenerator, Vsync filter, and
coast generator.
The Vsync filter is used to eliminate spurious Vsyncs,
maintain a stable timing relationship between the Vsync and
Hsync output signals, and generate the odd/even field output.
The coast generator creates a robust coast signal that
allows the PLL to maintain its frequency in the absence of
Hsync pulses.
Sync Slicer
•
•
•
The sync slicer extracts the sync signal from the green
graphics or luminance video signal that is connected to the
SOGINx input and outputs a digital composite sync.
The purpose of the sync slicer is to extract the sync signal from
the green graphics or luminance video signal that is connected
to the SOG input. The sync signal is extracted in a two step
process. First, the SOG input is clamped to its negative peak,
(typically 0.3 V below the black level). Next, the signal goes to a
comparator with a variable trigger level (set by Register 0x1D,
Bits[7:3]), but nominally 0.128 V above the clamped level. The
sync slicer output is a digital composite sync signal containing
both Hsync and Vsync information (see Figure 10).
The sync separator’s task is to extract Vsync from the
composite sync signal, which can come from either the sync
slicer or the HSYNCx inputs.
The Hsync filter is used to eliminate any extraneous pulses
from the HSYNCx or SOGINx inputs, outputting a clean,
low jitter signal that is appropriate for mode detection and
clock generation.
Rev. PrA | Page 16 of 44
Preliminary Technical Data
AD9983A
NEGATIVE PULSE WIDTH = 40 SAMPLE CLOCKS
700mV MAXIMUM
+300mV
SOG INPUT
0mV
–300mV
SOGOUT OUTPUT
CONNECTED TO
HSYNCIN
COMPOSITE
SYNC
AT HSYNCIN
VSYNCOUT
FROM SYNC
SEPARATOR
Figure 10. Sync Slicer and Sync Separator Output
Sync Separator
degree of tolerance to extraneous and missing pulses on the
Hsync input, but is not appropriate for use by the PLL in
creating the pixel clock due to jitter.
As part of sync processing, the sync separator’s task is to extract
Vsync from the composite sync signal. It works on the idea that
the Vsync signal stays active for a much longer time than the
Hsync signal. By using a digital low-pass filter and a digital
comparator, it rejects pulses with small durations (such as
Hsyncs and equalization pulses) and only passes pulses with
large durations, such as Vsync (see Figure 10).
The Hsync regenerator runs automatically and requires no
setup to operate. The Hsync filter requires the setting up of a
filter window. The filter window sets a periodic window of time
around the regenerated Hsync leading edge where valid Hsyncs
are allowed to occur. The general idea is that extraneous pulses
on the sync input occur outside of this filter window and thus
are filtered out. To set the filter window timing, program a value
(x) into Register 0x23. The resulting filter window time is x
times 25 ns around the regenerated Hsync leading edge. Just as
for the sync separator threshold multiplier, allow a 20%
variance in the 25 ns multiplier to account for all operating
conditions (20 ns to 30 ns range).
The threshold of the digital comparator is programmable for
maximum flexibility. To program the threshold duration, write
a value (N) to Register 0x11. The resulting pulse width is N ×
200 ns. So, if N = 5, the digital comparator threshold is 1 μs.
Any pulse less than 1 μs is rejected, while any pulse greater than
1 μs passes through.
There are two factors to consider when using the sync separator.
First, the resulting clean Vsync output is delayed from the
original Vsync by a duration equal to the digital comparator
threshold (N × 200 ns). Second, there is some variability to the
200 ns multiplier value. The maximum variability over all
operating conditions is 20% (160 ns to 240 ns). Since normal
Vsync and Hsync pulse widths differ by a factor of
A second output from the Hsync filter is a status bit (Register 0x25,
Bit 1) that tells whether extraneous pulses were present on the
incoming sync signal or not. Often, extraneous pulses are
included for copy protection purposes, so this status bit can be
used to detect that.
The filtered Hsync (rather than the raw HSYNCx/SOGINx
signal) for pixel clock generation by the PLL is controlled by
Register 0x20, Bit 2. The regenerated Hsync (rather than the
raw Hsync/SOGIN signal) for the sync processing is controlled
by Register 0x20, Bit 1. Use of the filtered Hsync and
regenerated Hsync is recommended. See Figure 11 for an
illustration of a filtered Hsync.
approximately 500 or more, the 20% variability is not an issue.
Hsync Filter and Regenerator
The Hsync filter is used to eliminate any extraneous pulses from
the Hsync or SOGIN inputs, outputting a clean, low jitter signal
that is appropriate for mode detection and clock generation.
The Hsync regenerator is used to recreate a clean, although not
low jitter, Hsync signal that can be used for mode detection and
counting Hsyncs per Vsync. The Hsync regenerator has a high
Rev. PrA | Page 17 of 44
AD9983A
Preliminary Technical Data
HSYNCIN
FILTER
WINDOW
HSYNCOUT
VSYNC
EQUALIZATION
PULSES
EXPECTED
EDGE
FILTER
WINDOW
Figure 11. Sync Processing Filter
SYNC SEPARATOR THRESHOLD
Vsync Filter and Odd/Even Fields
The Vsync filter is used to eliminate spurious Vsyncs, maintain
a stable timing relationship between the Vsync and Hsync
output signals, and generate the odd/even field output.
FIELD 1
2
FIELD 0
FIELD 1
FIELD 0
QUADRANT
HSYNCIN
3
4
1
2
3
4
1
The filter works by examining the placement of Vsync with
respect to Hsync and if necessary shifting it in time slightly.
The goal is to keep the Vsync and Hsync leading edges from
switching at the same time, thus eliminating confusion as to
when the first line of a frame occurs. Register 0x14, Bit 2
enables the Vsync filter. Use of the Vsync filter is recommended
for all cases, including interlaced video, and is required when
using the Hsyncs per Vsync counter. Figure 12 and Figure 13
illustrate even/odd field determination in two situations.
VSYNCIN
VSYNCOUT
O/E FIELD
ODD FIELD
Figure 12. Vsync Filter—Odd Field
SYNC SEPARATOR THRESHOLD
FIELD 1
FIELD 0
FIELD 1
FIELD 0
QUADRANT
HSYNCIN
2
3
4
1
2
3
4
1
VSYNCIN
VSYNCOUT
O/E FIELD
EVEN FIELD
Figure 13. Vsync Filter—Even Field
Rev. PrA | Page 18 of 44
Preliminary Technical Data
AD9983A
In power-down mode, there are several circuits that continue to
operate as normal. The serial register and sync detect circuits
maintain power so that the AD9983A can be woken up from
its power-down state. The bandgap circuit maintains power
because it is needed for sync detection. The sync-on-green and
SOGOUT functions continue to operate because the SOGOUT
output is needed when sync detection is performed by a
secondary chip. All of these circuits require minimal power to
operate. Typical standby power on the AD9983A is about 50 mW.
POWER MANAGEMENT
To meet display requirements for low standby power, the
AD9983A includes a power-down mode. The power-down state
can be controlled manually (via Pin 17 or Register 0x1E, Bit 3),
or automatically by the chip. If automatic control is selected
(Register 0x1E, Bit 4), the AD9983A decision is based on the
status of the sync detect bits (Register 0x24, Bit 2, Bit 3, Bit 6,
and Bit 7). If either an Hsync or a sync-on-green input is
detected on any input, the chip powers up, otherwise it powers
down. For manual control, the AD9983A allows flexibility of
control through both a dedicated pin and a register bit. The
dedicated pin allows a hardware watchdog circuit to control
power-down, while the register bit allows power-down to be
controlled by software. With manual power-down control, the
polarity of the power-down pin must be set (Register 0x1E, Bit 2)
whether the pin is used or not. If unused, it is recommended to
set the polarity to active high and hardwire the pin to ground with
a 10 kΩ resistor.
There are two options that can be selected when in power-
down. These are controlled by Bit 0 and Bit 1 in Register 0x1E.
Bit 0 controls whether the SOGOUT pin is in high impedance
or not. In most cases, the user will not place SOGOUT in high
impedance during normal operation. The option to put
SOGOUT in high impedance is included mainly to allow for
factory testing modes. Bit 1 keeps the AD9983A powered up
while placing only the outputs in high impedance. This option
is useful when the data outputs from two chips are connected
on a PCB and the user wants to switch instantaneously between
the two.
Table 11. Power-Down Control and Mode Descriptions
Inputs
Auto Power-Down
Control1
Power-Down2
Sync Detect3
Powered On/Comments
Mode
Power-Up
Power-Down
1
1
X
X
1
0
Everything
Only the serial bus, sync activity detect,
SOG, bandgap reference
Power-Up
Power-Down
0
0
0
1
X
X
Everything
Only the serial bus, sync activity detect,
SOG, bandgap reference
1 Auto power-down control is set by Register 0x1E, Bit 4.
2 Power-down is controlled by OR’ing Pin 17 with Register 0x1E, Bit 3. The polarity of Pin 17 is set by Register 0x1E, Bit 2.
3 Sync detect is determined by OR’ing Register 0x24, Bit 2, Bit 3, Bit 6, and Bit 7.
TIMING DIAGRAMS
The timing diagrams in Figure 14 to Figure 17 show the operation of the AD9983A. The output data clock signal is created so that its
rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the
AD9983A, which must be flushed before valid data becomes available. This means six data sets are presented before valid data is available.
tPER
tDCYCLE
DATACK
tSKEW
DATA
HSOUT
Figure 14. Output Timing
Rev. PrA | Page 19 of 44
AD9983A
Preliminary Technical Data
DATAIN
P0
P1
P2
P5
P6
P9
P3
P4
P7
P8
P10
P11
HSYNCx
DATACK
8 CLOCK CYCLE DELAY
P0 P1 P2
DATAOUT
HSOUT
P3
2 CLOCK CYCLE DELAY
Figure 15. 4:4:4 Timing Mode
DATAIN
P0
P1
P2
P5
P6
P9
P3
P4
P7
P8
P10
P11
HSYNCx
DATACK
8 CLOCK CYCLE DELAY
YOUT
Y0
Y1
Y2
Y3
CB/CROUT
CB0
CR0
CB2
CR2
2 CLOCK CYCLE DELAY
HSOUT
NOTES
1. PIXEL AFTER HSOUT CORRESONDS TO BLUE INPUT.
2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT.
Figure 16. 4:2:2 Timing Mode
DATAIN
P0
P1
P2
P5
P6
P9
P3
P4
P7
P8
P10
P11
HSYNCx
DATACK
8 CLOCK CYCLE DELAY
F0 R0 F1 R1 F2 R2 F3 R3
2 CLOCK CYCLE DELAY
HSOUT
DDR NOTES
1. OUTPUT DATACK MAY BE DELAYED 1/4 CLOCK PERIOD IN THE REGISTERS.
2. SEE PROJECT DOCUMENT FOR VALUES OF F (FALLING EDGE) AND R (RISING EDGE).
3. FOR DDR 4:2:2 MODE: TIMING IS IDENTICAL, VALUES OF F AND R CHANGE.
GENERAL NOTES
1. DATA DELAY MAY VARY ± ONE CLOCK CYCLE, DEPENDING ON PHASE SETTING.
2. ADCs SAMPLE INPUT ON FALLING EDGE OF DATACK.
3. HSYNC SHOWN IS ACTIVE HIGH (EDGE SHOWN IS LEADING EDGE).
Figure 17. Double Data Rate (DDR) Timing Mode
HSYNC TIMING
Three things happen to Hsync in the AD9983A. First, the
polarity of Hsync input is determined and thus has a known
output polarity. The known output polarity can be programmed
either active high or active low (Register 0x12, Bit 3). Second,
HSOUT is aligned with DATACK and data outputs. Third, the
duration of HSOUT (in pixel clocks) is set via Register 0x13.
HSOUT is the sync signal that should be used to drive the rest
of the display system.
The Hsync is processed in the AD9983A to eliminate ambiguity
in the timing of the leading edge with respect to the phase-
delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted with
respect to Hsync through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use Hsync to align memory and display write cycles, so
it is important to have a stable timing relationship between
Hsync output (HSOUT) and the data clock (DATACK).
Rev. PrA | Page 20 of 44
Preliminary Technical Data
AD9983A
COAST TIMING
OUTPUT FORMATTER
In most computer systems, the Hsync signal is provided
continuously on a dedicated wire. In these systems, the coast
input and function are unnecessary and should not be used.
The output formatter is capable of generating several output
formats to be presented to the 24 data output pins. The output
formats and the pin assignments for each format are listed in
Table 12. Also, there are several clock options for the output
clock. The user may select the pixel clock, a 90° phase-shifted
pixel clock, a 2× pixel clock, or a fixed frequency 40 MHz clock
for test purposes. The output clock may also be inverted.
In some systems, however, Hsync is disturbed during the
vertical sync period (Vsync). In some cases, Hsync pulses
disappear. In other systems, such as those that employ
composite sync (Csync) signals or embedded sync-on-green,
Hsync may include equalization pulses or other distortions
during Vsync. To avoid upsetting the clock generator during
Vsync, it is important to ignore these distortions. If the pixel
clock PLL sees extraneous pulses, it attempts to lock to this new
frequency, and will have changed frequency by the end of the
Vsync period. It then takes a few lines of correct Hsync timing
to recover at the beginning of a new frame, resulting in a tearing
of the image at the top of the display.
Data output is available as 24-pin RGB or YCbCr, or if either
4:2:2 or 4:4:4 DDR is selected, a secondary channel is available.
This secondary channel is always 4:2:2 DDR and allows the
flexibility of having a second channel with the same video data
that can be utilized by either another display or even a storage
device. Depending on the choice of output modes, the primary
output can be 24 pins, 16 pins, or as little as 12 pins.
Mode Descriptions
The COAST input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and holds the
clock at its current frequency. The PLL can free run for several
lines without significant frequency drift. Coast can be generated
internally by the AD9983A (see Register 0x18) or can be
provided externally by the graphics controller.
4:4:4
All channels come out with their 8 data bits at the same time.
Data is aligned to the negative edge of the clock for easy capture.
This is the normal 24-bit output mode for RGB or 4:4:4 YCbCr.
4:2:2
Red and green channels contain 4:2:2 formatted data (16 pins)
with Y data on the green channel and Cb, Cr data on the red
channel. Data is aligned to the negative edge of the clock. The
blue channel contains the secondary channel with Cb, Y, Cr, Y
formatted 4:2:2 DDR data. The data edges are aligned to both
edges of the pixel clock, so use of the 90° clock may be necessary to
capture the DDR data.
When internal coast is selected (Register 0x18, Bit 7 = 0, and
Register 0x14, Bits[7:6] to select source), Vsync is used as a
basis for determining the position of COAST. The internal coast
signal is enabled a programmed number of Hsync periods
before the periodic Vsync signal (Precoast Register 0x16) and
dropped a programmed number of Hsync periods after Vsync
(Postcoast Register 0x17). It is recommended that the Vsync
filter be enabled when using the internal coast function to allow
the AD9983A to determine precisely the number of Hsyncs/Vsync
and their location. In many applications where disruptions
occur and coast is used, values of 2 for Precoast and 10d for
Postcoast are sufficient to avoid most extraneous pulses.
4:4:4 DDR
This mode puts out full 4:4:4 data on 12 bits of the red and
green channels, thus saving 12 pins. The first half (RGB[11:0])
of the 24-bit data is sent on the rising edge and the second half
(RGB[23:12]) is sent on the falling edge. DDR 4:2:2 data is sent
on the blue channel, as in 4:2:2 mode.
RGB [23:0] = R [7:0] + G [7:0] + B [7:0], so
RGB [23:12] = R [7:0] + G [7:4] and
RGB [11:0] = G [3:0] + B [7:0]
Table 12. Output Formats
Port
Red
Green
Blue
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
Green/Y
Y
2
1
0
7
6
5
4
3
2
1
0
4:4:4
4:2:21
Red/Cr
Blue/Cb
Cb, Cr
DDR 4:2:2 ↑ Cb, Cr ↓ Y, Y
DDR 4:2:2 ↑ Cb, Cr
DDR 4:2:2 ↓ Y, Y
DDR ↑2 G [3:0]
DDR ↓2 R [7:0]
DDR ↑ B [7:4]
DDR ↑ B [3:0]
DDR ↓ G [7:4]
4:4:4 DDR
N/A
N/A
1 For 4:2:2 Cb sent before Cr.
2 Arrows in table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.
Rev. PrA | Page 21 of 44
AD9983A
Preliminary Technical Data
2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface control interface is provided. Up to two
AD9983A devices may be connected to the 2-wire serial
interface, with each device having a unique address.
Table 13. Serial Port Addresses
Bit 7
Bit 6
A5
0
Bit 5
A4
0
Bit 4
A3
1
Bit 3
A2
1
Bit 2
A1
0
Bit 1
A0
0
A6 (MSB)
1
1
The 2-wire serial interface comprises a clock (SCL) and a bi-
directional data (SDA) pin. The analog flat panel interface acts
as a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled high by external pull-up resistors.
0
0
1
1
0
1
DATA TRANSFER VIA SERIAL INTERFACE
For each byte of data read or written, the MSB is the first bit in
the sequence.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA must
change only when SCL is low. If SDA changes state while SCL is
high, the serial interface interprets that action as a start or stop
sequence.
If the AD9983A does not acknowledge the master device during
a write sequence, the SDA remains high so the master can gen-
erate a stop signal. If the master device does not acknowledge
the AD9983A during a read sequence, the AD9983A interprets
this as end of data. The SDA remains high so the master can
generate a stop signal.
The following are the five components to serial bus operation:
•
•
•
•
•
Start signal
Writing data to specific control registers of the AD9983A
requires writing to the 8-bit address of the control register of
interest after the slave address has been established. This control
register address is the base address for subsequent write
operations. The base address auto-increments by one for each
byte of data written after the data byte intended for the base
address. If more bytes are transferred than there are available
addresses, the address does not increment and remains at its
maximum value of 0x2E. Any base address higher than 0x2E
will not produce an acknowledge signal. Data are read from the
control registers of the AD9983A in a similar manner. Reading
requires two data transfer operations:
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
When the serial interface is inactive (SCL and SDA are high),
communications are initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slaved devices that a data transfer sequence
is coming.
The first 8 bits of data transferred after a start signal comprise a
7-bit slave address (the first 7 bits) and a single R/ bit (the
eighth bit). The R/ bit indicates the direction of data transfer,
read from 1 or write to 0 on the slave device. If the transmitted
slave address matches the address of the device, the AD9983A
acknowledges the match by bringing SDA low on the ninth SCL
pulse. If the addresses do not match, the AD9983A does not
acknowledge it.
W
The base address must be written with the R/ bit of the slave
W
address byte low to set up a sequential read operation. Reading
W
W
(the R/ bit of the slave address byte high) begins at the
previously established base address. The address of the read
register auto-increments after each byte is transferred.
To terminate a read/write sequence to the AD9983A, a stop
signal must be sent. A stop signal comprises a low-to-high
transition of SDA while SCL is high.
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first genera-
ting a stop signal to terminate the current communication. This
is used to change the mode of communication (read, write)
between the slave and master without releasing the serial
interface lines.
SDA
tBUFF
tDSU
tDHO
tSTOSU
tSTASU
tSTAH
tDAL
SCL
tDAH
Figure 18. Serial Port Read/Write Timing
Rev. PrA | Page 22 of 44
Preliminary Technical Data
AD9983A
Serial Interface Read/Write Examples
Read from One Control Register
Write to One Control Register
1. Start signal
1. Start signal
W
2. Slave address byte (R/ bit = low)
W
2. Slave address byte (R/ bit = low)
3. Base address byte
4. Start signal
3. Base address byte
4. Data byte to base address
5. Stop signal
W
5. Slave address byte (R/ bit = high)
6. Data byte from base address
7. Stop signal
Write to Four Consecutive Control Registers
1. Start signal
Read from Four Consecutive Control Registers
W
2. Slave address byte (R/ bit = low)
1. Start signal
3. Base address byte
W
2. Slave address byte (R/ bit = low)
4. Data byte to base address
5. Data byte to (base address + 1)
6. Data byte to (base address + 2)
7. Data byte to (base address + 3)
8. Stop signal
3. Base address byte
4. Start signal
W
5. Slave address byte (R/ bit = high)
6. Data byte from base address
7. Data byte from (base address + 1)
8. Data byte from (base address + 2)
9. Data byte from (base address + 3)
10. Stop signal
SDA
SCL
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ACK
BIT 7
Figure 19. Serial Interface—Typical Byte Transfer
Rev. PrA | Page 23 of 44
AD9983A
Preliminary Technical Data
2-WIRE SERIAL REGISTER MAP
The AD9983A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to
write and read the control registers through the 2-wire serial interface port.
Table 14. Control Register Map
Hex
Address
Read/Write,
Read Only
Default
Value
Bits
7:0
Register Name
Description
0x00
0x01
RO
Chip Revision
An 8-bit register that represents the silicon revision level.
R/W
7:0
0110 1001 PLL Div MSB
This register is for Bits [11:4] of the PLL divider. Larger values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. (This will give the PLL more time to
lock).1
0x02
0x03
R/W
R/W
7:4
1101 ****
PLL Div LSB
VCO/CPMP
LSBs of the PLL Divider Word. Links to the PLL Div MSB to make a
12-bit register.1
7:6
5:3
01** ****
**00 1***
VCO Range. Selects VCO frequency range. (See PLL section).
Charge Pump Current. Varies the current that drives the low-pass
filter. (See PLL section).
2
**** *0**
External Clock Enable.
0x04
0x05
R/W
R/W
7:3
1000 0***
Phase Adjust
Red Gain MSB
ADC Clock Phase Adjustment. Larger values mean more delay.
(1 LSB = T/32).
6:0
*100 0000
7-Bit Red Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.2
0x06
0x07
R/W
R/W
7:0
6:0
0000 0000
*100 0000
Must be written to 0x00 following a write of Reg. 0x05 for proper
operation.
Green Gain MSB
Blue Gain MSB
7-Bit Green Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.2
0x08
0x09
R/W
R/W
7:0
6:0
0000 0000
*100 0000
Must be written to 0x00 following a write of Reg. 0x07 for proper
operation.
7-Bit Blue Channel Gain Control. Controls the ADC input range
(contrast) of each respective channel. Bigger values give less
contrast.2
0x0A
0x0B
R/W
R/W
7:0
7:0
0000 0000
Must be written to 0x00 following a write of Reg. 0x09 for proper
operation.
0100 0000 Red Offset MSB
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.1
0x0C
0x0D
R/W
R/W
7
0*** ****
Red Offset LSB
Linked with Reg. 0x0B to form the 9-bit red offset that controls the
dc offset (brightness) of the red channel in auto-offset mode.
7:0
0100 0000 Green Offset MSB
8-Bit MSB of the Green Channel Offset Control. Controls the dc
offset (brightness) of each respective channel. Bigger values
decrease brightness.1
0x0E
0x0F
R/W
R/W
7
0*** ****
Green Offset LSB
Linked with Reg. 0x0D to form the 9-bit green offset that controls
the dc offset (brightness) of the green channel in auto-offset mode.
7:0
0100 0000 Blue Offset MSB
8-Bit MSB of the Red Channel Offset Control. Controls the dc offset
(brightness) of each respective channel. Bigger values decrease
brightness.1
0x10
0x11
R/W
R/W
7
0*** ****
Blue Offset LSB
Linked with Reg. 0x0F to form the 9-bit blue offset that controls the
dc offset (brightness) of the blue channel in auto-offset mode.
7:0
0010 0000 Sync Separator
Threshold
This register sets the threshold of the sync separator’s digital
comparator.
Rev. PrA | Page 24 of 44
Preliminary Technical Data
AD9983A
Hex
Address
Read/Write,
Read Only
Default
Value
Bits
Register Name
Description
0x12
R/W
7
0*** ****
*0** ****
Hsync Control
Active Hsync Override.
0 = The chip determines the active Hsync source
1 = The active Hsync source is set by Reg. 0x12, Bit 6
Selects the source of the Hsync for PLL and sync processing. This bit is
used only if Reg. 0x12, Bit 7 is set to 1 or if both syncs are active.
0 = Hsync is from HSYNCx input pin
6
5
1 = Hsync is from SOGINx
Hsync Input Polarity Override.
**0* ****
0 = The chip selects the Hsync input polarity
1 = The polarity of the input Hsync is controlled by Reg. 0x12, Bit 4
This applies to both HSYNC0 and HSYNC1.
4
3
***1 ****
**** 1***
Hsync Input Polarity. This bit is used only if Reg. 0x12, Bit 5 is set to 1.
0 = Active low input Hsync
1 = Active high input Hsync
Sets the polarity of the Hsync output signal.
0 = Active low Hsync output
1 = Active high Hsync output
0x13
0x14
R/W
R/W
7:0
7
0010 0000 Hsync Duration
Sets the number of pixel clocks that HSOUT is active.
0*** ****
Vsync Control
Active Vsync Override.
0 = The chip determines the active Vsync source
1 = The active Vsync source is set by Reg. 0x14, Bit 6
6
5
*0** ****
Selects the source of Vsync for the sync processing. This bit is used
only if Reg. 0x14, Bit 7 is set to 1.
0 = Vsync is from the Vsync input pin
1 = Vsync is from the sync separator
Vsync Input Polarity Override. This applies to both VSYNC0 and
VSYNC1.
**0* ****
0 = The chip selects the input Vsync polarity
1 = The polarity of the input Vsync is set by Reg. 0x14, Bit 4
4
3
2
***1 ****
**** 1***
**** *0**
Vsync Input Polarity. This bit is used only if Reg. 0x14, Bit 5 is set to 1.
0 = Active low input Vsync
1 = Active high input Vsync
Sets the polarity of the output Vsync signal.
0 = Active low output Vsync
1 = Active high output Vsync
Vsync Filter Enable. This needs to be enabled when using the
Hsync to Vsync counter.
0 = The Vsync filter is disabled
1 = The Vsync filter is enabled
1
**** **0*
Enables the Vsync duration block. This is designed to be used with
the Vsync filter.
0 = Vsync output duration is unchanged
1 = Vsync output duration is set by Reg. 0x15
0x15
R/W
7:0
0000 1010 Vsync Duration
Sets the number of Hsyncs that Vsync out is active. This is only
used if Reg. 0x14, Bit 1 is set to 1.
0x16
0x17
0x18
R/W
R/W
R/W
7:0
7:0
7
0000 0000 Precoast
0000 0000 Postcoast
The number of Hsync periods to coast prior to Vsync.
The number of Hsync periods to coast after Vsync.
0*** ****
*0** ****
**1* ****
Coast and Clamp
Control
Coast Source. Selects the source of the coast signal.
0 = Using internal coast generated from Vsync
1 = Using external coast signal from external COAST pin
Coast Polarity Override.
0 = The chip selects the external coast polarity
1 = The polarity of the external coast signal is set by Reg. 0x18, Bit 5
6
5
Coast Input Polarity. This bit is used only if Reg. 0x18, Bit 6 is set to 1.
0 = Active low external coast
1 = Active high external coast
Rev. PrA | Page 25 of 44
AD9983A
Preliminary Technical Data
Hex
Address
Read/Write,
Read Only
Default
Value
Bits
Register Name
Description
4
***0 ****
**** 0***
**** *0**
**** **0*
**** ***0
Clamp Source Select.
0 = Use the internal clamp generated from Hsync
1 = Use the external clamp signal
Red Clamp Select.
0 = Clamp the red channel to ground
1 = Clamp the red channel to midscale
Green Clamp Select.
0 = Clamp the green channel to ground
1 = Clamp the green channel to midscale
Blue Clamp Select.
0 = Clamp the blue channel to ground
1 = Clamp the blue channel to midscale
3
2
1
0
Must be set to 0 for proper operation.
0x19
R/W
7:0
0000 1000 Clamp Placement
Places the clamp signal an integer number of clock periods after
the trailing edge of the Hsync signal.
0x1A
0x1B
R/W
R/W
7:0
7
0010 0000 Clamp Duration
Number of clock periods that the clamp signal is actively clamping.
0*** ****
*1** ****
Clamp and Offset
External Clamp Polarity Override.
0 = The chip selects the clamp polarity
1 = The polarity of the clamp signal is set by Reg. 0x1B, Bit 6
External Clamp Input Polarity. This bit is used only if Reg. 0x1B, Bit 7
is set to 1.
6
0 = Active low external clamp
1 = Active high external clamp
5
**0* ****
***1 1***
Auto-Offset Enable.
0 = Auto-offset is disabled
1 = Auto-offset is enabled (offsets become the desired clamp code)
Auto-Offset Update Frequency. This selects how often the auto-
offset circuit operates.
4:3
00 = every 3 clamps
01 = 48 clamps
10 = every 192 clamps
11 = every 3 Vsyncs
2:0
7:0
7:3
**** *011
Must be written to default (011) for proper operation.
Must be set to 0xFF for proper operation.
0x1C
0x1D
R/W
R/W
1111 1111 TestReg0
0111 1***
SOG Control
SOG Slicer Threshold. Sets the voltage level of the SOG slicer’s
comparator.
2
**** *0**
SOGOUT Polarity. Sets the polarity of the signal on the SOGOUT pin.
0 = Active low SOGOUT
1 = Active high SOGOUT
1:0
**** **00
SOGOUT Select.
00 = Raw SOG from sync slicer (SOGIN0 or SOGIN1)
01 = Raw Hsync (HSYNC0 or HSYNC1)
10 = Regenerated sync from sync filter
11 = Filtered sync from sync filter
0x1E
R/W
7
6
*** ****
Power
Channel Select Override.
0 = The chip determines which input channels to use
1 = The input channel selection is determined by Reg. 0x1E, Bit 6
Channel Select. Input channel select: this is used only if Reg. 0x1E,
Bit 7 is set to 1, or if syncs are present on both channels.
0 = Channel 0 syncs and data are selected
*0** ****
1 = Channel 1 syncs and data are selected
5
4
**1* ****
***1 ****
Programmable Bandwidth.
0 = Low analog input bandwidth (7 MHz)
1 = High analog input bandwidth
Power-Down Control Select.
0 = Manual power-down control
1 = Auto power-down control
Rev. PrA | Page 26 of 44
Preliminary Technical Data
AD9983A
Hex
Address
Read/Write,
Read Only
Default
Value
Bits
Register Name
Description
3
**** 0***
**** *0**
**** **0*
Power-Down.
0 = Normal operation
1 = Power-down
Power-Down Pin Polarity.
0 = Active low
1 = Active high
2
1
Power-Down Fast Switching Control.
0 = Normal power-down operation
1 = The chip stays powered up and the outputs are put in high
impedance mode
0
**** ***0
100* ****
SOGOUT High Impedance Control.
0 = SOGOUT operates as normal during power-down
1 = SOGOUT is in high impedance during power-down
0x1F
R/W
7:5
Output Select 1
Output Mode.
100 = 4:4:4 output mode
101 = 4:2:2 output mode
110 = 4:4:4—DDR output mode
4
***1 ****
**** 0***
**** *10*
Primary Output Enable.
0 = Primary output is in high impedance state
1 = Primary output is enabled
Secondary Output Enable.
0 = Secondary output is in high impedance state
1 = Secondary output is enabled
3
2:1
Output Drive Strength.
00 = Low output drive strength
01 = Medium output drive strength
10 = High output drive strength
11 = High output drive strength
Applies to all outputs except VSOUT.
0
**** ***0
0*** ****
Output Clock Invert.
0 = Noninverted pixel clock
1 = Inverted pixel clock
Applies to all clocks output on DATACK.
0x20
R/W
7:6
Output Select 2
Output Clock Select.
00 = Pixel clock
01 = 90° phase shifted pixel clock
10 = 2× pixel clock
11 = 0.5× pixel clock
5
4
3
2
1
*0** ****
**0* ****
***0 ****
**** 1***
**** *0**
Output High Impedance.
0 = Normal outputs
1 = All outputs except SOGOUT in high impedance mode
SOG High Impedance.
0 = Normal SOG output
1 = SOGOUT pin is in high impedance mode
Field Output Polarity. Sets the polarity of the field output signal.
0 = Active low => even field, active high => odd field
1 = Active low => odd field, active high => even field
PLL Sync Filter Enable.
0 = PLL uses raw Hsync/SOG
1 = PLL uses filtered Hsync/SOG
Sync Processing Input Select. Selects the sync source for the sync
processor.
0 = Sync processing uses raw Hsync/SOGIN
1 = Sync processing uses regenerated Hsync from sync filter
0
Must be set to 1 for proper operation.
0x21
0x22
R/W
R/W
7:0
7:0
0010 0000
0011 0010
Must be set to default for proper operation.
Must be set to default for proper operation.
Rev. PrA | Page 27 of 44
AD9983A
Preliminary Technical Data
Hex
Address
Read/Write,
Read Only
Default
Value
Bits
Register Name
Description
0x23
0x24
R/W
7:0
0000 1010 Sync Filter
Window Width
Sync Detect
Sets the window of time around the regenerated Hsync leading
edge (in 25 ns steps) that sync pulses are allowed to pass through.
RO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
_*** ****
*_** ****
**_* ****
***_ ****
**** _***
**** *_**
**** **_*
**** ***_
_*** ****
*_** ****
**_* ****
***_ ****
**** _***
**** *_**
**** **_*
HSYNC0 Detection Bit.
0 = HSYNC0 is not active
1 = HSYNC0 is active
HSYNC1 Detection Bit.
0 = HSYNC1 is not active
1 = HSYNC1 is active
VSYNC0 Detection Bit.
0 = VSYNC0 is not active
1 = VSYNC0 is active
VSYNC1 Detection Bit.
0 = VSYNC1 is not active
1 = VSYNC1 is active
SOGIN0 Detection Bit
0 = SOGIN0 is not active
1 = SOGIN0 is active
SOGIN1 Detection Bit
0 = SOGIN1 is not active
1 = SOGIN1 is active
COAST Detection Bit.
0 = External COAST is not active
1 = External COAST is active
CLAMP Detection Bit.
0 = External CLAMP is not active
1 = External CLAMP is active
0x25
RO
Sync Polarity
Detect
HSYNC0 Polarity.
0 = HSYNC0 polarity is active low
1 = HSYNC0 polarity is active high
HSYNC1 Polarity.
0 = HSYNC1 polarity is active low
1 = HSYNC1 polarity is active high
VSYNC0 Polarity.
0 = VSYNC0 polarity is active low
1 = VSYNC0 polarity is active high
VSYNC1 Polarity.
0 = VSYNC1 polarity is active low
1 = VSYNC1 polarity is active high
COAST Polarity.
0 = External COAST polarity is active low
1 = External COAST polarity is active high
CLAMP Polarity.
0 = External CLAMP polarity is active low
1 = External CLAMP polarity is active high
Extraneous Pulses Detected.
0 = No extraneous pulses detected on HSYNCx
1 = Extraneous pulses detected on HSYNCx
Sync Filter Lock
0 = Sync filter unlocked
1 = Sync filter locked
0x26
0x27
RO
RO
7:0
7:4
Hsyncs Per Vsync
MSBs
MSBs of Hsyncs per Vsync count.
LSBs of Hsyncs per Vsync count.
Hsyncs Per Vsync
LSBs
0x28
0x29
0x2A
0x2B
R/W
R/W
RO
7:0
7:0
7:0
7:0
1011 1111 TestReg1
0000 0010 TestReg2
TestReg3
Must be written to Reg. 0xBF for proper operation.
Must be written to Reg. 0x02 for proper operation.
Read-only bits for future use.
RO
TestReg4
Read-only bits for future use.
Rev. PrA | Page 28 of 44
Preliminary Technical Data
AD9983A
Hex
Address
Read/Write,
Read Only
Default
Value
Bits
7:5
4
Register Name
Description
0x2C
R/W
000* ****
***0 ****
Offset Hold
Must be written to default for proper operation.
Auto-Offset Hold.
Disables the auto-offset and holds the feedback result.
0 = One time update
1 = Continuous update
3:0
7:0
7:0
2
**** 0000
Must be written to default for proper operation.
Must be written to Reg. 0xE8 for proper operation.
Must be written to Reg. 0xE0 for proper operation.
0x2D
0x2E
0x34
R/W
R/W
R/W
1111 0000 TestReg5
1111 0000 TestReg6
**** *0**
SOG Filter
SOG Filter Enable.
0 = Disable SOG filter
1 = Enable SOG filter
0x36
0x3C
R/W
R/W
0
**** ***0
VCO Gear
VCO Gear adds another range to the VCO—used for lower
frequencies only.
0 = Disable low VCO gear
1 = Enable low VCO gear
7:4
3
0000 ****
**** 0***
Auto Gain
Must be set to default for proper operation
Auto Gain Matching Hold
0 = Disables auto gain updates and holds the current auto offset
values.
1 = Allows auto gain to update continuously
2:0
**** *000
Auto Gain Matching Enable
000 = Auto gain is disabled
110= Auto gain is enabled
1 Functions with more than eight control bits, such as PLL divide ratio, gain, and offset, are only updated when the LSBs are written to (for example, Register 0x02 for
PLL divide ratio).
2 Gain registers (Register 0x05, Register 0x07, and Register 0x09) when written must each be followed with a write to their next register: Register 0x05 and Register 0x06,
Register 0x07, and Register 0x08, and Register 0x09 and Register 0x0A.
Rev. PrA | Page 29 of 44
AD9983A
Preliminary Technical Data
2-WIRE SERIAL CONTROL REGISTERS
CHIP IDENTIFICATION
Table 15. VCO Ranges
VCO Range
Results (Pixel Rates)
10 to 21
21 to 42
42 to 84
84 to 95
0x00—Bits[7:0] Chip Revision
00
01
10
11
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
0x01—Bits[7:0] PLL Divide Ratio MSBs
The 8 MSBs of the 12-bit PLL divide ratio PLLDIV.
0x03—Bits[5:3] Charge Pump Current
Three bits that establish the current driving the loop filter in the
clock generator. The current must be set to correspond with the
desired operating frequency. The power-up default value is
current = 001.
The PLL derives a pixel clock from the incoming Hsync signal.
The pixel clock frequency is then divided by an integer value,
such that the output is phase-locked to Hsync. This PLLDIV
value determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is typically 20% to
30% more than the number of active pixels in the display.
Table 16. Charge Pump Currents
Ip2
Ip1
Ip0
Results (Current)
The 12-bit value of the PLL divider supports divide ratios from
2 to 4095 as long as the output frequency is within range. The
higher the value loaded in this register, the higher the resulting
clock frequency with respect to a fixed Hsync frequency.
0
0
0
50
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
100
150
250
350
500
750
1500
VESA has established some standard timing specifications,
which will assist in determining the value for PLLDIV as a
function of horizontal and vertical display resolution and frame
rate (see Table 10). However, many computer systems do not
conform precisely to the recommendations and these numbers
should be used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV usually produces one or
more vertical noise bars on the display. The greater the error,
the greater the number of bars produced.
0x03—Bit[2] External Clock Enable
This bit determines the source of the pixel clock.
Table 17. External Clock Select Settings
EXTCK
Function
0
1
Internally generated clock
Externally provided clock signal
The power-up default value of PLLDIV is 1693. PLLDIVM =
0x69, PLLDIVL = 0xDX.
A Logic 0 enables the internal PLL that generates the pixel clock
from an externally provided Hsync.
The AD9983A updates the full divide ratio only when the LSBs
are written. Writing to this register by itself does not trigger
an update.
A Logic 1 enables the external EXTCK input pin. In this mode,
the PLL Divide Ratio (PLLDIV) is ignored. The clock phase
adjust (Phase) is still functional. The power-up default value is
EXTCK = 0.
0x02—Bits[7:4] PLL Divide Ratio LSBs
The 4 LSBs of the 12-bit PLL divide ratio PLLDIV.
PHASE ADJUST
0x04—Bits[7:3]
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDX.
CLOCK GENERATOR CONTROL
0x03—Bits[7:6] VCO Range Select
Phase adjustment for the DLL to generate the ADC clock. A 5-bit
value that adjusts the sampling phase in 32 steps across one
pixel time. Each step represents an 11.25° shift in sampling
phase. The power up default is 16.
Two bits that establish the operating range of the clock
generator. VCO range must be set to correspond to the desired
operating frequency (incoming pixel rate). The PLL gives the
best jitter performance at high frequencies. For this reason, in
order to output low pixel rates and still get good jitter performance,
the PLL actually operates at a higher frequency but then divides
down the clock rate afterwards. See Table 15 for the pixel rates
for each VCO range setting. The PLL output divisor is auto-
matically selected with the VCO range setting. The power-up
default value is 01.
Rev. PrA | Page 30 of 44
Preliminary Technical Data
AD9983A
0x0E—Bit[7] Green Channel Offset LSB
INPUT GAIN
The LSB of the green channel offset control combines with the
8 bits of MSBs in the previous register to make 9 bits of offset
control.
0x05—Bits[6:0] Red Channel Gain Adjust
The 7-Bit Red Channel Gain Control. The AD9983A can
accommodate input signals with a full-scale range of between
0.5 V and 1.0 V p-p. Setting the red gain to 127 corresponds to
an input range of 1.0 V. A red gain of 0 establishes an input
range of 0.5 V. Note that increasing red gain results in the
picture having less contrast (the input signal uses fewer of the
available converter codes). Values written to this register do not
update until the following register (Register 0x06) has been
written to 0x00. The power-up default is 100 0000.
0x0F—Bits[7:0] Blue Channel Offset
The 8-Bit Blue Channel Offset Control. See 0x0B—Bits[7:0]
Red Channel Offset. Update of this register occurs only when
Register 0x10 is also written.
0x10—Bit[7] Blue Channel Offset LSB
The LSB of the blue channel offset control combines with the
8 bits of MSB in the previous register to make 9 bits of offset
control.
0x07—Bits[6:0] Green Channel Gain Adjust
The 7-Bit Green Channel Gain Control. See red channel gain adjust
above. Register update requires writing 0x00 to Register 0x08.
HSYNC CONTROLS
0x11—Bits[7:0] Sync Separator Threshold
0x09—Bits[6:0] Blue Channel Gain Adjust
This register sets the threshold of the sync separator’s digital
comparator. The value written to this register is multiplied by
200 ns to get the threshold value. Therefore, if a value of 5 is
written, the digital comparator threshold is 1 μs and any pulses
less than 1 μs are rejected by the sync separator. There is some
variability to the 200 ns multiplier value. The maximum
variability over all operating conditions is 20% (160 ns to 240 ns).
Since normal Vsync and Hsync pulse widths differ by a factor of
about 500 or more, the 20% variability is not an issue. The
power-up default value is 32 DDR.
The 7-Bit Blue Channel Gain Control. See red channel gain adjust
above. Register update requires writing 0x00 to Register 0x0A.
INPUT OFFSET
0x0B—Bits[7:0] Red Channel Offset
The 8-Bit MSB of the Red Channel Offset Control. Along with
the LSB in the following register, there are 9 bits of dc offset
control in the red channel. The offset control shifts the analog
input, resulting in a change in brightness. Note that the function
of the offset register depends on whether auto-offset is enabled
(Register 0x1B, Bit 5).
0x12—Bit[7] Hsync Source Override
This is the active Hsync override. Setting this to 0 allows the
chip to determine the active Hsync source. Setting it to 1 uses
Bit 6 of Register 0x12 to determine the active Hsync source.
Power-up default value is 0.
If auto-offset is disabled, the lower 7 bits of the offset registers
(for the red channel Register 0x0B, Bits [5:0] plus Register 0x0C,
Bit 7) control the absolute offset added to the channel. The
offset control provides a 63 LSBs of adjustment range, with 1 LSB
of offset corresponding to 1 LSB of output code.
Table 18. Active Hsync Source Override
If auto-offset is enabled, the 9-bit offset (comprised of the 8 bits
of the MSB register and Bit 7 of the following register) determines
the clamp target code. The 9-bit offset consists of 1 sign bit
plus 8 bits. If the register is programmed to 130d, then the
output code is equal to 130d at the end of the clamp period.
Incrementing the offset register setting by 1 LSB adds 1 LSB of
offset, regardless of the auto-offset setting. Values written to this
register are not updated until the LSB register (Register 0x0C)
has also been written.
Override
Result
0
1
Hsync source determined by chip
Hsync source determined by user
Register 0x12, Bit 6
0x12—Bit[6] Hsync Source
This bit selects the source of the Hsync for PLL and sync
processing—only if Bit 7 of Register 0x12 is set to 1 or if both
syncs are active. Setting this bit to 0 specifies the Hsync from
the input pin. Setting it to 1 selects Hsync from SOG. Power-up
default is 0.
0x0C—Bit[7] Red Channel Offset LSB
The LSB of the red channel offset control combines with the 8 bits
of MSB in the previous register to make 9 bits of offset control.
Table 19. Active Hsync Select Settings
Select
Result
0x0D—Bits[7:0] Green Channel Offset
0
1
Hsync input
Hsync from SOG
The 8-Bit Green Channel Offset Control. See red channel offset
(0x0B). Update of this register occurs only when Register 0x0E
is also written.
Rev. PrA | Page 31 of 44
AD9983A
Preliminary Technical Data
0x12—Bit[5] Hsync Input Polarity Override
0x14—Bit[6] Vsync Source
This bit determines whether the chip selects the Hsync input
polarity or if it is specified. Setting this bit to 0 allows the chip
to automatically select the polarity of the input Hsync; setting it
to 1 indicates that Bit 4 of Register 0x12 specifies the polarity.
Power-up default is 0.
This bit selects the source of the Vsync for sync processing only
if Bit 7 of Register 0x14 is set to 1. Setting Bit 6 to 0 specifies the
Vsync from the input pin; setting it to 1 selects Vsync from the
sync separator. Power-up default is 0.
Table 24. Active Vsync Select Settings
Table 20. Hsync Input Polarity Override Settings
Select
Result
Override Bit
Result
0
1
Vsync input
Vsync from sync separator
0
1
Hsync polarity determined by chip
Hsync polarity determined by user
Register 0x12, Bit 4
0x14—Bit[5] Vsync Input Polarity Override
This bit sets whether the chip selects the Vsync input polarity or
if it is specified. Setting this bit to 0 allows the chip to
automatically select the polarity of the input Vsync. Setting this
bit to 1 indicates that Bit 4 of Register 0x14 specifies the
polarity. Power-up default is 0.
0x12—Bit[4] Hsync Input Polarity
If Bit 5 of Register 0x12 is 1, the value of this bit specifies the
polarity of the input Hsync. Setting this bit to 0 indicates an
active low Hsync; setting this bit to 1 indicates an active high
Hsync. Power-up default is 1.
Table 25. Vsync Input Polarity Override Settings
Table 21. Hsync Input Polarity Settings
Override Bit
Result
Hsync Polarity Bit
Result
0
1
Vsync polarity determined by chip
Vsync polarity determined by user
Register 0x14, Bit 4
0
1
Hsync input polarity is negative
Hsync input polarity is positive
0x12—Bit[3] Hsync Output Polarity
0x14—Bit[4] Vsync Input Polarity
This bit sets the polarity of the Hsync output. Setting this bit to
0 sets the Hsync output to active low. Setting this bit to 1 sets
the Hsync output to active high. Power-up default setting is 1.
If Bit 5 of Register 0x14 is 1, the value of this bit specifies the
polarity of the input Vsync. Setting this bit to 0 indicates an
active low Vsync; setting this bit to 1 indicates an active high
Vsync. Power-up default is 1.
Table 22. Hsync Output Polarity Settings
Table 26. Vsync Input Polarity Settings
Hsync Output
Polarity Bit
Result
Override Bit
Result
0
1
Hsync output polarity is negative
Hsync output polarity is positive
0
1
Vsync input polarity is negative
Vsync input polarity is positive
0x13—Bits[7:0] Hsync Duration
0x14—Bit[3] Vsync Output Polarity
An 8-bit register that sets the duration of the Hsync output
pulse. The leading edge of the Hsync output is triggered by the
internally-generated, phase-adjusted PLL feedback clock. The
AD9983A then counts a number of pixel clocks equal to the
value in this register. This triggers the trailing edge of the Hsync
output, which is also phase-adjusted.
This bit sets the polarity of the Vsync output. Setting this bit to
0 sets the Vsync output to active low. Setting this bit to 1 sets
the Vsync output to active high. Power-up default is 1.
Table 27. Vsync Output Polarity Settings
Vsync Output
Polarity Bit
Result
VSYNC CONTROLS
0x14—Bit[7] Vsync Source Override
0
1
Vsync output polarity is negative
Vsync output polarity is positive
This is the active Vsync override. Setting this to 0 allows the
chip to determine the active Vsync source, setting it to 1 uses
Bit 6 of Register 0x14 to determine the active Vsync source.
Power-up default value is 0.
0x14—Bit[2] Vsync Filter Enable
This bit enables the Vsync filter allowing precise placement of
the Vsync with respect to the Hsync and facilitating the correct
operation of the Hsyncs/Vsync count.
Table 23. Active Vsync Source Override
Table 28. Vsync Filter Enable
Override
Result
Vsync Filter Bit
Result
0
1
Vsync source determined by chip
Vsync source determined by user
Register 0x14, Bit 6
0
1
Vsync filter disabled
Vsync filter enabled
Rev. PrA | Page 32 of 44
Preliminary Technical Data
AD9983A
0x14—Bit[1] Vsync Duration Enable
0x18—Bit[5] Coast Input Polarity
This enables the Vsync duration block, which is designed to be
used with the Vsync filter. Setting the bit to 0 leaves the Vsync
output duration unchanged. Setting the bit to 1 sets the Vsync
output duration based on Register 0x15. Power-up duration is 0.
This register sets the input coast polarity when Bit 6 of
Register 0x18 = 1. The power-up default setting is 1.
Table 32. Coast Polarity Settings
Coast Polarity Bit
Result
Table 29. Vsync Duration Enable
Vsync Duration Bit Result
0
1
Coast polarity is negative
Coast polarity is positive
0
1
Vsync output duration is unchanged
Vsync output duration is set by Register
0x15
0x18—Bit[4] Clamp Source Select
This bit determines the source of clamp timing. A 0 enables the
clamp timing circuitry controlled by clamp placement and
clamp duration. The clamp position and duration is counted
from the leading edge of Hsync. A 1 enables the external clamp
input pin. The three channels are clamped when the clamp
signal is active. The polarity of clamp is determined by the
clamp polarity bit. The power-up default setting is 0.
0x15—Bits[7:0] Vsync Duration
This is used to set the output duration of the Vsync, and is
designed to be used with the Vsync filter. This is valid only if
Register 0x14, Bit 1 is set to 1. Power-up default is 10 DDR.
COAST AND CLAMP CONTROLS
0x16—Bits[7:0] Precoast
Table 33. Clamp Source Selection Settings
This register allows the internally generated coast signal to be
applied prior to the Vsync signal. This is necessary in cases
where pre-equalization pulses are present. The step size for this
control is one Hsync period. For precoast to work correctly, it is
necessary for the Vsync filter (0x14, Bit 2) and sync processing
filter (Register 0x20, Bit 1) both to be either enabled or disabled.
The power-up default is 00.
Clamp Source
Result
0
1
Internally generated clamp
Externally provided clamp signal
0x18—Bit[3] Red Clamp Select
This bit determines whether the red channel is clamped to
ground or to midscale. The power-up default setting is 0.
Table 34. Red Clamp Select Settings
0x17—Bits[7:0] Postcoast
Clamp
Result
This register allows the internally generated Coast signal to be
applied following the Vsync signal. This is necessary in cases
where postequalization pulses are present. The step size for this
control is one Hsync period. For Postcoast to work correctly, it
is necessary for the Vsync filter (0x14, Bit 2) and sync
processing filter (0x20, Bit 1) both to be either enabled or
disabled. The power-up default is 00.
0
1
Clamp to ground
Clamp to midscale
0x18—Bit[2] Green Clamp Select
This bit determines whether the green channel is clamped to
ground or to midscale. The power-up default setting is 0.
Table 35. Green Clamp Select Settings
0x18—Bit[7] Coast Source
Clamp
Result
This bit is used to select the active Coast source. The choices are
the coast input pin or Vsync. If Vsync is selected, the additional
decision of using the Vsync input pin or the output from the
sync separator needs to be made (Register 0x14, Bits [7: 6]).
0
1
Clamp to ground
Clamp to midscale
0x18—Bit[1] Blue Clamp Select
This bit determines whether the blue channel is clamped to
ground or to midscale. The power-up default setting is 0.
Table 30. Coast Source Selection Settings
Select
Result
Table 36. Blue Clamp Select Settings
0
1
Vsync (internal coast)
COAST input pin
Clamp
Result
0
1
Clamp to ground
Clamp to midscale
0x18—Bit[6] Coast Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into the PLL.
The power-up default setting is 0.
Table 31. Coast Polarity Override Settings
Override Bit
Result
0
1
Coast polarity determined by chip
Coast polarity determined by user
Rev. PrA | Page 33 of 44
AD9983A
Preliminary Technical Data
Table 39. Auto-Offset Settings
0x19—Bits[7:0] Clamp Placement
Auto-Offset
Result
An 8-bit register that sets the position of the internally
generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a
clamp signal is generated internally, at a position established by
the clamp placement register (Register 0x19) and for a duration
set by the clamp duration register (Register 0x1A). Clamping is
started a clamp placement count(Register 0x19) of pixel periods
after the trailing edge of Hsync. The clamp placement may be
programmed to any value between 1 and 255. A value of 0 is not
supported.
0
1
Auto-offset is disabled
Auto-offset is enabled (manual offset mode)
0x1B—Bits[4:3] Auto-Offset Update Frequency
These bits control how often the auto-offset circuit is updated
(if enabled). Updating every 64 Hsyncs is recommended. The
power-up default setting is 11.
Table 40. Auto-Offset Update Mode
Clamp Update Result
The clamp should be placed during a time that the input signal
presents a stable black-level reference, usually the back porch
period between Hsync and the image. When EXTCLMP = 1,
this register is ignored. Power-up default setting is 8.
00
01
10
11
Update offset every clamp period
Update offset every 16 clamp periods
Update offset every 64 clamp periods
Update offset every Vsync periods
0x1A—Bits[7:0] Clamp Duration
0x1B—Bits[2:0]
An 8-bit register that sets the duration of the internally
generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a
clamp signal is generated internally at a position established by
the clamp placement register (and for a duration set by the
clamp duration register). Clamping begins a clamp placement
count (Register 0x19) of pixel periods after the trailing edge of
Hsync. The clamp duration may be programmed to any value
between 1 and 255. A value of 0 is not supported.
Must be written to 011 for proper operation.
SOG CONTROL
0x1D—Bits[7:3] SOG Slicer Threshold
This register allows the comparator threshold of the SOG slicer
to be adjusted. This register adjusts it in steps of 8 mV, with the
minimum setting equaling 8 mV and the maximum setting
equaling 256 mV. The power-up default setting is 15 DDR and
corresponds to a threshold value of 128 mV.
For the best results, the clamp duration should be set to include
the majority of the black reference signal time that follows the
Hsync signal trailing edge. Insufficient clamping time can
produce brightness changes at the top of the screen, and a slow
recovery from large changes in the average picture level (APL),
or bright-ness. When EXTCLMP = 1, this register is ignored.
Power-up default setting is 20 DDR.
0x1D—Bit[2] SOGOUT Polarity
This bit sets the polarity of the SOGOUT signal. The power-up
default setting is 0.
Table 41. SOGOUT Polarity Settings
SOGOUT
Result
0x1B—Bit[7] Clamp Polarity Override
0
1
Active low
Active high
This bit is used to override the internal circuitry that
determines the polarity of the clamp signal. The power-up
default setting is 0.
0x1D—Bits[1:0] SOGOUT Select
These register bits control what is output on the SOGOUT pin.
Options are the raw SOG from the slicer (this is the
unprocessed SOG signal produced from the sync slicer), the
raw Hsync, the regenerated sync from the sync filter, which can
generate missing syncs either due to coasting or drop-out, or
finally the filtered sync which excludes extraneous syncs not
occurring within the sync filter window. The power-up default
setting is 0.
Table 37. Clamp Polarity Override Settings
Override Bit
Result
0
1
Clamp polarity determined by chip
Clamp polarity determined by user
Register 0x1B, Bit 6
0x1B—Bit[6] Clamp Input Polarity
This bit indicates the polarity of the clamp signal only if Bit 7 of
Register 0x1B = 1. The power-up default setting is 1.
Table 42. SOGOUT Select
SOGOUT Select
Function
Table 38. Clamp Polarity Override Settings
00
01
10
11
Raw SOG from sync slicer (SOGIN0 or SOGIN1)
Raw Hsync (HSYNC0 or HSYNC1)
Regenerated Hsync from sync filter
Filtered Hsync from sync filter
Value
Result
0
1
Active low external clamp
Active high external clamp
0x1B—Bit[5] Auto-Offset Enable
This bit selects between auto-offset mode and manual offset
mode (auto-offset disabled) (See the section on auto-offset
operation). The power-up default setting is 0.
Rev. PrA | Page 34 of 44
Preliminary Technical Data
AD9983A
0x1E—Bit[3] Power-Down
INPUT AND POWER CONTROL
This bit is used to manually place the chip in power-down
mode. It is only used if manual power-down control is selected
(see Bit 4 above). Both the state of this register bit and the
power-down pin (Pin 17) are used to control manual power-
down. (See the Power Management section for more details on
power-down.)
0x1E—Bit[7] Channel Select Override
This bit provides an override to the automatic input channel
selection. Power-up default setting is 0.
Table 43. Channel Source Override
Override
Result
0
1
Channel input source determined by chip
Channel input source determined by user
Register 0x1E, Bit 6
Table 47. Power-Down Settings
Power-Down Select
Pin 17
Result
0
1
0
X
Normal operation
Power-down
0x1E—Bit[6] Channel Select
This bit selects the active input channel if Register 0x1E, Bit 7 = 1.
This selects between Channel 0 data and syncs or Channel 1
data and syncs. Power-up default setting is 0.
0x1E—Bit[2] Power-Down Pin Polarity
This bit defines the polarity of the power-down pin (Pin 17). It
is only used if manual power-down control is selected (see
0x1E—Bit[4] Power-Down Control Select).
Table 44. Channel Select
Channel Select
Result
0
1
Channel 0 data and syncs are selected
Channel 1 data and syncs are selected
Table 48. Power-Down Pin Polarity
Select
Result
0
1
Power-down pin is active low
Power-down pin is active high
0x1E—Bit[5] Programmable Bandwidth
This bit selects between a low or high input bandwidth. It is
useful in limiting noise for lower frequency inputs. The power-
up default setting is 1. Low analog input bandwidth is ~100 MHz;
high analog input bandwidth is ~200 MHz.
0x1E—Bit[1] Power-Down Fast Switching Control
This bit controls a special fast switching mode. With this bit the
AD9983A can stay active during power-down and only put the
outputs in high impedance. This option is useful when the data
outputs from two chips are connected on a PCB and the user
wants to switch instantaneously between the two.
Table 45. Input Bandwidth Select.
Input Bandwidth
Result
0
1
Low analog input bandwidth
High analog input bandwidth
Table 49. Power-Down Fast Switching Control
Fast Switching Control
0x1E—Bit[4] Power-Down Control Select
Result
0
1
Normal power-down operation
This bit determines whether power-down is controlled
The chip stays powered up and the
outputs are put in high impedance
mode
manually or automatically by the chip. If automatic control is
selected (Register 0x1E, Bit 4), the AD9983A decision is based
on the status of the sync detect bits (Register 0x24, Bit 2, Bit 3,
Bit 6, and Bit 7). If either an Hsync or a sync-on-green input is
detected on any input, the chip powers up or powers down. For
manual control, the AD9983A allows the flexibility of control
through both a dedicated pin and a register bit. The dedicated
pin allows a hardware watchdog circuit to control power-down,
while the register bit allows power-down to be controlled by
software. With manual power-down control, the polarity of the
power-down pin must be set (Register 0x1E, Bit 2) whether it is
used or not. If unused, it is recommended to set the polarity to
active high and hardwire the pin to ground with a 10 kΩ resistor.
0x1E—Bit[0] SOGOUT High Impedance Control
This bit controls whether the SOGOUT pin is in high
impedance or not, when in power-down mode. In most cases,
SOGOUT is not put in high impedance during normal oper-
ation. It is usually needed for sync detection by the graphics
controller. The option to put SOGOUT in high impedance is
included mainly to allow for factory testing modes.
Table 50. SOGOUT High Impedance Control
SOGOUT Control
Result
0
SOGOUT operates as normal during
power-down
SOGOUT is in high impedance
during power-down
Table 46. Auto Power-Down Select.
1
Power-Down Select
Result
0
Manual power-down control
(user determines power-down)
1
Auto power-down control
(chip determines power-down)
Rev. PrA | Page 35 of 44
AD9983A
Preliminary Technical Data
0x1F—Bit[0] Output Clock Invert
OUTPUT CONTROL
This bit allows inversion of the output clock. The power-up
default setting is 0.
0x1F—Bits[7:5] Output Mode
These bits choose between three options for the output mode.
In 4:4:4 mode, RGB is standard. In 4:2:2 mode, YCbCr is
standard, which allows a reduction in the number of output
pins from 24 to 16. In 4:4:4 DDR output mode, the data is in
RGB mode, but changes on every clock edge. The power-up
default setting is 100.
Table 55. Output Clock Invert
Select
Result
0
1
Noninverted pixel clock
Inverted pixel clock
0x20—Bits[7:6] Output Clock Select
Table 51. Output Mode
These bits allow selection of optional output clocks such as a
fixed 40 MHz clock, a 2× clock, a 90° phase-shifted clock, or the
normal pixel clock. The power-up default setting is 00.
Output Mode
Result
100
101
110
4:4:4 RGB mode
4:2:2 YCbCr mode
4:4:4 DDR mode
Table 56. Output Clock Select
Select
Result
0x1F—Bit[4] Primary Output Enable
00
01
10
Pixel clock
90° phase-shifted pixel clock
2× pixel clock
This bit places the primary output in active or high impedance
mode. The power-up default setting is 1.
11
40 MHz internal clock
Table 52. Primary Output Enable
Select
Result
0x20—Bit[5] Output High Impedance
0
1
Primary output is in high impedance mode
Primary output is enabled
This bit puts all outputs (except SOGOUT) in a high impedance
state. The power-up default setting is 0.
0x1F—Bit[3] Secondary Output Enable
Table 57. Output High Impedance
This bit places the secondary output in active or high
impedance mode.
Select
Result
0
1
Normal outputs
All outputs (except SOGOUT) in high impedance mode
The secondary output is designated when using either 4:2:2 or
4:4:4 DDR. In these modes, the data on the blue output channel is
the secondary output while the output data on the red and green
channels are the primary output. Secondary output is always a
DDR YCbCr data mode. See the Output Formatter section and
Table 12. The power-up default setting is 0.
0x20—Bit[4] SOG High Impedance
This bit allows the SOGOUT pin to be placed in high impedance
mode. The power-up default setting is 0.
Table 58. SOGOUT High Impedance
Select
Result
Table 53. Secondary Output Enable
0
1
Normal SOG output
SOGOUT pin is in high impedance mode
Select
Result
0
1
Secondary output is in high impedance mode
Secondary output is enabled
0x20—Bit[3] Field Output Polarity
This bit sets the polarity of the field output bit. The power-up
default setting is 1.
0x1F—Bits[2:1] Output Drive Strength
These two bits select the drive strength for all the high-speed
digital outputs (except VSOUT, A0, and the O/E field). Higher
drive strength results in faster rise/fall times and in general
makes it easier to capture data. Lower drive strength results in
slower rise/fall times and helps to reduce EMI and digitally
generated power supply noise. The power-up default setting is 10.
Table 59. Field Output Polarity
Select
Result
0
1
Active low = even field; active high = odd field
Active low = odd field; active high = even field
Table 54. Output Drive Strength
Output Drive
Result
00
01
10
11
Low output drive strength
Medium low output drive strength
Medium high output drive strength
High output drive strength
Rev. PrA | Page 36 of 44
Preliminary Technical Data
AD9983A
0x24—Bit[6] HSYNC1 Detection Bit
SYNC PROCESSING
This bit is used to indicate when activity is detected on the
HSYNC1 input pin. If Hsync is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = HSYNC1 not active. 1 = HSYNC1
is active.
0x20—Bit[2] PLL Sync Filter
This bit selects which signal the PLL uses. It can select between
either raw Hsync or SOG or filtered versions. The filtering of
the Hsync and SOG can eliminate nearly all extraneous
transitions, which have traditionally caused PLL disruption.
The power-up default setting is 0.
Table 63. HSYNC1 Detection Results
Detect
Result
Table 60. PLL Sync Filter Enable
0
1
No activity detected
Activity detected
Select
Result
0
1
PLL uses raw Hsync or SOG inputs
PLL uses filtered Hsync or SOG inputs
0x24—Bit[5] VSYNC0 Detection Bit
This bit is used to indicate when activity is detected on the
VSYNC0 input pin. If Vsync is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = VSYNC0 not active. 1 = VSYNC0
is active.
0x20—Bit[1] Sync Processing Input Source
This bit selects whether the sync processor uses a raw sync or a
regenerated sync for the following functions: coast, H/V count,
field detection and Vsync duration counts. Using the
regenerated sync is recommended.
Table 64. VSYNC0 Detection Results
Table 61. SP Filter Enable
Detect
Result
Select
Result
0
1
No activity detected
Activity detected
0
1
Sync processing uses raw Hsync or SOG
Sync processing uses the internally regenerated Hsync
0x24—Bit[4] VSYNC1 Detection Bit
0x21—Bits[7:0]
This bit is used to indicate when activity is detected on the
VSYNC1 input pin. If Vsync is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = VSYNC1 not active. 1 = VSYNC1
is active.
Must be set to default
0x22—Bits[7:0]
Must be set to default
0x23—Bits[7:0] Sync Filter Window Width
This 8-bit register sets the window of time for the regenerated
Hsync leading edge (in 25 ns steps) and that sync pulses are
allowed to pass through. Therefore with the default value of 10,
the window width is 250 ns. The goal is to set the window
width so that extraneous pulses are rejected. (see the Sync
Processing section). As in the sync separator threshold, the
25 ns multiplier value is somewhat variable. The maximum
variability over all operating conditions is 20% (20 ns to 30 ns).
Table 65. VSYNC1 Detection Results
Detect
Result
0
1
No activity detected
Activity detected
0x24—Bit[3] SOGIN0 Detection Bit
This bit is used to indicate when activity is detected on the
SOGIN0 input pin. If SOG is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = SOGIN0 not active. 1 = SOGIN0
is active.
DETECTION STATUS
0x24—Bit[7] HSYNC0 Detection Bit
This bit is used to indicate when activity is detected on the
HSYNC0 input pin. If Hsync is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = HSYNC0 not active. 1 = HSYNC0
is active.
Table 66. SOGIN0 Detection Results
Detect
Result
0
1
No activity detected
Activity detected
Table 62. HSYNC0 Detection Results
Detect
Result
0
1
No activity detected
Activity detected
Rev. PrA | Page 37 of 44
AD9983A
Preliminary Technical Data
0x24—Bit[2] SOGIN1 Detection Bit
0x25—Bit[4] VSYNC1 Polarity
This bit is used to indicate when activity is detected on the
SOGIN1 input pin. If SOG is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = SOGIN1 not active. 1 = SOGIN1
is active.
Indicates the polarity of VSYNC1 input.
Table 73. Detected VSYNC1 Polarity Results
Detect
Result
0
1
Vsync polarity is negative
Vsync polarity is positive
Table 67. SOGIN1 Detection Results
0x25—Bit[3] COAST Polarity
Detect
Result
Indicates the polarity of the external COAST signal.
0
1
No activity detected
Activity detected
Table 74. Detected COAST Polarity Results
Detect
Result
0x24—Bit[1] COAST Detection Bit
0
1
Coast polarity is negative
Coast polarity is positive
This bit detects activity on the EXTCK/COAST pin. It indicates
that one of the two signals is active, but it does not indicate
which one. A dc signal is not detected.
0x25—Bit[2] CLAMP Polarity
Indicates the polarity of the CLAMP signal.
Table 68. COAST Detection Result
Detect
Result
Table 75. Detected CLAMP Polarity Results
0
1
No activity detected
Activity detected
Detect
Result
0
1
Clamp polarity is negative
Clamp polarity is positive
0x24—Bit[0] CLAMP Detection Bit
This bit is used to indicate when activity is detected on the
external CLAMP pin. If external CLAMP is held high or low,
activity is not detected.
0x25—Bit[1] Extraneous Pulses Detection
A second output from the Hsync filter, this status bit tells
whether extraneous pulses are present on the incoming sync
signal. Often extraneous pulses are used for copy protection, so
this status bit can be used for this purpose.
Table 69. CLAMP Detection Results
Detect
Result
0
1
No activity detected
Activity detected
Table 76. Equalization Pulse Detect Bit
Detect
Result
0
1
No equalization pulses detected during active Hsync
Equalization pulses detected during active Hsync
POLARITY STATUS
0x25—Bit[7] HSYNC0 Polarity
HSYNC COUNT
Indicates the polarity of HSYNC0 input.
0x26—Bits[7:0] Hsyncs per Vsync MSB
Table 70. Detected HSYNC0 Polarity Results
The 8 MSBs of the 12-bit counter that reports the number of
Hsyncs/Vsync on the active input. This is useful for determining
the mode and is an aid in setting the PLL divide ratio.
Detect
Result
0
1
Hsync polarity is negative
Hsync polarity is positive
0x27—Bits[7:4] Hsyncs per Vsync LSBs
0x25—Bit[6] HSYNC1 Polarity
The 4 LSBs of the 12-bit counter that reports the number of
Hsyncs/Vsync on the active input.
Indicates the polarity of HSYNC1 input.
Table 71. Detected HSYNC1 Polarity Results
TEST REGISTERS
0x28—Bits[7:0] Test Register 1
Detect
Result
0
1
Hsync polarity is negative
Hsync polarity is positive
Must be written to 0xBF for proper operation.
0x29—Bits[7:0] Test Register 2
Must be written to 0x00 for proper operation.
0x2A—Bits[7:0] Test Register 3
Read-only bits for future use.
0x25—Bit[5] VSYNC0 Polarity
Indicates the polarity of VSYNC0 input.
Table 72. Detected VSYNC0 Polarity Results
Detect
Result
0x2B—Bits[7:0] Test Register 4
Read-only bits for future use.
0
1
Vsync polarity is negative
Vsync polarity is positive
Rev. PrA | Page 38 of 44
Preliminary Technical Data
AD9983A
0x2C—Bits[7:5] Auto-Offset Hold
Must be written to 0x00 for proper operation.
0x2C—Bit[4] Auto-Offset Hold
0x36—Bit[0] VCO Gear Select
This bit allows the VCO to select a lower ‘gear’ which enables it
to run lower pixel clocks while remaining in a more linear range.
A bit for controlling whether the auto-offset function runs
continuously or runs once and holds the result. Continuous
updates are recommended because this allows the AD9983A to
compensate for drift over time and temperature. If one-time
updates are preferred, these should be performed every time the
part is powered up and when there is a mode change. To do a
one-time update, first auto-offset must be enabled (Register
0x1B, Bit 5). Next, this bit (auto-offset hold) must first be set to
1 to let the auto-offset function operate and settle to a final
value. Auto-offset hold should then be set to 0 to hold the offset
values that the auto circuitry calculates. The AD9983A auto-
offset circuit’s maximum settle time is 10 updates. For example,
if the update frequency is set to once every 64 Hsyncs, then the
maximum settling time would be 640 Hsyncs (10 × 64 Hsyncs).
Table 79. VCO Gear Select
Select
Result
0
1
Normal VCO setting
Enables lower VCO clock output
0x3C—Bits[7:4] Test Bits
Must be set to 0x0 for proper operation.
0x3C—Bit[3] Auto Gain Matching Hold
A bit for controlling whether the auto gain matching function
runs continuously or runs once and holds the result.
Continuous updates are recommended because it allows the
AD9983A to compensate for drift over time and temperature.
If one-time updates are preferred, these should be performed
every time the part is powered up and when there is a mode
change. To do a one-time update, first auto gain matching must
be enabled (Register Ox3C, Bit 2). Next, this bit (Auto Gain
Matching Hold) must first be set to 1 to let the auto gain
matching function operate and settle to a final value. The Auto
Gain Matching Hold bit should then be set to 0 to hold the gain
values that the auto circuitry calculates. The AD9983A auto gain
matching circuit’s maximum settle time is 10 updates. For example,
if the update frequency is set to once every 64 Hsyncs, then the
maximum settling time would be 640 Hsyncs (10 x 64 Hsyncs).
Table 77. Auto-Offset Hold
Select
Result
0
Disables auto-offset updates and holds the
current auto-offset values
1
Allows auto-offset to update continuously
0x2C—Bits[3:0]
Must be written to 0x0 for proper operation.
0x2D—Bits[7:0] Test Register 5
Read/write bits for future use. Must be written to 0xE8 for
proper operation.
Table 80. Auto Gain Hold
Select
Result
0
Disables auto gain updates and holds the
current auto offset values
Allows auto gain to update continuously
0x2E—Bits[7:0] Test Register 6
Read/write bits for future use. Must be written to 0xE0 for
proper operation.
1
The power-up default setting is 0.
0x34—Bit[2] SOG Filter Enable
0x3C—Bits[2:0] Auto Gain Matching Enable
This bit enables the SOG filter, which will reject inputs with a
width of less than 250 ns. This aids the PLL in the ability to
ignore extraneous (non-valid) sync pulses.
These bits enable or disable the auto gain matching function.
When set to 000, the auto gain matching function is disabled;
when set to 110 the auto gain matching function is enabled.
Table 78. SOG Filter Enable
Table 81. Auto Gain Matching Enable
Select
Result
Select
Result
0
1
SOG filter disabled
SOG filter enabled
000
110
Auto gain matching disabled
Auto gain matching enabled
Rev. PrA | Page 39 of 44
AD9983A
Preliminary Technical Data
PCB LAYOUT RECOMMENDATIONS
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make the
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
The AD9983A is a high precision, high speed analog device.
To achieve the maximum performance from the part, it is
important to have a well laid-out board. The Analog Interface
Inputs section provides a guide for designing a board using
the AD9983A.
ANALOG INTERFACE INPUTS
It is particularly important to maintain low noise and good
stability of the PVD (the clock generator supply). Abrupt
changes in PVD can result in similarly abrupt changes in
sampling clock phase and frequency. This can be avoided with
careful attention to regulation, filtering, and bypassing. It is
highly desirable to provide separate regulated supplies for each
of the analog circuitry groups (VD and PVD).
Using the following layout techniques on the graphics inputs is
extremely important:
•
•
Minimize the trace length running into the graphics
inputs. This is accomplished by placing the AD9983A as
close as possible to the graphics VGA connector. Long
input trace lengths are undesirable because they pick up
noise from the board and other external sources.
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PVD, from a different,
cleaner, power source (for example, from a 12 V supply).
Place the 75 Ω termination resistors (see Figure 4) as close
as possible to the AD9983A chip. Any additional trace
length between the termination resistors and the input of
the AD9983A increases the magnitude of reflections,
which corrupts the graphics signal.
•
•
Use 75 Ω matched impedance traces. Trace impedances
other than 75 Ω also increase the chance of reflections.
It is also recommended to use a single ground plane for the
entire board. Experience has repeatedly shown that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller and long ground loops can result.
The AD9983A has a very high input bandwidth, (200 MHz).
While this is desirable for acquiring a high resolution PC
graphics signal with fast edges, it also means that it captures
any high frequency noise present. Therefore, it is important
to reduce the amount of noise coupled to the inputs. Avoid
running any digital traces near the analog inputs.
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommended to at least place a single ground
plane under the AD9983A. The location of the split should be at
the receiver of the digital outputs. In this case it is even more
important to place components wisely because the current
loops will be much longer, (current takes the path of least
resistance). An example of a current loop is power plane to
AD9983A to digital output trace to digital data receiver to
digital ground plane to analog ground plane.
•
Due to the high bandwidth of the AD9983A, sometimes
low-pass filtering the analog inputs can help to reduce
noise. (For many applications, filtering is unnecessary.)
Experiments have shown that placing a ferrite bead in
series prior to the 75 Ω termination resistor is helpful in
filtering excess noise. Specifically, the Fair-Rite
#2508051217Z0 was used, but an application could work
best with a different bead value. Alternatively, placing a
100 Ω to 120 Ω resistor between the 75 Ω termination
resistor and the input coupling capacitor is beneficial.
PLL
Place the PLL loop filter components as close to the FILT pin as
possible. Do not place any digital or other high frequency traces
near these components. Use the values suggested in the data-
sheet with 10% tolerances or less.
Power Supply Bypassing
It is recommended to bypass each power supply pin with a
0.1 μF capacitor. The exception is where two or more supply
pins are adjacent to each other. For these groupings of
powers/grounds, it is only necessary to have one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Also, avoid placing the
capacitor on the opposite side of the PC board from the
AD9983A, since that interposes resistive vias in the path.
Rev. PrA | Page 40 of 44
Preliminary Technical Data
AD9983A
OUTPUTS (BOTH DATA AND CLOCKS)
DIGITAL INPUTS
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance and require more
instantaneous current to drive, which creates more internal
digital noise. Shorter traces reduce the possibility of reflections.
Digital inputs on the AD9983A (HSYNC0, HSYNC1, VSYNC0,
VSYNC1, SOGIN0, SOGIN1, SDA, SCL, and CLAMP) are
designed to work with 3.3 V signals, but are tolerant of 5.0 V
signals. Therefore, no extra components need to be added if
using 5.0 V logic.
Adding a series resistor of value 50 Ω to 200 Ω can suppress
reflections, reduce EMI, and reduce the current spikes inside of
the AD9983A. If series resistors are used, place them as close to
the AD9983A pins as possible, but try not to add vias or extra
length to the output trace to get the resistors closer.
Any noise that gets onto the Hsync input trace adds jitter to the
system. Therefore, minimize the trace length and do not run
any digital or other high frequency traces near it.
Reference Bypass
If possible, limit the capacitance that each digital output drives
to less than 10 pF. This is easily accomplished by keeping traces
short and by connecting the outputs to only one device.
Loading the outputs with excessive capacitance increases the
current transients inside of the AD9983A and creates more
digital noise on its power supplies.
The AD9983A has three reference voltages that must be
bypassed for proper operation of the input PGA. REFLO and
REFHI are connected to each other through a 10 μF capacitor.
These references are used by the input PGA circuitry to assure
the greatest stability. Place them as close to the AD9983A pin as
possible. Make the ground connection as short as possible.
Rev. PrA | Page 41 of 44
AD9983A
Preliminary Technical Data
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
0.75
0.60
0.45
1.60
MAX
61
60
80
1
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.10
COPLANARITY
20
41
40
0.15
0.05
21
SEATING
PLANE
VIEW A
0.65
0.38
0.32
0.22
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 20. 80-Lead Low Profile Quad Flat Pack [LQFP]
(ST-80-2)
Dimensions shown in millimeters
0.30
0.25
0.18
PIN 1
9.00
BSC SQ
0.60 MAX
0.60 MAX
64
49
48
INDICATOR
1
PIN 1
INDICATOR
*
4.85
4.70 SQ
4.55
8.75
BSC SQ
TOP
VIEW
EXPOSED PAD
(BOTTOM VIEW)
0.50
33
32
16
17
0.40
0.30
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
SEATING
PLANE
0.50 BSC
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 21. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ST-80-2
ST-80-2
CP-64-1
CP-64-1
AD9983AKSTZ-1401
AD9983AKSTZ-1701
AD9983AKCPZ-1401
AD9983AKCPZ-1701
AD9983A/PCB
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
80-Lead Low Profile Quad Flat Pack [LQFP]
80-Lead Low Profile Quad Flat Pack [LQFP]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Kit
1 Z = Pb-free part.
Rev. PrA | Page 42 of 44
Preliminary Technical Data
NOTES
AD9983A
Rev. PrA | Page 43 of 44
AD9983A
NOTES
Preliminary Technical Data
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
Pr06475-0-2/07(PrA)
Rev. PrA | Page 44 of 44
相关型号：
AD9984KSTZ-110
IC SPECIALTY INTERFACE CIRCUIT, PQFP80, LEAD FREE,PLASTIC,MS-026BEC,LQFP-80, Interface IC:Other
ADI
AD9984KSTZ-140
IC SPECIALTY INTERFACE CIRCUIT, PQFP80, LEAD FREE,PLASTIC,MS-026BEC,LQFP-80, Interface IC:Other
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