AD9995KCPZRL [ADI]
IC SPECIALTY CONSUMER CIRCUIT, QCC56, 8 X 8 MM, MO-220-VLLD-2, LFCSP-56, Consumer IC:Other;
| 型号： | AD9995KCPZRL |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, QCC56, 8 X 8 MM, MO-220-VLLD-2, LFCSP-56, Consumer IC:Other 商用集成电路 |
| 文件： | 总60页 (文件大小：1737K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit CCD Signal Processor with
Precision Timing™ Generator
AD9995
FEATURES
GENERAL DESCRIPTION
6-PhaseVerticalTransfer Clock Support
Correlated Double Sampler (CDS)
6 dB to 42 dB 10-BitVariable Gain Amplifier (VGA)
12-Bit 36 MHz A/D Converter
Black Level Clamp withVariable Level Control
Complete On-ChipTiming Generator
PrecisionTiming Core with <600 ps Resolution
On-Chip 3V Horizontal and RG Drivers
2-Phase and 4-Phase H-Clock Modes
Electronic and Mechanical Shutter Modes
On-Chip Driver for External Crystal
On-Chip Sync Generator with External Sync Input
56-Lead LFCSP Package
The AD9995 is a highly integrated CCD signal processor for
digital still camera and camcorder applications. It includes a
complete analog front end with A/D conversion, combined with a
full-function programmable timing generator.The timing genera-
tor is capable of supporting both 4- and 6-phase vertical clocking.
A PrecisionTiming core allows austment of high speed clocks
with less than 600 ps resolutioat 36 MHz operation.
The AD9995 is specified axel raof up to 36 MHz.The
analog front end includs blacel clampg, CDS,VGA,
and a 12-bit A/D coerter.The ing nerator provides all
the necessary CCcks: RG, H-s,V-clocks, sensor gate
pulses, substrate clock, d substrate bias control. Operation is
programmeusing a 3-wierial interface.
APPLICATIONS
Packagein a space-saving 56-lead LFCSP, the AD9995 is speci-
fied oan opating temperature range of –20°C to +85°C.
Digital Still Cameras
DigitalVideo Camcorders
Industrial Imaging
FUNCTIONAL OCK DIAGRAM
VRB
AD9995
VREF
12
12-BIT
ADC
CDS
DOUT
DCLK
CCDIN
CLAMP
INTERNAL CLOCKS
PRECISION
TIMING
GENERATOR
ORIZONTAL
DRIVERS
MSHUT
STROBE
H1–H
V-H
CONTROL
SYNC
GENERATOR
INTERNAL
REGISTERS
5
VSUB SUBCK
HD
VD SYNC CLI CLO SL SCK DATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed byAnalog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or oth-
erwise under any patent or patent rights of Analog Devices.Trademarks
and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9995
TABLE OF CONTENTS
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
AD9995 Analog Specifications . . . . . . . . . . . . . . . . . . . . . . 4
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . 5
PACKAGETHERMAL CHARACTERISTICS. . . . . . . . . . . 5
ORDERING GUIDE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . 6
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
EQUIVALENT CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . 7
TYPICAL PERFORMANCE CHARACTERISTICS . . . . . . 8
SYSTEM OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PRECISIONTIMING HIGH SPEEDTIMING
GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timing Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
High Speed Clock Programmability . . . . . . . . . . . . . . . . . 10
H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . 11
Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
HORIZONTAL CLAMPING AND BLANKING . . . . . . . . 13
Individual CLPOB and PBLK Patterns. . . . . . . . . . . . . . . 13
Individual HBLK Patterns . . . . . . . . . . . . . . . . . . . . . . . . 13
Generating Special HBLK Patterns. . . . . . . . . . . . . . . . . . 14
Generating HBLK Line Alternation . . . . . . . . . . . . . . . . . 14
HORIZONTALTIMING SEQUENCE EXAMPLE . . . . . . 15
VERTICALTIMING GENERATION . . . . . . . . . . . . . . . . 16
Vertical Pattern Groups (VPAT) . . . . . . . . . . . . . . . . . . . .
Vertical Sequences (VSEQ) . . . . . . . . . . . . . . . . . . . . . . .
Complete Field: CombiningV-Sequences . . . . . . . . . . .
Generating Line Alternation forV-Sequence and HBLK
SecondV-Pattern Group duringVSG Active Line . . . . . .
Sweep Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . 2
Multiplier Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Vertical Sensor Gate (Shift Gate) Patterns . . . . . . 22
MODE Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VERTICALTIMING EXAMPLE . . . . . . . . . . . . . . . . . . . . 24
Important Note about Signal Polarities . . . . . . . . . . . . . . . 24
SHUTTERTIMING CONTROL. . . . . . . . . . . . . . . . . . . . 26
Normal Shutter Operation . . . . . . . . . . . . . . . . . . . . . . . . 26
High Precision Shutter Operation . . . . . . . . . . . . . . . . . . . 26
Low Speed Shutter Operation. . . . . . . . . . . . . . . . . . . . . . 26
SUBCK Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Readout after Exposure. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Using theTRIGGER Register. . . . . . . . . . . . . . . . . . . . . . 27
VSUB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MSHUT and STROBE Control . . . . . . . . . . . . . . . . . . 28
TRIGGER Register Limitations . . . . . . . . . . . . . . . . . . 29
EXPOSURE AND READOUT XAMP. . . . . . . . . . . . 30
AFE DESCRIPTION AND OPATN . . . . . . . . . . . . . 31
DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Correlated Double Saler . . . . . . . . . . . . . . . . . . 31
Variable Gain Ampfier . . . . . . . . . . . . . . . . . . . . . . . 31
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Optical BlacClamp. . . . . . . . . . . . . . . . . . . . . . . . . . 32
Digital DaOutputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
POWER-AND YNCHRONIZATION . . . . . . . . . . . . . 33
RecommeePower-USequence for Master Mode. . . . 33
Generating Sware NC without
External SYNgnal . . . . . . . . . . . . . . . . . . . . . . . . . 33
YNC during Master Mode Operation . . . . . . . . . . . . . . . 34
Per-Up anSynchronization in Slave Mode . . . . . . . . . 34
STANBY ODE OPERATION. . . . . . . . . . . . . . . . . . . . 34
RCUILAYOUT INFORMATION . . . . . . . . . . . . . . . . 36
IAL INTERFACETIMING . . . . . . . . . . . . . . . . . . . . . 37
gister Address Banks 1 and 2. . . . . . . . . . . . . . . . . . . . . 38
pdating of New RegisterValues. . . . . . . . . . . . . . . . . . . . 39
COMPLETE LISTING OF REGISTER BANK 1 . . . . . . . 40
COMPLETE LISTING OF REGISTER BANK 2 . . . . . . . 43
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 59
–2–
REV. 0
Parameter
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
–20
–65
+85
+150
°C
°C
POWER SUPPLYVOLTAGE
AVDD (AFE Analog Supply)
TCVDD (Timing Core Analog Supply)
RGVDD (RG Driver)
HVDD (H1–H4 Drivers)
DRVDD (Data Output Drivers)
DVDD (Digital)
2.7
2.7
2.7
2.7
2.7
2.7
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
3.6
V
V
V
V
V
V
POWER DISSIPATION (SeeTPC 1 for Power Curves)
36 MHz,Typ Supply Levels, 100 pF H1–H4 Loading
Power from HVDD Only
Standby 1 Mode
Standby 2 Mode
360
130
1
mW
mW
mW
mW
mW
Standby 3 Mode
0.5
MAXIMUM CLOCK RATE (CLI)
36
MHz
The total power dissipated by the HVDD supply may be approximated using the equation
Total HVDDPower = C
× HVDD × Pixel Frequency × HVDD × Number of Huts use
Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will rede power diation.
Specifications subject to change without notice.
ymbo
Typ
High Level InputVoltage
Low Level InputVoltage
High Level Input Current
Low Level Input Current
Input Capacitance
IL
IH
IL
IN
µA
µA
pF
LOGIC OUTPUTS (Except H a)
High Level OutputVoltage
Low Level OutputVoltage
OH
OL
RG and H-DRIVER OUTPUTS
High Level Outpu@ Maent
Low Level OutMax Crrent
Maximum Ouogrammable)
Maximum LoaFor Each Output)
OH
OL
pF
Specifications subject to chut notice.
REV. 0
(AVDD = 3.0 V, fCLI = 36 MHz, Typical Timing Specifications, TMIN MAX, unless otherwise noted.)
Typ
Max Input Range before Saturation
Max CCD Black Pixel Amplitude
V p-p
VARIABLE GAIN AMPLIFIER (VGA)
Gain Monotonicity
Steps
Gain Range
Min Gain (VGA Code 0)
Max Gain (VGA Code 1023)
Clamp Level Resolution
Clamp Level
Steps
MeasureADutput.
Min Clamp Level (Code 0)
Max Clamp Level (Code 255)
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale InputVoltage
ReferenceTopVoltage (REFT)
Reference BottomVoltage (REFB)
Gain Accuracy
Includes entire signal chain.
Low Gain (VGA Code 0)
Max Gain (VGA Code 1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
%
Gain = (0.0351 Code) + 6 dB
12 dB gain applied.
AC grounded input, 6 dB gain applied.
Measured with step change on supply.
Power Supply Rejection (PSR)
Input signal characteristics defined as follows:
500mV TYP
RESET TRANSIENT
50mV MAX
OPTICAL BLACK PIXEL
1V MAX
INPUT L RANGE
Specifications subject to chane.
REV. 0
(CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 36 MHz, unless otherwise noted.)
Symbol
Typ
MASTER CLOCK, CLI (Figure 4)
CLI High/Low Pulsewidth
CONV
Delay from CLI Rising Edge to Internal Pixel Position 0
CLIDLY
1, 2 (Figures 9 and 14)
1 (Figure 7)
SHP Sample Edge to SHD Sample Edge
S1
DATA OUTPUTS (Figures 8a and 8b)
Output Delay from DCLK Rising Edge1
Pipeline Delay from SHP/SHD Sampling to DOUT
OD
Cycles
SERIAL INTERFACE (Figures 40a and 40b)
Maximum SCK Frequency
SL to SCK SetupTime
SCLK
LS
LH
DS
DH
DV
SDATAValid to SCK Rising Edge Setup
SCK Falling Edge to SDATAValid Hold
SCK Falling Edge to SDATAValid Read
1Parameter is programmable.
2Minimum CLPOB pulsewidth is for functional operation only.Wider typical pulses are recommended chievod clamp performance.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
JA
JA is measured using a 4-layer PCB with the exposed paddle soldered to the
board.
With
Respect
To
Parameter
Min Max
AVDD
TCVDD
HVDD
RGVDD
DVDD
DRVDD
RG Output
H1–H4 Output
Digital Outputs
Digital Inputs
SCK, SL, SDATA
REFT, REFB, CC
JunctionTemperat
LeadTemperature,
AVSS
–0.3 +3.9
–0.3 +39
–0.+3.9
–0.
–0.3 +3.9
.3 +39
V
V
V
V
TCVSS
HVSS
RGVSS
DVSS
DRVS
RG
DVS
Temperature
Range
Package
Description Option
Package
.RGVDD+0.3 V
3
DVDD + 0.3
DVDD + 0.3
150
V
V
°C
S
Stresses above those listed ubsolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only. Functional operation of the device
at these or any other conditions above those listed in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Absolute maximum ratings apply
individually only, not in combination. Unless otherwise specified, all other voltages
are referenced to GND.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9995 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
42 SDI
D5
D6
1
2
3
4
5
6
7
8
9
PIN 1
IDENTIFIER
41 SL
D7
40 REFB
39 REFT
38 AVSS
37 CCDIN
36 AVDD
35 CLI
D8
D9
D10
AD9995
TOP VIEW
(MSB) D11
DRVDD
DRVSS
34 CLO
VSUB 10
SUBCK 11
V1 12
33 TCVDD
32 TCVSS
31 RGV
30 R
V2 13
V3 14
29 GV
Type2 Description
Type2 Description
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output (M)
Data Output Der Sup
Data Output Dround
CCD e Clock utter)
H1–H4 Driver Supply
Analog Supply for AFE
CCD Signal Input
Analog Ground for AFE
Voltage ReferenceTop Bypass
Voltage Reference Bottom Bypass
3-Wire Serial Data Input
External System Sync Input
Vertical Sync Pulse
(Input for Slave Mode,
Output for Master Mode)
Digital Ground
Power Supply forVSG,V1–V6,
HD/VD, MSHUT, STROBE,
SYNC, and Serial Interface
Horizontal Sync Pulse
(Input for Slave Mode, Output for
Master Mode)
Data Clock Output
Data Output (LSB)
Data Output
Data Output
Data Output
Data Output
NOTES
1See Figure 38 for circuit configuration.
2AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
RG Driver Supply
Analog Ground forTiming Core
Analog Supply forTiming Core
Clock Output for Crystal
Reference Clock Input
REV. 0
Differential Nonlinearity (DNL)
age of the 2V ADC full-scale signal.The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value.Therefore,
every code must have a finite width. No missing codes guaran-
present over all operating conditions.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated in
LSB and represents the rms noise level of the total signal chain at
the specified gain setting.The output noise can be converted to
an equivalent voltage using the relationship 1 LSB = (ADC Full
n codes), where n is the bit resolution of the ADC. For the
AD9995, 1 LSB is 0.488 mV.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to
the peak deviation of the output of the AD9995 from a true
straight line. The point used as zero scale occurs 0.5 LSB
a level 1.5 LSB beyond the last code transition. The deviation
is measured from the middle of each particular output code to
the true straight line. The error is then expressed as a percent-
Power Supply Rejection (PSR)
The PSR is measured with a step hange applied to the supply
pins.The PSR specification is culated from the change in the
data outputs for a given stehange ithe supply voltage.
DVD
EQUIVALENT CIRCUITS
AVDD
R
AVSS
AVSS
DVSS
Circuit 1. CCDIN
Circuit 3. Digital Inputs
HVDD OR
RGVDD
DVDD
DRVDD
RG, H1–H4
DATA
ENABLE
OUTPUT
THREE-
STATE
DOUT
HVSS OR
RGVSS
DVSS
DRVSS
Circuit 4. H1–H4, RG Drivers
Circuit 2. Digital Data Outputs
REV. 0
AD9995–Typical Performance Characteristics
48
40
450
400
V
= 3.3V
DD
32
24
V
= 3.0V
350
300
DD
V
= 2.7V
DD
16
8
250
200
150
0
18
24
30
36
0
400
600
800
1000
200
SAMPLE RATE (MHz)
VGA GODE B)
TPC 3. Outut Noise . VGA ain
TPC 1. Power Dissipation vs. Sample Rate
1.0
0.5
0
–0.5
–1.0
0
500
1000 1500
2000 2500 3000 500 4000
CODES
TPC 2.Typical DNL Performance
REV. 0
The H-drivers for H1–H4 and RG are included in the AD9995,
allowing these clocks to be directly connected to the CCD.
H-drive voltage of up to 3.3V is supported. An externalV-driver
is required for the vertical transfer clocks, the sensor gate pulses,
Figure 1 shows the typical system block diagram for the AD9995
used in Master mode. The CCD output is processed by the
AD9995’s AFE circuitry, which consists of a CDS, VGA, black
level clamp, and A/D converter. The digitized pixel information
is sent to the digital image processor chip, which performs the
postprocessing and compression. To operate the CCD, all CCD
timing parameters are programmed into the AD9995 from the
system microprocessor through the 3-wire serial interface. From
the system master clock, CLI, provided by the image processor
or external crystal, the AD9995 generates all of the CCD’s hori-
synchronization is provided by a SYNC pulse from the micropro-
cessor, which will reset internal counters and resync the VD and
HD outputs.
The AD9995 also includes programmable MSHUT and
STROBE outputs, which may be used to trigger mechanical
shutter and strobe (flash) circuitry.
Figures 2 and 3 show the maximum horizontal and vertical
vertical clocking is controlled by these counters to specify line
and pixel locations. Maximum Hlength is 4095 pixels per line,
and maximumVD length is 40lines per field.
MAXIMUM
FIELD
DIMENSIONS
Alternatively, the AD9995 may be operated in Slave mode, in
whichVD and HD are provided externally from the image pro-
cessor. In this mode, all AD9995 timing will be synchronized
V1–V6, VSG1–VSG5, SUBCK
V-DRIVER
12HORIZONTAL = 4096 PIXELS MAX
H1–H4, RG, VSUB
DOUT
DCLK
DIGITAL
IMAGE
PROCESSING
ASIC
CCDIN
CCD
AD9995
AFETG
HD, VD
CLI
MSHUT
STROBE
12-BITVERTICAL = 4096 LINES MAX
SERIAL
INTERFACE
SYNC
Figure 2. Vertical and Horizontal Counters
MAX VD 4095 LINE
VD
AX HD LENGTH IS 4095 PIXELS
HD
CLI
Figure 3. Maximum VD/HD Dimensions
REV. 0
The AD9995 generates high speed timing signals using the
flexible PrecisionTiming core.This core is the foundation for
generating the timing used for both the CCD and the AFE: the
reset gate RG, horizontal drivers H1–H4, and SHP/SHD sample
clocks. A unique architecture makes it routine for the system
designer to optimize image quality by providing precise control
sampling.
CLIDIVIDE register (Addr. 0x30).The AD9995 will then inter-
nally divide the CLI frequency by 2.
The AD9995 also includes a master clock output, CLO, which is
the inverse of CLI.This output is intended to be used as a crystal
driver. A crystal can be placed between the CLI and CLO pins to
generate the master clock for the AD9995. For more information
on using a crystal, see Figure 39.
High Speed Clock Programmability
Figure 5 shows how the high speed clocks RG, H1–H4, SHP,
and SHD are generated.The RG pulse has programmable rising
and falling edges, and may be inverted using the polarity control.
The horizontal clocks H1 and H3 havprogrammable rising
and falling edges and polarity contr.The H2 and H4 clocks
are always inverses of H1 aH3, rpectively. Table I
summarizes the high speed timinegirs and their parameters.
Figure 6 shows the typical phase ock arrgement in
which H3 and H4 are prammed foe sme edge location as
The high speed timing of the AD9995 operates the same in either
Master or Slave mode configuration. For more information on
synchronization and pipeline delays, see the Power-Up and Syn-
Timing Resolution
The PrecisionTiming core uses a 1master clock input (CLI)
as a reference.This clock should be the same as the CCD pixel
clock frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Using a 20 MHz CLI frequency, the edge resolution of the Preci-
sionTiming core is 1 ns. If a 1system clock is not available, it
is also possible to use a 2reference clock by programming the
The edge locatioregisters arbits wide, but there are only 48
valid edge locons available.Thfore, the register values are
P[0]
P[12]
P[24]
36]
P[48] = P[0]
POSITION
CLI
tCLIDLY
1 PIXEL
PERIOD
NOTES
PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITS, PROVIDING FINE EE RESOLUTION FOR HIGH SPEED CLOCKS.
THERE IS A FIXED DELAY FROM THE CLI INPUT THE INPIXEL PERIOD POSITIONS (tCLIDLY = 6ns TYP).
Figure 4. High Speed Clocesolution from CLI Master Clock Input
CCD
SIGNAL
4
6
H1
H2
7
8
H3
H4
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE
5. H1 RISING EDGE POSITION
2. RG FALLING EDGE
6. H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1)
7. H3 RISING EDGE POSITION
3. SHP SAMPLE LOCATION
4. SHD SAMPLE LOCATION
8. H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3)
REV. 0
AD9995
Digital Data Outputs
mapped into four quadrants, with each quadrant containing 12
edge locations.Table II shows the correct register values for the
corresponding edge locations.
The AD9995 data output and DCLK phases are programmable
using the DOUTPHASE register (Addr. 0x37, Bits [5:0]). Any
edge from 0 to 47 may be programmed, as shown in Figure 8a.
Normally, the DOUT and DCLK signals will track in phase
based on the DOUTPHASE register contents. The DCLK
output phase can also be held fixed with respect to the data out-
puts by changing the DCLKMODE register high (Addr. 0x37,
Bit 6). In this mode, the DCLK output will remain at a fixed
phase equal to CLO (the inverse of CLI) while the data output
phase is still programmable.
Figure 7 shows the default timing locations for all of the high
speed clock signals.
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9995
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver and RG current can be adjusted for optimum
rise/fall time into a particular load by using the DRVCONTROL
register (Addr. 0x35). The 3-bit drive setting for each output is
adjustable in 4.1 mA increments, with the minimum setting of 0
equal to OFF or three-state, and the maximum setting of 7 equal
to 30.1 mA.
There is a fixed output delay from the DCLK rising edge to the
DOUT transition, called tOD.Tdelay can be programmed to
four values between 0 ns and 2 ns by sing the DOUTDELAY
register (Addr. 0x037, Bits 7]).Tdefault value is 8 ns.
The pipeline delay thrgh the 9995 is own in Figure 8b.
After the CCD inps sampled bHthere is an 11-cycle
delay until the da is ailable.
As shown in Figures 5, 6, and 7, the H2 and H4 outputs are
inverses of H1 and H3, respectively. The H1/H2 crossover volt-
age is approximately 50% of the output swing. The crossover
voltage is not programmable.
Table I.Timing Core Register Parameters r H1, HRG, SHP/SHD
Parameter
Length
Range
Description
Polarity
1b
6b
6b
6b
3b
High/Low
Polarity Control fH13, and RG (0 = No Inversion, 1 = Inversion)
Psitive Edge Locatifor H1, H3, and RG
Neive Edge Location for H1, H3, and RG
Sampg Locan for Internal SHP and SHD Signals
ive Cfor H1–H4 and RG Outputs (4.1 mA per Step)
Positive Edge
Negative Edge
Sampling Location
Drive Strength
0–47 Edge Location
0–47 Edge Location
0–47 Edge Location
0–47 Current St
CCD
SIGNAL
RG
H1/H3
TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.
Figure 6. 2-Phase H-Clock Operation
Table II. PrecisionTiming Edge Locations
Quadrant
Edge Location (Dec)
RegisterValue (Dec)
RegisterValue (Bin)
I
II
III
IV
0 to 11
0 to 11
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
12 to 23
24 to 35
36 to 47
16 to 27
32 to 43
48 to 59
REV. 0
–11–
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
POSITION
PIXEL
PERIOD
RGr[0]
RGf[12]
RG
Hr[0]
Hf[24]
H1/H3
H2/H4
SHP[24]
tS1
CCD
SIGNAL
S
NOTES
ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 PTIONS WHIN ONE PIXEL PERIOD.
DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.
Figure 7. High SpeedTiming Default Lions
P[0]
P[12]
P[24]
P[36]
P[48] = P[0]
PIXEL
PERIOD
DCLK
tOD
DOUT
NOTES
DATA OUTPUT ASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
WITHIN ONE CA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
OUTPUT DELAY (NG EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
gure 8a. Digital Output Phase Adjustment
CLI
tCLIDLY
N–1
N
N+1
N+4
N+5
N+6
N+7
N+8
N+9
N+10
N+11
N+12
N+13
N+2
N+3
CCDIN
SAMPLE PIXEL N
SHD
(INTERNAL)
DCLK
DOUT
PIPELINE LATENCY=11 CYCLES
N–8 N–7 N–6 N–5
N+2
N+1
N–11
N–10
N–9
N–4
N–3
N–2
N–1
N
N–13
N–12
NOTES
DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0, DCLKMODE = 0.
HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
Figure 8b. Pipeline Delay
REV. 0
AD9995
HORIZONTAL CLAMPING AND BLANKING
each containing a unique pulse pattern for CLPOB and PBLK.
Figure 9 shows how the sequence change positions divide the
readout field into different regions. A differentV-sequence can be
assigned to each region, allowing the CLPOB and PBLK signals
to be changed accordingly with each change in the vertical timing.
The AD9995’s horizontal clamping and blanking pulses are fully
programmable to suit a variety of applications. Individual control
is provided for CLPOB, PBLK, and HBLK during the different
regions of each field.This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout in
order to accommodate different image transfer timing and high
speed line shifts.
Individual HBLK Patterns
The HBLK programmable timing shown in Figure 10 is simi-
lar to CLPOB and PBLK. However, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, there is a
polarity control HBLKMASK that designates the polarity of the
horizontal clock signals H1–H4 during the blanking period. Set-
ting HBLKMASK high will set 1 = H3 = low and H2 = H4 =
high during the blanking, as own in igure 11. As with the
CLPOB and PBLK signalsBLK gisters are available in each
V-sequence, allowing derent king sigs to be used with
different vertical timg sequenc
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 9.These two signals are independently pro-
grammed using the registers inTable III. SPOL is the start
polarity for the signal, andTOG1 andTOG2 are the first and
second toggle positions of the pulse. Both signals are active low
and should be programmed accordingly.
A separate pattern for CLPOB and PBLK may be programmed
for every 10V-sequences. As described in theVerticalTiming
Generation section, up to 10 separateV-sequences can be created,
. . .
HD
(2)
(3)
. . .
CLPOB
PBLK
(1)
ACTIVE
ACTIVE
NOTES
PROGRAMMABLE SETTINGS:
1. START POLARITY (CLAMP AND BLANK REGIOW)
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION
Figure 9. ClaBlank Pulse Placement
III. COB and PBLK Pattern Registers
Register
Length
Range
Description
SPOL
TOG1
TOG2
1b
12b
12b
i/Low
Pixel Location
Pixel Location
Starting Polarity of CLPOB/PBLK forV-Sequence 0–9
FirstToggle Position within Line forV-Sequence 0–9
SecondToggle Position within Line forV-Sequence 0–9
Table IV. HBLK Pattern Registers
Register
Range
Description
HBLKMASK
HBLKALT
2b
High/Low
0–3 Alternation Mode
Masking Polarity for H1/H3 (0 = H1/H3 Low, 1 = H1/H3 High)
Enables Odd/Even Alternation of HBLKToggle Positions 0 =
Disable Alternation. 1 =TOG1–TOG2 Odd,TOG3–TOG6 Even.
2 = 3 =TOG1–TOG2 Even,TOG3–TOG6 Odd
HBLKTOG1
HBLKTOG2
HBLKTOG3
HBLKTOG4
HBLKTOG5
HBLKTOG6
12b
12b
12b
12b
12b
12b
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
FirstToggle Position within Line for EachV-Sequence 0–9
SecondToggle Position within Line for EachV-Sequence 0–9
ThirdToggle Position within Line for EachV-Sequence 0–9
FourthToggle Position within Line for EachV-Sequence 0–9
FifthToggle Position within Line for EachV-Sequence 0–9
SixthToggle Position within Line for EachV-Sequence 0–9
REV. 0
–13–
Generating Special HBLK Patterns
Generating HBLK Line Alternation
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions may be
used to generate special HBLK patterns, as shown in Figure 12.
The pattern in this example uses all six toggle positions to gen-
erate two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
One further feature of the AD9995 is the ability to alternate dif-
ferent HBLK toggle positions on odd and even lines.This may be
used in conjunction withV-pattern odd/even alternation or on its
own.When a 1 is written to the HBLKALT register,TOG1 and
TOG2 are used on odd lines only, whileT
on even lines.Writing a 2 to the HBLKALT register gives the
opposite result:TOG1 andTOG2 are used on even lines, while
TOG3–TOG6 are used on odd lines. See theVerticalTiming
Generation, Line Alternation section for more information.
HD
1
2
BLANK
BLANK
HBLK
PROGRAMMABLE SETTINGS:
1. FIRST TOGGLE POSITION = START OF BLANKING
2. SECOND TOGGLE POSITION = END OF BLANKING
Figure 10. Horizontal Blanking (HBLK) Pse Placment
HD
HBLK
H1/H3
H1/H3
H2/H4
THE POLARITY OF NG BLAGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1).
Figure 11. HBLK Masking Control
TOG2 TOG3
TOG1
TOG4 TOG5
TOG6
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS.
Figure 12. Generating Special HBLK Patterns
REV. 0
HORIZONTALTIMING SEQUENCE EXAMPLE
Figure 13 shows an example CCD layout.The horizontal register
contains 28 dummy pixels, which will occur on each line clocked
from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and two at the back
of the readout.The horizontal direction has four OB pixels in the
The HBLK, CLPOB, and PBLK parameters are programmed in
theV-sequence registers.
More elaborate clamping schemes may be used, such as adding
in a separate sequence to clamp during the entire shield OB lines.
This requires configuring a separateV-sequence for reading out
Figure 14 shows the basic sequence layout to be used during the
effective pixel readout.The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the noneffective CCD
pixels. HBLK is used during the vertical shift interval.
2 VERTIB LINES
10 VTICAL OB LINES
EFFECTIVE IMAGE AREA
V
H
48 OB PIX
4 OB PIXELS
HORIZOISTER
28 DUMMY PIXELS
Figure 13. Example CCD Configuration
HD
OB
OPTICAL BLACK
OPTICALBLACK
VERT
DUMMY
EFFECTIVE PIXELS
VERT SHIFT
CCDIN
SHP
SHD
H1/H3
H2/H
HBLK
PBLK
CLPOB
Figure 14. Horizontal Sequence Example
REV. 0
are created by using the vertical pattern group registers. Second,
theV-pattern groups are used to build the sequences, where
additional information is added.Third, the readout for an entire
field is constructed by dividing the field into different regions and
then assigning a sequence to each region. Each field can contain
up to seven different regions to accommodate different steps of
the readout such as high speed line shifts and unique vertical line
transfers. Up to six different fields may be created. Finally, the
Mode register allows the different fields to be combined into any
order for various readout configurations.
The AD9995 provides a very flexible solution for generating
vertical CCD timing, and can support multiple CCDs and dif-
ferent system architectures.The 6-phase vertical transfer clocks
V1–V6 are used to shift each line of pixels into the horizontal
output register of the CCD.The AD9995 allows these outputs to
be individually programmed into various readout configurations
using a 4-step process.
Figure 15 shows an overview of how the vertical timing is gener-
ated in four steps. First, the individual pulse patterns forV1–V6
CREATE THE VERTICAL PATTERN GROUPS
(MAXIMUM OF 10 GROUPS).
BUILD THE V-SEQUENCES BY ADDING LINE START
POSITION, # OF REPEATS, AND HBLPOB PULSES
(MAXIMUM OF 10 V-SEQUENCES)
V1
V2
V1
V2
V3
VPAT 0
V4
V3
V-SEQUENCE 0
V4
(VPAT0, 1 REP)
V5
V5
V6
6
V1
V1
V2
V3
V
V-SEQUENCE 1
V4
AT9, 2 REP)
VPAT 9
V4
V6
V5
V6
V1
V2
V3
V-SEQUENCE 2
V4
(VPAT9, N REP)
V5
V6
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS,
AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF 7 REGIONS IN EACH FIELD)
(MAXIMUM OF 6 FIELDS).
USE THE MTO COWHICH FIELDS
ARE USEDER
(MAXIMUE COMBINED IN ANY ORDER).
FIELD 0
FIELD 4
FIELD 1
FIELD 2
FIELD 0
FIELD 3
FIELD 5
REGION 0: USE V-SEQUENCE 2
REGION 1: USE V-SEQUENCE 0
REGION 2: USE V-SEQUENCE 3
REGION 3: USE V-SEQUENCE 0
FIELD 2
FIELD 4
REGION 4: USE V-SEQUENCE 2
FIELD 1
FIELD 2
Figure 15. Summary of VerticalTiming Generation
REV. 0
Vertical Pattern Groups (VPAT)
length of theV-pattern group, which will determine the number
of pixels between each of the pattern repetitions, when repetitions
are used (see theVertical Sequences section).
The vertical pattern groups define the individual pulse patterns
for eachV1–V6 output signal.TableV summarizes the registers
available for generating each of the 10V-pattern groups.The start
polarity (VPOL) determines the starting polarity of the vertical
sequence, and can be programmed high or low for eachV1–V6
output.The first, second, and third toggle position (VTOG1,
VTOG2, VTOG3) are the pixel locations within the line where
the pulse transitions. A fourth toggle position (VTOG4) is also
available for V-Pattern Groups 8 and 9. All toggle positions are
12-bit values, allowing their placement anywhere in the hori-
zontal line. A separate register,VPATSTART, specifies the start
position of theV-pattern group within the line (see theVertical
Sequences section).TheVPATLEN register designates the total
The FREEZE and RESUME registers are used to temporarily
stop the operation of the V1–V6 outputs. At the pixel location
specified in the FREEZE register, the V1–V6 outputs will be
held static at their current dc state, high or low. The V1–V6
outputs are held until the pixel location specified by RESUME
register. Two sets of FREEZE/RESUME registers are pro-
vided, allowing the vertical outputs to be interrupted twice in
the same line. The FREEZE and RESUME positions are pro-
grammed in the V-pattern group registers, but are separately
enabled using the VMASK regers, which are described in the
Vertical Sequence section.
TableV.Vertical Pattern Group Registers
Register
Length
Range
Description
High/Low
Starting Polarty of EachVV6 Output
FirstToggle osition within Lfor EachV1–V6 Output
Secondggle Potion within Line for EachV1–V6 Output
ThirdTgle Ption within Line for EachV1–V6 Output
FourthToPositionnly Available inV-Pattern Groups 8 and 9
Total Length EacV-Pattern Group
Holds theV1–Vutputs atTheir Current Levels (Static DC)
esumes Operation of theV1–V6 Outputs to FinishTheir Pattern
Hds theVV6 Outputs atTheir Current Levels (Static DC)
Reseperation of theV1–V6 Outputs to FinishTheir Pattern
START POSITION OF VPROGRAMMABLE IN V-SEQUENCE REGISTERS
HD
4
V1
V2
1
2
3
V6
2
3
PROGRAMMABLE SETTINGS FOR EACH V-PATTERN:
1. START POLARITY
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION (3RD TOGGLE POSITION ALSO AVAILABLE, 4TH TOGGLE POSITION AVAILABLE FOR V-PATTERN GROUPS 8 AND 9)
4. TOTAL PATTERN LENGTH FOR ALL V1-V6 OUTPUTS
Figure 16. Vertical Pattern Group Programmability
REV. 0
Vertical Sequences (VSEQ)
even lines, separate values may be used for each register (see
theV-Sequence Line Alternation section).TheVPATSTART
register specifies where in the line theV-pattern group will start.
TheVMASK register is used in conjunction with the FREEZE/
RESUME registers to enable optional masking of theV-outputs.
RESUME2 registers can be enabled.
The vertical sequences are created by selecting one of the 10
V-pattern groups and adding repeats, start position, and hori-
zontal clamping and blanking information. Up to 10V-sequences
can be programmed, each using the registers shown inTableVI.
Figure 17 shows how the different registers are used to generate
eachV-sequence.
TheVPATSEL register selects whichV-pattern group will be
used in a givenV-sequence.The basicV-pattern group can have
repetitions added, for high speed line shifts or line binning, by
using theVPATREPO andVPATREPE registers. Generally, the
same number of repetitions are programmed into both registers,
but if a different number of repetitions is required on odd and
The line length (in pixels) is programmable using the HDLEN
registers. EachV-sequence can have a different line length to
accommodate various image readout techniques.The maximum
number of pixels per line is 4096. Note that the last line of the
field is separately programmable using the HDLAST register
located in the Field register section.
TableVI.V-Sequence Registers (seeTables III and IV for HBLK, CLPOB, BLK ters)
Register
Length
Range
Description
0–9V-Pattern Group #
SelectedV-Pattern Group foEachequence.
Enables the Masking of V1–V6 Outpuat the Locations Specified by
the FREEZE/RESUMRegisters. 0 = NMask, 1 = Enable
FREEZE1/RESUM1, 2 = able FREEZE2/RESUME2, 3 = Enable
0–4095 # of Repeats
0–4095 # of Repeats
Number of Repetitior theV-tern Group for Odd Lines.
If no odd/even alternatios reired, set toVPATREPE.
Numbeof Repetitions for V-Pattern Group for Even Lines.
If no odden alternation is required, set toVPATREPO.
Start Positioor the ectedV-Pattern Group.
LengoLines in EachV-Sequence.
1
HD
2
3
4
4
V1–V6
VPAT REP 3
VPAT REP 2
UP
CLPOB
PBLK
5
HBLK
PRSETTINGS FOR EACH V-SEQUENCE:
1. STON IN THE LINE OF SELECTED V-PATTERN GROUP
2. HD LINE LENGTH
3. V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP
4. NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED)
5. START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS
6. MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL
Figure 17. V-Sequence Programmability
REV. 0
Complete Field: CombiningV-Sequences
ing any region.The SCP registers create the line boundaries for
each region.TheVDLEN register specifies the total number of
lines in the field.The total number of pixels per line (HDLEN) is
specified in theV-sequence registers, but the HDLAST register
specifies the number of pixels in the last line of the field.The
VPATSECOND register is used to add a secondV-pattern group
to theV1–6 outputs during the sensor gate (VSG) line.
After the V-sequences have been created, they are combined to
create different readout fields. A field consists of up to seven
different regions, and within each region a different V-sequence
can be selected. Figure 18 shows how the sequence change posi-
tions (SCP) designate the line boundary for each region, and
the VSEQSEL registers then select which V-sequence is used
during each region. Registers to control the VSG outputs are also
included in the Field registers.
The SGMASK register is used to enable or disable each indi-
vidualVSG output.There is a single bit for eachVSG output;
setting the bit high will mask the output, setting it low will enable
the output.The SGPAT register assigns one of the four different
SG patterns to eachVSG output.The individual SG patterns are
created separately using the SG attern registers.The SGLINE1
register specifies which line ihe field will contain theVSG out-
puts.The optional SGLINregistallows the sameVSG pulses
to be repeated on a diffent l
TableVII summarizes the registers used to create the different
fields. Up to six different fields can be preprogrammed using all
of the Field registers.
TheVEQSEL registers, one for each region, select which of the
10V-sequences will be active during each region.The SWEEP
registers are used to enable SWEEP mode during any region.
The MULTI registers are used to enable Multiplier mode dur-
TableVII. Field Registers
Register
Length
Range
Description
VSEQSEL
0–9V-Sequence #
High/Low
High/Low
SelectedV-quence r Each Region in the Field.
Enables SwMe for Each Region,When Set High.
Enables MultiMode r Each Region,When Set High.
Sequence Changosin for Each Region.
0–9V-Pattern Group #
High/Low, EachVS
Leth in Pixels f the Last HD Line in Each Field.
SelecV-Patn Group for Second Pattern Applied During VSG Line.
t Higask Each IndividualVSG Output.VSG1 [0],VSG2 [1],
3 [2],VSG4 [3],VSG5 [4].
0–3 Pattern #, Ets theVSG Pattern Number for EachVSG Output.VSG1 [1:0],
2 [3:2],VSG3 [5:4],VSG4 [7:6],VSG5 [9:8].
Selects a Second Line in the Field to Repeat theVSG Signals.
SCP 2
SCP 6
SCP 3
SCP 4
SCP 5
VD
HD
GION 0
REGION 2
REGION 4
REGION 6
REGION 3
REGION 5
V1–V6
VSEQSEL1
SGLINE1
VSEQSEL5
VSEQSEL6
VSEQSEL2
VSEQSEL3
VSEQSEL4
VSG
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP1–6) DEFINE EACH OF THE 7 REGIONS IN THE FIELD
2. VSEQSEL0–6 SELECTS THE DESIRED V-SEQUENCE (0–9) FOR EACH REGION.
3. SGLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD WILL CONTAIN THE SENSOR GATE PULSE(S)
Figure 18. Complete Field Is Divided into Regions
REV. 0
Generating Line Alternation forV-Sequence and HBLK
During low resolution readout, some CCDs require a different
support this by using theVPATREPO andVPATREPE regis-
ters.This allows a different number of VPAT repetitions to be
programmed on odd and even lines. Note that only the number
of repeats can be different in odd and even lines, but theVPAT
group remains the same.
SecondV-Pattern Group duringVSG Active Line
Most CCDs require additional vertical timing during the sensor
gate line.The AD9995 supports the option to output a second
V-pattern group forV1–V6 during the line when the sensor gates
VSG1–VSG5 are active. Figure 20 shows a typicalVSG line,
includes two separate sets of V-pattern groups forV1–V6.The
pattern group at the start of theVSG line is selected in the same
manner as the other regions, using the appropriateVSEQSEL
register.The secondV-pattern group, unique to theVSG line, is
selected using theVPATSECOND register, located with the Field
registers.The start position of the secondVPAT group uses the
VPATLEN register from the selectedVPAT registers. Because
theVPATLEN register is used as the rt position and not as the
VPAT length, it is not possible to pgram multiple repetitions
for the secondVPAT group.
Additionally, the HBLK signal can also be alternated for odd
and even lines. When the HBLKALT register is set high, the
HBLK TOG1 and TOG2 positions will be used on odd lines
and the TOG3–TOG6 positions will be used on even lines.
This allows the HBLK interval to be adjusted on odd and even
Figure 19 shows an example ofVPAT repetition alternation and
HBLK alternation used together. It is also possible to useVPAT
and HBLK alternation separately.
HD
VPATREPO = 2
VPATREPE = 5
VPATREPO = 2
V1
V2
V6
TOG1
TOG2
TOG1
TOG2
TOG4
HBLK
NOTES
1. THE NUMBER OF REPEATS FOR THE V-PATTEROUP MAY BE ALTERED ON ODD AND EVEN LINES.
2. THE HBLK TOGGLE POSITIONS MAY BE ALTBETWEEN DD EVEN LINES IN ORDER TO GENERATE DIFFERENT HBLK PATTERNS FOR ODD/EVEN LINES.
Figure 19. lternation of VPAT Repetitions and HBLKToggle Positions
START POSITION FOR 2ND VPAT GROUP
USES VPATLEN REGISTER
HD
VSG
V1
V2
V6
2ND VPAT GROUP
Figure 20. Example of Second VPAT Group during Sensor Gate Line
REV. 0
Sweep Mode Operation
region occupies 23 HD lines. After the Sweep mode region is
completed, in the next region, normal sequence operation will
resume. When using Sweep mode, be sure to set the region
boundaries (using the sequence change positions) to the appro-
priate lines to prevent the Sweep operation from overlapping the
next V-sequence.
The AD9995 contains an additional mode of vertical timing
operation called Sweep mode.This mode is used to generate a
large number of repetitive pulses that span multiple HD lines.
One example of where this mode is needed is at the start of the
CCD readout operation. At the end of the image exposure but
before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge.This
can be accomplished by quickly shifting out any charge using a
long series of pulses from theV1–V6 outputs. Depending on the
vertical resolution of the CCD, up to 2,000 or 3,000 clock cycles
will be needed to shift the charge out of each vertical CCD line.
This operation will span across multiple HD line lengths. Nor-
mally, the AD9995’s vertical timing must be contained within
one HD line length, but when Sweep mode is enabled, the HD
boundaries will be ignored until the region is finished.To enable
Sweep mode within any region, program the appropriate
SWEEP register to high.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
may be configured into a multiplier region. This mode uses
the V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than a single HD line length.
The start polarity and toggle pitions are still used in the same
manner as the standardVPAgroup ogramming, but the
VPATLEN is used differentnstd of using the pixel counter
(HD counter) to specthe topositioocations (VTOG1,
2, 3) of theVPAT gp, theVPAEN s multiplied with the
VTOG position allvery long pes to be generated.To cal-
culate the exact toggle pion, counted in pixels after the start
position, uthe equation
Figure 21 shows an example of Sweep mode operation. The
number of vertical pulses needed will depend on the vertical
resolution of the CCD. The V1–V6 output signals are gener-
ated using the V-pattern registers (shown in Table VII). A single
pulse is created using the polarity and toggle position registers.
The number of repetitions is then programmed to match the
number of vertical shifts required by the CCD. Repetitions are
programmed in the V-sequence registers using the VPATREP
registers. This produces a pulse train of the appropriate length.
Normally, the pulse train would be truncated at the end of th
HD line length, but with Sweep mode enabled for this r
the HD boundaries will be ignored. In Figure 21, the
ltiplier odeTogglePosition =VTOG ×VPATLEN
Because e TOG rester is multiplied by VPATLEN,
the resolutof thoggle position placement is reduced. If
VPATLEN = e toggle position accuracy is now reduced
to 4-pixel steps instead of single pixel steps. Table VIII sum-
arizes hothe VPAT group registers are used in Multiplier
me oration. In Multiplier mode, the VPATREPO and
VPAEPE registers should always be programmed to the same
value as the highest toggle position.
VD
CP 1
SCP 2
HD
LINE 0
LINE 1
LINE 2
LINE 24
LINE 25
V1–V6
REG
REGION 1: SWEEP REGION
REGION 2
Figur1. Example of Sweep Region for High Speed Vertical Shift
TableVIII. Multiplier Mode Register Parameters
Register
Length
Range
Description
MULTI
VPOL
VTOG1
VTOG2
VTOG3
VPATLEN
VPATREP
1b
1b
12b
12b
12b
10b
12b
High/Low
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
0–4095 Pixel Location
0–1023 Pixels
High enables Multiplier mode.
Starting Polarity of V1–V6 Signal in Each VPAT Group.
FirstToggle Position forV1–V6 Signal in EachVPAT Group.
SecondToggle Position forV1–V6 Signal in EachVPAT Group.
ThirdToggle Position forV1–V6 Signal in EachVPAT Group.
Used as Multiplier Factor forToggle Position Counter.
0–4096
VPATREPE/VPATREPO should be set to the same value asTOG2 or 3.
REV. 0
The example shown in Figure 22 illustrates this operation.The
first toggle position is 2, and the second toggle position is 9. In
non-Multiplier mode, this causes theV-sequence to toggle at
pixel 2 and then pixel 9 within a single HD line. However, toggle
positions are now multiplied by theVTPLEN = 4, so the first
toggle occurs at pixel count 8 and the second toggle occurs at
pixel count 36. Sweep mode has also been enabled to allow the
toggle positions to cross the HD line boundaries.
Table IX contains the summary of the VSG pattern registers. The
AD9995 has five VSG outputs, VSG1–VSG5. Each of the out-
puts can be assigned to one of four programmed patterns by using
the SGPATSEL registers. Each pattern is generated in a similar
manner as the V-pattern groups, with a programmable start polar-
ity (SGPOL), first toggle position (SGTOG1), and second toggle
position (SGTOG2). The active line where the VSG1–VSG5
pulses occur is programmable using the SGLINE1 and SGLINE2
registers. Additionally, any of the VSG1–VSG5 pulses may be
individually disabled by using the SGMASK register. The individ-
ual masking allows all of the SG patterns to be preprogrammed,
and the appropriate pulses for the different fields can be separately
enabled. For maximum flexibility, the GPATSEL, SGMASK,
and SGLINE registers are separateprogrammable for each field.
More detail is given in the Come Fielection.
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gates (VSG) are used
to transfer the pixel charges from the light-sensitive image area
into light-shielded vertical registers. From the light-shield verti-
cal registers, the image is then read out line-by-line by using the
vertical transfer pulses V1–V6 in conjunction with the high speed
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGS
HD
5
5
3
VPATLEN
1
1
2
2
3
3
4
4
1
5
2
6
3
7
4
8
1
9
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
3
4
1
3
4
1
2
3
4
1
2
3
4
PIXEL
NUMBER
10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 228 29 30 31 32 33 34 35 36 37 38 39 40
4
4
V1–V6
1
2
2
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES
1. START POLARITY (ABOVE: STARTPOL
2. FIRST, SECOND, AND THIRD TOGGLSONS (ABO2, VTOG2 = 9)
3. LENGTH OF VPAT COUNTER (ABOVPATLEN = 4). THIS IE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4. TOGGLE POSITIONS OCCUR AT LATION EQO (VTOG VPATLEN)
5. IF SWEEP REGION IS ENABLED, TV-PULSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE
Figure 22ample of Multier Region for Wide Vertical PulseTiming
Tablern Registers (also see Field Registers inTableVII)
Register
Range
Description
SGPOL
SGTOG1
SGTOG2
High/Low
0–4095 Pixel Location
0–4095 Pixel Location
Sensor Gate Starting Polarity for SG Pattern 0–3
FirstToggle Position for SG Pattern 0–3
SecondToggle Position for SG Pattern 0–3
VD
HD
4
VSG PATTERNS
1
2
3
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1. START POLARITY OF PULSE
2. FIRST TOGGLE POSITION
3. SECOND TOGGLE POSITION
4. ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN)
Figure 23. Vertical Sensor Gate Pulse Placement
REV. 0
MODE Register
startup. Then, during camera operation, the MODE register
would select which field timing would be active, depending on
how the camera was being used.
The MODE register is a single register that selects the field tim-
ing of the AD9995.Typically, all of the field,V-sequence, and
V-pattern group information is programmed into the AD9995
at startup. During operation, the MODE register allows the user
to select any combination of field timing to meet the current
requirements of the system.The advantage of using the MODE
register in conjunction with preprogrammed timing is that it
greatly reduces the system programming requirements during
camera operation. Only a few register writes are required when
the camera operating mode is changed, rather than having to
write in all of the vertical timing information with each camera
mode change.
Table X shows how the MODE register bits are used. The three
MSBs, D23–D21, are used to specify how many total fields will
be used. Any value from 1 to 7 can be selected using these three
bits. The remaining register bits are divided into 3-bit sections to
select which of the six fields are used and in which order. Up to
seven fields may be used in a single MODE write. The AD9995
will start with the Field timing specified by the first Field bits,
and on the next VD will switch to the timing specified by the
second Field bits, and so on.
After completing the total nuer of fields specified in Bits
D23 to D21, the AD9995 l repeay starting at the first
Field again. This will contiuna new write to the MODE
register occurs. Figur24 shoxample ODE register set-
tings for different configurats.
A basic still camera application might require five different
fields of vertical timing: one for draft mode operation, one for
autofocusing, and three for still image readout. All of the reg-
ister timing information for the five fields would be loaded at
Table X. MODE Register Data Bit Breakdn (D23 = MS
1 = 1st Field Only
6, 7 = Invalid 6, 7 = Invalid 6, 7 = Inva6, 7 = Invalid 6, 7 = Invalid 6, 7 = Invalid 6, 7 = Invalid
EXAMPLE 1:
TOTAL FIELDS = 3, 1ST FIELD = FIELD 1, 3RD FIELD = FIELD 2
MODE REGISTER CONTENTS =
FI1
FIELD 0
ST FIELD = FIELD 3, 2ND FIELD = FIELD 4
TENTS = 0x400023
ELD 4
AMPLE 3:
OTAL FIELDS = 4, 1ST FIELD = FIELD 5, 2ND FIELD = FIELD 1, 3RD FIELD = FIELD 4, 4TH FIELD = FIELD 2
MODE REGISTER CONTENTS = 0x80050D
FIELD 2
FIELD 1
FIELD 4
FIELD 5
Figure 24. Using the MODE Register to Select FieldTiming
REV. 0
Region 1 consists of only two lines, and uses standard single line
vertical shift timing.The timing of this region area will be the
same as the timing in Region 3.
To better understand how the AD9995’s vertical timing generation
is used, consider the example CCD timing chart in Figure 25. This
particular example illustrates a CCD using a general 3-field
readout technique. As described in the Field section, each
readout field should be divided into separate regions to per-
form each step of the readout.The sequence change positions
(SCP) determine the line boundaries for each region, and the
VSEQSEL registers will then assign a particular V-sequence to
each region.The V-sequences will contain the specific timing
information required in each region:V1–V6 pulses (using VPAT
groups), HBLK/CLPOB timing, and VSG patterns for the SG
Region 2 is the sensor gate line, where the VSG pulses transfer the
image into the vertical CCD registers. This region may require the
use of the second V-pattern group for SG active line.
Region 3 also uses the standard single line vertical shift timing,
the same timing as Region 1.
In summary, four regions are required in each of the three fields.
The timing for Regions 1 and 3 is essentially the same, reducing
the complexity of the register programming.
Other registers will need to be used ring the actual readout
operation, such as the MODE reter, shuer control registers
(TRIGGER, SUBCK,VSUB, MHUTTROBE), and AFE
gain register.These registerwill blained ither examples.
This particular timing example requires four regions for each
of the three fields, labeled Region 0, Region 1, Region 2, and
Region 3. Because the AD9995 allows up to six individual fields
to be programmed, the Field 0, Field 1, and Field 2 registers can
be used to meet the requirements of this timing example. The
four regions for each field are very similar in this example, but
the individual registers for each field allow flexibility to accom-
modate other timing charts.
Important Note about nal Polariti
When programming e A995 to genate the V1–V6,
VSG1–VSG5, and SUBCK als, it is important to note that
the V-driver ciuit usually invethese signals. Carefully check
the required iming sgnals needed at the input and output of
the V-drivcircuieing used and adjust the polarities of the
AD9995’s ouaccordly.
Region 0 is a high speed vertical shift region. Sweep mode can be
used to generate this timing operation, with the desired number
of high speed vertical pulses needed to clear any charge from the
CCD’s vertical registers.
REV. 0
n
3
n –
2 1
1 8
1 5
1 2
9
6
3
n –
n –
4
2 0
1 7
1 4
1
5
2
2
5
n –
n –
1 6
1 3
1 0
7
4
1
Figure 25. CCDTiming Example: Dividing Each Field into Regions
REV. 0
High Precision Shutter Operation
The CCD image exposure time is controlled by the substrate
clock signal (SUBCK), which pulses the CCD substrate to clear
out accumulated charge.The AD9995 supports three types of
electronic shuttering: normal shutter, high precision shutter,
and low speed shutter. Along with the SUBCK pulse placement,
the AD9995 can accommodate different readout configurations
to further suppress the SUBCK pulses during multiple field
readouts.The AD9995 also provides programmable outputs to
control an external mechanical shutter (MSHUT), strobe/flash
(STROBE), and the CCD bias select signal (VSUB).
High precision shuttering is used in the same manner as nor-
mal shuttering, but uses an additional register to control the
very last SUBCK pulse. In this mode, the SUBCK still pulses
once per line, but the last SUBCK in the field will have an
additional SUBCK pulse whose location is determined by the
SUBCK2TOG register, as shown in Figure 27. Finer resolution
of the exposure time is possible using this mode. Leaving the
SUBCK2TOG register set to max value (0xFFFFFF) will disable
the last SUBCK pulse (default setting).
Low Speed Shutter Operation
Normal Shutter Operation
Normal and high precision shutter operations are used when
the exposure time is less than one fid long. For long exposure
times greater than one field interl, low seed shutter opera-
tion is used. The AD9995 uses eparexposure counter to
achieve long exposure timeThe ber of fis for the low
speed shutter operation specified ihe EOSURE register
(Addr. 0x62). As shoFigure 28, thutter mode will
suppress the SUBCK and VG outputs for up to 4095 fields
(VD periods). Te VD and Hutputs may be suppressed
during the exsure period by prramming the VDHDOFF
register to
By default, the AD9995 is always operating in the normal shutter
configuration in which the SUBCK signal is pulsing in every VD
field (see Figure 26). The SUBCK pulse occurs once per line,
and the total number of repetitions within the field will determine
the length of the exposure time. The SUBCK pulse polarity
and toggle positions within a line are programmable using the
SUBCKPOL and SUBCK1TOG registers (see Table XI).
The number of SUBCK pulses per field is programmed in the
SUBCKNUM register (Addr. 0x63).
As shown in Figure 26, the SUBCK pulses will always begin
in the line following the SG active line, which is specified in
the SGACTLINE registers for each field.The SUBCKPOL,
SUBCK1TOG, SUBCK2TOG, SUBCKNUM, and SUBCK-
SUPPRESS registers are updated at the start of the line after
the sensor gate line, as described in the Updating New Register
To generate speed shter operation, it is necessary to trig-
ger the start of long posure by writing to theTRIGGER
register bit D3.Whis bit is set high, the AD9995 will begin
exposure operation at the nextVD edge. If a value greater than
zerspecified the EXPOSURE register, the AD9995 will
supprethe UBCK output on subsequent fields.
VD
HD
VSG
tEX
tEXP
SUBCK
SUBCK PROGRAMMABLE
1. PULSE PSING TL REGISTER.
2. NUMBWITHIN LD USING THE SUBCKNUM REGISTER (SUBCKNUM = 3 IN THE ABOVE FIGURE).
3. PIXELSE WITHE LINE AND PULSEWIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTER.
Figure 26. Normal Shutter Mode
VD
HD
VSG
tEXP
tEXP
SUBCK
NOTES
1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE.
2. LOCATION OF 2ND PULSE IS FULLY PROGRAMMABLE USING THE SUBCK2 TOGGLE POSITION REGISTER.
Figure 27. High Precision Shutter Mode
REV. 0
If the exposure is generated using theTRIGGER register and the
EXPOSURE register is set to zero, the behavior of the SUBCK
will not be any different than the normal shutter or high precision
shutter operations, in which theTRIGGER register is not used.
CCD frame readout mode will generally require two additional
fields of SUBCK suppression (READOUT = 2). A 3-field,
6-phase CCD will require three additional fields of SUBCK sup-
pression after the readout begins (READOUT = 3).
SUBCK Suppression
If the SUBCK output is required to start back up during the last
field of readout, simply program the READOUT register to one
Normally, the SUBCKs will begin to pulse on the line following
the sensor gate line (VSG).With some CCDs, the SUBCK pulse
needs to be suppressed for one or more lines following theVSG
line.The SUBCKSUPPRESS register allows for suppression of
the SUBCK pulses for additional lines following theVSG line.
Like the exposure operation, the readout operation must be trig-
gered by using theTRIGGER register.
Using theTRIGGER Register
Readout after Exposure
As described previously, by default the AD9995 will output the
SUBCK andVSG signals on evefield.This works well for
continuous single field exposand readout operations, such
as the CCD’s live preview de. Hoever, if the CCD requires
a longer exposure time, or if lte readofields are needed,
theTRIGGER registis needeinitiaspecific exposure and
readout sequences
After the exposure, the readout of the CCD data occurs, beginning
with the sensor gate (VSG) operation. By default, the AD9995 is
generating the VSG pulses in every field. In the case where only a
single exposure and single readout frame are needed, such as the
CCD’s preview mode, the VSG and SUBCK pulses can be oper-
ating in every field.
However in many cases, during readout the SUBCK output
needs to be further suppressed until the readout is completed.
The READOUT register specifies the number of additional
fields after the exposure to continue the suppression of
SUBCK. READOUT can be programmed for zero to seven
additional fields, and should be preprogrammed at startup,
not at the same time as the exposure write. A typical interlaced
Typically, the exposure readout bits in theTRIGGER
register are sed together.s will initiate a complete exposure-
plus-reaut operation. Once he exposure has been completed,
the reout wilutomatically occur.The values in the EXPO-
SURE d ADOUregisters will determine the length of
each opern.
TRIGGER
EXPOSURE
VD
VSG
tEXP
SUBCK
NOTES
1. SUBCK MAY BE MULTIPLE FIELDS BY PROGRAMMING THE EXPOSURE REGISTER GREATER THAN ZERO.
2. ABOVE EXAM1.
3. TRIGGER REGISED TO START THE LOW SPEED EXPOSURE
4. VD/HD OUTPUTS ESSED USING THE VDHDOFF REGISTER = 1.
Fig. Low Speed Shutter Mode Using EXPOSURE Register
Table XI. Shutter Mode Register Parameters
Register
gth
Range
Description
TRIGGER
5b
On/Off for Five Signals
Trigger forVSUB [0], MSHUT [1], STROBE [2], Exposure [3],
and Readout Start [4]
READOUT
EXPOSURE
3b
12b
0–7 # of Fields
0–4095 # of Fields
Number of Fields to Suppress SUBCK after Exposure
Number of Fields to Suppress to SUBCK andVSG during
ExposureTime (Low Speed Shutter)
VDHDOFF
1b
1b
24b
24b
On/Off
High/Low
0–4095 Pixel Locations
0–4095 Pixel Locations
DisableVD/HD Output during Exposure (1 = On, 0 = Off)
SUBCK Start Polarity for SUBCK1 and SUBCK2
Toggle Positions for First SUBCK Pulse (Normal Shutter)
Toggle Positions for Second SUBCK Pulse in Last Line
(High Precision)
SUBCKPOL
SUBCK1TOG
SUBCK2TOG
SUBCKNUM
SUBCKSUPPRESS12b
12b
1–4095 # of Pulses
0–4095 # of Pulses
Total Number of SUBCKs per Field at One Pulse per Line
Number of Lines to Further Suppress SUBCK after theVSG Line
Register is notVD updated, but is updated at the start of line after sensor gate line.
REV. 0
It is possible to independently trigger the readout operation
without triggering the exposure operation.This will cause the
readout to occur at the nextVD, and the SUBCK output will be
suppressed according to the value of the READOUT register.
the field.VSUB will remain active until the end of the image
readout. In Mode 1, the VSUB is not activated until the start of
When this bit is set high, theVSUB output will remain on (active)
time, set this bit back to low.
TheTRIGGER register is also used to control the STROBE,
MSHUT, andVSUB signal transitions. Each of these signals are
individually controlled, although they will be dependent on the
triggering of the exposure and readout operation.
MSHUT and STROBE Control
See Figure 32 for a complete example of triggering the exposure
and readout operations.
MSHUT and STROBE operation is shown in Figures 30, 31,
and 32.Table XII shows the register parameters for controlling
the MSHUT and STROBE outputs.The MSHUT output is
switched on with the MSHUTON regters, and will remain on
until the location specified in the MHUTOFF registers.The
location of MSHUTOFF is fully rogramable to anywhere
within the exposure period, usine F(field), LN (line), and
PX (pixel) registers.The SROBE e is defid by the on and
VSUB Control
The CCD readout bias (VSUB) can be programmed to accom-
modate different CCDs. Figure 29 shows two different modes
that are available. In Mode 0,VSUB goes active during the field
of the last SUBCK when the exposure begins.The On position
(rising edge in Figure 29) is programmable to any line within
TRIGGER
VSUB
VD
VSG1
tEXP
REUT
SUBCK
2
MODE 0
4
VSUB
1
3
VSUB OPERATION:
1. ACTIVE POLARITY IS POLARITY (ABOVE AMLE IS VSUB GH).
2. ON POSITION IS PROGRAMMABLE. MO0 TURNS ON AT THE SART OF EXPOSURE, MODE 1 TURNS ON AT THE START OF READOUT.
3. OFF POSITION OCCURS AT END OF RDOUT.
4. OPTIONAL VSUB KEEP-ON MODE WILEAVE CTIVE AT THE END OF READOUT.
Figure 29SUB Programmability
VD
VSG
tEXP
SUBCK
MSHUT
2
1
3
MSHUT PROGRAMMABLE SETTINGS:
1. ACTIVE POLARITY.
2. ON POSITION IS VD UPDATED AND MAY BE SWITCHED ON AT ANY TIME.
3. OFF POSITION CAN BE PROGRAMMED ANYWHERE FROM THE FIELD OF LAST SUBCK UNTIL THE FIELD BEFORE READOUT.
Figure 30. MSHUT Output Programmability
REV. 0
off positions. STROBON_FD is the field in which the STROBE
is turned on, measured from the field containing the last SUBCK
before exposure begins.The STROBON_ LN PX register gives
the line and pixel positions with respect to STROBON_FD.The
STROBE off position is programmable to any field, line, and
pixel location with respect to the field of the last SUBCK.
The same limitation applies to the triggering of the MSHUT
signal.There must be at least one idle field after the completion
of the MSHUT OFF operation before another MSHUT OFF
operation may be programmed.
TheVSUB trigger requires two idle fields between exposure/
readout operations in order to ensure properVSUB on/off trig-
gering. If theVSUB signal is not required to be turned on and
off in between each successive exposure/readout operation, this
limitation can be ignored.TheVSUB Keep-On mode is useful
when successive exposure/readout operations are required.
TRIGGER Register Limitations
While theTRIGGER register can be used to perform a complete
exposure and readout operation, there are limitations on its use.
Once an exposure-plus-readout operation has been triggered,
another exposure/readout operation cannot be triggered right
away.There must be at least one idle field (VD intervals) before
the next exposure/readout can be triggered.
TRIGGER
EXPOSURE
AND STROBE
VD
VSG
tEXP
SUBCK
STROBE
1
3
STROBE PROGRAMMABLE SETTINGS:
1. ACTIVE POLARITY.
2. ON POSITION IS PROGRAMMABLE IN ANY FIELURE TIME (WITH RESPECT TO THE FIELD CONTAINING THE LAST SUBCK).
3. OFF POSITION IS PROGRAMMABLE IN ANY FIESURE TIME.
F31. Stput Programmability
Table XII.VSUB, MHUT, and STROBE Register Parameters
Register
Length
nge
Description
VSUBMODE[0]
VSUBMODE[1]
1b
1b
w
VSUB Mode (0 = Mode 0, 1 = Mode 1) (See Figure 29).
VSUB Keep-On Mode.VSUB will stay active after readout
when set high.
VSUBON[11:0]
VSUBON[12]
MSHUTPOL[0]
MSHUTPOL[1]
MSHUTON
MSHUTOFF_FD
MSHUTOFF_LNPX 24b
12b
95 Line Location
High/Low
High/Low
VSUB On Position. Active starting in any line of field.
VSUB Active Polarity.
MSHUT Active Polarity.
MSHUT Manual Enable (1 = Active or Open).
MSHUT On Position Line [11:0] and Pixel [23:12] Location.
Field Location to Switch Off MSHUT (Inactive or Closed).
Line/Pixel Position to Switch Off MSHUT (Inactive or Closed).
STROBE Active Polarity.
On/Off
0–4095 Line/Pix Location
0–4095 Field Location
0–4095 Line/Pix Location
High/Low
STROBPOL
1b
STROBON_FD
STROBON_LNPX
STROBOFF_FD
STROBOFF_LNPX
12b
24b
12b
24b
0–4095 Field Location
0–4095 Line/Pix Location
0–4095 Field Location
0–4095 Line/Pix Location
STROBE ON Field Location, with Respect to Last SUBCK Field.
STROBE ON Line/Pixel Position.
STROBE OFF Field Location, with Respect to Last SUBCK Field.
STROBE OFF Line/Pixel Position.
REV. 0
AD9995
EXPOSURE AND READOUT EXAMPLE
SERIAL
WRITES
1
9
10
10
2
6
7
8
VD
STILL IMAGE READOUT
VSG
tEXP
SUBCK
4
STROBE
5
10
MSHUT
OPEN
OP
MECHANICAL
SHUTTER
CLOSED
3
1
MODE 0
VSUB
MODE 1
CCD
OUT
DRAFT IMAGE
DRAFT IMAGE
STILL IMAGE 1ST FIELD
STILL IMAGD FIELD
STILL IMAGE 3RELD
DRAFT IMAGE
Figure 32. Example of Exposure and Still Image Readout Using hter Signls and Mode Register
MSHUT output turns off at the location specified in the
SHUTFF registers (Addr. 0x6B and 0x6C).
1. Write to the READOUT register (Addr. 0x61) to specify
the number of fields to further suppress SUBCK while the
CCD data is read out. In this example, READOUT = 3.
. ThtVD falling edge will automatically start the first
readout field.
Write to the EXPOSURE register (Addr. 0x62) to sp
the number of fields to suppress SUBCK andVSG o
during exposure. In this example, EXPOSURE = 1.
The nextVD falling edge will automatically start the second
readout field.
Write to theTRIGGER register (Addr. 0x6to enable the
STROBE, MSHUT, andVSUB signals, d to sta
exposure/readout operation.To trigger all e evenas
in Figure 32), set the registerTRIGGER = 31. Readouwill
automatically occur after the exeriod is d.
8. The nextVD falling edge will automatically start the third
readout field.
9. Write to the MODE register to reconfigure the single Draft
mode field timing.
Write to the MSHUTON register (Addr. 0x6A) to open the
mechanical shutter.
Write to the MODE register configure the
next five fields.The first two fisure are the
same as the current draft mode fie following
three fields are the eadods.The registers
for the Draft mothree readout fields have
already been pro
10. VD/HD falling edge will update the serial write from 9.
VSG outputs return to Draft mode timing.
SUBCK output resumes operation.
MSHUT output returns to the on position (active or open).
VSUB output returns to the off position (inactive).
2. VD/HD falling edthe serial writes from 1.
3. IfVSUB mode = 0 (Addr. 0x67),VSUB output turns on at
the line specified in theVSUBON register (Addr. 0x68).
4. STROBE output turns on and off at the location specified
in the STROBEON and OFF registers (Addr. 0x6E to
Addr. 0x71).
–30–
REV. 0
AD9995
1.0F 1.0F
REFB REFT
1.0V
2.0V
DC RESTORE
1.5V
AD9995
INTERNAL
V
REF
DOUT
PHASE
SHP
SHD
2V FULL SCALE
6dB–42dB
VGA
0.1F
12
OUTPUT
DATA
LATCH
CCDIN
12-BIT
ADC
DOUT
CDS
OPTICAL BLACK
CLAMP
DAC
VGA GAIN
REGISTER
LK
CLPOB
8
DIGITAL
FILTER
DOUT
SHD PHASE
LAMP LEVEL
EGISTER
CLPOB PBLK
SHP
PRECISION
TIMING
GENERATION
V-H
TIMING
GENERATION
Figure 33. Analog Front EFunctional Block Diagram
ANALOG FRONT END DESCRIPTION AND OPE
The AD9995 signal processing chain is shown in Fig
Each processing step is essential in achieving a high qua
from the raw CCD pixel data.
with e ADC full-scale range of 2 V. When compared to 1 V
full-scale systems, the equivalent gain range is 0 dB to 36 dB.
TheVGA gain curve follows a linear-in-dB characteristic. The
exactVGA gain can be calculated for any gain register value by
using the equation
DC Restore
To reduce the large dc offset of the CCoutpg, a dc
restore circuit is used with an external 0.1 series cpling
capacitor. This restores the dc lethe CCD signto
approximately 1.5 V, to be cowith the V supply
voltage of the AD9995.
Gain dB = 0.0351× Code +6dB
where the code range is 0 to 1023.
42
Correlated Double Sampler
36
30
24
18
The CDS circuit samch CCwice to extract the
video information frequcy noise. The timing
shown in Figure the two internally generated
CDS clocks, SHP sed to sample the reference
level and level of th, respectively. The placement of
the SHP and SHD samedges is determined by the setting
of the SAMPCONTROL register located at Addr. 0x63. Place-
ment of these two clock signals is critical in achieving the best
performance from the CCD.
12
6
Variable Gain Amplifier
TheVGA stage provides a gain range of 6 dB to 42 dB, program-
mable with 10-bit resolution through the serial digital interface.
The minimum gain of 6 dB is needed to match a 1V input signal
0
127
255
383
511
639
767
895
1023
VGA GAIN REGISTER CODE
Figure 34. VGA Gain Curve
REV. 0
–31–
AD9995
A/D Converter
The CLPOB pulse should be placed during the CCD’s optical
black pixels. It is recommended that the CLPOB pulse dura-
tion be at least 20 pixels wide to minimize clamp noise. Shorter
pulsewidths may be used, but clamp noise may increase, and the
ability to track low frequency variations in the black level will
be reduced. See the Horizontal Clamping and Blanking section
and the HorizontalTiming Sequence Example section for timing
examples.
The AD9995 uses a high performance ADC architecture
optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB.The ADC
uses a 2V input range. SeeTPC 2 andTPC 3 for typical linearity
and noise performance plots for the AD9995.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel inter-
val on each line, the ADC output is compared with a fixed black
level reference, selected by the user in the Clamp Level register.
The value can be programmed between 0 LSB and 255 LSB in
256 steps. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamp-
ing is used during the postprocessing, the AD9995 optical black
clamping may be disabled using Bit D2 in the OPRMODE regis-
ter.When the loop is disabled, the Clamp Level register may still
be used to provide programmable offset adjustment.
Digital Data Outputs
The AD9995 digital output data is latched using the DOUT
PHASE register value, as shown in Figure 33. Output data timing
is shown in Figure 8a. It is also possible to leave the output latches
transparent so that the data outputs avalid immediately from
the A/D converter. Programming e AFE ONTROL register bit
D4 to 1 will set the output latchranspent. The data outputs
can also be disabled (three-sted) ting the FE CONTROL
register Bit D3 to 1.
The data output codg is rmally straigbinary, but the
coding my be changed to graoding by setting the AFE CON-
TROL register it D5 to 1.
–32–
REV. 0
AD9995
POWER-UP AND SYNCHRONIZATION
11. Write a 1 to the OUT_CONTROL register (Addr. 0x11 in
Bank 1). This will allow the outputs to become active after
the next SYNC rising edge.
Recommended Power-Up Sequence for Master Mode
When the AD9995 is powered up, the following sequence is
recommended (refer to Figure 35 for each step). Note that a
SYNC signal is required for Master mode operation. If an exter-
nal SYNC pulse is not available, it is also possible generate an
internal SYNC pulse by writing to the SYNCPOL register, as
described in the next section.
12. Generate a SYNC event: If SYNC is high at power-up,
bring the SYNC input low for a minimum of 100 ns.
Then bring SYNC back high.This will cause the internal
counters to reset and will startVD/HD operation.The first
VD/HD edge allows most Bank 1 register updates to occur,
including OUT_CONTROL to enable all outputs.
1. Turn on power supplies for AD9995.
2. Apply the master clock input CLI.
Table XIII. Power-Up RegisterWrite Sequence
3. Reset the internal AD9995 registers by writing a 1 to the
SW_RESET register (Addr. 0x10 in Bank 1).
Address
Data
Descrition
0x10
0x00
0x7F
0x00–0xFF
0x7F
0x01
0x04
0x01
ResAll Registers to DefaultValues
er Up e AFE and CLO Oscillator
Selgister Bak 2
VPATSequee, and FieldTiming
Select RBank 1
4. By default, the AD9995 is in Standby3 mode.To place the
part into normal power operation, write 0x004 to the AFE
OPRMODE register (Addr. 0x00 in Bank 1).
5. Write a 1 to the BANKSELECT register (Addr. 0x7F).
This will select Register Bank 2.
0x
01
0x15
Reset InternalTiming Core
0x30–71
0x20
0x11
orizontal and ShutterTiming
Cgure for Master Mode
Enable All Outputs after SYNC
SYNCPOL (for Software SYNC Only)
6. Load Bank 2 registers with the required VPAT group,
V-sequence, and field timing information.
0x01
001
0x01
7. Write a 0 to the BANKSELECT register to select Bank 1.
0x13
8. By default, the internal timing core is held in a reset state
with TGCORE_RSTB register = 0. Write a 1 to the TG-
CORE_RSTB register (Addr. 0x15 in Bank 1) to start the
internal timing core operation.
Generating ftwe SYNC without External SYNC Signal
If an external SNC pulse is not available, it is possible to
generate an internal SYNC in the AD9995 by writing to the
NCPOregister (Addr. 0x13). If the software SYNC option is
ustSYNC input (Pin 46) should be tied to ground (VSS).
9. Load the required registers to configure the high speed tim-
ing, horizontal timing, and shutter timing informat
After power-up, follow the same procedure as before for Steps
1 to 11.Then, for Step 12, instead of using the external SYNC
pulse, write a 1 to the SYNCPOL register.This will generate the
SYNC internally, and timing operation will begin.
10. Configure the AD9995 for Master mode timing
1 to the MASTER register (Addr. 0x20 in Bank
VDD
(INPUT)
1
CLI
(INPUT)
2
tPWR
SERIAL
WRITES
5
6
7
8
10
11
9
12
tSYNC
SYNC
(INPUT)
1V
VD
(OUTPUT)
1ST FIELD
1H
HD
(OUTPUT)
H2/H4
H1/H3, RG, DCLK
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUT CONTROL
REGISTER IS UPDATED AT VD/HD EDGE
Figure 35. Recommended Power-Up Sequence and Synchronization, Master Mode
REV. 0
–33–
SYNC during Master Mode Operation
The SYNC input may be used at any time during operation to
resync the AD9995 counters with external timing, as shown in
Figure 36.The operation of the digital outputs may be suspended
during the SYNC operation by setting the SYNCSUSPEND
register (Addr. 0x14) to 1.
The AD9995 contains three different standby modes
to optimize the overall power dissipation in a particular
application. Bits [1:0] of the OPRMODE register control
the power-down state of the device:
OPRMODE [1:0] = 00 = Normal Operation (Full Power)
OPRMODE[1:0] = 01 = Standby 1 Mode
Power-Up and Synchronization in Slave Mode
The power-up procedure for Slave mode operation is the same
as the procedure described for Master mode operation, with two
exceptions:
OPRMODE[1:0] = 10 = Standby 2 Mode
OPRMODE[1:0] = 11 = Standby 3 Mode (Lowest Overall Power)
• Eliminate Step 9. Do not write the part into Master mode.
Table XIV summarizes the operation of each power-down
mode. Note that the OUT_CONTRL register takes priority
over the Standby 1 and Standby modes in determining
the digital output states, but Sndby 3 ode takes priority
over OUT_CONTROL. Stan3 s the lowest power
consumption, and even sts dowe crystoscillator cir-
between CLI and O. Therefoif LI and CLO are
being used with a crtal generate the master clock, this
circuit will be powered downd there will be no clock signal.
When returninfrom Standby ode to normal operation, the
timing core ust be reset at least 500 µs after the OPRMODE
register is tten tThis will allow sufficient time for the crys-
• No SYNC pulse is required in Slave mode. Substitute Step 12
with starting the external VD and HD signals. This will syn-
chronize the part, allow Bank 1 register updates, and start the
timing operation.
When the AD9995 is used in Slave mode, the VD and HD inputs
are used to synchronize the internal counters. Following a falling
edge of VD, there will be a latency of 17 master clock cycles (CLI)
after the falling edge of HD until the internal H-counter will be
reset. The reset operation is shown in Figure 37.
SYNC
VD
END
HD
H124, RG, V1–V4,
VSG, SUBCK
NOTES
1. SYNC RISING EDGE RESETS VUNTERS TO.
2. SYNC POLARITY IS PROGRACPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14).
4. IF SYNCSUSPEND = 1, VERTIND RG ARE HELD AT THEIR DEFAULT POLARITIES.
5. IF SYNCSUSPEND = 0, ALL CLONUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.
e 36. CTiming to Synchronize AD9995 with ExternalTiming
VD
H-COUNTER
RESET
HD
CLI
H-COUNTER
(PIXEL COUNTER)
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
2
3
4
5
6
7
8
NOTES
INTERNAL H-COUNTER IS RESET 17 CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDPOL = 0).
TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE IS COINCIDENT WITH HD FALLING EDGE.
Figure 37. External VD/HD and Internal H-Counter Synchronization, Slave Mode
REV. 0
Table XIV. Standby Mode Operation
Standby 3 (Default)1, 2
OUT_CONT = LO2, 3
Standby 23, 4
Standby 13, 4
No Change
No Change
No Change
Running
Running
Only REFT, REFB ON
Running
Timing Core
O (4.3 mA)
HI (4.mA)
LO .3 mA)
(4.3 mA)
LO (4.3 mA)
LO (4.3 mA)
HI (4.3 mA)
LO (4.3 mA)
HI (4.3 mA)
LO (4.3 mA)
Running
Running
Running
1 To exit Standby 3, first write 00 to OPRMODE[1:0], thet theTi~500 µs to guarantee proper settling of the oscillator.
2 Standby 3 mode takes priority over OUT_CONTROor determining the t polarities.
3 These polarities assume OUT_CONT = HI becausUT_COL = LO takes priority over Standby 1 and 2.
4 Standby 1 and 2 will set H and RG drive strength to nivalue 3 mA).
REV. 0
AD9995
3V
ANALOG
SUPPLY
0.1F
TO STROBE CIRCUIT
TO MECHANICAL SHUTTER CIRCUIT
3
EXTERNAL SYNC FROM ASIC/DSP
LINE/FIELD/DCLK TO ASIC/DSP
3
SERIAL INTERFACE TO ASIC OR DSP
42 SDI
D5
D6
1
2
3
4
5
6
7
8
9
PIN 1
IDENTIFIER
41 SL
1F
1F
D7
40 REFB
39 REFT
38 AVSS
37 CCDIN
36 AVDD
35 CLI
D8
D9
D10
AD9995
TOP VIEW
OUT FROM CCD
D11
12
ASTER CLOCK INPUT
DATA OUTPUTS
0.1F
0.
DRVDD
DRVSS
3V
ANALOG
SUPPLY
34 CLO
3V
DRIVER
SUPPLY
+
VSUB 10
SUBCK 11
V1 12
33 TVDD
32 VSS
RGVDD
0 RG
+
0.1F
4.7F
4.7F
3V
RG
SUPPLY
V2 13
+
V3 14
RS
4.7F
VSUB TO CCD
1F
RG, H1–H4 TO CCD
5
3V
H1–H4
SUPPLY
+
4.7F
1F
TO
gure cal Circuit Configuration
CIRCUIT LAYOUT INFORMATION
The H1–H4 and RG traces should be designed to have low
inductance to avoid excessive distortion of the signals. Heavier
traces are recommended because of the large transient cur-
rent demand on H1–H4 by the CCD. If possible, locating the
AD9995 physically closer to the CCD will reduce the inductance
on these lines. As always, the routing path should be as direct as
possible from the AD9995 to the CCD.
The AD9995 typical circuit conneown in Figure 38.
The PCB layout is critical in achquality from
the AD999x products. All of the sucularly the
AVDD1, TCVDD, RGVDnd HVies, must be
decoupled to ground wality, frequency chip
capacitors. The decoshould be located as
close as possible to thd should have a very low
impedance path to a cond plane. There should
also be a 4.7 µF or larger pass capacitor for each main
supply—AVDD, RGVDD, HVDD, and DRVDD—although
this is not necessary for each individual pin. In most applications,
it is easier to share the supply for RGVDD and HVDD, which
may be done as long as the individual supply pins are separately
bypassed. A separate 3 V supply may also be used for DRVDD,
but this supply pin should still be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is
not recommended. It is recommended that the exposed paddle
on the bottom of the package be soldered to a large pad, with
multiple vias connecting the pad to the ground plane.
The AD9995 also contains an on-chip oscillator for driving an
external crystal. Figure 39 shows an example application using
a typical 24 MHz crystal. For the exact values of the external
resistors and capacitors, it is best to consult with the crystal
manufacturer’s data sheet.
AD9995
01D
35
CLI
34 CLO
500M
20pF
1M
The analog bypass pins (REFT, REFB) should also be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor should also be located
close to the pin.
20pF
24MHz
XTAL
Figure 39. Crystal Driver Application
–36–
REV. 0
AD9995
SERIAL INTERFACETIMING
Figure 40b shows a more efficient way to write to the registers,
using the AD9995’s address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 24-bit data-words. Each new 24-bit data-word will
automatically be written to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. Continuous write operations may be used
starting with any register location, and may be used to write to as
few as two registers, or as many as the entire register space.
All of the internal registers of the AD9995 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit address
and a 24-bit data-word. Both the 8-bit address and 24-bit data-
word are written starting with the LSB.To write to each register,
a 32-bit operation is required, as shown in Figure 40a. Although
many registers are fewer than 24 bits wide, all 24 bits must be
written for each register. For example, if the register is only
10 bits wide, the upper 14 bits are don’t cares and may be filled
with 0s during the serial write operation. If fewer than 24 bits are
written, the register will not be updated with new data.
8-BIT ADDRESS
24-BIT DATA
...
D21 D22 D
SDATA
SCK
SL
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
A3
tDS
tDH
...
1
2
3
4
5
6
7
8
9
10
11
12
31
32
tL
tLS
...
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HOR IN BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FO.
3. IF THE REGISTER LENGTH IS <24 BITS, “DON’T CARE” BITS MUST BE USECOMPLTHE 24-BIT DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION DIFFNT TIMES, DEPENDING ON THE
PARTICULAR REGISTER WRITTEN TO. SEE THE REGISTER UPDATES SECTIORE INFORMATION.
Figure 40a. Seriarite Operation
ARTING
DDRESS
DATA FOR NEXT
REGISTER ADDRESS
...
...
...
SDATA
A0
A1
A2
A4
A6
A
D0
D1
D22 D23 D0
D1
D22 D23 D0
A3
D1
D2
...
...
59 ...
...
SCK
SL
58
1
2
3
6
7
8
9
10
31
32
33
34
55
56
57
...
...
NOTE
1. ENTIAL TERS MAY BE LOADED CONTINUOUSLY.
2T ADDSS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
TIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
Figure 40b. Continuous Serial Write Operation
REV. 0
–37–
Register Address Banks 1 and 2
When writing to the AD9995, Address 0x7F is used to specify
which address bank is being written to.To write to Bank 1, the
LSB of Address 0x7F should be set to 0; to write to Bank 2, the
The AD9995 address space is divided into two different regis-
ter banks, referred to as Register Bank 1 and Register Bank 2.
Figure 41 illustrates how the two banks are divided. Register
Bank 1 contains the registers for the AFE, miscellaneous func-
tions, VD/HD parameters, timing core, CLPOB masking, VSG
patterns, and shutter functions. Register Bank 2 contains all
of the information for the V-pattern groups, V-sequences, and
Note that Register Bank 1 contains many unused addresses. Any
don’t cares, and it is acceptable if these addresses are filled in
with all 0s during a continuous register write operation. However,
the undefined addresses above 0x7F must not be written to, or
the AD9995 may not operate properly.
REGISTER BK 2
ADDR 0x00
REGISTER BANK 1
ADDR 0x00
AFE REGISTERS
ADDR 0x10
MISCELLANEOUS REGISTERS
VPATVPATTERS
ADDR 0x20
VD/HD REGISTERS
ADDR 0x30
TIMING CORE REGISTERS
ADDR 0x7E
ADDR 0x7F
ADDR 0x80
ADDR 0x40
CLPOB MASK REGISTERS
SWITCH TGISTER BANK 1
VSEQ0–VSEQ9 REGISTERS
ADDR 0x50
VSG PATTERN REGISTERS
ADDR 0x60
SHUTTER REGISTERS
ADDR 0xCF
ADDR 0xD0
ADDR 0x7F
ADDR 0x8F
SWITCH TO REGISTER BANK 2
INVALID—DO NOT ACCESS
FIELD 0–FIELD 5 REGISTERS
ADx
ADDR 0xFF
TE TO ADDRESTO SWITCH REGISTER BANKS
Figure out onternal Register Banks 1 and 2
REV. 0
Updating New RegisterValues
SG-Line Updated: A few of the registers in Bank 1 are
updated at the end of the SG active line, at the HD falling
edge.These are the registers to control the SUBCK signal so
that the SUBCK output will not be updated until after the SG
line has been completed.These registers are darkly shaded in
gray in the Bank 1 register list.
The AD9995’s internal registers are updated at different times,
depending on the particular register.Table XV summarizes the
four different types of register updates:
SCK Updated: Some of the registers in Bank 1 are updated
immediately, as soon as the 24th data bit (D23) is written.
These registers are used for functions that do not require gat-
ing with the nextVD boundary, such as power-up and reset
functions.These registers are lightly shaded in gray in the
Bank 1 register list.
SCP Updated: In Bank 2, all of the V-pattern group and
V-sequence registers (Addr. 0x00 through 0xCF, exclud-
ing 0x7F) are updated at the next SCP, where they will
be used. For example, in Figure 42, this field has selected
Region 1 to use V-Sequence 3 for the vertical outputs. This
means that a write to any of the V-Sequence 3 registers, or
any of the V-pattern group gisters that are referenced by
V-Sequence 3 will be upted at SCP1. If multiple writes
are done to the same reer, tlast one done before SCP1
will be the one that updLikewisregister writes to
any V-Sequence registers wbe uated at SCP2, and
register writes o y V-Sequenregisters will be updated
The Bank Select register (Addr. 0x7F in Bank 1 and 2) is also
SCK updated.
VD Updated: Most of the registers in Bank 1, as well as the
Field registers in Bank 2, are updated at the next VD falling
edge. By updating these values at the next VD edge, the cur-
rent field will not be corrupted and the new register values
will be applied to the next field.The Bank 1 register updates
may be further delayed past the VD falling edge by using
the UPDATE register (Addr. 0x19).This will delay the VD
updated register updates to any HD line in the field. Note that
the Bank 2 registers are not affected by the UPDATE register.
Table XV. Register Update Locans
Description
UpdateType
Register Bank
SCK Updated
VD Updated
Bank 1 Only
Register is immetely updad when the 24th data bit (D23) is clocked in.
Regisdated heD falling edge.VD updated registers in Bank 1 may be
dey usinhe UPDATE register at Address 0x19 in Bank 1. Bank 2
ue affected by the UPDATE register.
SG Line Updated
SCP Updated
Bank 1 Only
Bank 2 Only
Rd at the HD falling edge at the end of the SG-active line.
Reged at the next SCP when the register will be used.
SCK
SG
DATED
SCP
UPDATED
UPDATED UPDATED
SERIAL
WRITE
VD
H
SGLINE
VSG
USE VSEQ2
USE VSEQ3
REGION 1
USE VSEQ5
USE VSEQ8
REGION 3
V1–V6
REGION 0
SCP 0
REGION 2
SCP 0
SCP 2
SCP 1
SCP 3
Figure 42. Register Update Locations (SeeTable XV for Definitions)
REV. 0
All registers areVD updated, except where noted:
= SCK Updated
= SG-Line Updated
Table XVI. AFE Register Map
Register Description
Register Name
[11:0]
[9:0]
AFE Operation Modes (seeTable XXIV for detail).
[7:0]
Optical Black Clamp Level.
[11:0]
AFE Control Modes (seeTable XXV for detail).
Table XVII. Miscellaneous Register Map
Register Name
SW_RST
Register Description
[0]
[0]
[0]
[0]
[0]
[0]
[0]
Software Reset. 1 = Reset all regiers to fault, then self-clear back to 0.
Output Control. 0 = Make aoutputs dc inve.
Internal Use Only. Must e set to .
SYNC Active Polarity (Ace Low).
TGCORE_RSTB
OSC_PWRDOWN
Suspend Clocks during SYActiv1 = Suspend).
Timing Core Reset Bar. 0 = ReTG Core, 1 = Resume Operation.
CLO Oscillatoower-Down (0 = Oscillator is powered-down).
[0]
Iy. Mut be set to 0.
[11:0]
[0]
Sne (HD) in the field to updateVD updated registers.
Predate of theVD Updated Registers. 1 = Prevent update.
Mode Register.
[23:0]
[1:0]
FiValue Sync. 0 = Next Field 0, 1 = Next Field 1, 2/3 = Next Field 2.
TaVIII.VD/HD Register Map
Reg
Register Description
[0]
VD/HD Master or SlaveTiming (0 = Slave mode).
VD/HD Active Polarity. 0 = Low, 1 = High.
Rising Edge Location forVD [17:12] and HD [11:0].
[0]
[17:0]
REV. 0
Table XIX.Timing Core Register Map
Register Name
Register Description
[0]
Divide CLI Input Clock by 2. 1 = Divide by 2.
[12:0]
H1 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
H1 Positive Edge Location [6:1]. H1 Negative Edge Location [12:7].
[12:0]
[12:0]
[1:0]
H3 Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
H3 Positive Edge Location [6:1]. H3 Negative Edge Location [12:7].
RG Signal Control: Polarity [0](0 = Inversion, 1 = No Inversion).
RG Positive Edge Location [6:1]. RG Negative Edge Location [12:7].
Retime HBLK to Internal H1/H3 Clocks. HRetime [0]. H3 Retime [1].
Preferred setting is 1 for each bit. Setting ch bit to 1 will add one cycle delay
to HBLK toggle positions.
[14:0]
Drive Strength Control for H1 [2:0H2 [5H3 [8:6H4 [11:9], and
RG [14:12]. Drive CurrentValu0 = Off, 1 .3 , 2 = 8.6 mA,
3 = 12.9 mA, 4 = 17.2 mA, 5 2mA, 6 = 25mA, 7 = 30.1 mA.
[11:0]
[8:0]
SHP/SHD Sample Control: SHP Samng Location [5:0].
SHD Sampling Locati[11:6].
DOUT Phase Conl [5:0]CLK Mode [6]. DOUTDELAY [8:7].
Table XX. CLPOB Masking Regir Map
Register Name
Register escription
[23:0]
[23:0]
[11:0]
CLPOB Line askinLine #0 [11:0]. Line #1 [23:0].
ne Maing. Line #2 [11:0]. Line #3 [23:0].
Masking. Line #4 [11:0].
Table XXttern Register Map
Register
Register Description
[3:0]
Start Polarity for SG Patterns. Pattern #0 [0]. Pattern #1 [1].
Pattern #2 [2]. Pattern #3 [3].
[23:0]
[23:0]
[23:0]
[23:0]
FFFFFF S1
SGT12_2
GTOG12_3
Pattern #0.Toggle Position 1 [11:0].Toggle Position 2 [23:12].
Pattern #1.Toggle Position 1 [11:0].Toggle Position 2 [23:12].
Pattern #2.Toggle Position 1 [11:0].Toggle Position 2 [23:12].
Pattern #3.Toggle Position 1 [11:0].Toggle Position 2 [23:12].
Table XXII. Shutter Control Register Map
Register Name
Register Description
[4:0]
Trigger forVSUB [0], MSHUT [1], STROBE [2], Exposure [3], and
Readout [4]. Note that to trigger the readout to automatically occur after the
exposure period, both exposure and readout should be triggered together.
[2:0]
Number of Fields to Suppress the SUBCK Pulses after theVSG Line.
[11:0]
[12]
Number of Fields to Suppress the SUBCK andVSG Pulses.
Set = 1 to disable theVD/HD outputs during exposure (when >1 field).
[11:0]
[23:12]
Number of SUBCK Pulses to Suppress afterVSG Line.
Number of SUBCK Pulses per Field.
[0]
SUBCK Pulse Start Polarity.
[23:0]
[23:0]
First SUBCK Pulse.Toggle Position 1 [11:0].Toggle Position 2 [23:0].
Second SUBCK Pulse.Toggle Position 1 [11:0].Toggle Position 2 [23:0].
REV. 0
Table XXII. Shutter Control Register Map (continued)
Register Name
Register Description
[1:0]
VSUB Readout Mode [0].VSUB Keep-On Mode [1].
VSUB ON Position [11:0].VSUB Active Polarity [12].
MSHUT Active Polarity [0]. MSHUT Manual Enable [1].
MSHUT ON Position. Line [11:0]. Pixel [23:0].
[12:0]
[1:0]
MSHUTOFF_FD
[23:0]
[11:0]
[23:0]
[0]
MSHUTOFF_LNPX MSHUT OFF Position. Line [11:0]. Pixel [23:12].
STROBE Active Polarity.
[11:0]
[23:0]
[11:0]
[23:0]
STROBON_FD
STROBON_LNPX
STROBOFF_FD
STROBOFF_LNPX
STROBE ON Position. Line [11:0]. Pixel [22].
STROBE OFF Position. Line [11:. el [23:12].
Table XXIII. Register Map Selectio
Register Name
Register Description
7F [0]
Register Bank Access from k 1 to ank 2. 0 = Bank 1, 1 = Bank 2.
Table XXIV. AFE OperatRegister Detail
Register Name
Recripti
[1:0]
[2]
0 ation, 1 = Standby 1, 2 = Standby 2, 3 = Standby 3.
0 lamp, 1 = Enable OB Clamp.
0 = mal OB Clamp Settling, 1 = Select Fast OB Clamp Settling.
t Use Only. Set to 0.
[3]
[4]
[5]
PBLK_LVL
DOTValue during PBLK: 0 = Blank to Zero, 1 = Blank to Clamp Level.
t Use Only. Set to 0.
[7:6]
[8]
0 = Enable DC Restore Circuit, 1 = Bypass DC Restore Circuit during PBLK.
Test Use Only. Set to 0.
[9]
Table XXV. AFE Control Register Detail
ter Name
Register Description
[1:0]
[2]
Test Use Only. Set to 00.
Test Use Only. Set to 1.
[3]
0 = Data Outputs are Driven, 1 = Data Outputs areThree-Stated.
0 = Latch Data Outputs with DOUT Phase, 1 = Output LatchTransparent.
0 = Binary Encode Data Outputs, 1 = Gray Encode Data Outputs.
[4]
[5]
REV. 0
AllV-pattern group andV-sequence registers are SCP updated, and all Field registers areVD updated.
Table XXVI.V-Pattern Group 0 (VPAT0) Register Map
Register Name
Description
[5:0]
[11:6]
[23:12]
VPOL_0
VPATLEN_0
VPAT0 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Total Length of VPAT0. Note: If using VPAT0 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
[11:0]
[23:12]
V1TOG1_0
V1TOG2_0
V1 Toggle Position 1
V1 Toggle Position 2
[11:0]
[23:12]
V1TOG3_0
V2TOG1_0
V1 Toggle Position 3
V2 Toggle Position 1
[11:0]
[23:12]
V2TOG2_0
V2TOG3_0
V2 Toggle Position 2
V2 Toggle Position 3
[11:0]
[23:12]
V3TOG1_0
V3TOG2_0
V3 Toggle Position 1
V3 Toggle Position 2
[11:0]
[23:12]
V3TOG3_0
V4TOG1_0
V3 Toggle Positio
V4 Toggle Position
[11:0]
[23:12]
V4TOG2_0
V4TOG3_0
V4 Toggle Position 2
V4 Toggle Position 3
[11:0]
[23:12]
V5TOG1_0
V5TOG2_0
V5 Togglosition 1
V5 Toggle Ption 2
[11:0]
[23:12]
V5TOG3_0
V6TOG1_0
Posit
osition 1
[11:0]
[23:12]
V6TOG2_0
V6TOG3_0
osition 2
Position 3
[11:0]
[23:12]
0
_0
[11:0]
[23:12]
FREEZE2_0
ME2_0
XVII.V-Pattern Group 1 (VPAT1) Register Map
RegName
Description
[5:0]
[11:6]
[23:12]
POL_1
VPATLEN_1
VPAT1 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Total Length of VPAT1. Note: If using VPAT1 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
[11:0]
[23:12]
V1TOG1_1
V1TOG2_1
V1 Toggle Position 1
V1 Toggle Position 2
[11:0]
[23:12]
V1TOG3_1
V2TOG1_1
V1 Toggle Position 3
V2 Toggle Position 1
[11:0]
[23:12]
V2TOG2_1
V2TOG3_1
V2 Toggle Position 2
V2 Toggle Position 3
[11:0]
[23:12]
V3TOG1_1
V3TOG2_1
V3 Toggle Position 1
V3 Toggle Position 2
[11:0]
[23:12]
V3TOG3_1
V4TOG1_1
V3Toggle Position 3
V4 Toggle Position 1
[11:0]
[23:12]
V4TOG2_1
V4TOG3_1
V4 Toggle Position 2
V4 Toggle Position 3
REV. 0
Table XXVII.V-Pattern Group 1 (VPAT1) Register Map (continued)
Register Name
Description
[11:0]
[23:12]
V5TOG1_1
V5TOG2_1
V5 Toggle Position 1
V5 Toggle Position 2
[11:0]
[23:12]
V5TOG3_1
V6TOG1_1
V5 Toggle Position 3
V6 Toggle Position 1
[11:0]
[23:12]
V6TOG2_1
V6TOG3_1
V6 Toggle Position 2
V6 Toggle Position 3
[11:0]
[23:12]
FREEZE1_1
RESUME1_1
[11:0]
[23:12]
FREEZE2_1
RESUME2_1
Table XXVIII.V-Pattern Group 2 (VPAT2) Register M
Register Name
Description
[5:0]
[11:6]
[23:12]
VPOL_2
VPATLEN_2
VPAT2 Start Polarity. V1[. V2[1]. V3[2]. V3]. V5[4]. V6[5].
Total Length of VPAT2otf using VPAT2 as a second V-sequence in
the VSG active line, this vais the st position for the second V-sequence.
[11:0]
[23:12]
V1TOG1_2
V1TOG2_2
V1 Toggle Position 1
V1 Toggle Pion 2
[11:0]
[23:12]
V1TOG3_2
V2TOG1_2
V1 Toggle Positi3
V2 sition
[11:0]
[23:12]
V2TOG2_2
V2TOG3_2
Von 2
Vn 3
[11:0]
[23:12]
V3TOG1_2
V3TOG2_2
V3 ion 1
V3 Toosition 2
[11:0]
[23:12]
V3TOG3_2
V4TOG1_2
Voggle Position 3
V4 oggle Position 1
[11:0]
[23:12]
Toggle Position 2
V4 Toggle Position 3
[11:0]
[23:12]
V5 Toggle Position 1
V5 Toggle Position 2
[11:0]
[23:12]
OG1_2
V5 Toggle Position 3
V6 Toggle Position 1
[11:0]
[23:12]
G2_2
OG3_2
V6 Toggle Position 2
V6 Toggle Position 3
[11:0]
[23:12]
FREEZE1_2
RESUME1_2
[11:0]
[23:12]
FREEZE2_2
RESUME2_2
Table XXIX.V-Pattern Group 3 (VPAT3) Register Map
Register Name
Description
[5:0]
[11:6]
[23:12]
VPOL_3
VPATLEN_3
VPAT3 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Total Length of VPAT3. Note: If using VPAT3 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
[11:0]
[23:12]
V1TOG1_3
V1TOG2_3
V1 Toggle Position 1
V1 Toggle Position 2
REV. 0
Table XXIX.V-Pattern Group 3 (VPAT3) Register Map (continued)
Register Name
Description
[11:0]
[23:12]
V1TOG3_3
V2TOG1_3
V1 Toggle Position 3
V2 Toggle Position 1
[11:0]
[23:12]
V2TOG2_3
V2TOG3_3
V2 Toggle Position 2
V2 Toggle Position 3
[11:0]
[23:12]
V3TOG1_3
V3TOG2_3
V3 Toggle Position 1
V3 Toggle Position 2
[11:0]
[23:12]
V3TOG3_3
V4TOG1_3
V3Toggle Position 3
V4 Toggle Position 1
[11:0]
[23:12]
V4TOG2_3
V4TOG3_3
V4 Toggle Position 2
V4 Toggle Position 3
[11:0]
[23:12]
V5TOG1_3
V5TOG2_3
V5 Toggle Position 1
V5 Toggle Position 2
[11:0]
[23:12]
V5TOG3_3
V6TOG1_3
V5 Toggle Position 3
V6 Toggle Position 1
[11:0]
[23:12]
V6TOG2_3
V6TOG3_3
V6 Toggle Position 2
V6 Toggle Position
[11:0]
[23:12]
FREEZE1_3
RESUME1_3
[11:0]
[23:12]
FREEZE2_3
RESUME2_3
Table XXX.V-Pup 4 (4) Register Map
Register Name
[5:0]
[11:6]
[23:12]
VPOL_4
_4
art Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Total Length of VPAT4. Note: If using VPAT4 as a second V-sequence in
he VSG active line, this value is the start position for the second V-sequence.
[11:0]
[23:12]
1_4
2_4
V1 Toggle Position 1
V1 Toggle Position 2
[11:0]
[23:12]
V1 Toggle Position 3
V2 Toggle Position 1
[11:0]
[23:12
_4
2TOG3_4
V2 Toggle Position 2
V2 Toggle Position 3
[11:0]
[23:12]
3TOG1_4
V3TOG2_4
V3 Toggle Position 1
V3 Toggle Position 2
[11:0]
[23:12]
V3TOG3_4
V4TOG1_4
V3Toggle Position 3
V4 Toggle Position 1
[11:0]
[23:12]
V4TOG2_4
V4TOG3_4
V4 Toggle Position 2
V4 Toggle Position 3
[11:0]
[23:12]
V5TOG1_4
V5TOG2_4
V5 Toggle Position 1
V5 Toggle Position 2
[11:0]
[23:12]
V5TOG3_4
V6TOG1_4
V5 Toggle Position 3
V6 Toggle Position 1
[11:0]
[23:12]
V6TOG2_4
V6TOG3_4
V6 Toggle Position 2
V6 Toggle Position 3
[11:0]
[23:12]
FREEZE1_4
RESUME1_4
[11:0]
[23:12]
FREEZE2_4
RESUME2_4
REV. 0
Table XXXI.V-Pattern Group 5 (VPAT5) Register Map
Register Name
Description
[5:0]
[11:6]
[23:12]
VPOL_5
VPATLEN_5
VPAT5 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Total Length of VPAT5. Note: If using VPAT5 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
[11:0]
[23:12]
V1TOG1_5
V1TOG2_5
V1 Toggle Position 1
V1 Toggle Position 2
[11:0]
[23:12]
V1TOG3_5
V2TOG1_5
V1 Toggle Position 3
V2 Toggle Position 1
[11:0]
[23:12]
V2TOG2_5
V2TOG3_5
V2 Toggle Position 2
V2 Toggle Position 3
[11:0]
[23:12]
V3TOG1_5
V3TOG2_5
V3 Toggle Position 1
V3 Toggle Position 2
[11:0]
[23:12]
V3TOG3_5
V4TOG1_5
V3Toggle Position 3
V4 Toggle Position 1
[11:0]
[23:12]
V4TOG2_5
V4TOG3_5
V4 Toggle Position 2
V4 Toggle Position 3
[11:0]
[23:12]
V5TOG1_5
V5TOG2_5
V5 Toggle Position 1
V5 Toggle Position 2
[11:0]
[23:12]
V5TOG3_5
V6TOG1_5
V5 Toggle Position 3
V6 Toggle Pion 1
[11:0]
[23:12]
V6TOG2_5
V6TOG3_5
V6 Toggle Positi2
V6 sition
[11:0]
[23:12]
FREEZE1_5
RESUME1_5
[11:0]
[23:12]
FREEZE2_5
RESUME2_5
Table XX.V-PattGroup 6 (VPAT6) Register Map
Rme
Description
[5:0]
[11:6]
[23:12]
VP
VPAT6 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Total Length of VPAT6. Note: If using VPAT6 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
[11:0]
[23:12]
G1_6
OG2_6
V1 Toggle Position 1
V1 Toggle Position 2
[11:0]
[23:12]
V1TOG3_6
V2TOG1_6
V1 Toggle Position 3
V2 Toggle Position 1
[11:0]
[23:12]
V2TOG2_6
V2TOG3_6
V2 Toggle Position 2
V2 Toggle Position 3
[11:0]
[23:12]
V3TOG1_6
V3TOG2_6
V3 Toggle Position 1
V3 Toggle Position 2
[11:0]
[23:12]
V3TOG3_6
V4TOG1_6
V3 Toggle Position 3
V4 Toggle Position 1
[11:0]
[23:12]
V4TOG2_6
V4TOG3_6
V4 Toggle Position 2
V4 Toggle Position 3
[11:0]
[23:12]
V5TOG1_6
V5TOG2_6
V5 Toggle Position 1
V5 Toggle Position 2
REV. 0
Table XXXII.V-Pattern Group 6 (VPAT6) Register Map (continued)
Register Name
Description
[11:0]
[23:12]
V5TOG3_6
V6TOG1_6
V5 Toggle Position 3
V6 Toggle Position 1
[11:0]
[23:12]
V6TOG2_6
V6TOG3_6
V6 Toggle Position 2
V6 Toggle Position 3
[11:0]
[23:12]
FREEZE1_6
RESUME1_6
[11:0]
[23:12]
FREEZE2_6
RESUME2_6
Table XXXIII.V-Pattern Group 7 (VPAT7) Register Map
Register Name Description
[5:0]
[11:6]
[23:12]
VPOL_7
VPATLEN_7
VPAT7 Start Polarity. V1[0]V2[1V3[2]. V4[3V5[4]. V6[5].
Total Length of VPATNote: If using AT7 as a second V-sequence in
the VSG active line, his valuis the start position for the second V-sequence.
[11:0]
[23:12]
V1TOG1_7
V1TOG2_7
V1 Toggle Position
V1 Toggle Position 2
[11:0]
[23:12]
V1TOG3_7
V2TOG1_7
V1 Toggle Position 3
V2 ToggPosition 1
[11:0]
[23:12]
V2TOG2_7
V2TOG3_7
V2 Toggle Ption 2
e Posn
[11:0]
[23:12]
V3TOG1_7
V3TOG2_7
osition 1
osition 2
[11:0]
[23:12]
V3TOG3_7
V4TOG1_
Position 3
V4 gle Position 1
[11:0]
[23:12]
V4TOG3_7
V4 Toggle Position 2
V4 Toggle Position 3
[11:0]
[23:12]
1_7
2_7
V5 Toggle Position 1
V5 Toggle Position 2
[11:0]
[23:12]
V5 Toggle Position 3
V6 Toggle Position 1
[11:0]
[23:12
_7
6TOG3_7
V6 Toggle Position 2
V6 Toggle Position 3
[11:0]
[23:12]
REEZE1_7
RESUME1_7
[11:0]
[23:12]
FREEZE2_7
RESUME2_7
Table XXXIV.V-Pattern Group 8 (VPAT8) Register Map
Register Name
Description
[5:0]
[11:6]
[23:12]
VPOL_8
VPATLEN_8
VPAT8 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Total Length of VPAT8. Note: If using VPAT8 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
[11:0]
[23:12]
V1TOG1_8
V1TOG2_8
V1 Toggle Position 1
V1 Toggle Position 2
[11:0]
[23:12]
V1TOG3_8
V1TOG4_8
V1 Toggle Position 3
V1 Toggle Position 4
REV. 0
Table XXXIV.V-Pattern Group 8 (VPAT8) Register Map (continued)
Register Name
Description
[11:0]
[23:12]
V2TOG1_8
V2TOG2_8
V2 Toggle Position 1
V2 Toggle Position 2
[11:0]
[23:12]
V3TOG3_8
V3TOG4_8
V2 Toggle Position 3
V2 Toggle Position 4
[11:0]
[23:12]
V3TOG1_8
V4TOG2_8
V3 Toggle Position 1
V3 Toggle Position 2
[11:0]
[23:12]
V4TOG3_8
V4TOG4_8
V3 Toggle Position 3
V3 Toggle Position 4
[11:0]
[23:12]
V5TOG1_8
V5TOG2_8
V4 Toggle Position 1
V4 Toggle Position 2
[11:0]
[23:12]
V5TOG3_8
V6TOG4_8
V4 Toggle Position 3
V4 Toggle Position 4
[11:0]
[23:12]
V6TOG1_8
V6TOG2_8
V5 Toggle Position 1
V5 Toggle Position 2
[11:0]
[23:12]
V6TOG3_8
V6TOG4_8
V5 Toggle Position 3
V5 Toggle Position 4
[11:0]
[23:12]
V6TOG1_8
V6TOG2_8
V6 Toggle Position 1
V6 Toggle Position 2
[11:0]
[23:12]
V6TOG3_8
V6TOG4_8
V6 Toggle Psition 3
V6 Toggle Poon 4
[11:0]
[23:12]
FREEZE1_8
RESUME1_8
[11:0]
[23:12]
FREEZE2_8
RESUME2_8
Table XXVPattGroup 9 (VPAT9) Register Map
Regme
escription
[5:0]
[11:6]
[23:12]
VPAT9 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Total Length of VPAT9. Note: If using VPAT9 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
[11:0]
[23:12]
G1_9
G2_9
V1 Toggle Position 1
V1 Toggle Position 2
[11:0]
[23:12]
TOG3_9
V1TOG4_9
V1 Toggle Position 3
V1 Toggle Position 4
[11:0]
[23:12]
V2TOG1_9
V2TOG2_9
V2 Toggle Position 1
V2 Toggle Position 2
[11:0]
[23:12]
V3TOG3_9
V3TOG4_9
V2 Toggle Position 3
V2 Toggle Position 4
[11:0]
[23:12]
V3TOG1_9
V4TOG2_9
V3 Toggle Position 1
V3 Toggle Position 2
[11:0]
[23:12]
V4TOG3_9
V4TOG4_9
V3 Toggle Position 3
V3 Toggle Position 4
[11:0]
[23:12]
V5TOG1_9
V5TOG2_9
V4 Toggle Position 1
V4 Toggle Position 2
[11:0]
[23:12]
V5TOG3_9
V6TOG4_9
V4 Toggle Position 3
V4 Toggle Position 4
REV. 0
Table XXXV.V-Pattern Group 9 (VPAT9) Register Map (continued)
Register Name
Description
[11:0]
[23:12]
V6TOG1_9
V6TOG2_9
V5 Toggle Position 1
V5 Toggle Position 2
[11:0]
[23:12]
V6TOG3_9
V6TOG4_9
V5 Toggle Position 3
V5 Toggle Position 4
[11:0]
[23:12]
V6TOG1_9
V6TOG2_9
V6 Toggle Position 1
V6 Toggle Position 2
[11:0]
[23:12]
V6TOG3_9
V6TOG4_9
V6 Toggle Position 3
V6 Toggle Position 4
[11:0]
[23:12]
FREEZE1_9
RESUME1_9
[11:0]
[23:12]
FREEZE2_9
RESUME2_9
Table XXXVI. Register Map Selection (SCK Updated Reger)
Register Name
Register Descripn
7F [0]
Register Bank AccesoBank 2 Bank 1. 0 = Bank 1, 1 = Bank 2.
Table XXXVII.V-Sequee 0 (VSEQ0) Reger Map
Register Name
Description
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMASK_0
CLPOBPOL_0
PBLKPOL_0
VPATSEL_0
VMASK_
HBLKA_0
larity ring HBLK. H1 [0]. H3 [1].
t Polarity
Polarity
Pattern Group for V-Sequence 0
EnMasking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
REPO_0
EPE_0
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
[11:0]
[23:12]
_0
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 0
[11:0]
[23:12
G1_0
OG2_0
PBLK Toggle Position 1 for V-Sequence 0
PBLK Toggle Position 2 for V-Sequence 0
[11:0]
[23:12]
BLKTOG1_0
HBLKTOG2_0
HBLK Toggle Position 1 for V-Sequence 0
HBLK Toggle Position 2 for V-Sequence 0
[11:0]
[23:12]
HBLKTOG3_0
HBLKTOG4_0
HBLK Toggle Position 3 for V-Sequence 0
HBLK Toggle Position 4 for V-Sequence 0
[11:0]
[23:12]
HBLKTOG5_0
HBLKTOG6_0
HBLK Toggle Position 5 for V-Sequence 0
HBLK Toggle Position 6 for V-Sequence 0
[11:0]
[23:12]
CLPOBTOG1_0
CLPOBTOG2_0
CLPOB Toggle Position 1 for V-Sequence 0
CLPOB Toggle Position 2 for V-Sequence 0
REV. 0
Table XXXVIII.V-Sequence 1 (VSEQ1) Register Map
Register Name
Description
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMASK_1
CLPOBPOL_1
PBLKPOL_1
VPATSEL_1
VMASK_1
HBLKALT_1
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 1
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
VPATREPO_1
VPATREPE_1
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions r Even Lines
[11:0]
[23:12]
VPATSTART_1
HDLEN_1
Start Position in the Line for the Selected V-Ptern Grup
HD Line Length (Number of Pixels) for V-Suenc
[11:0]
[23:12]
PBLKTOG1_1
PBLKTOG2_1
PBLK Toggle Position 1 for V-Sequen1
PBLK Toggle Position 2 for V-Seque 1
[11:0]
[23:12]
HBLKTOG1_1
HBLKTOG2_1
HBLK Toggle Position 1 for V-Squenc
HBLK Toggle Position 2 for -Sequence 1
[11:0]
[23:12]
HBLKTOG3_1
HBLKTOG4_1
HBLK Toggle Position 3 r V-Sequence 1
HBLK Toggle Position for V-quence 1
[11:0]
[23:12]
HBLKTOG5_1
HBLKTOG6_1
HBLK Toggle Position 5 -Sequen1
HBLK Toggle Position 6 for Seqnce 1
[11:0]
[23:12]
CLPOBTOG1_1
CLPOBTOG2_1
CLPOB Toe Position 1 for Vequence 1
CLPOB Togglosition 2 foV-Sequence 1
Table XXXIX.V-SSEQ2egister Map
Register Name
D
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMASK_2
CLPOBPOL_
PBLKPOL_2
VPATSEL_2
H2
Maskity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBK Start Polarity
Seted V-Pattern Group for V-Sequence 2
able Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
[11:0]
[23:12]
TSTART_2
EN_2
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 2
[11:0]
[23:12]
KTOG1_2
BLKTOG2_2
PBLK Toggle Position 1 for V-Sequence 2
PBLK Toggle Position 2 for V-Sequence 2
[11:0]
[23:12]
HBLKTOG1_2
HBLKTOG2_2
HBLK Toggle Position 1 for V-Sequence 2
HBLK Toggle Position 2 for V-Sequence 2
[11:0]
[23:12]
HBLKTOG3_2
HBLKTOG4_2
HBLK Toggle Position 3 for V-Sequence 2
HBLK Toggle Position 4 for V-Sequence 2
[11:0]
[23:12]
HBLKTOG5_2
HBLKTOG6_2
HBLK Toggle Position 5 for V-Sequence 2
HBLK Toggle Position 6 for V-Sequence 2
[11:0]
[23:12]
CLPOBTOG1_2
CLPOBTOG2_2
CLPOB Toggle Position 1 for V-Sequence 2
CLPOB Toggle Position 2 for V-Sequence 2
REV. 0
Table XL.V-Sequence 3 (VSEQ3) Register Map
Register Name
Description
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMASK_3
CLPOBPOL_3
PBLKPOL_3
VPATSEL_3
VMASK_3
HBLKALT_3
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 3
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
VPATREPO_3
VPATREPE_3
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetins for Even Lines
[11:0]
[23:12]
VPATSTART_3
HDLEN_3
Start Position in the Line for the Selected -PatterGroup
HD Line Length (Number of Pixels) foSeqnce 3
[11:0]
[23:12]
PBLKTOG1_3
PBLKTOG2_3
PBLK Toggle Position 1 for V-Seence 3
PBLK Toggle Position 2 for V-uence 3
[11:0]
[23:12]
HBLKTOG1_3
HBLKTOG2_3
HBLK Toggle Position 1 foV-Seqnce 3
HBLK Toggle Position 2 or V-Seque3
[11:0]
[23:12]
HBLKTOG3_3
HBLKTOG4_3
HBLK Toggle Positi3 for V-Sequence
HBLK Toggle Poon 4 foV-Sequence 3
[11:0]
[23:12]
HBLKTOG5_3
HBLKTOG6_3
HBLK Toggle Positifor V-Seence 3
HBLK Toggle Position or Vquence 3
[11:0]
[23:12]
CLPOBTOG1_3
CLPOBTOG2_3
CLPOB oggle Position 1 fV-Sequence 3
CLPOB Tgle Position 2 for V-Sequence 3
Table XLI.V(VSE) Register Map
Register Name
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMAS_4
L_4
4
VPATSEL_4
K_4
LT_4
Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
Selected V-Pattern Group for V-Sequence 4
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
_4
E_4
Number of Selected V-Pattern Group Repetitions for Odd Lines
Number of Selected V-Pattern Group Repetitions for Even Lines
[11:0]
[23:12
VPATSTART_4
DLEN_4
Start Position in the Line for the Selected V-Pattern Group
HD Line Length (Number of Pixels) for V-Sequence 4
[11:0]
[23:12]
PBLKTOG1_4
PBLKTOG2_4
PBLK Toggle Position 1 for V-Sequence 4
PBLK Toggle Position 2 for V-Sequence 4
[11:0]
[23:12]
HBLKTOG1_4
HBLKTOG2_4
HBLK Toggle Position 1 for V-Sequence 4
HBLK Toggle Position 2 for V-Sequence 4
[11:0]
[23:12]
HBLKTOG3_4
HBLKTOG4_4
HBLK Toggle Position 3 for V-Sequence 4
HBLK Toggle Position 4 for V-Sequence 4
[11:0]
[23:12]
HBLKTOG5_4
HBLKTOG6_4
HBLK Toggle Position 5 for V-Sequence 4
HBLK Toggle Position 6 for V-Sequence 4
[11:0]
[23:12]
CLPOBTOG1_4
CLPOBTOG2_4
CLPOB Toggle Position 1 for V-Sequence 4
CLPOB Toggle Position 2 for V-Sequence 4
REV. 0
Table XLII.V-Sequence 5 (VSEQ5) Register Map
Register Name
Description
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMASK_5
CLPOBPOL_5
PBLKPOL_5
VPATSEL_5
VMASK_5
HBLKALT_5
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
SelectedV-Pattern Group forV-Sequence 5
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
VPATREPO_5
VPATREPE_5
Number of SelectedV-Pattern Group Repetitions for Odd Lines
Number of SelectedV-Pattern Group Repetitions r Even Lines
[11:0]
[23:12]
VPATSTART_5
HDLEN_5
Start Position in the Line for the SelectedV-Pern Grp
HD Line Length (Number of Pixels) forV-Sence
[11:0]
[23:12]
PBLKTOG1_5
PBLKTOG2_5
PBLKToggle Position 1 forV-Sequenc
PBLKToggle Position 2 forV-Seque5
[11:0]
[23:12]
HBLKTOG1_5
HBLKTOG2_5
HBLKToggle Position 1 forV-Seuence
HBLKToggle Position 2 forVSequence 5
[11:0]
[23:12]
HBLKTOG3_5
HBLKTOG4_5
HBLKToggle Position 3 V-Sequence 5
HBLKToggle Position orV-Suence 5
[11:0]
[23:12]
HBLKTOG5_5
HBLKTOG6_5
HBLKToggle Position 5 fSequenc5
HBLKToggle Position 6 forequce 5
[11:0]
[23:12]
CLPOBTOG1_5
CLPOBTOG2_5
CLPOBTogPosition 1 forV-quence 5
CLPOBToggle osition 2 forV-Sequence 5
Table XLIII.V-SeEQ6) gister Map
Register Name
D
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMASK_6
CLPOBPOL_
PBLKPOL_6
VPATSEL_6
H6
Maskity during HBLK. H1 [0]. H3 [1].
CLPOB StartPolarity
PBK Start Polarity
SetedV-Pattern Group forV-Sequence 6
able Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
Number of SelectedV-Pattern Group Repetitions for Odd Lines
Number of SelectedV-Pattern Group Repetitions for Even Lines
[11:0]
[23:12]
START_6
EN_6
Start Position in the Line for the SelectedV-Pattern Group
HD Line Length (Number of Pixels) forV-Sequence 6
[11:0]
[23:12]
KTOG1_6
BLKTOG2_6
PBLKToggle Position 1 forV-Sequence 6
PBLKToggle Position 2 forV-Sequence 6
[11:0]
[23:12]
HBLKTOG1_6
HBLKTOG2_6
HBLKToggle Position 1 forV-Sequence 6
HBLKToggle Position 2 forV-Sequence 6
[11:0]
[23:12]
HBLKTOG3_6
HBLKTOG4_6
HBLKToggle Position 3 forV-Sequence 6
HBLKToggle Position 4 forV-Sequence 6
[11:0]
[23:12]
HBLKTOG5_6
HBLKTOG6_6
HBLKToggle Position 5 forV-Sequence 6
HBLKToggle Position 6 forV-Sequence 6
[11:0]
[23:12]
CLPOBTOG1_6
CLPOBTOG2_6
CLPOBToggle Position 1 forV-Sequence 6
CLPOBToggle Position 2 forV-Sequence 6
REV. 0
Table XLIV.V-Sequence 7 (VSEQ7) Register Map
Register Name
Description
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMASK_7
CLPOBPOL_7
PBLKPOL_7
VPATSEL_7
VMASK_7
HBLKALT_7
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
SelectedV-Pattern Group forV-Sequence 7
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
VPATREPO_7
VPATREPE_7
Number of SelectedV-Pattern Group Repetitions for Odd Lines
Number of SelectedV-Pattern Group Repetitns for Even Lines
[11:0]
[23:12]
VPATSTART_7
HDLEN_7
Start Position in the Line for the Selected-PatterGroup
HD Line Length (Number of Pixels) foSequce 7
[11:0]
[23:12]
PBLKTOG1_7
PBLKTOG2_7
PBLKToggle Position 1 forV-Seqnce 7
PBLKToggle Position 2 forV-Sence 7
[11:0]
[23:12]
HBLKTOG1_7
HBLKTOG2_7
HBLKToggle Position 1 for-Sequce 7
HBLKToggle Position 2 orV-Sequen7
[11:0]
[23:12]
HBLKTOG3_7
HBLKTOG4_7
HBLKToggle Positio3 forV-Sequence 7
HBLKToggle Posn 4 fo-Sequence 7
[11:0]
[23:12]
HBLKTOG5_7
HBLKTOG6_7
HBLKToggle PositioorV-Seqnce 7
HBLKToggle Position rV-quence 7
[11:0]
[23:12]
CLPOBTOG1_7
CLPOBTOG2_7
CLPOBoggle Position 1 fV-Sequence 7
CLPOBTle Position 2 forV-Sequence 7
Table XLV.V(VSE) Register Map
Register Name
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMAS_8
L_8
8
VPATSEL_8
K_8
LT_8
Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
SelectedV-Pattern Group forV-Sequence 8
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
8
E_8
Number of SelectedV-Pattern Group Repetitions for Odd Lines
Number of SelectedV-Pattern Group Repetitions for Even Lines
[11:0]
[23:12
VPATSTART_8
DLEN_8
Start Position in the Line for the SelectedV-Pattern Group
HD Line Length (Number of Pixels) forV-Sequence 8
[11:0]
[23:12]
PBLKTOG1_8
PBLKTOG2_8
PBLKToggle Position 1 forV-Sequence 8
PBLKToggle Position 2 forV-Sequence 8
[11:0]
[23:12]
HBLKTOG1_8
HBLKTOG2_8
HBLKToggle Position 1 forV-Sequence 8
HBLKToggle Position 2 forV-Sequence 8
[11:0]
[23:12]
HBLKTOG3_8
HBLKTOG4_8
HBLKToggle Position 3 forV-Sequence 8
HBLKToggle Position 4 forV-Sequence 8
[11:0]
[23:12]
HBLKTOG5_8
HBLKTOG6_8
HBLKToggle Position 5 forV-Sequence 8
HBLKToggle Position 6 forV-Sequence 8
[11:0]
[23:12]
CLPOBTOG1_8
CLPOBTOG2_8
CLPOBToggle Position 1 forV-Sequence 8
CLPOBToggle Position 2 forV-Sequence 8
REV. 0
Table XLVI.V-Sequence 9 (VSEQ9) Register Map
Register Name
Description
[1:0]
[2]
[3]
[7:4]
[9:8]
[11:10]
[23:12]
HBLKMASK_9
CLPOBPOL_9
PBLKPOL_9
VPATSEL_9
VMASK_9
HBLKALT_9
Masking Polarity during HBLK. H1 [0]. H3 [1].
CLPOB Start Polarity
PBLK Start Polarity
SelectedV-Pattern Group forV-Sequence 9
Enable Masking of V-Outputs (Specified by FREEZE/RESUME Registers)
[11:0]
[23:12]
VPATREPO_9
VPATREPE_9
Number of SelectedV-Pattern Group Repetitions for Odd Lines
Number of SelectedV-Pattern Group Repetitions r Even Lines
[11:0]
[23:12]
VPATSTART_9
HDLEN_9
Start Position in the Line for the SelectedV-Pern Grp
HD Line Length (Number of Pixels) forV-Sence
[11:0]
[23:12]
PBLKTOG1_9
PBLKTOG2_9
PBLKToggle Position 1 forV-Sequenc
PBLKToggle Position 2 forV-Seque9
[11:0]
[23:12]
HBLKTOG1_9
HBLKTOG2_9
HBLKToggle Position 1 forV-Seuence
HBLKToggle Position 2 forVSequence 9
[11:0]
[23:12]
HBLKTOG3_9
HBLKTOG4_9
HBLKToggle Position 3 V-Sequence 9
HBLKToggle Position orV-Suence 9
[11:0]
[23:12]
HBLKTOG5_9
HBLKTOG6_9
HBLKToggle Position 5 fSequenc9
HBLKToggle Position 6 forequce 9
[11:0]
[23:12]
CLPOBTOG1_9
CLPOBTOG2_9
CLPOBTogPosition 1 forV-quence 9
CLPOBToggle osition 2 forV-Sequence 9
Table XLegisteap
D
Register Name
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
[21:18]
[22]
[23]
VSEQSEL0_0
SWEEP0_0
MULTI0_0
VSEQSEL1_0
V
QSE0
EP3_0
TI3_0
Selecuence for Region 0.
elect Sweep Region for Region 0. 0 = No Sweep, 1= Sweep.
Set Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier.
SetedV-Sequence for Region 1.
ect Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier.
SelectedV-Sequence for Region 2.
Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier.
SelectedV-Sequence for Region 3.
Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier.
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
QSEL4_0
SWEEP4_0
MULTI4_0
VSEQSEL5_0
SWEEP5_0
MULTI5_0
VSEQSEL6_0
SWEEP6_0
MULTI6_0
SelectedV-Sequence for Region 4.
Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier.
SelectedV-Sequence for Region 5.
Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier.
SelectedV-Sequence for Region 6.
Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier.
[23:18]
[11:0]
[23:12]
SCP1_0
SCP2_0
V-Sequence Change Position #1 for Field 0.
V-Sequence Change Position #2 for Field 0.
[11:0]
[23:12]
SCP3_0
SCP4_0
V-Sequence Change Position #3 for Field 0.
V-Sequence Change Position #4 for Field 0.
[11:0]
[23:12]
VDLEN_0
HDLAST_0
VD Field Length (Number of Lines) for Field 0.
HD Line Length (Number of Pixels) for Last Line in Field 0.
REV. 0
Table XLVII. Field 0 Register Map (continued)
Register Name
Description
[3:0]
[9:4]
[21:10]
VPATSECOND_0
SGMASK_0
SGPATSEL_0
Selected Second V-Pattern Group for VSG Active Line.
Masking of VSG Outputs during VSG Active Line.
Selection of VSG Patterns for Each VSG Output.
[11:0]
[23:12]
SGLINE1_0
SGLINE2_0
VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).
[11:0]
[23:12]
SCP5_0
SCP6_0
V-Sequence Change Position #5 for Field 0.
V-Sequence Change Position #6 for Field 0.
Table XLVIII. Field 1 Register Map
Description
Register Name
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
[21:18]
[22]
[23]
VSEQSEL0_1
SWEEP0_1
MULTI0_1
VSEQSEL1_1
SWEEP1_1
MULTI1_1
VSEQSEL2_1
SWEEP2_1
MULTI2_1
VSEQSEL3_1
SWEEP3_1
MULTI3_1
Selected V-Sequence for Region
Select Sweep Region for Regi0= No Swee= Sweep.
Select Multiplier Region for Region = No Multiplier, 1 = Multiplier.
Selected V-Sequence foRegion 1.
Select Sweep Region r Region 1. 0 = No Sweep, 1 = Sweep.
Select Multiplier ion foegion 1. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequencor egion 2.
Select Sweep Region foegion 0 = No Sweep, 1 = Sweep.
Select Multiplier Region fion 2. 0 = No Multiplier, 1 = Multiplier.
Selected -Sequence for Region 3.
Select SweRegion foegion 3. 0 = No Sweep, 1 = Sweep.
SMultipRegn for Region 3. 0 = No Multiplier, 1 = Multiplier.
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
VSEQSEL4_1
SWEEP4_1
MULTI4_1
VSEQSEL5_
SWEEP5_
VSEQSEL
P6_1
6_1
Sequee for Region 4.
Region for Region 4. 0 = No Sweep, 1 = Sweep.
plier Region for Region 4. 0 = No Multiplier, 1 = Multiplier.
Sequence for Region 5.
SeleSweep Region for Region 5. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier.
elected V-Sequence for Region 6.
Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier.
[23:18]
[11:0]
[23:12]
V-Sequence Change Position #1 for Field 1.
V-Sequence Change Position #2 for Field 1.
[11:0]
[23:12
CP4_1
V-Sequence Change Position #3 for Field 1.
V-Sequence Change Position #4 for Field 1.
[11:0]
[23:12]
VDLEN_1
HDLAST_1
VD Field Length (Number of Lines) for Field 1.
HD Line Length (Number of Pixels) for Last Line in Field 1.
[3:0]
[9:4]
[21:10]
VPATSECOND_1
SGMASK_1
SGPATSEL_1
Selected Second V-Pattern Group for VSG Active Line.
Masking of VSG Outputs during VSG Active Line.
Selection of VSG Patterns for Each VSG Output.
[11:0]
[23:12]
SGLINE1_1
SGLINE2_1
VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).
[11:0]
[23:12]
SCP5_1
SCP6_1
V-Sequence Change Position #5 for Field 1.
V-Sequence Change Position #6 for Field 1.
REV. 0
Table XLIX. Field 2 Register Map
Description
Register Name
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
[21:18]
[22]
[23]
VSEQSEL_2
SWEEP0_2
MULTI0_2
VSEQSEL1_2
SWEEP1_2
MULTI1_2
VSEQSEL2_2
SWEEP2_2
MULTI2_2
VSEQSEL3_2
SWEEP3_2
MULTI3_2
Selected V-Sequence for Region 0.
Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 1.
Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 2.
Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 2. 0 = No Mulplier, 1 = Multiplier.
Selected V-Sequence for Region 3.
Select Sweep Region for Region 3. 0 = No Sep, 1 = weep
Select Multiplier Region for Region 3. 0 = Nultier, 1 = Multiplier.
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
VSEQSEL4_2
SWEEP4_2
MULTI4_2
VSEQSEL5_2
SWEEP5_2
MULTI5_2
VSEQSEL6_2
SWEEP6_2
MULTI6_2
Selected V-Sequence for Region 4.
Select Sweep Region for Region 4. No Sweep, 1 eep.
Select Multiplier Region for Regin 4. 0 No Multiplier, 1 = Multiplier.
Selected V-Sequence for Regin 5.
Select Sweep Region for Ron 5. 0 = No Swp, 1 = Sweep.
Select Multiplier Region or Regi5. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence foegio6.
Select Sweep Region for Rn 6. 0 = o Sweep, 1 = Sweep.
Select Multiplier Region for ion 0 = No Multiplier, 1 = Multiplier.
[23:18]
[11:0]
[23:12]
SCP1_2
SCP2_2
V-Sequence Chge Position #1 for Field 2.
V-Seque ChanPositn #2 for Field 2.
[11:0]
[23:12]
SCP3_2
SCP4_2
Vange Pition #3 for Field 2.
Vge Position #4 for Field 2.
[11:0]
[23:12]
VDLEN0_2
HDLAST_2
V(Number of Lines) for Field 2.
HD th (Number of Pixels) for Last Line in Field 2.
[3:0]
[9:4]
[21:10]
_2
SGMASK_2
SGPATSEL_2
ected Second V-Pattern Group for VSG Active Line.
Ming of VSG Outputs during VSG Active Line.
Setion of VSG Patterns for Each VSG Output.
[11:0]
[23:12]
VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).
[11:0]
[23:12]
SCP6_
V-Sequence Change Position #5 for Field 2.
V-Sequence Change Position #6 for Field 2.
Table L. Field 3 Register Map
Description
gister Name
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
[21:18]
[22]
[23]
VSEQSEL_3
SWEEP0_3
MULTI0_3
VSEQSEL1_3
SWEEP1_3
MULTI1_3
VSEQSEL2_3
SWEEP2_3
MULTI2_3
VSEQSEL3_3
SWEEP3_3
MULTI3_3
Selected V-Sequence for Region 0.
Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 1.
Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 2.
Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 3.
Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier.
REV. 0
Table L. Field 3 Register Map (continued)
Register Name
Description
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
VSEQSEL4_3
SWEEP4_3
MULTI4_3
VSEQSEL5_3
SWEEP5_3
MULTI5_3
VSEQSEL6_3
SWEEP6_3
MULTI6_3
Selected V-Sequence for Region 4.
Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 5.
Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 6.
Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier.
[23:18]
[11:0]
[23:12]
SCP1_3
SCP2_3
V-Sequence Change Position #1 for Fi3.
V-Sequence Change Position #2 for Field
[23:12]
[11:0]
SCP3_3
SCP4_3
V-Sequence Change Position #3 r Field 3.
V-Sequence Change Position 4 Field 3.
[11:0]
[23:12]
VDLEN_3
HDLAST_3
VD Field Length (Number of Lines) Field 3.
HD Line Length (Numer of Pixels) for st Line in Field 3.
[3:0]
[9:4]
[21:10]
VPATSECOND_3
SGMASK_3
SGPATSEL_3
Selected Second V-attern Goup for VSG Active Line.
Masking of VSG Outs uring VSG Active Line.
Selection of VSG Pattfor EaVSG Output.
[11:0]
[23:12]
SGLINE1_3
SGLINE2_3
VSG Ace Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).
[11:0]
[23:12]
SCP5_3
SCP6_3
V-Sequence hange Ption #5 for Field 3.
nce Cge osition #6 for Field 3.
TRegister Map
Dtion
Register Nme
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
[21:18
[22]
[23]
VSEQSE_4
SWEEP0_
MI0_4
EL1_4
V_4
SW_4
MULTI2_4
SEQSEL3_4
WEEP3_4
MULTI3_4
Selected V-Sequence for Region 0.
elect Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 1.
Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 2.
Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 3.
Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier.
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
VSEQSEL4_4
SWEEP4_4
MULTI4_4
VSEQSEL5_4
SWEEP5_4
MULTI5_4
VSEQSEL6_4
SWEEP6_4
MULTI6_4
Selected V-Sequence for Region 4.
Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 5.
Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier..
Selected V-Sequence for Region 6.
Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier.
[23:18]
[11:0]
[23:12]
SCP1_4
SCP2_4
V-Sequence Change Position #1 for Field 4.
V-Sequence Change Position #2 for Field 4.
[11:0]
[23:12]
SCP3_4
SCP4_4
V-Sequence Change Position #3 for Field 4.
V-Sequence Change Position #4 for Field 4.
REV. 0
Table LI. Field 4 Register Map (continued)
Register Name
Description
[11:0]
[23:12]
VDLEN_4
HDLAST_4
VD Field Length (Number of Lines) for Field 4.
HD Line Length (Number of Pixels) for Last Line in Field 4.
[3:0]
[9:4]
[21:10]
VPATSECOND_4
SGMASK_4
SGPATSEL_4
Selected Second V-Pattern Group for VSG Active Line.
Masking of VSG Outputs during VSG Active Line.
Selection of VSG Patterns for Each VSG Output.
[11:0]
[23:12]
SGLINE1_4
SGLINE2_4
VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).
[11:0]
[23:12]
SCP5_4
SCP6_4
V-Sequence Change Position #5 for Field 4.
V-Sequence Change Position #6 for Field 4.
Table LII. Field 5 Register Map
Description
Register Name
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
[21:18]
[22]
[23]
VSEQSEL0_5
SWEEP0_5
MULTI0_5
VSEQSEL1_5
SWEEP1_5
MULTI1_5
VSEQSEL2_5
SWEEP2_5
MULTI2_5
VSEQSEL3_5
SWEEP3_5
MULTI3_5
Selected V-Sequence for Region 0.
Select Sweep Region for Reon 0. 0 = No Sp, 1 = Sweep.
Select Multiplier Region r Regio0. 0 = No Multiplier, 1 = Multiplier.
Selected V-Sequence fRegio1.
Select Sweep Region for Rn 1. 0 = o Sweep, 1 = Sweep.
Select Multiplier Region for gion 0 = No Multiplier, 1 = Multiplier.
Selected V-Squence for Regio
Select Sweep gion for Region 2. 0 = No Sweep, 1 = Sweep.
Select Multiplier gion foegion 2. 0 = No Multiplier, 1 = Multiplier.
Selequencor egion 3.
Sgion fRegion 3. 0 = No Sweep, 1 = Sweep.
SRegion for Region 3. 0 = No Multiplier, 1 = Multiplier.
[3:0]
[4]
[5]
[9:6]
[10]
[11]
[15:12]
[16]
[17]
VSEQSEL4_5
SWEEP4_5
MULTI4_5
VSEQSEL5_
SWEEP5_5
MUL
VS5
S
MU
Sence for Region 4.
Selecegion for Region 4. 0 = No Sweep, 1 = Sweep
Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier.
Seted V-Sequence for Region 5.
Set Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep.
Sect Multiplier Region for Region 5. 0 =No Multiplier, 1 = Multiplier.
Selected V-Sequence for Region 6.
Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep.
Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier.
[23:18]
[11:0]
[23:12]
1_5
_5
V-Sequence Change Position #1 for Field 5.
V-Sequence Change Position #2 for Field 5.
[11:0]
[23:12]
_5
P4_5
V-Sequence Change Position #3 for Field 5.
V-Sequence Change Position #4 for Field 5.
[11:0]
[23:12]
VDLEN_5
HDLAST_5
VD Field Length (Number of Lines) for Field 5.
HD Line Length (Number of Pixels) for Last Line in Field 5.
[3:0]
[9:4]
[21:10]
VPATSECOND_5
SGMASK_5
SGPATSEL_5
Selected Second V-Pattern Group for VSG Active Line.
Masking of VSG Outputs during VSG Active Line.
Selection of VSG Patterns for Each VSG Output.
[11:0]
[23:12]
SGLINE1_5
SGLINE2_5
VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).
[11:0]
[23:12]
SCP5_5
SCP6_5
V-Sequence Change Position #5 for Field 5.
V-Sequence Change Position #6 for Field 5.
REV. 0
56-Lead Lead Frame Chip Scale Package [LFCSP]
8 mm Body
(CP-56)
0.30
8.00
BSC SQ
0.23
0.18
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
43
56
1
42
PIN 1
INDICATOR
6.25
6.10
5.
7.75
BSC SQ
BOTTOM
VIEW
TOP
VIEW
0.50
0.40
0.30
29
28
14
15
0.25 MIN
6.50
REF
0.80 MAX
0.65 NOM
1.00
0.90
0.80
12 MAX
0.05 MAX
0.02 NOM
0.20
REF
COPLANARITY
0.08
0.50 BSC
SEATING
PLANE
COMPLIANT TO JEDEC ANDARDS MO-220-VL
REV. 0
相关型号：
ADA-4543-BLK
0MHz - 2500MHz RF/MICROWAVE WIDE BAND LOW POWER AMPLIFIER, PLASTIC, SC-70, SOT-343, 4 PIN
AVAGO
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