ADA4062-2ARMZ-RL7 [ADI]
DUAL OP-AMP, 5000uV OFFSET-MAX, 1.4MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8;
| 型号： | ADA4062-2ARMZ-RL7 |
| 厂家： | 
ADI |
| 描述： | DUAL OP-AMP, 5000uV OFFSET-MAX, 1.4MHz BAND WIDTH, PDSO8, ROHS COMPLIANT, MO-187AA, MSOP-8 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power JFET-Input Op Amps
ADA4062-2/ADA4062-4
FEATURES
PIN CONFIGURATIONS
Low input bias current: 50 pA maximum
Offset voltage
1.5 mV maximum for B grade (ADA4062-2 SOIC package)
2.5 mV maximum for A grade
Offset voltage drift: 5 μV/°C typical
Slew rate: 3.3 V/μs typical
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
ADA4062-2
TOP VIEW
(Not to Scale)
OUT B
–IN B
+IN B
Figure 1. 8-Lead Narrow-Body SOIC and 8-Lead MSOP
CMRR: 90 dB typical
Low supply current: 165 μA typical
High input impedance
Unity-gain stable
–IN A
8 OUT B
2
5 V to 15 V dual-supply operation
Packaging
ADA4062-2
TOP VIEW
(Not to Scale)
+IN A 3
7
–IN B
8-lead SOIC, 8-lead MSOP, 10-lead LFCSP, 14-lead TSSOP, and
16-lead LFCSP packages
NC = NO CONNECT
APPLICATIONS
Figure 2. 10-Lead LFCSP
Power controls and monitoring
Active filters
Industrial/process controls
Body probe electronics
Data acquisition
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT A
–IN A
+IN A
V+
OUT D
–IN D
+IN D
V–
ADA4062-4
TOP VIEW
(Not to Scale)
Integrators
Input buffering
+IN B
–IN B
OUT B
+IN C
–IN C
OUT C
8
GENERAL DESCRIPTION
Figure 3. 14-Lead TSSOP
The ADA4062-2 and ADA4062-4 are dual and quad JFET-input
amplifiers with industry-leading performance. They offer lower
power, offset voltage, drift, and ultralow bias current. The
ADA4062-2 B grade (SOIC package) features a typical low offset
voltage of 0.5 mV, an offset drift of 5 μV/°C, and a bias current
of 2 pA.
1
12 –IN D
–IN A
+IN A
V+
ADA4062-4
+IN D
V–
2
3
4
11
10
9
TOP VIEW
The ADA4062 family is ideal for various applications, including
process controls, industrial and instrumentation equipment,
active filtering, data conversion, buffering, and power control
and monitoring. With a low supply current of 165 μA per
amplifier, they are well suited for lower power applications.
(Not to Scale)
+IN B
+IN C
NOTES
1. NC = NO CONNECT.
2. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO V–.
The ADA4062 family is also specified for the extended industrial
temperature range of −40°C to +125°C. The ADA4062-2 is
available in lead-free, 8-lead SOIC, 8-lead MSOP, and 10-lead
LFCSP (1.6 mm × 1.3 mm × 0.55 mm) packages, while the
ADA4062-4 is available in lead-free, 14-lead TSSOP and
16-lead LFCSP packages.
Figure 4. 16-Lead LFCSP
Table 1. Low Power Op Amps
Precision
CMOS
Precision
High Bandwidth
High
Bandwidth
Single
Dual
Quad
AD8663
AD8667
AD8669
AD8641
AD8642
AD8643
AD8682
AD8684
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
ADA4062-2/ADA4062-4
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Applications Information.............................................................. 15
Notch Filter ................................................................................. 15
High-Side Signal Conditioning ................................................ 15
Micropower Instrumentation Amplifier................................. 15
Phase Reversal ............................................................................ 16
Schematic......................................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Power Sequencing ........................................................................ 5
REVISION HISTORY
2/10—Rev. A to Rev. B
7/09—Rev. 0 to Rev. A
Added 16-Lead LFCSP Package........................................Universal
Changes to Features Section, General Description Section, and
Table 1 ................................................................................................ 1
Changes to Offset Voltage Drift Parameter, Table 2 .................... 3
Changes to Table 4............................................................................ 5
Changes to Typical Performance Characteristics Layout............ 6
Added Figure 6 and Figure 9; Renumbered Sequentially ........... 6
Changes to Figure 7, Figure 8, and Figure 10 ............................... 6
Changes to Figure 25 and Figure 28............................................... 9
Changes to Figure 37 and Figure 40............................................. 11
Changes to Figure 41 to Figure 46................................................ 12
Changes to Figure 47 and Figure 50............................................. 13
Changes to Figure 53 to Figure 58................................................ 14
Changes to Notch Filter Section and Micropower Instrumentation
Amplifier Section............................................................................ 15
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 20
Added ADA4062-4.............................................................Universal
Added 14-Lead TSSOP Package.......................................Universal
Added 10-Lead LFCSP Package .......................................Universal
Changes to Features Section and Table 1 .......................................1
Changes to Table 2.............................................................................3
Changes to Thermal Resistance Section ........................................5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9..................6
Changes to Figure 37 and Figure 40............................................. 11
Changes to Figure 41 and Figure 44............................................. 12
Changes to Figure 47, Figure 48, Figure 50, and Figure 51....... 13
Added Figure 49 and Figure 52; Renumbered Sequentially ..... 13
Changes to Figure 57 and Figure 59............................................. 15
Changes to Phase Reversal Section and Figure 61..................... 16
Changes to Figure 63...................................................................... 17
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide.......................................................... 19
10/08—Revision 0: Initial Version
Rev. B | Page 2 of 20
ADA4062-2/ADA4062-4
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VSY
= 15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
B Grade (ADA4062-2, 8-Lead SOIC Only)
0.5
1.5
3
2.5
5
mV
mV
mV
mV
μV/°C
pA
−40°C ≤ TA ≤ +125°C
A Grade
0.75
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Offset Voltage Drift
Input Bias Current
∆VOS/∆T
IB
5
2
50
5
−40°C ≤ TA ≤ +125°C
nA
Input Offset Current
IOS
0.5
25
2.5
+15
pA
nA
V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
Input Voltage Range
−11.5
Common-Mode Rejection Ratio
B Grade (ADA4062-2, 8-Lead SOIC Only)
CMRR
VCM = −11.5 V to +11.5 V
−40°C ≤ TA ≤ +125°C
VCM = −11.5 V to +11.5 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = −10 V to +10 V
−40°C ≤ TA ≤ +125°C
80
80
73
70
76
72
90
90
83
dB
dB
dB
dB
dB
dB
TΩ
pF
pF
A Grade
Large-Signal Voltage Gain
AVO
Input Resistance
RIN
CINDM
CINCM
10
1.5
4.8
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
VOH
VOL
RL = 10 kΩ to VCM
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ to VCM
13
12.5
13.5
V
V
V
Output Voltage Low
−13.8
−13
−40°C ≤ TA ≤ +125°C
−12.5
V
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
20
1
mA
Ω
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
B Grade (ADA4062-2, 8-Lead SOIC Only)
PSRR
VSY
−40°C ≤ TA ≤ +125°C
VSY 4 V to 18 V
−40°C ≤ TA ≤ +125°C
IO = 0 mA
=
4 V to 18 V
80
80
74
70
90
dB
dB
dB
dB
μA
μA
A Grade
=
90
Supply Current per Amplifier
ISY
165
220
260
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
SR
tS
RL = 10 kΩ, CL = 100 pF, AV = 1
To 0.1%, VIN = 10 V step, CL = 100 pF,
RL = 10 kΩ, AV = 1
3.3
3.5
V/μs
μs
Gain Bandwidth Product
Phase Margin
Channel Separation (ADA4062-2 Only)
Channel Separation (ADA4062-4 Only)
GBP
ΦM
CS
RL = 10 kΩ, AV = 1
RL = 10 kΩ, AV = 1
f = 1 kHz
1.4
78
135
130
MHz
Degrees
dB
CS
f = 1 kHz
dB
Rev. B | Page 3 of 20
ADA4062-2/ADA4062-4
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
1.5
36
5
μV p-p
nV/√Hz
fA/√Hz
Rev. B | Page 4 of 20
ADA4062-2/ADA4062-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. It was
measured using a standard 4-layer board.
Parameter
Rating
18 V
VSY
Supply Voltage
Input Voltage
Differential Input Voltage
Input Current
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
VSY
10 mA
Table 4. Thermal Resistance
Package Type
θJA
θJC
45
45
46
35
12
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
8-Lead SOIC
120
142
132
112
75
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
8-Lead MSOP
10-Lead LFCSP
14-Lead TSSOP
16-Lead LFCSP
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
POWER SEQUENCING
The supply voltages of the op amps must be established
simultaneously with, or before, any input signals are applied. If
this is not possible, the input current must be limited to 10 mA.
ESD CAUTION
Rev. B | Page 5 of 20
ADA4062-2/ADA4062-4
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
70
280
V
V
= ±5V
= 0V
V
V
= ±15V
= 0V
SY
SY
CM
CM
BASED ON 600 OP AMPS
60
50
40
30
20
10
0
240 BASED ON 600 OP AMPS
200
160
120
80
40
0
–4
–3
–2
–1
0
1
2
3
4
–4
–2
0
–3
–2
–1
0
1
2
3
4
V
(mV)
V
(mV)
OS
OS
Figure 5. Input Offset Voltage Distribution
Figure 8. Input Offset Voltage Distribution
40
30
20
10
0
40
30
20
10
0
ADA4062-2 ONLY
= ±5V
ADA4062-2 ONLY
SY
–40°C ≤ T ≤ +125°C
BASED ON 200 OP AMPS
V
V
= ±15V
SY
–40°C ≤ T ≤ +125°C
A
A
BASED ON 200 OP AMPS
–2
0
2
4
6
8
10
0
2
4
6
8
10
TCV (µV/°C)
OS
TCV
(µV/°C)
OS
Figure 6. Input Offset Voltage Drift Distribution
Figure 9. Input Offset Voltage Drift Distribution
25
20
15
10
5
25
20
15
10
5
ADA4062-4 ONLY
ADA4062-4 ONLY
= ±5V
–40°C ≤ T ≤ 125°C
V
= ±15V
V
SY
SY
–40°C ≤ T ≤ 125°C
BASED ON 200 OP AMPS
BASED ON 200 OP AMPS
0
0
0
2
4
6
8
10
12
14
16
18
2
4
6
8
10
12
14
16
18
TCV (µV/°C)
TCV (µV/°C)
OS
OS
Figure 10. Input Offset Voltage Drift Distribution
Figure 7. Input Offset Voltage Drift Distribution
Rev. B | Page 6 of 20
ADA4062-2/ADA4062-4
5
4
5
4
V
= ±5V
V
= ±15V
SY
SY
3
3
2
2
1
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
–4
–3
–2
–1
0
1
2
3
4
5
–15 –12
–9
–6
–3
0
3
6
9
12
15
V
(V)
V
(V)
CM
CM
Figure 11. Input Offset Voltage vs. Common-Mode Voltage
Figure 14. Input Offset Voltage vs. Common-Mode Voltage
10000
1000
100
10
10000
1000
100
10
V
SY
= ±15V
V
= ±5V
SY
1
1
0.1
–50
0.1
–50
–25
0
25
50
75
100
125
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Input Bias Current vs. Temperature
Figure 15. Input Bias Current vs. Temperature
5
4
3
2
1
0
3
2
V
= ±15V
V
= ±5V
SY
SY
1
0
–1
–2
–12 –10 –8 –6 –4 –2
0
2
4
6
8
10 12 14 16
–3
–2
–1
0
1
2
3
4
5
V
(V)
V
(V)
CM
CM
Figure 16. Input Bias Current vs. Common-Mode Voltage
Figure 13. Input Bias Current vs. Common-Mode Voltage
Rev. B | Page 7 of 20
ADA4062-2/ADA4062-4
10
10
V
= ±15V
V
= ±5V
SY
SY
V+ – V
OH
V+ – V
OH
1
1
V
– V–
V
– V–
OL
OL
0.1
0.01
0.1
0.01
0.1
1
LOAD CURRENT (mA)
10
100
0.1
1
LOAD CURRENT (mA)
10
100
Figure 17. Output Voltage to Supply Rail vs. Load Current
Figure 20. Output Voltage to Supply Rail vs. Load Current
220
200
+125°C
200
180
160
140
120
100
80
190
180
170
160
150
140
130
120
110
100
+85°C
V
= ±15V
SY
+25°C
–40°C
V
= ±5V
SY
60
40
20
0
0
2
4
6
8
10
12
14
16
18
–50
–25
0
25
50
75
100
125
150
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
Figure 18. Supply Current/Amp vs. Supply Voltage
Figure 21. Supply Current/Amp vs. Temperature
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
V
R
= ±15V
V
R
= ±5V
SY
L
SY
= 10kΩ
= 10kΩ
L
V+ – V
OH
V+ – V
OH
V
– V–
OL
V
– V–
OL
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 19. Output Voltage to Supply Rail vs. Temperature
Figure 22. Output Voltage to Supply Rail vs. Temperature
Rev. B | Page 8 of 20
ADA4062-2/ADA4062-4
120
100
80
120
100
80
120
100
80
120
V
= ±5V
V
= ±15V
SY
SY
PHASE
100
80
PHASE
60
60
60
60
40
40
40
40
GAIN
GAIN
20
20
20
20
0
0
0
0
–20
–40
–60
–20
–40
–60
–20
–40
–60
–20
–40
–60
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. Open-Loop Gain and Phase vs. Frequency
Figure 26. Open-Loop Gain and Phase vs. Frequency
50
50
V
= ±5V
V
= ±15V
SY
SY
A
= +100
= +10
A
= +100
= +10
V
V
V
V
40
30
40
30
A
A
20
20
10
10
A
= +1
A
= +1
V
V
0
0
–10
–20
–10
–20
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. Closed-Loop Gain vs. Frequency
Figure 27. Closed-Loop Gain vs. Frequency
1000
100
10
1000
100
10
V
= ±5V
V
= ±15V
SY
SY
A
= +100
= +10
V
A
= +100
= +10
V
A
A
V
V
1
1
A
= +1
V
A
= +1
V
0.1
100
0.1
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. Output Impedance vs. Frequency
Figure 28. Output Impedance vs. Frequency
Rev. B | Page 9 of 20
ADA4062-2/ADA4062-4
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
= ±5V
V
= ±15V
SY
SY
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29. CMRR vs. Frequency
Figure 32. CMRR vs. Frequency
120
140
120
100
80
V
= ±5V
V
= ±15V
SY
SY
100
80
60
40
20
0
PSRR+
60
PSRR+
40
PSRR–
PSRR–
20
0
–20
–20
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. PSRR vs. Frequency
Figure 33. PSRR vs. Frequency
60
50
40
30
20
10
0
60
50
40
30
20
10
0
V
= ±5V
V
= ±15V
SY
V
L
SY
V
L
A
R
= +1
A
R
= +1
= 10kΩ
= 10kΩ
10
100
1000
10000
10
100
1000
10000
C
(pF)
C
(pF)
L
L
Figure 31. Small-Signal Overshoot vs. Load Capacitance
Figure 34. Small-Signal Overshoot vs. Load Capacitance
Rev. B | Page 10 of 20
ADA4062-2/ADA4062-4
V
V
A
R
C
= ±5V
= 4V p-p
= +1
V
V
A
R
C
= ±15V
= 20V p-p
= +1
SY
IN
SY
IN
V
L
L
V
L
L
= 10kΩ
= 100pF
= 10kΩ
= 100pF
TIME (4µs/DIV)
TIME (10µs/DIV)
Figure 35. Large-Signal Transient Response
Figure 38. Large-Signal Transient Response
V
V
A
R
C
= ±5V
V
V
A
R
C
= ±15V
= 100mV p-p
= +1
SY
IN
V
L
L
SY
IN
= 100mV p-p
= +1
V
L
L
= 10kΩ
= 100pF
= 10kΩ
= 100pF
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 36. Small-Signal Transient Response
Figure 39. Small-Signal Transient Response
4
2
0
4
2
0
V
A
= ±15V
= –10
SY
V
A
= ±5V
= –10
SY
V
V
INPUT
INPUT
OUTPUT
0
OUTPUT
0
–5
–2
–4
–6
–10
–15
–20
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 40. Negative Overload Recovery
Figure 37. Negative Overload Recovery
Rev. B | Page 11 of 20
ADA4062-2/ADA4062-4
2
2
0
V
A
= ±5V
= –10
V
= ±15V
A = –10
V
SY
SY
V
INPUT
0
INPUT
–2
–2
15
10
5
4
2
OUTPUT
OUTPUT
0
0
–2
–5
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 41. Positive Overload Recovery
Figure 44. Positive Overload Recovery
INPUT
INPUT
+20mV
0V
+100mV
0V
OUTPUT
OUTPUT
–20mV
–100mV
ERROR BAND
ERROR BAND
V
C
R
= ±5V
= 100pF
= 10kΩ
V
C
R
= ±15V
= 100pF
= 10kΩ
SY
L
L
SY
L
L
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 42. Positive Settling Time to 0.1%
Figure 45. Positive Settling Time to 0.1%
V
= ±5V
= 100pF
= 10kΩ
V
C
R
= ±15V
SY
L
L
SY
L
L
C
R
= 100pF
INPUT
INPUT
= 10kΩ
+20mV
0V
+100mV
0V
OUTPUT
OUTPUT
–20mV
–100mV
ERROR BAND
ERROR BAND
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 43. Negative Settling Time to 0.1%
Figure 46. Negative Settling Time to 0.1%
Rev. B | Page 12 of 20
ADA4062-2/ADA4062-4
1000
100
10
1000
100
10
V
= ±15V
V
= ±5V
SY
SY
1
10
100
1k
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 47. Voltage Noise Density
Figure 50. Voltage Noise Density
V
= ±5V
V
= ±15V
SY
SY
TIME (1s/DIV)
TIME (1s/DIV)
Figure 48. 0.1 Hz to 10 Hz Noise
Figure 51. 0.1 Hz to 10 Hz Noise
0
–20
0
–20
V
V
R
= ±5V
= 5V p-p
= 10kΩ
V
V
R
= ±15V
= 10V p-p
= 10kꢀ
SY
100kꢀ
100kꢀ
SY
IN
IN
1kꢀ
1kꢀ
L
L
ADA4062-2 ONLY
ADA4062-2 ONLY
–40
–40
R
R
L
L
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
100
1k
10k
100k
100
1k
10k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
Figure 49. Channel Separation vs. Frequency (ADA4062-2 Only)
Figure 52. Channel Separation vs. Frequency (ADA4062-2 Only)
Rev. B | Page 13 of 20
ADA4062-2/ADA4062-4
0
–20
0
V
V
R
= ±5V
= 5V p-p
= 10kꢀ
V
V
R
= ±15V
= 10V p-p
= 10kꢀ
100kꢀ
SY
100kꢀ
SY
IN
IN
1kꢀ
1kꢀ
–20
–40
L
L
ADA4062-4 ONLY
ADA4062-4 ONLY
–40
R
R
L
L
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
100
1k
10k
FREQUENCY (Hz)
100k
100
1k
10k
100k
FREQUENCY (Hz)
Figure 56. Channel Separation vs. Frequency (ADA4062-4 Only)
Figure 53. Channel Separation vs. Frequency (ADA4062-4 Only)
100
10
V
= ±5V
S
f = 1kHz
= 10kꢀ
R
L
10
1
1
0.1
0.1
0.01
0.01
V
= ±15V
S
f = 1kHz
= 10kꢀ
R
L
0.001
0.001
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
AMPLITUDE (V rms)
AMPLITUDE (V rms)
Figure 57 THD + N vs. Amplitude
Figure 54. THD + N vs. Amplitude
1
1
V
V
R
= ±5V
= 0.5V rms
= 10kꢀ
V
V
R
= ±15V
SY
IN
S
= 2V rms
IN
L
= 10kꢀ
L
0.1
0.1
0.01
0.001
0.01
0.001
10
100
1k
10k
100k
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 58. THD + N vs. Frequency
Figure 55. THD + N vs. Frequency
Rev. B | Page 14 of 20
ADA4062-2/ADA4062-4
APPLICATIONS INFORMATION
NOTCH FILTER
HIGH-SIDE SIGNAL CONDITIONING
Many applications require the sensing of signals near the positive
rail. The ADA4062-x can be used in high-side current sensing
applications. Figure 61 shows a high-side signal conditioning
circuit using the ADA4062-x. The ADA4062-x has an input
common-mode range that includes the positive supply (−11.5 V ≤
A notch filter rejects a specific interfering frequency and can be
implemented using a single op amp. Figure 59 shows a 60 Hz
notch filter that uses the twin-T network with the ADA4062-x
configured as a voltage follower. The ADA4062-x works as a buffer
that provides high input resistance and low output impedance.
The low bias current (2 pA typical) and high input resistance
(10 TΩ typical) of the ADA4062-x enable large resistors and small
capacitors to be used.
VCM ≤ +15 V). In the circuit, the voltage drop across a low value
resistor, such as the 0.1 Ω shown in Figure 61, is amplified by a
factor of 5 using the ADA4062-x.
0.1ꢀ
+15V
Alternatively, different combinations of resistor and capacitor
values can be used to achieve the desired notch frequency.
However, the major drawback to this circuit topology is the
need to ensure that all the resistors and capacitors be closely
matched. If they are not closely matched, the notch frequency
offset and drift cause the circuit to attenuate at a frequency
other than the ideal notch frequency.
500kꢀ
R
V
L
100kꢀ
+15V
100kꢀ
500kꢀ
O
ADA4062-x
–15V
Figure 61. High-Side Signal Conditioning
Therefore, to achieve the desired performance, 1% or better
component tolerances are usually required. In addition, a notch
filter requires an op amp with a bandwidth of at least 100× to
200× the center frequency. Hence, using the ADA4062-x with
a bandwidth of 1.4 MHz is excellent for a 60 Hz notch filter.
Figure 60 shows the frequency response of the notch filter. At
60 Hz, the notch filter has about 50 dB attenuation of signal.
MICROPOWER INSTRUMENTATION AMPLIFIER
The ADA4062-2 is a dual amplifier and is perfectly suited for
applications that require lower supply currents. For supply
voltages of 15 V, the supply current per amplifier is 165 μA
typical. The ADA4062-2 also offers a typical low offset voltage
drift of 5 μV/°C and a very low bias current of 2 pA, which
make it well suited for instrumentation amplifiers.
+V
SY
Figure 62 shows the classic 2-op-amp instrumentation amplifier
with four resistors using the ADA4062-2. The key to high CMRR
for this instrumentation amplifier are resistors that are well
matched to both the resistive ratio and relative drift. For true
difference amplification, matching of the resistor ratio is very
important, where R3/R4 = R1/R2. Assuming perfectly matched
resistors, the gain of the circuit is 1 + R2/R1, which is approximately
100. Tighter matching of two op amps in one package, as is the
case with the ADA4062-2, offers a significant boost in performance
over the classical 3-op-amp configuration. Overall, the circuit only
requires about 330 μA of supply current.
R1
R2
V
O
804kꢀ
804kꢀ
IN
ADA4062-x
C3
6.6nF
–V
R3
SY
402kꢀ
C1
3.3nF
C2
3.3nF
1
fO
=
2π R
C
1
1
R1 = R2 = 2R3
C3
C1 = C2 =
2
R3
10.1kꢀ
Figure 59. Notch Filter Circuit
R2
1Mꢀ
20
10
+15V
R4
+15V
1Mꢀ
R1
10.1kꢀ
1/2
0
V
1/2
O
ADA4062-2
–10
–20
–30
–40
–50
–60
–70
–80
ADA4062-2
–15V
V1
V2
–15V
V
= 100(V2 – V1)
TYPICAL: 0.5mV < │V2 – V1│< 135mV
TYPICAL: –13.8V < V < +13.5V
USE MATCHED RESISTORS
O
O
Figure 62. Micropower Instrumentation Amplifier
10
100
1k
FREQUENCY (Hz)
Figure 60. Frequency Response of the Notch Filter
Rev. B | Page 15 of 20
ADA4062-2/ADA4062-4
V
PHASE REVERSAL
IN
V
= ±15V
SY
Phase reversal occurs in some amplifiers when the input common-
mode voltage range is exceeded. When the voltage driving the
input to these amplifiers exceeds the maximum input common-
mode voltage range, the output of the amplifiers changes polarity.
Most JFET input amplifiers have phase reversal if either input
exceeds the input common-mode range.
V
OUT
For the ADA4062-x, the output does not phase reverse if one
or both of the inputs exceeds the input voltage range but remains
within the positive supply rail and 0.5 V above the negative
supply rail. In other words, for an application with a supply
voltage of 15 V, the input voltage can be as high as +15 V
without any output phase reversal. However, when the voltage
of the inputs is driven beyond −14.5 V, phase reversal occurs
due to saturation of the input stage leading to forward biasing
of the gate-drain diode. Phase reversal in ADA4062-x can be
prevented by using a Schottky diode to clamp the input terminals
to each other. In the simple buffer circuit in Figure 63, D1
protects the op amp against phase reversal, and R limits the
input current that flows into the op amp.
TIME (40µs/DIV)
Figure 64. No Phase Reversal
+V
SY
R
10kꢀ
D1
IN5711
V
O
ADA4062-x
–V
SY
Figure 63. Phase Reversal Solution Circuit
Rev. B | Page 16 of 20
ADA4062-2/ADA4062-4
SCHEMATIC
V+
OUT
–IN
+IN
V–
Figure 65. Simplified Schematic of the ADA4062-x
Rev. B | Page 17 of 20
ADA4062-2/ADA4062-4
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 66. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 67. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
0.55
0.40
0.30
0.20 DIA
TYP
1.30
PIN 1
IDENTIFIER
9
1
4
1.60
0.35
0.30
0.25
0.40
BSC
6
BOTTOM VIEW
TOP VIEW
0.20 BSC
0.60
0.55
0.50
0.05 MAX
0.02 NOM
SEATING
PLANE
Figure 68. 10-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
1.30 mm × 1.60 mm, Body, Ultra Thin Quad
(CP-10-10)
Dimensions shown in millimeters
Rev. B | Page 18 of 20
ADA4062-2/ADA4062-4
5.10
5.00
4.90
14
8
7
4.50
4.40
4.30
6.40
BSC
1
PIN 1
0.65 BSC
1.05
1.00
0.80
1.20
MAX
0.20
0.09
0.75
8°
0°
0.15
0.05
COPLANARITY
0.10
0.60
0.45
SEATING
PLANE
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 69. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.50
BSC
1
4
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
8
5
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 70. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
Rev. B | Page 19 of 20
ADA4062-2/ADA4062-4
ORDERING GUIDE
Model1
Temperature Range
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Package Option
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
Branding
A25
A25
ADA4062-2ARMZ
ADA4062-2ARMZ-RL
ADA4062-2ARMZ-RL7
ADA4062-2ARZ
ADA4062-2ARZ-R7
ADA4062-2ARZ-RL
ADA4062-2BRZ
ADA4062-2BRZ-R7
ADA4062-2BRZ-RL
ADA4062-2ACPZ-R2
ADA4062-2ACPZ-RL
ADA4062-2ACPZ-R7
ADA4062-4ARUZ
ADA4062-4ARUZ-RL
ADA4062-4ACPZ-R2
ADA4062-4ACPZ-R7
ADA4062-4ACPZ-RL
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
A25
8-Lead SOIC_N
R-8
10-Lead LFCSP_UQ
10-Lead LFCSP_UQ
10-Lead LFCSP_UQ
14-Lead TSSOP
CP-10-10
CP-10-10
CP-10-10
RU-14
RU-14
CP-16-22
CP-16-22
CP-16-22
J
J
J
14-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
A2K
A2K
A2K
1 Z = RoHS Compliant Part.
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07670-0-2/10(B)
Rev. B | Page 20 of 20
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