ADA4075-2ACPZ-RL [ADI]
Ultralow Noise Amplifier at Lower Power; 超低噪声放大器的低功耗
| 型号： | ADA4075-2ACPZ-RL |
| 厂家： | 
ADI |
| 描述： | Ultralow Noise Amplifier at Lower Power |
| 文件： | 总24页 (文件大小：1576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise Amplifier at Lower Power
Data Sheet
ADA4075-2
FEATURES
PIN CONFIGURATIONS
Ultralow noise: 2.8 nV/√Hz at 1 kHz typical
Ultralow distortion: 0.0002% typical
Low supply current: 1.8 mA per amplifier typical
Offset voltage: 1 mV maximum
OUTA
–INA
+INA
V–
1
2
3
4
8
7
6
5
V+
ADA4075-2
TOP VIEW
(Not to Scale)
OUTB
–INB
+INB
Bandwidth: 6.5 MHz typical
Slew rate: 12 V/μs typical
Dual-supply operation: 4.5 V to 18 V
Unity-gain stable
Figure 1. 8-Lead SOIC
Extended industrial temperature range
8-lead SOIC and 2 mm × 2 mm LFCSP packages
OUTA
1
8
V+
ADA4075-2
TOP VIEW
(Not to Scale)
–INA
+INA
V–
2
3
4
7
6
5
OUTB
–INB
+INB
APPLICATIONS
Precision instrumentation
Professional audio
Active filters
Figure 2. 8-Lead, 2 mm × 2 mm LFCSP
Low noise amplifier front end
Integrators
GENERAL DESCRIPTION
Table 1. Low Noise Precision Op Amps
The ADA4075-2 is a dual, high performance, low noise operational
amplifier combining excellent dc and ac characteristics on the
Analog Devices, Inc., iPolar® process. The iPolar process is an
advanced bipolar technology implementing vertical junction
isolation with lateral trench isolation. This allows for low noise
performance amplifiers in smaller die size at faster speed and
lower power. Its high slew rate, low distortion, and ultralow
noise make the ADA4075-2 ideal for high fidelity audio and
high performance instrumentation applications. It is also
especially useful for lower power demands, small enclosures,
and high density applications. The ADA4075-2 is specified for
the −40°C to +125°C temperature range and is available in a
standard SOIC package and a 2 mm × 2 mm LFCSP package.
Supply 44 V
36 V
12 V to 16 V
AD8665
OP162
5 V
Single
OP27
AD8671
AD8675
AD8597
ADA4004-1
AD797
AD8605
AD8655
AD8691
Dual
OP275
AD8672
AD8676
AD8599
ADA4004-2
AD8674
ADA4004-4
AD8666
OP262
AD8606
AD8656
AD8692
Quad
AD8668
OP462
AD8608
AD8694
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2011 Analog Devices, Inc. All rights reserved.
ADA4075-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information.............................................................. 16
Input Protection ......................................................................... 16
Total Harmonic Distortion ....................................................... 16
Phase Reversal ............................................................................ 16
DAC Output Filter...................................................................... 17
Balanced Line Driver................................................................. 18
Balanced Line Receiver.............................................................. 19
Low Noise Parametric Equalizer.............................................. 20
Schematic......................................................................................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Power Sequencing ........................................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
12/11—Rev. A to Rev. B
Changes to Features Section............................................................ 1
8/09—Rev. 0 to Rev. A
Added 8-Lead LFCSP_WD...............................................Universal
Changes to Table 1............................................................................ 1
Changes to Table 2............................................................................ 3
Changes to Table 3............................................................................ 4
Changes to Table 4 and Table 5....................................................... 5
Changes to Figure 3, Figure 5, Figure 6, and Figure 8 ................. 6
Added Figure 4 and Figure 7; Renumbered Sequentially ........... 6
Added Figure 9 and Figure 12......................................................... 7
Changes to Figure 10, Figure 11, Figure 13, and Figure 14......... 7
Changes to Figure 16, Figure 17, Figure 19, and Figure 20......... 8
Changes to Figure 22 and Figure 25............................................... 9
Changes to Figure 36...................................................................... 11
Changes to Figure 54...................................................................... 14
Changes to and Moved Figure 57 and Figure 60 to ................... 15
Changes to Figure 59 and Figure 62............................................. 15
Changes to Input Protection Section and Phase
Reversal Section.............................................................................. 16
Changes to DAC Output Filter Section ....................................... 17
Changes to Figure 67...................................................................... 18
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 22
10/08—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADA4075-2
SPECIFICATIONS
VSY = ±±1 V, VCM = 0 V, TA = 21°C, SOIC package, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
Min
Typ
0.2
30
5
Max
Unit
VOS
IB
1
mV
mV
nA
nA
nA
nA
V
dB
dB
dB
dB
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
1.2
100
150
50
75
+12.5
Input Bias Current
Input Offset Current
IOS
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
VCM = −12.5 V to +12.5 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, VO = −11 V to +11 V
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
−12.5
110
106
114
108
112
106
CMRR
AVO
118
117
117
Large Signal Voltage Gain
RL = 600 Ω, VO = −10 V to +10 V
−40°C ≤ TA ≤ +125°C
dB
dB
Offset Voltage Drift
∆VOS/∆T
RINDM
RINCM
CINDM
CINCM
−40°C ≤ TA ≤ +125°C
0.3
1.5
500
2.4
2.1
μV/°C
MΩ
MΩ
pF
Input Resistance, Differential Mode
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
pF
VOH
RL = 2 kΩ to GND
12.8
12.5
12.4
12
15
14
13
V
V
V
V
V
V
V
V
−40°C ≤ TA ≤ +125°C
RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
12.8
15.8
−14
VSY
=
18 V, RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
Output Voltage Low
VOL
−13.6
−13
−13
−12.5
−16
−13.6
−16.6
V
V
V
VSY
=
18 V, RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
−15
V
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
40
0.1
mA
Ω
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY
−40°C ≤ TA ≤ +125°C
VSY 4.5 V to 18 V, IO = 0 mA
=
4.5 V to 18 V
106
100
110
1.8
dB
dB
mA
mA
Supply Current per Amplifier
=
2.25
3.35
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
ΦM
RL = 2 kΩ, AV = 1
12
3
6.5
60
V/μs
μs
MHz
Degrees
To 0.01%, VIN = 10 V step, RL = 1 kΩ
RL = 1 MΩ, CL = 35 pF, AV = 1
RL = 1 MΩ, CL = 35 pF, AV = 1
THD + NOISE
Total Harmonic Distortion and Noise
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
THD + N
RL = 2 kΩ, AV = 1, VIN = 3 V rms, f = 1 kHz
0.0002
%
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
60
2.8
1.2
nV p-p
nV/√Hz
pA/√Hz
Rev. B | Page 3 of 24
ADA4075-2
Data Sheet
VSY = ±±1 V, VCM = 0 V, TA = 21°C, LFCSP package, unless otherwise noted.
Table 3.
Parameter
Symbol
Conditions
Min
Typ
0.3
30
5
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
VOS
IB
1
mV
mV
nA
nA
nA
nA
V
dB
dB
dB
dB
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
1.5
100
150
50
75
+12.5
Input Bias Current
Input Offset Current
IOS
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
VCM = −12.5 V to +12.5 V
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ, VO = −11 V to +11 V
−40°C ≤ TA ≤ +125°C
Input Voltage Range
Common-Mode Rejection Ratio
−12.5
110
106
110
102
108
100
CMRR
AVO
116
117
117
Large Signal Voltage Gain
RL = 600 Ω, VO = −10 V to +10 V
−40°C ≤ TA ≤ +125°C
dB
dB
Offset Voltage Drift
∆VOS/∆T
RINDM
RINCM
CINDM
CINCM
−40°C ≤ TA ≤ +125°C
3
μV/°C
MΩ
MΩ
pF
Input Resistance, Differential Mode
Input Resistance, Common Mode
Input Capacitance, Differential Mode
Input Capacitance, Common Mode
OUTPUT CHARACTERISTICS
Output Voltage High
1.5
500
2.4
2.1
pF
VOH
RL = 2 kΩ to GND
12.8
12.5
12.4
12
15
14
13
V
V
V
V
V
V
V
V
−40°C ≤ TA ≤ +125°C
RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
12.8
15.8
−14
VSY
=
18 V, RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
RL = 2 kΩ to GND
−40°C ≤ TA ≤ +125°C
RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
Output Voltage Low
VOL
−13.6
−13
−13
−12.5
−16
−13.6
−16.6
V
V
V
VSY
=
18 V, RL = 600 Ω to GND
−40°C ≤ TA ≤ +125°C
−15
V
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
ISC
ZOUT
40
0.1
mA
Ω
f = 1 kHz, AV = 1
Power Supply Rejection Ratio
PSRR
ISY
VSY
−40°C ≤ TA ≤ +125°C
VSY 4.5 V to 18 V, IO = 0 mA
=
4.5 V to 18 V
100
95
104
1.8
dB
dB
mA
mA
Supply Current per Amplifier
=
2.25
3.35
−40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
tS
GBP
ΦM
RL = 2 kΩ, AV = 1
12
3
6.5
60
V/μs
μs
MHz
Degrees
To 0.01%, VIN = 10 V step, RL = 1 kΩ
RL = 1 MΩ, CL = 35 pF, AV = 1
RL = 1 MΩ, CL = 35 pF, AV = 1
THD + NOISE
Total Harmonic Distortion and Noise
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
THD + N
RL = 2 kΩ, AV = 1, VIN = 3 V rms, f = 1 kHz
0.0002
%
en p-p
en
in
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 1 kHz
60
2.8
1.2
nV p-p
nV/√Hz
pA/√Hz
Rev. B | Page 4 of 24
Data Sheet
ADA4075-2
ABSOLUTE MAXIMUM RATINGS
Table 4.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
was measured using a standard 4-layer board.
Parameter
Rating
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
20 V
VSY
10 mA
1.2 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
Table 5. Thermal Resistance
Package Type
θJA
θJC
43
40
Unit
°C/W
°C/W
8-Lead SOIC
8-Lead LFCSP
158
115
POWER SEQUENCING
Lead Temperature (Soldering, 60 sec) 300°C
The op amp supplies must be established simultaneously with,
or before, any input signals that are applied. If this is not possible,
limit the input current to 10 mA.
1 The input pins have clamp diodes to the power supply pins.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 5 of 24
ADA4075-2
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
250
200
150
100
50
250
V
V
= ±5V
= 0V
V
V
= ±15V
= 0V
SY
SY
CM
CM
BASED ON 600 OP AMPS
SOIC PACKAGE
BASED ON 600 OP AMPS
SOIC PACKAGE
200
150
100
50
0
0
–1.0
–0.5
0
0.5
1.0
–1.0
–0.5
0
0.5
1.0
1.0
2.0
V
(mV)
V
(mV)
OS
OS
Figure 3. Input Offset Voltage Distribution
Figure 6. Input Offset Voltage Distribution
100
80
60
40
20
0
100
80
60
40
20
0
V
V
= ±15V
= 0V
V
V
= ±5V
= 0V
SY
SY
CM
CM
BASED ON 300 OP AMPS
LFCSP PACKAGE
BASED ON 300 OP AMPS
LFCSP PACKAGE
–1.0
–0.5
0
0.5
–1.0
–0.5
0
0.5
1.0
V
(mV)
V
(mV)
OS
OS
Figure 4. Input Offset Voltage Distribution
Figure 7. Input Offset Voltage Distribution
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
V
= ±15V
V
= ±5V
SY
SY
–40°C ≤ T ≤ +125°C
–40°C ≤ T ≤ +125°C
A
A
BASED ON 200 OP AMPS
SOIC PACKAGE
BASED ON 200 OP AMPS
SOIC PACKAGE
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
2.0
–2.0 –1.6 –1.2 –0.8 –0.4
0
0.4
0.8
1.2
1.6
TCV (μV/°C)
TCV (μV/°C)
OS
OS
Figure 8. Input Offset Voltage Drift Distribution
Figure 5. Input Offset Voltage Drift Distribution
Rev. B | Page 6 of 24
Data Sheet
ADA4075-2
40
40
V
V
= ±15V
= 0V
V
V
= ±5V
= 0V
SY
SY
CM
CM
35
30
25
20
35
30
25
20
BASED ON 300 OP AMPS
LFCSP PACKAGE
BASED ON 300 OP AMPS
LFCSP PACKAGE
15
10
5
15
10
5
0
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
TCV (µV/°C)
OS
TCV (µV/°C)
OS
Figure 9. Input Offset Voltage Drift Distribution
Figure 12. Input Offset Voltage Drift Distribution
300
200
100
0
300
200
100
0
V
= ±15V
SY
BASED ON 60 OP AMPS
V
= ±5V
SY
BASED ON 60 OP AMPS
–100
–200
–300
–100
–200
–300
–15
–10
–5
0
5
10
15
–5
–4
–3
–2
–1
0
1
2
3
4
5
V
(V)
CM
V
(V)
CM
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
Figure 13. Input Offset Voltage vs. Common-Mode Voltage
80
100
80
60
40
20
0
V
= ±15V
V
= ±5V
SY
SY
60
40
20
0
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Input Bias Current vs. Temperature
Figure 14. Input Bias Current vs. Temperature
Rev. B | Page 7 of 24
ADA4075-2
Data Sheet
60
60
50
40
30
20
10
0
V
= ±15V
V
= ±5V
SY
SY
50
40
30
20
10
0
–15
–10
–5
0
5
10
15
–4
–3
–2
–1
0
1
2
3
4
V
(V)
V
(V)
CM
CM
Figure 15. Input Bias Current vs. Input Common-Mode Voltage
Figure 18. Input Bias Current vs. Input Common-Mode Voltage
10
10
V
= ±15V
SY
V
= ±5V
SY
V+ – V
OH
V+ – V
OH
1
1
V
– V–
V
– V–
OL
OL
0.1
0.001
0.1
0.001
0.01
0.1
1
10
100
0.01
0.1
1
10
100
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 16. Output Voltage to Supply Rail vs. Load Current
Figure 19. Output Voltage to Supply Rail vs. Load Current
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
V
R
= ±15V
= 2kΩ
SY
V
R
= ±5V
SY
= 2kΩ
L
V+ – V
OH
L
V+ – V
OH
V
– V–
OL
V
– V–
OL
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Output Voltage to Supply Rail vs. Temperature
Figure 20. Output Voltage to Supply Rail vs. Temperature
Rev. B | Page 8 of 24
Data Sheet
ADA4075-2
140
120
100
80
140
120
100
80
140
120
100
80
140
V
= ±15V
V
= ±5V
SY
SY
120
100
80
PHASE
PHASE
60
60
60
60
GAIN
40
40
40
40
20
20
20
20
GAIN
0
0
0
0
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
–20
–40
–60
–80
–100
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. Open-Loop Gain and Phase vs. Frequency
Figure 24. Open-Loop Gain and Phase vs. Frequency
50
50
V
= ±15V
V
= ±5V
SY
SY
A
= +100
= +10
A
= +100
= +10
V
V
V
V
40
30
40
30
A
A
20
20
10
10
A
= +1
A
= +1
V
V
0
0
–10
–20
–10
–20
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. Closed-Loop Gain vs. Frequency
Figure 25. Closed-Loop Gain vs. Frequency
1k
100
10
1k
100
10
V
= ±15V
V
= ±5V
SY
SY
A
= +10
A
= +10
V
V
A
= +100
A
= +100
V
V
A
= +1
V
A
= +1
V
1
1
0.1
0.1
0.01
0.01
0.001
0.001
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. Output Impedance vs. Frequency
Figure 23. Output Impedance vs. Frequency
Rev. B | Page 9 of 24
ADA4075-2
Data Sheet
140
120
100
80
140
120
100
80
V
= ±15V
V
= ±5V
SY
SY
60
60
40
40
20
20
0
100
0
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. CMRR vs. Frequency
Figure 27. CMRR vs. Frequency
120
100
80
120
100
80
V
= ±15V
V
= ±5V
SY
SY
60
60
PSRR–
PSRR+
PSRR–
PSRR+
40
40
20
20
0
0
–20
10
–20
10
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 31. PSRR vs. Frequency
Figure 28. PSRR vs. Frequency
40
35
30
25
20
15
10
5
40
V
A
R
= ±5V
V
A
R
= ±15V
SY
V
L
SY
V
L
= +1
= +1
= 2kΩ
35
30
25
20
15
10
5
= 2kΩ
0
10
0
10
100
1000
100
1000
CAPACITANCE (pF)
CAPACITANCE (pF)
Figure 32. Small Signal Overshoot vs. Load Capacitance
Figure 29. Small Signal Overshoot vs. Load Capacitance
Rev. B | Page 10 of 24
Data Sheet
ADA4075-2
V
V
A
R
C
= ±5V
V
V
A
R
C
= ±15V
= 20V p-p
= +1
SY
IN
V
L
L
SY
IN
= 7V p-p
= +1
V
L
L
= 2kΩ
= 100pF
= 2kΩ
= 100pF
0V
0V
TIME (4µs/DIV)
TIME (4µs/DIV)
Figure 33. Large Signal Transient Response
Figure 36. Large Signal Transient Response
V
V
A
R
C
= ±15V
= 100mV p-p
= +1
SY
IN
V
V
A
R
C
= ±5V
SY
IN
V
L
L
= 100mV p-p
= +1
V
L
L
= 2kΩ
= 100pF
= 2kΩ
= 100pF
0V
0V
TIME (10µs/DIV)
TIME (10µs/DIV)
Figure 34. Small Signal Transient Response
Figure 37. Small Signal Transient Response
4
2
0
4
2
0
V
= ±15V
V
= ±5V
SY
SY
INPUT
INPUT
OUTPUT
OUTPUT
0
0
–5
–2
–4
–6
–8
–10
–15
–20
TIME (1µs/DIV)
TIME (1µs/DIV)
Figure 35. Negative Overload Recovery
Figure 38. Negative Overload Recovery
Rev. B | Page 11 of 24
ADA4075-2
Data Sheet
4
2
4
V
= ±5V
V
= ±15V
SY
SY
2
INPUT
INPUT
0
0
–2
–2
15
10
5
4
2
OUTPUT
OUTPUT
0
0
–2
–4
–5
–10
TIME (1µs/DIV)
TIME (1µs/DIV)
Figure 42. Positive Overload Recovery
Figure 39. Positive Overload Recovery
V
= ±5V
V
= ±15V
SY
SY
INPUT
INPUT
+6mV
+10mV
OUTPUT
OUTPUT
0V
0V
ERROR BAND
ERROR BAND
–10mV
–6mV
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 43. Positive Settling Time to 0.01%
Figure 40. Positive Settling Time to 0.01%
V
= ±5V
V
= ±15V
SY
SY
INPUT
INPUT
+6mV
+10mV
0V
ERROR BAND
OUTPUT
OUTPUT
0V
ERROR BAND
–10mV
–6mV
TIME (2µs/DIV)
TIME (2µs/DIV)
Figure 44. Negative Settling Time to 0.01%
Figure 41. Negative Settling Time to 0.01%
Rev. B | Page 12 of 24
Data Sheet
ADA4075-2
10
10
V
= ±15V
V
= ±5V
SY
SY
1
1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 45. Voltage Noise Density
Figure 48. Voltage Noise Density
10
10
V
= ±5V
R
V
= ±15V
R
SY
S1
SY
S1
R
R
S2
S2
UNCORRELATED
= 0ꢀ
UNCORRELATED
= 0ꢀ
R
R
S1
S1
1
1
CORRELATED
= R
CORRELATED
= R
R
R
S1
S2
S1
S2
0.1
0.1
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 49. Current Noise Density
Figure 46. Current Noise Density
V
= ±5V
V
= ±15V
SY
SY
TIME (1s/DIV)
TIME (1s/DIV)
Figure 47. 0.1 Hz to 10 Hz Noise
Figure 50. 0.1 Hz to 10 Hz Noise
Rev. B | Page 13 of 24
ADA4075-2
Data Sheet
8
6
5
4
3
2
1
0
6
V
= ±15V
= ±5V
SY
+125°C
+85°C
V
SY
4
2
0
+25°C
–40°C
4
6
8
10
12
14
16
18
–50
–25
0
25
50
75
100
125
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
Figure 54. Supply Current vs. Temperature
Figure 51. Supply Current vs. Supply Voltage
10
1
10
1
V
= ±5V
V
= ±15V
SY
SY
f = 1kHz
f = 1kHz
0.1
0.1
0.01
0.01
0.001
0.0001
0.00001
600ꢀ
0.001
0.0001
0.00001
600ꢀ
2kꢀ
2kꢀ
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
0.1
1
10
AMPLITUDE (V rms)
AMPLITUDE (V rms)
Figure 52. THD + Noise vs. Amplitude
Figure 55. THD + Noise vs. Amplitude
1
0.1
1
0.1
V
IN
= ±15V
= 3V rms
V
V
= ±5V
= 1.5V rms
SY
SY
V
IN
0.01
0.01
600ꢀ
0.001
0.0001
0.001
600ꢀ
2kꢀ
2kꢀ
0.0001
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 53. THD + Noise vs. Frequency
Figure 56. THD + Noise vs. Frequency
Rev. B | Page 14 of 24
Data Sheet
ADA4075-2
0
0
–20
V
V
R
= ±15V
= 10V p-p
= 2kꢀ
V
V
R
= ±5V
= 5V p-p
= 2kꢀ
100kꢀ
SY
IN
SY
IN
100kꢀ
1kꢀ
1kꢀ
–20
L
L
–40
–40
R
R
L
L
–60
–60
–80
–80
–100
–120
–100
–120
–140
–140
100
1k
10k
FREQUENCY (Hz)
100k
100
1k
10k
FREQUENCY (Hz)
100k
Figure 57. Channel Separation vs. Frequency
Figure 60. Channel Separation vs. Frequency
10
1
1
0.1
V
IN
= ±18V
= 8V rms
V
= ±18V
SY
SY
V
f = 1kHz
0.1
0.01
0.01
0.001
0.0001
0.00001
0.001
0.0001
0.00001
600ꢀ
600ꢀ
2kꢀ
2kꢀ
0.0001
0.001
0.01
0.1
1
10
100
10
100
1k
10k
100k
AMPLITUDE (V rms)
FREQUENCY (Hz)
Figure 61. THD + Noise vs. Frequency
Figure 58. THD + Noise vs. Amplitude
10
2.5
2.0
1.5
1.0
0.5
0
V
= ±18V
SY
V
R
= ±18V
= 2kꢀ
SY
L
V+ – V
OH
V+ – V
OH
1
V
– V–
OL
V
– V–
OL
0.1
0.001
0.01
0.1
1
10
100
–50
–25
0
25
50
75
100
125
LOAD CURRENT (mA)
TEMPERATURE (°C)
Figure 59. Output Voltage to Supply Rail vs. Temperature
Figure 62. Output Voltage to Supply Rail vs. Load Current
Rev. B | Page 15 of 24
ADA4075-2
Data Sheet
APPLICATIONS INFORMATION
1
0.1
INPUT PROTECTION
To prevent base-emitter junction breakdown from occurring in
the input stage of the ADA4075-2 when a very large differential
voltage is applied, the inputs are clamped by the internal diodes
to 1.2 ꢀ. To preserve the ultralow voltage noise feature of the
ADA4075-2, the commonly used internal current-limiting
resistors in series with the inputs are not used.
V
= ±4V
SY
0.01
R
= 2kꢀ
L
V
= 1.5V rms
IN
V
= ±15V
= 2kꢀ
= 3V rms
SY
In small signal applications, current limiting is not required;
however, in applications where the differential voltage of the
ADA4075-2 exceeds 1.2 ꢀ, large currents may flow through
these diodes. Employ external current-limiting resistors as
shown in Figure 63 to reduce the input currents to less than
10 mA. Note that depending on the value of these resistors,
the total voltage noise will most likely be degraded. For example,
a 1 kΩ resistor at room temperature has a thermal noise of
4 nꢀ/√Hz, whereas the ADA4075-2 has an ultralow voltage
noise of only 2.8 nꢀ/√Hz typical.
R
V
L
0.001
0.0001
IN
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 64. THD + Noise vs. Frequency
PHASE REVERSAL
An undesired phenomenon, phase reversal (also known as phase
inversion) occurs in many op amps when one or both of the
inputs are driven beyond the specified input common-mode
voltage (ꢀICM) range, in effect reversing the polarity of the output.
In some cases, phase reversal can induce lockups and cause
equipment damage as well as self destruction.
ADA4075-2
R1
R2
2
3
1
The ADA4075-2 incorporates phase reversal prevention circuitry
that clamps the output to 2 ꢀ typical from the supply rails when
one or both inputs exceed the ꢀICM range. Figure 65 shows the
input/output waveforms of the ADA4075-2 configured as a unity-
gain buffer for a supply voltage of 15 ꢀ.
Figure 63. Input Protection
TOTAL HARMONIC DISTORTION
The total harmonic distortion + noise (THD + N) of the
ADA4075-2 is 0.0002% typical with a load resistance of 2 kꢁ.
Figure 64 shows the performance of the ADA4075-2 driving a
2 kꢁ load with supply voltages of 4 ꢀ and 15 ꢀ. Notice that
there is more distortion for the supply voltage of 4 ꢀ than for a
supply voltage of 15 ꢀ. Therefore, it is important to operate the
ADA4075-2 at a supply voltage greater than 5 ꢀ for optimum
distortion. The THD + noise graphs for supply voltages of 5 ꢀ
and 18 ꢀ are available in Figure 56 and Figure 61.
V
= ±15V
SY
V
IN
V
OUT
TIME (40µs/DIV)
Figure 65. No Phase Reversal
Rev. B | Page 16 of 24
Data Sheet
ADA4075-2
For a DAC output filter, an op amp with reasonable slew rate and
bandwidth is required. The ADA4075-2 has a high slew rate of the
12 V/μs and a relatively wide bandwidth of 6.5 MHz. The cutoff
frequency of the low-pass filter is approximately 167 kHz. In
addition, the 100 kΩ − 47 μF RC network provides ac coupling
to block out the dc components at the output.
DAC OUTPUT FILTER
The ultralow voltage noise, low distortion, and high slew rate of
the ADA4075-2 make it an ideal choice for professional audio
signal processing. Figure 66 shows the ADA4075-2 used in a
typical audio DAC output filter configuration. The differential
outputs of the DAC are fed into the ADA4075-2. The ADA4075-2
is configured as a differential Sallen-Key filter. It operates as an
external low-pass filter to remove high frequency noise present
on the output pins of the DAC. It also provides differential-to-
single-ended conversion from the differential outputs of the DAC.
11kΩ
68pF
11kΩ
3.01kΩ
47µF
DAC OUTN
DAC OUTP
100Ω
1/2
OUTPUT
100kΩ
5.62kΩ
1.5kΩ
270pF
2.2nF
ADA4075-2
560pF
150pF
5.62kΩ
Figure 66. Typical DAC Output Filter Circuit (Differential)
Rev. B | Page 17 of 24
ADA4075-2
Data Sheet
Finally, even with these precautions, it is vital that the positive
feedback be accurately controlled. This is partly achieved by
using 1% resistors. In addition, the following setup procedure
ensures that the positive feedback does not become excessive:
BALANCED LINE DRIVER
The circuit of Figure 67 shows a balanced line driver designed
for audio use. Such drivers are intended to mimic an output
transformer in operation, whereby the common-mode voltage
can be impressed by the load. Furthermore, either output can be
shorted to ground in single-ended applications without affecting
the overall operation.
1. Set R11 to its midposition (or short the ends together,
whichever is easier) and temporarily short the negative
output to ground.
2. Apply a 10 ꢀ p-p sine wave at approximately 1 kHz to the
input and adjust R7 to provide 930 mꢀ p-p at TEST (see
Figure 67).
3. Remove the short from the negative output (and across
R11, if used) and adjust R11 until the output waveforms
are symmetric.
Circuits of this type use positive and negative feedback to obtain a
high common-mode output impedance, and they are somewhat
notorious for component sensitivity and susceptibility to latch-up.
This circuit uses several techniques to avoid spurious behavior.
First, the 4-op-amp arrangement ensures that the input impedance
is load independent (the input impedance can become negative
with some configurations). Note that the output op amps are
packaged with the input op amps to maximize drive capability.
The overall gain of the driver is equal to 2, which provides an
extra 6 dB of headroom in balanced differential mode. The
output noise is about −109 dBꢀ in a 20 kHz bandwidth.
Second, the positive feedback is ac-coupled by C2 and C3, which
eliminates the need for offset trim. Because the circuit is ac-coupled
at the input, these capacitors do not have significant dc voltage
across them, thus tantalum types of capacitors can be used.
C5
IN
50pF
R5
C1
R4
10µF
A1
1/2
4.7kꢀ
4.7kꢀ
A2
R1
R13
10kꢀ
OUT+
1/2
100ꢀ
ADA4075-2
ADA4075-2
R18
4.7kꢀ
R7
250ꢀ
R6
R8
R9
R2
4.7kꢀ
4.7kꢀ
100ꢀ 4.7kꢀ
FEEDBACK
TRIM
C4
50pF
R3
SYMMETRY
TRIM
TEST
C3
10µF
C2
10µF
R10
R12
4.7kꢀ
C6
4.7kꢀ
4.7kꢀ
R11
250ꢀ
A3
1/2
50pF
A4
R14
ADA4075-2
OUT–
1/2
R15
100ꢀ
4.7kꢀ
ADA4075-2
R16
R17
4.7kꢀ
100ꢀ
NOTES
1. ALL RESISTORS SHOULD HAVE 1% TOLERANCE.
2. A1/A2 IN SAME PACKAGE; A3/A4 IN SAME PACKAGE.
Figure 67. Balanced Line Driver
Rev. B | Page 18 of 24
Data Sheet
ADA4075-2
Note that A3 is not in the signal path, and almost any op amp
works well here. Although it may seem as though the inverting
output should be noisier than the noninverting one, they are in
fact symmetric at about −111 dBV (20 kHz bandwidth).
BALANCED LINE RECEIVER
Figure 68 depicts a unity-gain balanced line receiver capable of
a high degree of hum rejection. The CMRR is approximately
given by
Sometimes an overall gain of ½ is desired to provide an extra
6 dB of differential input headroom. This can be attained by
reducing R3 and R4 to 5 kΩ and increasing R9 to 22 kΩ.
R1 R4
R2 R3
20 log
10
Therefore, R1 to R4 should be close tolerance components to
obtain the best possible CMRR without adjustment. The presence
of A2 ensures that the impedances are symmetric at the two inputs
(unlike many other designs), and, as a bonus, A2 also provides
a complementary output. A3 raises the common-mode input
impedance from approximately 7.5 kΩ to approximately 70 kΩ,
reducing the degradation of CMRR due to mismatches in source
impedance.
C2
50pF
R3
OUT+
C3
10kΩ
50pF
R6
R1
5kΩ
A1
IN–
IN+
R5
A2
5kΩ
1/2
R2
5kΩ
OUT–
1/2
5kΩ
ADA4075-2
ADA4075-2
R7
5.6kΩ
R8
5.6kΩ
R4
10kΩ
C1
22µF
A3*
(NON-POLAR)
R9
R10
11kΩ
11kΩ
*A3 REDUCES THE DEGRADATION OF CMRR
(SEE THE BALANCED LINE RECEIVER SECTION FOR MORE DETAILS).
Figure 68. Balanced Line Receiver
Rev. B | Page 19 of 24
ADA4075-2
Data Sheet
The bandwidth control adjusts the Q from 2.9 to about 11. The
overall noise is setting dependent, but with all controls centered,
it is about −124 dBV in a ±2 kHz bandwidth. Such a low noise
level can obviate the need for a bypass switch in many applications.
LOW NOISE PARAMETRIC EQUALIZER
The circuit in Figure 69 is a reciprocal parametric equalizer
yielding ±±2 dB of cut or boost with variable bandwidth and
frequency. The frequency control range is 6.9:1, with the geometric
mean center frequency conveniently occurring at the midpoint
of the potentiometer setting. The center frequency is equal to
48 Hz/Ct, where Ct is the value of C1 and C± in microfarads.
47µF
6.2kΩ
6.2kΩ
620Ω
IN
OUT
1/2
ADA4075-2
100Ω
BOOST
CUT
BANDWIDTH
1kΩ
5kΩ
2.7kΩ
1.5kΩ
ADA4075-2
C1*
C2*
1.5kΩ
2.5kΩ
1/2
1.3kΩ
1.3kΩ
2.5kΩ
2.5kΩ
620Ω
2.5kΩ
1/2
1/2
ADA4075-2
ADA4075-2
620Ω
FREQUENCY (GANGED POTENTIOMETER)
*THE CENTER FREQUENCY IS AFFECTED BY THE VALUE OF C1 AND C2
(SEE THE LOW NOISE PARAMETRIC EQUALIZER SECTION FOR MORE DETAILS).
Figure 69. Low Noise Parametric Equalizer
Rev. B | Page 20 of 24
Data Sheet
SCHEMATIC
ADA4075-2
V+
OUTA/
OUTB
–INA/
–INB
+INA/
+INB
V–
Figure 70. Simplified Schematic
Rev. B | Page 21 of 24
ADA4075-2
Data Sheet
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 71. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
0.30
0.25
0.18
2.00
BSC SQ
0.50 BSC
8
1
5
4
0.65
0.60
0.55
PIN 1 INDEX
AREA
PIN 1
INDICATOR
TOP VIEW
BOTTOM VIEW
0.60
0.55
0.50
0.05 MAX
0.02 NOM
SEATING
PLANE
0.20 REF
Figure 72. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
2 mm × 2 mm Body, Very Very Thin, Dual Lead
(CP-8-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4075-2ARZ
ADA4075-2ARZ-R7
ADA4075-2ARZ-RL
ADA4075-2ACPZ-R7
ADA4075-2ACPZ-RL
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead LFCSP_WD
8-Lead LFCSP_WD
Package Option
Branding
R-8
R-8
R-8
CP-8-6
CP-8-6
A0
A0
1 Z = RoHS Compliant Part.
Rev. B | Page 22 of 24
Data Sheet
NOTES
ADA4075-2
Rev. B | Page 23 of 24
ADA4075-2
NOTES
Data Sheet
©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07642-0-12/11(B)
Rev. B | Page 24 of 24
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