ADA4097-1 [ADI]
50 V, 130 kHz, 32.5 μA, Robust, Over-The-Top Precision Op Amp;
| 型号： | ADA4097-1 |
| 厂家： | 
ADI |
| 描述： | 50 V, 130 kHz, 32.5 μA, Robust, Over-The-Top Precision Op Amp |
| 文件： | 总27页 (文件大小：517K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
50 V, 130 kHz, 32.5 μA, Robust,
Over-The-Top Precision Op Amp
ADA4097-1
Data Sheet
FEATURES
GENERAL DESCRIPTION
Ultrawide common-mode input range: −VS − 0.1 V to −VS + 70 V
Wide power supply voltage range: +3 V to +50 V (to 25 V for PSRR)
Low power supply current: 32.5 μA (typical)
Low input offset voltage: 60 μV maximum
Low input offset voltage drift: 1 μVꢀ/C maximum (B grade)
Low input voltage noise
The ADA4097-1 is a robust, precision, rail-to-rail input and output
operational amplifier (op amp) with inputs that operate from −VS
to +VS and beyond, which is referred to in this data sheet as Over-
The-Top™. The device features offset voltages of <60 μV, input bias
currents (IB) of <0.3 nA, and can operate on single or split supplies
that range from 3 V to 50 V. The ADA4097-1 draws 32.5 μA of
supply current.
6 Hz typical 1ꢀf noise corner
1000 nV p-p typical at 0.1 Hz to 10 Hz
The ADA4097-1 Over-The-Top input stage has robust input
protection features for abusive environments. The inputs can
tolerate up to 80 V of differential voltage without damage or
degradation to dc accuracy. The operating common-mode input
range extends from rail-to-rail and beyond, up to 70 V > –VS,
independent of the +VS supply.
GBP: 130 kHz typical for fTEST = 250 Hz
Slew rate: 0.1 Vꢀμs typical at ΔVOUT = 4 V
Low power supply current shutdown: 20 μA maximum
Low input offset current: 300 pA maximum
Large signal voltage gain: 120 dB minimum for ΔVOUT = 4 V
CMRR: 120 dB minimum at VCM = −0.1 V to +70 V
PSRR: 123 dB minimum at VSY = +3 V to 25 V
Input overdrive tolerant with no phase reversal
2 kV HBM and 1.25 kV FICDM
The ADA4097-1 is unity-gain stable and can drive loads requiring
up to 20 mA. The device can also drive capacitive loads as large as
200 pF. The amplifier is available with low power shutdown.
Wide temperature range: −55/C to +150/C (H grade)
6-lead TSOT package
The ADA4097-1 is available in a standard, 6-lead, thin small
outline transistor (TSOT) package.
APPLICATIONS
Industrial sensor conditioning
Supply current sensing
Battery and power supply monitoring
Front-end amplifiers in abusive environments
4 mA to 20 mA transmitters
TYPICAL APPLICATION CIRCUIT
5
15V
1.5V
ADA4097-1
5V
0.1Ω
3
10W
M1
V
= 1.5V TO 70V
BAT
100Ω
BSS123LT1G
SHDN
100Ω
1
0
V
OUT
1V/A
LOAD
10mA TO 1A
1kΩ
–1
–3
Figure 1. 1 V/A Over-The-Top Current Sense Application
(VBAT Is the Battery Voltage.)
–5
–7
0.001
0.01
0.1
1
LOAD CURRENT (A)
Figure 2. Output Error vs. Load Current
Rev. 0
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Technical Support
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ADA4097-1
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output.......................................................................................... 20
Shutdown Pin (SHDN).............................................................. 20
Applications Information.............................................................. 21
Large Resistor Gain Operation................................................. 21
Recommended Values for Various Gains................................ 21
Noise ............................................................................................ 22
Distortion .................................................................................... 22
Power Dissipation and Thermal Shutdown............................ 23
Circuit Layout Considerations ................................................. 23
Power Supply Bypassing............................................................ 23
Grounding................................................................................... 24
ESD Protection when Powered................................................. 24
Related Products......................................................................... 24
Typical Applications................................................................... 25
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Supply...................................................................................... 3
15 V Supply................................................................................. 5
Absolute Maximum Ratings............................................................ 8
Maximum Power Dissipation ..................................................... 8
Thermal Resistance...................................................................... 8
Electrostatic Discharge (ESD) Ratings ...................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 18
Input Protection.......................................................................... 19
Over-The-Top Operation Considerations .............................. 19
REVISION HISTORY
5/2021—Revision 0: Initial Version
Rev. 0 | Page 2 of 27
Data Sheet
ADA4097-1
SPECIFICATIONS
5 V SUPPLY
Common-mode voltage (VCM) = 2.5 V, SHDN pin is open, load resistance (RL) = 499 kΩ to midsupply, TA = 25°C, unless otherwise noted.
Table 1.
B Grade
Typ
H Grade
Typ
Parameter
Test ConditionsꢀComments Min
Max
Min
Max
Unit
DC PERFORMANCE
Input Offset Voltage (VOS)1
0.25 V < VCM < 3.5 V
Minimum temperature (TMIN
< TA < maximum
±20
±±0
±130
±20
±±0
±1±0
μV
μV
)
temperature (TMAX
)
0.25 V < VCM < 70 V
TMIN < TA < TMAX
−0.1 V < VCM < +70 V
TMIN < TA < TMAX
±30
±30
±±0
±1±0
±±0
±ꢁ00
±1
±0.3
±10
1.5
2.25
1
10
±300
±5
±30
±30
±±0
±1ꢀ5
±±0
±ꢁ50
±1.5
±0.3
±25
1.5
2.5
1
10
±300
±10
μV
μV
μV
μV
Input Offset Voltage Drift2
Input Bias Current (IB)
TMIN < TA < TMAX
±0.1
±0.1
±0.1
±0.1
μV/°C
nA
nA
μA
μA
μA
μA
pA
nA
μA
μA
dB
TMIN < TA < TMAX
VCM = 70 V, Over-The-Top
TMIN < TA < TMAX
0 V < VCM < 70 V, VSY = 0 V
TMIN < TA < TMAX
0.25
0.175
0.ꢀ
0.25
0.125
0.ꢀ
0.001
±100
0.001
±100
Input Offset Current (IOS)
TMIN < TA < TMAX
VCM = 70 V, Over-The-Top3
TMIN < TA < TMAX
±0.025 ±0.0±5
±0.0ꢂ5
1ꢁ5
±0.025 ±0.0±5
±0.15
1ꢁ5
Common-Mode Rejection
Ratio (CMRR)
VCM = −0.1 V to +70 V
120
120
TMIN < TA < TMAX
VCM = 0.25 V to 3.5 V
TMIN < TA < TMAX
10ꢁ
115
110
−0.1
103
115
107
−0.1
dB
dB
dB
V
13ꢁ
13ꢁ
Common-Mode Input
Range
Guaranteed by CMRR tests
+70
+70
Large Signal Voltage
Gain (AOL)
Delta output voltage
(ΔVOUT) = ꢁ V
120
1ꢁ0
120
1ꢁ0
dB
TMIN < TA < TMAX
ΔVOUT = ꢁ V, RL = 10 kΩ
TMIN < TA < TMAX
11ꢁ
100
ꢂꢁ
112
100
ꢂ0
dB
dB
dB
10ꢀ
10ꢀ
NOISE PERFORMANCE
Input Voltage Noise
Frequency (f) = 0.1 Hz to 10 Hz
1/f noise corner
1000
±
1000
±
nV p-p
Hz
f = 100 Hz
f = 100 Hz, VCM > 5 V
f = 100 Hz
53
±5
0.05
0.5
53
±5
0.05
0.5
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
Over-The-Top
Input Current Noise
Over-The-Top
f = 100 Hz, VCM > 5 V
DYNAMIC PERFORMANCE
Slew Rate
ΔVOUT = ꢁ V
TMIN < TA < TMAX
Test frequency (fTEST) = 250 Hz
0.025
0.01ꢀ
120
0.1
0.025
0.015
120
0.1
V/μs
V/μs
kHz
Gain Bandwidth Product
(GBP)
130
130
TMIN < TA < TMAX
100
100
kHz
Rev. 0 | Page 3 of 27
ADA4097-1
Data Sheet
B Grade
Typ
5ꢀ
70
100
H Grade
Typ
5ꢀ
70
100
Parameter
Phase Margin
1% Settling Time
0.1% Settling Time
Test ConditionsꢀComments Min
Max
Min
Max
Unit
Degrees
μs
ΔVOUT = ±2 V
ΔVOUT = ±2 V
μs
Total Harmonic Distortion
Plus Noise (THD + N)
f = 1 kHz, VOUT = 2 V p-p, RL =
10 kΩ, bandwidth = ꢀ0 kHz
0.05
0.05
%
INPUT CHARACTERISTICS
Input Resistance
Differential mode
Common mode
Differential mode, VCM > 5 V
Common mode, VCM > 5 V
Differential mode
10
>1
±0
>1
1
10
>1
±0
>1
1
MΩ
GΩ
kΩ
GΩ
pF
Over-The-Top
Input Capacitance
Common mode
3
3
pF
SHDN PIN
Input Logic Low
Amplifier active, SHDN pin
voltage (VSHDN) < −VS + 0.5 V,
−VS + 0.5
−VS + 0.5
V
V
T
MIN < TA < TMAX
Input Logic High
Response Time
Amplifier shutdown, VSHDN
>
−VS + 1.5
−VS + 1.5
−VS + 1.5 V, TMIN < TA < TMAX
Amplifier active to shutdown
Amplifier shutdown to active
2.5
100
0.±
2.5
100
0.±
μs
μs
μA
Pull-Down Current
V
SHDN = −VS + 0.5 V,
TMIN < TA < TMAX
SHDN = −VS + 1.5 V,
3
3
V
0.3
2.5
0.3
2.5
μA
TMIN < TA < TMAX
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
Overdrive voltage (VODꢁ) =
30 mV, no load
15
ꢁ0
15
ꢁ0
mV
TMIN < TA < TMAX
ꢁ5
325
50
325
mV
mV
VOD = 30 mV,
2ꢁ0
2ꢁ0
sink current (ISINK) = 5 mA
TMIN < TA < TMAX
VOD = 30 mV, no load
TMIN < TA < TMAX
3ꢀ0
5
10
ꢁ00
5
15
mV
mV
mV
mV
Output Voltage Swing High
Short-Circuit Current
2.5
2.5
V
OD = 30 mV, source current
570
700
570
700
(ISOURCE) = 5 mA
TMIN < TA < TMAX
ISOURCE
TMIN< TA < TMAX
ISINK
1000
1100
mV
mA
mA
mA
mA
nA
20
10
35
10
30
ꢁ0
±5
20
±
35
±
30
ꢁ0
±5
TMIN < TA < TMAX
VSHDN = −VS + 1.5 V
Output Pin Leakage
During Shutdown
±100
±10
±100
±10
TMIN < TA < TMAX
μA
Rev. 0 | Page ꢁ of 27
Data Sheet
ADA4097-1
B Grade
Typ
H Grade
Typ
Parameter
Test ConditionsꢀComments Min
Max
Min
Max
Unit
POWER SUPPLY
Maximum Operating
Voltage5
Voltage Range (VSY)
50
50
50
50
V
V
Guaranteed by power supply
rejection ratio (PSRR)
3
3
Supply Current
Amplifier active
TMIN < TA < TMAX
Amplifier shutdown,
VSHDN = −VS + 1.5 V
32.5
12
3±
55
20
32.5
12
3±
±0
20
μA
μA
μA
TMIN < TA < TMAX
VSY = +3 V to ±25 V
TMIN < TA < TMAX
22.5
22.5
μA
dB
dB
PSRR
123
120
1ꢁ5
123
120
1ꢁ5
THERMAL SHUTDOWN±
Temperature
Hysteresis
TJ
175
20
175
20
°C
°C
°C
Operating Temperature
TA
−ꢁ0
+125
−55
+150
1 Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 1 are determined by
test capability and are not necessarily indicative of actual device performance.
2 Offset voltage drift is guaranteed through lab characterization and is not production tested.
3 Test accuracy is limited by high speed production test equipment repeatability. Bench measurements indicate that the input offset current in Over-The-Top
configuration is typically controlled to under 50 nA at +25°C and 100 nA over the −55°C < TA < +150°C temperature range.
ꢁ VOD is +30 mV for VOUT high and −30 mV for VOUT low.
5 Maximum operating voltage is limited by the time-dependent dielectric breakdown (TDDB) of the on-chip capacitor oxides. The amplifier tolerates temporary
transient overshoot up to the specified absolute maximum rating, but the dc supply voltage must be limited to the maximum operating voltage.
± Thermal shutdown is lab characterized only and is not tested in production.
15 V SUPPLY
VCM = 0 V, SHDN pin is open, RL = 499 kΩ to ground, and TA = 25°C, unless otherwise noted.
Table 2.
B Grade
Typ
H Grade
Typ
Parameter
Test ConditionsꢀComments
Min
Max
Min
Max
Unit
DC PERFORMANCE
1
VOS
±20
±20
±±0
±150
±±0
±150
±1
±0.3
±10
±0.3
±10
±0.3
±5
±20
±20
±±0
±175
±±0
±175
±1.5
±0.3
±25
±0.3
±25
±0.3
±10
±0.3
±10
μV
μV
μV
μV
μV/°C
nA
nA
nA
nA
nA
nA
nA
nA
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
TMIN < TA < TMAX
Input Offset Voltage Drift2
IB
±0.1
±0.1
±0.1
±0.1
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
±0.1
±0.1
±0.1
±0.1
±0.1
±0.1
IOS
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
±0.3
±5
Rev. 0 | Page 5 of 27
ADA4097-1
Data Sheet
B Grade
Typ
135
H Grade
Typ
135
Parameter
CMRR
Test ConditionsꢀComments
VCM = −1ꢁ.75 V to +13.5 V
TMIN < TA < TMAX
VCM = −15.1 V to +13.5 V
TMIN < TA < TMAX
VCM = −15.1 V to +55 V
TMIN < TA < TMAX
Guaranteed by CMRR tests
ΔVOUT = 25 V
Min
117
10ꢂ
117
ꢂꢂ
117
103
−15.1
120
11ꢁ
100
ꢂꢁ
Max
Min
117
10ꢂ
117
ꢂ5
117
103
−15.1
120
112
100
ꢂ0
Max
Unit
dB
dB
dB
dB
dB
dB
V
dB
dB
dB
dB
135
1ꢁ0
135
1ꢁ0
Common-Mode Input Range
AOL
+55
+55
150
10ꢀ
150
10ꢀ
TMIN < TA < TMAX
ΔVOUT = 25 V, RL =10 kΩ
TMIN < TA < TMAX
NOISE PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz
1/f noise corner
f = 100 Hz
f = 100 Hz, VCM > +VS
f =100 Hz
1
±
53
±5
0.05
0.5
1
±
53
±5
0.05
0.5
μV p-p
Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
Over-The-Top
Input Current Noise
Over-The-Top
f = 100 Hz, VCM > +VS
DYNAMIC PERFORMANCE
Slew Rate
ΔVOUT = 25 V
0.03
0.02
125
100
0.1
0.03
0.015
125
0.1
V/μs
V/μs
kHz
kHz
Degrees
μs
TMIN < TA < TMAX
fTEST = 250 Hz
TMIN < TA < TMAX
GBP
130
130
100
Phase Margin
1% Settling Time
0.1% Settling Time
THD + N
5ꢂ
70
100
0.1
5ꢂ
70
100
0.1
ΔVOUT = ±2 V
ΔVOUT = ±2 V
f = 1 kHz, VOUT = 5.± V p-p,
μs
%
RL = 10 kΩ, bandwidth = ꢀ0 kHz
INPUT CHARACTERISTICS
Input Resistance
Differential mode
Common mode
Differential mode
Common mode
10
>1
1
10
>1
1
MΩ
GΩ
pF
Input Capacitance
3
3
pF
SHDN PIN
Input Logic Low
Amplifier active,
VSHDN < −VS + 0.5 V
Amplifier shutdown,
VSHDN > −VS + 1.5 V
Amplifier active to shutdown
Amplifier shutdown to active
−VS + 0.5
−VS + 0.5
V
V
Input Logic High
Response Time
−VS + 1.5
−VS + 1.5
2.5
100
0.3
2.5
100
0.3
μs
μs
μA
Pull-Down Current
V
SHDN = −VS + 0.5 V,
TMIN < TA < TMAX
SHDN = −VS + 1.5 V,
TMIN < TA < TMAX
3
3
V
0.±
2.5
0.±
2.5
μA
Rev. 0 | Page ± of 27
Data Sheet
ADA4097-1
B Grade
Typ
H Grade
Typ
Parameter
Test ConditionsꢀComments
Min
Max
Min
Max
Unit
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
VOD3 = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, ISINK = 5 mA
TMIN < TA < TMAX
VOD = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, ISOURCE = 5 mA
TMIN < TA < TMAX
ISOURCE
15
ꢁ0
ꢁ5
325
3ꢀ0
10
15
700
1000
15
ꢁ0
50
325
ꢁ00
10
20
700
1100
mV
mV
mV
mV
mV
mV
mV
mV
mA
mA
mA
mA
2ꢁ0
2.5
570
30
2ꢁ0
2.5
570
30
Output Voltage Swing High
Short-Circuit Current
POWER SUPPLY
20
10
35
10
20
±
35
±
TMIN < TA < TMAX
ISINK
TMIN < TA < TMAX
ꢁ5
ꢁ5
Maximum Operating
Voltageꢁ
50
50
V
Voltage Range
Supply Current
Guaranteed by PSRR
Amplifier active
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
Amplifier shutdown,
VSHDN = −VS + 1.5 V
3
50
ꢁꢁ
±5
ꢁꢀ
70
22.5
3
50
ꢁꢁ
70
ꢁꢀ
75
22.5
V
ꢁ0
ꢁ2
15
ꢁ0
ꢁ2
15
μA
μA
μA
μA
μA
TMIN < TA < TMAX
VSY = 3 V to 50 V
TMIN < TA < TMAX
25
25
μA
dB
dB
PSRR
123
120
1ꢁ5
123
120
1ꢁ5
THERMAL SHUTDOWN5
Temperature
Hysteresis
TJ
175
20
175
20
°C
°C
°C
Operating Temperature
TA
−ꢁ0
+125
−55
+150
1 Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 2 are determined by
test capability and are not necessarily indicative of actual device performance.
2 Offset voltage drift is guaranteed through lab characterization and is not production tested.
3 VOD is +30 mV for VOUT high and −30 mV for VOUT low.
ꢁ Maximum operating voltage is limited by the TDDB of the on-chip capacitor oxides. The amplifier tolerates temporary transient overshoot up to the specified absolute
maximum rating and the dc supply voltage must be limited to the maximum operating voltage.
5 Thermal shutdown is lab characterized only and is not tested in production.
Rev. 0 | Page 7 of 27
ADA4097-1
Data Sheet
ABSOLUTE MAXIMUM RATINGS
from metal traces through vias, ground, and power planes
Table 3.
reduces θJA.
Parameter
Supply Voltage1
Rating
Figure 3 shows the maximum PD vs. TA for the single and dual
6-lead TSOT packages on a JEDEC standard, 4-layer board, with
−VS connected to a pad that is thermally connected to a printed
circuit board (PCB) plane. θJA values are approximations.
1.4
Transient
Continuous
Power Dissipation (PD)
Differential Input Voltage
±IN Pin Voltage
±0 V
50 V
See Figure 3
±ꢀ0 V
1.2
1.0
0.8
0.6
0.4
0.2
0
Continuous
Survival
±IN Pin Current
−10 V to +ꢀ0 V
−15 V to +ꢀ0 V
10 mA
−0.3 V to +±0 V
−±5°C to +150°C
−55°C to +150°C
300°C
SHDN Pin Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
TJ
1 Maximum supply voltage is limited by the TDDB of the on-chip capacitor
oxides. The amplifier tolerates temporary transient overshoot up to the
specified transient maximum rating. The continuous operating supply
voltage must be limited to no more than 50 V.
175°C
–60
–30
0
30
60
90
120
150
AMBIENT TEMPERATURE (°C)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
θ
JA is the junction to ambient thermal resistance.
TJ exceeding 125°C promotes accelerated aging. The ADA4097-1
demonstrates 25 V supply operation beyond 1000 hours at
TA = 150°C.
Table 4. Thermal Resistance
Package Type
UJ-±
θJA
1ꢂ2
Unit
C/W
MAXIMUM POWER DISSIPATION
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The maximum safe PD on the device is limited by the associated
rise in either TC or TJ on the die. At approximately TC = 150°C,
which is the glass transition temperature, the properties of the
plastic changes. Exceeding this temperature limit, even temporarily,
may change the stresses that the package exerts on the die, which
permanently shifts the parametric performance of the ADA4097-1.
Exceeding TJ = 175°C for an extended period may result in changes
in the silicon devices and may potentially cause failure of the device.
The following ESD information is provided for handling of
ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) per
ANSI/ESDA/JEDEC JS-002.
ESD Ratings for ADA4097-1
Table 5. ADA4097-1, 6-Lead TSOT
The PD on the package is the sum of the quiescent power dissipation
and the power dissipated in the package due to the output load
drive. The quiescent power is expressed as VSY × ISY, where ISY is
the quiescent current.
ESD Model
HBM
FICDM
Withstand Threshold
±2 kV
±1.25 kV
Class
3A
3
ESD CAUTION
The PD due to the load drive depends on the application. The PD
due to load drive is calculated by multiplying the load current
by the associated voltage drop across the device. RMS voltages
and currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA.
Additional metal that is directly in contact with the package leads
Rev. 0 | Page ꢀ of 27
Data Sheet
ADA4097-1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADA4097-1
V
1
2
3
6
5
4
+V
S
OUT
–V
SHDN
–IN
S
+IN
TOP VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
VOUT
−VS
Amplifier Output.
Negative Power Supply. In single-supply applications, the −VS pin is normally soldered to a low impedance ground
plane. In split-supply applications, bypass the −VS pin with a capacitance of at least 0.1 ꢃF to a low impedance
ground plane, as close to the −VS pin as possible.
3
ꢁ
5
+IN
−IN
SHDN
Noninverting Input of the Amplifier.
Inverting Input of the Amplifier.
Op Amp Shutdown. The threshold for shutdown is approximately 1 V above the negative supply. If the SHDN pin is
not connected or hard tied to −VS, the amplifier is active. If the SHDN pin is asserted high (VSHDN > −VS + 1.5 V), the
amplifier is placed in a shutdown state, and the output of the amplifier goes to a high impedance state. If the SHDN
pin is left unconnected, it is recommended to connect a small capacitor of 1 nF between the SHDN pin and the −VS
pin to prevent signals from the −IN pin from capacitively coupling to the SHDN pin.
±
+VS
Positive Power Supply. Bypass the +VS pin with a capacitance of at least 0.1 ꢃF to a low impedance ground plane, as
close to the +VS pin as possible.
Rev. 0 | Page ꢂ of 27
ADA4097-1
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
70
20
15
10
5
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
60
50
40
30
20
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
10
0
0
0
5
10
15
20
25
30
35
40
45
50
1
10
50
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 5. Supply Current vs. Supply Voltage
Figure 8. Shutdown Supply Current vs. Supply Voltage
70
60
50
40
30
20
10
20
18
16
14
12
10
8
V
= 5V
SY
10 REPRESENTATIVE UNITS
V
V
= MIDSUPPLY
CM
1080 UNITS
= ±25V
SY
V
= +5V
SY
6
4
2
0
–60
–30
0
30
60
90
120
150
–30 –24 –18 –12
–6
0
6
12
18
24
30
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (µV)
Figure 6. Supply Current vs. Temperature Across Various Supply Voltages
Figure 9. Typical Distribution of Input Offset Voltage, VSY = 5 V
100
20
V
= ±15V
= 0V
V
= 5V
SY
SY
18
16
14
12
10
8
V
CM
1080 UNITS
10
6
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
4
2
1
0
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
–30 –24 –18 –12
–6
0
6
12
18
24
30
V
WITH RESPECT TO –V (V)
INPUT OFFSET VOLTAGE (µV)
SHDN
S
Figure 10. Typical Distribution of Input Offset Voltage with VSY
= 15 V
Figure 7. Supply Current vs. VSHDN with Respect to −VS
Rev. 0 | Page 10 of 27
Data Sheet
ADA4097-1
20
200
150
100
50
V
V
= ±25V
= 0V
V
V
= ±25V
= 0V
SY
SY
18
16
14
12
10
8
CM
CM
10 REPRESENTATIVE UNITS
1080 UNITS
0
–50
–100
–150
–200
6
4
2
0
–30 –24 –18 –12
–6
0
6
12
18
24
30
–60
–30
0
30
60
90
120
150
INPUT OFFSET VOLTAGE (µV)
TEMPERATURE (°C)
Figure 11. Typical Distribution of Input Offset Voltage with VSY
=
25 V
Figure 14. Offset Voltage vs. Temperature with VSY
=
25 V
200
2.0
1.5
V
V
= 5V
V
V
= 5V
SY
SY
150
100
50
= MIDSUPPLY
= MIDSUPPLY
CM
CM
10 REPRESENTATIVE UNITS
10 REPRESENTATIVE UNITS
1.0
0.5
0
0
–50
–100
–150
–200
–0.5
–1.0
–1.5
–2.0
–60
–30
0
30
60
90
120
150
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Midsupply Offset Voltage vs. Temperature with VSY = 5 V
Figure 15. Midsupply Input Bias Current vs. Temperature with VSY = 5 V
200
2.0
V
V
= ±15V
= 0V
V
V
= ±15V
= 0V
SY
SY
150
100
50
1.5
1.0
CM
CM
10 REPRESENTATIVE UNITS
10 REPRESENTATIVE UNITS
0.5
0
0
–50
–100
–150
–200
–0.5
–1.0
–1.5
–2.0
–60
–30
0
30
60
90
120
150
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. Offset Voltage vs. Temperature with VSY
=
15 V
Figure 16. Input Bias Current vs. Temperature with VSY
= 15 V
Rev. 0 | Page 11 of 27
ADA4097-1
Data Sheet
200
2.5
2.0
1.5
1.0
0.5
0
V
V
= 5V
= 6V
V
V
= 5V
= 6V
SY
SY
150
100
50
CM
CM
10 REPRESENTATIVE UNITS
10 REPRESENTATIVE UNITS
0
–50
–100
–150
–200
–60
–30
0
30
60
90
120
150
–60
–30
0
30
60
90
120
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Offset Voltage vs. Temperature with VCM = 6 V,
Over-The-Top
Figure 20. Input Bias Current vs. Temperature with VCM = 6 V,
Over-The-Top
200
150
100
50
2.0
1.5
1.0
0.5
0
V = 5V
SY
V
V
= 5V
SY
= 70V
CM
10 REPRESENTATIVE UNITS
0
–50
–100
–150
–200
V
V
= 6V
= 70V
CM
CM
–60
–30
0
30
60
90
120
150
–60
–30
0
30
60
90
120
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. Offset Voltage vs. Temperature with VCM = 70 V
Figure 21. Input Bias Current vs. Temperature Across Various VCM
20
18
16
14
12
10
8
5
V
V
V
V
V
= +3V
= +5V
= ±5V
= ±15V
= ±25V
V
= 5V
SY
SY
SY
SY
SY
SY
4
3
V
= MIDSUPPLY
CM
1080 UNITS
2
V
= MIDSUPPLY
CM
1
0
–1
–2
–3
–4
–5
6
4
2
0
–100 –70 –40 –10
20
50
80
110 140 170 200
–60
–30
0
30
60
90
120
150
INPUT BIAS CURRENT (pA)
TEMPERATURE (°C)
Figure 19. Typical Distribution of Input Bias Current, VSY = 5 V
Figure 22. Input Bias Current vs. Temperature Across Various Supply Voltages
Rev. 0 | Page 12 of 27
Data Sheet
ADA4097-1
100
10
1
V
= 5V
SY
V
= +3V
= +5V
= ±5V
= ±15V
= ±25V
SY
SY
SY
SY
SY
V
V
V
V
75
50
0.1
V
= MIDSUPPLY
CM
25
0
0.01
0.001
0.0001
0
–25
–50
–75
–100
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
–60
–30
0
30
60
90
120
150
3.0
3.5
4.0
4.5
5.0
TEMPERATURE (°C)
INPUT COMMON-MODE VOLTAGE (V)
Figure 23. Offset Voltage vs. Temperature Across Various Supply Voltages
Figure 26. Input Bias Current vs. Input Common-Mode Voltage from
Normal Operation to Over-The-Top Operation
200
200
V
= 5V
V
= 5V
SY
SY
150
100
50
150
100
50
0
0
–50
–100
–150
–200
–50
–100
–150
–200
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
A
A
A
A
0.1
1
10
100
–0.1
0
0.1
0.2
0.3
0.4
0.5
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
Figure 24. Offset Voltage vs. Input Common-Mode Voltage from
Normal Operation to Over-The-Top Operation
Figure 27. Offset Voltage vs. Input Common-Mode Voltage for
Ground Sensing Applications
200
0.5
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
V
= 5V
SY
V
= 5V
SY
150
100
50
0
–0.5
–1.0
–1.5
–2.0
–2.5
0
–50
–100
–150
–200
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
3.0
3.5
4.0
4.5
5.0
–0.1
0
0.1
0.2
0.3
0.4
0.5
INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
Figure 25. Offset Voltage vs. Input Common-Mode Voltage over
the Input Common-Mode Range
Figure 28. Input Bias Current vs. Input Common-Mode Voltage for Ground
Sensing Applications
Rev. 0 | Page 13 of 27
ADA4097-1
Data Sheet
10
100
75
T
A
= –55°C
= +25°C
= +125°C
= +150°C
V
= 5V
SY
T
A
T
A
T
1
0.1
A
50
25
0
0.01
–25
–50
–75
–100
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
0.001
0.0001
V
= MIDSUPPLY
CM
1
10
INPUT COMMON-MODE VOLTAGE (V)
100
5
10
15
20
25
30
35
40
45
50
SUPPLY VOLTAGE (V)
Figure 29. Input Bias Current vs. Input Common-Mode Voltage
Figure 32. Offset Voltage vs. Supply Voltage
60
300
200
100
0
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
V
= ±15V
SY
50
40
30
20
10
0
–100
–200
–300
R
R
R
R
R
= 499kΩ
= 100kΩ
= 10kΩ
= 5kΩ
LOAD
LOAD
LOAD
LOAD
LOAD
V
= MIDSUPPLY
4
CM
= 2kΩ
0
1
2
3
5
–15
–10
–5
0
5
10
15
MINIMUM SUPPLY VOLTAGE (V)
V
(V)
OUT
Figure 30. Supply Current vs. Minimum Supply Voltage
Figure 33. ΔOffset Voltage vs. VOUT Across Various RLOAD
100
75
400
300
T
T
T
T
= –55°C
= 25°C
= 125°C
= 150°C
A
A
A
A
V
=
±15V
SY
R
= 10 kΩ
LOAD
50
200
25
100
0
0
–25
–50
–75
–100
–100
–200
–300
–400
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
V
= MIDSUPPLY
CM
2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00
–15
–10
–5
0
5
10
15
MINIMUM SUPPLY VOLTAGE (V)
V
(V)
OUT
Figure 31. Offset Voltage vs. Minimum Supply Voltage
Figure 34. ΔOffset Voltage vs. VOUT Across Various Temperatures
Rev. 0 | Page 1ꢁ of 27
Data Sheet
ADA4097-1
1.00
50
40
30
20
10
0
90
75
60
45
30
15
V
= 5V
SY
0.75
0.50
0.25
0
OPEN-LOOP GAIN (V = 5V)
OPEN-LOOP GAIN (V = ±15V)
SY
OPEN-LOOP PHASE MARGIN (V = 5V)
SY
OPEN-LOOP PHASE MARGIN (V = ±15V)
SY
SY
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
–10
0
500
0
0.5
1.0
1.5
2.0
1
10
100
V
WITH RESPECT TO −VS (V)
FREQUENCY (kHz)
SHDN
Figure 38. Open-Loop Gain and Open-Loop Phase Margin vs. Frequency
Figure 35. SHDN Pin Current (ISHDN) vs. VSHDN with Respect to −VS over Various
Temperatures
25
20
15
10
5
100
V
OL
10
1
V
OH
0
–5
–10
V
V
= 5V
SY
0.1
0.01
R
R
R
R
= 0Ω, R = OPEN
G
F
F
F
F
= MIDSUPPLY
CM
= 10kΩ, R = 10kΩ
G
10 REPRESENTATIVE UNITS
–15
–20
= 40kΩ, R = 10kΩ
G
R
= OPEN
= 100kΩ, R = 10kΩ
LOAD
G
1
10
100
500
–60
–30
0
30
60
90
120
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 39. Noninverting Small Signal Frequency Response
Figure 36. Output Swing Relative to Supply vs. Temperature
25
200
175
150
125
100
75
V
V
= ±15V
= 0V
SY
20
15
CM
10 REPRESENTATIVE UNITS
10
5
0
–5
50
–10
–15
–20
R
R
R
R
= 10kΩ, R = 10kΩ
G
F
F
F
F
= 20kΩ, R = 10kΩ
G
25
= 49.9kΩ, R = 10kΩ
G
= 100kΩ, R = 10kΩ
G
0
–60
1
10
100
500
–30
0
30
60
90
120
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 40. Inverting Small Signal Frequency Response
Figure 37. Gain Bandwidth vs. Temperature
Rev. 0 | Page 15 of 27
ADA4097-1
Data Sheet
250
225
200
175
150
125
100
75
V
= ±15V
SY
V
IN
10V/DIV
V
OUT
10V/DIV
50
V
V
IN
25
OUT
0
0.2ms/DIV
0.0001
0.001
0.01
0.1
1
10
100
1k
FREQUENCY (kHz)
Figure 41. Output Noise vs. Frequency
Figure 44. Unity-Gain Large Signal Step Response
100
10
0
G = +1, R
G = +1, R
G = +1, R
G = +1, R
G = +1, R
G = +1, R
G = +1, R
G = +1, R
G = +1, R
= 2kΩ, V = 100mV rms
IN
V
= ±8V
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
SY
= 2kΩ, V = 300mV rms
IN
= 2kΩ, V = 1V rms
IN
= 5kΩ, V = 100mV rms
–20
–40
–60
–80
–100
–120
IN
= 5kΩ, V = 300mV rms
IN
= 5kΩ, V = 1V rms
IN
= 10kΩ, V = 100mV rms
IN
1
= 10kΩ, V = 300mV rms
IN
= 10kΩ, V = 1V rms
IN
0.1
OUTPUT NOISE
200nV/DIV
0.01
0.001
0.0001
20
TIME (1s/DIV)
200
2000
20000
FREQUENCY (Hz)
Figure 42. 0.1 Hz to 10 Hz Noise
Figure 45. THD + N vs. Frequency over Load
100
10
0
G = +1, 250Hz, R
= 10kΩ
= 10kΩ
= 10kΩ
= 10kΩ
= 10kΩ
= 10kΩ
= 20kΩ
= 20kΩ
= 20kΩ
LOAD
V
= ±8V
SY
G = +1, 500Hz, R
G = +1, 1kHz, R
LOAD
V
= ±15V
SY
LOAD
G = +1, 2kHz, R
LOAD
LOAD
G = +1, 5kHz, R
–20
–40
–60
–80
–100
G = +1, 10kHz, R
G = +1, 250Hz, R
LOAD
LOAD
V
IN
G = +1, 500Hz, R
G = +1, 1kHz, R
LOAD
50mV/DIV
LOAD
1
V
0.1
0.01
OUT
50mV/DIV
V
G = +1, 2kHz, R
LOAD
= 20kΩ
= 20kΩ
= 20kΩ
IN
G = +1, 5kHz, R
V
LOAD
OUT
G = +1, 10kHz, R
LOAD
0.001
0.01
0.1
1
10
20µs/DIV
OUTPUT AMPLITUDE (V rms)
Figure 46. THD + N vs. Output Amplitude
Figure 43. Unity-Gain Small Signal Step Response
Rev. 0 | Page 1± of 27
Data Sheet
ADA4097-1
100
90
80
70
60
50
40
30
20
10
0
100
0
G = +1, R
= 200Ω
= 500Ω
= 1kΩ
G = –1, R
G = –1, R
G = –1, R
G = –1, R
G = –1, R
G = –1, R
G = –1, R
= 200Ω
= 500Ω
= 1kΩ
V
= ±8V
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
SY
G = +1, R
G = +1, R
G = +1, R
G = +1, R
= 2kΩ
= 2kΩ
= 5kΩ
= 10kΩ
= 20kΩ
= 5kΩ
= 10kΩ
= 20kΩ
+V PSRR
S
10
–20
–40
–60
–80
–100
G = +1, R
G = +1, R
1
–V PSRR
S
0.1
0.01
0.001
0.01
0.1
1
10
10
100
1k
10k
100k
1M
OUTPUT AMPLITUDE (V rms)
FREQUENCY (Hz)
Figure 49. PSRR vs. Frequency
Figure 47. THD + N vs. Output Amplitude and Load
100
10
1
90
80
70
60
50
40
30
20
10
0
GAIN = 100V/V
GAIN = 10V/V
GAIN = 1V/V
0.1
100
–10
1k
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 50. Output Impedance vs. Frequency
Figure 48. CMRR vs. Frequency
Rev. 0 | Page 17 of 27
ADA4097-1
Data Sheet
THEORY OF OPERATION
The ADA4097-1 is a robust, voltage feedback amplifier that
combines unity-gain stability with low offset, low offset drift, and
53 nV/√Hz of input voltage noise. Figure 53 shows a simplified
schematic of the device. The ADA4097-1 has two input stages:
a common emitter differential input stage consisting of the Q1
and Q2 PNP transistors that operate with the inputs biased
between −VS and 1 V below +VS, and a common base input
stage that consists of the Q3 to Q6 PNP transistors that operate
when the common-mode input is biased >+VS − 1 V. These input
stages result in two distinct operating regions, as shown in
Figure 51.
For common-mode input voltages that are approximately 1 V
below the +VS supply, where Q1 and Q2 are active (see Figure 51),
the common emitter PNP input stage is active and the input bias
current is typically <0.3 nA. When the common-mode input is
above +VS − 1 V, the Q9 transistor turns on, which diverts bias
current away from the common emitter differential input pair
to the mirror that consists of M3 and M4. The current from M4
biases the common base differential input pair (Q3 to Q6). The
Over-The-Top input pair operates in a common base configuration
and the input bias current increases to ~0.8 μA. The offset
voltages of both input stages are tightly trimmed and are
specified in Table 1 and Table 2.
10
V
= 5V
SY
As the input common-mode transitions to the Over-The-Top
region, the input CMRR degrades slightly when compared to
the rest of the input common-mode range, as shown in Figure 52.
200
1
0.1
V
= 5V
SY
0.01
0.001
0.0001
0
150
100
50
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
0
–50
–100
–150
–200
3.0
3.5
4.0
4.5
5.0
INPUT COMMON-MODE VOLTAGE (V)
T
T
T
T
= –55°C
= +25°C
= +125°C
= +150°C
A
A
A
A
Figure 51. Input Bias Current vs. Input Common-Mode Voltage over
Temperature, VSY = 5 V
3.0
3.5
4.0
4.5
5.0
INPUT COMMON-MODE VOLTAGE (V)
Figure 52 . Offset Voltage vs. Input Common-Mode Voltage over
Temperature, VSY = 5 V
+V
S
Q10
PNP
I2
1µA
I3
1µA
I1
0.85µA
M1
PMOS
R5
40kΩ
Q9
PNP
D3
ESD
R1
OUTPUT
DRIVER
–IN
+IN
880Ω
R2
J1
NJF
P
N
I
Q2 Q1
SD
OUT
880Ω
PNP
PNP
Q6
PNP
Q5
PNP
Q4
PNP
Q3
PNP
R6
2MΩ
Q8
Q7
U1
NPN
NPN
SHDN
Q13
NPN
D3
ESD
D4
ESD
V1
1V
R4
100kΩ
R3
100kΩ
D1
ESD
D2
ESD
M1
M2
M3
M4
NMOS
NMOS NMOS
NMOS
–V
S
Figure 53. Simplified ADA4097-1 Schematic
Rev. 0 | Page 1ꢀ of 27
Data Sheet
ADA4097-1
INPUT PROTECTION
OVER-THE-TOP OPERATION CONSIDERATIONS
The inputs are protected against temporary voltage excursions
to 15 V below –VS (see Figure 54) by internal 880 ꢀ resistors
(see Figure 53). These resistors limit the current in the series
D1 diode and D2 diode that are tied to the bases of the Q1 and
Q2 transistors, respectively. Adding additional external series
resistance extends the protection to >15 V below −VS, at the
cost of stability and added thermal noise. The input stage of the
ADA4097-1 incorporates phase reversal protection to prevent
the output from phase reversing for inputs below −VS. The
ADA4097-1 op amp does not have clamping diodes between the
inputs and can be differentially overdriven up to 80 V without
damage, inducing parametric shifts, or drawing appreciable input
current. Figure 55 summarizes the input fault types that can be
applied to the ADA4097-1 without compromising input integrity.
When the ADA4097-1 input common-mode is biased near or
>+VS supply, the amplifier operates in the Over-The-Top
configuration. The differential input pair that controls amplifier
operation is the common base pair, Q3 to Q6 (see Figure 53).
Input bias currents change from< 0.3 nA in normal operation
to approximately 0.8 ꢁA in Over-The-Top operation when the
input stage transitions from common emitter to common base.
The Over-The-Top input bias currents are well matched, and the
associated offset is typically <50 nA. Ensure that the impedance
connected to the inverting and noninverting inputs is well matched
to avoid any input bias current induced voltage offsets.
Differential input impedance, RIN (see Figure 56), decreases
from >10 Mꢀ in normal operation to ~60 kꢀ in Over-The-Top
operation (see Table 1 and Table 2).
V
= 5V
SY
R
F
R
I
V
R
IN
IN
R
I
V
INCM
R
F
V
OUT
Figure 56. Difference Amplifier Configured for Normal Operation and
Over-The-Top Operation (RI Is a Gain Setting Resistor)
This RIN resistance appears across the summing nodes in Over-
The-Top operation due to the configuration of the common
base input stage.
V
IN
TIME (400ms/DIV)
The RIN value is derived from the specified IB that flows to the
op amp inputs, as expressed in the following equation:
Figure 54. ADA4097-1 as Unity-Gain Buffer with Noninverting Input Driven
Beyond the Supply (VSY = 5 V)
R
IN = 2kT/(qIB)
5V
5V
OK!
OK!
where:
k is Boltzmann’s constant.
T is the operating temperature.
q is the charge of an electron.
IB is the operating input bias current in Over-The-Top
operation.
80V
80V
INPUTS DRIVEN
ABOVE THE SUPPLY
TOLERANT
LARGE DIFFERENTIAL
INPUT VOLTAGE
TOLERANT
5V
5V
The inputs are biased proportional to absolute temperature.
Therefore, RIN is relatively constant with temperature. This
resistance appears across the summing nodes of the amplifier,
which is forced to 0 V differentially by the feedback action of
the amplifier and can seem relatively harmless. However,
depending on the configuration, this input resistance can boost
the noise gain, lower overall amplifier loop gain and closed-
loop bandwidth, and raise output noise. The singular benefit of
this configuration is an increase in closed-loop amplifier stability.
OK!
OK!
80V
–5V
LARGE DIFFERENTIAL
INPUT VOLTAGE
TOLERANT
INPUTS DRIVEN
BELOW GROUND
TOLERANT
Figure 55. ADA4097-1 Fault Tolerant Conditions
In normal mode (−VS < VCM < +VS −1 V), RIN is typically large
compared to the value of the gain setting resistors (RF and RI),
and RIN can be ignored.
Rev. 0 | Page 1ꢂ of 27
ADA4097-1
Data Sheet
In this case, the noise gain is defined by the following equation:
OUTPUT
Noise Gain = 1 + RF/RI
The output of the ADA4097-1 can swing rail-to-rail to within
15 mV of the either supply with no load. The output can source
30 mA and sink 40 mA. The amplifier is internally compensated to
drive at least 200 pF of CLOAD. Adding a series resistance of 50 ꢀ
between the output and larger capacitive loads extends the
capacitive drive capability of the amplifier.
When the amplifier transitions to Over-The-Top operation with
the input common-mode biased near or above the +VS supply,
consider the value of RIN.
The noise gain of the amplifier increases as shown in the
following equation:
If the ADA4097-1 enters shutdown, the VOUT pin appears as
high impedance with two steering diodes connected to either
supply. In this state, the output typically leaks <5 nA.
RF
RI || RF
RIN
Noise GainOTT 1
1
RI || RIN RI || RF
SHUTDOWN PIN (SHDN)
where Noise GainOTT is the Over-The-Top noise gain.
The ADA4097-1 has a dedicated SHDN pin to place the
amplifier in a very low power shutdown state when asserted
high. A logic high is defined by a voltage ≥1.5 V applied to the
SHDN pin with respect to the −VS pin. In shutdown, the amplifier
draws <20 ꢁA of supply current (see Figure 7) and the VOUT pin
is placed in a high impedance state.
The dc closed-loop gain remains mostly unaffected (RF/RI).
However, the loop gain of the amplifier decreases, as expressed
in the following equation:
AOL
RF
AOL
Noise GainOTT
to
1
RI
The SHDN pin can be driven beyond the +VS supply up to the
absolute maximum voltage (60 V with respect to −VS) and draws
little current (<2.5 ꢁA). For normal active amplifier operation,
the SHDN pin can be floated or driven by an external voltage
source low (within 0.5 V of −VS). If the SHDN pin is left floating,
an internal current source (~600 nA) pulls the SHDN pin to –VS,
which places the amplifier into a default, active amplifying state.
Because of the close proximity of the −IN pin and SHDN pin,
fast edges on the −IN pin may ac-couple to the adjacent high
impedance SHDN pin, inadvertently placing the device in
shutdown. If this scenario is a concern, add a 1 nF capacitor
between the SHDN pin and the −VS pin.
Likewise, the closed-loop bandwidth (BWCLOSED_LOOP) of the
amplifier changes going from normal operation to Over-The-
Top operation.
In normal operation,
GBP
BWCLOSED_LOOP
≈
RF
RI
1
In Over-The-Top operation,
GBP
Noise GainOTT
BWCLOSED_LOOP
≈
Alternatively, the amplifier can be effectively placed in a low power
state by removing +VS. In this low power state, the inputs typically
leak <1 nA with either IN pin biased between −VS and 70 V
above −VS. If the IN pins are taken below −VS, they appear as a
diode connected to the −VS supply in series with a resistance of
880 ꢀ. In this condition, limit the current to <10 mA.
Output voltage noise density (eno) is impacted when the device
transitions from normal operation to Over-The-Top operation.
Resistor noise is neglected in both modes of operation in the
following equations.
In normal operation, neglecting resistor noise,
Using an external source to drive the output beyond either VS
supply under shutdown conditions may produce unlimited
current and may damage the device.
RF
RI
eno e 1
n
where en is input referred voltage noise density.
In Over-The-Top operation, neglecting resistor noise,
eno en Noise GainOTT
Rev. 0 | Page 20 of 27
Data Sheet
ADA4097-1
APPLICATIONS INFORMATION
10
5
LARGE RESISTOR GAIN OPERATION
R
= R = 1MΩ
G
F
The ADA4097-1 has approximately 3.5 pF of input capacitance.
The parallel combination of the RF and RG on the inverting
input can combine with this input capacitance (CIN) to form a
pole that can reduce bandwidth, cause frequency response
peaking, or produce oscillations (see Figure 58). To mitigate
these consequences, place a feedback capacitor with a value of
CF > CIN(RG/RF) in parallel with RF for summing node impedances
>200 kꢀ (RF||RG > 200 kꢀ). This capacitor placement cancels the
input pole and optimizes dynamic performance (see Figure 57).
0
–5
–10
–15
C
C
C
= 0pF
= 1pF
= 2pF
F
F
F
For applications where the noise gain is unity (RG→∞), and the
feedback resistor exceeds 200 kꢀ, CF ≥ CIN. Optimize PCB layouts
to keep layout related summing node capacitance to an absolute
minimum.
0.1
1
10
FREQUENCY (kHz)
100
Figure 58. Inverting Gain of 1, Small Signal Frequency Response,
RF = RG = 1 MΩ
C
F
RECOMMENDED VALUES FOR VARIOUS GAINS
R
F
Table 7 is a reference for determining various recommended
gains and associated noise performance. The total impedance
seen at the inverting input is kept to <200 kΩ for gains >1 to
maintain ideal small signal bandwidth.
1MΩ
U1
R
G
V
IN
1MΩ
C
IN
V
OUT
3.5pF
Figure 57. Inverting Gain Schematic
Table 7. Gains and Associated Recommended Resistor Values (TA = 25°C)
Total System Noise (nVꢀ√Hz at 1 kHz),
Referred to Input
Gain RF (kΩ)
RG (kΩ)
CF (pF)
Approximate −3 dB Frequency (kHz)
+1
+2
+2
+5
+10
−1
−1
−1
−2
−5
−10
0
10
100
10
10
Not applicable
10
100
ꢁ0.2
ꢂ0
Not applicable 220
53
5ꢁ
0
0
0
0
0
0
2
0
0
0
ꢀ0
100
33.5
1ꢀ
ꢀ7
ꢂ5
55
5±
2ꢂ
17
5ꢂ.5
53.2
53.2
10ꢀ
11ꢂ
215
ꢀ0
10
10
100
1000
10
10
10
100
1000
20
ꢁꢂ.ꢂ
100
±ꢁ.2
5ꢀ.5
Rev. 0 | Page 21 of 27
ADA4097-1
Data Sheet
is determined by the resistor and current noise density. The
ADA4097-1 has an en of 53 nV/Hz.
NOISE
To analyze the noise performance of an amplifier circuit,
identify the noise sources, and then determine if each source
has a significant contribution to the overall noise performance
of the amplifier. To simplify the noise calculations, noise spectral
densities (NSDs) are used rather than actual voltages, to leave
bandwidth out of the expressions. NSD is generally expressed in
nV/Hz and is equivalent to the noise in a 1 Hz bandwidth.
If resistor and current noise contributions are less than half this
value, the en introduced by the op amp dominates and provides
optimal noise performance of the device.
1k
100
10
The noise model shown in Figure 59 has six individual noise
sources: the Johnson noise of the three resistors (R1 to R3), the
op amp voltage noise, and the current noise (IN ) in each input
of the amplifier. Each noise source has its own contribution to
the noise at the output. Noise is generally specified as referring
to input (RTI), but it is often simpler to calculate the noise referred
to the output (RTO), and then divide by the noise gain to obtain
the RTI noise.
1
RTI NOISE
V
NR
I
× R
EQ
N
V
N
0.1
eN, R2
1k
10k
100k
(Ω)
1M
10M
R2
GAIN FROM
=
R
EQ
4kTR2
A TO OUTPUT
Figure 60. Noise Contributions vs. Equivalent Input Resistance
NOISE GAIN =
R2
eN, R1
I
I
For the ADA4097-1, this lower bound of resistance in the feedback
network is about 40 kꢀ. For the amplifier configuration shown
in Figure 59, REQ < 40 kꢀ provides stable noise performance. If
noise performance is not important, en is typically fixed for a
given TA, en,R increases with the square root of the resistor value,
and the IN × REQ resistance increases linearly, but does not impact
total noise until it approaches the value of en,R. With REQ < ~6 Mꢀ,
en,R is larger than IN × REQ. A safe value for REQ < 2 Mꢀ to ensure
that IN is not the majority contributor to total noise seen by the
input.
N–
N+
NG = 1 +
R1
R1
R3
B
A
eN
4kTR1
eN, R3
V
OUT
R2
R1
GAIN FROM
B TO OUTPUT
= –
4kTR3
2
R2
R1 + R2
2
2
eN + 4kTR3 + 4kTR1
2
R1 × R2
R1
RTI NOISE =
2
2
2
+I
R3 + I
+ 4kTR2
N+
N–
R1 + R2
R1 + R2
RTO NOISE = NG × RTI NOISE
Figure 60 shows the noise contributions for the range of resistance
values discussed in this section.
Figure 59. Op Amp Noise Analysis Model
Assuming IN+ = IN− = IN, the equation for RTI noise can be
simplified to the following form:
DISTORTION
There are two main contributors of distortion in op amps: output
crossover distortion as the output transitions from sourcing to
sinking, and distortion caused by nonlinear common-mode
rejection. If the op amp is operating in an inverting configuration,
there is no common-mode induced distortion. If the op amp is
operating in the noninverting configurations within the normal
input common-mode range (−VS to +VS − 1 V), distortion is
acceptable. When the inputs transition from normal to Over-
The-Top operation or vice versa, a significant degradation
occurs in linearity due to the change of input circuitry.
2
2
RTI Noise = en +en,R2+ I R
EQ
N
en,R
EQ = R3 + R1||R2
where:
=
4kTREQ
R
en is the op amp voltage noise.
n,R is the thermal noise contribution of the surrounding R1 to
R3 resistors.
e
R
EQ is the equivalent input resistance.
As RL decreases, distortion increases due to a net decrease in loop
gain and greater signal swings internal to the amplifier that are
necessary to drive the load. The lowest distortion can be achieved
with the ADA4097-1 operating in Class A operation in an inverting
configuration, with the input common-mode biased at midsupply.
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the absolute temperature in Kelvin.
A 50 Ω resistor generates a Johnson noise of 1 nV/√Hz at 25°C.
For optimal performance, the lower bound of resistance in a
feedback network is determined by the amount of quiescent
power and distortion that can be tolerated. The upper bound
Rev. 0 | Page 22 of 27
Data Sheet
ADA4097-1
For a given supply voltage, use Figure 62 as a guide for estimating
the minimum load resistance that the ADA4097-1 can drive for
a given supply voltage and a given rise in junction temperature
(ΔTJ). For example, to limit ΔTJ to 50°C, the load driven on the
15 V supplies (+30 V total supply) must not be lower than
0.8 kꢀ. It is assumed that θJA is 192°C/W.
POWER DISSIPATION AND THERMAL SHUTDOWN
The ADA4097-1 can drive heavy loads on power supplies up to
25 V. Therefore, ensure that TJ on the integrated circuit does
not exceed 175°C. The ADA4097-1 is housed in a 6-lead TSOT
package (θJA = 192°C/W).
Junction temperatures exceeding 125°C promote accelerated aging.
Reliability of the ADA4097-1 may be impaired if the junction
temperature exceeds 175°C. If the junction temperature exceeds
175°C, the ADA4097-1 has a final safety measure in the form of
a thermal shutdown that shuts off the output stage and reduces
the internal device currents. When this thermal shutdown function
triggers, the output remains disabled in a high impedance state
until the junction temperature drops 20°C. Persistent heavy loads
and elevated ambient temperatures can cause the ADA4097-1 to
oscillate in and out of thermal shutdown depending on the power
dissipated on the die, until the heavy load is removed (see
Figure 61).
4
1
0.1
ΔT = 50°C
0.01
J
ΔT = 75°C
J
ΔT = 100°C
J
ΔT = 125°C
J
0.001
5
10
15
20
25
30
35
40
45
50
T
= 150°C
A
V
= ±25V
TOTAL SUPPY VOLTAGE (V)
SY
R
= 550Ω
LOAD
Figure 62. Minimum Load Resistance for Given ΔTJ and VSY
INPUT
10V/DIV
CIRCUIT LAYOUT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the
ADA4097-1 boards yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.
OUTPUT
10V/DIV
T < 155°C
J
T
> 175°C
POWER SUPPLY BYPASSING
J
On single supplies, solder the −VS supply pin directly to a low
impedance ground plane. Bypass the +VS pin to a low impedance
ground plane with a low effective series resistance (ESR) multilayer
ceramic capacitor (MLCC) of 0.1 μF, typically, as close to the VS
supply pins as possible. When driving heavy loads, add 10 μF of
supply capacitance. When using split supplies, these conditions
are applicable to the −VS supply pin.
100ms/DIV
Figure 61. ADA4097-1 Cycling In and Out of Thermal Shutdown
It is not recommended to operate near the maximum junction
temperature.
Typically, TJ can be estimated from TA and the device power
dissipation (PD × θJA), as shown in the following equation:
The ADA4097-1 has an internal current source of ~0.6 ꢁA on
the SHDN pin to pull the pin down to −VS and to place the
amplifier in the default amplifying state. If the SHDN state is not
required, hard tie the SHDN pin to the −VS pin. If the SHDN pin is
left floating or driven by a source with significant source impe-
dance (>100 ꢀ), bypass the −VS supply pin with a small, 1 nF
capacitor to prevent stray signals from coupling on the SHDN pin,
which can inadvertently trigger shutdown.
TJ = TA + PD × θJA
The power dissipation in the IC varies as a function of supply
voltage, the output voltage, and load resistance. For a given supply
voltage, the worst case power dissipation (PD(MAX)) in the IC occurs
when the supply current is maximum, and the output voltage is
at half of either supply voltage.
V
2
RL
2
SY
PD(MAX) VsIs(MAX)
Rev. 0 | Page 23 of 27
ADA4097-1
Data Sheet
In the circuit shown in Figure 63, R1 is a 220 ꢀ, Panasonic,
0805, ERJ-P6 series, and C1 is a 100 pF, Yageo, 0805, 100 V,
C0G/NPO.
GROUNDING
Use ground and power planes where possible to reduce the
resistance and inductance of the supply and ground returns.
Place bypass capacitors as close as possible to the VS supply
pins, with the other ends connected to the ground plane. It is
recommended to use a bypass capacitor of at least 0.1 μF when
driving light loads (load currents < 100 μA), and more capacitance
when driving heavier loads. Routing from the output to the load
and return to the ground plane must have minimal loop area to
keep inductance to a minimum.
VCC
ADVANTAGES DISADVANTAGES
8
R1
U1
VIN
IN+
3
INEXPENSIVE
(~5 CENTS)
R1 INTRODUCES
THERMAL NOISE
1 VOUT
V+
V–
C1
2
SMALL
RC NETWORK
LIMITS SPEED
FOOTPRINT
VEE
GND
4
MINIMAL
LEAKAGE
NEED TO CAREFULLY
CHARACTERIZE
CAPACITOR
NOT AS ROBUST
AGAINST REPEATED
STRIKES
Figure 63. ESD Protection Circuit (RC Network)
ESD PROTECTION WHEN POWERED
In the circuit shown in Figure 64, R1 is a 220 ꢀ, Panasonic,
0805, ERJ-P6 series, and D1 is a Bourns CDSOD323-T36SC.
An ESD varistor can be considered for D1.
ICs react to ESD strikes differently when unpowered vs.
powered, which falls under IEC-61000-4-2 standards (see
the Absolute Maximum Ratings section). A device that
performs well under HBM conditions can perform poorly
under International Electrotechnical Commission (IEC)
conditions. The ADA4097-1 is thoroughly abused with ESD
strikes under IEC conditions to create a front-end circuit
protection scheme that protects the device if subjected to ESD
strikes. Figure 63 and Figure 64 show two different protection
schemes that extend the protection of the ADA4097-1 to 8 kV
ESD strikes.
For more information on system level ESD considerations, see
the technical article, When Good Electrons Go Bad: How to
Protect Your Analog Front End, on the Analog Devices, Inc.,
website.
RELATED PRODUCTS
Table 8 describes several alternative precision amplifiers that
can also be considered for certain applications.
Consider the following when selecting components:
A component size of 0805 or larger to reduce chance of
arc-over.
Pulse withstanding, thick film resistors.
C0G MLCC with a minimum rating of 100 V.
Bidirectional, transient voltage suppression (TVS) diodes.
VCC
8
ADVANTAGES DISADVANTAGES
R1
U1
VIN
IN+
3
2
INEXPENSIVE
R1 INTRODUCES
1
VOUT
(20 TO 30 CENTS) NOISE
V+
V–
D_TVS
D1
SMALL
FOOTPRINT
D1 HAS LEAKAGE
CURRENT
GND
4
VEE
VERY ROBUST
D1 HAS
CAPACITANCE
(5pF TO 300pF)
Figure 64. ESD Protection Circuit (R-TVS Network)
Table 8. ADA4097-1 Related Products
Model
VOS (μV)
±0
30
30
35
50
±0
375
500
IB (nA)
0.3
0.7
10
1
5
0.ꢁ
1
GBP (kHz)
130
en (nVꢀ√Hz)
ISY (ꢁA)
33
Common-Mode Input Range (V)
−VS to −VS + 70
−VS to −VS + 70
−VS to −VS + 70
−VS to +VS
−VS to −VS + 7±
−VS to +VS
−VS to −VS + 3±
−VS to −VS + ꢁꢁ
ADAꢁ0ꢂ7-1
ADAꢁ0ꢂꢀ-1
ADAꢁ0ꢂꢂ-1
ADAꢁ077-1
LT±015
LT±01ꢁ
LT1ꢁꢂꢁ
LT1ꢁꢂ0A
53
17
7
1000
ꢀ000
3ꢂ00
3200
1±00
2.7
1±5
1500
500
335
1±5
1.5
7
1ꢀ
ꢂ.5
1ꢀ5
50
ꢀ
1ꢀ0
55
Rev. 0 | Page 2ꢁ of 27
Data Sheet
ADA4097-1
TYPICAL APPLICATIONS
5kΩ
5V
1.25kΩ
+
LT6654-2.5
SHDN
–
V
OUT
1.25kΩ
ADA4097-1
5V
IN
OUT
GND
C2
100nF
C1
10µF
5kΩ
±10V
LT5400-7
Figure 65. 10 V to 0 V to +5 V Funnel Amplifier, High CMRR and 80 V Input Protection via LT5400-7 Resistor Network
V
= 5V
SY
INPUT
OUTPUT
5V/DIV
V
OUT
V
IN
TIME (200µs/DIV)
Figure 66. 10 V to 0 V to +5 V Funnel Amplifier, Input and Output Voltages
0
DIFFERENTIAL
–10
–20
–30
–40
COMMON MODE
–50
–60
–70
–80
–90
0.1
1
10
100
1k
FREQUENCY (kHz)
Figure 67. 10 V to 0 V to +5 V Funnel Amplifier, System Gain
Rev. 0 | Page 25 of 27
ADA4097-1
Data Sheet
V
= 5V
SY
OUTPUT
INPUT
2V/DIV
V
OUT
V
IN
TIME (200µs/DIV)
Figure 68. 10 V to 0 V to +5 V Funnel Amplifier, Large Signal Pulse Response
R3
R2
V
OUT
1kΩ
9.09kΩ
D1*
5V
+
1N4148
V
BAT
SHDN
R4
ADA4097-1
–
909Ω
R1
0.1Ω
*DIODE IMPROVES SINGLE SUPPLY AMPLIFIER
ACCURACY AT LOW LOAD CURRENTS
Figure 69. 1 V/A Low-Side Current Sense
100Ω
ADA4097-1
5V
0.1Ω
10W
M1
V
= 1.5V TO 70V
BAT
BSS123LT1G
SHDN
100Ω
100Ω
V
OUT
1V/A
LOAD
10mA TO 1A
1kΩ
Figure 70. 1 V/A High-Side Current Sense
1.8V TO 5V LOGIC
A1
R3
R2
SHDN
1kΩ
10kΩ
15V
SHDN
M1
BSS84
ADA4097-1
R4
10MΩ
C1
1nF
–15V
Figure 71. Microprocessor Control of SHDN Pin in Split Supply Applications
Rev. 0 | Page 2± of 27
Data Sheet
ADA4097-1
OUTLINE DIMENSIONS
3.05
2.90
2.75
6
1
5
2
4
3
3.05
2.80
2.55
1.75
1.60
1.45
TOP VIEW
0.95 BSC
1.90 REF
0.90
SIDE VIEW
END VIEW
0.87
0.84
1.00 MAX
0.20
0.08
0.60
0.45
0.30
8°
4°
0°
SEATING
PLANE
0.60
REF
0.10 MAX
0.50
0.30
COMPLIANT TO JEDEC STANDARDS MO-193-AA
Figure 72. 6-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADAꢁ0ꢂ7-1BUJZ-R5
ADAꢁ0ꢂ7-1BUJZ-RL7
ADAꢁ0ꢂ7-1HUJZ-RL7
EVAL-ADAꢁ0ꢂ7-1HUJZ
Temperature Range
−ꢁ0°C to +125°C
−ꢁ0°C to +125°C
−55°C to +150°C
Package Description
±-Lead TSOT
±-Lead TSOT
±-Lead TSOT
Evaluation Board
Package Option
Marking Code
UJ-±
UJ-±
UJ-±
Y7K
Y7K
Y7L
1 Z = RoHS Compliant Part.
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