ADA4099-2BRMZ-RL7 [ADI]
50 V, 8 MHz, 1.5 mA per Channel, Robust, Over-The-Top, Precision Op Amps;
| 型号： | ADA4099-2BRMZ-RL7 |
| 厂家： | 
ADI |
| 描述： | 50 V, 8 MHz, 1.5 mA per Channel, Robust, Over-The-Top, Precision Op Amps |
| 文件： | 总34页 (文件大小：1962K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ADA4099-1/ADA4099-2
50 V, 8 MHz, 1.5 mA per Channel, Robust, Over-The-Top, Precision Op Amps
FEATURES
GENERAL DESCRIPTION
► Ultrawide common-mode range: −VS − 0.1 V to −VS + 70 V
► Wide power supply voltage range: (VSY): +3.15 V to +50 V (±25
V for PSRR)
► Low supply current: 1.5 mA per channel (typical)
► Low input offset voltage: ±40 µV maximum
► Low input offset voltage drift: ±0.4 μV/°C maximum
► Low voltage noise:
► 1/f noise corner: 6 Hz typical
► 150 nV p-p typical at 0.1 Hz to 10 Hz
► 7 nV/√Hz typical at 100 Hz (en)
► High speed
► GBP: 8 MHz typical
► Slew rate: 5.5 V/µs typical at ΔVOUT = 25 V
► Low power shutdown: 20 µA maximum
► Low input bias current: ±10 nA maximum
► Large signal voltage gain: 120 dB minimum
► CMRR: 118 dB, minimum
The ADA4099-1 and ADA4099-2 are single/dual robust, precision,
rail-to-rail input/output operational amplifiers (op amps) with inputs
that operate from −VS to +VS and beyond, which is referred to
™
in this data sheet as Over-The-Top . The devices feature offset
voltages of <40 µV, input bias currents (IB) of <10 nA, and can
operate on single or split supplies that range from 3.15 V to 50 V.
The ADA4099-1 and ADA4099-2 draws 1.5 mA of quiescent current
per channel.
The ADA4099-1 and ADA4099-2 Over-The-Top input stages have
robust input protection features for abusive environments. The
inputs can tolerate up to 80 V of differential voltage without damage
or degradation to dc accuracy. The operating input common-mode
range extends from rail-to-rail and beyond, up to 70 V > –VS,
independent of the +VS supply.
The ADA4099-1 and ADA4099-2 are unity-gain stable and can
drive loads requiring up to 20 mA per channel. The device can
also drive capacitive loads as large as 100 pF. The amplifiers are
available with low power shutdown.
The ADA4099-1 is available in a standard, 6-lead, thin small outline
transistor (TSOT) package. The ADA4099-2 is available in an 8-
lead, standard small outline package (SOIC_N), 8-lead, mini small
outline package (MSOP), and a 10-lead, lead frame chip scale
package (LFCSP).
► PSRR: 123 dB, minimum
► Input overdrive tolerant with no phase reversal
► ±2 kV HBM and ±1.25 kV FICDM
► Wide temperature range: −55°C to +150°C (H grade)
APPLICATIONS
► Industrial sensor conditioning
► Supply current sensing
► Battery and power supply monitoring
► Front-end amplifiers in abusive environments
► 4 mA to 20 mA transmitters
TYPICAL APPLICATION CIRCUIT
Figure 1. 1 V/A Over-The-Top Current Sense Application (ADA4099-1 6-lead
TSOT)
Figure 2. Output Error vs. Load Current
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Data Sheet
ADA4099-1/ADA4099-2
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
General Description...............................................1
Typical Application Circuit......................................1
Specifications........................................................ 3
5 V Supply..........................................................3
±15 V Supply......................................................5
Absolute Maximum Ratings...................................8
Maximum Power Dissipation..............................8
Thermal Resistance........................................... 8
Electrostatic Discharge (ESD) Ratings...............8
ESD Caution.......................................................9
Pin Configurations and Function Descriptions.....10
Typical Performance Characteristics...................12
Theory of Operation.............................................20
Input Protection................................................ 21
Over-The-Top Operation Considerations......... 21
Output...............................................................22
Shutdown Pins................................................. 22
Applications Information...................................... 24
Large Resistor Gain Operation.........................24
Recommended Values for Various Gains.........24
Noise................................................................ 25
Distortion.......................................................... 25
Power Dissipation and Thermal Shutdown...... 26
Circuit Layout Considerations.......................... 26
Power Supply Bypassing..................................26
Grounding.........................................................26
ESD Protection when Powered........................27
Related Products..............................................27
Typical Applications..........................................28
Outline Dimensions............................................. 30
Ordering Guide.................................................34
Evaluation Boards............................................ 34
REVISION HISTORY
1/2022—Rev. 0 to Rev. A
Added ADA4099-2...........................................................................................................................................1
Change to Data Sheet Title..............................................................................................................................1
Changes to Features Section.......................................................................................................................... 1
Changes to General Description Section.........................................................................................................1
Changes to 5 V Supply Section and Table 1....................................................................................................3
Changes to ±15 V Supply Section and Table 2................................................................................................5
Changes to Table 3..........................................................................................................................................8
Changes to Table 4..........................................................................................................................................8
Change to Table 6 Title..................................................................................................................................10
Added Figure 5, Figure 6, Table 7, and Table 8; Renumbered Sequentially..................................................10
Added Figure 50............................................................................................................................................ 19
Changes to Shutdown Pins Section and Title................................................................................................22
Changes to Power Supply Bypassing............................................................................................................26
Changes to Table 10......................................................................................................................................27
Added Figure 76, Figure 77, and Figure 78...................................................................................................30
Changes to Ordering Guide...........................................................................................................................34
1/2021—Revision 0: Initial Version
analog.com
Rev. A | 2 of 34
Data Sheet
ADA4099-1/ADA4099-2
SPECIFICATIONS
5 V SUPPLY
Common-mode voltage (VCM) = 2.5 V, SHDN pin (ADA4099-1) and SHDNx pins (ADA4099-2 10-lead LFCSP) are open, load resistance (RL) =
499 kΩ to midsupply, ambient temperature (TA) = 25°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
B Grade
Typ
H Grade
Typ
Unit
Min
Max
Min
Max
DC PERFORMANCE
1
Input Offset Voltage (VOS
)
0.25 V < VCM < 3.25 V
±10
±40
±90
±10
±40
±90
µV
µV
Minimum temperature (TMIN) < TA
<
maximum temperature (TMAX
0.25 V < VCM < 70 V
TMIN < TA < TMAX
)
±25
±25
±65
±125
±70
±125
±0.4
±10
±15
98
±25
±25
±65
±140
±70
±200
±0.8
±10
±30
98
µV
µV
µV
µV
µV/°C
nA
nA
µA
µA
µA
µA
nA
nA
µA
µA
dB
−0.1 V < VCM < +70 V
TMIN < TA < TMAX
Input Offset Voltage Drift2
Input Bias Current (IB)
TMIN < TA < TMAX
±0.1
±4
±0.1
±4
TMIN < TA < TMAX
VCM = 70 V, Over-The-Top
TMIN < TA < TMAX
70
40
82.5
0.001
±2
70
40
82.5
0.001
±2
125
10
125
10
0 V < VCM < 70 V, VSY = 0 V
TMIN < TA < TMAX
25
25
Input Offset Current (IOS
)
±4
±4
TMIN < TA < TMAX
VCM = 70 V, Over-The-Top3
±10
±2
±20
±2
±0.5
136
±0.5
136
TMIN < TA < TMAX
±5
±5
Common-Mode Rejection Ratio
(CMRR)
VCM = −0.1 V to +70 V
118
118
TMIN < TA < TMAX
110
108
dB
dB
dB
V
VCM = 0.25 V to 3.25 V
TMIN < TA < TMAX
114
132
114
132
108
108
Common-Mode Input Range
Guaranteed by CMRR tests
ΔVOUT = 4 V
−VS − 0.1
126
−VS + 70
−VS − 0.1
126
−VS + 70
Large Signal Voltage Gain (AOL
)
140
130
140
130
dB
dB
dB
dB
TMIN < TA < TMAX
116
110
ΔVOUT = 4 V, RL = 10 kΩ
TMIN < TA < TMAX
120
120
110
102
NOISE PERFORMANCE
Input Voltage Noise
Frequency (f) = 0.1 Hz to 10 Hz
1/f noise corner
150
6
150
6
nV p-p
Hz
f = 100 Hz
7
7
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
Over-The-Top
Input Current Noise
Over-The-Top
f = 100 Hz, VCM > 5 V
f = 100 Hz
8
8
0.5
5
0.5
5
f = 100 Hz, VCM > 5 V
DYNAMIC PERFORMANCE
Slew Rate
ΔVOUT = 2 V
2.7
4
8
2.7
1.75
7.5
4
8
V/μs
V/μs
MHz
MHz
Degrees
μs
TMIN < TA < TMAX
1.75
7.5
Gain Bandwidth Product (GBP)
Test frequency (fTEST) = 25 kHz
TMIN < TA < TMAX
6.75
6.5
Phase Margin
47
47
1% Settling Time
ΔVOUT = ±2 V
1.15
1.15
analog.com
Rev. A | 3 of 34
Data Sheet
ADA4099-1/ADA4099-2
SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
B Grade
Typ
H Grade
Typ
Unit
Min
Max
Min
Max
0.1% Settling Time
ΔVOUT = ±2 V
1.5
1.5
μs
%
Total Harmonic Distortion Plus Noise
(THD + N)
f = 10 kHz, VOUT = 2 V p-p, RL = 10 kΩ,
bandwidth = 80 kHz
0.001
0.001
Channel Separation
INPUT CHARACTERISTICS
Input Resistance
f = 1 kHz, RL = 2 kΩ
115
115
dB
Differential mode
100
>1
100
>1
kΩ
GΩ
Ω
Common mode
Over-The-Top
Differential mode, VCM > 5 V
Common mode, VCM > 5 V
Differential mode
600
>100
9
600
>100
9
MΩ
pF
pF
Input Capacitance
Common mode
3
3
SHDN AND SHDNx PINS
Input Logic Low
Amplifier active, SHDN and SHDNx
voltage (VSHDN) < −VS + 0.5 V, TMIN
< TA < TMAX
−VS + 0.5
−VS + 0.5
V
V
Input Logic High
Response Time
Pull-Down Current
Amplifier shutdown, VSHDN
>
−VS + 1.5
−VS + 1.5
−VS + 1.5 V, TMIN < TA < TMAX
Amplifier active to shutdown
2.5
10
2.5
10
μs
μs
µA
µA
Amplifier shutdown to active
VSHDN = −VS + 0.5 V, TMIN < TA < TMAX
VSHDN = −VS + 1.5 V, TMIN < TA < TMAX
0.6
0.3
3
0.6
0.3
3
2.5
2.5
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
Overdrive voltage (VOD4) = 30 mV, no
load
45
60
45
60
mV
TMIN < TA < TMAX
105
325
120
325
mV
mV
VOD = 30 mV, sink current, (ISINK) =
10 mA
260
260
TMIN < TA < TMAX
VOD = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, source current,
(ISOURCE) = 10 mA
TMIN < TA < TMAX
ISOURCE
435
55
450
55
mV
mV
mV
mV
Output Voltage Swing High
Short-Circuit Current
45
45
110
1100
140
1100
900
900
1500
1650
mV
mA
mA
mA
mA
nA
20
15
40
20
30
20
15
40
20
30
TMIN< TA < TMAX
ISINK
50
50
TMIN < TA < TMAX
Output Pin Leakage During Shutdown VSHDN = −VS + 1.5 V
TMIN < TA < TMAX
±0.01
±100
±10
±0.01
±100
±10
µA
POWER SUPPLY
Maximum Operating Voltage5
50
50
50
50
V
V
Voltage Range
Guaranteed by power supply rejection
3.15
3.15
ratio (PSRR)
Supply Current/Channel
Amplifier active
TMIN < TA < TMAX
1.5
12
1.6
2.2
20
1.5
12
1.6
2.35
20
mA
mA
µA
Amplifier shutdown VSHDN = −VS + 1.5
V
TMIN < TA < TMAX
22.5
22.5
µA
analog.com
Rev. A | 4 of 34
Data Sheet
ADA4099-1/ADA4099-2
SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
B Grade
Typ
H Grade
Typ
Unit
Min
Max
Min
Max
PSRR
VSY = 3.15 V to ±25 V
TMIN < TA < TMAX
123
119
136
123
120
136
dB
dB
THERMAL SHUTDOWN6
Temperature
Junction temperature (TJ)
Ambient temperature (TA)
175
20
175
20
°C
°C
°C
Hysteresis
Operating Temperature
−40
+125
−55
+150
1
Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 1 are determined by test
capability and are not necessarily indicative of actual device performance.
2
3
Offset voltage drift is guaranteed through lab characterization and is not production tested.
Test accuracy is limited by high speed production test equipment repeatability. Bench measurements indicate that the input offset current in Over-The-Top configuration is
typically controlled to under 250 nA at +25°C and 1000 nA over the −55°C < TA < +150°C temperature range.
4
5
VOD is +30 mV for VOUT high and −30 mV for VOUT low.
Maximum operating voltage is limited by the time-dependent dielectric breakdown (TDDB) of on-chip capacitor oxides. The amplifier tolerates temporary transient overshoot
up to the specified absolute maximum rating, but the dc supply voltage must be limited to the maximum operating voltage.
6
Thermal shutdown is lab characterized only and is not tested in production.
±15 V SUPPLY
VCM = 0 V, SHDN pin (ADA4099-1) and SHDNx pins (ADA4099-2 10-lead LFCSP) are open, RL = 499 kΩ to ground, and TA = 25°C, unless
otherwise noted.
Table 2.
B Grade
Typ
H Grade
Typ
Parameter
Test Conditions/Comments
Min
Max
Min
Max
Unit
DC PERFORMANCE
1
Input Offset Voltage (VOS
)
±12
±15
±40
±95
±40
±105
±12
±15
±40
±90
±40
±90
µV
µV
µV
µV
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
Input Offset Voltage Drift2
Input Bias Current
TMIN < TA < TMAX
±0.1
±4
±0.4
±10
±25
±10
±35
±5
±0.1
±4
±0.9
±10
±60
±10
±100
±5
µV/°C
nA
nA
nA
nA
nA
nA
nA
nA
dB
dB
dB
dB
dB
dB
V
TMIN < TA < TMAX
VSY = ±25 V
±4
±4
TMIN < TA < TMAX
Input Offset Current
CMRR
±2
±2
TMIN < TA < TMAX
±15
±5
±30
±5
VSY = ±25 V
±4
±4
TMIN < TA < TMAX
±20
±35
VCM = −14.75 V to +13.25 V
TMIN < TA < TMAX
118
112
115
105
117
110
−15.1
130
126
126
118
114
115
101
117
107
−15.1
130
126
126
VCM = −15.1 V to +13.25 V
TMIN < TA < TMAX
VCM = −15.1 V to +55 V
TMIN < TA < TMAX
Common-Mode Input Range
Guaranteed by CMRR tests
+55
+55
analog.com
Rev. A | 5 of 34
Data Sheet
ADA4099-1/ADA4099-2
SPECIFICATIONS
Table 2.
B Grade
Typ
H Grade
Parameter
Test Conditions/Comments
Min
Max
Min
Typ
Max
Unit
AOL
ΔVOUT = 25 V
134
120
120
114
154
134
116
120
110
154
dB
dB
dB
dB
TMIN < TA < TMAX
ΔVOUT = 25 V, RL =10 kΩ
TMIN < TA < TMAX
134
134
NOISE PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz
1/f noise corner
f = 100 Hz
150
6
150
6
nV p-p
Hz
7
7
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
Over-The-Top
Input Current Noise
Over-The-Top
f = 100 Hz, VCM > +VS
f = 100 Hz
8
8
0.5
5
0.5
5
f = 100 Hz, VCM > +VS
DYNAMIC PERFORMANCE
Slew Rate
ΔVOUT = 25 V
3.5
2.0
5.5
8
3.5
2.0
7.5
6.5
5.5
8
V/μs
V/μs
MHz
MHz
Degrees
μs
TMIN < TA < TMAX
fTEST = 25 kHz
TMIN < TA < TMAX
GBP
7.5
6.75
Phase Margin
1% Settling Time
0.1% Settling Time
THD + N
57
57
ΔVOUT = ±2 V
ΔVOUT = ±2 V
1.15
1.5
1.15
1.5
μs
f = 10 kHz, VOUT = 5.6 V p-p, RL
10 kΩ, bandwidth = 80 kHz
=
0.001
0.001
%
Channel Separation
INPUT CHARACTERISTICS
Input Resistance
f = 1 kHz, RL = 2 kΩ
115
115
dB
Differential mode
Common mode
Differential mode
Common mode
100
>1
9
100
>1
9
kΩ
GΩ
pF
Input Capacitance
3
3
pF
SHDN AND SHDNx PINS
Input Logic Low
Amplifier active, VSHDN < −VS + 0.5 V
−VS + 0.5
−VS + 0.5
V
Input Logic High
Amplifier shutdown, VSHDN > −VS + 1.5 V −VS + 1.5
Amplifier active to shutdown
−VS + 1.5
V
Response Time
2.5
10
2.5
10
μs
μs
µA
µA
Amplifier shutdown to active
Pull-Down Current
VSHDN = −VS + 0.5 V, TMIN < TA < TMAX
VSHDN = −VS + 1.5 V, TMIN < TA < TMAX
0.6
0.3
3
0.6
0.3
3
2.5
2.5
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
VOD3 = 30 mV, no load
TMIN < TA < TMAX
45
60
45
60
mV
mV
mV
mV
mV
mV
mV
mV
115
325
435
55
125
325
450
55
VOD = 30 mV, ISINK = 10 mA
TMIN < TA < TMAX
260
45
260
45
Output Voltage Swing High
VOD = 30 mV, no load
TMIN < TA < TMAX
140
1100
1500
165
1100
1650
VOD = 30 mV, ISOURCE = 10 mA
TMIN < TA < TMAX
900
900
analog.com
Rev. A | 6 of 34
Data Sheet
ADA4099-1/ADA4099-2
SPECIFICATIONS
Table 2.
B Grade
Typ
H Grade
Parameter
Test Conditions/Comments
Min
Max
Min
Typ
Max
Unit
Short-Circuit Current
ISOURCE
25
20
40
20
34
25
20
40
20
34
mA
mA
mA
mA
TMIN < TA < TMAX
ISINK
50
50
TMIN < TA < TMAX
POWER SUPPLY
Maximum Operating Voltage4
50
50
1.8
2.45
2
50
50
1.8
2.6
2
V
Voltage Range
Guaranteed by PSRR
Amplifier active
3.15
3.15
V
Supply Current/Channel
1.65
1.75
17
1.65
1.75
17
mA
mA
mA
mA
µA
µA
dB
dB
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
2.7
24
27
2.85
24
27
Amplifier shutdown, VSHDN = −VS + 1.5 V
TMIN < TA < TMAX
PSRR
VSY = 3.15 V to 50 V
TMIN < TA < TMAX
123
119
136
123
120
136
THERMAL SHUTDOWN5
Temperature
TJ
175
20
175
20
°C
°C
°C
Hysteresis
Operating Temperature
TA
−40
+125
−55
+150
1
Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 2 are determined by test
capability and are not necessarily indicative of actual device performance.
2
3
4
Offset voltage drift is guaranteed through lab characterization and is not production tested.
VOD is +30 mV for VOUT high and −30 mV for VOUT low.
Maximum operating voltage is limited by the TDDB of on-chip capacitor oxides. The amplifier tolerates temporary transient overshoot up to the specified absolute maximum
rating and the dc supply voltage must be limited to the maximum operating voltage.
5
Thermal shutdown is lab characterized only and is not tested in production.
analog.com
Rev. A | 7 of 34
Data Sheet
ADA4099-1/ADA4099-2
ABSOLUTE MAXIMUM RATINGS
Table 3.
The PD due to the load drive depends on the application. The PD
due to load drive is calculated by multiplying the load current by
the associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
Parameter
Rating
Supply Voltage1
Transient
60 V
Continuous
50 V
Airflow increases heat dissipation, effectively reducing θJA. Addi-
tional metal that is directly in contact with the package leads from
metal traces through vias, ground, and power planes reduces θJA
Power Dissipation (PD)
Differential Input Voltage
±IN Pin Voltage
See Figure 3
±80 V
.
Figure 3 shows the maximum PD vs. TA for the single and dual
Continuous
−5 V to +80 V
−10 V to +80 V
20 mA
6-lead TSOT packages on a JEDEC standard, 4‑layer board, with
−VS connected to a pad that is thermally connected to a printed
circuit board (PCB) plane. θJA values are approximations.
Survival
±IN Pin Current
SHDN and SHDNx Voltage2
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature (TJ)
−0.3 V to +60 V
−65°C to +150°C
−55°C to +150°C
300°C
175°C
1
Maximum supply voltage is limited by the TDDB of on-chip capacitor oxides.
The amplifiers tolerate temporary transient overshoot up to the specified
transient maximum rating. The continuous operating supply voltage must be
limited to no more than 50 V.
2
SHDN is Pin 5 on the ADA4099-1. SHDNx refers to SHDN1 and SHDN2 (Pin 5
and Pin 6, respectively) on the ADA4099-2 10-lead LFCSP).
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
THERMAL RESISTANCE
Junction temperatures (TJ) exceeding 125°C promote accelerated
aging. The ADA4099-1 and ADA4099-2 demonstrates ±25 V supply
operation beyond 1400 hours at TA = 140°C.
Thermal performance is directly linked to PCB design and operating
environment. Careful attention to PCB thermal design is required.
θJA is the junction to ambient thermal resistance.
MAXIMUM POWER DISSIPATION
Table 4. Thermal Resistance
The maximum safe power dissipation (PD) on the device is limited
by the associated rise in either case temperature (TC) or TJ on
the die. At approximately TC = 150°C, which is the glass transition
temperature, the properties of the plastic changes. Exceeding this
temperature limit, even temporarily, may change the stresses that
the package exerts on the die, which permanently shifts the para-
metric performance of the ADA4099-1 and ADA4099-2. Exceeding
TJ = 175°C for an extended period may result in changes in the
silicon devices and may cause failure of the device.
Package Type
θJA
Unit
UJ-6
192
120
163
43
°C/W
°C/W
°C/W
°C/W
R-8
RM-8
05-08-1699
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD-sen-
sitive devices in an ESD protected area only.
The PD on the package is the sum of the quiescent power dissipa-
tion and the power dissipated in the package due to the output load
drive. The quiescent power is expressed in the following equation:
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) per ANSI/ESDA/JE-
DEC JS-002.
VSY × ISY
where ISY is the quiescent current.
analog.com
Rev. A | 8 of 34
Data Sheet
ADA4099-1/ADA4099-2
ABSOLUTE MAXIMUM RATINGS
ESD Ratings for ADA4099-1 and ADA4099-2
ESD CAUTION
Table 5. ADA4099-1 6-Lead TSOT, ADA4099-2 8-Lead SOIC_N, ADA4099-2
8-Lead MSOP, ADA4099-2 10-Lead LFCSP
ESD (electrostatic discharge) sensitive device. Charged devi-
ces and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
ESD Model
Withstand Threshold (kV)
Class
HBM
±2
2
3
FICDM
±1.25
analog.com
Rev. A | 9 of 34
Data Sheet
ADA4099-1/ADA4099-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration for ADA4099-1 6-Lead TSOT
Table 6. Pin Function Descriptions for ADA4099-1 6-Lead TSOT
Pin No. Mnemonic Description
1
2
VOUT
−VS
Amplifier Output.
Negative Power Supply. In single-supply applications, this pin is normally soldered to a low impedance ground plane. In split supply applications,
bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible.
3
4
5
+IN
Noninverting Input of the Amplifier.
Inverting Input of the Amplifier.
−IN
SHDN
Op Amp Shutdown. The threshold for shutdown is approximately 1 V above the negative supply. If this pin is not connected or hard tied to −VS, the
amplifier is active. If asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state, and the output of the amplifier goes to a high
impedance state. If this pin is left unconnected, it is recommended to connect a small capacitor of 1 nF between SHDN and −VS to prevent signals
from −IN from capacitively coupling to the SHDN pin.
6
+VS
Positive Power Supply. Bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible.
Figure 5. Pin Configuration for ADA4099-2 8-Lead SOIC_N and 8-Lead MSOP
Table 7. Pin Function Descriptions for ADA4099-2 8-Lead SOIC_N and 8-Lead MSOP
Pin No. Mnemonic Description
1
2
3
4
VOUT1
−IN1
+IN1
−VS
Amplifier Output, Channel 1.
Inverting Input of the Amplifier, Channel 1.
Noninverting Input of the Amplifier, Channel 1.
Negative Power Supply. In single-supply applications, this pin is normally soldered to a low impedance ground plane. In split supply applications,
bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible.
5
6
7
8
+IN2
−IN2
VOUT2
+VS
Inverting Input of the Amplifier, Channel 2.
Noninverting Input of the Amplifier, Channel 2.
Amplifier Output, Channel 2.
Positive Power Supply. Bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible.
analog.com
Rev. A | 10 of 34
Data Sheet
ADA4099-1/ADA4099-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration for ADA4099-2 10-Lead LFCSP
Table 8. Pin Function Descriptions for ADA4099-2 10-Lead LFCSP
Pin No. Mnemonic Description
1
2
3
4
VOUT1
−IN1
+IN1
−VS
Amplifier Output, Channel 1.
Inverting Input of the Amplifier, Channel 1.
Noninverting Input of the Amplifier, Channel 1.
Negative Power Supply. In single-supply applications, this pin is normally soldered to a low impedance ground plane. In split supply applications,
bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible.
5
SHDN1
Op Amp Shutdown, Channel 1. The threshold for shutdown is approximately 1 V above the negative supply. If this pin is not connected or hard tied to
−VS, the amplifier is active. If asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state, and the output of the amplifier goes to
a high impedance state. If this pin is left unconnected, it is recommended to connect a small capacitor of 1 nF between SHDN1 and −VS to prevent
signals from −IN from capacitively coupling to the SHDN1 pin.
6
SHDN2
Op Amp Shutdown, Channel 2. The threshold for shutdown is approximately 1 V above the negative supply. If this pin is not connected or hard tied to
−VS, the amplifier is active. If asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state, and the output of the amplifier goes to
a high impedance state. If this pin is left unconnected, it is recommended to connect a small capacitor of 1 nF between SHDN2 and −VS to prevent
signals from −IN from capacitively coupling to the SHDN2 pin.
7
+IN2
−IN2
VOUT2
+VS
Inverting Input of the Amplifier, Channel 2.
8
Noninverting Input of the Amplifier, Channel 2.
9
Amplifier Output, Channel 2.
10
Positive Power Supply. Bypass this pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the pin as possible.
Exposed Pad. Connect the exposed pad to −VS.
EPAD
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Rev. A | 11 of 34
Data Sheet
ADA4099-1/ADA4099-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. Supply Current vs. Supply Voltage
Figure 10. Shutdown Supply Current vs. Supply Voltage
Figure 8. Supply Current vs. Temperature Across Various Supply Voltages
Figure 11. Typical Distribution of Input Offset Voltage, VSY = 5 V
Figure 9. Supply Current vs. VSHDN with Respect to −VS
Figure 12. Typical Distribution of Input Offset Voltage with VSY = ±15 V
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Rev. A | 12 of 34
Data Sheet
ADA4099-1/ADA4099-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 13. Typical Distribution of Input Offset Voltage with VSY = ±25 V
Figure 16. Offset Voltage vs. Temperature with VSY = ±25 V
Figure 14. Offset Voltage vs. Temperature with VSY = 5 V
Figure 17. Midsupply Input Bias Current vs. Temperature with VSY = 5 V
Figure 15. Offset Voltage vs. Temperature with VSY = ±15 V
Figure 18. Midsupply Input Bias Current vs. Temperature with VSY = ±15 V
analog.com
Rev. A | 13 of 34
Data Sheet
ADA4099-1/ADA4099-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 19. Offset Voltage vs. Temperature with VCM = 6 V, Over-The-Top
Figure 22. Input Bias Current vs. Temperature with VSY = 5 V, Over-The-Top
Figure 20. Offset Voltage vs. Temperature with VCM = 70 V
Figure 23. Midsupply Input Bias Current vs. Temperature Across Various
Supply Voltages
Figure 21. Over-The-Top Input Bias Current vs. Temperature with VCM = 6 V
Figure 24. Offset Voltage vs. Temperature Across Various Supply Voltages
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Rev. A | 14 of 34
Data Sheet
ADA4099-1/ADA4099-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 25. Offset Voltage vs. Input Common-Mode Voltage over the Input
Common-Mode Range
Figure 28. Offset Voltage vs. Input Common-Mode Voltage for Ground
Sensing Applications
Figure 26. Offset Voltage vs. Input Common-Mode Voltage from Normal
Operation to Over-The-Top Operation
Figure 29. Input Bias Current vs. Input Common-Mode Voltage for Ground
Sensing Applications
Figure 27. Input Bias Current vs. Input Common-Mode Voltage from Normal
Operation to Over-The-Top Operation
Figure 30. Input Bias Current vs. Input Common-Mode Voltage
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Rev. A | 15 of 34
Data Sheet
ADA4099-1/ADA4099-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 31. Supply Current vs. Minimum Supply Voltage
Figure 34. Δ Offset Voltage vs. Output Voltage (VOUT)
Figure 32. Offset Voltage vs. Minimum Supply Voltage
Figure 35. Δ Offset Voltage vs. VOUT (2 kΩ Load)
Figure 33. Offset Voltage vs. Supply Voltage
Figure 36. SHDN Pin Current vs. VSHDN with Respect to −VS over Various
Temperatures
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Rev. A | 16 of 34
Data Sheet
ADA4099-1/ADA4099-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 37. Output Voltage Low (VOL) and Output Voltage High (VOH) vs.
Temperature
Figure 40. Noninverting Small Signal Frequency Response
Figure 41. Inverting Small Signal Frequency Response
Figure 38. Gain Bandwidth vs. Temperature
Figure 39. Loop Gain and Phase vs. Frequency
Figure 42. Unity-Gain Output Noise Density vs. Frequency
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Rev. A | 17 of 34
Data Sheet
ADA4099-1/ADA4099-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 46. THD + N vs. Frequency over Load
Figure 43. 0.1 Hz to 10 Hz Noise
Figure 47. THD + N vs. Output Amplitude
Figure 44. Unity-Gain Small Signal Step Response
Figure 48. THD + N vs. Output Amplitude and Load
Figure 45. Unity-Gain Large Signal Step Response
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Rev. A | 18 of 34
Data Sheet
ADA4099-1/ADA4099-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 49. CMRR vs. Frequency
Figure 51. Output Impedance vs. Frequency
Figure 50. PSRR vs. Frequency
Figure 52. Channel Separation vs. Frequency
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Rev. A | 19 of 34
Data Sheet
ADA4099-1/ADA4099-2
THEORY OF OPERATION
The ADA4099-1 and ADA4099-2 are single/dual robust, voltage
feedback amplifiers that combine unity-gain stability with low offset,
low offset drift, and 7 nV/√Hz of input noise. Figure 55 shows a
simplified schematic of the device. The ADA4099-1 and ADA4099-2
have two input stages: a common emitter differential input stage
consisting of the Q1 and Q2 PNP transistors that operate with the
inputs biased between −VS and 1.5 V below +VS, and a common
base input stage that consists of the Q3 to Q6 PNP transistors
that operate when the common-mode input is biased >+VS − 1.5
V. These input stages result in two distinct operating regions, as
shown in Figure 53.
For common-mode input voltages that are approximately 1.5 V
below the +VS supply, where Q1 and Q2 are active (see Figure
53), the common emitter PNP input stage is active and the input
bias current is typically <4 nA. When the common-mode input is
above +VS − 1.5 V, the Q9 transistor turns on, which diverts bias
current away from the common emitter differential input pair to the
mirror that consists of M3 and M4. The current from M4 biases the
common base differential input pair (Q3 to Q6). The Over-The-Top
input pair operates in a common base configuration and the input
bias current increases to ~82.5 µA. The offset voltages of both input
stages are tightly trimmed and are specified in Table 1 and Table 2.
As the input common-mode transitions to the Over-The-Top region,
the input CMRR degrades slightly when compared to the rest of the
input common-mode range, as shown in Figure 54.
Figure 53. Input Bias Current vs. Input Common-Mode Voltage over
Temperature, VSY = 5 V
Figure 54. Offset Voltage vs. Input Common-Mode Voltage over Temperature,
VSY = 5 V
Figure 55. Simplified ADA4099-1 and ADA4099-2 Schematic
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Rev. A | 20 of 34
Data Sheet
ADA4099-1/ADA4099-2
THEORY OF OPERATION
INPUT PROTECTION
The inputs are protected against temporary voltage excursions to
10 V below –VS (see Figure 56) by an internal 250 Ω resistor (see
Figure 55). This resistor limits the current in the series D1 diode
and D2 diode that are tied to the bases of the Q1 and Q2 tran-
sistors, respectively. Adding additional external series resistance
extends the protection to >10 V below −VS, at the cost of stability
and added thermal noise. The input stage of the ADA4099-1 and
ADA4099-2 incorporates phase reversal protection to prevent the
output from phase reversing for inputs below −VS. The ADA4099-1
and ADA4099-2 op amps do not have clamping diodes between
the inputs and can be differentially overdriven up to 80 V without
damage, inducing parametric shifts, or drawing appreciable input
current. Figure 57 summarizes the input fault types that can be
applied to the ADA4099-1 and ADA4099-2 without compromising
input integrity.
Figure 57. ADA4099-1 and ADA4099-2 Fault Tolerant Conditions
OVER-THE-TOP OPERATION
CONSIDERATIONS
When the ADA4099-1 and ADA4099-2 input common-modes are
biased near or >+VS supply, the amplifiers operate in the Over-The-
Top configuration. The differential input pair that controls amplifier
operation is the common base pair, Q3 to Q6 (see Figure 55).
Input bias currents change from <±4 nA in normal operation to
approximately 82.5 μA in Over-The-Top operation when the input
stage transitions from common emitter to common base. The Over-
The-Top input bias currents are well matched, and the associated
offset is typically <250 nA. Ensure that the impedance connected to
the inverting and noninverting inputs is well matched to avoid any
input bias current induced voltage offsets.
Figure 56. ADA4099-1 and ADA4099-2 as Unity-Gain Buffers with
Noninverting Inputs Driven Beyond the Supply (VSY = 5 V)
Differential input impedance, RIN (see Figure 58), decreases from
>100 kΩ in normal operation to ~600 Ω in Over-The-Top operation
(see Table 1 and Table 2).
Figure 58. Difference Amplifier Configured for Normal Operation and Over-
The-Top Operation
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Rev. A | 21 of 34
Data Sheet
ADA4099-1/ADA4099-2
THEORY OF OPERATION
This RIN resistance appears across the summing nodes in Over-
The-Top operation due to the configuration of the common base
input stage.
In normal operation,
GBP
BWCLOSED_LOOP
≈
R
F
1 +
R
I
The RIN value is derived from the specified IB that flows to the op
amp inputs, as expressed in the following equation:
In Over-The-Top operation,
GBP
RIN = 2kT/(qIB)
BWCLOSED_LOOP
≈
Noise Gain
OTT
where:
k is Boltzmann’s constant.
T is the operating temperature.
q is the charge of an electron.
IB is the operating input bias current in Over-The-Top operation.
Output voltage noise density (eno) is impacted when the device
transitions from normal operation to Over-The-Top operation. Resis-
tor noise is neglected in both modes of operation in the following
equations:
In normal operation, neglecting resistor noise,
The inputs are biased proportional to absolute temperature. There-
fore, RIN is relatively constant with temperature. This resistance
appears across the summing nodes of the amplifiers, which is
forced to 0 V differentially by the feedback action of the amplifi-
ers and can seem relatively harmless. However, depending on
the configuration, this input resistance can boost the noise gain,
lower overall amplifier loop gain and closed-loop bandwidth, and
raise output noise. The singular benefit of this configuration is an
increase in closed-loop amplifier stability.
R
F
eno ≅ en 1 +
R
I
where en is input referred voltage noise density.
In Over-The-Top operation, neglecting resistor noise,
eno ≅ en × Noise GainOTT
OUTPUT
In normal mode (−VS < VCM < +VS −1.5 V), RIN is typically large
compared to the value of the gain setting resistors (RF and RI), and
RIN can be ignored.
The output of the ADA4099-1 and ADA4099-2 can swing rail-to-rail
to within 45 mV of either supply with no load. The output can source
and sink ~30 mA. The amplifiers are internally compensated to
drive at least 100 pF of load capacitance (CL). Adding a series
resistance of 50 Ω between the output and larger capacitive loads
extends the capacitive drive capability of the amplifiers.
In this case, the noise gain is defined by the following equation:
Noise Gain = 1 + RF/RI
When the amplifiers transition to Over-The-Top operation with the
input common-mode biased near or above the +VS supply, consider
the value of RIN.
If the ADA4099-1 and ADA4099-2 enter shutdown, the VOUT pin
appears as high impedance with two steering diodes connected to
either supply. In this state, the output typically leaks <5 nA.
The noise gain of the amplifiers increases as shown in the following
equation:
SHUTDOWN PINS
The ADA4099-1 and ADA4099-2 have dedicated shutdown pins
(SHDN for the ADA4099-1, and SHDN1 and SHDN2 for the
ADA4099-2 10-lead LFCSP) to place the amplifiers in a very low
power shutdown state when asserted high. A logic high is defined
by a voltage ≥1.5 V applied to SHDN and SHDNx with respect to
the −VS pin. In shutdown, the amplifiers draw <15 μA of supply
current (see Figure 59) and the VOUT pin is placed in a high
impedance state.
R
F
+ R
Noise GainOTT
=
1 +
×
R
R
R
F
I
IN
I
R
R
F
I
R
1 +
IN
where Noise GainOTT is the Over-The-Top noise gain.
The dc closed-loop gain remains mostly unaffected (RF/RI). Howev-
er, the loop gain of the amplifiers decreases, as expressed in the
following equation:
A
A
OL
R
OL
Noise Gain
to
F
OTT
1 +
R
I
Likewise, the closed-loop bandwidth (BWCLOSED_LOOP) of the am-
plifiers changes, going from normal operation to Over-The-Top
operation.
analog.com
Rev. A | 22 of 34
Data Sheet
ADA4099-1/ADA4099-2
THEORY OF OPERATION
Alternatively, the amplifiers can be effectively placed in a low power
state by removing +VS. In this low power state, the inputs typically
leak <1 nA with either ±IN pin or either ±INx biased between −VS
and 70 V above −VS. If the ±IN pins or ±INx pins are taken below
−VS, they appear as a diode connected to the −VS supply in series
with a resistance of 250 Ω. In this condition, limit the current to <30
mA.
Using an external source to drive the output beyond either ±VS
supply under shutdown conditions may produce unlimited current
and may damage the device.
Figure 59. Supply Current vs. VSHDN with Respect to −VS
SHDN or SHDNx can be driven beyond the +VS supply up to the
absolute maximum voltage (60 V with respect to −VS) and draws
little current (<1.5 μA). For normal active amplifier operation, SHDN
or SHDNx can be floated or driven by an external voltage source
low (within 0.5 V of −VS). If SHDN or SHDNx are left floating, an
internal current source (~600 nA) pulls SHDN or SHDNx to –VS,
which places the amplifiers into a default, active amplifying state.
Because of the close proximity of the −IN pin (ADA4099-1) or
−INx pins (ADA4099-2 10-lead LFCSP) and SHDN or SHDNx, fast
edges on the −IN pin or −INx pins may ac-couple to the adjacent
high impedance SHDN or SHDNx, inadvertently placing the devices
in shutdown. If this scenario is a concern, add a 1 nF capacitor
between SHDN or SHDNx and the −VS pin.
analog.com
Rev. A | 23 of 34
Data Sheet
ADA4099-1/ADA4099-2
APPLICATIONS INFORMATION
LARGE RESISTOR GAIN OPERATION
The ADA4099-1 and ADA4099-2 have approximately 12 pF of input
capacitance.
The parallel combination of the feedback resistor (RF) and gain set-
ting resistor (RG) on the inverting input can combine with this input
capacitance (CIN) to form a pole that can reduce bandwidth, cause
frequency response peaking, or produce oscillations (see Figure
61). To mitigate these consequences, place a feedback capacitor
with a value of CF > CIN(RG/RF) in parallel with RF for summing
node impedances >1 kΩ (RF||RG>1 kΩ). This capacitor placement
cancels the input pole and optimizes dynamic performance (see
Figure 60).
For applications where the noise gain is unity (RG→∞), and the
feedback resistor exceeds 1 kΩ, CF ≥ CIN. Optimize PCB layouts
to keep layout related summing node capacitance to an absolute
minimum.
Figure 61. Inverting Gain of 1, Small Signal Frequency Response, RF = RG
10 kΩ
=
RECOMMENDED VALUES FOR VARIOUS
GAINS
Table 9 is a reference for determining various recommended gains
and associated noise performance. The total impedance seen at
the inverting input is kept to <1 kΩ for gains >1 to maintain ideal
small signal bandwidth.
Figure 60. Inverting Gain Schematic
Table 9. Gains and Associated Recommended Resistor Values (TA = 25°C)
Gain RG (kΩ)
RF (kΩ)
CF (pF)
Approximate −3 dB Frequency (MHz)
Total System Noise (nV/√Hz at 1 kHz), Referred to Input
+1
+2
+2
+5
−1
−1
−2
−5
−10
Not applicable
0
Not applicable
8
6.8
7.2
11
1
1
0
4
10
1
10
4.02
10
1
8.2
0
2.7
1.5
2.1
4.8
2.9
1.4
0.75
7.4
22
10
1
8.2
0
14.4
11.3
9.2
8.7
1
2
0
1
4.99
10
0
1
0
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Rev. A | 24 of 34
Data Sheet
APPLICATIONS INFORMATION
NOISE
ADA4099-1/ADA4099-2
by the resistor and current noise density. The ADA4099-1 and
ADA4099-2 have an en of 7 nV/√Hz.
To analyze the noise performance of an amplifier circuit, identify the
noise sources, and then determine if each source has a significant
contribution to the overall noise performance of the amplifiers. To
simplify the noise calculations, noise spectral densities (NSDs)
are used rather than actual voltages, to leave bandwidth out of
the expressions. NSD is generally expressed in nV/√Hz and is
equivalent to the noise in a 1 Hz bandwidth.
If resistor and current noise contributions are less than half this
value, the en introduced by the op amps dominates and provides
optimal noise performance of the devices.
The noise model shown in Figure 62 has six individual noise
sources: the Johnson noise of the three resistors (R1 to R3), the op
amp voltage noise, and the current noise (IN±) in each input of the
amplifiers. Each noise source has its own contribution to the noise
at the output. Noise is generally specified as referring to input (RTI),
but it is often simpler to calculate the noise referred to the output
(RTO), and then divide by the noise gain to obtain the RTI noise.
Figure 63. Noise Contributions vs. Equivalent Input Resistance (REQ
)
For the ADA4099-1 and ADA4099-2, this lower bound of resistance
in the feedback network is about 750 Ω. For the amplifier configu-
ration shown in Figure 62, REQ < 750 Ω provides stable noise
performance. If noise performance is not important, en is typically
fixed for a given TA, en,R increases with the square root of the
resistor value, and the IN × REQ resistance increases linearly, but
does not impact total noise until it approaches the value of en,R
.
With REQ < ~60 kΩ, en,R is larger than IN × REQ. A safe value for
REQ is ~30 kΩ to ensure that IN is not the majority contributor to
total noise seen by the input.
Figure 62. Op Amp Noise Analysis Model
Figure 63 shows the noise contributions for the range of resistance
values discussed in this section.
Assuming IN+ = IN− = IN, the equation for RTI noise can be simpli-
fied to the following form:
DISTORTION
2
2
RTI Noise = en +en, R2+ INREQ
There are two main contributors of distortion in op amps: output
crossover distortion as the output transitions from sourcing to sink-
ing, and distortion caused by nonlinear common-mode rejection. If
the op amps are operating in an inverting configuration, there is
no common-mode induced distortion. If the op amps are operating
in the noninverting configurations within the normal input common-
mode range (−VS to +VS − 1.5 V), distortion is acceptable. When
the inputs transition from normal to Over-The-Top operation or
vice versa, a significant degradation occurs in linearity due to the
change of input circuitry.
en, R = 4kTREQ
REQ = R3 + R1||R2
where:
en is the op amp voltage noise.
en,R is the thermal noise contribution of the surrounding R1 to R3
resistors.
REQ is the equivalent input resistance.
T is the absolute temperature in Kelvin.
As RL decreases, distortion increases due to a net decrease in loop
gain and greater signal swings internal to the amplifiers that are
necessary to drive the load. The lowest distortion can be achieved
with the ADA4099-1 and ADA4099-2 operating in Class A operation
A 50 Ω resistor generates a Johnson noise of 1 nV/√Hz at 25°C.
For optimal performance, the lower bound of resistance in a feed-
back network is determined by the amount of quiescent power and
distortion that can be tolerated. The upper bound is determined
analog.com
Rev. A | 25 of 34
Data Sheet
ADA4099-1/ADA4099-2
APPLICATIONS INFORMATION
in an inverting configuration, with the input common-mode biased at
midsupply.
For a given supply voltage, use Figure 65 as a guide for estimating
the minimum load resistance that the ADA4099-1 and ADA4099-2
can drive for a given supply voltage and a given rise in junction
temperature (ΔTJ). For example, to limit ΔTJ to 50°C, the load
driven on the ±15 V supplies (+30 V total supply) must not be lower
than 1.2 kΩ. It is assumed that θJA is 192°C/W.
POWER DISSIPATION AND THERMAL
SHUTDOWN
The ADA4099-1 and ADA4099-2 can drive heavy loads on power
supplies up to ±25 V. Therefore, ensure that TJ on the integrated
circuit does not exceed 175°C.
Junction temperatures exceeding 125°C promote accelerated ag-
ing. Reliability of the ADA4099-1 and ADA4099-2 may be impaired
if the junction temperature exceeds 175°C. If the junction tempera-
ture exceeds 175°C, the ADA4099-1 and ADA4099-2 have a final
safety measure in the form of a thermal shutdown that shuts off the
output stage and reduces the internal device currents. When this
thermal shutdown function triggers, the output remains disabled in
a high impedance state until the junction temperature drops 20°C.
Persistent heavy loads and elevated ambient temperatures can
cause the ADA4099-1 and ADA4099-2 to oscillate in and out of
thermal shutdown depending on the power dissipated on the die,
until the heavy load is removed (see Figure 64).
Figure 65. Minimum Load Resistance for Given ΔTJ and VSY
CIRCUIT LAYOUT CONSIDERATIONS
Careful and deliberate attention to detail when laying out the
ADA4099-1 and ADA4099-2 boards yields optimal performance.
Power supply bypassing, parasitic capacitance, and component
selection all contribute to the overall performance of the amplifiers.
POWER SUPPLY BYPASSING
On single supplies, solder the −VS supply pin directly to a low
impedance ground plane. Bypass the +VS pin to a low impedance
ground plane with a low effective series resistance (ESR) multilayer
ceramic capacitor (MLCC) of 0.1 µF, typically, as close to the ±VS
supply pins as possible. When driving heavy loads, add 10 µF of
supply capacitance. When using split supplies, these conditions are
applicable to the −VS supply pin.
Figure 64. ADA4099-1 and ADA4099-2 Cycling In and Out of Thermal
Shutdown
It is not recommended to operate near the maximum junction
temperature.
The ADA4099-1 and ADA4099-2 have an internal current source
of ~0.6 μA on the SHDN (ADA4099-1) and SHDNx (ADA4099-2
10-lead LFCSP) pins to pull the pins down to −VS and place the
amplifiers in the default amplifying state. If the shutdown state is
not required, hard tie SHDN or SHDNx to the −VS pin. If SHDN or
SHDNx is left floating or driven by a source with significant source
impedance (>100 Ω), bypass the −VS supply pin with a small,
1 nF capacitor to prevent stray signals from coupling on SHDN or
SHDNx, which can inadvertently trigger shutdown.
Typically, TJ can be estimated from TA and the device power
dissipation (PD × θJA), as shown in the following equation:
TJ = TA + PD × θJA
The power dissipation in the IC varies as a function of supply
voltage, the output voltage, and load resistance. For a given supply
voltage, the worst case power dissipation (PD(MAX)) in the IC occurs
when the supply current is maximum, and the output voltage is at
half of either supply voltage.
GROUNDING
Use ground and power planes where possible to reduce the re-
sistance and inductance of the supply and ground returns. Place
bypass capacitors as close as possible to the ±VS supply pins, with
2
V
SY
2
PD(MAX) = VsIs(MAX)
+
R
L
analog.com
Rev. A | 26 of 34
Data Sheet
ADA4099-1/ADA4099-2
APPLICATIONS INFORMATION
the other ends connected to the ground plane. It is recommended
to use a bypass capacitor of at least 0.1 µF when driving light
loads (load currents < 100 µA), and more capacitance when driving
heavier loads. Routing from the output to the load and return to the
ground plane must have minimal loop area to keep inductance to a
minimum.
ESD PROTECTION WHEN POWERED
Figure 66. ESD Protection Circuit (RC Network)
ICs react to ESD strikes differently when unpowered vs. powered,
which falls under IEC-61000-4-2 standards (see the Absolute Max-
imum Ratings section). A device that performs well under HBM
conditions can perform poorly under International Electrotechnical
Commission (IEC) conditions. The ADA4099-1 and ADA4099-2
are thoroughly abused with ESD strikes under IEC conditions
to create a front-end circuit protection scheme that protects the
devices if subjected to ESD strikes. Figure 66 and Figure 67 show
two different protection schemes that extend the protection of the
ADA4099-1 and ADA4099-2 to ±8 kV ESD strikes.
In the circuit shown in Figure 67, R1 is a 220 Ω, Panasonic, 0805,
ERJ-P6 series, and D1 is a Bourns CDSOD323-T36SC. An ESD
varistor can be considered for D1.
For more information on system level ESD considerations, see the
technical article, When Good Electrons Go Bad: How to Protect
Your Analog Front End, on the Analog Devices, Inc., website.
RELATED PRODUCTS
Table 10 describes several alternative precision amplifiers that can
also be considered for certain applications.
Consider the following when selecting components:
► A component size of 0805 or larger to reduce chance of arc-over.
► Pulse withstanding, thick film resistors.
► C0G MLCC with a minimum rating of 100 V.
► Bidirectional, transient voltage suppression (TVS) diodes.
In the circuit shown in Figure 66, R1 is a 220 Ω, Panasonic, 0805,
ERJ-P6 series, and C1 is a 100 pF, Yageo, 0805, 100 V, C0G/NPO.
Figure 67. ESD Protection Circuit (R-TVS Network)
Table 10. ADA4099-1 and ADA4099-2 Related Products
Model
VOS (μV)
IB (nA)
GBP (kHz)
en (nV/√Hz)
ISY (μA)
Input Common-Mode Range (V)
ADA4099-1
ADA4099-2
ADA4077-1
LT6015
25
10
10
1
8000
8000
3900
3200
1600
2.7
7
1500
1500
500
335
165
1.5
−VS to −VS + 70
−VS to −VS + 70
−VS to +VS
25
7
35
7
50
5
18
9.5
185
50
−VS to −VS + 76
−VS to +VS
LT6014
60
0.4
1
LT1494
375
500
−VS to −VS + 36
−VS to −VS + 44
LT1490A
8
180
55
analog.com
Rev. A | 27 of 34
Data Sheet
ADA4099-1/ADA4099-2
APPLICATIONS INFORMATION
TYPICAL APPLICATIONS
Figure 68. ±10 V to 0 V to +5 V Funnel Amplifier, High CMRR and ±80 V Input Protection via LT5400-7 Resistor Network (ADA4099-1 6-lead TSOT)
Figure 69. ±10 V to 0 V to +5 V Funnel Amplifier, Input and Output Voltages
Figure 70. ±10 V to 0 V to +5 V Funnel Amplifier, System Gain
analog.com
Rev. A | 28 of 34
Data Sheet
ADA4099-1/ADA4099-2
APPLICATIONS INFORMATION
Figure 71. ±10 V to 0 V to +5 V Funnel Amplifier, Large Signal Pulse Response
Figure 72. 1 V/A Low-Side Current Sense (ADA4099-1 6-lead TSOT)
Figure 73. 1 V/A High-Side Current Sense (ADA4099-1 6-lead TSOT)
Figure 74. Microprocessor Control of SHDN Pin in Split Supply Applications (ADA4099-1 6-lead TSOT)
analog.com
Rev. A | 29 of 34
Data Sheet
ADA4099-1/ADA4099-2
OUTLINE DIMENSIONS
Figure 75. 6-Lead Small Outline Transistor Package [TSOT]
(UJ-6)
Dimensions shown in millimeters
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Rev. A | 30 of 34
Data Sheet
ADA4099-1/ADA4099-2
OUTLINE DIMENSIONS
Figure 76. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
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Rev. A | 31 of 34
Data Sheet
ADA4099-1/ADA4099-2
OUTLINE DIMENSIONS
Figure 77. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
analog.com
Rev. A | 32 of 34
Data Sheet
ADA4099-1/ADA4099-2
OUTLINE DIMENSIONS
Figure 78. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(05-08-1699)
Dimensions shown in millimeters
analog.com
Rev. A | 33 of 34
Data Sheet
ADA4099-1/ADA4099-2
OUTLINE DIMENSIONS
Updated: January 07, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option Marking Code
ADA4099-1BUJZ-R5
ADA4099-1BUJZ-RL7
ADA4099-1HUJZ-RL7
ADA4099-2BCPZ
-40°C to +125°C
-40°C to +125°C
-55°C to +150°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-55°C to +150°C
-55°C to +150°C
-55°C to +150°C
-55°C to +150°C
6-Lead TSOT
UJ-6
Y7P
Y7P
Y7Q
A44
A44
A44
A44
6-Lead TSOT
UJ-6
6-Lead TSOT
UJ-6
10-Lead LFCSP (3mm x 3mm w/ EP)
10-Lead LFCSP (3mm x 3mm w/ EP)
8-Lead MSOP
05-08-1699
05-08-1699
RM-8
ADA4099-2BCPZ-RL7
ADA4099-2BRMZ
ADA4099-2BRMZ-RL7
ADA4099-2BRZ
8-Lead MSOP
RM-8
8-Lead SOIC_N
R-8
ADA4099-2BRZ-RL7
ADA4099-2HCPZ
8-Lead SOIC_N
R-8
10-Lead LFCSP (3mm x 3mm w/ EP)
10-Lead LFCSP (3mm x 3mm w/ EP)
8-Lead SOIC_N
05-08-1699
05-08-1699
R-8
A45
A45
ADA4099-2HCPZ-RL7
ADA4099-2HRZ
ADA4099-2HRZ-RL7
8-Lead SOIC_N
R-8
1
Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1
Description
EVAL-ADA4099-1HUJZ
EVAL-ADA4099-2BCPZ
Evaluation Board, Single TSOT
Evaluation Board, Dual LFCSP
1
Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. A | 34 of 34
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