ADA4500-2ARMZ_技术文档

10 MHz, 14.5 nV/√Hz, Rail-to-Rail I/O,

Zero Input Crossover Distortion Amplifier

Data Sheet

ADA4500-2

FEATURES

PIN CONFIGURATION

Power supply rejection ratio (PSRR): 98 dB minimum

Common-mode rejection ratio (CMRR): 95 dB minimum

Offset voltage: 120 µV maximum

Single-supply operation: 2.7 V to 5.5 V

Dual-supply operation: 1.35 V to 2.75 V

Wide bandwidth: 10 MHz

OUT A

–IN A

+IN A

V–

1

2

3

4

8

7

6

5

V+

OUT B

–IN B

+IN B

ADA4500-2

TOP VIEW

(Not to Scale)

Figure 1. 8-Lead MSOP Pin Configuration

Rail-to-rail input and output

Low noise

2 µV p-p from 0.1 Hz to 10 Hz

14.5 nV/√Hz at 1 kHz

For more information on the pin connections, see the Pin

Configurations and Function Descriptions section

100

ADA4500-2

V

= 5.0V

SY

80

60

Very low input bias current: 2 pA maximum

40

APPLICATIONS

20

Pressure and position sensors

Remote security

0

Medical monitors

Process controls

Hazard detectors

Photodiode applications

–20

–40

–60

–80

–100

0

1

2

3

4

5

V

(V)

CM

Figure 2. The ADA4500-2 Eliminates Crossover Distortion

Across its Full Supply Range

GENERAL DESCRIPTION

The ADA4500-2 is a dual 10 MHz, 14.5 nV/√Hz, low power

amplifier featuring rail-to-rail input and output swings while

operating from a 2.7 V to 5.5 V single power supply. Compatible

with industry-standard nominal voltages of +3.0 V, +3.3 V,

+5.0 V, and 2.5 V.

This combination of features makes the ADA4500-2 an ideal choice

for precision sensor applications because it minimizes errors due to

power supply variation and maintains high CMRR over the full

input voltage range. The ADA4500-2 is also an excellent amplifier

for driving analog-to-digital converters (ADCs) because the output

does not distort with the common-mode voltage, which enables

the ADC to use its full input voltage range, maximizing the

dynamic range of the conversion subsystem.

Employing a novel zero-crossover distortion circuit topology, this

amplifier offers high linearity over the full, rail-to-rail input

common-mode range, with excellent power supply rejection ratio

(PSRR) and common-mode rejection ratio (CMRR) performance

without the crossover distortion seen with the traditional

complementary rail-to-rail input stage. The resulting op amp

also has excellent precision, wide bandwidth, and very low

bias current.

Many applications such as sensors, handheld instrumentation,

precision signal conditioning, and patient monitors can benefit

from the features of the ADA4500-2.

The ADA4500-2 is specified for the extended industrial temperature

range (−40°C to +125°C) and available in the standard 8-lead

MSOP and 8-lead LFCSP packages.

Rev. A

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Tel: 781.329.4700

Technical Support

www.analog.com

IMPORTANT LINKS for the ADA4500-2*

Last content update 07/12/2013 06:24 pm

PARAMETRIC SELECTION TABLES

DESIGN COLLABORATION COMMUNITY

Find Similar Products By Operating Parameters

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versions offering similar AC and DC specifications with lower voltage

noise and supply current. in a precision RRIO Op Amp.

ADA4084-2: offers similar speed and precision with lower noise and

supply current in a 30V RRIO Op Amp.

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ADA4505-1, ADA4505-2, ADA4505-4: available in single, dual and

quad channel counts, it offers lower supply current with rail-to-rail

linearity of a Zero Crossover Op Amp.

AD8505, AD8506, AD8508: available in single, dual and quad channel

versions offering lower supply current with the rail-to-rail linearity of a

Zero Crossover Op Amp.

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Embedded Processing and DSP

DOCUMENTATION

Sensor Signal Conditioning - Amplifiers for Signal Conditioning

Telephone our Customer Interaction Centers toll free:

MT-095: EMI, RFI, and Shielding Concepts

Americas:

Europe:

China:

1-800-262-5643

00800-266-822-82

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MT-035: Op Amp Inputs, Outputs, Single-Supply, and Rail-to-Rail

Issues

India:

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1800-419-0108

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MS-2066: Low Noise Signal Conditioning for Sensor-Based Circuits

Quality and Reliability

Lead(Pb)-Free Data

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This content may be frequently modified.

ADA4500-2

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 19

Rail-to-Rail Output .................................................................... 19

Rail-to-Rail Input (RRI) ............................................................ 19

Zero Cross-Over Distortion ..................................................... 19

Overload Recovery..................................................................... 20

Power-On Current Profile......................................................... 21

Applications Information .............................................................. 22

Resistance and Capacitance Sensor Circuit............................ 22

Adaptive Single-Ended-to-Differential Signal Converter..... 22

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

Pin Configuration............................................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

V_SY= 2.7 V Electrical Characteristics ........................................ 3

V_SY= 5.0 V Electrical Characteristics ........................................ 5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

REVISION HISTORY

10/12–Rev. 0 to Rev. A

Changes to Ordering Guide .......................................................... 24

10/12–Revision 0: Initial Version

Rev. A | Page 2 of 24

Data Sheet

ADA4500-2

SPECIFICATIONS

V_SY= 2.7 V ELECTRICAL CHARACTERISTICS

V_SY= 2.7 V, V _CM= V_SY/2, T_A= 25°C, unless otherwise specified.

Table 1.

Parameter

Symbol

Test Conditions/Conditions

Min

Typ

Max Unit

INPUT CHARACTERISTICS

Offset Voltage

V_OS

120

700

5.5

1

170

1

µV

µV/°C

pA

V

dB

−40°C < T_A< +125°C

Offset Voltage Drift

Input Bias Current

TCV_OS

I_B

0.8

0.3

−40°C < T_A< +125°C

Input Offset Current

I_OS

0.3

−40°C < T_A< +125°C

V_CM= V− to V+

−40°C < T_A< +125°C

V_CM= [(V−) − 0.2 V] to [(V+) + 0.2 V]

−40°C < T_A< +125°C

R_L= 2 kΩ, [(V−) + 0.05 V] < V_OUT< [(V+) − 0.05 V]

−40°C < T_A< +125°C

R_L= 10 kΩ, [(V−) + 0.05 V] < V_OUT< [(V+) − 0.05 V]

−40°C < T_A< +125°C

20

V+

Input Voltage Range

Common-Mode Rejection Ratio

IVR

CMRR

V−

95

90

80

100

105

110

120

Large Signal Voltage Gain

A_VO

Input Capacitance

Common Mode

Differential

C_INCM

C_INDM

R_IN

5

1.7

400

pF

GΩ

Input Resistance

Common mode and differential mode

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

R_L= 10 kΩ to V−

−40°C < T_A< +125°C

R_L= 2 kΩ to V−

−40°C < T_A< +125°C

R_L= 10 kΩ to V+

−40°C < T_A< +125°C

R_L= 2 kΩ to V+

−40°C < T_A< +125°C

Sourcing, V_OUTshorted to V−

Sinking, V_OUTshorted to V+

f = 10 MHz, A_V= 1

2.685 2.695

2.68

V

mV

mA

Ω

2.65

2.68

Output Voltage Low

Short Circuit Limit

V_OL

3

5

10

20

25

13

I_SC

26

−48

70

Closed-Loop Impedance

POWER SUPPLY

Power Supply Rejection Ratio

Z_OUT

PSRR

I_SY

V_SY= 2.7 V to 5.5 V

−40°C to +125°C

I_O= 0 mA

98

94

119

1.5

dB

mA

Supply Current per Amplifier

1.65

1.7

−40°C < T_A< +125°C

DYNAMIC PERFORMANCE

Slew Rate

SR

R_L= 10 kΩ, C_L= 30 pF, A_V= +1, V_IN= V_SY

R_L= 10 kΩ, C_L= 30 pF, A_V= −1, V_IN= V_SY

V_IN= 5 mV p-p, R_L= 10 kΩ, A_V= +100

V_IN= 5 mV p-p, R_L= 10 kΩ, A_V= +1

V_IN= 5 mV p-p, R_L= 10 kΩ, A_V= −1

V_IN= 5 mV p-p, R_L= 10 kΩ, C_L= 20 pF, A_V= +1

V_IN= 2 V p-p, R_L= 10 kΩ, C_L= 10 pF, A_V= −1

5.5

8.7

10.1

10.3

18.4

52

V/µs

MHz

Degrees

µs

Gain Bandwidth Product

Unity Gain Crossover

−3 dB Bandwidth

Phase Margin

Settling Time to 0.1%

GBP

UGC

−3 dB

ΦM

t_s

1

Rev. A | Page 3 of 24

ADA4500-2

Data Sheet

Parameter

Symbol

Test Conditions/Conditions

Min

Typ

Max Unit

NOISE PERFORMANCE

Total Harmonic Distortion + Noise THD+N

Bandwidth = 80 kHz

Bandwidth = 500 kHz

G = 1, f = 10 Hz to 20 kHz, V_IN= 0.7 V rms at 1 kHz

0.0006

0.001

3

14.5

<0.5

%

µV p-p

nV/√Hz

fA/√Hz

Peak-to-Peak Noise

Voltage Noise Density

Current Noise Density

e_{n p-p}

e_n

i_n

f = 0.1 Hz to 10 Hz

f = 1 kHz

Rev. A | Page 4 of 24

Data Sheet

ADA4500-2

V_SY= 5.0 V ELECTRICAL CHARACTERISTICS

V_SY= 5.0 V, V _CM= V_SY/2, T_A= 25°C, unless otherwise specified.

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max Unit

INPUT CHARACTERISTICS

Offset Voltage

V_OS

120

700

5.5

2

190

3

µV

µV/°C

pA

V

dB

−40°C < T_A< +125°C

Offset Voltage Drift

Input Bias Current

TCV_OS

I_B

0.9

0.7

−40°C < T_A< +125°C

Input Offset Current

I_OS

0.3

−40°C < T_A< +125°C

V_CM= V− to V+

−40°C < T_A< +125°C

V_CM= [(V−) − 0.2 V] to [(V+) + 0.2 V]

−40°C < T_A< +125°C

R_L= 2 kΩ, [(V−) + 0.05 V] < V_OUT< [(V+) − 0.05 V]

−40°C < T_A< +125°C

R_L= 10 kΩ, [(V−) + 0.05 V] < V_OUT< [(V+) − 0.05 V]

−40°C < T_A< +125°C

20

V+

Input Voltage Range

Common-Mode Rejection Ratio

IVR

CMRR

V−

95

84

105

80

110

115

110

120

Large Signal Voltage Gain

A_VO

Input Capacitance

Common Mode

Differential

C_INCM

C_INDM

R_IN

5

1.7

400

pF

GΩ

Input Resistance

Common mode and differential mode

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

R_L= 10 kΩ to V−

−40°C < T_A< +125°C

R_L= 2 kΩ to V−

−40°C < T_A< +125°C

R_L= 10 kΩ to V+

−40°C < T_A< +125°C

R_L= 2 kΩ to V+

−40°C < T_A< +125°C

Sourcing, V_OUTshorted to V−

Sinking, V_OUTshorted to V+

f = 10 MHz, A_V= +1

4.975 4.99

4.97

V

mV

mA

Ω

4.95

4.97

Output Voltage Low

Short Circuit Limit

V_OL

7

15

20

40

50

24

I_SC

75

−75

60

Closed-Loop Impedance

POWER SUPPLY

Power Supply Rejection Ratio

Z_OUT

PSRR

I_SY

V_SY= 2.7 V to 5.5 V

−40°C to +125°C

I_O= 0 mA

98

94

119

dB

mA

Supply Current per Amplifier

1.55

1.75

1.8

−40°C < T_A< +125°C

DYNAMIC PERFORMANCE

Slew Rate

SR

R_L= 10 kΩ, C_L= 30 pF, A_V= +1, V_IN= V_SY

R_L= 10 kΩ, C_L= 30 pF, A_V= −1, V_IN= V_SY

V_IN= 5 mV p-p, R_L= 10 kΩ, A_V= +100

V_IN= 5 mV p-p, R_L= 10 kΩ, A_V= +1

V_IN= 5 mV p-p, R_L= 10 kΩ, A_V= −1

V_IN= 5 mV p-p, R_L= 10 kΩ, C_L= 20 pF, A_V= +1

V_IN= 4 V p-p, R_L= 10 kΩ, C_L= 10 pF, A_V= −1

5.5

8.7

10

10.5

19.2

57

V/µs

MHz

Degrees

µs

Gain Bandwidth Product

Unity Gain Crossover

−3 dB Bandwidth

Phase Margin

Settling Time to 0.1%

GBP

UGC

−3 dB

ΦM

t_s

1

Rev. A | Page 5 of 24

ADA4500-2

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max Unit

NOISE PERFORMANCE

Total Harmonic Distortion + Noise THD+N

Bandwidth = 80 kHz

Bandwidth = 500 kHz

G = 1, f = 20 Hz to 20 kHz, V_IN= 1.4 V rms at 1 kHz

0.0004

0.0008

2

14.5

<0.5

%

µV p-p

nV/√Hz

fA/√Hz

Peak-to-Peak Noise

Voltage Noise Density

Current Noise Density

e_{n p-p}

e_n

i_n

f = 0.1 Hz to 10 Hz

f = 1 kHz

Rev. A | Page 6 of 24

Data Sheet

ADA4500-2

ABSOLUTE MAXIMUM RATINGS

Table 3.

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Parameter

Rating

Supply Voltage

6 V

Input Voltage

(V−) − 0.2 V to (V+) + 0.2 V

Indefinite

−65°C to +150°C

−40°C to +125°C

−65°C to +150°C

300°C

Table 4. Thermal Resistance

Package Type

8-Lead MSOP (RM-8)¹

8-Lead LFCSP (CP-8-12)^{2, 3}

Differential Input Voltage¹

Output Short-Circuit Duration

Storage Temperature Range

Operating Temperature Range

Junction Temperature Range

Lead Temperature (Soldering, 60 sec)

θ_JA

142

85

θ_JC

45

2

Unit

°C/W

¹Thermal numbers were simulated on a 4-layer JEDEC printed circuit board (PCB).

²Thermals numbers were simulated on a 4 layer JEDEC PCB with the exposed

pad soldered to the PCB.

³θ_JCwas simulated at the exposed pad on the bottom of the package.

¹Differential input voltage is limited to 5.6 V or the supply voltage + 0.6 V,

whichever is less.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. A | Page 7 of 24

ADA4500-2

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

OUT A 1

–IN A 2

+IN A 3

V– 4

8 V+

7 OUT B

6 –IN B

5 +IN B

ADA4500-2

OUT A

–IN A

+IN A

V–

1

2

3

4

8

7

6

5

V+

TOP VIEW

(Not to Scale)

OUT B

–IN B

+IN B

ADA4500-2

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO V–

OR LEAVE IT UNCONNECTED.

Figure 4. 8-Lead LFCSP Pin Configuration

Figure 3. 8-Lead MSOP Pin Configuration

Table 5. 8-Lead MSOP and 8-Lead LFCSP Pin Function Descriptions

Pin No.

Mnemonic

OUT A

−IN A

+IN A

V−

+IN B

−IN B

OUT B

V+

Description

1

2

3

4

5

6

7

8

Output, Channel A.

Inverting Input, Channel A.

Noninverting Input, Channel A.

Negative Supply Voltage.

Noninverting Input, Channel B.

Inverting Input, Channel B.

Output, Channel B.

Positive Supply Voltage.

EPAD

For the LFCSP package only, connect the exposed pad to V− or leave it unconnected.

Rev. A | Page 8 of 24

Data Sheet

ADA4500-2

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, unless otherwise noted.

100

90

80

70

60

50

40

30

20

10

0

ADA4500-2

V

= 2.7V

V

= 5.0V

= V /2

SY

90

80

70

60

50

40

30

20

10

0

= V /2

CM

SY

CM

–120 –100 –80 –60 –40 –20

0

20 40 60 80 100 120

(µV)

–120 –100 –80 –60 –40 –20

0

20 40 60 80 100 120

(µV)

V

OS

Figure 5. Input Offset Voltage Distribution, V_SY= 2.7 V

Figure 8. Input Offset Voltage Distribution, V_SY= 5.0 V

35

30

25

20

15

10

5

35

30

25

20

15

10

5

ADA4500-2

V

= 2.7V

V

= 5.0V

SY

= V /2

CM

SY

CM

SY

–40°C ≤ T ≤ +125°C

A

0

1.25

2.50

3.75

5.00

6.25

7.50

8.75

0

1.25

2.50

3.75

5.00

6.25

7.50

8.75

TCV (µV/°C)

OS

Figure 6. Input Offset Voltage Drift Distribution, V_SY= 2.7 V

Figure 9. Input Offset Voltage Drift Distribution, V_SY= 5.0 V

100

ADA4500-2

= 2.7V

ADA4500-2

= 5.0V

V

SY

80

60

80

60

40

20

0

–20

–40

–60

–80

–100

–20

–40

–60

–80

–100

–0.2

0.8

1.8

2.8

(V)

3.8

4.8

–0.2

0.3

0.8

1.3

1.8

2.3

2.8

V

(V)

CM

Figure 10. Input Offset Voltage (V_OS) vs. Common-Mode Voltage (V_CM), V_SY= 5.0 V

Figure 7. Input Offset Voltage (V_OS) vs. Common-Mode Voltage (V_CM), V_SY= 2.7 V

Rev. A | Page 9 of 24

ADA4500-2

Data Sheet

T_A= 25°C, unless otherwise noted.

100

80

ADA4500-2

V

= 2.7V

V

= 5.0V

SY

= V /2

80

60

CM

SY

CM

SY

I

+

B

60

40

I

–

B

20

I

+

B

0

I

–

B

–20

–40

–20

–40

–50

–25

0

25

50

75

100

125

150

–50

–25

0

25

50

75

100

125

150

TEMPERATURE (°C)

Figure 11. Input Bias Current (I_B) vs. Temperature, V_SY= 2.7 V

Figure 14. Input Bias Current (I_B) vs. Temperature, V_SY= 5.0 V

100

ADA4500-2

= 2.7V

ADA4500-2

V = 5.0V

SY

V

SY

80

60

80

60

40

20

0

–20

–40

–20

–40

0

0.5

1.0

1.5

(V)

2.0

2.5

3.0

0

1

2

3

4

5

V

(V)

CM

Figure 12. Input Bias Current (I_B) vs. Common-Mode Voltage (V_CM), V_SY= 2.7 V

Figure 15. Input Bias Current (I_B) vs. Common-Mode Voltage (V_CM), V_SY= 5.0 V

10k

ADA4500-2

V

= 2.7V

V

= 5.0V

SY

SOURCING OUTPUT CURRENT

1k

100

10

1k

100

10

+125°C

+25°C

–40°C

1

–40°C

0.1

0.001

0.01

0.1

1

10

100

0.001

0.01

0.1

1

10

100

LOAD CURRENT (mA)

Figure 13. Output Voltage (V_OH) to Supply Rail vs. Load Current, V_SY= 2.7 V

Figure 16. Output Voltage (V_OH) to Supply Rail vs. Load Current, V_SY= 5.0 V

Rev. A | Page 10 of 24

Data Sheet

ADA4500-2

T_A= 25°C, unless otherwise noted.

10k

1k

ADA4500-2

= 5.0V

SINKING OUTPUT CURRENT

V

= 2.7V

V

SY

SINKING OUTPUT CURRENT

1k

100

10

+25°C

100

10

+125°C

–40°C

+25°C

–40°C

1

0.1

0.001

0.01

0.1

1

10

100

0.001

0.01

0.1

1

10

100

LOAD CURRENT (mA)

Figure 17. Output Voltage (V_OL) to Supply Rail vs. Temperature, V_SY= 2.7 V

Figure 20. Output Voltage (V_OL) to Supply Rail vs. Load Current, V_SY= 5.0 V

50

ADA4500-2

V

= 2.7V

V

= 5.0V

SY

40

30

20

10

0

40

30

20

10

0

R

= 2kΩ

L

R

= 2kΩ

L

R

= 10kΩ

L

R

= 10kΩ

L

–50

–25

0

25

50

75

100

125

150

–50

–25

0

25

50

75

100

125

150

TEMPERATURE (°C)

Figure 18. Output Voltage (V_OH) to Supply Rail vs. Temperature, V_SY= 2.7 V

Figure 21. Output Voltage (V_OH) to Supply Rail vs. Temperature, V_SY= 5.0 V

50

20

ADA4500-2

V

= 5.0V

SY

V

= 2.7V

SY

40

30

20

10

0

15

10

5

R

= 2kΩ

L

R

= 2kΩ

L

R

= 10kΩ

L

R

= 10kΩ

L

0

–50

–25

0

25

50

75

100

125

150

–25

0

25

50

75

100

125

150

TEMPERATURE (°C)

Figure 22. Output Voltage (V_OL) to Supply Rail vs. Temperature, V_SY= 5.0 V

Figure 19. Output Voltage (V_OL) to Supply Rail vs. Temperature, V_SY= 2.7 V

Rev. A | Page 11 of 24

ADA4500-2

Data Sheet

T_A= 25°C, unless otherwise noted.

1.75

2.0

1.8

1.6

1.4

1.2

1.0

ADA4500-2

1.50

1.25

+85°C

V

= ±2.5V

SY

1.00

+125°C

+25°C

0.75

0.50

0.25

0

V

= ±1.35V

SY

–40°C

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

SUPPLY VOLTAGE (V)

–50

–25

0

25

50

75

100

125

150

TEMPERATURE (°C)

Figure 23. Supply Current per Amp vs. Supply Voltage

Figure 26. Supply Current per Amp vs. Temperature

150

100

50

150

100

50

ADA4500-2

PHASE

100

PHASE

100

50

GAIN

0

–50

R

= 10kΩ

= 20pF

= 2.7V

L

R

= 10kΩ

= 20pF

= 5.0V

L

C

L

C

L

V

SY

CM

V

SY

CM

= V /2

SY

= V /2

SY

–100

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 24. Open-Loop Gain and Phase vs. Frequency, V_SY= 2.7 V

Figure 27. Open-Loop Gain and Phase vs. Frequency, V_SY= 5.0 V

60

ADA4500-2

V

= 2.7V

V

= 5.0V

SY

50

40

50

40

= V /2

CM

SY

CM

SY

A

= +100

= +10

= +1

A

= +100

= +10

= +1

V

30

A

V

20

10

A

V

0

–10

–20

–10

–20

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 25. Closed Loop Gain vs. Frequency, V_SY= 2.7 V

Figure 28. Closed-Loop Gain vs. Frequency, V_SY= 5.0 V

Rev. A | Page 12 of 24

Data Sheet

ADA4500-2

T_A= 25°C, unless otherwise noted.

160

140

120

100

80

140

120

100

80

60

40

20

ADA4500-2

20

0

V

= 5.0V

V

= 2.7V

SY

= V /2

CM

SY

CM

SY

0

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 29. CMRR vs. Frequency, V_SY= 2.7 V

Figure 32. CMRR vs. Frequency, V_SY= 5.0 V

140

120

100

80

140

120

100

80

PSRR+

PSRR–

PSRR+

PSRR–

ADA4500-2

V

= 5.0V

V

= 2.7V

SY

= V /2

CM

SY

CM

SY

60

40

20

0

–20

100

–20

100

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 30. PSRR vs. Frequency, V_SY= 2.7 V

Figure 33. PSRR vs. Frequency, V_SY= 5.0 V

1k

100

10

1k

100

10

ADA4500-2

V

= 2.7V

V

= 5.0V

= V /2

SY

= V /2

CM

SY

CM

A

= +100

A

= +100

V

1

0.1

A = +1

V

A

= +1

A

= +10

V

A

= +10

V

0.01

0.001

0.01

0.001

100

1k

10k

100k

1M

10M

100M

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 31. Closed Loop Output Impedance (Z_OUT) vs. Frequency, V_SY= 2.7 V

Figure 34. Closed Loop Output Impedance (Z_OUT) vs. Frequency, V_SY= 5.0 V

Rev. A | Page 13 of 24

ADA4500-2

Data Sheet

T_A= 25°C, unless otherwise noted.

ADA4500-2

V

A

R

C

= 5.0V

V

A

R

C

= 2.7V

SY

= V /2

CM

SY

CM

SY

= 4V p-p

= +1

= 10kΩ

= 100pF

= 2V p-p

= +1

= 10kΩ

= 100pF

IN

V

L

V

L

TIME (400ns/DIV)

TIME (200ns/DIV)

Figure 35. Large Signal Transient Response, V_SY= 2.7 V

Figure 38. Large Signal Transient Response, V_SY= 5.0 V

ADA4500-2

V

A

R

C

= 5.0V

V

A

R

C

= 2.7V

SY

= V /2

CM

SY

CM

SY

= 100mV p-p

= +1

= 10kΩ

= 100pF

= 100mV p-p

= +1

= 10kΩ

= 100pF

IN

V

L

V

L

TIME (200ns/DIV)

Figure 36. Small Signal Transient Response, V_SY= 2.7 V

Figure 39. Small Signal Transient Response, V_SY= 5.0 V

80

70

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

ADA4500-2

V

A

R

= 2.7V

V

= 5.0V

= V /2

SY

= 100mV p-p

SY

= V /2

CM

SY

CM

= 100mV p-p

= +1

IN

A

R

= +1

= 10kΩ

V

L

V

L

= 10kΩ

OS–

OS+

OS–

1

10

LOAD CAPACITANCE (pF)

100

1

10

100

LOAD CAPACITANCE (pF)

Figure 37. Small Signal Overshoot vs. Load Capacitance, V_SY= 2.7 V

Figure 40. Small Signal Overshoot vs. Load Capacitance, V_SY= 5.0 V

Rev. A | Page 14 of 24

Data Sheet

ADA4500-2

T_A= 25°C, unless otherwise noted.

0.05

0.1

0

INPUT

0

–0.05

–0.10

–0.1

–0.2

ADA4500-2

V

A

R

C

= ±1.35V

= 50mV p-p

= –100

V

A

R

C

= ±2.5V

= 100mV p-p

= –100

SY

IN

SY

IN

1.5

1.0

0.5

0

3

V

L

V

L

= 10kΩ

= 100pF

2

1

0

OUTPUT

–0.5

–1

TIME (2µs/DIV)

Figure 41. Positive Overload Recovery, V_SY

=

1.35 V

Figure 43. Positive Overload Recovery, V_SY= 2.5 V

0.10

0.05

0

0.2

0.1

0

INPUT

–0.1

–0.05

1

0.5

OUTPUT

0

ADA4500-2

–1

–2

–3

–0.5

–1.0

–1.5

V

A

R

C

= ±2.5V

= 100mV p-p

= –100

V

A

R

C

= ±1.35V

= 50mV p-p

= –100

SY

IN

SY

IN

V

L

V

L

= 10kΩ

= 100pF

TIME (2µs/DIV)

Figure 44. Negative Overload Recovery, V_SY

= 2.5 V

Figure 42. Negative Overload Recovery, V_SY

= 1.35 V

Rev. A | Page 15 of 24

ADA4500-2

Data Sheet

T_A= 25°C, unless otherwise noted.

INPUT

ADA4500-2

V

= 2.7V

V

= 5.0V

= V /2

SY

= V /2

V

CM

SY

CM

R

C

= 10kΩ

= 10pF

R

= 10kΩ

= 10pF

L

C

L

DUT A = –1

V

ERROR BAND

POST GAIN = 20

ERROR BAND

POST GAIN = 20

+20mV

0

+40mV

0

OUTPUT

–20mV

–40mV

TIME (400ns/DIV)

Figure 45. Positive Settling Time to 0.1%, V_SY= 2.7 V

Figure 47. Positive Settling Time to 0.1%, V_SY= 5.0 V

ADA4500-2

V

= 2.7V

V

= 5.0V

SY

= V /2

CM

SY

CM

SY

R

C

= 10kΩ

= 10pF

R

C

= 10kΩ

= 10pF

L

DUT A = –1

V

INPUT

ERROR BAND

POST GAIN = 20

ERROR BAND

POST GAIN = 20

+20mV

0

+40mV

0

OUTPUT

–20mV

–40mV

TIME (400ns/DIV)

Figure 46. Negative Settling Time to 0.1%, V_SY= 2.7 V

Figure 48. Negative Settling Time to 0.1%, V_SY= 5.0 V

Rev. A | Page 16 of 24

Data Sheet

ADA4500-2

T_A= 25°C, unless otherwise noted.

1k

100

10

ADA4500-2

V

= 2.7V

V

= 5.0V

SY

= V /2

V

= V /2

SY

CM

SY

CM

100

10

1

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 49. Voltage Noise Density vs. Frequency, V_SY= 2.7 V

(10 Hz to 10 MHz)

Figure 52. Voltage Noise Density vs. Frequency, V_SY= 5.0 V

(10 Hz to 10 MHz)

1k

ADA4500-2

V

= 2.7V

V

= 5.0V

= V /2

SY

= V /2

V

CM

SY

CM

100

10

1

100

10

1

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 50. Voltage Noise Density vs. Frequency, V_SY= 2.7 V

(10 Hz to 100 MHz)

Figure 53. Voltage Noise Density vs. Frequency, V_SY= 5.0 V

(10 Hz to 100 MHz)

ADA4500-2

V

= 2.7V, A = +100

SY

V

= V /2

CM

SY

ADA4500-2

V

= 5.0V

= +100

SY

V

A

V

= V /2

CM

SY

TIME (1s/DIV)

Figure 51. 0.1 to 10 Hz Noise, V_SY= 2.7 V

Figure 54. 0.1 to 10 Hz Noise, V_SY= 5.0 V

Rev. A | Page 17 of 24

ADA4500-2

Data Sheet

T_A= 25°C, unless otherwise noted.

100

10

ADA4500-2

V

= 2.7V

V

= 5.0V

= V /2

SY

= V /2

CM

SY

CM

10

1

A

= +1

A = +1

V

80kHz LOW-PASS FILTER

R = 10kΩ

L

R

= 10kΩ

L

1

0.1

0.01

0.001

0.0001

0.01

0.001

0.0001

0.001

0.01

0.1

1

10

100

0.001

0.01

0.1

1

10

100

V

(V rms)

V

(V rms)

IN

Figure 55. THD + Noise vs. Amplitude, V_SY= 2.7 V

Figure 57. THD + Noise vs. Amplitude, V_SY= 5.0 V

1

ADA4500-2

V

A

= 2.7V

= +1

V

= 5.0V

A = +1

V

SY

V

80kHz LOW-PASS FILTER

R

= 10kΩ

= 0.7V rms

R

= 10kΩ

= 1.4V rms

L

0.1

0.01

0.1

0.01

V

IN

0.001

0.0001

0.001

0.0001

10

100

1k

10k

100k

10

100

1k

10k

100k

FREQUENCY (Hz)

Figure 56. THD + Noise vs. Frequency, V_SY= 2.7 V

Figure 58. THD + Noise vs. Frequency, V_SY= 5.0 V

Rev. A | Page 18 of 24

Data Sheet

ADA4500-2

THEORY OF OPERATION

VDD

M10

RAIL-TO-RAIL OUTPUT

M9

BIAS5

BIAS4

When processing a signal through an op amp to a load, it is often

desirable to have the output of the op amp swing as close to the

voltage supply rails as possible. For example, when an op amp is

driving an ADC and both the op amp and ADC are using the

same supply rail voltages, the op amp must drive as close to the

V+ and V− rails as possible so that all codes in the ADC are

usable. A non-rail-to-rail output can require as much as 1.5 V

or more between the output and the rails, thus limiting the

input dynamic range to the ADC, resulting in less precision

(number of codes) in the converted signal.

M3 M4

M12

M11

BIAS2

BIAS1

–A

M8

OUT

V

+

V –

IN

VSS

VDD

IN

M7

M5

BIAS3

M1 M2

The ADA4500-2 can drive its output to within a few millivolts

of the supply rails (see the output voltage high and output voltage

low specifications in Table 1 and Table 2). The rail-to-rail output

maximizes the dynamic range of the output, increasing the range

and precision, and often saving the cost, board space, and added

error of the additional gain stages.

M6

VSS

Figure 59. Typical PMOS-NMOS Rail-to-Rail Input Structure

300

250

200

150

100

50

V

= 5V

= 25°C

SY

T

A

RAIL-TO-RAIL INPUT (RRI)

Using a CMOS nonrail-to-rail input stage (that is, a single

differential pair) limits the input voltage to approximately one gate-

source voltage (V_GS) away from one of the supply lines. Because

0

–50

–100

–150

–200

–250

–300

V

_GSfor normal operation is commonly more than 1 V, a single

differential pair, input stage op amp greatly restricts the allowable

input voltage. This can be quite limiting with low supply voltages

supplies. To solve this problem, RRI stages are designed to allow

the input signal to range to the supply voltages (see the input

voltage range specifications in Table 1 and Table 2). In the case

of the ADA4500-2, the inputs continue to operate 200 mV beyond

the supply rails (see Figure 7 and Figure 10).

0

0.5

1.0

1.5

2.0

2.5

(V)

3.0

3.5

4.0

4.5

5.0

V

CM

Figure 60. Typical Input Offset Voltage (V_OS) vs. Common-Mode Voltage (V_CM

Response in a Dual Differential Pair Input Stage Op Amp (Powered by a 5 V

Supply; Results of Approximately 100 Units per Graph Are Displayed)

)

ZERO CROSS-OVER DISTORTION

A typical rail-to-rail input stage uses two differential pairs (see

Figure 59). One differential pair amplifies the input signal when

the common-mode voltage is on the high end, and the other

pair amplifies the input signal when the common-mode voltage

is on the low end. This classic dual-differential pair topology

does have a potential drawback. If the signal level moves through

the range where one input stage turns off and the other input

stage turns on, noticeable distortion occurs. Figure 60 shows the

distortion in a typical plot of V_OS(voltage difference between the

inverting and the noninverting input) vs. V_CM(input voltage).

This distortion in the offset error forces the designer to live with

the bump in the common-mode error or devise impractical ways

to avoid the crossover distortion areas, thereby narrowing the

common-mode dynamic range of the op amp.

Rev. A | Page 19 of 24

ADA4500-2

Data Sheet

The ADA4500-2 solves the crossover distortion problem by using

an on-chip charge pump in its input structure to power the input

differential pair (see Figure 61). The charge pump creates a

supply voltage higher than the voltage of the supply, allowing

the input stage to handle a wide range of input signal voltages

without using a second differential pair. With this solution, the

input voltage can vary from one supply voltage to the other with

no distortion, thereby restoring the full common-mode dynamic

range of the op amp.

Figure 62 shows the elimination of the crossover distortion in

the ADA4500-2. This solution improves the CMRR performance

tremendously. For example, if the input varies from rail to rail

on a 5 V supply rail, using a part with a CMRR of 70 dB minimum,

an input-referred error of 1581 µV is introduced. The ADA4500-2,

with its high CMRR of 90 dB minimum (over its full operating

temperature) reduces distortion to a maximum error of 158 µV

with a 5 V supply. The ADA4500-2 eliminates crossover distortion

without unnecessary circuitry complexity and increased cost.

VCP

300

ADA4500-2

V

= 5.0V

BIAS6

SY

240

180

120

60

CHARGE

PUMP

VDD

BIAS5

0

V

+

V –

IN

BIAS4

M1 M2

–60

–120

–180

–240

–300

–A

OUT

V

BIAS3

0

1

2

3

4

5

V

(V)

CM

Figure 62. Charge Pump Design Eliminates Crossover Distortion

VSS

OVERLOAD RECOVERY

Figure 61. ADA4500-2 Input Structure

When the output is driven to one of the supply rails, the

ADA4500-2 is in an overload condition. The ADA4500-2 recovers

quickly from the overload condition. Typical op amp recovery

times can be in the tens of microseconds. The ADA4500-2 typically

recovers from an overload condition in 1 µs from the time the

overload condition is removed until the output is active again.

This is important in, for example, a feedback control system. The

fast overload recovery of the ADA4500-2 greatly reduces loop

delay and increases the response time of the control loop (see

Figure 41 to Figure 44).

Some charge pumps are designed to run in an open-loop

configuration. Disadvantages of this design include: a large ripple

voltage on the output, no output regulation, slow start-up, and a

large power-supply current ripple. The charge pump in this op

amp uses a feedback network that includes a controllable clock

driver and a differential amplifier. This topology results in a low

ripple voltage; a regulated output that is robust to line, load, and

process variations; a fast power-on startup; and lower ripple on

the power supply current.¹The charge pump ripple does not

show up on an oscilloscope; however, it can be seen at a high

frequency on a spectrum analyzer. The charge pump clock speed

adjusts between 3.5 MHz (when the supply voltage is 2.7 V) to

5 MHz (at V_SY= 5 V). The noise and distortion are limited only by

the input signal and the thermal or flicker noise.

¹Oto, D.H.; Dham, V.K.; Gudger, K.H.; Reitsma, M.J.; Gongwer, G.S.; Hu, Y.W.; Olund, J.F.; Jones, H.S.; Nieh, S.T.K.; "High-Voltage Regulation and Process

Considerations for High-Density 5 V-Only E²PROM's," IEEE Journal of Solid-State Circuits, Vol. SC-18, No.5, pp.532-538, October 1983.

Rev. A | Page 20 of 24

Data Sheet

ADA4500-2

5

4

3

2

1

0

60

55

50

45

40

35

30

25

20

15

10

5

POWER-ON CURRENT PROFILE

The ADA4500-2 powers up with a smooth current profile, with

no supply current overshoot (see Figure 63). When powering up

a system, spikes in the power-up current are undesirable (see

Figure 64). The overshoot requires a designer to source a large

enough power supply (such as a voltage regulator) to supply the

peak current, even though a heavier supply is not necessary once

the system is powered up. If multiple amplifiers are pulling a

spike in current, the system can go into a current limit state and

not power up. This is all avoided with the smooth power up of

the ADA4500-2.

5

4

3

2

1

0

60

55

50

45

40

35

30

25

20

15

10

5

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

TIME (µs)

Figure 64. I_SYand V_SYvs. Time with a Power-Up Spike

For systems that are frequently switching off and on, the power-

up overshoot results in excess power use. As the amplifier switches

off and on, the power consumed by the large spike is repeated

on each power-up, increasing the total power consumption by

magnitudes. As an example, if a battery-powered sensor system

periodically powers up the sensor and signal path, takes a reading,

and shuts down until the next reading, the ADA4500-2 enables

much longer battery life because there is no excess charge being

consumed at each power-up.

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

TIME (µs)

Figure 63. I_SYand V_SYvs. Time for ADA4500-2 with No Spike

Rev. A | Page 21 of 24

ADA4500-2

Data Sheet

APPLICATIONS INFORMATION

Three key challenges are encountered often when designing a

single-ended-to-differential signal converter circuit with a

single supply:

RESISTANCE AND CAPACITANCE SENSOR CIRCUIT

The application shown in Figure 65 generates a square-wave

output in which the period is proportional to the value of R_X

and C_Xby Equation 1. By fixing the C_Xand measuring the

period of the output signal, R_Xcan be determined. Fixing R_X

allows for the measurement of C_X.

•

When the supply is limited to a single voltage, the input

signal level to the circuit is generally limited to operate

from ground to the supply voltage (V_SY). This limitation

on the input dynamic range can require attenuation and/or

level-shifting of the source signal before it even gets to the

single-ended-to-differential signal converter. This results in

reduced signal-to-noise ratio (SNR) and additional error.

The dc part of the input signal, on which the ac signal rides, is

generally not known during system operation. For example, if

multiple input signals from varying sources are multiplexed

into the single-ended-to-differential signal converter circuit,

each one could have a different dc level. Accommodating

multiple dc input levels means that the system design must

compromise the maximum allowed peak voltage of the ac

part of the input so that it does not clip against the rails.

The system processor does not know what the dc level is of the

original signal so it cannot make adjustments accordingly.

Period = 4.80 × R_X× C_X

(1)

U1A takes advantage of the high input impedance and large rail-

to-rail input dynamic range of the ADA4500-2 to measure a

wide range of resistances (R_X).

•

U1B is used as a comparator; with the noninverting input

swinging between (1/12) × V_POSand (11/12) × V_POS, and the

output swinging from rail to rail. Because the accuracy of the

circuit depends on the propagation time through the amplifers,

the fast recovery of U1B from the output overload conditions

makes it ideal for this application.

V

POS

V

POS

•

Rx

Cx

U1A

ADA4500-2

V

POS

OUTPUT

U1B

ADA4500-2

R3

The Solution

100kΩ

These challenges are solved with the adaptive single-ended to

differential converter shown in Figure 66. This circuit operates

off a single supply from 2.7 V to 5.5 V, it automatically adjusts the

dc common mode of the output to a desired level, and it provides

the ability to measure the dc component of the input signal. This

circuit uses two voltage sources: a positive supply rail (V_SY) and

a reference voltage (V_REF). U1A buffers the input signal, while

U1B integrates that signal and feeds the integrated (dc) voltage

back to U1A to center the output signal on V_REF. Resistors R10

and R11 are set to equal the impedance of the resistors R8 and R9

for a matched ac response and for balancing the effects of the

bias current.

R1

R2

100kΩ

10kΩ

Figure 65. A Resistance/Capacitance Sensor

ADAPTIVE SINGLE-ENDED-TO-DIFFERENTIAL

SIGNAL CONVERTER

The Challenge

When designing a signal path in systems that have a single voltage

supply, the biggest challenge is how to represent the full range of

an input signal that may have positive, zero, and negative values.

By including zero in the output, the output signal must go

completely to ground, which single-supply amplifiers cannot do.

Converting the single-ended input signal to a differential signal

(through a single-ended-to-differential signal converter circuit)

allows zero to be represented as the positive and negative outputs

being equal, requiring neither amplifier to go to ground.

The input frequency can range from 10 Hz to 1 MHz. Peak-to-peak

amplitude of the input signal can be as large as V_SY− 100 mV.

The dc common mode (V_CM) of the input signal can be as high

as +1.5 × V_SYand −0.5 × V_SY; therefore, a system with a +5 V supply

voltage can take a common mode from as high as +7.5 V and as

low as −2.5 V with a signal amplitude of 5 V p-p. The wide range of

There are other benefits of the single-ended-to-differential signal

conversion, such as doubling the amplitude of the signal for

better signal-to-noise ratio, rejecting common-mode noise, and

driving the input of a high precision differential ADC.

V

_CMabove and below ground, along with a signal amplitude as

large as the supply, eliminates the need to reduce the amplitude

of the input signal and sacrifice SNR. When measuring both the

ac and the dc parts of the signal, a capacitor cannot be in the signal

path. Figure 66 shows examples of the voltage ranges of the single-

ended-to-differential signal converter circuit.

In addition to converting to a differential signal, the circuit must set

the common-mode dc level of its output to a level that gives the ac

signal maximum swing at the load (like the input to an ADC).

Rev. A | Page 22 of 24

Data Sheet

ADA4500-2

Besides converting the ac signal from single-ended to differential,

this circuit separates the ac and dc part of the input signal and

automatically adjusts the common-mode dc level of the output

signal to the same voltage as V_REF. The output signal is then a

differential version of the input signal with its common-mode

voltage set to an optimal value (such as, ½ the full-scale input

range to the ADC). The noninverted ac part of the signal is

output at OUTP, and the inverted ac signal is output at OUTN.

The differential output signal (OUTP to OUTN) is centered on

the voltage applied to REF. In this design, R3 and R4 set REF to

½V_POSfor maximum signal peak-to-peak swing; however, these

resistors can be eliminated, and the REF input can be driven

from an external source, such as a reference or the output of a

digital-to-analog converter (DAC).

The dc common-mode part of the input signal (V_DC) was measured

using the voltage applied at REF and the voltage measured at the

feedback (FB) output using Equation 2. With V_CMof the input

signal known to the system, it can respond appropriately to, for

example, a situation when the common mode is getting too close to

the rails.

V_DC= (2 × FB) − (REF)

(2)

C2

10pF

R11

5kΩ

R2

2kΩ

V

SY

V

R1A

1kΩ

R1B

1kΩ

SY

R10

5kΩ

OUTN

OUTP

INPUT

U2A

R9

C1

100pF

ADA4500-2

5kΩ

U1A

ADA4500-2

R8

5kΩ

V

SY

C7

1µF

C6

1µF

U2B

R5

10kΩ

V

R6

10kΩ

SY

R4

100kΩ

REF

FB

U1B

C5

0.01µF

C3

1µF

R3

100kΩ

INPUT

OUTPUT

OUTP

V

REF

CM

V

PP

OUTN

V

= 1.5 × V

SY

CM_MAX

CM_MIN

PP_MAX

= –0.5 × V

SY

= V – 0.1V

SY

EXAMPLES (V = 5V)

SY

+10V

+7.5V

+5V

OUTP

+5V

OR

V

PP

+2.5V

0V

–2.5V

–5V

OUTN

Figure 66. Single-Ended-to-Differential Conversion Circuit Separates the AC and DC Part of the Signal

Rev. A | Page 23 of 24

ADA4500-2

Data Sheet

OUTLINE DIMENSIONS

3.10

3.00 SQ

2.90

0.50 BSC

8

5

PIN 1 INDEX

EXPOSED

PAD

1.70

1.60 SQ

1.50

AREA

0.50

0.40

0.30

4

1

PIN 1

INDICATOR

(R 0.15)

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.25

0.20

0.203 REF

COMPLIANT TO JEDEC STANDARDS MO-229-WEED

Figure 67. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very, Very Thin, Dual Lead

(CP-8-12)

Dimensions shown in millimeters

3.20

3.00

2.80

8

1

5

4

5.15

4.90

4.65

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.65 BSC

0.95

0.85

0.75

15° MAX

1.10 MAX

0.80

0.55

0.40

0.15

0.05

0.23

0.09

6°

0°

0.40

0.25

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 68. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature

Package Description

Package Option

Branding

A2Z

ADA4500-2ACPZ-R7

ADA4500-2ACPZ-RL

ADA4500-2ARMZ

ADA4500-2ARMZ-R7

ADA4500-2ARMZ-RL

−40°C to +125°C

8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

8-Lead Mini Small Outline Package [MSOP]

CP-8-12

RM-8

A2Z

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D10617-0-10/12(A)

Rev. A | Page 24 of 24


型号：	ADA4500-2ARMZ
厂家：	ADI
描述：	10 MHz, 14.5 nV/âHz, Rail-to-Rail I/O, Zero Input Crossover Distortion Amplifier 10兆赫， 14.5纳伏/ A ????赫兹，轨至轨I / O，零输入交越失真放大器放大器
文件：	总25页 (文件大小：1122K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADA4500-2ARMZ [ADI]

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